2022-03-10 14:03:50 +08:00
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.metals/
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.vscode/
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# design/project/target/
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# design/project/project/
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design/project/
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2022-03-10 11:56:21 +08:00
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design/.idea/
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2022-03-27 01:51:42 +08:00
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design/target/
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2022-03-10 11:56:21 +08:00
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2022-03-10 14:03:50 +08:00
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generated_rtl/*.sv
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verif/sim/*.log
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verif/sim/*.s
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verif/sim/*.hex
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verif/sim/*.dis
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verif/sim/*.tbl
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verif/sim/vcs*
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verif/sim/simv*
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verif/sim/quasar*
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verif/sim/*.exe
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verif/sim/obj*
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verif/sim/*.o
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verif/sim/ucli.key
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verif/sim/vc_hdrs.h
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verif/sim/csrc
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verif/sim/*.csv
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verif/sim/work
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verif/sim/*.dump
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verif/sim/*.fsdb
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FM_WORK
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tracer_logs/*.log
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verif/LEC/formality_work/formality_log/*.log
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verif/LEC/*.fss
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design/snapshots/
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2022-03-10 11:56:21 +08:00
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design/src/main/scala/lib/param.scala
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2022-03-10 14:03:50 +08:00
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design/*.v
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design/*.sv
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design/*.f
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design/*.json
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design/*.fir
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2022-03-10 11:56:21 +08:00
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# soc/
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# demo/
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