quasar/demo/synth.sh

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#!/bin/bash
set -ex
PWD=$(pwd)
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SOC=$PWD/../soc/
SOCFILE=../soc/soc_top.mk
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DEFINE_DIR=$PWD/../design/snapshots/default
DEFINE="${DEFINE_DIR}/pd_defines.vh"
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mkdir -p gen
rm -rf gen/*
mkdir gen/design
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YOSYS_COARSE=true
YOSYS_GLOBRST=false
YOSYS_SPLITNETS=false
TOP="soc_top"
RTL_FILES="$DEFINE $(cat $SOCFILE | sed 's/[[:space:]]//g' | sed '/^$/d' | sed -e "s!^!$SOC!" | tr '\n' ' ')"
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sv2v -I${DEFINE_DIR} $RTL_FILES > gen/soc_top.v
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{
echo "read_verilog gen/soc_top.v"
if test -n "$TOP"; then
echo "hierarchy -check -top $TOP"
else
echo "hierarchy -check"
fi
if $YOSYS_GLOBRST; then
# insertation of global reset (e.g. for FPGA cores)
echo "add -global_input globrst 1"
echo "proc -global_arst globrst"
fi
echo "synth -run coarse; opt -fine"
# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
if ! $YOSYS_COARSE; then
echo "memory_map; techmap; opt; abc -dff; clean"
fi
if $YOSYS_SPLITNETS; then
# icarus verilog has a performance problems when there are
# dependencies between the bits of a long vector
echo "splitnets; clean"
fi
if $YOSYS_COARSE; then
echo "write_verilog -noexpr -noattr gen/synth.v"
else
echo "select -assert-none t:\$[!_]"
echo "write_verilog -noattr gen/synth.v"
fi
echo "synth_ecp5 -top $TOP -json gen/soc.json"
# echo "synth_xilinx -top $TOP"
} > gen/synth.ys
yosys -v2 -l gen/synth.log gen/synth.ys
nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 1 --json gen/soc.json