21 lines
876 B
Scala
21 lines
876 B
Scala
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package dec
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import chisel3.util._
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import chisel3._
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import include.el2_trigger_pkt_t
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import lib._
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class el2_dec_trigger extends Module with el2_lib {
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val io = IO(new Bundle {
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val trigger_pkt_any = Input(Vec(4, new el2_trigger_pkt_t))
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val dec_i0_pc_d = Input(UInt(31.W))
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val dec_i0_trigger_match_d = Output(UInt(4.W))
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})
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val dec_i0_match_data = VecInit.tabulate(4)(i => repl(32, (!io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).execute)) & Cat(io.dec_i0_pc_d, io.trigger_pkt_any(i).tdata2(0)))
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io.dec_i0_trigger_match_d := (0 until 4).map(j =>io.trigger_pkt_any(j).execute & io.trigger_pkt_any(j).m & rvmaskandmatch(io.trigger_pkt_any(j).tdata2, dec_i0_match_data(j), io.trigger_pkt_any(j).match_.asBool())).reverse.reduce(Cat(_,_))
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}
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object dec_trig extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_trigger())))
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}
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