colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
quasar/exu_div_new_2bit_fullshortq...

2176 lines
128 KiB
Plaintext
Raw Normal View History

2 bit divider
2021-01-06 12:32:46 +08:00
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit exu_div_new_2bit_fullshortq :
module exu_div_cls :
input clock : Clock
input reset : Reset
output io : {flip operand : UInt<33>, cls : UInt<5>}
wire cls_zeros : UInt<5>
cls_zeros <= UInt<5>("h00")
wire cls_ones : UInt<5>
cls_ones <= UInt<5>("h00")
node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 655:54]
node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 655:54]
node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 655:54]
node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 655:54]
node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 655:54]
node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 655:54]
node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 655:54]
node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 655:54]
node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 655:54]
node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 655:54]
node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 655:54]
node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 655:54]
node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 655:54]
node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 655:54]
node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 655:54]
node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 655:54]
node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 655:54]
node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 655:54]
node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 655:54]
node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 655:54]
node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 655:54]
node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 655:54]
node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 655:54]
node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 655:54]
node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 655:54]
node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 655:54]
node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 655:54]
node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 655:54]
node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 655:54]
node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 655:54]
node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 655:54]
node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 655:54]
node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_67 = mux(_T_7, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_68 = mux(_T_9, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_69 = mux(_T_11, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_70 = mux(_T_13, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_71 = mux(_T_15, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_72 = mux(_T_17, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_73 = mux(_T_19, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_74 = mux(_T_21, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_75 = mux(_T_23, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_76 = mux(_T_25, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_77 = mux(_T_27, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_78 = mux(_T_29, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_79 = mux(_T_31, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_80 = mux(_T_33, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_81 = mux(_T_35, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_82 = mux(_T_37, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_83 = mux(_T_39, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_84 = mux(_T_41, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_85 = mux(_T_43, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_86 = mux(_T_45, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_87 = mux(_T_47, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_88 = mux(_T_49, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_89 = mux(_T_51, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_90 = mux(_T_53, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_91 = mux(_T_55, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_92 = mux(_T_57, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_93 = mux(_T_59, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_94 = mux(_T_61, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_95 = mux(_T_63, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_96 = or(_T_64, _T_65) @[Mux.scala 27:72]
node _T_97 = or(_T_96, _T_66) @[Mux.scala 27:72]
node _T_98 = or(_T_97, _T_67) @[Mux.scala 27:72]
node _T_99 = or(_T_98, _T_68) @[Mux.scala 27:72]
node _T_100 = or(_T_99, _T_69) @[Mux.scala 27:72]
node _T_101 = or(_T_100, _T_70) @[Mux.scala 27:72]
node _T_102 = or(_T_101, _T_71) @[Mux.scala 27:72]
node _T_103 = or(_T_102, _T_72) @[Mux.scala 27:72]
node _T_104 = or(_T_103, _T_73) @[Mux.scala 27:72]
node _T_105 = or(_T_104, _T_74) @[Mux.scala 27:72]
node _T_106 = or(_T_105, _T_75) @[Mux.scala 27:72]
node _T_107 = or(_T_106, _T_76) @[Mux.scala 27:72]
node _T_108 = or(_T_107, _T_77) @[Mux.scala 27:72]
node _T_109 = or(_T_108, _T_78) @[Mux.scala 27:72]
node _T_110 = or(_T_109, _T_79) @[Mux.scala 27:72]
node _T_111 = or(_T_110, _T_80) @[Mux.scala 27:72]
node _T_112 = or(_T_111, _T_81) @[Mux.scala 27:72]
node _T_113 = or(_T_112, _T_82) @[Mux.scala 27:72]
node _T_114 = or(_T_113, _T_83) @[Mux.scala 27:72]
node _T_115 = or(_T_114, _T_84) @[Mux.scala 27:72]
node _T_116 = or(_T_115, _T_85) @[Mux.scala 27:72]
node _T_117 = or(_T_116, _T_86) @[Mux.scala 27:72]
node _T_118 = or(_T_117, _T_87) @[Mux.scala 27:72]
node _T_119 = or(_T_118, _T_88) @[Mux.scala 27:72]
node _T_120 = or(_T_119, _T_89) @[Mux.scala 27:72]
node _T_121 = or(_T_120, _T_90) @[Mux.scala 27:72]
node _T_122 = or(_T_121, _T_91) @[Mux.scala 27:72]
node _T_123 = or(_T_122, _T_92) @[Mux.scala 27:72]
node _T_124 = or(_T_123, _T_93) @[Mux.scala 27:72]
node _T_125 = or(_T_124, _T_94) @[Mux.scala 27:72]
node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72]
wire _T_127 : UInt<5> @[Mux.scala 27:72]
_T_127 <= _T_126 @[Mux.scala 27:72]
cls_zeros <= _T_127 @[exu_div_ctl.scala 655:13]
node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 657:18]
node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 657:25]
when _T_129 : @[exu_div_ctl.scala 657:44]
cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 657:55]
skip @[exu_div_ctl.scala 657:44]
else : @[exu_div_ctl.scala 658:15]
node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 658:66]
node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 658:76]
node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 658:66]
node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 658:76]
node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 658:66]
node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 658:76]
node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 658:66]
node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 658:76]
node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 658:66]
node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 658:76]
node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 658:66]
node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 658:76]
node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 658:66]
node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 658:76]
node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 658:66]
node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 658:76]
node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 658:66]
node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 658:76]
node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 658:66]
node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12]
node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 658:76]
node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 658:66]
node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12]
node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 658:76]
node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 658:66]
node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 658:76]
node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 658:66]
node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 658:76]
node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 658:66]
node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12]
node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 658:76]
node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 658:66]
node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12]
node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 658:76]
node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 658:66]
node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 658:76]
node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 658:66]
node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 658:76]
node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 658:66]
node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12]
node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 658:76]
node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 658:66]
node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 658:76]
node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 658:66]
node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 658:76]
node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 658:66]
node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12]
node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 658:76]
node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 658:66]
node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12]
node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 658:76]
node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 658:66]
node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12]
node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 658:76]
node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 658:66]
node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 658:76]
node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 658:66]
node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12]
node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 658:76]
node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 658:66]
node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 658:76]
node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 658:66]
node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12]
node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 658:76]
node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 658:66]
node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 658:76]
node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 658:66]
node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 658:76]
node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 658:66]
node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 658:76]
node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 658:66]
node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 658:76]
node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_287 = mux(_T_148, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_288 = mux(_T_153, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_289 = mux(_T_158, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_290 = mux(_T_163, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_291 = mux(_T_168, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_292 = mux(_T_173, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_293 = mux(_T_178, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_294 = mux(_T_183, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_295 = mux(_T_188, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_296 = mux(_T_193, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_297 = mux(_T_198, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_298 = mux(_T_203, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_299 = mux(_T_208, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_300 = mux(_T_213, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_301 = mux(_T_218, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_302 = mux(_T_223, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_303 = mux(_T_228, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_304 = mux(_T_233, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_305 = mux(_T_238, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_306 = mux(_T_243, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_307 = mux(_T_248, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_308 = mux(_T_253, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_309 = mux(_T_258, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_310 = mux(_T_263, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_311 = mux(_T_268, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_312 = mux(_T_273, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_313 = mux(_T_278, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_314 = mux(_T_283, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_315 = or(_T_284, _T_285) @[Mux.scala 27:72]
node _T_316 = or(_T_315, _T_286) @[Mux.scala 27:72]
node _T_317 = or(_T_316, _T_287) @[Mux.scala 27:72]
node _T_318 = or(_T_317, _T_288) @[Mux.scala 27:72]
node _T_319 = or(_T_318, _T_289) @[Mux.scala 27:72]
node _T_320 = or(_T_319, _T_290) @[Mux.scala 27:72]
node _T_321 = or(_T_320, _T_291) @[Mux.scala 27:72]
node _T_322 = or(_T_321, _T_292) @[Mux.scala 27:72]
node _T_323 = or(_T_322, _T_293) @[Mux.scala 27:72]
node _T_324 = or(_T_323, _T_294) @[Mux.scala 27:72]
node _T_325 = or(_T_324, _T_295) @[Mux.scala 27:72]
node _T_326 = or(_T_325, _T_296) @[Mux.scala 27:72]
node _T_327 = or(_T_326, _T_297) @[Mux.scala 27:72]
node _T_328 = or(_T_327, _T_298) @[Mux.scala 27:72]
node _T_329 = or(_T_328, _T_299) @[Mux.scala 27:72]
node _T_330 = or(_T_329, _T_300) @[Mux.scala 27:72]
node _T_331 = or(_T_330, _T_301) @[Mux.scala 27:72]
node _T_332 = or(_T_331, _T_302) @[Mux.scala 27:72]
node _T_333 = or(_T_332, _T_303) @[Mux.scala 27:72]
node _T_334 = or(_T_333, _T_304) @[Mux.scala 27:72]
node _T_335 = or(_T_334, _T_305) @[Mux.scala 27:72]
node _T_336 = or(_T_335, _T_306) @[Mux.scala 27:72]
node _T_337 = or(_T_336, _T_307) @[Mux.scala 27:72]
node _T_338 = or(_T_337, _T_308) @[Mux.scala 27:72]
node _T_339 = or(_T_338, _T_309) @[Mux.scala 27:72]
node _T_340 = or(_T_339, _T_310) @[Mux.scala 27:72]
node _T_341 = or(_T_340, _T_311) @[Mux.scala 27:72]
node _T_342 = or(_T_341, _T_312) @[Mux.scala 27:72]
node _T_343 = or(_T_342, _T_313) @[Mux.scala 27:72]
node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72]
wire _T_345 : UInt<5> @[Mux.scala 27:72]
_T_345 <= _T_344 @[Mux.scala 27:72]
cls_ones <= _T_345 @[exu_div_ctl.scala 658:25]
skip @[exu_div_ctl.scala 658:15]
node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 659:27]
node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 659:16]
io.cls <= _T_347 @[exu_div_ctl.scala 659:10]
module exu_div_cls_1 :
input clock : Clock
input reset : Reset
output io : {flip operand : UInt<33>, cls : UInt<5>}
wire cls_zeros : UInt<5>
cls_zeros <= UInt<5>("h00")
wire cls_ones : UInt<5>
cls_ones <= UInt<5>("h00")
node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 655:54]
node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 655:54]
node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 655:54]
node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 655:54]
node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 655:54]
node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 655:54]
node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 655:54]
node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 655:54]
node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 655:54]
node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 655:54]
node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 655:54]
node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 655:54]
node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 655:54]
node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 655:54]
node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 655:54]
node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 655:54]
node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 655:54]
node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 655:54]
node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 655:54]
node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 655:54]
node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 655:54]
node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 655:54]
node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 655:54]
node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 655:54]
node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 655:54]
node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 655:54]
node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 655:54]
node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 655:54]
node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 655:54]
node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 655:54]
node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 655:54]
node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 655:54]
node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_67 = mux(_T_7, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_68 = mux(_T_9, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_69 = mux(_T_11, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_70 = mux(_T_13, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_71 = mux(_T_15, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_72 = mux(_T_17, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_73 = mux(_T_19, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_74 = mux(_T_21, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_75 = mux(_T_23, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_76 = mux(_T_25, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_77 = mux(_T_27, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_78 = mux(_T_29, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_79 = mux(_T_31, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_80 = mux(_T_33, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_81 = mux(_T_35, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_82 = mux(_T_37, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_83 = mux(_T_39, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_84 = mux(_T_41, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_85 = mux(_T_43, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_86 = mux(_T_45, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_87 = mux(_T_47, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_88 = mux(_T_49, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_89 = mux(_T_51, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_90 = mux(_T_53, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_91 = mux(_T_55, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_92 = mux(_T_57, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_93 = mux(_T_59, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_94 = mux(_T_61, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_95 = mux(_T_63, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_96 = or(_T_64, _T_65) @[Mux.scala 27:72]
node _T_97 = or(_T_96, _T_66) @[Mux.scala 27:72]
node _T_98 = or(_T_97, _T_67) @[Mux.scala 27:72]
node _T_99 = or(_T_98, _T_68) @[Mux.scala 27:72]
node _T_100 = or(_T_99, _T_69) @[Mux.scala 27:72]
node _T_101 = or(_T_100, _T_70) @[Mux.scala 27:72]
node _T_102 = or(_T_101, _T_71) @[Mux.scala 27:72]
node _T_103 = or(_T_102, _T_72) @[Mux.scala 27:72]
node _T_104 = or(_T_103, _T_73) @[Mux.scala 27:72]
node _T_105 = or(_T_104, _T_74) @[Mux.scala 27:72]
node _T_106 = or(_T_105, _T_75) @[Mux.scala 27:72]
node _T_107 = or(_T_106, _T_76) @[Mux.scala 27:72]
node _T_108 = or(_T_107, _T_77) @[Mux.scala 27:72]
node _T_109 = or(_T_108, _T_78) @[Mux.scala 27:72]
node _T_110 = or(_T_109, _T_79) @[Mux.scala 27:72]
node _T_111 = or(_T_110, _T_80) @[Mux.scala 27:72]
node _T_112 = or(_T_111, _T_81) @[Mux.scala 27:72]
node _T_113 = or(_T_112, _T_82) @[Mux.scala 27:72]
node _T_114 = or(_T_113, _T_83) @[Mux.scala 27:72]
node _T_115 = or(_T_114, _T_84) @[Mux.scala 27:72]
node _T_116 = or(_T_115, _T_85) @[Mux.scala 27:72]
node _T_117 = or(_T_116, _T_86) @[Mux.scala 27:72]
node _T_118 = or(_T_117, _T_87) @[Mux.scala 27:72]
node _T_119 = or(_T_118, _T_88) @[Mux.scala 27:72]
node _T_120 = or(_T_119, _T_89) @[Mux.scala 27:72]
node _T_121 = or(_T_120, _T_90) @[Mux.scala 27:72]
node _T_122 = or(_T_121, _T_91) @[Mux.scala 27:72]
node _T_123 = or(_T_122, _T_92) @[Mux.scala 27:72]
node _T_124 = or(_T_123, _T_93) @[Mux.scala 27:72]
node _T_125 = or(_T_124, _T_94) @[Mux.scala 27:72]
node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72]
wire _T_127 : UInt<5> @[Mux.scala 27:72]
_T_127 <= _T_126 @[Mux.scala 27:72]
cls_zeros <= _T_127 @[exu_div_ctl.scala 655:13]
node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 657:18]
node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 657:25]
when _T_129 : @[exu_div_ctl.scala 657:44]
cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 657:55]
skip @[exu_div_ctl.scala 657:44]
else : @[exu_div_ctl.scala 658:15]
node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 658:66]
node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 658:76]
node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 658:66]
node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 658:76]
node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 658:66]
node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 658:76]
node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 658:66]
node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 658:76]
node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 658:66]
node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 658:76]
node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 658:66]
node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 658:76]
node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 658:66]
node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 658:76]
node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 658:66]
node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 658:76]
node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 658:66]
node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 658:76]
node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 658:66]
node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12]
node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 658:76]
node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 658:66]
node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12]
node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 658:76]
node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 658:66]
node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 658:76]
node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 658:66]
node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 658:76]
node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 658:66]
node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12]
node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 658:76]
node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 658:66]
node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12]
node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 658:76]
node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 658:66]
node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 658:76]
node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 658:66]
node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 658:76]
node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 658:66]
node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12]
node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 658:76]
node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 658:66]
node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 658:76]
node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 658:66]
node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 658:76]
node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 658:66]
node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12]
node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 658:76]
node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 658:66]
node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12]
node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 658:76]
node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 658:66]
node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12]
node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 658:76]
node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 658:66]
node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 658:76]
node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 658:66]
node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12]
node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 658:76]
node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 658:66]
node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 658:76]
node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 658:66]
node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12]
node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 658:76]
node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 658:66]
node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 658:76]
node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 658:66]
node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 658:76]
node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 658:66]
node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 658:76]
node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 658:66]
node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 658:76]
node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_287 = mux(_T_148, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_288 = mux(_T_153, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_289 = mux(_T_158, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_290 = mux(_T_163, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_291 = mux(_T_168, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_292 = mux(_T_173, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_293 = mux(_T_178, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_294 = mux(_T_183, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_295 = mux(_T_188, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_296 = mux(_T_193, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_297 = mux(_T_198, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_298 = mux(_T_203, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_299 = mux(_T_208, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_300 = mux(_T_213, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_301 = mux(_T_218, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_302 = mux(_T_223, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_303 = mux(_T_228, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_304 = mux(_T_233, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_305 = mux(_T_238, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_306 = mux(_T_243, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_307 = mux(_T_248, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_308 = mux(_T_253, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_309 = mux(_T_258, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_310 = mux(_T_263, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_311 = mux(_T_268, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_312 = mux(_T_273, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_313 = mux(_T_278, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_314 = mux(_T_283, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_315 = or(_T_284, _T_285) @[Mux.scala 27:72]
node _T_316 = or(_T_315, _T_286) @[Mux.scala 27:72]
node _T_317 = or(_T_316, _T_287) @[Mux.scala 27:72]
node _T_318 = or(_T_317, _T_288) @[Mux.scala 27:72]
node _T_319 = or(_T_318, _T_289) @[Mux.scala 27:72]
node _T_320 = or(_T_319, _T_290) @[Mux.scala 27:72]
node _T_321 = or(_T_320, _T_291) @[Mux.scala 27:72]
node _T_322 = or(_T_321, _T_292) @[Mux.scala 27:72]
node _T_323 = or(_T_322, _T_293) @[Mux.scala 27:72]
node _T_324 = or(_T_323, _T_294) @[Mux.scala 27:72]
node _T_325 = or(_T_324, _T_295) @[Mux.scala 27:72]
node _T_326 = or(_T_325, _T_296) @[Mux.scala 27:72]
node _T_327 = or(_T_326, _T_297) @[Mux.scala 27:72]
node _T_328 = or(_T_327, _T_298) @[Mux.scala 27:72]
node _T_329 = or(_T_328, _T_299) @[Mux.scala 27:72]
node _T_330 = or(_T_329, _T_300) @[Mux.scala 27:72]
node _T_331 = or(_T_330, _T_301) @[Mux.scala 27:72]
node _T_332 = or(_T_331, _T_302) @[Mux.scala 27:72]
node _T_333 = or(_T_332, _T_303) @[Mux.scala 27:72]
node _T_334 = or(_T_333, _T_304) @[Mux.scala 27:72]
node _T_335 = or(_T_334, _T_305) @[Mux.scala 27:72]
node _T_336 = or(_T_335, _T_306) @[Mux.scala 27:72]
node _T_337 = or(_T_336, _T_307) @[Mux.scala 27:72]
node _T_338 = or(_T_337, _T_308) @[Mux.scala 27:72]
node _T_339 = or(_T_338, _T_309) @[Mux.scala 27:72]
node _T_340 = or(_T_339, _T_310) @[Mux.scala 27:72]
node _T_341 = or(_T_340, _T_311) @[Mux.scala 27:72]
node _T_342 = or(_T_341, _T_312) @[Mux.scala 27:72]
node _T_343 = or(_T_342, _T_313) @[Mux.scala 27:72]
node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72]
wire _T_345 : UInt<5> @[Mux.scala 27:72]
_T_345 <= _T_344 @[Mux.scala 27:72]
cls_ones <= _T_345 @[exu_div_ctl.scala 658:25]
skip @[exu_div_ctl.scala 658:15]
node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 659:27]
node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 659:16]
io.cls <= _T_347 @[exu_div_ctl.scala 659:10]
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_4 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_5 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_5 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_6 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_7 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_8 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_8 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_9 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_9 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_10 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_10 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_10 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
module exu_div_new_2bit_fullshortq :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip cancel : UInt<1>, flip valid_in : UInt<1>, flip signed_in : UInt<1>, flip rem_in : UInt<1>, flip dividend_in : UInt<32>, flip divisor_in : UInt<32>, data_out : UInt<32>, valid_out : UInt<1>}
wire valid_ff : UInt<1>
valid_ff <= UInt<1>("h00")
wire finish_ff : UInt<1>
finish_ff <= UInt<1>("h00")
wire control_ff : UInt<3>
control_ff <= UInt<3>("h00")
wire count_ff : UInt<7>
count_ff <= UInt<7>("h00")
wire smallnum : UInt<4>
smallnum <= UInt<4>("h00")
wire smallnum_case : UInt<1>
smallnum_case <= UInt<1>("h00")
wire a_ff : UInt<32>
a_ff <= UInt<32>("h00")
wire b_ff1 : UInt<33>
b_ff1 <= UInt<33>("h00")
wire b_ff : UInt<35>
b_ff <= UInt<35>("h00")
wire q_ff : UInt<32>
q_ff <= UInt<32>("h00")
wire r_ff : UInt<32>
r_ff <= UInt<32>("h00")
quotient new changed
2021-01-06 13:05:37 +08:00
wire quotient_raw : UInt<4>
quotient_raw <= UInt<4>("h00")
2 bit divider
2021-01-06 12:32:46 +08:00
wire quotient_new : UInt<2>
quotient_new <= UInt<2>("h00")
wire shortq_enable : UInt<1>
shortq_enable <= UInt<1>("h00")
wire shortq_enable_ff : UInt<1>
shortq_enable_ff <= UInt<1>("h00")
wire by_zero_case_ff : UInt<1>
by_zero_case_ff <= UInt<1>("h00")
wire ar_shifted : UInt<64>
ar_shifted <= UInt<64>("h00")
wire shortq_shift_ff : UInt<4>
shortq_shift_ff <= UInt<4>("h00")
node _T = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 488:35]
node valid_ff_in = and(io.valid_in, _T) @[exu_div_ctl.scala 488:33]
node _T_1 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 489:35]
node _T_2 = bits(control_ff, 2, 2) @[exu_div_ctl.scala 489:60]
node _T_3 = and(_T_1, _T_2) @[exu_div_ctl.scala 489:48]
node _T_4 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 489:80]
node _T_5 = bits(io.dividend_in, 31, 31) @[exu_div_ctl.scala 489:112]
node _T_6 = and(_T_4, _T_5) @[exu_div_ctl.scala 489:96]
node _T_7 = or(_T_3, _T_6) @[exu_div_ctl.scala 489:65]
node _T_8 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 489:120]
node _T_9 = bits(control_ff, 1, 1) @[exu_div_ctl.scala 489:145]
node _T_10 = and(_T_8, _T_9) @[exu_div_ctl.scala 489:133]
node _T_11 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 489:165]
node _T_12 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 489:197]
node _T_13 = and(_T_11, _T_12) @[exu_div_ctl.scala 489:181]
node _T_14 = or(_T_10, _T_13) @[exu_div_ctl.scala 489:150]
node _T_15 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 489:205]
node _T_16 = bits(control_ff, 0, 0) @[exu_div_ctl.scala 489:230]
node _T_17 = and(_T_15, _T_16) @[exu_div_ctl.scala 489:218]
node _T_18 = and(io.valid_in, io.rem_in) @[exu_div_ctl.scala 489:250]
node _T_19 = or(_T_17, _T_18) @[exu_div_ctl.scala 489:235]
node _T_20 = cat(_T_7, _T_14) @[Cat.scala 29:58]
node control_in = cat(_T_20, _T_19) @[Cat.scala 29:58]
node dividend_sign_ff = bits(control_ff, 2, 2) @[exu_div_ctl.scala 490:40]
node divisor_sign_ff = bits(control_ff, 1, 1) @[exu_div_ctl.scala 491:40]
node rem_ff = bits(control_ff, 0, 0) @[exu_div_ctl.scala 492:40]
node _T_21 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 493:47]
node _T_22 = eq(_T_21, UInt<1>("h00")) @[exu_div_ctl.scala 493:54]
node by_zero_case = and(valid_ff, _T_22) @[exu_div_ctl.scala 493:40]
node _T_23 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 496:11]
node _T_24 = eq(_T_23, UInt<1>("h00")) @[exu_div_ctl.scala 496:18]
node _T_25 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 496:29]
node _T_26 = and(_T_24, _T_25) @[exu_div_ctl.scala 496:27]
node _T_27 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 496:45]
node _T_28 = and(_T_26, _T_27) @[exu_div_ctl.scala 496:43]
node _T_29 = and(_T_28, valid_ff) @[exu_div_ctl.scala 496:53]
node _T_30 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 496:66]
node _T_31 = and(_T_29, _T_30) @[exu_div_ctl.scala 496:64]
node _T_32 = orr(count_ff) @[exu_div_ctl.scala 497:42]
node running_state = or(_T_32, shortq_enable_ff) @[exu_div_ctl.scala 497:45]
node _T_33 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 498:43]
node _T_34 = or(_T_33, io.cancel) @[exu_div_ctl.scala 498:54]
node _T_35 = or(_T_34, running_state) @[exu_div_ctl.scala 498:66]
node misc_enable = or(_T_35, finish_ff) @[exu_div_ctl.scala 498:82]
node _T_36 = or(smallnum_case, by_zero_case) @[exu_div_ctl.scala 499:45]
node _T_37 = eq(count_ff, UInt<6>("h020")) @[exu_div_ctl.scala 499:72]
node finish_raw = or(_T_36, _T_37) @[exu_div_ctl.scala 499:60]
node _T_38 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 500:43]
node finish = and(finish_raw, _T_38) @[exu_div_ctl.scala 500:41]
node _T_39 = or(valid_ff, running_state) @[exu_div_ctl.scala 501:40]
node _T_40 = eq(finish, UInt<1>("h00")) @[exu_div_ctl.scala 501:59]
node _T_41 = and(_T_39, _T_40) @[exu_div_ctl.scala 501:57]
node _T_42 = eq(finish_ff, UInt<1>("h00")) @[exu_div_ctl.scala 501:69]
node _T_43 = and(_T_41, _T_42) @[exu_div_ctl.scala 501:67]
node _T_44 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 501:82]
node _T_45 = and(_T_43, _T_44) @[exu_div_ctl.scala 501:80]
node _T_46 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 501:95]
node count_enable = and(_T_45, _T_46) @[exu_div_ctl.scala 501:93]
node _T_47 = bits(count_enable, 0, 0) @[Bitwise.scala 72:15]
node _T_48 = mux(_T_47, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
node _T_49 = cat(UInt<5>("h00"), UInt<2>("h02")) @[Cat.scala 29:58]
node _T_50 = add(count_ff, _T_49) @[exu_div_ctl.scala 502:63]
node _T_51 = tail(_T_50, 1) @[exu_div_ctl.scala 502:63]
node _T_52 = cat(UInt<2>("h00"), shortq_shift_ff) @[Cat.scala 29:58]
node _T_53 = cat(_T_52, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_54 = add(_T_51, _T_53) @[exu_div_ctl.scala 502:83]
node _T_55 = tail(_T_54, 1) @[exu_div_ctl.scala 502:83]
node count_in = and(_T_48, _T_55) @[exu_div_ctl.scala 502:51]
node a_enable = or(io.valid_in, running_state) @[exu_div_ctl.scala 503:43]
node _T_56 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 504:47]
node a_shift = and(running_state, _T_56) @[exu_div_ctl.scala 504:45]
node _T_57 = bits(dividend_sign_ff, 0, 0) @[Bitwise.scala 72:15]
node _T_58 = mux(_T_57, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_59 = cat(_T_58, a_ff) @[Cat.scala 29:58]
node _T_60 = cat(shortq_shift_ff, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_61 = dshl(_T_59, _T_60) @[exu_div_ctl.scala 505:68]
ar_shifted <= _T_61 @[exu_div_ctl.scala 505:28]
node _T_62 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 506:61]
node _T_63 = eq(_T_62, UInt<1>("h00")) @[exu_div_ctl.scala 506:42]
node b_twos_comp = and(valid_ff, _T_63) @[exu_div_ctl.scala 506:40]
node _T_64 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 507:62]
node _T_65 = eq(_T_64, UInt<1>("h00")) @[exu_div_ctl.scala 507:43]
node twos_comp_b_sel = and(valid_ff, _T_65) @[exu_div_ctl.scala 507:41]
node _T_66 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 508:30]
node _T_67 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 508:42]
node _T_68 = and(_T_66, _T_67) @[exu_div_ctl.scala 508:40]
node _T_69 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 508:71]
node _T_70 = and(_T_68, _T_69) @[exu_div_ctl.scala 508:50]
node _T_71 = eq(by_zero_case_ff, UInt<1>("h00")) @[exu_div_ctl.scala 508:92]
node twos_comp_q_sel = and(_T_70, _T_71) @[exu_div_ctl.scala 508:90]
node b_enable = or(io.valid_in, b_twos_comp) @[exu_div_ctl.scala 509:43]
node _T_72 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 510:43]
node rq_enable = or(_T_72, running_state) @[exu_div_ctl.scala 510:54]
node _T_73 = and(valid_ff, dividend_sign_ff) @[exu_div_ctl.scala 511:40]
node _T_74 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 511:61]
node r_sign_sel = and(_T_73, _T_74) @[exu_div_ctl.scala 511:59]
node _T_75 = eq(quotient_new, UInt<1>("h00")) @[exu_div_ctl.scala 512:61]
node _T_76 = and(running_state, _T_75) @[exu_div_ctl.scala 512:45]
node _T_77 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 512:72]
node r_restore_sel = and(_T_76, _T_77) @[exu_div_ctl.scala 512:70]
node _T_78 = eq(quotient_new, UInt<1>("h01")) @[exu_div_ctl.scala 513:61]
node _T_79 = and(running_state, _T_78) @[exu_div_ctl.scala 513:45]
node _T_80 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 513:72]
node r_adder1_sel = and(_T_79, _T_80) @[exu_div_ctl.scala 513:70]
node _T_81 = eq(quotient_new, UInt<2>("h02")) @[exu_div_ctl.scala 514:61]
node _T_82 = and(running_state, _T_81) @[exu_div_ctl.scala 514:45]
node _T_83 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 514:72]
node r_adder2_sel = and(_T_82, _T_83) @[exu_div_ctl.scala 514:70]
node _T_84 = eq(quotient_new, UInt<2>("h03")) @[exu_div_ctl.scala 515:61]
node _T_85 = and(running_state, _T_84) @[exu_div_ctl.scala 515:45]
node _T_86 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 515:72]
node r_adder3_sel = and(_T_85, _T_86) @[exu_div_ctl.scala 515:70]
node _T_87 = bits(r_ff, 30, 0) @[exu_div_ctl.scala 516:28]
node _T_88 = bits(a_ff, 31, 30) @[exu_div_ctl.scala 516:39]
node _T_89 = cat(_T_87, _T_88) @[Cat.scala 29:58]
node _T_90 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 516:54]
node _T_91 = add(_T_89, _T_90) @[exu_div_ctl.scala 516:48]
node adder1_out = tail(_T_91, 1) @[exu_div_ctl.scala 516:48]
node _T_92 = bits(r_ff, 30, 0) @[exu_div_ctl.scala 517:28]
node _T_93 = bits(a_ff, 31, 30) @[exu_div_ctl.scala 517:39]
node _T_94 = cat(_T_92, _T_93) @[Cat.scala 29:58]
node _T_95 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 517:58]
node _T_96 = cat(_T_95, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_97 = add(_T_94, _T_96) @[exu_div_ctl.scala 517:48]
node adder2_out = tail(_T_97, 1) @[exu_div_ctl.scala 517:48]
node _T_98 = bits(r_ff, 31, 31) @[exu_div_ctl.scala 518:28]
node _T_99 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 518:37]
node _T_100 = bits(a_ff, 31, 30) @[exu_div_ctl.scala 518:48]
node _T_101 = cat(_T_98, _T_99) @[Cat.scala 29:58]
node _T_102 = cat(_T_101, _T_100) @[Cat.scala 29:58]
node _T_103 = bits(b_ff, 33, 0) @[exu_div_ctl.scala 518:67]
node _T_104 = cat(_T_103, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_105 = add(_T_102, _T_104) @[exu_div_ctl.scala 518:57]
node _T_106 = tail(_T_105, 1) @[exu_div_ctl.scala 518:57]
node _T_107 = add(_T_106, b_ff) @[exu_div_ctl.scala 518:79]
node adder3_out = tail(_T_107, 1) @[exu_div_ctl.scala 518:79]
node _T_108 = bits(adder3_out, 34, 34) @[exu_div_ctl.scala 519:35]
node _T_109 = eq(_T_108, UInt<1>("h00")) @[exu_div_ctl.scala 519:24]
node _T_110 = xor(_T_109, dividend_sign_ff) @[exu_div_ctl.scala 519:40]
node _T_111 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 519:68]
node _T_112 = eq(_T_111, UInt<1>("h00")) @[exu_div_ctl.scala 519:75]
node _T_113 = eq(adder3_out, UInt<1>("h00")) @[exu_div_ctl.scala 519:98]
node _T_114 = and(_T_112, _T_113) @[exu_div_ctl.scala 519:84]
node _T_115 = or(_T_110, _T_114) @[exu_div_ctl.scala 519:60]
node _T_116 = bits(adder2_out, 33, 33) @[exu_div_ctl.scala 520:17]
node _T_117 = eq(_T_116, UInt<1>("h00")) @[exu_div_ctl.scala 520:6]
node _T_118 = xor(_T_117, dividend_sign_ff) @[exu_div_ctl.scala 520:22]
node _T_119 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 520:50]
node _T_120 = eq(_T_119, UInt<1>("h00")) @[exu_div_ctl.scala 520:57]
node _T_121 = eq(adder2_out, UInt<1>("h00")) @[exu_div_ctl.scala 520:80]
node _T_122 = and(_T_120, _T_121) @[exu_div_ctl.scala 520:66]
node _T_123 = or(_T_118, _T_122) @[exu_div_ctl.scala 520:42]
node _T_124 = bits(adder1_out, 32, 32) @[exu_div_ctl.scala 521:17]
node _T_125 = eq(_T_124, UInt<1>("h00")) @[exu_div_ctl.scala 521:6]
node _T_126 = xor(_T_125, dividend_sign_ff) @[exu_div_ctl.scala 521:22]
node _T_127 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 521:50]
node _T_128 = eq(_T_127, UInt<1>("h00")) @[exu_div_ctl.scala 521:57]
node _T_129 = eq(adder1_out, UInt<1>("h00")) @[exu_div_ctl.scala 521:80]
node _T_130 = and(_T_128, _T_129) @[exu_div_ctl.scala 521:66]
node _T_131 = or(_T_126, _T_130) @[exu_div_ctl.scala 521:42]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_132 = cat(_T_131, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_133 = cat(_T_115, _T_123) @[Cat.scala 29:58]
node _T_134 = cat(_T_133, _T_132) @[Cat.scala 29:58]
quotient_raw <= _T_134 @[exu_div_ctl.scala 519:16]
node _T_135 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 522:37]
node _T_136 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 522:56]
node _T_137 = or(_T_135, _T_136) @[exu_div_ctl.scala 522:41]
node _T_138 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 522:76]
node _T_139 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 522:95]
node _T_140 = eq(_T_139, UInt<1>("h00")) @[exu_div_ctl.scala 522:82]
node _T_141 = bits(quotient_raw, 1, 1) @[exu_div_ctl.scala 522:113]
node _T_142 = and(_T_140, _T_141) @[exu_div_ctl.scala 522:99]
node _T_143 = or(_T_138, _T_142) @[exu_div_ctl.scala 522:80]
node _T_144 = cat(_T_137, _T_143) @[Cat.scala 29:58]
quotient_new <= _T_144 @[exu_div_ctl.scala 522:16]
node _T_145 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 525:48]
node _T_146 = mux(twos_comp_q_sel, q_ff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_147 = mux(twos_comp_b_sel, _T_145, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_148 = or(_T_146, _T_147) @[Mux.scala 27:72]
2 bit divider
2021-01-06 12:32:46 +08:00
wire twos_comp_in : UInt<32> @[Mux.scala 27:72]
quotient new changed
2021-01-06 13:05:37 +08:00
twos_comp_in <= _T_148 @[Mux.scala 27:72]
wire _T_149 : UInt<1>[31] @[lib.scala 426:20]
node _T_150 = bits(twos_comp_in, 0, 0) @[lib.scala 428:27]
node _T_151 = orr(_T_150) @[lib.scala 428:35]
node _T_152 = bits(twos_comp_in, 1, 1) @[lib.scala 428:44]
node _T_153 = not(_T_152) @[lib.scala 428:40]
node _T_154 = bits(twos_comp_in, 1, 1) @[lib.scala 428:51]
node _T_155 = mux(_T_151, _T_153, _T_154) @[lib.scala 428:23]
_T_149[0] <= _T_155 @[lib.scala 428:17]
node _T_156 = bits(twos_comp_in, 1, 0) @[lib.scala 428:27]
node _T_157 = orr(_T_156) @[lib.scala 428:35]
node _T_158 = bits(twos_comp_in, 2, 2) @[lib.scala 428:44]
node _T_159 = not(_T_158) @[lib.scala 428:40]
node _T_160 = bits(twos_comp_in, 2, 2) @[lib.scala 428:51]
node _T_161 = mux(_T_157, _T_159, _T_160) @[lib.scala 428:23]
_T_149[1] <= _T_161 @[lib.scala 428:17]
node _T_162 = bits(twos_comp_in, 2, 0) @[lib.scala 428:27]
node _T_163 = orr(_T_162) @[lib.scala 428:35]
node _T_164 = bits(twos_comp_in, 3, 3) @[lib.scala 428:44]
node _T_165 = not(_T_164) @[lib.scala 428:40]
node _T_166 = bits(twos_comp_in, 3, 3) @[lib.scala 428:51]
node _T_167 = mux(_T_163, _T_165, _T_166) @[lib.scala 428:23]
_T_149[2] <= _T_167 @[lib.scala 428:17]
node _T_168 = bits(twos_comp_in, 3, 0) @[lib.scala 428:27]
node _T_169 = orr(_T_168) @[lib.scala 428:35]
node _T_170 = bits(twos_comp_in, 4, 4) @[lib.scala 428:44]
node _T_171 = not(_T_170) @[lib.scala 428:40]
node _T_172 = bits(twos_comp_in, 4, 4) @[lib.scala 428:51]
node _T_173 = mux(_T_169, _T_171, _T_172) @[lib.scala 428:23]
_T_149[3] <= _T_173 @[lib.scala 428:17]
node _T_174 = bits(twos_comp_in, 4, 0) @[lib.scala 428:27]
node _T_175 = orr(_T_174) @[lib.scala 428:35]
node _T_176 = bits(twos_comp_in, 5, 5) @[lib.scala 428:44]
node _T_177 = not(_T_176) @[lib.scala 428:40]
node _T_178 = bits(twos_comp_in, 5, 5) @[lib.scala 428:51]
node _T_179 = mux(_T_175, _T_177, _T_178) @[lib.scala 428:23]
_T_149[4] <= _T_179 @[lib.scala 428:17]
node _T_180 = bits(twos_comp_in, 5, 0) @[lib.scala 428:27]
node _T_181 = orr(_T_180) @[lib.scala 428:35]
node _T_182 = bits(twos_comp_in, 6, 6) @[lib.scala 428:44]
node _T_183 = not(_T_182) @[lib.scala 428:40]
node _T_184 = bits(twos_comp_in, 6, 6) @[lib.scala 428:51]
node _T_185 = mux(_T_181, _T_183, _T_184) @[lib.scala 428:23]
_T_149[5] <= _T_185 @[lib.scala 428:17]
node _T_186 = bits(twos_comp_in, 6, 0) @[lib.scala 428:27]
node _T_187 = orr(_T_186) @[lib.scala 428:35]
node _T_188 = bits(twos_comp_in, 7, 7) @[lib.scala 428:44]
node _T_189 = not(_T_188) @[lib.scala 428:40]
node _T_190 = bits(twos_comp_in, 7, 7) @[lib.scala 428:51]
node _T_191 = mux(_T_187, _T_189, _T_190) @[lib.scala 428:23]
_T_149[6] <= _T_191 @[lib.scala 428:17]
node _T_192 = bits(twos_comp_in, 7, 0) @[lib.scala 428:27]
node _T_193 = orr(_T_192) @[lib.scala 428:35]
node _T_194 = bits(twos_comp_in, 8, 8) @[lib.scala 428:44]
node _T_195 = not(_T_194) @[lib.scala 428:40]
node _T_196 = bits(twos_comp_in, 8, 8) @[lib.scala 428:51]
node _T_197 = mux(_T_193, _T_195, _T_196) @[lib.scala 428:23]
_T_149[7] <= _T_197 @[lib.scala 428:17]
node _T_198 = bits(twos_comp_in, 8, 0) @[lib.scala 428:27]
node _T_199 = orr(_T_198) @[lib.scala 428:35]
node _T_200 = bits(twos_comp_in, 9, 9) @[lib.scala 428:44]
node _T_201 = not(_T_200) @[lib.scala 428:40]
node _T_202 = bits(twos_comp_in, 9, 9) @[lib.scala 428:51]
node _T_203 = mux(_T_199, _T_201, _T_202) @[lib.scala 428:23]
_T_149[8] <= _T_203 @[lib.scala 428:17]
node _T_204 = bits(twos_comp_in, 9, 0) @[lib.scala 428:27]
node _T_205 = orr(_T_204) @[lib.scala 428:35]
node _T_206 = bits(twos_comp_in, 10, 10) @[lib.scala 428:44]
node _T_207 = not(_T_206) @[lib.scala 428:40]
node _T_208 = bits(twos_comp_in, 10, 10) @[lib.scala 428:51]
node _T_209 = mux(_T_205, _T_207, _T_208) @[lib.scala 428:23]
_T_149[9] <= _T_209 @[lib.scala 428:17]
node _T_210 = bits(twos_comp_in, 10, 0) @[lib.scala 428:27]
node _T_211 = orr(_T_210) @[lib.scala 428:35]
node _T_212 = bits(twos_comp_in, 11, 11) @[lib.scala 428:44]
node _T_213 = not(_T_212) @[lib.scala 428:40]
node _T_214 = bits(twos_comp_in, 11, 11) @[lib.scala 428:51]
node _T_215 = mux(_T_211, _T_213, _T_214) @[lib.scala 428:23]
_T_149[10] <= _T_215 @[lib.scala 428:17]
node _T_216 = bits(twos_comp_in, 11, 0) @[lib.scala 428:27]
node _T_217 = orr(_T_216) @[lib.scala 428:35]
node _T_218 = bits(twos_comp_in, 12, 12) @[lib.scala 428:44]
node _T_219 = not(_T_218) @[lib.scala 428:40]
node _T_220 = bits(twos_comp_in, 12, 12) @[lib.scala 428:51]
node _T_221 = mux(_T_217, _T_219, _T_220) @[lib.scala 428:23]
_T_149[11] <= _T_221 @[lib.scala 428:17]
node _T_222 = bits(twos_comp_in, 12, 0) @[lib.scala 428:27]
node _T_223 = orr(_T_222) @[lib.scala 428:35]
node _T_224 = bits(twos_comp_in, 13, 13) @[lib.scala 428:44]
node _T_225 = not(_T_224) @[lib.scala 428:40]
node _T_226 = bits(twos_comp_in, 13, 13) @[lib.scala 428:51]
node _T_227 = mux(_T_223, _T_225, _T_226) @[lib.scala 428:23]
_T_149[12] <= _T_227 @[lib.scala 428:17]
node _T_228 = bits(twos_comp_in, 13, 0) @[lib.scala 428:27]
node _T_229 = orr(_T_228) @[lib.scala 428:35]
node _T_230 = bits(twos_comp_in, 14, 14) @[lib.scala 428:44]
node _T_231 = not(_T_230) @[lib.scala 428:40]
node _T_232 = bits(twos_comp_in, 14, 14) @[lib.scala 428:51]
node _T_233 = mux(_T_229, _T_231, _T_232) @[lib.scala 428:23]
_T_149[13] <= _T_233 @[lib.scala 428:17]
node _T_234 = bits(twos_comp_in, 14, 0) @[lib.scala 428:27]
node _T_235 = orr(_T_234) @[lib.scala 428:35]
node _T_236 = bits(twos_comp_in, 15, 15) @[lib.scala 428:44]
node _T_237 = not(_T_236) @[lib.scala 428:40]
node _T_238 = bits(twos_comp_in, 15, 15) @[lib.scala 428:51]
node _T_239 = mux(_T_235, _T_237, _T_238) @[lib.scala 428:23]
_T_149[14] <= _T_239 @[lib.scala 428:17]
node _T_240 = bits(twos_comp_in, 15, 0) @[lib.scala 428:27]
node _T_241 = orr(_T_240) @[lib.scala 428:35]
node _T_242 = bits(twos_comp_in, 16, 16) @[lib.scala 428:44]
node _T_243 = not(_T_242) @[lib.scala 428:40]
node _T_244 = bits(twos_comp_in, 16, 16) @[lib.scala 428:51]
node _T_245 = mux(_T_241, _T_243, _T_244) @[lib.scala 428:23]
_T_149[15] <= _T_245 @[lib.scala 428:17]
node _T_246 = bits(twos_comp_in, 16, 0) @[lib.scala 428:27]
node _T_247 = orr(_T_246) @[lib.scala 428:35]
node _T_248 = bits(twos_comp_in, 17, 17) @[lib.scala 428:44]
node _T_249 = not(_T_248) @[lib.scala 428:40]
node _T_250 = bits(twos_comp_in, 17, 17) @[lib.scala 428:51]
node _T_251 = mux(_T_247, _T_249, _T_250) @[lib.scala 428:23]
_T_149[16] <= _T_251 @[lib.scala 428:17]
node _T_252 = bits(twos_comp_in, 17, 0) @[lib.scala 428:27]
node _T_253 = orr(_T_252) @[lib.scala 428:35]
node _T_254 = bits(twos_comp_in, 18, 18) @[lib.scala 428:44]
node _T_255 = not(_T_254) @[lib.scala 428:40]
node _T_256 = bits(twos_comp_in, 18, 18) @[lib.scala 428:51]
node _T_257 = mux(_T_253, _T_255, _T_256) @[lib.scala 428:23]
_T_149[17] <= _T_257 @[lib.scala 428:17]
node _T_258 = bits(twos_comp_in, 18, 0) @[lib.scala 428:27]
node _T_259 = orr(_T_258) @[lib.scala 428:35]
node _T_260 = bits(twos_comp_in, 19, 19) @[lib.scala 428:44]
node _T_261 = not(_T_260) @[lib.scala 428:40]
node _T_262 = bits(twos_comp_in, 19, 19) @[lib.scala 428:51]
node _T_263 = mux(_T_259, _T_261, _T_262) @[lib.scala 428:23]
_T_149[18] <= _T_263 @[lib.scala 428:17]
node _T_264 = bits(twos_comp_in, 19, 0) @[lib.scala 428:27]
node _T_265 = orr(_T_264) @[lib.scala 428:35]
node _T_266 = bits(twos_comp_in, 20, 20) @[lib.scala 428:44]
node _T_267 = not(_T_266) @[lib.scala 428:40]
node _T_268 = bits(twos_comp_in, 20, 20) @[lib.scala 428:51]
node _T_269 = mux(_T_265, _T_267, _T_268) @[lib.scala 428:23]
_T_149[19] <= _T_269 @[lib.scala 428:17]
node _T_270 = bits(twos_comp_in, 20, 0) @[lib.scala 428:27]
node _T_271 = orr(_T_270) @[lib.scala 428:35]
node _T_272 = bits(twos_comp_in, 21, 21) @[lib.scala 428:44]
node _T_273 = not(_T_272) @[lib.scala 428:40]
node _T_274 = bits(twos_comp_in, 21, 21) @[lib.scala 428:51]
node _T_275 = mux(_T_271, _T_273, _T_274) @[lib.scala 428:23]
_T_149[20] <= _T_275 @[lib.scala 428:17]
node _T_276 = bits(twos_comp_in, 21, 0) @[lib.scala 428:27]
node _T_277 = orr(_T_276) @[lib.scala 428:35]
node _T_278 = bits(twos_comp_in, 22, 22) @[lib.scala 428:44]
node _T_279 = not(_T_278) @[lib.scala 428:40]
node _T_280 = bits(twos_comp_in, 22, 22) @[lib.scala 428:51]
node _T_281 = mux(_T_277, _T_279, _T_280) @[lib.scala 428:23]
_T_149[21] <= _T_281 @[lib.scala 428:17]
node _T_282 = bits(twos_comp_in, 22, 0) @[lib.scala 428:27]
node _T_283 = orr(_T_282) @[lib.scala 428:35]
node _T_284 = bits(twos_comp_in, 23, 23) @[lib.scala 428:44]
node _T_285 = not(_T_284) @[lib.scala 428:40]
node _T_286 = bits(twos_comp_in, 23, 23) @[lib.scala 428:51]
node _T_287 = mux(_T_283, _T_285, _T_286) @[lib.scala 428:23]
_T_149[22] <= _T_287 @[lib.scala 428:17]
node _T_288 = bits(twos_comp_in, 23, 0) @[lib.scala 428:27]
node _T_289 = orr(_T_288) @[lib.scala 428:35]
node _T_290 = bits(twos_comp_in, 24, 24) @[lib.scala 428:44]
node _T_291 = not(_T_290) @[lib.scala 428:40]
node _T_292 = bits(twos_comp_in, 24, 24) @[lib.scala 428:51]
node _T_293 = mux(_T_289, _T_291, _T_292) @[lib.scala 428:23]
_T_149[23] <= _T_293 @[lib.scala 428:17]
node _T_294 = bits(twos_comp_in, 24, 0) @[lib.scala 428:27]
node _T_295 = orr(_T_294) @[lib.scala 428:35]
node _T_296 = bits(twos_comp_in, 25, 25) @[lib.scala 428:44]
node _T_297 = not(_T_296) @[lib.scala 428:40]
node _T_298 = bits(twos_comp_in, 25, 25) @[lib.scala 428:51]
node _T_299 = mux(_T_295, _T_297, _T_298) @[lib.scala 428:23]
_T_149[24] <= _T_299 @[lib.scala 428:17]
node _T_300 = bits(twos_comp_in, 25, 0) @[lib.scala 428:27]
node _T_301 = orr(_T_300) @[lib.scala 428:35]
node _T_302 = bits(twos_comp_in, 26, 26) @[lib.scala 428:44]
node _T_303 = not(_T_302) @[lib.scala 428:40]
node _T_304 = bits(twos_comp_in, 26, 26) @[lib.scala 428:51]
node _T_305 = mux(_T_301, _T_303, _T_304) @[lib.scala 428:23]
_T_149[25] <= _T_305 @[lib.scala 428:17]
node _T_306 = bits(twos_comp_in, 26, 0) @[lib.scala 428:27]
node _T_307 = orr(_T_306) @[lib.scala 428:35]
node _T_308 = bits(twos_comp_in, 27, 27) @[lib.scala 428:44]
node _T_309 = not(_T_308) @[lib.scala 428:40]
node _T_310 = bits(twos_comp_in, 27, 27) @[lib.scala 428:51]
node _T_311 = mux(_T_307, _T_309, _T_310) @[lib.scala 428:23]
_T_149[26] <= _T_311 @[lib.scala 428:17]
node _T_312 = bits(twos_comp_in, 27, 0) @[lib.scala 428:27]
node _T_313 = orr(_T_312) @[lib.scala 428:35]
node _T_314 = bits(twos_comp_in, 28, 28) @[lib.scala 428:44]
node _T_315 = not(_T_314) @[lib.scala 428:40]
node _T_316 = bits(twos_comp_in, 28, 28) @[lib.scala 428:51]
node _T_317 = mux(_T_313, _T_315, _T_316) @[lib.scala 428:23]
_T_149[27] <= _T_317 @[lib.scala 428:17]
node _T_318 = bits(twos_comp_in, 28, 0) @[lib.scala 428:27]
node _T_319 = orr(_T_318) @[lib.scala 428:35]
node _T_320 = bits(twos_comp_in, 29, 29) @[lib.scala 428:44]
node _T_321 = not(_T_320) @[lib.scala 428:40]
node _T_322 = bits(twos_comp_in, 29, 29) @[lib.scala 428:51]
node _T_323 = mux(_T_319, _T_321, _T_322) @[lib.scala 428:23]
_T_149[28] <= _T_323 @[lib.scala 428:17]
node _T_324 = bits(twos_comp_in, 29, 0) @[lib.scala 428:27]
node _T_325 = orr(_T_324) @[lib.scala 428:35]
node _T_326 = bits(twos_comp_in, 30, 30) @[lib.scala 428:44]
node _T_327 = not(_T_326) @[lib.scala 428:40]
node _T_328 = bits(twos_comp_in, 30, 30) @[lib.scala 428:51]
node _T_329 = mux(_T_325, _T_327, _T_328) @[lib.scala 428:23]
_T_149[29] <= _T_329 @[lib.scala 428:17]
node _T_330 = bits(twos_comp_in, 30, 0) @[lib.scala 428:27]
node _T_331 = orr(_T_330) @[lib.scala 428:35]
node _T_332 = bits(twos_comp_in, 31, 31) @[lib.scala 428:44]
node _T_333 = not(_T_332) @[lib.scala 428:40]
node _T_334 = bits(twos_comp_in, 31, 31) @[lib.scala 428:51]
node _T_335 = mux(_T_331, _T_333, _T_334) @[lib.scala 428:23]
_T_149[30] <= _T_335 @[lib.scala 428:17]
node _T_336 = cat(_T_149[2], _T_149[1]) @[lib.scala 430:14]
node _T_337 = cat(_T_336, _T_149[0]) @[lib.scala 430:14]
node _T_338 = cat(_T_149[4], _T_149[3]) @[lib.scala 430:14]
node _T_339 = cat(_T_149[6], _T_149[5]) @[lib.scala 430:14]
node _T_340 = cat(_T_339, _T_338) @[lib.scala 430:14]
node _T_341 = cat(_T_340, _T_337) @[lib.scala 430:14]
node _T_342 = cat(_T_149[8], _T_149[7]) @[lib.scala 430:14]
node _T_343 = cat(_T_149[10], _T_149[9]) @[lib.scala 430:14]
node _T_344 = cat(_T_343, _T_342) @[lib.scala 430:14]
node _T_345 = cat(_T_149[12], _T_149[11]) @[lib.scala 430:14]
node _T_346 = cat(_T_149[14], _T_149[13]) @[lib.scala 430:14]
node _T_347 = cat(_T_346, _T_345) @[lib.scala 430:14]
node _T_348 = cat(_T_347, _T_344) @[lib.scala 430:14]
node _T_349 = cat(_T_348, _T_341) @[lib.scala 430:14]
node _T_350 = cat(_T_149[16], _T_149[15]) @[lib.scala 430:14]
node _T_351 = cat(_T_149[18], _T_149[17]) @[lib.scala 430:14]
node _T_352 = cat(_T_351, _T_350) @[lib.scala 430:14]
node _T_353 = cat(_T_149[20], _T_149[19]) @[lib.scala 430:14]
node _T_354 = cat(_T_149[22], _T_149[21]) @[lib.scala 430:14]
node _T_355 = cat(_T_354, _T_353) @[lib.scala 430:14]
node _T_356 = cat(_T_355, _T_352) @[lib.scala 430:14]
node _T_357 = cat(_T_149[24], _T_149[23]) @[lib.scala 430:14]
node _T_358 = cat(_T_149[26], _T_149[25]) @[lib.scala 430:14]
node _T_359 = cat(_T_358, _T_357) @[lib.scala 430:14]
node _T_360 = cat(_T_149[28], _T_149[27]) @[lib.scala 430:14]
node _T_361 = cat(_T_149[30], _T_149[29]) @[lib.scala 430:14]
node _T_362 = cat(_T_361, _T_360) @[lib.scala 430:14]
node _T_363 = cat(_T_362, _T_359) @[lib.scala 430:14]
node _T_364 = cat(_T_363, _T_356) @[lib.scala 430:14]
node _T_365 = cat(_T_364, _T_349) @[lib.scala 430:14]
node _T_366 = bits(twos_comp_in, 0, 0) @[lib.scala 430:24]
node twos_comp_out = cat(_T_365, _T_366) @[Cat.scala 29:58]
node _T_367 = eq(a_shift, UInt<1>("h00")) @[exu_div_ctl.scala 530:6]
node _T_368 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 530:17]
node _T_369 = and(_T_367, _T_368) @[exu_div_ctl.scala 530:15]
node _T_370 = bits(_T_369, 0, 0) @[exu_div_ctl.scala 530:36]
node _T_371 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 531:52]
node _T_372 = cat(_T_371, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_373 = bits(ar_shifted, 31, 0) @[exu_div_ctl.scala 532:54]
node _T_374 = mux(_T_370, io.dividend_in, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_375 = mux(a_shift, _T_372, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_376 = mux(shortq_enable_ff, _T_373, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_377 = or(_T_374, _T_375) @[Mux.scala 27:72]
node _T_378 = or(_T_377, _T_376) @[Mux.scala 27:72]
2 bit divider
2021-01-06 12:32:46 +08:00
wire a_in : UInt<32> @[Mux.scala 27:72]
quotient new changed
2021-01-06 13:05:37 +08:00
a_in <= _T_378 @[Mux.scala 27:72]
node _T_379 = eq(b_twos_comp, UInt<1>("h00")) @[exu_div_ctl.scala 536:5]
node _T_380 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 536:78]
node _T_381 = and(io.signed_in, _T_380) @[exu_div_ctl.scala 536:63]
node _T_382 = bits(io.divisor_in, 31, 0) @[exu_div_ctl.scala 536:96]
node _T_383 = cat(_T_381, _T_382) @[Cat.scala 29:58]
node _T_384 = eq(divisor_sign_ff, UInt<1>("h00")) @[exu_div_ctl.scala 537:49]
node _T_385 = bits(twos_comp_out, 31, 0) @[exu_div_ctl.scala 537:79]
node _T_386 = cat(_T_384, _T_385) @[Cat.scala 29:58]
node _T_387 = mux(_T_379, _T_383, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_388 = mux(b_twos_comp, _T_386, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_389 = or(_T_387, _T_388) @[Mux.scala 27:72]
2 bit divider
2021-01-06 12:32:46 +08:00
wire b_in : UInt<33> @[Mux.scala 27:72]
quotient new changed
2021-01-06 13:05:37 +08:00
b_in <= _T_389 @[Mux.scala 27:72]
node _T_390 = bits(r_ff, 29, 0) @[exu_div_ctl.scala 541:54]
node _T_391 = bits(a_ff, 31, 30) @[exu_div_ctl.scala 541:65]
node _T_392 = cat(_T_390, _T_391) @[Cat.scala 29:58]
node _T_393 = bits(adder1_out, 31, 0) @[exu_div_ctl.scala 542:57]
node _T_394 = bits(adder2_out, 31, 0) @[exu_div_ctl.scala 543:57]
node _T_395 = bits(adder3_out, 31, 0) @[exu_div_ctl.scala 544:57]
node _T_396 = bits(ar_shifted, 63, 32) @[exu_div_ctl.scala 545:56]
node _T_397 = mux(r_sign_sel, UInt<32>("h0ffffffff"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_398 = mux(r_restore_sel, _T_392, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_399 = mux(r_adder1_sel, _T_393, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_400 = mux(r_adder2_sel, _T_394, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_401 = mux(r_adder3_sel, _T_395, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_402 = mux(shortq_enable_ff, _T_396, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_403 = mux(by_zero_case, a_ff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_404 = or(_T_397, _T_398) @[Mux.scala 27:72]
2 bit divider
2021-01-06 12:32:46 +08:00
node _T_405 = or(_T_404, _T_399) @[Mux.scala 27:72]
node _T_406 = or(_T_405, _T_400) @[Mux.scala 27:72]
node _T_407 = or(_T_406, _T_401) @[Mux.scala 27:72]
node _T_408 = or(_T_407, _T_402) @[Mux.scala 27:72]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_409 = or(_T_408, _T_403) @[Mux.scala 27:72]
2 bit divider
2021-01-06 12:32:46 +08:00
wire r_in : UInt<32> @[Mux.scala 27:72]
quotient new changed
2021-01-06 13:05:37 +08:00
r_in <= _T_409 @[Mux.scala 27:72]
node _T_410 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 549:5]
node _T_411 = bits(q_ff, 29, 0) @[exu_div_ctl.scala 549:55]
node _T_412 = cat(_T_411, quotient_new) @[Cat.scala 29:58]
node _T_413 = cat(UInt<28>("h00"), smallnum) @[Cat.scala 29:58]
node _T_414 = mux(UInt<1>("h01"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_415 = mux(_T_410, _T_412, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_416 = mux(smallnum_case, _T_413, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_417 = mux(by_zero_case, _T_414, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_418 = or(_T_415, _T_416) @[Mux.scala 27:72]
node _T_419 = or(_T_418, _T_417) @[Mux.scala 27:72]
2 bit divider
2021-01-06 12:32:46 +08:00
wire q_in : UInt<32> @[Mux.scala 27:72]
quotient new changed
2021-01-06 13:05:37 +08:00
q_in <= _T_419 @[Mux.scala 27:72]
node _T_420 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 553:31]
node _T_421 = and(finish_ff, _T_420) @[exu_div_ctl.scala 553:29]
io.valid_out <= _T_421 @[exu_div_ctl.scala 553:16]
node _T_422 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 555:6]
node _T_423 = eq(twos_comp_q_sel, UInt<1>("h00")) @[exu_div_ctl.scala 555:16]
node _T_424 = and(_T_422, _T_423) @[exu_div_ctl.scala 555:14]
node _T_425 = bits(_T_424, 0, 0) @[exu_div_ctl.scala 555:40]
node _T_426 = mux(_T_425, q_ff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_427 = mux(rem_ff, r_ff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_428 = mux(twos_comp_q_sel, twos_comp_out, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_429 = or(_T_426, _T_427) @[Mux.scala 27:72]
node _T_430 = or(_T_429, _T_428) @[Mux.scala 27:72]
wire _T_431 : UInt<32> @[Mux.scala 27:72]
_T_431 <= _T_430 @[Mux.scala 27:72]
io.data_out <= _T_431 @[exu_div_ctl.scala 554:15]
node _T_432 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_433 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_434 = eq(_T_433, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_435 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_436 = eq(_T_435, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_437 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_438 = eq(_T_437, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_439 = and(_T_434, _T_436) @[exu_div_ctl.scala 561:95]
node _T_440 = and(_T_439, _T_438) @[exu_div_ctl.scala 561:95]
node _T_441 = and(_T_432, _T_440) @[exu_div_ctl.scala 562:11]
node _T_442 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_443 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_444 = eq(_T_443, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_445 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_446 = eq(_T_445, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_447 = and(_T_444, _T_446) @[exu_div_ctl.scala 561:95]
node _T_448 = and(_T_442, _T_447) @[exu_div_ctl.scala 562:11]
node _T_449 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 567:38]
node _T_450 = eq(_T_449, UInt<1>("h00")) @[exu_div_ctl.scala 567:33]
node _T_451 = and(_T_448, _T_450) @[exu_div_ctl.scala 567:31]
node _T_452 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_453 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_454 = eq(_T_453, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_455 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_456 = eq(_T_455, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_457 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_458 = eq(_T_457, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_459 = and(_T_454, _T_456) @[exu_div_ctl.scala 561:95]
node _T_460 = and(_T_459, _T_458) @[exu_div_ctl.scala 561:95]
node _T_461 = and(_T_452, _T_460) @[exu_div_ctl.scala 562:11]
node _T_462 = or(_T_451, _T_461) @[exu_div_ctl.scala 567:42]
node _T_463 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_464 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_465 = and(_T_463, _T_464) @[exu_div_ctl.scala 560:95]
node _T_466 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_467 = eq(_T_466, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_468 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_469 = eq(_T_468, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_470 = and(_T_467, _T_469) @[exu_div_ctl.scala 561:95]
node _T_471 = and(_T_465, _T_470) @[exu_div_ctl.scala 562:11]
node _T_472 = or(_T_462, _T_471) @[exu_div_ctl.scala 567:75]
node _T_473 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_474 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_475 = eq(_T_474, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_476 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_477 = eq(_T_476, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_478 = and(_T_475, _T_477) @[exu_div_ctl.scala 561:95]
node _T_479 = and(_T_473, _T_478) @[exu_div_ctl.scala 562:11]
node _T_480 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 569:38]
node _T_481 = eq(_T_480, UInt<1>("h00")) @[exu_div_ctl.scala 569:33]
node _T_482 = and(_T_479, _T_481) @[exu_div_ctl.scala 569:31]
node _T_483 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_484 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_485 = eq(_T_484, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_486 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_487 = eq(_T_486, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_488 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_489 = eq(_T_488, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_490 = and(_T_485, _T_487) @[exu_div_ctl.scala 561:95]
node _T_491 = and(_T_490, _T_489) @[exu_div_ctl.scala 561:95]
node _T_492 = and(_T_483, _T_491) @[exu_div_ctl.scala 562:11]
node _T_493 = or(_T_482, _T_492) @[exu_div_ctl.scala 569:42]
node _T_494 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_495 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_496 = eq(_T_495, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_497 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_498 = eq(_T_497, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_499 = and(_T_496, _T_498) @[exu_div_ctl.scala 561:95]
node _T_500 = and(_T_494, _T_499) @[exu_div_ctl.scala 562:11]
node _T_501 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 569:113]
node _T_502 = eq(_T_501, UInt<1>("h00")) @[exu_div_ctl.scala 569:108]
node _T_503 = and(_T_500, _T_502) @[exu_div_ctl.scala 569:106]
node _T_504 = or(_T_493, _T_503) @[exu_div_ctl.scala 569:78]
node _T_505 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_506 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
node _T_507 = eq(_T_506, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_508 = and(_T_505, _T_507) @[exu_div_ctl.scala 560:95]
node _T_509 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_510 = eq(_T_509, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_511 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_512 = eq(_T_511, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_513 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_514 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 561:58]
node _T_515 = and(_T_510, _T_512) @[exu_div_ctl.scala 561:95]
2 bit divider
2021-01-06 12:32:46 +08:00
node _T_516 = and(_T_515, _T_513) @[exu_div_ctl.scala 561:95]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_517 = and(_T_516, _T_514) @[exu_div_ctl.scala 561:95]
node _T_518 = and(_T_508, _T_517) @[exu_div_ctl.scala 562:11]
node _T_519 = or(_T_504, _T_518) @[exu_div_ctl.scala 569:117]
node _T_520 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
node _T_521 = eq(_T_520, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_522 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_523 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_524 = and(_T_521, _T_522) @[exu_div_ctl.scala 560:95]
node _T_525 = and(_T_524, _T_523) @[exu_div_ctl.scala 560:95]
node _T_526 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_527 = eq(_T_526, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_528 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_529 = eq(_T_528, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_530 = and(_T_527, _T_529) @[exu_div_ctl.scala 561:95]
node _T_531 = and(_T_525, _T_530) @[exu_div_ctl.scala 562:11]
node _T_532 = or(_T_519, _T_531) @[exu_div_ctl.scala 570:44]
node _T_533 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_534 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_535 = and(_T_533, _T_534) @[exu_div_ctl.scala 560:95]
node _T_536 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_537 = eq(_T_536, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_538 = and(_T_535, _T_537) @[exu_div_ctl.scala 562:11]
node _T_539 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 570:114]
node _T_540 = eq(_T_539, UInt<1>("h00")) @[exu_div_ctl.scala 570:109]
node _T_541 = and(_T_538, _T_540) @[exu_div_ctl.scala 570:107]
node _T_542 = or(_T_532, _T_541) @[exu_div_ctl.scala 570:80]
node _T_543 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_544 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_545 = and(_T_543, _T_544) @[exu_div_ctl.scala 560:95]
node _T_546 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_547 = eq(_T_546, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_548 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_549 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_550 = eq(_T_549, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_551 = and(_T_547, _T_548) @[exu_div_ctl.scala 561:95]
node _T_552 = and(_T_551, _T_550) @[exu_div_ctl.scala 561:95]
node _T_553 = and(_T_545, _T_552) @[exu_div_ctl.scala 562:11]
node _T_554 = or(_T_542, _T_553) @[exu_div_ctl.scala 570:119]
node _T_555 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_556 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_557 = and(_T_555, _T_556) @[exu_div_ctl.scala 560:95]
node _T_558 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_559 = eq(_T_558, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_560 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_561 = eq(_T_560, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_562 = and(_T_559, _T_561) @[exu_div_ctl.scala 561:95]
node _T_563 = and(_T_557, _T_562) @[exu_div_ctl.scala 562:11]
node _T_564 = or(_T_554, _T_563) @[exu_div_ctl.scala 571:44]
node _T_565 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_566 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_567 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_568 = and(_T_565, _T_566) @[exu_div_ctl.scala 560:95]
node _T_569 = and(_T_568, _T_567) @[exu_div_ctl.scala 560:95]
node _T_570 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_571 = eq(_T_570, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_572 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_573 = and(_T_571, _T_572) @[exu_div_ctl.scala 561:95]
node _T_574 = and(_T_569, _T_573) @[exu_div_ctl.scala 562:11]
node _T_575 = or(_T_564, _T_574) @[exu_div_ctl.scala 571:79]
node _T_576 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_577 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_578 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_579 = and(_T_576, _T_577) @[exu_div_ctl.scala 560:95]
node _T_580 = and(_T_579, _T_578) @[exu_div_ctl.scala 560:95]
node _T_581 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_582 = eq(_T_581, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_583 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_584 = eq(_T_583, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_585 = and(_T_582, _T_584) @[exu_div_ctl.scala 561:95]
node _T_586 = and(_T_580, _T_585) @[exu_div_ctl.scala 562:11]
node _T_587 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_588 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
node _T_589 = eq(_T_588, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_590 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_591 = and(_T_587, _T_589) @[exu_div_ctl.scala 560:95]
node _T_592 = and(_T_591, _T_590) @[exu_div_ctl.scala 560:95]
node _T_593 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_594 = eq(_T_593, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_595 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_596 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 561:58]
node _T_597 = and(_T_594, _T_595) @[exu_div_ctl.scala 561:95]
node _T_598 = and(_T_597, _T_596) @[exu_div_ctl.scala 561:95]
node _T_599 = and(_T_592, _T_598) @[exu_div_ctl.scala 562:11]
node _T_600 = or(_T_586, _T_599) @[exu_div_ctl.scala 573:45]
node _T_601 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_602 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_603 = eq(_T_602, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_604 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_605 = eq(_T_604, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_606 = and(_T_603, _T_605) @[exu_div_ctl.scala 561:95]
node _T_607 = and(_T_601, _T_606) @[exu_div_ctl.scala 562:11]
node _T_608 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 573:121]
node _T_609 = eq(_T_608, UInt<1>("h00")) @[exu_div_ctl.scala 573:116]
node _T_610 = and(_T_607, _T_609) @[exu_div_ctl.scala 573:114]
node _T_611 = or(_T_600, _T_610) @[exu_div_ctl.scala 573:86]
node _T_612 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_613 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_614 = eq(_T_613, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_615 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_616 = eq(_T_615, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_617 = and(_T_614, _T_616) @[exu_div_ctl.scala 561:95]
node _T_618 = and(_T_612, _T_617) @[exu_div_ctl.scala 562:11]
node _T_619 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 574:40]
node _T_620 = eq(_T_619, UInt<1>("h00")) @[exu_div_ctl.scala 574:35]
node _T_621 = and(_T_618, _T_620) @[exu_div_ctl.scala 574:33]
node _T_622 = or(_T_611, _T_621) @[exu_div_ctl.scala 573:129]
node _T_623 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_624 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_625 = eq(_T_624, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_626 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_627 = eq(_T_626, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_628 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_629 = eq(_T_628, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_630 = and(_T_625, _T_627) @[exu_div_ctl.scala 561:95]
node _T_631 = and(_T_630, _T_629) @[exu_div_ctl.scala 561:95]
node _T_632 = and(_T_623, _T_631) @[exu_div_ctl.scala 562:11]
node _T_633 = or(_T_622, _T_632) @[exu_div_ctl.scala 574:47]
node _T_634 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
node _T_635 = eq(_T_634, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_636 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_637 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:75]
node _T_638 = eq(_T_637, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_639 = and(_T_635, _T_636) @[exu_div_ctl.scala 560:95]
node _T_640 = and(_T_639, _T_638) @[exu_div_ctl.scala 560:95]
node _T_641 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_642 = eq(_T_641, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_643 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_644 = eq(_T_643, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_645 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_646 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 561:58]
node _T_647 = and(_T_642, _T_644) @[exu_div_ctl.scala 561:95]
2 bit divider
2021-01-06 12:32:46 +08:00
node _T_648 = and(_T_647, _T_645) @[exu_div_ctl.scala 561:95]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_649 = and(_T_648, _T_646) @[exu_div_ctl.scala 561:95]
node _T_650 = and(_T_640, _T_649) @[exu_div_ctl.scala 562:11]
node _T_651 = or(_T_633, _T_650) @[exu_div_ctl.scala 574:88]
node _T_652 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
node _T_653 = eq(_T_652, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_654 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_655 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_656 = and(_T_653, _T_654) @[exu_div_ctl.scala 560:95]
node _T_657 = and(_T_656, _T_655) @[exu_div_ctl.scala 560:95]
node _T_658 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_659 = eq(_T_658, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_660 = and(_T_657, _T_659) @[exu_div_ctl.scala 562:11]
node _T_661 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 575:43]
node _T_662 = eq(_T_661, UInt<1>("h00")) @[exu_div_ctl.scala 575:38]
node _T_663 = and(_T_660, _T_662) @[exu_div_ctl.scala 575:36]
node _T_664 = or(_T_651, _T_663) @[exu_div_ctl.scala 574:131]
node _T_665 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_666 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_667 = eq(_T_666, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_668 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_669 = eq(_T_668, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_670 = and(_T_667, _T_669) @[exu_div_ctl.scala 561:95]
node _T_671 = and(_T_665, _T_670) @[exu_div_ctl.scala 562:11]
node _T_672 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 575:83]
node _T_673 = eq(_T_672, UInt<1>("h00")) @[exu_div_ctl.scala 575:78]
node _T_674 = and(_T_671, _T_673) @[exu_div_ctl.scala 575:76]
node _T_675 = or(_T_664, _T_674) @[exu_div_ctl.scala 575:47]
node _T_676 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_677 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
node _T_678 = eq(_T_677, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_679 = and(_T_676, _T_678) @[exu_div_ctl.scala 560:95]
node _T_680 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_681 = eq(_T_680, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_682 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_683 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_684 = and(_T_681, _T_682) @[exu_div_ctl.scala 561:95]
node _T_685 = and(_T_684, _T_683) @[exu_div_ctl.scala 561:95]
node _T_686 = and(_T_679, _T_685) @[exu_div_ctl.scala 562:11]
node _T_687 = or(_T_675, _T_686) @[exu_div_ctl.scala 575:88]
node _T_688 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
node _T_689 = eq(_T_688, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_690 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_691 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_692 = and(_T_689, _T_690) @[exu_div_ctl.scala 560:95]
node _T_693 = and(_T_692, _T_691) @[exu_div_ctl.scala 560:95]
node _T_694 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_695 = eq(_T_694, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_696 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_697 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_698 = eq(_T_697, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_699 = and(_T_695, _T_696) @[exu_div_ctl.scala 561:95]
node _T_700 = and(_T_699, _T_698) @[exu_div_ctl.scala 561:95]
node _T_701 = and(_T_693, _T_700) @[exu_div_ctl.scala 562:11]
node _T_702 = or(_T_687, _T_701) @[exu_div_ctl.scala 575:131]
node _T_703 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
node _T_704 = eq(_T_703, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_705 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_706 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_707 = and(_T_704, _T_705) @[exu_div_ctl.scala 560:95]
node _T_708 = and(_T_707, _T_706) @[exu_div_ctl.scala 560:95]
node _T_709 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_710 = eq(_T_709, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_711 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_712 = eq(_T_711, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_713 = and(_T_710, _T_712) @[exu_div_ctl.scala 561:95]
node _T_714 = and(_T_708, _T_713) @[exu_div_ctl.scala 562:11]
node _T_715 = or(_T_702, _T_714) @[exu_div_ctl.scala 576:47]
node _T_716 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_717 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
node _T_718 = eq(_T_717, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_719 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:75]
node _T_720 = eq(_T_719, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_721 = and(_T_716, _T_718) @[exu_div_ctl.scala 560:95]
node _T_722 = and(_T_721, _T_720) @[exu_div_ctl.scala 560:95]
node _T_723 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_724 = eq(_T_723, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_725 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_726 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 561:58]
node _T_727 = and(_T_724, _T_725) @[exu_div_ctl.scala 561:95]
node _T_728 = and(_T_727, _T_726) @[exu_div_ctl.scala 561:95]
node _T_729 = and(_T_722, _T_728) @[exu_div_ctl.scala 562:11]
node _T_730 = or(_T_715, _T_729) @[exu_div_ctl.scala 576:88]
node _T_731 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
node _T_732 = eq(_T_731, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_733 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_734 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_735 = and(_T_732, _T_733) @[exu_div_ctl.scala 560:95]
node _T_736 = and(_T_735, _T_734) @[exu_div_ctl.scala 560:95]
node _T_737 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_738 = eq(_T_737, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_739 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_740 = eq(_T_739, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_741 = and(_T_738, _T_740) @[exu_div_ctl.scala 561:95]
node _T_742 = and(_T_736, _T_741) @[exu_div_ctl.scala 562:11]
node _T_743 = or(_T_730, _T_742) @[exu_div_ctl.scala 576:131]
node _T_744 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_745 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_746 = and(_T_744, _T_745) @[exu_div_ctl.scala 560:95]
node _T_747 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_748 = eq(_T_747, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_749 = and(_T_746, _T_748) @[exu_div_ctl.scala 562:11]
node _T_750 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 577:82]
node _T_751 = eq(_T_750, UInt<1>("h00")) @[exu_div_ctl.scala 577:77]
node _T_752 = and(_T_749, _T_751) @[exu_div_ctl.scala 577:75]
node _T_753 = or(_T_743, _T_752) @[exu_div_ctl.scala 577:47]
node _T_754 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
node _T_755 = eq(_T_754, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_756 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_757 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_758 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_759 = and(_T_755, _T_756) @[exu_div_ctl.scala 560:95]
2 bit divider
2021-01-06 12:32:46 +08:00
node _T_760 = and(_T_759, _T_757) @[exu_div_ctl.scala 560:95]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_761 = and(_T_760, _T_758) @[exu_div_ctl.scala 560:95]
node _T_762 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_763 = eq(_T_762, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_764 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_765 = and(_T_763, _T_764) @[exu_div_ctl.scala 561:95]
node _T_766 = and(_T_761, _T_765) @[exu_div_ctl.scala 562:11]
node _T_767 = or(_T_753, _T_766) @[exu_div_ctl.scala 577:88]
node _T_768 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_769 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_770 = and(_T_768, _T_769) @[exu_div_ctl.scala 560:95]
node _T_771 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_772 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_773 = eq(_T_772, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_774 = and(_T_771, _T_773) @[exu_div_ctl.scala 561:95]
node _T_775 = and(_T_770, _T_774) @[exu_div_ctl.scala 562:11]
node _T_776 = or(_T_767, _T_775) @[exu_div_ctl.scala 577:131]
node _T_777 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_778 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_779 = and(_T_777, _T_778) @[exu_div_ctl.scala 560:95]
node _T_780 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_781 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_782 = eq(_T_781, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_783 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_784 = eq(_T_783, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_785 = and(_T_780, _T_782) @[exu_div_ctl.scala 561:95]
node _T_786 = and(_T_785, _T_784) @[exu_div_ctl.scala 561:95]
node _T_787 = and(_T_779, _T_786) @[exu_div_ctl.scala 562:11]
node _T_788 = or(_T_776, _T_787) @[exu_div_ctl.scala 578:47]
node _T_789 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_790 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_791 = and(_T_789, _T_790) @[exu_div_ctl.scala 560:95]
node _T_792 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_793 = eq(_T_792, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_794 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_795 = eq(_T_794, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_796 = and(_T_793, _T_795) @[exu_div_ctl.scala 561:95]
node _T_797 = and(_T_791, _T_796) @[exu_div_ctl.scala 562:11]
node _T_798 = or(_T_788, _T_797) @[exu_div_ctl.scala 578:88]
node _T_799 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_800 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:75]
node _T_801 = eq(_T_800, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_802 = and(_T_799, _T_801) @[exu_div_ctl.scala 560:95]
node _T_803 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_804 = eq(_T_803, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_805 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_806 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_807 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 561:58]
node _T_808 = and(_T_804, _T_805) @[exu_div_ctl.scala 561:95]
2 bit divider
2021-01-06 12:32:46 +08:00
node _T_809 = and(_T_808, _T_806) @[exu_div_ctl.scala 561:95]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_810 = and(_T_809, _T_807) @[exu_div_ctl.scala 561:95]
node _T_811 = and(_T_802, _T_810) @[exu_div_ctl.scala 562:11]
node _T_812 = or(_T_798, _T_811) @[exu_div_ctl.scala 578:131]
node _T_813 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_814 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_815 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_816 = and(_T_813, _T_814) @[exu_div_ctl.scala 560:95]
node _T_817 = and(_T_816, _T_815) @[exu_div_ctl.scala 560:95]
node _T_818 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_819 = and(_T_817, _T_818) @[exu_div_ctl.scala 562:11]
node _T_820 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 579:84]
node _T_821 = eq(_T_820, UInt<1>("h00")) @[exu_div_ctl.scala 579:79]
node _T_822 = and(_T_819, _T_821) @[exu_div_ctl.scala 579:77]
node _T_823 = or(_T_812, _T_822) @[exu_div_ctl.scala 579:47]
node _T_824 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_825 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_826 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_827 = and(_T_824, _T_825) @[exu_div_ctl.scala 560:95]
node _T_828 = and(_T_827, _T_826) @[exu_div_ctl.scala 560:95]
node _T_829 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_830 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_831 = eq(_T_830, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_832 = and(_T_829, _T_831) @[exu_div_ctl.scala 561:95]
node _T_833 = and(_T_828, _T_832) @[exu_div_ctl.scala 562:11]
node _T_834 = or(_T_823, _T_833) @[exu_div_ctl.scala 579:88]
node _T_835 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_836 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_837 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_838 = and(_T_835, _T_836) @[exu_div_ctl.scala 560:95]
node _T_839 = and(_T_838, _T_837) @[exu_div_ctl.scala 560:95]
node _T_840 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_841 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_842 = eq(_T_841, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_843 = and(_T_840, _T_842) @[exu_div_ctl.scala 561:95]
node _T_844 = and(_T_839, _T_843) @[exu_div_ctl.scala 562:11]
node _T_845 = or(_T_834, _T_844) @[exu_div_ctl.scala 579:131]
node _T_846 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_847 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
node _T_848 = eq(_T_847, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_849 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_850 = and(_T_846, _T_848) @[exu_div_ctl.scala 560:95]
node _T_851 = and(_T_850, _T_849) @[exu_div_ctl.scala 560:95]
node _T_852 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_853 = eq(_T_852, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_854 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_855 = and(_T_853, _T_854) @[exu_div_ctl.scala 561:95]
node _T_856 = and(_T_851, _T_855) @[exu_div_ctl.scala 562:11]
node _T_857 = or(_T_845, _T_856) @[exu_div_ctl.scala 580:47]
node _T_858 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_859 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_860 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_861 = and(_T_858, _T_859) @[exu_div_ctl.scala 560:95]
node _T_862 = and(_T_861, _T_860) @[exu_div_ctl.scala 560:95]
node _T_863 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_864 = eq(_T_863, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_865 = and(_T_862, _T_864) @[exu_div_ctl.scala 562:11]
node _T_866 = or(_T_857, _T_865) @[exu_div_ctl.scala 580:88]
node _T_867 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_868 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_869 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_870 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_871 = and(_T_867, _T_868) @[exu_div_ctl.scala 560:95]
2 bit divider
2021-01-06 12:32:46 +08:00
node _T_872 = and(_T_871, _T_869) @[exu_div_ctl.scala 560:95]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_873 = and(_T_872, _T_870) @[exu_div_ctl.scala 560:95]
node _T_874 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_875 = and(_T_873, _T_874) @[exu_div_ctl.scala 562:11]
node _T_876 = or(_T_866, _T_875) @[exu_div_ctl.scala 580:131]
node _T_877 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_878 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_879 = and(_T_877, _T_878) @[exu_div_ctl.scala 560:95]
node _T_880 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_881 = eq(_T_880, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_882 = and(_T_879, _T_881) @[exu_div_ctl.scala 562:11]
node _T_883 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 581:81]
node _T_884 = eq(_T_883, UInt<1>("h00")) @[exu_div_ctl.scala 581:76]
node _T_885 = and(_T_882, _T_884) @[exu_div_ctl.scala 581:74]
node _T_886 = or(_T_876, _T_885) @[exu_div_ctl.scala 581:47]
node _T_887 = cat(_T_575, _T_886) @[Cat.scala 29:58]
node _T_888 = cat(_T_441, _T_472) @[Cat.scala 29:58]
node _T_889 = cat(_T_888, _T_887) @[Cat.scala 29:58]
smallnum <= _T_889 @[exu_div_ctl.scala 564:12]
2 bit divider
2021-01-06 12:32:46 +08:00
node shortq_dividend = cat(dividend_sign_ff, a_ff) @[Cat.scala 29:58]
inst a_enc of exu_div_cls @[exu_div_ctl.scala 584:21]
a_enc.clock <= clock
a_enc.reset <= reset
a_enc.io.operand <= shortq_dividend @[exu_div_ctl.scala 585:20]
inst b_enc of exu_div_cls_1 @[exu_div_ctl.scala 587:21]
b_enc.clock <= clock
b_enc.reset <= reset
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_890 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 588:27]
b_enc.io.operand <= _T_890 @[exu_div_ctl.scala 588:20]
2 bit divider
2021-01-06 12:32:46 +08:00
node dw_a_enc = cat(UInt<1>("h00"), a_enc.io.cls) @[Cat.scala 29:58]
node dw_b_enc = cat(UInt<1>("h00"), b_enc.io.cls) @[Cat.scala 29:58]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_891 = cat(UInt<1>("h00"), dw_b_enc) @[Cat.scala 29:58]
node _T_892 = cat(UInt<1>("h00"), dw_a_enc) @[Cat.scala 29:58]
node _T_893 = sub(_T_891, _T_892) @[exu_div_ctl.scala 592:41]
node _T_894 = tail(_T_893, 1) @[exu_div_ctl.scala 592:41]
node _T_895 = add(_T_894, UInt<7>("h01")) @[exu_div_ctl.scala 592:61]
node dw_shortq_raw = tail(_T_895, 1) @[exu_div_ctl.scala 592:61]
node _T_896 = bits(dw_shortq_raw, 6, 6) @[exu_div_ctl.scala 593:33]
node _T_897 = bits(_T_896, 0, 0) @[exu_div_ctl.scala 593:43]
node _T_898 = bits(dw_shortq_raw, 5, 0) @[exu_div_ctl.scala 593:63]
node shortq = mux(_T_897, UInt<1>("h00"), _T_898) @[exu_div_ctl.scala 593:19]
node _T_899 = bits(shortq, 5, 5) @[exu_div_ctl.scala 594:38]
node _T_900 = eq(_T_899, UInt<1>("h00")) @[exu_div_ctl.scala 594:31]
node _T_901 = and(valid_ff, _T_900) @[exu_div_ctl.scala 594:29]
node _T_902 = bits(shortq, 4, 1) @[exu_div_ctl.scala 594:52]
node _T_903 = eq(_T_902, UInt<4>("h0f")) @[exu_div_ctl.scala 594:58]
node _T_904 = eq(_T_903, UInt<1>("h00")) @[exu_div_ctl.scala 594:44]
node _T_905 = and(_T_901, _T_904) @[exu_div_ctl.scala 594:42]
node _T_906 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 594:76]
node _T_907 = and(_T_905, _T_906) @[exu_div_ctl.scala 594:74]
shortq_enable <= _T_907 @[exu_div_ctl.scala 594:17]
node _T_908 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 595:26]
node _T_909 = bits(shortq, 4, 0) @[exu_div_ctl.scala 595:65]
node _T_910 = sub(UInt<5>("h01f"), _T_909) @[exu_div_ctl.scala 595:57]
node _T_911 = tail(_T_910, 1) @[exu_div_ctl.scala 595:57]
node shortq_shift = mux(_T_908, UInt<1>("h00"), _T_911) @[exu_div_ctl.scala 595:25]
node _T_912 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 596:20]
node _T_913 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 596:30]
node _T_914 = cat(_T_912, _T_913) @[Cat.scala 29:58]
node _T_915 = cat(_T_914, b_ff1) @[Cat.scala 29:58]
b_ff <= _T_915 @[exu_div_ctl.scala 596:8]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 392:18]
rvclkhdr.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
quotient new changed
2021-01-06 13:05:37 +08:00
reg _T_916 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when misc_enable : @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
_T_916 <= valid_ff_in @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
valid_ff <= _T_916 @[exu_div_ctl.scala 597:12]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_1.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
quotient new changed
2021-01-06 13:05:37 +08:00
reg _T_917 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when misc_enable : @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
_T_917 <= control_in @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
control_ff <= _T_917 @[exu_div_ctl.scala 598:16]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_2.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
quotient new changed
2021-01-06 13:05:37 +08:00
reg _T_918 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when misc_enable : @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
_T_918 <= by_zero_case @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
by_zero_case_ff <= _T_918 @[exu_div_ctl.scala 599:19]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 390:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_3.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
quotient new changed
2021-01-06 13:05:37 +08:00
reg _T_919 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when misc_enable : @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
_T_919 <= shortq_enable @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
shortq_enable_ff <= _T_919 @[exu_div_ctl.scala 600:20]
node _T_920 = bits(shortq_shift, 4, 1) @[exu_div_ctl.scala 601:41]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 390:23]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_4.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
quotient new changed
2021-01-06 13:05:37 +08:00
reg _T_921 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when misc_enable : @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
_T_921 <= _T_920 @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
shortq_shift_ff <= _T_921 @[exu_div_ctl.scala 601:19]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 390:23]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_5.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
quotient new changed
2021-01-06 13:05:37 +08:00
reg _T_922 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when misc_enable : @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
_T_922 <= finish @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
finish_ff <= _T_922 @[exu_div_ctl.scala 602:13]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 390:23]
rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_6.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
quotient new changed
2021-01-06 13:05:37 +08:00
reg _T_923 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when misc_enable : @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
_T_923 <= count_in @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
count_ff <= _T_923 @[exu_div_ctl.scala 603:12]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 390:23]
rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_7.io.en <= a_enable @[lib.scala 393:17]
rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
quotient new changed
2021-01-06 13:05:37 +08:00
reg _T_924 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when a_enable : @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
_T_924 <= a_in @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
a_ff <= _T_924 @[exu_div_ctl.scala 605:8]
node _T_925 = bits(b_in, 32, 0) @[exu_div_ctl.scala 606:23]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 390:23]
rvclkhdr_8.clock <= clock
rvclkhdr_8.reset <= reset
rvclkhdr_8.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_8.io.en <= b_enable @[lib.scala 393:17]
rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
quotient new changed
2021-01-06 13:05:37 +08:00
reg _T_926 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when b_enable : @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
_T_926 <= _T_925 @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
b_ff1 <= _T_926 @[exu_div_ctl.scala 606:9]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 390:23]
rvclkhdr_9.clock <= clock
rvclkhdr_9.reset <= reset
rvclkhdr_9.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_9.io.en <= rq_enable @[lib.scala 393:17]
rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
quotient new changed
2021-01-06 13:05:37 +08:00
reg _T_927 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when rq_enable : @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
_T_927 <= r_in @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
r_ff <= _T_927 @[exu_div_ctl.scala 607:8]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 390:23]
rvclkhdr_10.clock <= clock
rvclkhdr_10.reset <= reset
rvclkhdr_10.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_10.io.en <= rq_enable @[lib.scala 393:17]
rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
quotient new changed
2021-01-06 13:05:37 +08:00
reg _T_928 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when rq_enable : @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
_T_928 <= q_in @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
quotient new changed
2021-01-06 13:05:37 +08:00
q_ff <= _T_928 @[exu_div_ctl.scala 608:8]
2 bit divider
2021-01-06 12:32:46 +08:00