2021-01-28 20:36:33 +08:00
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn",
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"sources":[
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"~lsu|lsu>io_axi_ar_ready",
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"~lsu|lsu>io_axi_aw_ready",
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"~lsu|lsu>io_axi_w_ready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_pic_picm_mken",
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"sources":[
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"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
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"~lsu|lsu>io_dec_lsu_valid_raw_d",
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"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
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"~lsu|lsu>io_dec_lsu_offset_d",
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"~lsu|lsu>io_lsu_p_bits_dword",
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"~lsu|lsu>io_lsu_p_bits_half",
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"~lsu|lsu>io_lsu_p_bits_word",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
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"~lsu|lsu>io_lsu_p_valid",
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"~lsu|lsu>io_dec_tlu_flush_lower_r",
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"~lsu|lsu>io_lsu_p_bits_fast_int",
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"~lsu|lsu>io_lsu_p_bits_store",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
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"~lsu|lsu>io_dec_tlu_force_halt",
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"~lsu|lsu>io_lsu_pic_picm_rd_data",
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"~lsu|lsu>io_dccm_rd_data_hi",
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"~lsu|lsu>io_dccm_rd_data_lo",
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"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
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"~lsu|lsu>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_single_ecc_error_incr",
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"sources":[
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"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
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"~lsu|lsu>io_dec_tlu_core_ecc_disable",
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"~lsu|lsu>io_dccm_rd_data_hi",
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"~lsu|lsu>io_dccm_rd_data_lo"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_dma_dccm_ready",
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"sources":[
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"~lsu|lsu>io_dec_lsu_valid_raw_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_trigger_match_m",
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"sources":[
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"~lsu|lsu>io_trigger_pkt_any_0_store",
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"~lsu|lsu>io_trigger_pkt_any_1_store",
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"~lsu|lsu>io_trigger_pkt_any_3_m",
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"~lsu|lsu>io_trigger_pkt_any_0_load",
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"~lsu|lsu>io_trigger_pkt_any_0_select",
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"~lsu|lsu>io_trigger_pkt_any_3_store",
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"~lsu|lsu>io_trigger_pkt_any_2_store",
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"~lsu|lsu>io_trigger_pkt_any_1_load",
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"~lsu|lsu>io_trigger_pkt_any_1_select",
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"~lsu|lsu>io_trigger_pkt_any_2_m",
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"~lsu|lsu>io_trigger_pkt_any_3_load",
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"~lsu|lsu>io_trigger_pkt_any_3_select",
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"~lsu|lsu>io_trigger_pkt_any_2_load",
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"~lsu|lsu>io_trigger_pkt_any_2_select",
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"~lsu|lsu>io_trigger_pkt_any_0_m",
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"~lsu|lsu>io_trigger_pkt_any_1_m",
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"~lsu|lsu>io_trigger_pkt_any_0_tdata2",
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"~lsu|lsu>io_trigger_pkt_any_0_match_pkt",
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"~lsu|lsu>io_trigger_pkt_any_1_tdata2",
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"~lsu|lsu>io_trigger_pkt_any_1_match_pkt",
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"~lsu|lsu>io_trigger_pkt_any_3_tdata2",
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"~lsu|lsu>io_trigger_pkt_any_3_match_pkt",
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"~lsu|lsu>io_trigger_pkt_any_2_tdata2",
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"~lsu|lsu>io_trigger_pkt_any_2_match_pkt",
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"~lsu|lsu>io_lsu_pic_picm_rd_data",
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"~lsu|lsu>io_dec_tlu_force_halt",
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"~lsu|lsu>io_dccm_rd_data_hi",
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"~lsu|lsu>io_dccm_rd_data_lo",
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"~lsu|lsu>io_dec_tlu_flush_lower_r",
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"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
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"~lsu|lsu>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_dccm_wren",
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"sources":[
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
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"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
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"~lsu|lsu>io_dec_lsu_valid_raw_d",
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"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
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"~lsu|lsu>io_dec_lsu_offset_d",
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"~lsu|lsu>io_lsu_p_bits_dword",
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"~lsu|lsu>io_lsu_p_bits_half",
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"~lsu|lsu>io_lsu_p_bits_word",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
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"~lsu|lsu>io_lsu_p_valid",
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"~lsu|lsu>io_dec_tlu_flush_lower_r",
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"~lsu|lsu>io_lsu_p_bits_fast_int",
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"~lsu|lsu>io_lsu_p_bits_load",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
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"~lsu|lsu>io_lsu_p_bits_store",
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"~lsu|lsu>io_dec_tlu_force_halt",
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"~lsu|lsu>io_lsu_pic_picm_rd_data",
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"~lsu|lsu>io_dccm_rd_data_hi",
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"~lsu|lsu>io_dccm_rd_data_lo",
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"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
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"~lsu|lsu>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy",
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"sources":[
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"~lsu|lsu>io_axi_ar_ready",
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"~lsu|lsu>io_axi_aw_ready",
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"~lsu|lsu>io_axi_w_ready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_dccm_wr_data_hi",
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"sources":[
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
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"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
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"~lsu|lsu>io_dec_lsu_valid_raw_d",
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"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
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"~lsu|lsu>io_dec_lsu_offset_d",
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"~lsu|lsu>io_lsu_p_bits_dword",
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"~lsu|lsu>io_lsu_p_bits_half",
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"~lsu|lsu>io_lsu_p_bits_word",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
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"~lsu|lsu>io_dec_tlu_force_halt",
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"~lsu|lsu>io_lsu_pic_picm_rd_data",
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"~lsu|lsu>io_dccm_rd_data_hi",
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"~lsu|lsu>io_dccm_rd_data_lo",
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"~lsu|lsu>io_dec_tlu_flush_lower_r",
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"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
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"~lsu|lsu>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_dccm_wr_addr_lo",
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"sources":[
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
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"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
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"~lsu|lsu>io_dec_lsu_valid_raw_d",
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"~lsu|lsu>io_dec_lsu_offset_d",
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"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
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"~lsu|lsu>io_lsu_p_bits_dword",
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"~lsu|lsu>io_lsu_p_bits_half",
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"~lsu|lsu>io_lsu_p_bits_word",
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"~lsu|lsu>io_dec_tlu_force_halt",
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"~lsu|lsu>io_lsu_pic_picm_rd_data",
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"~lsu|lsu>io_dccm_rd_data_hi",
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"~lsu|lsu>io_dccm_rd_data_lo",
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"~lsu|lsu>io_dec_tlu_flush_lower_r",
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"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
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"~lsu|lsu>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_store_stall_any",
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"sources":[
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"~lsu|lsu>io_dec_lsu_valid_raw_d",
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2021-01-29 19:38:05 +08:00
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"~lsu|lsu>io_dec_tlu_flush_lower_r",
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2021-01-28 20:36:33 +08:00
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"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
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"~lsu|lsu>io_dec_lsu_offset_d",
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"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
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"~lsu|lsu>io_lsu_p_bits_dword",
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"~lsu|lsu>io_lsu_p_bits_half",
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"~lsu|lsu>io_lsu_p_bits_word",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
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"~lsu|lsu>io_dec_tlu_force_halt",
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"~lsu|lsu>io_lsu_pic_picm_rd_data",
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"~lsu|lsu>io_dccm_rd_data_hi",
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"~lsu|lsu>io_dccm_rd_data_lo",
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"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
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"~lsu|lsu>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
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"sources":[
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"~lsu|lsu>io_lsu_pic_picm_rd_data",
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"~lsu|lsu>io_dec_tlu_core_ecc_disable",
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"~lsu|lsu>io_dccm_rd_data_hi",
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"~lsu|lsu>io_dccm_rd_data_lo",
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"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_dccm_wr_addr_hi",
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"sources":[
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
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"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
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"~lsu|lsu>io_dec_lsu_valid_raw_d",
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"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
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"~lsu|lsu>io_dec_lsu_offset_d",
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"~lsu|lsu>io_lsu_p_bits_dword",
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"~lsu|lsu>io_lsu_p_bits_half",
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"~lsu|lsu>io_lsu_p_bits_word",
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"~lsu|lsu>io_dec_tlu_force_halt",
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"~lsu|lsu>io_lsu_pic_picm_rd_data",
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"~lsu|lsu>io_dccm_rd_data_hi",
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"~lsu|lsu>io_dccm_rd_data_lo",
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"~lsu|lsu>io_dec_tlu_flush_lower_r",
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"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
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"~lsu|lsu>io_dec_tlu_core_ecc_disable"
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]
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},
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|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_fastint_stall_any",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_exu_lsu_result_m",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt",
|
|
|
|
|
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_dccm_rd_addr_hi",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_offset_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_dword",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_half",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_word",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt",
|
|
|
|
|
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_dccm_wr_data_lo",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
|
|
|
|
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_offset_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_dword",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_half",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_word",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt",
|
|
|
|
|
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_pic_picm_wren",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
|
|
|
|
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_offset_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_dword",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_half",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_word",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt",
|
|
|
|
|
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_pic_picm_rden",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_offset_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_dword",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_half",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_word",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_valid",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_fast_int",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt",
|
|
|
|
|
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_load_stall_any",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
2021-01-29 19:38:05 +08:00
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
2021-01-28 20:36:33 +08:00
|
|
|
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_offset_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_dword",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_half",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_word",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt",
|
|
|
|
|
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_dccm_rden",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_offset_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_dword",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_half",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_word",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_valid",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_fast_int",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_store",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt",
|
|
|
|
|
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_dccm_rd_addr_lo",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_offset_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt",
|
|
|
|
|
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_pic_picm_wr_data",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
|
|
|
|
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_offset_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_dword",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_half",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_word",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_valid",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_fast_int",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_store",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt",
|
|
|
|
|
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_pic_picm_wraddr",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
|
|
|
|
|
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_offset_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_dword",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_half",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_word",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt",
|
|
|
|
|
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_valid_raw_d",
|
|
|
|
|
"~lsu|lsu>io_dec_lsu_offset_d",
|
|
|
|
|
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt",
|
|
|
|
|
"~lsu|lsu>io_lsu_pic_picm_rd_data",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_hi",
|
|
|
|
|
"~lsu|lsu>io_dccm_rd_data_lo",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_core_ecc_disable"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.CombinationalPath",
|
|
|
|
|
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m",
|
|
|
|
|
"sources":[
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_flush_lower_r",
|
|
|
|
|
"~lsu|lsu>io_dec_tlu_force_halt"
|
|
|
|
|
]
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.EmitCircuitAnnotation",
|
|
|
|
|
"emitter":"firrtl.VerilogEmitter"
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
|
|
|
|
"target":"lsu.gated_latch",
|
|
|
|
|
"resourceId":"/vsrc/gated_latch.sv"
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.options.TargetDirAnnotation",
|
|
|
|
|
"directory":"."
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
|
|
|
|
"file":"lsu"
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
|
|
|
|
"targetDir":"."
|
|
|
|
|
}
|
|
|
|
|
]
|
