2021-01-27 14:46:11 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit dec :
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module dec_ib_ctl :
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input clock : Clock
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input reset : Reset
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output io : {flip ifu_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_second : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, flip ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dec_debug_valid_d : UInt<1>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, flip ifu_i0_fa_index : UInt<9>, dec_i0_bp_fa_index : UInt<9>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_second_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_fence_d : UInt<1>}
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io.dec_i0_icaf_second_d <= io.ifu_ib.ifu_i0_icaf_second @[dec_ib_ctl.scala 34:35]
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io.dec_i0_dbecc_d <= io.ifu_ib.ifu_i0_dbecc @[dec_ib_ctl.scala 35:31]
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io.dec_i0_icaf_d <= io.ifu_ib.ifu_i0_icaf @[dec_ib_ctl.scala 36:31]
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io.ib_exu.dec_i0_pc_d <= io.ifu_ib.ifu_i0_pc @[dec_ib_ctl.scala 37:31]
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io.dec_i0_pc4_d <= io.ifu_ib.ifu_i0_pc4 @[dec_ib_ctl.scala 38:31]
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io.dec_i0_icaf_type_d <= io.ifu_ib.ifu_i0_icaf_type @[dec_ib_ctl.scala 39:31]
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io.dec_i0_brp.bits.ret <= io.ifu_ib.i0_brp.bits.ret @[dec_ib_ctl.scala 40:31]
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io.dec_i0_brp.bits.way <= io.ifu_ib.i0_brp.bits.way @[dec_ib_ctl.scala 40:31]
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io.dec_i0_brp.bits.prett <= io.ifu_ib.i0_brp.bits.prett @[dec_ib_ctl.scala 40:31]
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io.dec_i0_brp.bits.bank <= io.ifu_ib.i0_brp.bits.bank @[dec_ib_ctl.scala 40:31]
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io.dec_i0_brp.bits.br_start_error <= io.ifu_ib.i0_brp.bits.br_start_error @[dec_ib_ctl.scala 40:31]
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io.dec_i0_brp.bits.br_error <= io.ifu_ib.i0_brp.bits.br_error @[dec_ib_ctl.scala 40:31]
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io.dec_i0_brp.bits.hist <= io.ifu_ib.i0_brp.bits.hist @[dec_ib_ctl.scala 40:31]
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io.dec_i0_brp.bits.toffset <= io.ifu_ib.i0_brp.bits.toffset @[dec_ib_ctl.scala 40:31]
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io.dec_i0_brp.valid <= io.ifu_ib.i0_brp.valid @[dec_ib_ctl.scala 40:31]
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io.dec_i0_bp_index <= io.ifu_ib.ifu_i0_bp_index @[dec_ib_ctl.scala 41:31]
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io.dec_i0_bp_fghr <= io.ifu_ib.ifu_i0_bp_fghr @[dec_ib_ctl.scala 42:31]
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io.dec_i0_bp_btag <= io.ifu_ib.ifu_i0_bp_btag @[dec_ib_ctl.scala 43:31]
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io.dec_i0_bp_fa_index <= io.ifu_i0_fa_index @[dec_ib_ctl.scala 44:25]
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node _T = neq(io.dbg_ib.dbg_cmd_type, UInt<2>("h02")) @[dec_ib_ctl.scala 58:74]
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node debug_valid = and(io.dbg_ib.dbg_cmd_valid, _T) @[dec_ib_ctl.scala 58:48]
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node _T_1 = eq(io.dbg_ib.dbg_cmd_write, UInt<1>("h00")) @[dec_ib_ctl.scala 59:38]
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node debug_read = and(debug_valid, _T_1) @[dec_ib_ctl.scala 59:36]
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node debug_write = and(debug_valid, io.dbg_ib.dbg_cmd_write) @[dec_ib_ctl.scala 60:36]
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io.dec_debug_valid_d <= debug_valid @[dec_ib_ctl.scala 61:24]
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node _T_2 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 62:62]
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node debug_read_gpr = and(debug_read, _T_2) @[dec_ib_ctl.scala 62:37]
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node _T_3 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 63:62]
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node debug_write_gpr = and(debug_write, _T_3) @[dec_ib_ctl.scala 63:37]
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node _T_4 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 64:62]
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node debug_read_csr = and(debug_read, _T_4) @[dec_ib_ctl.scala 64:37]
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node _T_5 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 65:62]
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node debug_write_csr = and(debug_write, _T_5) @[dec_ib_ctl.scala 65:37]
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node dreg = bits(io.dbg_ib.dbg_cmd_addr, 4, 0) @[dec_ib_ctl.scala 67:47]
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node dcsr = bits(io.dbg_ib.dbg_cmd_addr, 11, 0) @[dec_ib_ctl.scala 68:47]
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node _T_6 = bits(debug_read_gpr, 0, 0) @[dec_ib_ctl.scala 71:20]
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node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
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node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58]
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node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58]
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node _T_10 = bits(debug_write_gpr, 0, 0) @[dec_ib_ctl.scala 72:21]
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node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58]
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node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58]
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node _T_13 = bits(debug_read_csr, 0, 0) @[dec_ib_ctl.scala 73:20]
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node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58]
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node _T_15 = bits(debug_write_csr, 0, 0) @[dec_ib_ctl.scala 74:21]
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node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58]
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node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
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node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
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node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
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wire ib0_debug_in : UInt<32> @[Mux.scala 27:72]
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ib0_debug_in <= _T_23 @[Mux.scala 27:72]
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node _T_24 = or(debug_write_gpr, debug_write_csr) @[dec_ib_ctl.scala 78:54]
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io.ib_exu.dec_debug_wdata_rs1_d <= _T_24 @[dec_ib_ctl.scala 78:35]
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node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[dec_ib_ctl.scala 81:51]
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node _T_26 = and(debug_write_csr, _T_25) @[dec_ib_ctl.scala 81:43]
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io.dec_debug_fence_d <= _T_26 @[dec_ib_ctl.scala 81:24]
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node _T_27 = or(io.ifu_ib.ifu_i0_valid, debug_valid) @[dec_ib_ctl.scala 83:48]
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io.dec_ib0_valid_d <= _T_27 @[dec_ib_ctl.scala 83:22]
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node _T_28 = bits(debug_valid, 0, 0) @[dec_ib_ctl.scala 84:41]
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node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_ib.ifu_i0_instr) @[dec_ib_ctl.scala 84:28]
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io.dec_i0_instr_d <= _T_29 @[dec_ib_ctl.scala 84:22]
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module dec_dec_ctl :
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input clock : Clock
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input reset : Reset
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output io : {flip ins : UInt<32>, out : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}}
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node _T = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
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node _T_1 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
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node _T_2 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34]
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node _T_3 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
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node _T_4 = eq(_T_3, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_5 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
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node _T_6 = eq(_T_5, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_7 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
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node _T_8 = eq(_T_7, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_9 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
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node _T_10 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
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node _T_11 = eq(_T_10, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_12 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
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node _T_13 = and(_T, _T_1) @[dec_dec_ctl.scala 17:17]
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node _T_14 = and(_T_13, _T_2) @[dec_dec_ctl.scala 17:17]
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node _T_15 = and(_T_14, _T_4) @[dec_dec_ctl.scala 17:17]
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node _T_16 = and(_T_15, _T_6) @[dec_dec_ctl.scala 17:17]
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node _T_17 = and(_T_16, _T_8) @[dec_dec_ctl.scala 17:17]
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node _T_18 = and(_T_17, _T_9) @[dec_dec_ctl.scala 17:17]
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node _T_19 = and(_T_18, _T_11) @[dec_dec_ctl.scala 17:17]
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node _T_20 = and(_T_19, _T_12) @[dec_dec_ctl.scala 17:17]
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node _T_21 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
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node _T_22 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
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node _T_23 = eq(_T_22, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_24 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
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node _T_25 = eq(_T_24, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_26 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
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node _T_27 = and(_T_21, _T_23) @[dec_dec_ctl.scala 17:17]
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node _T_28 = and(_T_27, _T_25) @[dec_dec_ctl.scala 17:17]
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node _T_29 = and(_T_28, _T_26) @[dec_dec_ctl.scala 17:17]
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node _T_30 = or(_T_20, _T_29) @[dec_dec_ctl.scala 20:62]
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node _T_31 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
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node _T_32 = eq(_T_31, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_33 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
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node _T_34 = eq(_T_33, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_35 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
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node _T_36 = eq(_T_35, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_37 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
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node _T_38 = and(_T_32, _T_34) @[dec_dec_ctl.scala 17:17]
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node _T_39 = and(_T_38, _T_36) @[dec_dec_ctl.scala 17:17]
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node _T_40 = and(_T_39, _T_37) @[dec_dec_ctl.scala 17:17]
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node _T_41 = or(_T_30, _T_40) @[dec_dec_ctl.scala 20:92]
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node _T_42 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
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node _T_43 = eq(_T_42, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_44 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
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node _T_45 = eq(_T_44, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
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node _T_46 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
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node _T_47 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
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node _T_48 = and(_T_43, _T_45) @[dec_dec_ctl.scala 17:17]
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node _T_49 = and(_T_48, _T_46) @[dec_dec_ctl.scala 17:17]
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node _T_50 = and(_T_49, _T_47) @[dec_dec_ctl.scala 17:17]
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node _T_51 = or(_T_41, _T_50) @[dec_dec_ctl.scala 21:34]
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node _T_52 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
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node _T_53 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
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node _T_54 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
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node _T_55 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
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node _T_56 = and(_T_52, _T_53) @[dec_dec_ctl.scala 17:17]
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node _T_57 = and(_T_56, _T_54) @[dec_dec_ctl.scala 17:17]
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node _T_58 = and(_T_57, _T_55) @[dec_dec_ctl.scala 17:17]
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node _T_59 = or(_T_51, _T_58) @[dec_dec_ctl.scala 21:66]
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node _T_60 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
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node _T_61 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
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node _T_62 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_63 = eq(_T_62, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_64 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_65 = and(_T_60, _T_61) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_66 = and(_T_65, _T_63) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_67 = and(_T_66, _T_64) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_68 = or(_T_59, _T_67) @[dec_dec_ctl.scala 21:94]
|
|
|
|
|
node _T_69 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_70 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_71 = eq(_T_70, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_72 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_73 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_74 = and(_T_69, _T_71) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_75 = and(_T_74, _T_72) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_76 = and(_T_75, _T_73) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_77 = or(_T_68, _T_76) @[dec_dec_ctl.scala 22:32]
|
|
|
|
|
node _T_78 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_79 = eq(_T_78, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_80 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_81 = eq(_T_80, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_82 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_83 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_84 = and(_T_79, _T_81) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_85 = and(_T_84, _T_82) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_86 = and(_T_85, _T_83) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_87 = or(_T_77, _T_86) @[dec_dec_ctl.scala 22:60]
|
|
|
|
|
node _T_88 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_89 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_90 = eq(_T_89, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_91 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_93 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_94 = and(_T_88, _T_90) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_95 = and(_T_94, _T_92) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_96 = and(_T_95, _T_93) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_97 = or(_T_87, _T_96) @[dec_dec_ctl.scala 22:90]
|
|
|
|
|
node _T_98 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_99 = eq(_T_98, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_100 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_101 = eq(_T_100, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_102 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_103 = eq(_T_102, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_104 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_105 = and(_T_99, _T_101) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_106 = and(_T_105, _T_103) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_107 = and(_T_106, _T_104) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_108 = or(_T_97, _T_107) @[dec_dec_ctl.scala 23:33]
|
|
|
|
|
node _T_109 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_110 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_111 = eq(_T_110, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_112 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_113 = and(_T_109, _T_111) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_114 = and(_T_113, _T_112) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_115 = or(_T_108, _T_114) @[dec_dec_ctl.scala 23:64]
|
|
|
|
|
node _T_116 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_117 = eq(_T_116, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_118 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_119 = eq(_T_118, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_120 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_121 = and(_T_117, _T_119) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_122 = and(_T_121, _T_120) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_123 = or(_T_115, _T_122) @[dec_dec_ctl.scala 23:89]
|
|
|
|
|
node _T_124 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_125 = or(_T_123, _T_124) @[dec_dec_ctl.scala 24:29]
|
|
|
|
|
node _T_126 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_127 = or(_T_125, _T_126) @[dec_dec_ctl.scala 24:48]
|
|
|
|
|
node _T_128 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_129 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_130 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_131 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_132 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_133 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_134 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_135 = eq(_T_134, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_136 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_137 = and(_T_128, _T_129) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_138 = and(_T_137, _T_130) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_139 = and(_T_138, _T_131) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_140 = and(_T_139, _T_132) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_141 = and(_T_140, _T_133) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_142 = and(_T_141, _T_135) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_143 = and(_T_142, _T_136) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_144 = or(_T_127, _T_143) @[dec_dec_ctl.scala 24:67]
|
|
|
|
|
node _T_145 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_146 = eq(_T_145, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_147 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_148 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_149 = eq(_T_148, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_150 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_151 = eq(_T_150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_152 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_153 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_154 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_155 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_156 = eq(_T_155, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_157 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_158 = and(_T_146, _T_147) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_159 = and(_T_158, _T_149) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_160 = and(_T_159, _T_151) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_161 = and(_T_160, _T_152) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_162 = and(_T_161, _T_153) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_163 = and(_T_162, _T_154) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_164 = and(_T_163, _T_156) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_165 = and(_T_164, _T_157) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_166 = or(_T_144, _T_165) @[dec_dec_ctl.scala 24:107]
|
|
|
|
|
node _T_167 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_169 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_170 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_171 = eq(_T_170, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_172 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_173 = eq(_T_172, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_174 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_175 = eq(_T_174, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_176 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_177 = eq(_T_176, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_178 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_180 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_181 = and(_T_168, _T_169) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_182 = and(_T_181, _T_171) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_183 = and(_T_182, _T_173) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_184 = and(_T_183, _T_175) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_185 = and(_T_184, _T_177) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_186 = and(_T_185, _T_179) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_187 = and(_T_186, _T_180) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_188 = or(_T_166, _T_187) @[dec_dec_ctl.scala 25:49]
|
|
|
|
|
io.out.alu <= _T_188 @[dec_dec_ctl.scala 20:14]
|
|
|
|
|
node _T_189 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_190 = eq(_T_189, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_191 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_192 = eq(_T_191, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_193 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_194 = eq(_T_193, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_195 = and(_T_190, _T_192) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_196 = and(_T_195, _T_194) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_197 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_198 = eq(_T_197, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_199 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_200 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_201 = eq(_T_200, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_202 = and(_T_198, _T_199) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_203 = and(_T_202, _T_201) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_204 = or(_T_196, _T_203) @[dec_dec_ctl.scala 27:43]
|
|
|
|
|
node _T_205 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_206 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_207 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_208 = eq(_T_207, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_209 = and(_T_205, _T_206) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_210 = and(_T_209, _T_208) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_211 = or(_T_204, _T_210) @[dec_dec_ctl.scala 27:70]
|
|
|
|
|
node _T_212 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_213 = eq(_T_212, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_214 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_215 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_217 = and(_T_213, _T_214) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_218 = and(_T_217, _T_216) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_219 = or(_T_211, _T_218) @[dec_dec_ctl.scala 27:96]
|
|
|
|
|
node _T_220 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_221 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_222 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_223 = eq(_T_222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_224 = and(_T_220, _T_221) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_225 = and(_T_224, _T_223) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_226 = or(_T_219, _T_225) @[dec_dec_ctl.scala 28:30]
|
|
|
|
|
node _T_227 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_228 = eq(_T_227, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_229 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_230 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_231 = eq(_T_230, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_232 = and(_T_228, _T_229) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_233 = and(_T_232, _T_231) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_234 = or(_T_226, _T_233) @[dec_dec_ctl.scala 28:57]
|
|
|
|
|
node _T_235 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_236 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_237 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_238 = eq(_T_237, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_239 = and(_T_235, _T_236) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_240 = and(_T_239, _T_238) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_241 = or(_T_234, _T_240) @[dec_dec_ctl.scala 28:83]
|
|
|
|
|
node _T_242 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_243 = eq(_T_242, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_244 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_245 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_246 = eq(_T_245, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_247 = and(_T_243, _T_244) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_248 = and(_T_247, _T_246) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_249 = or(_T_241, _T_248) @[dec_dec_ctl.scala 28:109]
|
|
|
|
|
node _T_250 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_251 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_252 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_254 = and(_T_250, _T_251) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_255 = and(_T_254, _T_253) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_256 = or(_T_249, _T_255) @[dec_dec_ctl.scala 29:29]
|
|
|
|
|
node _T_257 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_258 = eq(_T_257, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_259 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_260 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_261 = eq(_T_260, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_262 = and(_T_258, _T_259) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_263 = and(_T_262, _T_261) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_264 = or(_T_256, _T_263) @[dec_dec_ctl.scala 29:55]
|
|
|
|
|
node _T_265 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_266 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_267 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_268 = eq(_T_267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_269 = and(_T_265, _T_266) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_270 = and(_T_269, _T_268) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_271 = or(_T_264, _T_270) @[dec_dec_ctl.scala 29:81]
|
|
|
|
|
node _T_272 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_273 = eq(_T_272, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_274 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_275 = eq(_T_274, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_276 = and(_T_273, _T_275) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_277 = or(_T_271, _T_276) @[dec_dec_ctl.scala 30:29]
|
|
|
|
|
node _T_278 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_279 = eq(_T_278, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_280 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_281 = eq(_T_280, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_282 = and(_T_279, _T_281) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_283 = or(_T_277, _T_282) @[dec_dec_ctl.scala 30:52]
|
|
|
|
|
io.out.rs1 <= _T_283 @[dec_dec_ctl.scala 27:14]
|
|
|
|
|
node _T_284 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_285 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_286 = eq(_T_285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_287 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_288 = eq(_T_287, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_289 = and(_T_284, _T_286) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_290 = and(_T_289, _T_288) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_291 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_292 = eq(_T_291, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_293 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_294 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_295 = eq(_T_294, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_296 = and(_T_292, _T_293) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_297 = and(_T_296, _T_295) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_298 = or(_T_290, _T_297) @[dec_dec_ctl.scala 32:40]
|
|
|
|
|
io.out.rs2 <= _T_298 @[dec_dec_ctl.scala 32:14]
|
|
|
|
|
node _T_299 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_300 = eq(_T_299, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_301 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_302 = eq(_T_301, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_303 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_304 = and(_T_300, _T_302) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_305 = and(_T_304, _T_303) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_306 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_307 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_308 = eq(_T_307, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_309 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_310 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_311 = eq(_T_310, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_312 = and(_T_306, _T_308) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_313 = and(_T_312, _T_309) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_314 = and(_T_313, _T_311) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_315 = or(_T_305, _T_314) @[dec_dec_ctl.scala 34:42]
|
|
|
|
|
node _T_316 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_317 = eq(_T_316, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_318 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_319 = eq(_T_318, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_320 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_321 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_322 = and(_T_317, _T_319) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_323 = and(_T_322, _T_320) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_324 = and(_T_323, _T_321) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_325 = or(_T_315, _T_324) @[dec_dec_ctl.scala 34:70]
|
|
|
|
|
node _T_326 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_328 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_330 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_331 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_332 = eq(_T_331, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_333 = and(_T_327, _T_329) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_334 = and(_T_333, _T_330) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_335 = and(_T_334, _T_332) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_336 = or(_T_325, _T_335) @[dec_dec_ctl.scala 34:99]
|
|
|
|
|
io.out.imm12 <= _T_336 @[dec_dec_ctl.scala 34:16]
|
|
|
|
|
node _T_337 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_339 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_340 = eq(_T_339, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_341 = and(_T_338, _T_340) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_342 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_343 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_344 = and(_T_342, _T_343) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_345 = or(_T_341, _T_344) @[dec_dec_ctl.scala 36:37]
|
|
|
|
|
node _T_346 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_347 = or(_T_345, _T_346) @[dec_dec_ctl.scala 36:58]
|
|
|
|
|
io.out.rd <= _T_347 @[dec_dec_ctl.scala 36:13]
|
|
|
|
|
node _T_348 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_349 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_350 = eq(_T_349, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_351 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_352 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_354 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_355 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_356 = eq(_T_355, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_357 = and(_T_348, _T_350) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_358 = and(_T_357, _T_351) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_359 = and(_T_358, _T_353) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_360 = and(_T_359, _T_354) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_361 = and(_T_360, _T_356) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_362 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_363 = eq(_T_362, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_364 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_365 = eq(_T_364, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_366 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_367 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_369 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_370 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_371 = eq(_T_370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_372 = and(_T_363, _T_365) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_373 = and(_T_372, _T_366) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_374 = and(_T_373, _T_368) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_375 = and(_T_374, _T_369) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_376 = and(_T_375, _T_371) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_377 = or(_T_361, _T_376) @[dec_dec_ctl.scala 38:53]
|
|
|
|
|
node _T_378 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_379 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_380 = eq(_T_379, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_381 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_382 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_383 = eq(_T_382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_384 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_385 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_387 = and(_T_378, _T_380) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_388 = and(_T_387, _T_381) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_389 = and(_T_388, _T_383) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_390 = and(_T_389, _T_384) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_391 = and(_T_390, _T_386) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_392 = or(_T_377, _T_391) @[dec_dec_ctl.scala 38:89]
|
|
|
|
|
io.out.shimm5 <= _T_392 @[dec_dec_ctl.scala 38:17]
|
|
|
|
|
node _T_393 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_394 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_395 = and(_T_393, _T_394) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_396 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_397 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_398 = and(_T_396, _T_397) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_399 = or(_T_395, _T_398) @[dec_dec_ctl.scala 40:38]
|
|
|
|
|
io.out.imm20 <= _T_399 @[dec_dec_ctl.scala 40:16]
|
|
|
|
|
node _T_400 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_401 = eq(_T_400, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_402 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_403 = eq(_T_402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_404 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_405 = and(_T_401, _T_403) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_406 = and(_T_405, _T_404) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_407 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_408 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_409 = and(_T_407, _T_408) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_410 = or(_T_406, _T_409) @[dec_dec_ctl.scala 42:39]
|
|
|
|
|
io.out.pc <= _T_410 @[dec_dec_ctl.scala 42:13]
|
|
|
|
|
node _T_411 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_412 = eq(_T_411, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_413 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_414 = eq(_T_413, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_415 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_416 = eq(_T_415, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_417 = and(_T_412, _T_414) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_418 = and(_T_417, _T_416) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.load <= _T_418 @[dec_dec_ctl.scala 44:15]
|
|
|
|
|
node _T_419 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_420 = eq(_T_419, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_421 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_422 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_424 = and(_T_420, _T_421) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_425 = and(_T_424, _T_423) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.store <= _T_425 @[dec_dec_ctl.scala 46:16]
|
|
|
|
|
node _T_426 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_427 = eq(_T_426, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_428 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_429 = eq(_T_428, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_430 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_431 = eq(_T_430, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_432 = and(_T_427, _T_429) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_433 = and(_T_432, _T_431) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.lsu <= _T_433 @[dec_dec_ctl.scala 48:14]
|
|
|
|
|
node _T_434 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_436 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_438 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_439 = eq(_T_438, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_440 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_441 = eq(_T_440, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_442 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_443 = and(_T_435, _T_437) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_444 = and(_T_443, _T_439) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_445 = and(_T_444, _T_441) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_446 = and(_T_445, _T_442) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_447 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_448 = eq(_T_447, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_449 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_450 = eq(_T_449, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_451 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_452 = and(_T_448, _T_450) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_453 = and(_T_452, _T_451) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_454 = or(_T_446, _T_453) @[dec_dec_ctl.scala 50:49]
|
|
|
|
|
node _T_455 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_457 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_458 = eq(_T_457, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_459 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_460 = eq(_T_459, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_461 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_462 = eq(_T_461, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_463 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_464 = eq(_T_463, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_465 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_466 = eq(_T_465, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_467 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_468 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_470 = and(_T_456, _T_458) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_471 = and(_T_470, _T_460) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_472 = and(_T_471, _T_462) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_473 = and(_T_472, _T_464) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_474 = and(_T_473, _T_466) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_475 = and(_T_474, _T_467) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_476 = and(_T_475, _T_469) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_477 = or(_T_454, _T_476) @[dec_dec_ctl.scala 50:74]
|
|
|
|
|
io.out.add <= _T_477 @[dec_dec_ctl.scala 50:14]
|
|
|
|
|
node _T_478 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_479 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_480 = eq(_T_479, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_481 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_482 = eq(_T_481, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_483 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_485 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_486 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_487 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_489 = and(_T_478, _T_480) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_490 = and(_T_489, _T_482) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_491 = and(_T_490, _T_484) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_492 = and(_T_491, _T_485) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_493 = and(_T_492, _T_486) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_494 = and(_T_493, _T_488) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_495 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_496 = eq(_T_495, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_497 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_498 = eq(_T_497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_499 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_500 = eq(_T_499, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_501 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_502 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_503 = eq(_T_502, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_504 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_505 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_506 = eq(_T_505, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_507 = and(_T_496, _T_498) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_508 = and(_T_507, _T_500) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_509 = and(_T_508, _T_501) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_510 = and(_T_509, _T_503) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_511 = and(_T_510, _T_504) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_512 = and(_T_511, _T_506) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_513 = or(_T_494, _T_512) @[dec_dec_ctl.scala 52:53]
|
|
|
|
|
node _T_514 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_515 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_516 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_517 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_518 = eq(_T_517, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_519 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_520 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_521 = eq(_T_520, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_522 = and(_T_514, _T_515) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_523 = and(_T_522, _T_516) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_524 = and(_T_523, _T_518) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_525 = and(_T_524, _T_519) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_526 = and(_T_525, _T_521) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_527 = or(_T_513, _T_526) @[dec_dec_ctl.scala 52:93]
|
|
|
|
|
node _T_528 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_529 = eq(_T_528, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_530 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_531 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_533 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_534 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_535 = eq(_T_534, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_536 = and(_T_529, _T_530) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_537 = and(_T_536, _T_532) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_538 = and(_T_537, _T_533) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_539 = and(_T_538, _T_535) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_540 = or(_T_527, _T_539) @[dec_dec_ctl.scala 53:37]
|
|
|
|
|
node _T_541 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_542 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_543 = eq(_T_542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_544 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_545 = eq(_T_544, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_546 = and(_T_541, _T_543) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_547 = and(_T_546, _T_545) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_548 = or(_T_540, _T_547) @[dec_dec_ctl.scala 53:69]
|
|
|
|
|
io.out.sub <= _T_548 @[dec_dec_ctl.scala 52:14]
|
|
|
|
|
node _T_549 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_550 = eq(_T_549, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_551 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_552 = eq(_T_551, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_553 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_554 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_555 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_556 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_557 = eq(_T_556, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_558 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_560 = and(_T_550, _T_552) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_561 = and(_T_560, _T_553) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_562 = and(_T_561, _T_554) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_563 = and(_T_562, _T_555) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_564 = and(_T_563, _T_557) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_565 = and(_T_564, _T_559) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_566 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_567 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_568 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_569 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_570 = eq(_T_569, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_571 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_572 = eq(_T_571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_573 = and(_T_566, _T_567) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_574 = and(_T_573, _T_568) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_575 = and(_T_574, _T_570) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_576 = and(_T_575, _T_572) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_577 = or(_T_565, _T_576) @[dec_dec_ctl.scala 55:56]
|
|
|
|
|
io.out.land <= _T_577 @[dec_dec_ctl.scala 55:15]
|
|
|
|
|
node _T_578 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_579 = eq(_T_578, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_580 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_581 = and(_T_579, _T_580) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_582 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_583 = eq(_T_582, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_584 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_585 = eq(_T_584, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_586 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_587 = eq(_T_586, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_588 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_589 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_590 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_591 = eq(_T_590, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_592 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_593 = eq(_T_592, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_594 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_595 = eq(_T_594, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_596 = and(_T_583, _T_585) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_597 = and(_T_596, _T_587) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_598 = and(_T_597, _T_588) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_599 = and(_T_598, _T_589) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_600 = and(_T_599, _T_591) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_601 = and(_T_600, _T_593) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_602 = and(_T_601, _T_595) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_603 = or(_T_581, _T_602) @[dec_dec_ctl.scala 57:37]
|
|
|
|
|
node _T_604 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_605 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_606 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_607 = and(_T_604, _T_605) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_608 = and(_T_607, _T_606) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_609 = or(_T_603, _T_608) @[dec_dec_ctl.scala 57:82]
|
|
|
|
|
node _T_610 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_611 = eq(_T_610, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_612 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_613 = eq(_T_612, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_614 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_615 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_616 = and(_T_611, _T_613) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_617 = and(_T_616, _T_614) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_618 = and(_T_617, _T_615) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_619 = or(_T_609, _T_618) @[dec_dec_ctl.scala 57:105]
|
|
|
|
|
node _T_620 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_621 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_622 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_623 = eq(_T_622, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_624 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_625 = eq(_T_624, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_626 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_627 = eq(_T_626, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_628 = and(_T_620, _T_621) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_629 = and(_T_628, _T_623) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_630 = and(_T_629, _T_625) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_631 = and(_T_630, _T_627) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_632 = or(_T_619, _T_631) @[dec_dec_ctl.scala 58:32]
|
|
|
|
|
io.out.lor <= _T_632 @[dec_dec_ctl.scala 57:14]
|
|
|
|
|
node _T_633 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_634 = eq(_T_633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_635 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_636 = eq(_T_635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_637 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_638 = eq(_T_637, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_639 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_640 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_641 = eq(_T_640, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_642 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_643 = eq(_T_642, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_644 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_645 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_647 = and(_T_634, _T_636) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_648 = and(_T_647, _T_638) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_649 = and(_T_648, _T_639) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_650 = and(_T_649, _T_641) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_651 = and(_T_650, _T_643) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_652 = and(_T_651, _T_644) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_653 = and(_T_652, _T_646) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_654 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_655 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_656 = eq(_T_655, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_657 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_658 = eq(_T_657, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_659 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_660 = eq(_T_659, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_661 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_662 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_663 = eq(_T_662, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_664 = and(_T_654, _T_656) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_665 = and(_T_664, _T_658) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_666 = and(_T_665, _T_660) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_667 = and(_T_666, _T_661) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_668 = and(_T_667, _T_663) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_669 = or(_T_653, _T_668) @[dec_dec_ctl.scala 60:61]
|
|
|
|
|
io.out.lxor <= _T_669 @[dec_dec_ctl.scala 60:15]
|
|
|
|
|
node _T_670 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_671 = eq(_T_670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_672 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_673 = eq(_T_672, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_674 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_675 = eq(_T_674, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_676 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_677 = eq(_T_676, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_678 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_679 = eq(_T_678, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_680 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_681 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_682 = eq(_T_681, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_683 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_684 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_685 = eq(_T_684, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_686 = and(_T_671, _T_673) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_687 = and(_T_686, _T_675) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_688 = and(_T_687, _T_677) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_689 = and(_T_688, _T_679) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_690 = and(_T_689, _T_680) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_691 = and(_T_690, _T_682) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_692 = and(_T_691, _T_683) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_693 = and(_T_692, _T_685) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sll <= _T_693 @[dec_dec_ctl.scala 62:14]
|
|
|
|
|
node _T_694 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_695 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_696 = eq(_T_695, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_697 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_698 = eq(_T_697, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_699 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_700 = eq(_T_699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_701 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_702 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_703 = eq(_T_702, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_704 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_705 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_707 = and(_T_694, _T_696) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_708 = and(_T_707, _T_698) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_709 = and(_T_708, _T_700) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_710 = and(_T_709, _T_701) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_711 = and(_T_710, _T_703) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_712 = and(_T_711, _T_704) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_713 = and(_T_712, _T_706) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sra <= _T_713 @[dec_dec_ctl.scala 64:14]
|
|
|
|
|
node _T_714 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_716 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_717 = eq(_T_716, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_718 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_719 = eq(_T_718, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_720 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_721 = eq(_T_720, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_722 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_723 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_724 = eq(_T_723, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_725 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_726 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_727 = eq(_T_726, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_728 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_729 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_730 = eq(_T_729, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_731 = and(_T_715, _T_717) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_732 = and(_T_731, _T_719) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_733 = and(_T_732, _T_721) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_734 = and(_T_733, _T_722) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_735 = and(_T_734, _T_724) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_736 = and(_T_735, _T_725) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_737 = and(_T_736, _T_727) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_738 = and(_T_737, _T_728) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_739 = and(_T_738, _T_730) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.srl <= _T_739 @[dec_dec_ctl.scala 66:14]
|
|
|
|
|
node _T_740 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_741 = eq(_T_740, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_742 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_744 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_745 = eq(_T_744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_746 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_747 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_748 = eq(_T_747, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_749 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_750 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_751 = eq(_T_750, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_752 = and(_T_741, _T_743) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_753 = and(_T_752, _T_745) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_754 = and(_T_753, _T_746) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_755 = and(_T_754, _T_748) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_756 = and(_T_755, _T_749) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_757 = and(_T_756, _T_751) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_758 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_759 = eq(_T_758, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_760 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_761 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_762 = eq(_T_761, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_763 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_764 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_766 = and(_T_759, _T_760) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_767 = and(_T_766, _T_762) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_768 = and(_T_767, _T_763) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_769 = and(_T_768, _T_765) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_770 = or(_T_757, _T_769) @[dec_dec_ctl.scala 68:55]
|
|
|
|
|
io.out.slt <= _T_770 @[dec_dec_ctl.scala 68:14]
|
|
|
|
|
node _T_771 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_773 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_774 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_775 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_776 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_778 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_779 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_780 = eq(_T_779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_781 = and(_T_772, _T_773) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_782 = and(_T_781, _T_774) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_783 = and(_T_782, _T_775) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_784 = and(_T_783, _T_777) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_785 = and(_T_784, _T_778) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_786 = and(_T_785, _T_780) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_787 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_788 = eq(_T_787, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_789 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_790 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_791 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_792 = eq(_T_791, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_793 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_794 = eq(_T_793, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_795 = and(_T_788, _T_789) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_796 = and(_T_795, _T_790) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_797 = and(_T_796, _T_792) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_798 = and(_T_797, _T_794) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_799 = or(_T_786, _T_798) @[dec_dec_ctl.scala 70:56]
|
|
|
|
|
node _T_800 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_801 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_802 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_803 = eq(_T_802, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_804 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_805 = eq(_T_804, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_806 = and(_T_800, _T_801) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_807 = and(_T_806, _T_803) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_808 = and(_T_807, _T_805) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_809 = or(_T_799, _T_808) @[dec_dec_ctl.scala 70:89]
|
|
|
|
|
node _T_810 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_811 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_813 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_814 = eq(_T_813, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_815 = and(_T_810, _T_812) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_816 = and(_T_815, _T_814) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_817 = or(_T_809, _T_816) @[dec_dec_ctl.scala 71:31]
|
|
|
|
|
node _T_818 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_819 = eq(_T_818, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_820 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_821 = eq(_T_820, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_822 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_823 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_824 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_826 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_827 = eq(_T_826, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_828 = and(_T_819, _T_821) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_829 = and(_T_828, _T_822) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_830 = and(_T_829, _T_823) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_831 = and(_T_830, _T_825) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_832 = and(_T_831, _T_827) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_833 = or(_T_817, _T_832) @[dec_dec_ctl.scala 71:57]
|
|
|
|
|
node _T_834 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_835 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_836 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_837 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_838 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_840 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_841 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_842 = eq(_T_841, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_843 = and(_T_834, _T_835) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_844 = and(_T_843, _T_836) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_845 = and(_T_844, _T_837) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_846 = and(_T_845, _T_839) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_847 = and(_T_846, _T_840) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_848 = and(_T_847, _T_842) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_849 = or(_T_833, _T_848) @[dec_dec_ctl.scala 71:94]
|
|
|
|
|
io.out.unsign <= _T_849 @[dec_dec_ctl.scala 70:17]
|
|
|
|
|
node _T_850 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_851 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_852 = eq(_T_851, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_853 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_854 = eq(_T_853, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_855 = and(_T_850, _T_852) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_856 = and(_T_855, _T_854) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.condbr <= _T_856 @[dec_dec_ctl.scala 74:17]
|
|
|
|
|
node _T_857 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_859 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_861 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_862 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_863 = eq(_T_862, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_864 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_865 = eq(_T_864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_866 = and(_T_858, _T_860) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_867 = and(_T_866, _T_861) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_868 = and(_T_867, _T_863) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_869 = and(_T_868, _T_865) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.beq <= _T_869 @[dec_dec_ctl.scala 76:14]
|
|
|
|
|
node _T_870 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_872 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_873 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_874 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_875 = eq(_T_874, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_876 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_877 = eq(_T_876, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_878 = and(_T_871, _T_872) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_879 = and(_T_878, _T_873) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_880 = and(_T_879, _T_875) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_881 = and(_T_880, _T_877) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.bne <= _T_881 @[dec_dec_ctl.scala 78:14]
|
|
|
|
|
node _T_882 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_883 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_884 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_885 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_886 = eq(_T_885, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_887 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_888 = eq(_T_887, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_889 = and(_T_882, _T_883) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_890 = and(_T_889, _T_884) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_891 = and(_T_890, _T_886) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_892 = and(_T_891, _T_888) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.bge <= _T_892 @[dec_dec_ctl.scala 80:14]
|
|
|
|
|
node _T_893 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_894 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_896 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_897 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_898 = eq(_T_897, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_899 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_900 = eq(_T_899, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_901 = and(_T_893, _T_895) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_902 = and(_T_901, _T_896) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_903 = and(_T_902, _T_898) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_904 = and(_T_903, _T_900) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.blt <= _T_904 @[dec_dec_ctl.scala 82:14]
|
|
|
|
|
node _T_905 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_906 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_907 = and(_T_905, _T_906) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.jal <= _T_907 @[dec_dec_ctl.scala 84:14]
|
|
|
|
|
node _T_908 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_909 = eq(_T_908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_910 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_911 = eq(_T_910, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_912 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_913 = eq(_T_912, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_914 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_915 = eq(_T_914, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_916 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_917 = eq(_T_916, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_918 = and(_T_909, _T_911) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_919 = and(_T_918, _T_913) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_920 = and(_T_919, _T_915) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_921 = and(_T_920, _T_917) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.by <= _T_921 @[dec_dec_ctl.scala 86:13]
|
|
|
|
|
node _T_922 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_923 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_924 = eq(_T_923, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_925 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_926 = eq(_T_925, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_927 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_928 = eq(_T_927, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_929 = and(_T_922, _T_924) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_930 = and(_T_929, _T_926) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_931 = and(_T_930, _T_928) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.half <= _T_931 @[dec_dec_ctl.scala 88:15]
|
|
|
|
|
node _T_932 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_933 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_934 = eq(_T_933, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_935 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_936 = eq(_T_935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_937 = and(_T_932, _T_934) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_938 = and(_T_937, _T_936) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.word <= _T_938 @[dec_dec_ctl.scala 90:15]
|
|
|
|
|
node _T_939 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_940 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_941 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_942 = and(_T_939, _T_940) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_943 = and(_T_942, _T_941) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_944 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_945 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_946 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_947 = and(_T_944, _T_945) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_948 = and(_T_947, _T_946) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_949 = or(_T_943, _T_948) @[dec_dec_ctl.scala 92:44]
|
|
|
|
|
node _T_950 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_951 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_952 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_953 = and(_T_950, _T_951) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_954 = and(_T_953, _T_952) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_955 = or(_T_949, _T_954) @[dec_dec_ctl.scala 92:67]
|
|
|
|
|
node _T_956 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_957 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_958 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_959 = and(_T_956, _T_957) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_960 = and(_T_959, _T_958) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_961 = or(_T_955, _T_960) @[dec_dec_ctl.scala 92:90]
|
|
|
|
|
node _T_962 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_963 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_964 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_965 = and(_T_962, _T_963) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_966 = and(_T_965, _T_964) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_967 = or(_T_961, _T_966) @[dec_dec_ctl.scala 93:26]
|
|
|
|
|
node _T_968 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_969 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_970 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_971 = and(_T_968, _T_969) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_972 = and(_T_971, _T_970) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_973 = or(_T_967, _T_972) @[dec_dec_ctl.scala 93:50]
|
|
|
|
|
io.out.csr_read <= _T_973 @[dec_dec_ctl.scala 92:19]
|
|
|
|
|
node _T_974 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_975 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_976 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_977 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_978 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_979 = and(_T_974, _T_975) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_980 = and(_T_979, _T_976) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_981 = and(_T_980, _T_977) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_982 = and(_T_981, _T_978) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_983 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_984 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_985 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_986 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_987 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_988 = and(_T_983, _T_984) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_989 = and(_T_988, _T_985) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_990 = and(_T_989, _T_986) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_991 = and(_T_990, _T_987) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_992 = or(_T_982, _T_991) @[dec_dec_ctl.scala 95:49]
|
|
|
|
|
node _T_993 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_994 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_996 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_997 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_998 = and(_T_993, _T_994) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_999 = and(_T_998, _T_995) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1000 = and(_T_999, _T_996) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1001 = and(_T_1000, _T_997) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1002 = or(_T_992, _T_1001) @[dec_dec_ctl.scala 95:79]
|
|
|
|
|
node _T_1003 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1004 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1005 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1006 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1007 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1008 = and(_T_1003, _T_1004) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1009 = and(_T_1008, _T_1005) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1010 = and(_T_1009, _T_1006) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1011 = and(_T_1010, _T_1007) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1012 = or(_T_1002, _T_1011) @[dec_dec_ctl.scala 96:33]
|
|
|
|
|
node _T_1013 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1014 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1015 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1016 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1017 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1018 = and(_T_1013, _T_1014) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1019 = and(_T_1018, _T_1015) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1020 = and(_T_1019, _T_1016) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1021 = and(_T_1020, _T_1017) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1022 = or(_T_1012, _T_1021) @[dec_dec_ctl.scala 96:63]
|
|
|
|
|
io.out.csr_clr <= _T_1022 @[dec_dec_ctl.scala 95:18]
|
|
|
|
|
node _T_1023 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1024 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1026 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1027 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1028 = and(_T_1023, _T_1025) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1029 = and(_T_1028, _T_1026) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1030 = and(_T_1029, _T_1027) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1031 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1032 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1033 = eq(_T_1032, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1034 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1035 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1036 = and(_T_1031, _T_1033) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1037 = and(_T_1036, _T_1034) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1038 = and(_T_1037, _T_1035) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1039 = or(_T_1030, _T_1038) @[dec_dec_ctl.scala 98:47]
|
|
|
|
|
node _T_1040 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1041 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1042 = eq(_T_1041, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1043 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1044 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1045 = and(_T_1040, _T_1042) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1046 = and(_T_1045, _T_1043) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1047 = and(_T_1046, _T_1044) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1048 = or(_T_1039, _T_1047) @[dec_dec_ctl.scala 98:75]
|
|
|
|
|
node _T_1049 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1050 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1051 = eq(_T_1050, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1052 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1053 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1054 = and(_T_1049, _T_1051) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1055 = and(_T_1054, _T_1052) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1056 = and(_T_1055, _T_1053) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1057 = or(_T_1048, _T_1056) @[dec_dec_ctl.scala 98:103]
|
|
|
|
|
node _T_1058 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1059 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1060 = eq(_T_1059, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1061 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1062 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1063 = and(_T_1058, _T_1060) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1064 = and(_T_1063, _T_1061) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1065 = and(_T_1064, _T_1062) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1066 = or(_T_1057, _T_1065) @[dec_dec_ctl.scala 99:31]
|
|
|
|
|
io.out.csr_set <= _T_1066 @[dec_dec_ctl.scala 98:18]
|
|
|
|
|
node _T_1067 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1069 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1070 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1071 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1072 = and(_T_1068, _T_1069) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1073 = and(_T_1072, _T_1070) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1074 = and(_T_1073, _T_1071) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.csr_write <= _T_1074 @[dec_dec_ctl.scala 101:20]
|
|
|
|
|
node _T_1075 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1076 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1078 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1079 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
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|
|
node _T_1080 = and(_T_1075, _T_1077) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1081 = and(_T_1080, _T_1078) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1082 = and(_T_1081, _T_1079) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1083 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1084 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1085 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1086 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1087 = and(_T_1083, _T_1084) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1088 = and(_T_1087, _T_1085) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1089 = and(_T_1088, _T_1086) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1090 = or(_T_1082, _T_1089) @[dec_dec_ctl.scala 103:47]
|
|
|
|
|
node _T_1091 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1092 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1093 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1094 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1095 = and(_T_1091, _T_1092) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1096 = and(_T_1095, _T_1093) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1097 = and(_T_1096, _T_1094) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1098 = or(_T_1090, _T_1097) @[dec_dec_ctl.scala 103:74]
|
|
|
|
|
node _T_1099 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1100 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1101 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1102 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1103 = and(_T_1099, _T_1100) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1104 = and(_T_1103, _T_1101) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1105 = and(_T_1104, _T_1102) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1106 = or(_T_1098, _T_1105) @[dec_dec_ctl.scala 103:101]
|
|
|
|
|
node _T_1107 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1108 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1109 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1110 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1111 = and(_T_1107, _T_1108) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1112 = and(_T_1111, _T_1109) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1113 = and(_T_1112, _T_1110) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1114 = or(_T_1106, _T_1113) @[dec_dec_ctl.scala 104:30]
|
|
|
|
|
node _T_1115 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1116 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1117 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1118 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1119 = and(_T_1115, _T_1116) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1120 = and(_T_1119, _T_1117) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1121 = and(_T_1120, _T_1118) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1122 = or(_T_1114, _T_1121) @[dec_dec_ctl.scala 104:57]
|
|
|
|
|
io.out.csr_imm <= _T_1122 @[dec_dec_ctl.scala 103:18]
|
|
|
|
|
node _T_1123 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1125 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1126 = and(_T_1124, _T_1125) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1127 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1129 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1130 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1131 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1132 = and(_T_1128, _T_1129) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1133 = and(_T_1132, _T_1130) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1134 = and(_T_1133, _T_1131) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1135 = or(_T_1126, _T_1134) @[dec_dec_ctl.scala 106:41]
|
|
|
|
|
node _T_1136 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1137 = eq(_T_1136, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1138 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1139 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1140 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1141 = and(_T_1137, _T_1138) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1142 = and(_T_1141, _T_1139) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1143 = and(_T_1142, _T_1140) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1144 = or(_T_1135, _T_1143) @[dec_dec_ctl.scala 106:68]
|
|
|
|
|
node _T_1145 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1146 = eq(_T_1145, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1147 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1148 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1149 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1150 = and(_T_1146, _T_1147) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1151 = and(_T_1150, _T_1148) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1152 = and(_T_1151, _T_1149) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1153 = or(_T_1144, _T_1152) @[dec_dec_ctl.scala 106:95]
|
|
|
|
|
node _T_1154 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1156 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1157 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1158 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1159 = and(_T_1155, _T_1156) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1160 = and(_T_1159, _T_1157) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1161 = and(_T_1160, _T_1158) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1162 = or(_T_1153, _T_1161) @[dec_dec_ctl.scala 107:30]
|
|
|
|
|
node _T_1163 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1164 = eq(_T_1163, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1165 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1166 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1167 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1168 = and(_T_1164, _T_1165) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1169 = and(_T_1168, _T_1166) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1170 = and(_T_1169, _T_1167) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1171 = or(_T_1162, _T_1170) @[dec_dec_ctl.scala 107:58]
|
|
|
|
|
node _T_1172 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1173 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1174 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1175 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1176 = and(_T_1172, _T_1173) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1177 = and(_T_1176, _T_1174) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1178 = and(_T_1177, _T_1175) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1179 = or(_T_1171, _T_1178) @[dec_dec_ctl.scala 107:86]
|
|
|
|
|
node _T_1180 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1181 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1182 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1183 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1184 = and(_T_1180, _T_1181) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1185 = and(_T_1184, _T_1182) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1186 = and(_T_1185, _T_1183) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1187 = or(_T_1179, _T_1186) @[dec_dec_ctl.scala 108:30]
|
|
|
|
|
node _T_1188 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1189 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1190 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1191 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1192 = and(_T_1188, _T_1189) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1193 = and(_T_1192, _T_1190) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1194 = and(_T_1193, _T_1191) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1195 = or(_T_1187, _T_1194) @[dec_dec_ctl.scala 108:57]
|
|
|
|
|
node _T_1196 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1197 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1198 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1199 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1200 = and(_T_1196, _T_1197) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1201 = and(_T_1200, _T_1198) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1202 = and(_T_1201, _T_1199) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1203 = or(_T_1195, _T_1202) @[dec_dec_ctl.scala 108:84]
|
|
|
|
|
node _T_1204 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1205 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1206 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1207 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1208 = and(_T_1204, _T_1205) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1209 = and(_T_1208, _T_1206) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1210 = and(_T_1209, _T_1207) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1211 = or(_T_1203, _T_1210) @[dec_dec_ctl.scala 109:30]
|
|
|
|
|
io.out.presync <= _T_1211 @[dec_dec_ctl.scala 106:18]
|
|
|
|
|
node _T_1212 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1213 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1215 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1216 = and(_T_1212, _T_1214) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1217 = and(_T_1216, _T_1215) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1218 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1219 = eq(_T_1218, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1220 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1221 = eq(_T_1220, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1222 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1223 = eq(_T_1222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1224 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1225 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1226 = and(_T_1219, _T_1221) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1227 = and(_T_1226, _T_1223) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1228 = and(_T_1227, _T_1224) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1229 = and(_T_1228, _T_1225) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1230 = or(_T_1217, _T_1229) @[dec_dec_ctl.scala 111:45]
|
|
|
|
|
node _T_1231 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1233 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1234 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1235 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1236 = and(_T_1232, _T_1233) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1237 = and(_T_1236, _T_1234) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1238 = and(_T_1237, _T_1235) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1239 = or(_T_1230, _T_1238) @[dec_dec_ctl.scala 111:78]
|
|
|
|
|
node _T_1240 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1241 = eq(_T_1240, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1242 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1243 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1244 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1245 = and(_T_1241, _T_1242) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1246 = and(_T_1245, _T_1243) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1247 = and(_T_1246, _T_1244) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1248 = or(_T_1239, _T_1247) @[dec_dec_ctl.scala 112:30]
|
|
|
|
|
node _T_1249 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1250 = eq(_T_1249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1251 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1252 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1253 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1254 = and(_T_1250, _T_1251) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1255 = and(_T_1254, _T_1252) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1256 = and(_T_1255, _T_1253) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1257 = or(_T_1248, _T_1256) @[dec_dec_ctl.scala 112:57]
|
|
|
|
|
node _T_1258 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1260 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1261 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1262 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1263 = and(_T_1259, _T_1260) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1264 = and(_T_1263, _T_1261) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1265 = and(_T_1264, _T_1262) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1266 = or(_T_1257, _T_1265) @[dec_dec_ctl.scala 112:84]
|
|
|
|
|
node _T_1267 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1268 = eq(_T_1267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1269 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1270 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1271 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1272 = and(_T_1268, _T_1269) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1273 = and(_T_1272, _T_1270) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1274 = and(_T_1273, _T_1271) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1275 = or(_T_1266, _T_1274) @[dec_dec_ctl.scala 112:112]
|
|
|
|
|
node _T_1276 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1277 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1278 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1279 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1280 = and(_T_1276, _T_1277) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1281 = and(_T_1280, _T_1278) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1282 = and(_T_1281, _T_1279) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1283 = or(_T_1275, _T_1282) @[dec_dec_ctl.scala 113:31]
|
|
|
|
|
node _T_1284 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1285 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1286 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1287 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1288 = and(_T_1284, _T_1285) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1289 = and(_T_1288, _T_1286) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1290 = and(_T_1289, _T_1287) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1291 = or(_T_1283, _T_1290) @[dec_dec_ctl.scala 113:58]
|
|
|
|
|
node _T_1292 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1293 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1294 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1295 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1296 = and(_T_1292, _T_1293) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1297 = and(_T_1296, _T_1294) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1298 = and(_T_1297, _T_1295) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1299 = or(_T_1291, _T_1298) @[dec_dec_ctl.scala 113:85]
|
|
|
|
|
node _T_1300 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1301 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1302 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1303 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1304 = and(_T_1300, _T_1301) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1305 = and(_T_1304, _T_1302) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1306 = and(_T_1305, _T_1303) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1307 = or(_T_1299, _T_1306) @[dec_dec_ctl.scala 113:112]
|
|
|
|
|
node _T_1308 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1309 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1310 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1311 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1312 = and(_T_1308, _T_1309) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1313 = and(_T_1312, _T_1310) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1314 = and(_T_1313, _T_1311) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1315 = or(_T_1307, _T_1314) @[dec_dec_ctl.scala 114:30]
|
|
|
|
|
io.out.postsync <= _T_1315 @[dec_dec_ctl.scala 111:19]
|
|
|
|
|
node _T_1316 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1317 = eq(_T_1316, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1318 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1319 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1321 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1322 = eq(_T_1321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1323 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1324 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1325 = and(_T_1317, _T_1318) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1326 = and(_T_1325, _T_1320) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1327 = and(_T_1326, _T_1322) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1328 = and(_T_1327, _T_1323) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1329 = and(_T_1328, _T_1324) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.ebreak <= _T_1329 @[dec_dec_ctl.scala 116:17]
|
|
|
|
|
node _T_1330 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1331 = eq(_T_1330, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1332 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1334 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1336 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1338 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1339 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1340 = and(_T_1331, _T_1333) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1341 = and(_T_1340, _T_1335) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1342 = and(_T_1341, _T_1337) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1343 = and(_T_1342, _T_1338) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1344 = and(_T_1343, _T_1339) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.ecall <= _T_1344 @[dec_dec_ctl.scala 118:16]
|
|
|
|
|
node _T_1345 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1346 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1348 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1350 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1351 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1352 = and(_T_1345, _T_1347) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1353 = and(_T_1352, _T_1349) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1354 = and(_T_1353, _T_1350) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1355 = and(_T_1354, _T_1351) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.mret <= _T_1355 @[dec_dec_ctl.scala 120:15]
|
|
|
|
|
node _T_1356 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1357 = eq(_T_1356, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1358 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1359 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1360 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1361 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1362 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1364 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1365 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1366 = eq(_T_1365, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1367 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1368 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1369 = eq(_T_1368, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1370 = and(_T_1357, _T_1358) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1371 = and(_T_1370, _T_1359) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1372 = and(_T_1371, _T_1360) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1373 = and(_T_1372, _T_1361) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1374 = and(_T_1373, _T_1363) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1375 = and(_T_1374, _T_1364) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1376 = and(_T_1375, _T_1366) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1377 = and(_T_1376, _T_1367) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1378 = and(_T_1377, _T_1369) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1379 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1380 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1381 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1382 = eq(_T_1381, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1383 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1384 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1385 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1386 = eq(_T_1385, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1387 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1388 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1389 = eq(_T_1388, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1390 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1391 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
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|
|
node _T_1392 = eq(_T_1391, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1393 = and(_T_1379, _T_1380) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1394 = and(_T_1393, _T_1382) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1395 = and(_T_1394, _T_1383) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1396 = and(_T_1395, _T_1384) @[dec_dec_ctl.scala 17:17]
|
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|
|
node _T_1397 = and(_T_1396, _T_1386) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1398 = and(_T_1397, _T_1387) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1399 = and(_T_1398, _T_1389) @[dec_dec_ctl.scala 17:17]
|
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|
|
node _T_1400 = and(_T_1399, _T_1390) @[dec_dec_ctl.scala 17:17]
|
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|
|
node _T_1401 = and(_T_1400, _T_1392) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1402 = or(_T_1378, _T_1401) @[dec_dec_ctl.scala 122:63]
|
|
|
|
|
node _T_1403 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1404 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
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|
|
node _T_1405 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
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|
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|
|
node _T_1406 = eq(_T_1405, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1407 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
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|
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|
|
node _T_1408 = eq(_T_1407, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
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|
|
node _T_1409 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
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|
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|
|
node _T_1410 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
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|
|
node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
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|
|
node _T_1412 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
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|
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|
|
node _T_1413 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
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|
|
node _T_1414 = eq(_T_1413, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
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|
|
node _T_1415 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
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|
|
node _T_1416 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
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|
|
node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
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|
|
node _T_1418 = and(_T_1403, _T_1404) @[dec_dec_ctl.scala 17:17]
|
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|
|
node _T_1419 = and(_T_1418, _T_1406) @[dec_dec_ctl.scala 17:17]
|
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|
|
node _T_1420 = and(_T_1419, _T_1408) @[dec_dec_ctl.scala 17:17]
|
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|
|
node _T_1421 = and(_T_1420, _T_1409) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1422 = and(_T_1421, _T_1411) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1423 = and(_T_1422, _T_1412) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1424 = and(_T_1423, _T_1414) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1425 = and(_T_1424, _T_1415) @[dec_dec_ctl.scala 17:17]
|
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|
|
node _T_1426 = and(_T_1425, _T_1417) @[dec_dec_ctl.scala 17:17]
|
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|
|
node _T_1427 = or(_T_1402, _T_1426) @[dec_dec_ctl.scala 122:111]
|
|
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|
|
node _T_1428 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1429 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1430 = eq(_T_1429, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1431 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
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|
|
node _T_1432 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
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|
|
node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1434 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1436 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1437 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
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|
|
node _T_1438 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
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|
|
node _T_1440 = and(_T_1428, _T_1430) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1441 = and(_T_1440, _T_1431) @[dec_dec_ctl.scala 17:17]
|
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|
|
node _T_1442 = and(_T_1441, _T_1433) @[dec_dec_ctl.scala 17:17]
|
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|
|
node _T_1443 = and(_T_1442, _T_1435) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1444 = and(_T_1443, _T_1436) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1445 = and(_T_1444, _T_1437) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1446 = and(_T_1445, _T_1439) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_1447 = or(_T_1427, _T_1446) @[dec_dec_ctl.scala 123:52]
|
|
|
|
|
node _T_1448 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1449 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1450 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1451 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1452 = eq(_T_1451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1453 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1454 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1455 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1456 = eq(_T_1455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1457 = and(_T_1448, _T_1449) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1458 = and(_T_1457, _T_1450) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1459 = and(_T_1458, _T_1452) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1460 = and(_T_1459, _T_1453) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1461 = and(_T_1460, _T_1454) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1462 = and(_T_1461, _T_1456) @[dec_dec_ctl.scala 17:17]
|
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|
|
node _T_1463 = or(_T_1447, _T_1462) @[dec_dec_ctl.scala 123:93]
|
|
|
|
|
node _T_1464 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1465 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
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|
|
node _T_1466 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1467 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1469 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1470 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1471 = eq(_T_1470, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1472 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1473 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1474 = eq(_T_1473, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1475 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1476 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1477 = eq(_T_1476, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1478 = and(_T_1464, _T_1465) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1479 = and(_T_1478, _T_1466) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1480 = and(_T_1479, _T_1468) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1481 = and(_T_1480, _T_1469) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1482 = and(_T_1481, _T_1471) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1483 = and(_T_1482, _T_1472) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1484 = and(_T_1483, _T_1474) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1485 = and(_T_1484, _T_1475) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1486 = and(_T_1485, _T_1477) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1487 = or(_T_1463, _T_1486) @[dec_dec_ctl.scala 124:39]
|
|
|
|
|
node _T_1488 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1489 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1490 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1492 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1493 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1494 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1495 = eq(_T_1494, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1496 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1497 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1499 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1500 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1501 = eq(_T_1500, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1502 = and(_T_1488, _T_1489) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1503 = and(_T_1502, _T_1491) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1504 = and(_T_1503, _T_1492) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1505 = and(_T_1504, _T_1493) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1506 = and(_T_1505, _T_1495) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1507 = and(_T_1506, _T_1496) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1508 = and(_T_1507, _T_1498) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1509 = and(_T_1508, _T_1499) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1510 = and(_T_1509, _T_1501) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1511 = or(_T_1487, _T_1510) @[dec_dec_ctl.scala 124:87]
|
|
|
|
|
node _T_1512 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1513 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1514 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1516 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1517 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1518 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1520 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1521 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1523 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1524 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1525 = eq(_T_1524, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1526 = and(_T_1512, _T_1513) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1527 = and(_T_1526, _T_1515) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1528 = and(_T_1527, _T_1516) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1529 = and(_T_1528, _T_1517) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1530 = and(_T_1529, _T_1519) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1531 = and(_T_1530, _T_1520) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1532 = and(_T_1531, _T_1522) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1533 = and(_T_1532, _T_1523) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1534 = and(_T_1533, _T_1525) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1535 = or(_T_1511, _T_1534) @[dec_dec_ctl.scala 125:51]
|
|
|
|
|
node _T_1536 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1537 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1538 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1539 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1541 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1542 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1543 = eq(_T_1542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1544 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1545 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1546 = eq(_T_1545, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1547 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1548 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1550 = and(_T_1536, _T_1537) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1551 = and(_T_1550, _T_1538) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1552 = and(_T_1551, _T_1540) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1553 = and(_T_1552, _T_1541) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1554 = and(_T_1553, _T_1543) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1555 = and(_T_1554, _T_1544) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1556 = and(_T_1555, _T_1546) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1557 = and(_T_1556, _T_1547) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1558 = and(_T_1557, _T_1549) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1559 = or(_T_1535, _T_1558) @[dec_dec_ctl.scala 125:99]
|
|
|
|
|
node _T_1560 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1562 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1563 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1564 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1565 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1566 = eq(_T_1565, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1567 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1568 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1569 = eq(_T_1568, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1570 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1571 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1573 = and(_T_1561, _T_1562) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1574 = and(_T_1573, _T_1563) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1575 = and(_T_1574, _T_1564) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1576 = and(_T_1575, _T_1566) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1577 = and(_T_1576, _T_1567) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1578 = and(_T_1577, _T_1569) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1579 = and(_T_1578, _T_1570) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1580 = and(_T_1579, _T_1572) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1581 = or(_T_1559, _T_1580) @[dec_dec_ctl.scala 126:51]
|
|
|
|
|
node _T_1582 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1584 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1586 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1587 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1588 = eq(_T_1587, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1589 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1590 = eq(_T_1589, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1591 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1592 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1594 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1595 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1596 = eq(_T_1595, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1597 = and(_T_1583, _T_1585) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1598 = and(_T_1597, _T_1586) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1599 = and(_T_1598, _T_1588) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1600 = and(_T_1599, _T_1590) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1601 = and(_T_1600, _T_1591) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1602 = and(_T_1601, _T_1593) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1603 = and(_T_1602, _T_1594) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1604 = and(_T_1603, _T_1596) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1605 = or(_T_1581, _T_1604) @[dec_dec_ctl.scala 126:96]
|
|
|
|
|
node _T_1606 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1607 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1609 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1610 = eq(_T_1609, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1611 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1612 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1613 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1614 = eq(_T_1613, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1615 = and(_T_1606, _T_1608) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1616 = and(_T_1615, _T_1610) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1617 = and(_T_1616, _T_1611) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1618 = and(_T_1617, _T_1612) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1619 = and(_T_1618, _T_1614) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1620 = or(_T_1605, _T_1619) @[dec_dec_ctl.scala 127:50]
|
|
|
|
|
node _T_1621 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1622 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1623 = eq(_T_1622, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1624 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1625 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1627 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1628 = eq(_T_1627, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1629 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1630 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1631 = eq(_T_1630, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1632 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1633 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1634 = eq(_T_1633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1635 = and(_T_1621, _T_1623) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1636 = and(_T_1635, _T_1624) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1637 = and(_T_1636, _T_1626) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1638 = and(_T_1637, _T_1628) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1639 = and(_T_1638, _T_1629) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1640 = and(_T_1639, _T_1631) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1641 = and(_T_1640, _T_1632) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1642 = and(_T_1641, _T_1634) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1643 = or(_T_1620, _T_1642) @[dec_dec_ctl.scala 127:84]
|
|
|
|
|
node _T_1644 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1645 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1646 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1647 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1648 = eq(_T_1647, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1649 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1650 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1652 = and(_T_1644, _T_1645) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1653 = and(_T_1652, _T_1646) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1654 = and(_T_1653, _T_1648) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1655 = and(_T_1654, _T_1649) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1656 = and(_T_1655, _T_1651) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1657 = or(_T_1643, _T_1656) @[dec_dec_ctl.scala 128:49]
|
|
|
|
|
io.out.mul <= _T_1657 @[dec_dec_ctl.scala 122:14]
|
|
|
|
|
node _T_1658 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1659 = eq(_T_1658, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1660 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1661 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1662 = eq(_T_1661, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1663 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1664 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1665 = eq(_T_1664, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1666 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1668 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1669 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1670 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1672 = and(_T_1659, _T_1660) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1673 = and(_T_1672, _T_1662) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1674 = and(_T_1673, _T_1663) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1675 = and(_T_1674, _T_1665) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1676 = and(_T_1675, _T_1667) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1677 = and(_T_1676, _T_1668) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1678 = and(_T_1677, _T_1669) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1679 = and(_T_1678, _T_1671) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1680 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1681 = eq(_T_1680, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1682 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1683 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1684 = eq(_T_1683, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1685 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1686 = eq(_T_1685, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1687 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1688 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1690 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1691 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1693 = and(_T_1681, _T_1682) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1694 = and(_T_1693, _T_1684) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1695 = and(_T_1694, _T_1686) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1696 = and(_T_1695, _T_1687) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1697 = and(_T_1696, _T_1689) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1698 = and(_T_1697, _T_1690) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1699 = and(_T_1698, _T_1692) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1700 = or(_T_1679, _T_1699) @[dec_dec_ctl.scala 130:65]
|
|
|
|
|
io.out.rs1_sign <= _T_1700 @[dec_dec_ctl.scala 130:19]
|
|
|
|
|
node _T_1701 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1702 = eq(_T_1701, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1703 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1704 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1705 = eq(_T_1704, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1706 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1707 = eq(_T_1706, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1708 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1709 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1710 = eq(_T_1709, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1711 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1712 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1714 = and(_T_1702, _T_1703) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1715 = and(_T_1714, _T_1705) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1716 = and(_T_1715, _T_1707) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1717 = and(_T_1716, _T_1708) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1718 = and(_T_1717, _T_1710) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1719 = and(_T_1718, _T_1711) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1720 = and(_T_1719, _T_1713) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.rs2_sign <= _T_1720 @[dec_dec_ctl.scala 132:19]
|
|
|
|
|
node _T_1721 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1722 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1723 = eq(_T_1722, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1724 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1725 = eq(_T_1724, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1726 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1727 = eq(_T_1726, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1728 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1729 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1730 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1731 = eq(_T_1730, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1732 = and(_T_1721, _T_1723) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1733 = and(_T_1732, _T_1725) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1734 = and(_T_1733, _T_1727) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1735 = and(_T_1734, _T_1728) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1736 = and(_T_1735, _T_1729) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1737 = and(_T_1736, _T_1731) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.low <= _T_1737 @[dec_dec_ctl.scala 134:14]
|
|
|
|
|
node _T_1738 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1739 = eq(_T_1738, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1740 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1741 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1742 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1743 = eq(_T_1742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1744 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1745 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1747 = and(_T_1739, _T_1740) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1748 = and(_T_1747, _T_1741) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1749 = and(_T_1748, _T_1743) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1750 = and(_T_1749, _T_1744) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1751 = and(_T_1750, _T_1746) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.div <= _T_1751 @[dec_dec_ctl.scala 136:14]
|
|
|
|
|
node _T_1752 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1753 = eq(_T_1752, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1754 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1755 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1756 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1757 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1759 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1760 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1761 = eq(_T_1760, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1762 = and(_T_1753, _T_1754) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1763 = and(_T_1762, _T_1755) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1764 = and(_T_1763, _T_1756) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1765 = and(_T_1764, _T_1758) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1766 = and(_T_1765, _T_1759) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1767 = and(_T_1766, _T_1761) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.rem <= _T_1767 @[dec_dec_ctl.scala 138:14]
|
|
|
|
|
node _T_1768 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1769 = eq(_T_1768, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1770 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1771 = and(_T_1769, _T_1770) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.fence <= _T_1771 @[dec_dec_ctl.scala 140:16]
|
|
|
|
|
node _T_1772 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1773 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1775 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1776 = and(_T_1772, _T_1774) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1777 = and(_T_1776, _T_1775) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.fence_i <= _T_1777 @[dec_dec_ctl.scala 142:18]
|
|
|
|
|
node _T_1778 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1779 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1781 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1782 = eq(_T_1781, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1783 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1784 = eq(_T_1783, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1785 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1786 = eq(_T_1785, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1787 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1788 = eq(_T_1787, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1789 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1790 = eq(_T_1789, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1791 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1792 = eq(_T_1791, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1793 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1794 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1795 = eq(_T_1794, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1796 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1797 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1798 = eq(_T_1797, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1799 = and(_T_1778, _T_1780) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1800 = and(_T_1799, _T_1782) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1801 = and(_T_1800, _T_1784) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1802 = and(_T_1801, _T_1786) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1803 = and(_T_1802, _T_1788) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1804 = and(_T_1803, _T_1790) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1805 = and(_T_1804, _T_1792) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1806 = and(_T_1805, _T_1793) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1807 = and(_T_1806, _T_1795) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1808 = and(_T_1807, _T_1796) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1809 = and(_T_1808, _T_1798) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.clz <= _T_1809 @[dec_dec_ctl.scala 144:14]
|
|
|
|
|
node _T_1810 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1811 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1813 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1814 = eq(_T_1813, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1815 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1816 = eq(_T_1815, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1817 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1818 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1820 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1822 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1823 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1824 = eq(_T_1823, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1825 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1826 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1828 = and(_T_1810, _T_1812) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1829 = and(_T_1828, _T_1814) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1830 = and(_T_1829, _T_1816) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1831 = and(_T_1830, _T_1817) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1832 = and(_T_1831, _T_1819) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1833 = and(_T_1832, _T_1821) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1834 = and(_T_1833, _T_1822) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1835 = and(_T_1834, _T_1824) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1836 = and(_T_1835, _T_1825) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1837 = and(_T_1836, _T_1827) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.ctz <= _T_1837 @[dec_dec_ctl.scala 146:14]
|
|
|
|
|
node _T_1838 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1839 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1840 = eq(_T_1839, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1841 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1842 = eq(_T_1841, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1843 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1844 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1846 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1848 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1849 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1850 = eq(_T_1849, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1851 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1852 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1854 = and(_T_1838, _T_1840) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1855 = and(_T_1854, _T_1842) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1856 = and(_T_1855, _T_1843) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1857 = and(_T_1856, _T_1845) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1858 = and(_T_1857, _T_1847) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1859 = and(_T_1858, _T_1848) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1860 = and(_T_1859, _T_1850) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1861 = and(_T_1860, _T_1851) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1862 = and(_T_1861, _T_1853) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.pcnt <= _T_1862 @[dec_dec_ctl.scala 148:15]
|
|
|
|
|
node _T_1863 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1864 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1865 = eq(_T_1864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1866 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1867 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1868 = eq(_T_1867, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1869 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1870 = eq(_T_1869, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1871 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1872 = eq(_T_1871, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1873 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1874 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1875 = eq(_T_1874, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1876 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1877 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1878 = eq(_T_1877, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1879 = and(_T_1863, _T_1865) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1880 = and(_T_1879, _T_1866) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1881 = and(_T_1880, _T_1868) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1882 = and(_T_1881, _T_1870) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1883 = and(_T_1882, _T_1872) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1884 = and(_T_1883, _T_1873) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1885 = and(_T_1884, _T_1875) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1886 = and(_T_1885, _T_1876) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1887 = and(_T_1886, _T_1878) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sext_b <= _T_1887 @[dec_dec_ctl.scala 150:17]
|
|
|
|
|
node _T_1888 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1889 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1891 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1892 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1893 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1895 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1897 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1898 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1899 = eq(_T_1898, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1900 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1901 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1902 = eq(_T_1901, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1903 = and(_T_1888, _T_1890) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1904 = and(_T_1903, _T_1891) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1905 = and(_T_1904, _T_1892) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1906 = and(_T_1905, _T_1894) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1907 = and(_T_1906, _T_1896) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1908 = and(_T_1907, _T_1897) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1909 = and(_T_1908, _T_1899) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1910 = and(_T_1909, _T_1900) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1911 = and(_T_1910, _T_1902) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sext_h <= _T_1911 @[dec_dec_ctl.scala 152:17]
|
|
|
|
|
node _T_1912 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1914 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1915 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1916 = eq(_T_1915, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1917 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1919 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1920 = eq(_T_1919, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1921 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1922 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1923 = eq(_T_1922, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1924 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1925 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1926 = eq(_T_1925, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1927 = and(_T_1913, _T_1914) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1928 = and(_T_1927, _T_1916) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1929 = and(_T_1928, _T_1918) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1930 = and(_T_1929, _T_1920) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1931 = and(_T_1930, _T_1921) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1932 = and(_T_1931, _T_1923) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1933 = and(_T_1932, _T_1924) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1934 = and(_T_1933, _T_1926) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.slo <= _T_1934 @[dec_dec_ctl.scala 154:14]
|
|
|
|
|
node _T_1935 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1937 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1938 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1939 = eq(_T_1938, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1940 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1941 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1942 = eq(_T_1941, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1943 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1944 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1946 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1947 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1948 = eq(_T_1947, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1949 = and(_T_1936, _T_1937) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1950 = and(_T_1949, _T_1939) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1951 = and(_T_1950, _T_1940) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1952 = and(_T_1951, _T_1942) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1953 = and(_T_1952, _T_1943) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1954 = and(_T_1953, _T_1945) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1955 = and(_T_1954, _T_1946) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1956 = and(_T_1955, _T_1948) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sro <= _T_1956 @[dec_dec_ctl.scala 156:14]
|
|
|
|
|
node _T_1957 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1958 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1959 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1960 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1961 = eq(_T_1960, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1962 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1963 = eq(_T_1962, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1964 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1965 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1966 = eq(_T_1965, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1967 = and(_T_1957, _T_1958) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1968 = and(_T_1967, _T_1959) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1969 = and(_T_1968, _T_1961) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1970 = and(_T_1969, _T_1963) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1971 = and(_T_1970, _T_1964) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1972 = and(_T_1971, _T_1966) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.min <= _T_1972 @[dec_dec_ctl.scala 158:14]
|
|
|
|
|
node _T_1973 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1974 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1975 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1976 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1977 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1978 = eq(_T_1977, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1979 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1980 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1981 = eq(_T_1980, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1982 = and(_T_1973, _T_1974) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1983 = and(_T_1982, _T_1975) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1984 = and(_T_1983, _T_1976) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1985 = and(_T_1984, _T_1978) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1986 = and(_T_1985, _T_1979) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_1987 = and(_T_1986, _T_1981) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.max <= _T_1987 @[dec_dec_ctl.scala 160:14]
|
|
|
|
|
node _T_1988 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1989 = eq(_T_1988, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1990 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1991 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1993 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1994 = eq(_T_1993, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_1996 = eq(_T_1995, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_1997 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1998 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_1999 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2000 = eq(_T_1999, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2001 = and(_T_1989, _T_1990) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2002 = and(_T_2001, _T_1992) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2003 = and(_T_2002, _T_1994) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2004 = and(_T_2003, _T_1996) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2005 = and(_T_2004, _T_1997) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2006 = and(_T_2005, _T_1998) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2007 = and(_T_2006, _T_2000) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.pack <= _T_2007 @[dec_dec_ctl.scala 162:15]
|
|
|
|
|
node _T_2008 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2009 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2010 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2011 = eq(_T_2010, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2012 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2013 = eq(_T_2012, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2014 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2015 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2016 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2017 = eq(_T_2016, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2018 = and(_T_2008, _T_2009) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2019 = and(_T_2018, _T_2011) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2020 = and(_T_2019, _T_2013) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2021 = and(_T_2020, _T_2014) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2022 = and(_T_2021, _T_2015) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2023 = and(_T_2022, _T_2017) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.packu <= _T_2023 @[dec_dec_ctl.scala 164:16]
|
|
|
|
|
node _T_2024 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2026 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2027 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2028 = eq(_T_2027, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2029 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2030 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2031 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2032 = eq(_T_2031, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2033 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2034 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2035 = eq(_T_2034, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2036 = and(_T_2025, _T_2026) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2037 = and(_T_2036, _T_2028) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2038 = and(_T_2037, _T_2029) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2039 = and(_T_2038, _T_2030) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2040 = and(_T_2039, _T_2032) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2041 = and(_T_2040, _T_2033) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2042 = and(_T_2041, _T_2035) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.packh <= _T_2042 @[dec_dec_ctl.scala 166:16]
|
|
|
|
|
node _T_2043 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2044 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2045 = eq(_T_2044, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2046 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2047 = eq(_T_2046, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2048 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2049 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2050 = eq(_T_2049, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2051 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2052 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2053 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2054 = eq(_T_2053, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2055 = and(_T_2043, _T_2045) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2056 = and(_T_2055, _T_2047) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2057 = and(_T_2056, _T_2048) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2058 = and(_T_2057, _T_2050) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2059 = and(_T_2058, _T_2051) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2060 = and(_T_2059, _T_2052) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2061 = and(_T_2060, _T_2054) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.rol <= _T_2061 @[dec_dec_ctl.scala 168:14]
|
|
|
|
|
node _T_2062 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2063 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2064 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2065 = eq(_T_2064, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2066 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2067 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2068 = eq(_T_2067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2069 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2070 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2071 = eq(_T_2070, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2072 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2073 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2074 = eq(_T_2073, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2075 = and(_T_2062, _T_2063) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2076 = and(_T_2075, _T_2065) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2077 = and(_T_2076, _T_2066) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2078 = and(_T_2077, _T_2068) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2079 = and(_T_2078, _T_2069) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2080 = and(_T_2079, _T_2071) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2081 = and(_T_2080, _T_2072) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2082 = and(_T_2081, _T_2074) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.ror <= _T_2082 @[dec_dec_ctl.scala 170:14]
|
|
|
|
|
node _T_2083 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2084 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2085 = eq(_T_2084, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2086 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2087 = eq(_T_2086, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2088 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2089 = eq(_T_2088, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2090 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2091 = eq(_T_2090, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2092 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2093 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2094 = eq(_T_2093, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2095 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2096 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2097 = eq(_T_2096, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2098 = and(_T_2083, _T_2085) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2099 = and(_T_2098, _T_2087) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2100 = and(_T_2099, _T_2089) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2101 = and(_T_2100, _T_2091) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2102 = and(_T_2101, _T_2092) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2103 = and(_T_2102, _T_2094) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2104 = and(_T_2103, _T_2095) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2105 = and(_T_2104, _T_2097) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2106 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2107 = eq(_T_2106, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2108 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2109 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2110 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2111 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2112 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2113 = eq(_T_2112, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2114 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2115 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2116 = eq(_T_2115, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2117 = and(_T_2107, _T_2108) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2118 = and(_T_2117, _T_2109) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2119 = and(_T_2118, _T_2110) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2120 = and(_T_2119, _T_2111) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2121 = and(_T_2120, _T_2113) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2122 = and(_T_2121, _T_2114) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2123 = and(_T_2122, _T_2116) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2124 = or(_T_2105, _T_2123) @[dec_dec_ctl.scala 172:62]
|
|
|
|
|
node _T_2125 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2126 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2127 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2128 = eq(_T_2127, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2129 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2130 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2131 = eq(_T_2130, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2132 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2133 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2134 = eq(_T_2133, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2135 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2136 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2137 = eq(_T_2136, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2138 = and(_T_2125, _T_2126) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2139 = and(_T_2138, _T_2128) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2140 = and(_T_2139, _T_2129) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2141 = and(_T_2140, _T_2131) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2142 = and(_T_2141, _T_2132) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2143 = and(_T_2142, _T_2134) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2144 = and(_T_2143, _T_2135) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2145 = and(_T_2144, _T_2137) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2146 = or(_T_2124, _T_2145) @[dec_dec_ctl.scala 172:103]
|
|
|
|
|
node _T_2147 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2148 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2149 = eq(_T_2148, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2150 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2151 = eq(_T_2150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2152 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2153 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2154 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2155 = eq(_T_2154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2156 = and(_T_2147, _T_2149) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2157 = and(_T_2156, _T_2151) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2158 = and(_T_2157, _T_2152) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2159 = and(_T_2158, _T_2153) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2160 = and(_T_2159, _T_2155) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2161 = or(_T_2146, _T_2160) @[dec_dec_ctl.scala 173:48]
|
|
|
|
|
node _T_2162 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2163 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2164 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2165 = eq(_T_2164, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2166 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2167 = eq(_T_2166, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2168 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2169 = eq(_T_2168, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2170 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2171 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2172 = eq(_T_2171, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2173 = and(_T_2162, _T_2163) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2174 = and(_T_2173, _T_2165) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2175 = and(_T_2174, _T_2167) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2176 = and(_T_2175, _T_2169) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2177 = and(_T_2176, _T_2170) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2178 = and(_T_2177, _T_2172) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2179 = or(_T_2161, _T_2178) @[dec_dec_ctl.scala 173:83]
|
|
|
|
|
node _T_2180 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2181 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2182 = eq(_T_2181, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2183 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2184 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2185 = eq(_T_2184, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2186 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2187 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2188 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2189 = eq(_T_2188, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2190 = and(_T_2180, _T_2182) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2191 = and(_T_2190, _T_2183) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2192 = and(_T_2191, _T_2185) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2193 = and(_T_2192, _T_2186) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2194 = and(_T_2193, _T_2187) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2195 = and(_T_2194, _T_2189) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2196 = or(_T_2179, _T_2195) @[dec_dec_ctl.scala 174:42]
|
|
|
|
|
node _T_2197 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2198 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2199 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2200 = eq(_T_2199, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2201 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2202 = eq(_T_2201, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2203 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2204 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2205 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2206 = eq(_T_2205, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2207 = and(_T_2197, _T_2198) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2208 = and(_T_2207, _T_2200) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2209 = and(_T_2208, _T_2202) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2210 = and(_T_2209, _T_2203) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2211 = and(_T_2210, _T_2204) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2212 = and(_T_2211, _T_2206) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2213 = or(_T_2196, _T_2212) @[dec_dec_ctl.scala 174:79]
|
|
|
|
|
node _T_2214 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2215 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2216 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2217 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2218 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2219 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2220 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2221 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2222 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2223 = eq(_T_2222, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2224 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2225 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2226 = eq(_T_2225, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2227 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2228 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2229 = eq(_T_2228, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2230 = and(_T_2214, _T_2215) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2231 = and(_T_2230, _T_2216) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2232 = and(_T_2231, _T_2217) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2233 = and(_T_2232, _T_2218) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2234 = and(_T_2233, _T_2219) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2235 = and(_T_2234, _T_2220) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2236 = and(_T_2235, _T_2221) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2237 = and(_T_2236, _T_2223) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2238 = and(_T_2237, _T_2224) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2239 = and(_T_2238, _T_2226) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2240 = and(_T_2239, _T_2227) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2241 = and(_T_2240, _T_2229) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_2242 = or(_T_2213, _T_2241) @[dec_dec_ctl.scala 175:40]
|
|
|
|
|
node _T_2243 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2244 = eq(_T_2243, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2245 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2246 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2247 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2248 = eq(_T_2247, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2249 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2250 = eq(_T_2249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2251 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2252 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34]
|
|
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|
|
node _T_2253 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
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|
|
node _T_2254 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
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|
|
node _T_2255 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2256 = eq(_T_2255, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2257 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2258 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2259 = eq(_T_2258, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2260 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2261 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2262 = eq(_T_2261, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2263 = and(_T_2244, _T_2245) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2264 = and(_T_2263, _T_2246) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2265 = and(_T_2264, _T_2248) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2266 = and(_T_2265, _T_2250) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2267 = and(_T_2266, _T_2251) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2268 = and(_T_2267, _T_2252) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2269 = and(_T_2268, _T_2253) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2270 = and(_T_2269, _T_2254) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2271 = and(_T_2270, _T_2256) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2272 = and(_T_2271, _T_2257) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2273 = and(_T_2272, _T_2259) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2274 = and(_T_2273, _T_2260) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2275 = and(_T_2274, _T_2262) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2276 = or(_T_2242, _T_2275) @[dec_dec_ctl.scala 175:96]
|
|
|
|
|
node _T_2277 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2278 = eq(_T_2277, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2279 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2280 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2281 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2282 = eq(_T_2281, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2283 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2284 = eq(_T_2283, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2285 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2286 = eq(_T_2285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2287 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2288 = eq(_T_2287, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2289 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2290 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2291 = eq(_T_2290, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2292 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2293 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2294 = eq(_T_2293, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2295 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2296 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2297 = eq(_T_2296, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2298 = and(_T_2278, _T_2279) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2299 = and(_T_2298, _T_2280) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2300 = and(_T_2299, _T_2282) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2301 = and(_T_2300, _T_2284) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2302 = and(_T_2301, _T_2286) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2303 = and(_T_2302, _T_2288) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2304 = and(_T_2303, _T_2289) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2305 = and(_T_2304, _T_2291) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2306 = and(_T_2305, _T_2292) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2307 = and(_T_2306, _T_2294) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2308 = and(_T_2307, _T_2295) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2309 = and(_T_2308, _T_2297) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2310 = or(_T_2276, _T_2309) @[dec_dec_ctl.scala 176:65]
|
|
|
|
|
node _T_2311 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2312 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2313 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2314 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2315 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2316 = eq(_T_2315, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2317 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2318 = eq(_T_2317, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2319 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2320 = eq(_T_2319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2321 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2322 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2323 = eq(_T_2322, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2324 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2325 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2326 = eq(_T_2325, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2327 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2328 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2329 = eq(_T_2328, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2330 = and(_T_2311, _T_2312) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2331 = and(_T_2330, _T_2313) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2332 = and(_T_2331, _T_2314) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2333 = and(_T_2332, _T_2316) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2334 = and(_T_2333, _T_2318) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2335 = and(_T_2334, _T_2320) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2336 = and(_T_2335, _T_2321) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2337 = and(_T_2336, _T_2323) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2338 = and(_T_2337, _T_2324) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2339 = and(_T_2338, _T_2326) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2340 = and(_T_2339, _T_2327) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2341 = and(_T_2340, _T_2329) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2342 = or(_T_2310, _T_2341) @[dec_dec_ctl.scala 177:64]
|
|
|
|
|
node _T_2343 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2344 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2345 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2346 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2347 = eq(_T_2346, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2348 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2349 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2350 = eq(_T_2349, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2351 = and(_T_2343, _T_2344) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2352 = and(_T_2351, _T_2345) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2353 = and(_T_2352, _T_2347) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2354 = and(_T_2353, _T_2348) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2355 = and(_T_2354, _T_2350) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2356 = or(_T_2342, _T_2355) @[dec_dec_ctl.scala 178:62]
|
|
|
|
|
io.out.zbb <= _T_2356 @[dec_dec_ctl.scala 172:14]
|
|
|
|
|
node _T_2357 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2358 = eq(_T_2357, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2359 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2360 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2361 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2362 = eq(_T_2361, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2363 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2364 = eq(_T_2363, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2365 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2366 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2367 = eq(_T_2366, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2368 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2369 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2370 = eq(_T_2369, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2371 = and(_T_2358, _T_2359) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2372 = and(_T_2371, _T_2360) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2373 = and(_T_2372, _T_2362) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2374 = and(_T_2373, _T_2364) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2375 = and(_T_2374, _T_2365) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2376 = and(_T_2375, _T_2367) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2377 = and(_T_2376, _T_2368) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2378 = and(_T_2377, _T_2370) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sbset <= _T_2378 @[dec_dec_ctl.scala 180:16]
|
|
|
|
|
node _T_2379 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2380 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2381 = eq(_T_2380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2382 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2383 = eq(_T_2382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2384 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2385 = eq(_T_2384, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2386 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2387 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2388 = eq(_T_2387, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2389 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2390 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2391 = eq(_T_2390, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2392 = and(_T_2379, _T_2381) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2393 = and(_T_2392, _T_2383) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2394 = and(_T_2393, _T_2385) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2395 = and(_T_2394, _T_2386) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2396 = and(_T_2395, _T_2388) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2397 = and(_T_2396, _T_2389) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2398 = and(_T_2397, _T_2391) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sbclr <= _T_2398 @[dec_dec_ctl.scala 182:16]
|
|
|
|
|
node _T_2399 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2400 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2401 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2402 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2403 = eq(_T_2402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2404 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2405 = eq(_T_2404, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2406 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2407 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2408 = eq(_T_2407, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2409 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2410 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2411 = eq(_T_2410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2412 = and(_T_2399, _T_2400) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2413 = and(_T_2412, _T_2401) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2414 = and(_T_2413, _T_2403) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2415 = and(_T_2414, _T_2405) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2416 = and(_T_2415, _T_2406) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2417 = and(_T_2416, _T_2408) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2418 = and(_T_2417, _T_2409) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2419 = and(_T_2418, _T_2411) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sbinv <= _T_2419 @[dec_dec_ctl.scala 184:16]
|
|
|
|
|
node _T_2420 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2421 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2422 = eq(_T_2421, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2423 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2424 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2425 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2426 = eq(_T_2425, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2427 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2428 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2429 = eq(_T_2428, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2430 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2431 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2432 = eq(_T_2431, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2433 = and(_T_2420, _T_2422) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2434 = and(_T_2433, _T_2423) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2435 = and(_T_2434, _T_2424) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2436 = and(_T_2435, _T_2426) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2437 = and(_T_2436, _T_2427) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2438 = and(_T_2437, _T_2429) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2439 = and(_T_2438, _T_2430) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2440 = and(_T_2439, _T_2432) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sbext <= _T_2440 @[dec_dec_ctl.scala 186:16]
|
|
|
|
|
node _T_2441 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2442 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2443 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2444 = eq(_T_2443, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2445 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2446 = eq(_T_2445, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2447 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2448 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2449 = eq(_T_2448, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2450 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2451 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2452 = eq(_T_2451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2453 = and(_T_2441, _T_2442) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2454 = and(_T_2453, _T_2444) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2455 = and(_T_2454, _T_2446) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2456 = and(_T_2455, _T_2447) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2457 = and(_T_2456, _T_2449) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2458 = and(_T_2457, _T_2450) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2459 = and(_T_2458, _T_2452) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2460 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2461 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2462 = eq(_T_2461, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2463 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2464 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2465 = eq(_T_2464, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2466 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2467 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2468 = eq(_T_2467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2469 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2470 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2471 = eq(_T_2470, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2472 = and(_T_2460, _T_2462) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2473 = and(_T_2472, _T_2463) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2474 = and(_T_2473, _T_2465) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2475 = and(_T_2474, _T_2466) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2476 = and(_T_2475, _T_2468) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2477 = and(_T_2476, _T_2469) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2478 = and(_T_2477, _T_2471) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2479 = or(_T_2459, _T_2478) @[dec_dec_ctl.scala 188:57]
|
|
|
|
|
io.out.zbs <= _T_2479 @[dec_dec_ctl.scala 188:14]
|
|
|
|
|
node _T_2480 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2481 = eq(_T_2480, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2482 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2483 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2484 = eq(_T_2483, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2485 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2486 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2487 = eq(_T_2486, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2488 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2489 = eq(_T_2488, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2490 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2491 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2492 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2493 = eq(_T_2492, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2494 = and(_T_2481, _T_2482) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2495 = and(_T_2494, _T_2484) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2496 = and(_T_2495, _T_2485) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2497 = and(_T_2496, _T_2487) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2498 = and(_T_2497, _T_2489) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2499 = and(_T_2498, _T_2490) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2500 = and(_T_2499, _T_2491) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2501 = and(_T_2500, _T_2493) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.bext <= _T_2501 @[dec_dec_ctl.scala 190:15]
|
|
|
|
|
node _T_2502 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2503 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2504 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2505 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2506 = eq(_T_2505, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2507 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2508 = eq(_T_2507, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2509 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2510 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2511 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2512 = eq(_T_2511, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2513 = and(_T_2502, _T_2503) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2514 = and(_T_2513, _T_2504) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2515 = and(_T_2514, _T_2506) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2516 = and(_T_2515, _T_2508) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2517 = and(_T_2516, _T_2509) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2518 = and(_T_2517, _T_2510) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2519 = and(_T_2518, _T_2512) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.bdep <= _T_2519 @[dec_dec_ctl.scala 192:15]
|
|
|
|
|
node _T_2520 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2521 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2522 = eq(_T_2521, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2523 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2524 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2525 = eq(_T_2524, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2526 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2527 = eq(_T_2526, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2528 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2529 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2530 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2531 = eq(_T_2530, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2532 = and(_T_2520, _T_2522) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2533 = and(_T_2532, _T_2523) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2534 = and(_T_2533, _T_2525) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2535 = and(_T_2534, _T_2527) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2536 = and(_T_2535, _T_2528) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2537 = and(_T_2536, _T_2529) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2538 = and(_T_2537, _T_2531) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.zbe <= _T_2538 @[dec_dec_ctl.scala 194:14]
|
|
|
|
|
node _T_2539 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2540 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2541 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2542 = eq(_T_2541, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2543 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2545 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2546 = eq(_T_2545, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2547 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2548 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2549 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2550 = eq(_T_2549, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2551 = and(_T_2539, _T_2540) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2552 = and(_T_2551, _T_2542) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2553 = and(_T_2552, _T_2544) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2554 = and(_T_2553, _T_2546) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2555 = and(_T_2554, _T_2547) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2556 = and(_T_2555, _T_2548) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2557 = and(_T_2556, _T_2550) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.clmul <= _T_2557 @[dec_dec_ctl.scala 196:16]
|
|
|
|
|
node _T_2558 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2559 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2560 = eq(_T_2559, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2561 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2562 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2563 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2564 = eq(_T_2563, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2565 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2566 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2568 = and(_T_2558, _T_2560) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2569 = and(_T_2568, _T_2561) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2570 = and(_T_2569, _T_2562) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2571 = and(_T_2570, _T_2564) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2572 = and(_T_2571, _T_2565) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2573 = and(_T_2572, _T_2567) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.clmulh <= _T_2573 @[dec_dec_ctl.scala 198:17]
|
|
|
|
|
node _T_2574 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2575 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2576 = eq(_T_2575, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2577 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2578 = eq(_T_2577, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2579 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2580 = eq(_T_2579, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2581 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2582 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2583 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2584 = eq(_T_2583, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2585 = and(_T_2574, _T_2576) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2586 = and(_T_2585, _T_2578) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2587 = and(_T_2586, _T_2580) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2588 = and(_T_2587, _T_2581) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2589 = and(_T_2588, _T_2582) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2590 = and(_T_2589, _T_2584) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.clmulr <= _T_2590 @[dec_dec_ctl.scala 200:17]
|
|
|
|
|
node _T_2591 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2592 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2593 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2594 = eq(_T_2593, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2595 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2596 = eq(_T_2595, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2597 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2598 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2599 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2601 = and(_T_2591, _T_2592) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2602 = and(_T_2601, _T_2594) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2603 = and(_T_2602, _T_2596) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2604 = and(_T_2603, _T_2597) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2605 = and(_T_2604, _T_2598) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2606 = and(_T_2605, _T_2600) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.zbc <= _T_2606 @[dec_dec_ctl.scala 202:14]
|
|
|
|
|
node _T_2607 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2608 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2609 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2610 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2611 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2612 = eq(_T_2611, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2613 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2614 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2615 = eq(_T_2614, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2616 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2617 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2619 = and(_T_2607, _T_2608) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2620 = and(_T_2619, _T_2609) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2621 = and(_T_2620, _T_2610) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2622 = and(_T_2621, _T_2612) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2623 = and(_T_2622, _T_2613) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2624 = and(_T_2623, _T_2615) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2625 = and(_T_2624, _T_2616) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2626 = and(_T_2625, _T_2618) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.grev <= _T_2626 @[dec_dec_ctl.scala 204:15]
|
|
|
|
|
node _T_2627 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2628 = eq(_T_2627, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2629 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2630 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2631 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2632 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2633 = eq(_T_2632, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2634 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2635 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2637 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2638 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2639 = eq(_T_2638, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2640 = and(_T_2628, _T_2629) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2641 = and(_T_2640, _T_2630) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2642 = and(_T_2641, _T_2631) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2643 = and(_T_2642, _T_2633) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2644 = and(_T_2643, _T_2634) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2645 = and(_T_2644, _T_2636) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2646 = and(_T_2645, _T_2637) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2647 = and(_T_2646, _T_2639) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.gorc <= _T_2647 @[dec_dec_ctl.scala 206:15]
|
|
|
|
|
node _T_2648 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2649 = eq(_T_2648, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2650 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2651 = eq(_T_2650, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2652 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2653 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2654 = eq(_T_2653, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2655 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2656 = eq(_T_2655, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2657 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2658 = eq(_T_2657, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2659 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2660 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2661 = eq(_T_2660, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2662 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2663 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2664 = eq(_T_2663, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2665 = and(_T_2649, _T_2651) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2666 = and(_T_2665, _T_2652) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2667 = and(_T_2666, _T_2654) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2668 = and(_T_2667, _T_2656) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2669 = and(_T_2668, _T_2658) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2670 = and(_T_2669, _T_2659) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2671 = and(_T_2670, _T_2661) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2672 = and(_T_2671, _T_2662) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2673 = and(_T_2672, _T_2664) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.shfl <= _T_2673 @[dec_dec_ctl.scala 208:15]
|
|
|
|
|
node _T_2674 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2676 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2677 = eq(_T_2676, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2678 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2679 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2680 = eq(_T_2679, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2681 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2682 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2683 = eq(_T_2682, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2684 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2685 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2686 = eq(_T_2685, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2687 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2688 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2689 = eq(_T_2688, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2690 = and(_T_2675, _T_2677) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2691 = and(_T_2690, _T_2678) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2692 = and(_T_2691, _T_2680) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2693 = and(_T_2692, _T_2681) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2694 = and(_T_2693, _T_2683) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2695 = and(_T_2694, _T_2684) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2696 = and(_T_2695, _T_2686) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2697 = and(_T_2696, _T_2687) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2698 = and(_T_2697, _T_2689) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.unshfl <= _T_2698 @[dec_dec_ctl.scala 210:17]
|
|
|
|
|
node _T_2699 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2700 = eq(_T_2699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2701 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2702 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2703 = eq(_T_2702, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2704 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2705 = eq(_T_2704, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2706 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2707 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2708 = eq(_T_2707, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2709 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2710 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2712 = and(_T_2700, _T_2701) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2713 = and(_T_2712, _T_2703) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2714 = and(_T_2713, _T_2705) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2715 = and(_T_2714, _T_2706) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2716 = and(_T_2715, _T_2708) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2717 = and(_T_2716, _T_2709) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2718 = and(_T_2717, _T_2711) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2719 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2720 = eq(_T_2719, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2721 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2722 = eq(_T_2721, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2723 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2724 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2725 = eq(_T_2724, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2726 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2727 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2728 = eq(_T_2727, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2729 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2730 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2731 = eq(_T_2730, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2732 = and(_T_2720, _T_2722) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2733 = and(_T_2732, _T_2723) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2734 = and(_T_2733, _T_2725) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2735 = and(_T_2734, _T_2726) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2736 = and(_T_2735, _T_2728) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2737 = and(_T_2736, _T_2729) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2738 = and(_T_2737, _T_2731) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2739 = or(_T_2718, _T_2738) @[dec_dec_ctl.scala 212:58]
|
|
|
|
|
node _T_2740 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2741 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2742 = eq(_T_2741, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2743 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2744 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2745 = eq(_T_2744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2746 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2747 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2748 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2749 = eq(_T_2748, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2750 = and(_T_2740, _T_2742) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2751 = and(_T_2750, _T_2743) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2752 = and(_T_2751, _T_2745) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2753 = and(_T_2752, _T_2746) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2754 = and(_T_2753, _T_2747) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2755 = and(_T_2754, _T_2749) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2756 = or(_T_2739, _T_2755) @[dec_dec_ctl.scala 212:101]
|
|
|
|
|
node _T_2757 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2758 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2759 = eq(_T_2758, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2760 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2761 = eq(_T_2760, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2762 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2763 = eq(_T_2762, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2764 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2765 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2766 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2767 = eq(_T_2766, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2768 = and(_T_2757, _T_2759) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2769 = and(_T_2768, _T_2761) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2770 = and(_T_2769, _T_2763) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2771 = and(_T_2770, _T_2764) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2772 = and(_T_2771, _T_2765) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2773 = and(_T_2772, _T_2767) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2774 = or(_T_2756, _T_2773) @[dec_dec_ctl.scala 213:40]
|
|
|
|
|
node _T_2775 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2776 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2777 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2778 = eq(_T_2777, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2779 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2780 = eq(_T_2779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2781 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2782 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2783 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2784 = eq(_T_2783, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2785 = and(_T_2775, _T_2776) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2786 = and(_T_2785, _T_2778) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2787 = and(_T_2786, _T_2780) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2788 = and(_T_2787, _T_2781) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2789 = and(_T_2788, _T_2782) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2790 = and(_T_2789, _T_2784) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2791 = or(_T_2774, _T_2790) @[dec_dec_ctl.scala 213:79]
|
|
|
|
|
node _T_2792 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2793 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2794 = eq(_T_2793, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2795 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2796 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2797 = eq(_T_2796, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2798 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2799 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2800 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2802 = and(_T_2792, _T_2794) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2803 = and(_T_2802, _T_2795) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2804 = and(_T_2803, _T_2797) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2805 = and(_T_2804, _T_2798) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2806 = and(_T_2805, _T_2799) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2807 = and(_T_2806, _T_2801) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2808 = or(_T_2791, _T_2807) @[dec_dec_ctl.scala 214:41]
|
|
|
|
|
node _T_2809 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2810 = eq(_T_2809, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2811 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2812 = eq(_T_2811, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2813 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2814 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2815 = eq(_T_2814, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2816 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2817 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2818 = eq(_T_2817, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2819 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2820 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2821 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2822 = eq(_T_2821, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2823 = and(_T_2810, _T_2812) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2824 = and(_T_2823, _T_2813) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2825 = and(_T_2824, _T_2815) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2826 = and(_T_2825, _T_2816) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2827 = and(_T_2826, _T_2818) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2828 = and(_T_2827, _T_2819) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2829 = and(_T_2828, _T_2820) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2830 = and(_T_2829, _T_2822) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2831 = or(_T_2808, _T_2830) @[dec_dec_ctl.scala 214:78]
|
|
|
|
|
node _T_2832 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2833 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2834 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2835 = eq(_T_2834, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2836 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2837 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2838 = eq(_T_2837, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2839 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2840 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2841 = eq(_T_2840, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2842 = and(_T_2832, _T_2833) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2843 = and(_T_2842, _T_2835) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2844 = and(_T_2843, _T_2836) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2845 = and(_T_2844, _T_2838) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2846 = and(_T_2845, _T_2839) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2847 = and(_T_2846, _T_2841) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2848 = or(_T_2831, _T_2847) @[dec_dec_ctl.scala 215:48]
|
|
|
|
|
io.out.zbp <= _T_2848 @[dec_dec_ctl.scala 212:14]
|
|
|
|
|
node _T_2849 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2850 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2851 = eq(_T_2850, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2852 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2853 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2854 = eq(_T_2853, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2855 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2856 = eq(_T_2855, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2857 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2858 = eq(_T_2857, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2859 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2860 = eq(_T_2859, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2861 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2862 = eq(_T_2861, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2863 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2864 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2865 = eq(_T_2864, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2866 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2867 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2868 = eq(_T_2867, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2869 = and(_T_2849, _T_2851) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2870 = and(_T_2869, _T_2852) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2871 = and(_T_2870, _T_2854) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2872 = and(_T_2871, _T_2856) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2873 = and(_T_2872, _T_2858) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2874 = and(_T_2873, _T_2860) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2875 = and(_T_2874, _T_2862) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2876 = and(_T_2875, _T_2863) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2877 = and(_T_2876, _T_2865) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2878 = and(_T_2877, _T_2866) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2879 = and(_T_2878, _T_2868) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.crc32_b <= _T_2879 @[dec_dec_ctl.scala 217:18]
|
|
|
|
|
node _T_2880 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2881 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2882 = eq(_T_2881, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2883 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2884 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2885 = eq(_T_2884, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2886 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2887 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2888 = eq(_T_2887, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2889 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2890 = eq(_T_2889, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2891 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2892 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2893 = eq(_T_2892, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2894 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2895 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2896 = eq(_T_2895, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2897 = and(_T_2880, _T_2882) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2898 = and(_T_2897, _T_2883) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2899 = and(_T_2898, _T_2885) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2900 = and(_T_2899, _T_2886) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2901 = and(_T_2900, _T_2888) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2902 = and(_T_2901, _T_2890) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2903 = and(_T_2902, _T_2891) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2904 = and(_T_2903, _T_2893) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2905 = and(_T_2904, _T_2894) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2906 = and(_T_2905, _T_2896) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.crc32_h <= _T_2906 @[dec_dec_ctl.scala 219:18]
|
|
|
|
|
node _T_2907 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2908 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2909 = eq(_T_2908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2910 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2911 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2912 = eq(_T_2911, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2913 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2914 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2915 = eq(_T_2914, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2916 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2917 = eq(_T_2916, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2918 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2919 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2920 = eq(_T_2919, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2921 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2922 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2923 = eq(_T_2922, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2924 = and(_T_2907, _T_2909) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2925 = and(_T_2924, _T_2910) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2926 = and(_T_2925, _T_2912) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2927 = and(_T_2926, _T_2913) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2928 = and(_T_2927, _T_2915) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2929 = and(_T_2928, _T_2917) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2930 = and(_T_2929, _T_2918) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2931 = and(_T_2930, _T_2920) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2932 = and(_T_2931, _T_2921) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2933 = and(_T_2932, _T_2923) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.crc32_w <= _T_2933 @[dec_dec_ctl.scala 221:18]
|
|
|
|
|
node _T_2934 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2935 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2937 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2938 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2939 = eq(_T_2938, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2940 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2941 = eq(_T_2940, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2942 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2943 = eq(_T_2942, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2944 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2945 = eq(_T_2944, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2946 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2947 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2948 = eq(_T_2947, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2949 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2950 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2951 = eq(_T_2950, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2952 = and(_T_2934, _T_2936) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2953 = and(_T_2952, _T_2937) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2954 = and(_T_2953, _T_2939) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2955 = and(_T_2954, _T_2941) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2956 = and(_T_2955, _T_2943) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2957 = and(_T_2956, _T_2945) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2958 = and(_T_2957, _T_2946) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2959 = and(_T_2958, _T_2948) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2960 = and(_T_2959, _T_2949) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2961 = and(_T_2960, _T_2951) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.crc32c_b <= _T_2961 @[dec_dec_ctl.scala 223:19]
|
|
|
|
|
node _T_2962 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2963 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2964 = eq(_T_2963, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2965 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2966 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2967 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2968 = eq(_T_2967, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2969 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2970 = eq(_T_2969, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2971 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2972 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2973 = eq(_T_2972, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2974 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2975 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2976 = eq(_T_2975, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2977 = and(_T_2962, _T_2964) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2978 = and(_T_2977, _T_2965) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2979 = and(_T_2978, _T_2966) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2980 = and(_T_2979, _T_2968) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2981 = and(_T_2980, _T_2970) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2982 = and(_T_2981, _T_2971) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2983 = and(_T_2982, _T_2973) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2984 = and(_T_2983, _T_2974) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_2985 = and(_T_2984, _T_2976) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.crc32c_h <= _T_2985 @[dec_dec_ctl.scala 225:19]
|
|
|
|
|
node _T_2986 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2987 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2988 = eq(_T_2987, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2989 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2990 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2991 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2992 = eq(_T_2991, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2993 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2994 = eq(_T_2993, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2995 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2996 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_2997 = eq(_T_2996, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_2998 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_2999 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3000 = eq(_T_2999, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3001 = and(_T_2986, _T_2988) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3002 = and(_T_3001, _T_2989) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3003 = and(_T_3002, _T_2990) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3004 = and(_T_3003, _T_2992) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3005 = and(_T_3004, _T_2994) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3006 = and(_T_3005, _T_2995) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3007 = and(_T_3006, _T_2997) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3008 = and(_T_3007, _T_2998) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3009 = and(_T_3008, _T_3000) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.crc32c_w <= _T_3009 @[dec_dec_ctl.scala 227:19]
|
|
|
|
|
node _T_3010 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3011 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3012 = eq(_T_3011, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3013 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3014 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3015 = eq(_T_3014, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3016 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3017 = eq(_T_3016, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3018 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3019 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3020 = eq(_T_3019, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3021 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3022 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3023 = eq(_T_3022, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3024 = and(_T_3010, _T_3012) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3025 = and(_T_3024, _T_3013) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3026 = and(_T_3025, _T_3015) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3027 = and(_T_3026, _T_3017) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3028 = and(_T_3027, _T_3018) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3029 = and(_T_3028, _T_3020) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3030 = and(_T_3029, _T_3021) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3031 = and(_T_3030, _T_3023) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.zbr <= _T_3031 @[dec_dec_ctl.scala 229:14]
|
|
|
|
|
node _T_3032 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3033 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3034 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3035 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3036 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3037 = eq(_T_3036, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3038 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3039 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3040 = eq(_T_3039, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3041 = and(_T_3032, _T_3033) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3042 = and(_T_3041, _T_3034) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3043 = and(_T_3042, _T_3035) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3044 = and(_T_3043, _T_3037) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3045 = and(_T_3044, _T_3038) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3046 = and(_T_3045, _T_3040) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.bfp <= _T_3046 @[dec_dec_ctl.scala 231:14]
|
|
|
|
|
node _T_3047 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3048 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3049 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3050 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3051 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3052 = eq(_T_3051, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3053 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3054 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3055 = eq(_T_3054, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3056 = and(_T_3047, _T_3048) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3057 = and(_T_3056, _T_3049) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3058 = and(_T_3057, _T_3050) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3059 = and(_T_3058, _T_3052) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3060 = and(_T_3059, _T_3053) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3061 = and(_T_3060, _T_3055) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.zbf <= _T_3061 @[dec_dec_ctl.scala 233:14]
|
|
|
|
|
node _T_3062 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3063 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3064 = eq(_T_3063, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3065 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3066 = eq(_T_3065, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3067 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3068 = eq(_T_3067, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3069 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3070 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3071 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3072 = eq(_T_3071, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3073 = and(_T_3062, _T_3064) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3074 = and(_T_3073, _T_3066) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3075 = and(_T_3074, _T_3068) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3076 = and(_T_3075, _T_3069) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3077 = and(_T_3076, _T_3070) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3078 = and(_T_3077, _T_3072) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sh1add <= _T_3078 @[dec_dec_ctl.scala 235:17]
|
|
|
|
|
node _T_3079 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3080 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3081 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3082 = eq(_T_3081, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3083 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3084 = eq(_T_3083, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3085 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3086 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3087 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3088 = eq(_T_3087, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3089 = and(_T_3079, _T_3080) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3090 = and(_T_3089, _T_3082) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3091 = and(_T_3090, _T_3084) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3092 = and(_T_3091, _T_3085) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3093 = and(_T_3092, _T_3086) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3094 = and(_T_3093, _T_3088) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sh2add <= _T_3094 @[dec_dec_ctl.scala 237:17]
|
|
|
|
|
node _T_3095 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3096 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3097 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3098 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3099 = eq(_T_3098, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3100 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3101 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3102 = eq(_T_3101, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3103 = and(_T_3095, _T_3096) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3104 = and(_T_3103, _T_3097) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3105 = and(_T_3104, _T_3099) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3106 = and(_T_3105, _T_3100) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3107 = and(_T_3106, _T_3102) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.sh3add <= _T_3107 @[dec_dec_ctl.scala 239:17]
|
|
|
|
|
node _T_3108 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3109 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3110 = eq(_T_3109, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3111 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3112 = eq(_T_3111, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3113 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3114 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3115 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3116 = eq(_T_3115, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3117 = and(_T_3108, _T_3110) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3118 = and(_T_3117, _T_3112) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3119 = and(_T_3118, _T_3113) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3120 = and(_T_3119, _T_3114) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3121 = and(_T_3120, _T_3116) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
io.out.zba <= _T_3121 @[dec_dec_ctl.scala 241:14]
|
|
|
|
|
node _T_3122 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3123 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3124 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3125 = eq(_T_3124, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3126 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3127 = eq(_T_3126, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3128 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3129 = and(_T_3122, _T_3123) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3130 = and(_T_3129, _T_3125) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3131 = and(_T_3130, _T_3127) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3132 = and(_T_3131, _T_3128) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3133 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3134 = eq(_T_3133, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3135 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3136 = eq(_T_3135, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3137 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3138 = eq(_T_3137, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3139 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3141 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3142 = eq(_T_3141, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3143 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3144 = and(_T_3134, _T_3136) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3145 = and(_T_3144, _T_3138) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3146 = and(_T_3145, _T_3140) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3147 = and(_T_3146, _T_3142) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3148 = and(_T_3147, _T_3143) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3149 = or(_T_3132, _T_3148) @[dec_dec_ctl.scala 243:51]
|
|
|
|
|
node _T_3150 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3151 = eq(_T_3150, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3152 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3153 = eq(_T_3152, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3154 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3155 = eq(_T_3154, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3156 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3157 = eq(_T_3156, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3158 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3159 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3160 = eq(_T_3159, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3161 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3162 = and(_T_3151, _T_3153) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3163 = and(_T_3162, _T_3155) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3164 = and(_T_3163, _T_3157) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3165 = and(_T_3164, _T_3158) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3166 = and(_T_3165, _T_3160) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3167 = and(_T_3166, _T_3161) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3168 = or(_T_3149, _T_3167) @[dec_dec_ctl.scala 243:89]
|
|
|
|
|
node _T_3169 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3170 = eq(_T_3169, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3171 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3172 = eq(_T_3171, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3173 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3174 = eq(_T_3173, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3175 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3176 = eq(_T_3175, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3177 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3178 = eq(_T_3177, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3179 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3180 = and(_T_3170, _T_3172) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3181 = and(_T_3180, _T_3174) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3182 = and(_T_3181, _T_3176) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3183 = and(_T_3182, _T_3178) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3184 = and(_T_3183, _T_3179) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3185 = or(_T_3168, _T_3184) @[dec_dec_ctl.scala 244:44]
|
|
|
|
|
node _T_3186 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3187 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3188 = eq(_T_3187, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3189 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3190 = and(_T_3186, _T_3188) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3191 = and(_T_3190, _T_3189) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3192 = or(_T_3185, _T_3191) @[dec_dec_ctl.scala 244:82]
|
|
|
|
|
node _T_3193 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3194 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3195 = and(_T_3193, _T_3194) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3196 = or(_T_3192, _T_3195) @[dec_dec_ctl.scala 245:28]
|
|
|
|
|
node _T_3197 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3198 = eq(_T_3197, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3199 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3200 = eq(_T_3199, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3201 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3202 = and(_T_3198, _T_3200) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3203 = and(_T_3202, _T_3201) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3204 = or(_T_3196, _T_3203) @[dec_dec_ctl.scala 245:49]
|
|
|
|
|
io.out.pm_alu <= _T_3204 @[dec_dec_ctl.scala 243:17]
|
|
|
|
|
node _T_3205 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3206 = eq(_T_3205, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3207 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3208 = eq(_T_3207, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3209 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3210 = eq(_T_3209, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3211 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3212 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3213 = eq(_T_3212, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3214 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3215 = eq(_T_3214, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3216 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3217 = eq(_T_3216, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3218 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3219 = eq(_T_3218, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3220 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3221 = eq(_T_3220, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3222 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3223 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3225 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3226 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3227 = eq(_T_3226, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3228 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3229 = eq(_T_3228, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3230 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3231 = eq(_T_3230, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3232 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3233 = eq(_T_3232, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3234 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3235 = eq(_T_3234, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3236 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3237 = eq(_T_3236, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3238 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3239 = eq(_T_3238, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3240 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3241 = eq(_T_3240, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3242 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3243 = eq(_T_3242, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3244 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3245 = eq(_T_3244, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3246 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3247 = eq(_T_3246, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3248 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3249 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3250 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3251 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3252 = eq(_T_3251, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3253 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3254 = eq(_T_3253, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3255 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3256 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3257 = and(_T_3206, _T_3208) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3258 = and(_T_3257, _T_3210) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3259 = and(_T_3258, _T_3211) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3260 = and(_T_3259, _T_3213) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3261 = and(_T_3260, _T_3215) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3262 = and(_T_3261, _T_3217) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3263 = and(_T_3262, _T_3219) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3264 = and(_T_3263, _T_3221) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3265 = and(_T_3264, _T_3222) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3266 = and(_T_3265, _T_3224) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3267 = and(_T_3266, _T_3225) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3268 = and(_T_3267, _T_3227) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3269 = and(_T_3268, _T_3229) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3270 = and(_T_3269, _T_3231) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3271 = and(_T_3270, _T_3233) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3272 = and(_T_3271, _T_3235) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3273 = and(_T_3272, _T_3237) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3274 = and(_T_3273, _T_3239) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3275 = and(_T_3274, _T_3241) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3276 = and(_T_3275, _T_3243) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3277 = and(_T_3276, _T_3245) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3278 = and(_T_3277, _T_3247) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3279 = and(_T_3278, _T_3248) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3280 = and(_T_3279, _T_3249) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3281 = and(_T_3280, _T_3250) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3282 = and(_T_3281, _T_3252) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3283 = and(_T_3282, _T_3254) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3284 = and(_T_3283, _T_3255) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3285 = and(_T_3284, _T_3256) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3286 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3287 = eq(_T_3286, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3288 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3289 = eq(_T_3288, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3290 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3291 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3292 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3293 = eq(_T_3292, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3294 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3295 = eq(_T_3294, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3296 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3297 = eq(_T_3296, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3298 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3299 = eq(_T_3298, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3300 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3301 = eq(_T_3300, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3302 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3303 = eq(_T_3302, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3304 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3305 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3306 = eq(_T_3305, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3307 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3308 = eq(_T_3307, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3309 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3310 = eq(_T_3309, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3311 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3312 = eq(_T_3311, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3313 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3314 = eq(_T_3313, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3315 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3316 = eq(_T_3315, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3317 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3318 = eq(_T_3317, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3319 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3320 = eq(_T_3319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3321 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3322 = eq(_T_3321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3323 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3324 = eq(_T_3323, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3325 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3326 = eq(_T_3325, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3327 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3328 = eq(_T_3327, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3329 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3330 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3331 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3332 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3333 = eq(_T_3332, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3334 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3335 = eq(_T_3334, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3336 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
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|
|
|
|
node _T_3337 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3338 = and(_T_3287, _T_3289) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3339 = and(_T_3338, _T_3290) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3340 = and(_T_3339, _T_3291) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3341 = and(_T_3340, _T_3293) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3342 = and(_T_3341, _T_3295) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3343 = and(_T_3342, _T_3297) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3344 = and(_T_3343, _T_3299) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3345 = and(_T_3344, _T_3301) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3346 = and(_T_3345, _T_3303) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3347 = and(_T_3346, _T_3304) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3348 = and(_T_3347, _T_3306) @[dec_dec_ctl.scala 17:17]
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|
|
|
|
node _T_3349 = and(_T_3348, _T_3308) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_3350 = and(_T_3349, _T_3310) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3351 = and(_T_3350, _T_3312) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3352 = and(_T_3351, _T_3314) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3353 = and(_T_3352, _T_3316) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_3354 = and(_T_3353, _T_3318) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3355 = and(_T_3354, _T_3320) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3356 = and(_T_3355, _T_3322) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3357 = and(_T_3356, _T_3324) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3358 = and(_T_3357, _T_3326) @[dec_dec_ctl.scala 17:17]
|
|
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|
|
node _T_3359 = and(_T_3358, _T_3328) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3360 = and(_T_3359, _T_3329) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3361 = and(_T_3360, _T_3330) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3362 = and(_T_3361, _T_3331) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3363 = and(_T_3362, _T_3333) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3364 = and(_T_3363, _T_3335) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3365 = and(_T_3364, _T_3336) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3366 = and(_T_3365, _T_3337) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3367 = or(_T_3285, _T_3366) @[dec_dec_ctl.scala 248:136]
|
|
|
|
|
node _T_3368 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3369 = eq(_T_3368, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3370 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3371 = eq(_T_3370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3372 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3373 = eq(_T_3372, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3374 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3375 = eq(_T_3374, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3376 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3377 = eq(_T_3376, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3378 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3379 = eq(_T_3378, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3380 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3381 = eq(_T_3380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3382 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3383 = eq(_T_3382, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3384 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3385 = eq(_T_3384, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3386 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3387 = eq(_T_3386, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3388 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3389 = eq(_T_3388, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3390 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3391 = eq(_T_3390, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3392 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3393 = eq(_T_3392, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3394 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3395 = eq(_T_3394, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3396 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3397 = eq(_T_3396, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3398 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3399 = eq(_T_3398, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3400 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3401 = eq(_T_3400, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3402 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3403 = eq(_T_3402, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3404 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3405 = eq(_T_3404, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3406 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3407 = eq(_T_3406, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3408 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3409 = eq(_T_3408, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3410 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3411 = eq(_T_3410, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3412 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3413 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3414 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3415 = eq(_T_3414, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3416 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3417 = eq(_T_3416, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3418 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3419 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3420 = and(_T_3369, _T_3371) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3421 = and(_T_3420, _T_3373) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3422 = and(_T_3421, _T_3375) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3423 = and(_T_3422, _T_3377) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3424 = and(_T_3423, _T_3379) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3425 = and(_T_3424, _T_3381) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3426 = and(_T_3425, _T_3383) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3427 = and(_T_3426, _T_3385) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3428 = and(_T_3427, _T_3387) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3429 = and(_T_3428, _T_3389) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3430 = and(_T_3429, _T_3391) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3431 = and(_T_3430, _T_3393) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3432 = and(_T_3431, _T_3395) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3433 = and(_T_3432, _T_3397) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3434 = and(_T_3433, _T_3399) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3435 = and(_T_3434, _T_3401) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3436 = and(_T_3435, _T_3403) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3437 = and(_T_3436, _T_3405) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3438 = and(_T_3437, _T_3407) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3439 = and(_T_3438, _T_3409) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3440 = and(_T_3439, _T_3411) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3441 = and(_T_3440, _T_3412) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3442 = and(_T_3441, _T_3413) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3443 = and(_T_3442, _T_3415) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3444 = and(_T_3443, _T_3417) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3445 = and(_T_3444, _T_3418) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3446 = and(_T_3445, _T_3419) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3447 = or(_T_3367, _T_3446) @[dec_dec_ctl.scala 249:122]
|
|
|
|
|
node _T_3448 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3449 = eq(_T_3448, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3450 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3451 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3452 = eq(_T_3451, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3453 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3454 = eq(_T_3453, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3455 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3456 = eq(_T_3455, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3457 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3458 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3459 = eq(_T_3458, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3460 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3461 = eq(_T_3460, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3462 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3463 = eq(_T_3462, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3464 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3465 = eq(_T_3464, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3466 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3467 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3468 = eq(_T_3467, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3469 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3470 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3471 = and(_T_3449, _T_3450) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3472 = and(_T_3471, _T_3452) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3473 = and(_T_3472, _T_3454) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3474 = and(_T_3473, _T_3456) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3475 = and(_T_3474, _T_3457) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3476 = and(_T_3475, _T_3459) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3477 = and(_T_3476, _T_3461) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3478 = and(_T_3477, _T_3463) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3479 = and(_T_3478, _T_3465) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3480 = and(_T_3479, _T_3466) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3481 = and(_T_3480, _T_3468) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3482 = and(_T_3481, _T_3469) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3483 = and(_T_3482, _T_3470) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3484 = or(_T_3447, _T_3483) @[dec_dec_ctl.scala 250:119]
|
|
|
|
|
node _T_3485 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3486 = eq(_T_3485, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3487 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3488 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3489 = eq(_T_3488, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3490 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3491 = eq(_T_3490, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3492 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3493 = eq(_T_3492, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3494 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3495 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3496 = eq(_T_3495, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3497 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3498 = eq(_T_3497, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3499 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3500 = eq(_T_3499, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3501 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3502 = eq(_T_3501, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3503 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3504 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3505 = eq(_T_3504, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3506 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3507 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3508 = and(_T_3486, _T_3487) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3509 = and(_T_3508, _T_3489) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3510 = and(_T_3509, _T_3491) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3511 = and(_T_3510, _T_3493) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3512 = and(_T_3511, _T_3494) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3513 = and(_T_3512, _T_3496) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3514 = and(_T_3513, _T_3498) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3515 = and(_T_3514, _T_3500) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3516 = and(_T_3515, _T_3502) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3517 = and(_T_3516, _T_3503) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3518 = and(_T_3517, _T_3505) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3519 = and(_T_3518, _T_3506) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3520 = and(_T_3519, _T_3507) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3521 = or(_T_3484, _T_3520) @[dec_dec_ctl.scala 251:65]
|
|
|
|
|
node _T_3522 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3523 = eq(_T_3522, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3524 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3525 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3526 = eq(_T_3525, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3527 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3528 = eq(_T_3527, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3529 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3530 = eq(_T_3529, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3531 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3532 = eq(_T_3531, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3533 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3534 = eq(_T_3533, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3535 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3536 = eq(_T_3535, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3537 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3538 = eq(_T_3537, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3539 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3540 = eq(_T_3539, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3541 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3542 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3543 = eq(_T_3542, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3544 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3545 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3546 = and(_T_3523, _T_3524) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3547 = and(_T_3546, _T_3526) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3548 = and(_T_3547, _T_3528) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3549 = and(_T_3548, _T_3530) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3550 = and(_T_3549, _T_3532) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3551 = and(_T_3550, _T_3534) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3552 = and(_T_3551, _T_3536) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3553 = and(_T_3552, _T_3538) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3554 = and(_T_3553, _T_3540) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3555 = and(_T_3554, _T_3541) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3556 = and(_T_3555, _T_3543) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3557 = and(_T_3556, _T_3544) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3558 = and(_T_3557, _T_3545) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3559 = or(_T_3521, _T_3558) @[dec_dec_ctl.scala 251:127]
|
|
|
|
|
node _T_3560 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3561 = eq(_T_3560, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3562 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3563 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3564 = eq(_T_3563, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3565 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3566 = eq(_T_3565, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3567 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3568 = eq(_T_3567, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3569 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3570 = eq(_T_3569, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3571 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3572 = eq(_T_3571, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3573 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3574 = eq(_T_3573, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3575 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3576 = eq(_T_3575, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3577 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3578 = eq(_T_3577, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3579 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3580 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3581 = eq(_T_3580, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3582 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3583 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3584 = and(_T_3561, _T_3562) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3585 = and(_T_3584, _T_3564) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3586 = and(_T_3585, _T_3566) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3587 = and(_T_3586, _T_3568) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3588 = and(_T_3587, _T_3570) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3589 = and(_T_3588, _T_3572) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3590 = and(_T_3589, _T_3574) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3591 = and(_T_3590, _T_3576) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3592 = and(_T_3591, _T_3578) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3593 = and(_T_3592, _T_3579) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3594 = and(_T_3593, _T_3581) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3595 = and(_T_3594, _T_3582) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3596 = and(_T_3595, _T_3583) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3597 = or(_T_3559, _T_3596) @[dec_dec_ctl.scala 252:66]
|
|
|
|
|
node _T_3598 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3600 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3601 = eq(_T_3600, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3602 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3603 = eq(_T_3602, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3604 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3605 = eq(_T_3604, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3606 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3607 = eq(_T_3606, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3608 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3609 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3610 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3611 = eq(_T_3610, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3612 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3613 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3614 = eq(_T_3613, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3615 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3616 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3617 = and(_T_3599, _T_3601) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3618 = and(_T_3617, _T_3603) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3619 = and(_T_3618, _T_3605) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3620 = and(_T_3619, _T_3607) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3621 = and(_T_3620, _T_3608) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3622 = and(_T_3621, _T_3609) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3623 = and(_T_3622, _T_3611) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3624 = and(_T_3623, _T_3612) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3625 = and(_T_3624, _T_3614) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3626 = and(_T_3625, _T_3615) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3627 = and(_T_3626, _T_3616) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3628 = or(_T_3597, _T_3627) @[dec_dec_ctl.scala 252:129]
|
|
|
|
|
node _T_3629 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3630 = eq(_T_3629, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3631 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3632 = eq(_T_3631, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3633 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3634 = eq(_T_3633, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3635 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3636 = eq(_T_3635, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3637 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3638 = eq(_T_3637, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3639 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3640 = eq(_T_3639, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3641 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3642 = eq(_T_3641, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3643 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3644 = eq(_T_3643, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3645 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3646 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3647 = eq(_T_3646, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3648 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3649 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3650 = and(_T_3630, _T_3632) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3651 = and(_T_3650, _T_3634) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3652 = and(_T_3651, _T_3636) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3653 = and(_T_3652, _T_3638) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3654 = and(_T_3653, _T_3640) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3655 = and(_T_3654, _T_3642) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3656 = and(_T_3655, _T_3644) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3657 = and(_T_3656, _T_3645) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3658 = and(_T_3657, _T_3647) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3659 = and(_T_3658, _T_3648) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3660 = and(_T_3659, _T_3649) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3661 = or(_T_3628, _T_3660) @[dec_dec_ctl.scala 253:58]
|
|
|
|
|
node _T_3662 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3663 = eq(_T_3662, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3664 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3665 = eq(_T_3664, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3666 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3667 = eq(_T_3666, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3668 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3669 = eq(_T_3668, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3670 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3671 = eq(_T_3670, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3672 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3673 = eq(_T_3672, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3674 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3675 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3676 = eq(_T_3675, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3677 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3678 = eq(_T_3677, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3679 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3680 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3681 = eq(_T_3680, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3682 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3683 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3684 = and(_T_3663, _T_3665) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3685 = and(_T_3684, _T_3667) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3686 = and(_T_3685, _T_3669) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3687 = and(_T_3686, _T_3671) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3688 = and(_T_3687, _T_3673) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3689 = and(_T_3688, _T_3674) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3690 = and(_T_3689, _T_3676) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3691 = and(_T_3690, _T_3678) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3692 = and(_T_3691, _T_3679) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3693 = and(_T_3692, _T_3681) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3694 = and(_T_3693, _T_3682) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3695 = and(_T_3694, _T_3683) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3696 = or(_T_3661, _T_3695) @[dec_dec_ctl.scala 253:114]
|
|
|
|
|
node _T_3697 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3698 = eq(_T_3697, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3699 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3700 = eq(_T_3699, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3701 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3702 = eq(_T_3701, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3703 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3704 = eq(_T_3703, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3705 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3706 = eq(_T_3705, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3707 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3708 = eq(_T_3707, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3709 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3710 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3711 = eq(_T_3710, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3712 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3713 = eq(_T_3712, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3714 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3715 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3716 = eq(_T_3715, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3717 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3718 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3719 = and(_T_3698, _T_3700) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3720 = and(_T_3719, _T_3702) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3721 = and(_T_3720, _T_3704) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3722 = and(_T_3721, _T_3706) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3723 = and(_T_3722, _T_3708) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3724 = and(_T_3723, _T_3709) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3725 = and(_T_3724, _T_3711) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3726 = and(_T_3725, _T_3713) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3727 = and(_T_3726, _T_3714) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3728 = and(_T_3727, _T_3716) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3729 = and(_T_3728, _T_3717) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3730 = and(_T_3729, _T_3718) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3731 = or(_T_3696, _T_3730) @[dec_dec_ctl.scala 254:63]
|
|
|
|
|
node _T_3732 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3733 = eq(_T_3732, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3734 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3735 = eq(_T_3734, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3736 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3737 = eq(_T_3736, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3738 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3739 = eq(_T_3738, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3740 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3741 = eq(_T_3740, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3742 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3743 = eq(_T_3742, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3744 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3745 = eq(_T_3744, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3746 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3747 = eq(_T_3746, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3748 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3749 = eq(_T_3748, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3750 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3751 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3752 = eq(_T_3751, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3753 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3754 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3755 = and(_T_3733, _T_3735) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3756 = and(_T_3755, _T_3737) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3757 = and(_T_3756, _T_3739) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3758 = and(_T_3757, _T_3741) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3759 = and(_T_3758, _T_3743) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3760 = and(_T_3759, _T_3745) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3761 = and(_T_3760, _T_3747) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3762 = and(_T_3761, _T_3749) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3763 = and(_T_3762, _T_3750) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3764 = and(_T_3763, _T_3752) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3765 = and(_T_3764, _T_3753) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3766 = and(_T_3765, _T_3754) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3767 = or(_T_3731, _T_3766) @[dec_dec_ctl.scala 254:123]
|
|
|
|
|
node _T_3768 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3769 = eq(_T_3768, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3770 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3771 = eq(_T_3770, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3772 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3773 = eq(_T_3772, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3774 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3775 = eq(_T_3774, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3776 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3777 = eq(_T_3776, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3778 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3779 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3780 = eq(_T_3779, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3781 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3782 = eq(_T_3781, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3783 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3784 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3786 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3787 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3788 = and(_T_3769, _T_3771) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3789 = and(_T_3788, _T_3773) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3790 = and(_T_3789, _T_3775) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3791 = and(_T_3790, _T_3777) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3792 = and(_T_3791, _T_3778) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3793 = and(_T_3792, _T_3780) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3794 = and(_T_3793, _T_3782) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3795 = and(_T_3794, _T_3783) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3796 = and(_T_3795, _T_3785) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3797 = and(_T_3796, _T_3786) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3798 = and(_T_3797, _T_3787) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3799 = or(_T_3767, _T_3798) @[dec_dec_ctl.scala 255:64]
|
|
|
|
|
node _T_3800 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3802 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3803 = eq(_T_3802, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3804 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3805 = eq(_T_3804, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3806 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3807 = eq(_T_3806, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3808 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3809 = eq(_T_3808, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3810 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3811 = eq(_T_3810, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3812 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3813 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3814 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3815 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3816 = eq(_T_3815, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3817 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3818 = eq(_T_3817, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3819 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3820 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3821 = and(_T_3801, _T_3803) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3822 = and(_T_3821, _T_3805) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3823 = and(_T_3822, _T_3807) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3824 = and(_T_3823, _T_3809) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3825 = and(_T_3824, _T_3811) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3826 = and(_T_3825, _T_3812) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3827 = and(_T_3826, _T_3813) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3828 = and(_T_3827, _T_3814) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3829 = and(_T_3828, _T_3816) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3830 = and(_T_3829, _T_3818) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3831 = and(_T_3830, _T_3819) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3832 = and(_T_3831, _T_3820) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3833 = or(_T_3799, _T_3832) @[dec_dec_ctl.scala 255:119]
|
|
|
|
|
node _T_3834 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3835 = eq(_T_3834, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3836 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3837 = eq(_T_3836, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3838 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3839 = eq(_T_3838, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3840 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3841 = eq(_T_3840, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3842 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3843 = eq(_T_3842, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3844 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3845 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3846 = eq(_T_3845, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3847 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3848 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3849 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3850 = eq(_T_3849, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3851 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3852 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3853 = and(_T_3835, _T_3837) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3854 = and(_T_3853, _T_3839) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3855 = and(_T_3854, _T_3841) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3856 = and(_T_3855, _T_3843) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3857 = and(_T_3856, _T_3844) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3858 = and(_T_3857, _T_3846) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3859 = and(_T_3858, _T_3847) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3860 = and(_T_3859, _T_3848) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3861 = and(_T_3860, _T_3850) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3862 = and(_T_3861, _T_3851) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3863 = and(_T_3862, _T_3852) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3864 = or(_T_3833, _T_3863) @[dec_dec_ctl.scala 256:61]
|
|
|
|
|
node _T_3865 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3866 = eq(_T_3865, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3867 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3868 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3869 = eq(_T_3868, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3870 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3871 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3872 = eq(_T_3871, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3873 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3874 = eq(_T_3873, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3875 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3876 = eq(_T_3875, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3877 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3878 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3879 = eq(_T_3878, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3880 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3881 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3882 = eq(_T_3881, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3883 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3884 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3885 = and(_T_3866, _T_3867) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3886 = and(_T_3885, _T_3869) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3887 = and(_T_3886, _T_3870) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3888 = and(_T_3887, _T_3872) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3889 = and(_T_3888, _T_3874) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3890 = and(_T_3889, _T_3876) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3891 = and(_T_3890, _T_3877) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3892 = and(_T_3891, _T_3879) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3893 = and(_T_3892, _T_3880) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3894 = and(_T_3893, _T_3882) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3895 = and(_T_3894, _T_3883) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3896 = and(_T_3895, _T_3884) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3897 = or(_T_3864, _T_3896) @[dec_dec_ctl.scala 256:115]
|
|
|
|
|
node _T_3898 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3899 = eq(_T_3898, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3900 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3901 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3902 = eq(_T_3901, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3903 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3904 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3905 = eq(_T_3904, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3906 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3907 = eq(_T_3906, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3908 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3909 = eq(_T_3908, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3910 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3911 = eq(_T_3910, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3912 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3913 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3914 = eq(_T_3913, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3915 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3916 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3917 = and(_T_3899, _T_3900) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3918 = and(_T_3917, _T_3902) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3919 = and(_T_3918, _T_3903) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3920 = and(_T_3919, _T_3905) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3921 = and(_T_3920, _T_3907) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3922 = and(_T_3921, _T_3909) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3923 = and(_T_3922, _T_3911) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3924 = and(_T_3923, _T_3912) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3925 = and(_T_3924, _T_3914) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3926 = and(_T_3925, _T_3915) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3927 = and(_T_3926, _T_3916) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3928 = or(_T_3897, _T_3927) @[dec_dec_ctl.scala 257:61]
|
|
|
|
|
node _T_3929 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3930 = eq(_T_3929, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3931 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3932 = eq(_T_3931, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3933 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3934 = eq(_T_3933, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3935 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3936 = eq(_T_3935, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3937 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3938 = eq(_T_3937, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3939 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3940 = eq(_T_3939, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3941 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3942 = eq(_T_3941, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3943 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3944 = eq(_T_3943, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3945 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3946 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3947 = eq(_T_3946, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3948 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3949 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3950 = and(_T_3930, _T_3932) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3951 = and(_T_3950, _T_3934) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3952 = and(_T_3951, _T_3936) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3953 = and(_T_3952, _T_3938) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3954 = and(_T_3953, _T_3940) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3955 = and(_T_3954, _T_3942) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3956 = and(_T_3955, _T_3944) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3957 = and(_T_3956, _T_3945) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3958 = and(_T_3957, _T_3947) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3959 = and(_T_3958, _T_3948) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3960 = and(_T_3959, _T_3949) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3961 = or(_T_3928, _T_3960) @[dec_dec_ctl.scala 257:116]
|
|
|
|
|
node _T_3962 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3963 = eq(_T_3962, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3964 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3965 = eq(_T_3964, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3966 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3967 = eq(_T_3966, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3968 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3969 = eq(_T_3968, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3970 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3971 = eq(_T_3970, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3972 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3973 = eq(_T_3972, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3974 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3975 = eq(_T_3974, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3976 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3977 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3978 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3979 = eq(_T_3978, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3980 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3981 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_3982 = and(_T_3963, _T_3965) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3983 = and(_T_3982, _T_3967) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3984 = and(_T_3983, _T_3969) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3985 = and(_T_3984, _T_3971) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3986 = and(_T_3985, _T_3973) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3987 = and(_T_3986, _T_3975) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3988 = and(_T_3987, _T_3976) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3989 = and(_T_3988, _T_3977) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3990 = and(_T_3989, _T_3979) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3991 = and(_T_3990, _T_3980) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3992 = and(_T_3991, _T_3981) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_3993 = or(_T_3961, _T_3992) @[dec_dec_ctl.scala 258:59]
|
|
|
|
|
node _T_3994 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3995 = eq(_T_3994, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3996 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3997 = eq(_T_3996, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_3998 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_3999 = eq(_T_3998, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4000 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4001 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4002 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4003 = eq(_T_4002, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4004 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4005 = eq(_T_4004, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4006 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4007 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4008 = and(_T_3995, _T_3997) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4009 = and(_T_4008, _T_3999) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4010 = and(_T_4009, _T_4000) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4011 = and(_T_4010, _T_4001) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4012 = and(_T_4011, _T_4003) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4013 = and(_T_4012, _T_4005) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4014 = and(_T_4013, _T_4006) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4015 = and(_T_4014, _T_4007) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4016 = or(_T_3993, _T_4015) @[dec_dec_ctl.scala 258:114]
|
|
|
|
|
node _T_4017 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4018 = eq(_T_4017, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4019 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4020 = eq(_T_4019, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4021 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4022 = eq(_T_4021, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4023 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4024 = eq(_T_4023, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4025 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4026 = eq(_T_4025, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4027 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4028 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4029 = eq(_T_4028, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4030 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4031 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4032 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4033 = eq(_T_4032, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4034 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4035 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4036 = and(_T_4018, _T_4020) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4037 = and(_T_4036, _T_4022) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4038 = and(_T_4037, _T_4024) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4039 = and(_T_4038, _T_4026) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4040 = and(_T_4039, _T_4027) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4041 = and(_T_4040, _T_4029) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4042 = and(_T_4041, _T_4030) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4043 = and(_T_4042, _T_4031) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4044 = and(_T_4043, _T_4033) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4045 = and(_T_4044, _T_4034) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4046 = and(_T_4045, _T_4035) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4047 = or(_T_4016, _T_4046) @[dec_dec_ctl.scala 259:46]
|
|
|
|
|
node _T_4048 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4049 = eq(_T_4048, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4050 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4051 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4052 = eq(_T_4051, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4053 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4054 = eq(_T_4053, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4055 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4056 = eq(_T_4055, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4057 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4058 = eq(_T_4057, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4059 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4060 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4061 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4062 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4063 = eq(_T_4062, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4064 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4065 = eq(_T_4064, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4066 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4067 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4068 = and(_T_4049, _T_4050) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4069 = and(_T_4068, _T_4052) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4070 = and(_T_4069, _T_4054) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4071 = and(_T_4070, _T_4056) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4072 = and(_T_4071, _T_4058) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4073 = and(_T_4072, _T_4059) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4074 = and(_T_4073, _T_4060) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4075 = and(_T_4074, _T_4061) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4076 = and(_T_4075, _T_4063) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4077 = and(_T_4076, _T_4065) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4078 = and(_T_4077, _T_4066) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4079 = and(_T_4078, _T_4067) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4080 = or(_T_4047, _T_4079) @[dec_dec_ctl.scala 259:100]
|
|
|
|
|
node _T_4081 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4082 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4083 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4084 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4085 = eq(_T_4084, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4086 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4087 = eq(_T_4086, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4088 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4089 = eq(_T_4088, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4090 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4091 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4092 = and(_T_4081, _T_4082) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4093 = and(_T_4092, _T_4083) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4094 = and(_T_4093, _T_4085) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4095 = and(_T_4094, _T_4087) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4096 = and(_T_4095, _T_4089) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4097 = and(_T_4096, _T_4090) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4098 = and(_T_4097, _T_4091) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4099 = or(_T_4080, _T_4098) @[dec_dec_ctl.scala 260:60]
|
|
|
|
|
node _T_4100 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4101 = eq(_T_4100, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4102 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4103 = eq(_T_4102, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4104 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4105 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4106 = eq(_T_4105, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4107 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4108 = eq(_T_4107, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4109 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4110 = eq(_T_4109, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4111 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4112 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4113 = and(_T_4101, _T_4103) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4114 = and(_T_4113, _T_4104) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4115 = and(_T_4114, _T_4106) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4116 = and(_T_4115, _T_4108) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4117 = and(_T_4116, _T_4110) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4118 = and(_T_4117, _T_4111) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4119 = and(_T_4118, _T_4112) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4120 = or(_T_4099, _T_4119) @[dec_dec_ctl.scala 260:97]
|
|
|
|
|
node _T_4121 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4122 = eq(_T_4121, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4123 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4124 = eq(_T_4123, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4125 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4126 = eq(_T_4125, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4127 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4128 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4129 = eq(_T_4128, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4130 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4131 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4132 = and(_T_4122, _T_4124) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4133 = and(_T_4132, _T_4126) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4134 = and(_T_4133, _T_4127) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4135 = and(_T_4134, _T_4129) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4136 = and(_T_4135, _T_4130) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4137 = and(_T_4136, _T_4131) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4138 = or(_T_4120, _T_4137) @[dec_dec_ctl.scala 261:43]
|
|
|
|
|
node _T_4139 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4140 = eq(_T_4139, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4141 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4142 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4143 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4144 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4145 = eq(_T_4144, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4146 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4147 = eq(_T_4146, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4148 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4149 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4150 = and(_T_4140, _T_4141) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4151 = and(_T_4150, _T_4142) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4152 = and(_T_4151, _T_4143) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4153 = and(_T_4152, _T_4145) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4154 = and(_T_4153, _T_4147) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4155 = and(_T_4154, _T_4148) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4156 = and(_T_4155, _T_4149) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4157 = or(_T_4138, _T_4156) @[dec_dec_ctl.scala 261:79]
|
|
|
|
|
node _T_4158 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4159 = eq(_T_4158, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4160 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4161 = eq(_T_4160, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4162 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4163 = eq(_T_4162, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4164 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4165 = eq(_T_4164, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4166 = bits(io.ins, 27, 27) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4167 = eq(_T_4166, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4168 = bits(io.ins, 26, 26) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4169 = eq(_T_4168, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4170 = bits(io.ins, 25, 25) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4172 = bits(io.ins, 24, 24) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4173 = eq(_T_4172, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4174 = bits(io.ins, 23, 23) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4175 = eq(_T_4174, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4176 = bits(io.ins, 22, 22) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4177 = eq(_T_4176, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4178 = bits(io.ins, 21, 21) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4179 = eq(_T_4178, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4180 = bits(io.ins, 20, 20) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4181 = eq(_T_4180, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4182 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4183 = eq(_T_4182, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4184 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4185 = eq(_T_4184, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4186 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4188 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4189 = eq(_T_4188, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4190 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4191 = eq(_T_4190, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4192 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4193 = eq(_T_4192, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4194 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4195 = eq(_T_4194, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4196 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4197 = eq(_T_4196, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4198 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4199 = eq(_T_4198, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4200 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4201 = eq(_T_4200, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4202 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4203 = eq(_T_4202, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4204 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4205 = eq(_T_4204, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4206 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4207 = eq(_T_4206, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4208 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4209 = eq(_T_4208, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4210 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4211 = eq(_T_4210, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4212 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4213 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4214 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4215 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4216 = and(_T_4159, _T_4161) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4217 = and(_T_4216, _T_4163) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4218 = and(_T_4217, _T_4165) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4219 = and(_T_4218, _T_4167) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4220 = and(_T_4219, _T_4169) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4221 = and(_T_4220, _T_4171) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4222 = and(_T_4221, _T_4173) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4223 = and(_T_4222, _T_4175) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4224 = and(_T_4223, _T_4177) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4225 = and(_T_4224, _T_4179) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4226 = and(_T_4225, _T_4181) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4227 = and(_T_4226, _T_4183) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4228 = and(_T_4227, _T_4185) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4229 = and(_T_4228, _T_4187) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4230 = and(_T_4229, _T_4189) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4231 = and(_T_4230, _T_4191) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4232 = and(_T_4231, _T_4193) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4233 = and(_T_4232, _T_4195) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4234 = and(_T_4233, _T_4197) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4235 = and(_T_4234, _T_4199) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4236 = and(_T_4235, _T_4201) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4237 = and(_T_4236, _T_4203) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4238 = and(_T_4237, _T_4205) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4239 = and(_T_4238, _T_4207) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4240 = and(_T_4239, _T_4209) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4241 = and(_T_4240, _T_4211) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4242 = and(_T_4241, _T_4212) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4243 = and(_T_4242, _T_4213) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4244 = and(_T_4243, _T_4214) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4245 = and(_T_4244, _T_4215) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4246 = or(_T_4157, _T_4245) @[dec_dec_ctl.scala 261:117]
|
|
|
|
|
node _T_4247 = bits(io.ins, 31, 31) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4248 = eq(_T_4247, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4249 = bits(io.ins, 30, 30) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4250 = eq(_T_4249, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4251 = bits(io.ins, 29, 29) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4252 = eq(_T_4251, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4253 = bits(io.ins, 28, 28) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4254 = eq(_T_4253, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4255 = bits(io.ins, 19, 19) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4256 = eq(_T_4255, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4257 = bits(io.ins, 18, 18) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4258 = eq(_T_4257, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4259 = bits(io.ins, 17, 17) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4260 = eq(_T_4259, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4261 = bits(io.ins, 16, 16) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4262 = eq(_T_4261, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4263 = bits(io.ins, 15, 15) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4264 = eq(_T_4263, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4265 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4266 = eq(_T_4265, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4267 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4268 = eq(_T_4267, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4269 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4270 = eq(_T_4269, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4271 = bits(io.ins, 11, 11) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4272 = eq(_T_4271, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4273 = bits(io.ins, 10, 10) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4274 = eq(_T_4273, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4275 = bits(io.ins, 9, 9) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4276 = eq(_T_4275, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4277 = bits(io.ins, 8, 8) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4278 = eq(_T_4277, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4279 = bits(io.ins, 7, 7) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4280 = eq(_T_4279, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4281 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4282 = eq(_T_4281, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4283 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4284 = eq(_T_4283, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4285 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4286 = eq(_T_4285, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4287 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4288 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4289 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4290 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4291 = and(_T_4248, _T_4250) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4292 = and(_T_4291, _T_4252) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4293 = and(_T_4292, _T_4254) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4294 = and(_T_4293, _T_4256) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4295 = and(_T_4294, _T_4258) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4296 = and(_T_4295, _T_4260) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4297 = and(_T_4296, _T_4262) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4298 = and(_T_4297, _T_4264) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4299 = and(_T_4298, _T_4266) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4300 = and(_T_4299, _T_4268) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4301 = and(_T_4300, _T_4270) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4302 = and(_T_4301, _T_4272) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4303 = and(_T_4302, _T_4274) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4304 = and(_T_4303, _T_4276) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4305 = and(_T_4304, _T_4278) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4306 = and(_T_4305, _T_4280) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4307 = and(_T_4306, _T_4282) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4308 = and(_T_4307, _T_4284) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4309 = and(_T_4308, _T_4286) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4310 = and(_T_4309, _T_4287) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4311 = and(_T_4310, _T_4288) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4312 = and(_T_4311, _T_4289) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4313 = and(_T_4312, _T_4290) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4314 = or(_T_4246, _T_4313) @[dec_dec_ctl.scala 262:130]
|
|
|
|
|
node _T_4315 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4316 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4317 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4318 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4319 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4320 = eq(_T_4319, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4321 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4322 = eq(_T_4321, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4323 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4324 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4325 = and(_T_4315, _T_4316) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4326 = and(_T_4325, _T_4317) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4327 = and(_T_4326, _T_4318) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4328 = and(_T_4327, _T_4320) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4329 = and(_T_4328, _T_4322) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4330 = and(_T_4329, _T_4323) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4331 = and(_T_4330, _T_4324) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4332 = or(_T_4314, _T_4331) @[dec_dec_ctl.scala 263:102]
|
|
|
|
|
node _T_4333 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4334 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4335 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4336 = eq(_T_4335, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4337 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4338 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4339 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4340 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4341 = and(_T_4333, _T_4334) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4342 = and(_T_4341, _T_4336) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4343 = and(_T_4342, _T_4337) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4344 = and(_T_4343, _T_4338) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4345 = and(_T_4344, _T_4339) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4346 = and(_T_4345, _T_4340) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4347 = or(_T_4332, _T_4346) @[dec_dec_ctl.scala 264:39]
|
|
|
|
|
node _T_4348 = bits(io.ins, 14, 14) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4349 = eq(_T_4348, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4350 = bits(io.ins, 12, 12) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4351 = eq(_T_4350, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4352 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4353 = eq(_T_4352, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4354 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4355 = eq(_T_4354, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4356 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4357 = eq(_T_4356, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4358 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4359 = eq(_T_4358, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4360 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4361 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4362 = and(_T_4349, _T_4351) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4363 = and(_T_4362, _T_4353) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4364 = and(_T_4363, _T_4355) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4365 = and(_T_4364, _T_4357) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4366 = and(_T_4365, _T_4359) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4367 = and(_T_4366, _T_4360) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4368 = and(_T_4367, _T_4361) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4369 = or(_T_4347, _T_4368) @[dec_dec_ctl.scala 264:71]
|
|
|
|
|
node _T_4370 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4371 = eq(_T_4370, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4372 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4373 = eq(_T_4372, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4374 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4375 = eq(_T_4374, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4376 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4377 = eq(_T_4376, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4378 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4379 = eq(_T_4378, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4380 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4381 = eq(_T_4380, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4382 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4383 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4384 = and(_T_4371, _T_4373) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4385 = and(_T_4384, _T_4375) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4386 = and(_T_4385, _T_4377) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4387 = and(_T_4386, _T_4379) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4388 = and(_T_4387, _T_4381) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4389 = and(_T_4388, _T_4382) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4390 = and(_T_4389, _T_4383) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4391 = or(_T_4369, _T_4390) @[dec_dec_ctl.scala 264:112]
|
|
|
|
|
node _T_4392 = bits(io.ins, 13, 13) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4393 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4394 = eq(_T_4393, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4395 = bits(io.ins, 5, 5) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4396 = eq(_T_4395, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4397 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4398 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4399 = eq(_T_4398, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4400 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4401 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4402 = and(_T_4392, _T_4394) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4403 = and(_T_4402, _T_4396) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4404 = and(_T_4403, _T_4397) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4405 = and(_T_4404, _T_4399) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4406 = and(_T_4405, _T_4400) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4407 = and(_T_4406, _T_4401) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4408 = or(_T_4391, _T_4407) @[dec_dec_ctl.scala 265:43]
|
|
|
|
|
node _T_4409 = bits(io.ins, 6, 6) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4410 = eq(_T_4409, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4411 = bits(io.ins, 4, 4) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4412 = bits(io.ins, 3, 3) @[dec_dec_ctl.scala 15:53]
|
|
|
|
|
node _T_4413 = eq(_T_4412, UInt<1>("h00")) @[dec_dec_ctl.scala 15:46]
|
|
|
|
|
node _T_4414 = bits(io.ins, 2, 2) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4415 = bits(io.ins, 1, 1) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4416 = bits(io.ins, 0, 0) @[dec_dec_ctl.scala 15:34]
|
|
|
|
|
node _T_4417 = and(_T_4410, _T_4411) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4418 = and(_T_4417, _T_4413) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4419 = and(_T_4418, _T_4414) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4420 = and(_T_4419, _T_4415) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4421 = and(_T_4420, _T_4416) @[dec_dec_ctl.scala 17:17]
|
|
|
|
|
node _T_4422 = or(_T_4408, _T_4421) @[dec_dec_ctl.scala 265:78]
|
|
|
|
|
io.out.legal <= _T_4422 @[dec_dec_ctl.scala 248:16]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_1 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_1 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_2 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_2 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_3 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_3 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_4 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_4 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_4 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
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|
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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|
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_5 :
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|
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output Q : Clock
|
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|
|
input CK : Clock
|
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|
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input EN : UInt<1>
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|
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_5 :
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|
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input clock : Clock
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|
|
input reset : Reset
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|
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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|
|
inst clkhdr of gated_latch_5 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
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|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
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|
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_6 :
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|
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output Q : Clock
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|
|
input CK : Clock
|
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|
|
input EN : UInt<1>
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|
|
input SE : UInt<1>
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|
|
defname = gated_latch
|
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module rvclkhdr_6 :
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|
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|
|
input clock : Clock
|
|
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|
|
input reset : Reset
|
|
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|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
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|
|
|
|
|
|
inst clkhdr of gated_latch_6 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
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|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
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|
|
extmodule gated_latch_7 :
|
|
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|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
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|
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|
|
module rvclkhdr_7 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_7 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
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|
|
extmodule gated_latch_8 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_8 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_8 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_9 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_9 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_9 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_10 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_10 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_10 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
module dec_decode_ctl :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : AsyncReset
|
2021-01-27 21:01:24 +08:00
|
|
|
output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_branch_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_result_r : UInt<32>, flip dec_qual_lsu_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<4>, flip dec_i0_rs2_bypass_en_d : UInt<4>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_aln : {ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}, flip dec_tlu_trace_disable : UInt<1>, flip dec_debug_valid_d : UInt<1>, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb : UInt<32>, dec_i0_pc_wb : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_second_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_bp_fa_index : UInt<9>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_
|
|
|
|
|
|
|
|
|
|
wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.gorc <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
_T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 118:40]
|
|
|
|
|
io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.gorc <= _T.bits.gorc @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 118:25]
|
|
|
|
|
io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 118:25]
|
|
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|
io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 118:25]
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|
|
|
io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 118:25]
|
2021-01-27 14:46:11 +08:00
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wire leak1_i1_stall_in : UInt<1>
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|
|
|
leak1_i1_stall_in <= UInt<1>("h00")
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|
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|
wire leak1_i0_stall_in : UInt<1>
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|
leak1_i0_stall_in <= UInt<1>("h00")
|
2021-01-27 21:01:24 +08:00
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wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 122:37]
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wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 123:37]
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wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 124:37]
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wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 125:37]
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wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 126:37]
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wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 127:37]
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wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 128:37]
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wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 129:37]
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wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 130:37]
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wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 131:37]
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wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 132:37]
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wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 133:37]
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wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 134:37]
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wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 135:37]
|
2021-01-27 14:46:11 +08:00
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wire i0_rs1_depth_d : UInt<2>
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|
|
i0_rs1_depth_d <= UInt<1>("h00")
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|
wire i0_rs2_depth_d : UInt<2>
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|
|
i0_rs2_depth_d <= UInt<1>("h00")
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|
wire cam_wen : UInt<4>
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|
cam_wen <= UInt<1>("h00")
|
2021-01-27 21:01:24 +08:00
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wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 139:37]
|
2021-01-27 14:46:11 +08:00
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wire cam_write : UInt<1>
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|
cam_write <= UInt<1>("h00")
|
2021-01-27 21:01:24 +08:00
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|
wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 141:37]
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wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 142:37]
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wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 143:37]
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wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 144:37]
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wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 145:37]
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wire i0_dp : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 146:37]
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|
wire i0_dp_raw : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 147:37]
|
2021-01-27 14:46:11 +08:00
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|
|
wire i0_rs1bypass : UInt<3>
|
|
|
|
|
i0_rs1bypass <= UInt<1>("h00")
|
|
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|
|
wire i0_rs2bypass : UInt<3>
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|
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|
|
i0_rs2bypass <= UInt<1>("h00")
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|
|
wire illegal_lockout : UInt<1>
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|
|
illegal_lockout <= UInt<1>("h00")
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|
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|
wire postsync_stall : UInt<1>
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|
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|
|
postsync_stall <= UInt<1>("h00")
|
|
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|
|
wire ps_stall_in : UInt<1>
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|
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|
|
ps_stall_in <= UInt<1>("h00")
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|
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|
|
wire i0_pipe_en : UInt<4>
|
|
|
|
|
i0_pipe_en <= UInt<1>("h00")
|
|
|
|
|
wire i0_load_block_d : UInt<1>
|
|
|
|
|
i0_load_block_d <= UInt<1>("h00")
|
|
|
|
|
wire load_ldst_bypass_d : UInt<1>
|
|
|
|
|
load_ldst_bypass_d <= UInt<1>("h00")
|
|
|
|
|
wire store_data_bypass_d : UInt<1>
|
|
|
|
|
store_data_bypass_d <= UInt<1>("h00")
|
|
|
|
|
wire store_data_bypass_m : UInt<1>
|
|
|
|
|
store_data_bypass_m <= UInt<1>("h00")
|
|
|
|
|
wire tlu_wr_pause_r1 : UInt<1>
|
|
|
|
|
tlu_wr_pause_r1 <= UInt<1>("h00")
|
|
|
|
|
wire tlu_wr_pause_r2 : UInt<1>
|
|
|
|
|
tlu_wr_pause_r2 <= UInt<1>("h00")
|
|
|
|
|
wire leak1_i1_stall : UInt<1>
|
|
|
|
|
leak1_i1_stall <= UInt<1>("h00")
|
|
|
|
|
wire leak1_i0_stall : UInt<1>
|
|
|
|
|
leak1_i0_stall <= UInt<1>("h00")
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|
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|
|
wire pause_stall : UInt<1>
|
|
|
|
|
pause_stall <= UInt<1>("h00")
|
|
|
|
|
wire flush_final_r : UInt<1>
|
|
|
|
|
flush_final_r <= UInt<1>("h00")
|
|
|
|
|
wire illegal_lockout_in : UInt<1>
|
|
|
|
|
illegal_lockout_in <= UInt<1>("h00")
|
|
|
|
|
wire lsu_idle : UInt<1>
|
|
|
|
|
lsu_idle <= UInt<1>("h00")
|
|
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|
|
wire pause_state_in : UInt<1>
|
|
|
|
|
pause_state_in <= UInt<1>("h00")
|
|
|
|
|
wire leak1_mode : UInt<1>
|
|
|
|
|
leak1_mode <= UInt<1>("h00")
|
|
|
|
|
wire i0_pcall : UInt<1>
|
|
|
|
|
i0_pcall <= UInt<1>("h00")
|
|
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|
|
wire i0_pja : UInt<1>
|
|
|
|
|
i0_pja <= UInt<1>("h00")
|
|
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|
|
wire i0_pret : UInt<1>
|
|
|
|
|
i0_pret <= UInt<1>("h00")
|
|
|
|
|
wire i0_legal_decode_d : UInt<1>
|
|
|
|
|
i0_legal_decode_d <= UInt<1>("h00")
|
|
|
|
|
wire i0_pcall_raw : UInt<1>
|
|
|
|
|
i0_pcall_raw <= UInt<1>("h00")
|
|
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|
|
wire i0_pja_raw : UInt<1>
|
|
|
|
|
i0_pja_raw <= UInt<1>("h00")
|
|
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|
|
wire i0_pret_raw : UInt<1>
|
|
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|
|
i0_pret_raw <= UInt<1>("h00")
|
|
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|
|
wire i0_br_offset : UInt<12>
|
|
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|
|
i0_br_offset <= UInt<1>("h00")
|
|
|
|
|
wire i0_csr_write_only_d : UInt<1>
|
|
|
|
|
i0_csr_write_only_d <= UInt<1>("h00")
|
|
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|
|
wire i0_jal : UInt<1>
|
|
|
|
|
i0_jal <= UInt<1>("h00")
|
|
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|
|
wire i0_wen_r : UInt<1>
|
|
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|
|
i0_wen_r <= UInt<1>("h00")
|
|
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|
|
wire i0_x_ctl_en : UInt<1>
|
|
|
|
|
i0_x_ctl_en <= UInt<1>("h00")
|
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|
|
wire i0_r_ctl_en : UInt<1>
|
|
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|
|
i0_r_ctl_en <= UInt<1>("h00")
|
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|
|
wire i0_wb_ctl_en : UInt<1>
|
|
|
|
|
i0_wb_ctl_en <= UInt<1>("h00")
|
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|
|
wire i0_x_data_en : UInt<1>
|
|
|
|
|
i0_x_data_en <= UInt<1>("h00")
|
|
|
|
|
wire i0_r_data_en : UInt<1>
|
|
|
|
|
i0_r_data_en <= UInt<1>("h00")
|
|
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|
|
wire i0_wb_data_en : UInt<1>
|
|
|
|
|
i0_wb_data_en <= UInt<1>("h00")
|
|
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|
|
wire i0_wb1_data_en : UInt<1>
|
|
|
|
|
i0_wb1_data_en <= UInt<1>("h00")
|
|
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|
|
wire i0_nonblock_load_stall : UInt<1>
|
|
|
|
|
i0_nonblock_load_stall <= UInt<1>("h00")
|
|
|
|
|
wire csr_read : UInt<1>
|
|
|
|
|
csr_read <= UInt<1>("h00")
|
|
|
|
|
wire lsu_decode_d : UInt<1>
|
|
|
|
|
lsu_decode_d <= UInt<1>("h00")
|
|
|
|
|
wire mul_decode_d : UInt<1>
|
|
|
|
|
mul_decode_d <= UInt<1>("h00")
|
|
|
|
|
wire div_decode_d : UInt<1>
|
|
|
|
|
div_decode_d <= UInt<1>("h00")
|
|
|
|
|
wire write_csr_data : UInt<32>
|
|
|
|
|
write_csr_data <= UInt<1>("h00")
|
|
|
|
|
wire i0_result_corr_r : UInt<32>
|
|
|
|
|
i0_result_corr_r <= UInt<1>("h00")
|
|
|
|
|
wire presync_stall : UInt<1>
|
|
|
|
|
presync_stall <= UInt<1>("h00")
|
|
|
|
|
wire i0_nonblock_div_stall : UInt<1>
|
|
|
|
|
i0_nonblock_div_stall <= UInt<1>("h00")
|
|
|
|
|
wire debug_fence : UInt<1>
|
|
|
|
|
debug_fence <= UInt<1>("h00")
|
|
|
|
|
wire i0_immed_d : UInt<32>
|
|
|
|
|
i0_immed_d <= UInt<1>("h00")
|
|
|
|
|
wire i0_result_x : UInt<32>
|
|
|
|
|
i0_result_x <= UInt<1>("h00")
|
|
|
|
|
wire i0_result_r : UInt<32>
|
|
|
|
|
i0_result_r <= UInt<1>("h00")
|
|
|
|
|
wire i0_br_error_all : UInt<1>
|
|
|
|
|
i0_br_error_all <= UInt<1>("h00")
|
|
|
|
|
wire i0_brp_valid : UInt<1>
|
|
|
|
|
i0_brp_valid <= UInt<1>("h00")
|
|
|
|
|
wire btb_error_found_f : UInt<1>
|
|
|
|
|
btb_error_found_f <= UInt<1>("h00")
|
|
|
|
|
wire fa_error_index_ns : UInt<1>
|
|
|
|
|
fa_error_index_ns <= UInt<1>("h00")
|
|
|
|
|
wire btb_error_found : UInt<1>
|
|
|
|
|
btb_error_found <= UInt<1>("h00")
|
|
|
|
|
wire div_active_in : UInt<1>
|
|
|
|
|
div_active_in <= UInt<1>("h00")
|
|
|
|
|
wire _T_1 : UInt
|
|
|
|
|
_T_1 <= UInt<1>("h00")
|
|
|
|
|
node _T_2 = xor(leak1_i1_stall_in, _T_1) @[lib.scala 448:21]
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|
|
|
|
node _T_3 = orr(_T_2) @[lib.scala 448:29]
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|
|
reg _T_4 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
|
|
|
when _T_3 : @[Reg.scala 28:19]
|
|
|
|
|
_T_4 <= leak1_i1_stall_in @[Reg.scala 28:23]
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|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1 <= _T_4 @[lib.scala 451:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
leak1_i1_stall <= _T_1 @[dec_decode_ctl.scala 208:35]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_5 : UInt
|
|
|
|
|
_T_5 <= UInt<1>("h00")
|
|
|
|
|
node _T_6 = xor(leak1_i0_stall_in, _T_5) @[lib.scala 448:21]
|
|
|
|
|
node _T_7 = orr(_T_6) @[lib.scala 448:29]
|
|
|
|
|
reg _T_8 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_7 : @[Reg.scala 28:19]
|
|
|
|
|
_T_8 <= leak1_i0_stall_in @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_5 <= _T_8 @[lib.scala 451:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
leak1_i0_stall <= _T_5 @[dec_decode_ctl.scala 209:35]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_9 : UInt<1>
|
|
|
|
|
_T_9 <= UInt<1>("h00")
|
|
|
|
|
node _T_10 = xor(io.dec_tlu_flush_extint, _T_9) @[lib.scala 470:21]
|
|
|
|
|
node _T_11 = orr(_T_10) @[lib.scala 470:29]
|
|
|
|
|
reg _T_12 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_11 : @[Reg.scala 28:19]
|
|
|
|
|
_T_12 <= io.dec_tlu_flush_extint @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_9 <= _T_12 @[lib.scala 473:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
io.decode_exu.dec_extint_stall <= _T_9 @[dec_decode_ctl.scala 210:35]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_13 : UInt<1>
|
|
|
|
|
_T_13 <= UInt<1>("h00")
|
|
|
|
|
node _T_14 = xor(pause_state_in, _T_13) @[lib.scala 470:21]
|
|
|
|
|
node _T_15 = orr(_T_14) @[lib.scala 470:29]
|
|
|
|
|
reg _T_16 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_15 : @[Reg.scala 28:19]
|
|
|
|
|
_T_16 <= pause_state_in @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_13 <= _T_16 @[lib.scala 473:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
pause_stall <= _T_13 @[dec_decode_ctl.scala 211:35]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_17 : UInt<1>
|
|
|
|
|
_T_17 <= UInt<1>("h00")
|
|
|
|
|
node _T_18 = xor(io.dec_tlu_wr_pause_r, _T_17) @[lib.scala 470:21]
|
|
|
|
|
node _T_19 = orr(_T_18) @[lib.scala 470:29]
|
|
|
|
|
reg _T_20 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_19 : @[Reg.scala 28:19]
|
|
|
|
|
_T_20 <= io.dec_tlu_wr_pause_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_17 <= _T_20 @[lib.scala 473:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
tlu_wr_pause_r1 <= _T_17 @[dec_decode_ctl.scala 212:35]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_21 : UInt
|
|
|
|
|
_T_21 <= UInt<1>("h00")
|
|
|
|
|
node _T_22 = xor(tlu_wr_pause_r1, _T_21) @[lib.scala 448:21]
|
|
|
|
|
node _T_23 = orr(_T_22) @[lib.scala 448:29]
|
|
|
|
|
reg _T_24 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_23 : @[Reg.scala 28:19]
|
|
|
|
|
_T_24 <= tlu_wr_pause_r1 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_21 <= _T_24 @[lib.scala 451:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
tlu_wr_pause_r2 <= _T_21 @[dec_decode_ctl.scala 213:35]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_25 : UInt
|
|
|
|
|
_T_25 <= UInt<1>("h00")
|
|
|
|
|
node _T_26 = xor(illegal_lockout_in, _T_25) @[lib.scala 448:21]
|
|
|
|
|
node _T_27 = orr(_T_26) @[lib.scala 448:29]
|
|
|
|
|
reg _T_28 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_27 : @[Reg.scala 28:19]
|
|
|
|
|
_T_28 <= illegal_lockout_in @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_25 <= _T_28 @[lib.scala 451:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
illegal_lockout <= _T_25 @[dec_decode_ctl.scala 214:35]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_29 : UInt
|
|
|
|
|
_T_29 <= UInt<1>("h00")
|
|
|
|
|
node _T_30 = xor(ps_stall_in, _T_29) @[lib.scala 448:21]
|
|
|
|
|
node _T_31 = orr(_T_30) @[lib.scala 448:29]
|
|
|
|
|
reg _T_32 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_31 : @[Reg.scala 28:19]
|
|
|
|
|
_T_32 <= ps_stall_in @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_29 <= _T_32 @[lib.scala 451:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
postsync_stall <= _T_29 @[dec_decode_ctl.scala 215:35]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire lsu_trigger_match_r : UInt
|
|
|
|
|
lsu_trigger_match_r <= UInt<1>("h00")
|
|
|
|
|
node _T_33 = xor(io.lsu_trigger_match_m, lsu_trigger_match_r) @[lib.scala 448:21]
|
|
|
|
|
node _T_34 = orr(_T_33) @[lib.scala 448:29]
|
|
|
|
|
reg _T_35 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_34 : @[Reg.scala 28:19]
|
|
|
|
|
_T_35 <= io.lsu_trigger_match_m @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
lsu_trigger_match_r <= _T_35 @[lib.scala 451:16]
|
|
|
|
|
wire lsu_pmu_misaligned_r : UInt<1>
|
|
|
|
|
lsu_pmu_misaligned_r <= UInt<1>("h00")
|
|
|
|
|
node _T_36 = xor(io.lsu_pmu_misaligned_m, lsu_pmu_misaligned_r) @[lib.scala 470:21]
|
|
|
|
|
node _T_37 = orr(_T_36) @[lib.scala 470:29]
|
|
|
|
|
reg _T_38 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_37 : @[Reg.scala 28:19]
|
|
|
|
|
_T_38 <= io.lsu_pmu_misaligned_m @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
lsu_pmu_misaligned_r <= _T_38 @[lib.scala 473:16]
|
|
|
|
|
wire _T_39 : UInt<1>
|
|
|
|
|
_T_39 <= UInt<1>("h00")
|
|
|
|
|
node _T_40 = xor(div_active_in, _T_39) @[lib.scala 470:21]
|
|
|
|
|
node _T_41 = orr(_T_40) @[lib.scala 470:29]
|
|
|
|
|
reg _T_42 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_41 : @[Reg.scala 28:19]
|
|
|
|
|
_T_42 <= div_active_in @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_39 <= _T_42 @[lib.scala 473:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
io.dec_div_active <= _T_39 @[dec_decode_ctl.scala 219:35]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_43 : UInt<1>
|
|
|
|
|
_T_43 <= UInt<1>("h00")
|
|
|
|
|
node _T_44 = xor(io.exu_flush_final, _T_43) @[lib.scala 470:21]
|
|
|
|
|
node _T_45 = orr(_T_44) @[lib.scala 470:29]
|
|
|
|
|
reg _T_46 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_45 : @[Reg.scala 28:19]
|
|
|
|
|
_T_46 <= io.exu_flush_final @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_43 <= _T_46 @[lib.scala 473:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
flush_final_r <= _T_43 @[dec_decode_ctl.scala 220:35]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire debug_valid_x : UInt<1>
|
|
|
|
|
debug_valid_x <= UInt<1>("h00")
|
|
|
|
|
node _T_47 = xor(io.dec_debug_valid_d, debug_valid_x) @[lib.scala 470:21]
|
|
|
|
|
node _T_48 = orr(_T_47) @[lib.scala 470:29]
|
|
|
|
|
reg _T_49 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_48 : @[Reg.scala 28:19]
|
|
|
|
|
_T_49 <= io.dec_debug_valid_d @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
debug_valid_x <= _T_49 @[lib.scala 473:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 222:43]
|
|
|
|
|
node _T_50 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 224:82]
|
|
|
|
|
node _T_51 = and(io.dec_i0_brp.valid, _T_50) @[dec_decode_ctl.scala 224:80]
|
|
|
|
|
node _T_52 = eq(i0_icaf_d, UInt<1>("h00")) @[dec_decode_ctl.scala 224:96]
|
|
|
|
|
node _T_53 = and(_T_51, _T_52) @[dec_decode_ctl.scala 224:94]
|
|
|
|
|
i0_brp_valid <= _T_53 @[dec_decode_ctl.scala 224:57]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 225:57]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 226:57]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 227:57]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 228:57]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 229:57]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 230:57]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 231:57]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 232:57]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 233:57]
|
|
|
|
|
node _T_54 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 234:73]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.valid <= _T_54 @[dec_decode_ctl.scala 234:57]
|
|
|
|
|
node _T_55 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 235:94]
|
|
|
|
|
node _T_56 = or(_T_55, i0_pja_raw) @[dec_decode_ctl.scala 235:109]
|
|
|
|
|
node _T_57 = or(_T_56, i0_pret_raw) @[dec_decode_ctl.scala 235:122]
|
|
|
|
|
node _T_58 = eq(_T_57, UInt<1>("h00")) @[dec_decode_ctl.scala 235:75]
|
|
|
|
|
node _T_59 = and(i0_brp_valid, _T_58) @[dec_decode_ctl.scala 235:73]
|
|
|
|
|
node _T_60 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 238:99]
|
|
|
|
|
node _T_61 = and(i0_brp_valid, _T_60) @[dec_decode_ctl.scala 238:74]
|
|
|
|
|
node _T_62 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 238:133]
|
|
|
|
|
node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 238:103]
|
|
|
|
|
node _T_64 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 238:153]
|
|
|
|
|
node _T_65 = and(_T_63, _T_64) @[dec_decode_ctl.scala 238:151]
|
|
|
|
|
node _T_66 = xor(io.dec_i0_brp.bits.ret, i0_pret_raw) @[dec_decode_ctl.scala 239:100]
|
|
|
|
|
node _T_67 = and(i0_brp_valid, _T_66) @[dec_decode_ctl.scala 239:74]
|
|
|
|
|
node _T_68 = or(io.dec_i0_brp.bits.br_error, _T_59) @[dec_decode_ctl.scala 240:89]
|
|
|
|
|
node _T_69 = or(_T_68, _T_65) @[dec_decode_ctl.scala 240:106]
|
|
|
|
|
node _T_70 = or(_T_69, _T_67) @[dec_decode_ctl.scala 240:128]
|
|
|
|
|
node _T_71 = and(_T_70, i0_legal_decode_d) @[dec_decode_ctl.scala 241:74]
|
|
|
|
|
node _T_72 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 241:96]
|
|
|
|
|
node _T_73 = and(_T_71, _T_72) @[dec_decode_ctl.scala 241:94]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_73 @[dec_decode_ctl.scala 241:58]
|
|
|
|
|
node _T_74 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 242:96]
|
|
|
|
|
node _T_75 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 242:118]
|
|
|
|
|
node _T_76 = and(_T_74, _T_75) @[dec_decode_ctl.scala 242:116]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_76 @[dec_decode_ctl.scala 242:58]
|
|
|
|
|
io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 243:58]
|
|
|
|
|
io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 244:58]
|
|
|
|
|
node _T_77 = or(_T_70, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 245:74]
|
|
|
|
|
node _T_78 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 245:113]
|
|
|
|
|
node _T_79 = and(_T_77, _T_78) @[dec_decode_ctl.scala 245:111]
|
|
|
|
|
i0_br_error_all <= _T_79 @[dec_decode_ctl.scala 245:58]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 246:58]
|
|
|
|
|
io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 247:58]
|
|
|
|
|
io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 248:58]
|
|
|
|
|
io.dec_fa_error_index <= UInt<1>("h00") @[dec_decode_ctl.scala 257:29]
|
|
|
|
|
i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.zba <= i0_dp_raw.zba @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sh3add <= i0_dp_raw.sh3add @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sh2add <= i0_dp_raw.sh2add @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sh1add <= i0_dp_raw.sh1add @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.zbf <= i0_dp_raw.zbf @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.bfp <= i0_dp_raw.bfp @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.zbr <= i0_dp_raw.zbr @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.crc32c_w <= i0_dp_raw.crc32c_w @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.crc32c_h <= i0_dp_raw.crc32c_h @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.crc32c_b <= i0_dp_raw.crc32c_b @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.crc32_w <= i0_dp_raw.crc32_w @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.crc32_h <= i0_dp_raw.crc32_h @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.crc32_b <= i0_dp_raw.crc32_b @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.zbp <= i0_dp_raw.zbp @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.unshfl <= i0_dp_raw.unshfl @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.shfl <= i0_dp_raw.shfl @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.zbc <= i0_dp_raw.zbc @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.clmulr <= i0_dp_raw.clmulr @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.clmulh <= i0_dp_raw.clmulh @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.clmul <= i0_dp_raw.clmul @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.zbe <= i0_dp_raw.zbe @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.bdep <= i0_dp_raw.bdep @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.bext <= i0_dp_raw.bext @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.zbs <= i0_dp_raw.zbs @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sbext <= i0_dp_raw.sbext @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sbinv <= i0_dp_raw.sbinv @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sbclr <= i0_dp_raw.sbclr @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sbset <= i0_dp_raw.sbset @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.zbb <= i0_dp_raw.zbb @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.gorc <= i0_dp_raw.gorc @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.grev <= i0_dp_raw.grev @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.ror <= i0_dp_raw.ror @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.rol <= i0_dp_raw.rol @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.packh <= i0_dp_raw.packh @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.packu <= i0_dp_raw.packu @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.pack <= i0_dp_raw.pack @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.max <= i0_dp_raw.max @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.min <= i0_dp_raw.min @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sro <= i0_dp_raw.sro @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.slo <= i0_dp_raw.slo @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sext_h <= i0_dp_raw.sext_h @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.sext_b <= i0_dp_raw.sext_b @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.pcnt <= i0_dp_raw.pcnt @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.ctz <= i0_dp_raw.ctz @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
i0_dp.clz <= i0_dp_raw.clz @[dec_decode_ctl.scala 281:23]
|
|
|
|
|
node _T_80 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 282:25]
|
|
|
|
|
node _T_81 = bits(_T_80, 0, 0) @[dec_decode_ctl.scala 282:43]
|
|
|
|
|
when _T_81 : @[dec_decode_ctl.scala 282:50]
|
|
|
|
|
wire _T_82 : {clz : UInt<1>, ctz : UInt<1>, pcnt : UInt<1>, sext_b : UInt<1>, sext_h : UInt<1>, slo : UInt<1>, sro : UInt<1>, min : UInt<1>, max : UInt<1>, pack : UInt<1>, packu : UInt<1>, packh : UInt<1>, rol : UInt<1>, ror : UInt<1>, grev : UInt<1>, gorc : UInt<1>, zbb : UInt<1>, sbset : UInt<1>, sbclr : UInt<1>, sbinv : UInt<1>, sbext : UInt<1>, zbs : UInt<1>, bext : UInt<1>, bdep : UInt<1>, zbe : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, zbc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, zbp : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, zbr : UInt<1>, bfp : UInt<1>, zbf : UInt<1>, sh1add : UInt<1>, sh2add : UInt<1>, sh3add : UInt<1>, zba : UInt<1>, alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.div <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.low <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.word <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.half <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.by <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.land <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.add <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.store <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.load <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.zba <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sh3add <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sh2add <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sh1add <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.zbf <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.zbr <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.zbp <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.zbc <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.zbe <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.zbs <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sbext <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sbinv <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sbclr <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sbset <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.zbb <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.gorc <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.ror <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.rol <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.packh <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.packu <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.pack <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.max <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.min <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sro <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.slo <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sext_h <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.sext_b <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.pcnt <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.ctz <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
_T_82.clz <= UInt<1>("h00") @[dec_decode_ctl.scala 283:38]
|
|
|
|
|
i0_dp.legal <= _T_82.legal @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.pm_alu <= _T_82.pm_alu @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.fence_i <= _T_82.fence_i @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.fence <= _T_82.fence @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.rem <= _T_82.rem @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.div <= _T_82.div @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.low <= _T_82.low @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.rs2_sign <= _T_82.rs2_sign @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.rs1_sign <= _T_82.rs1_sign @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.mul <= _T_82.mul @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.mret <= _T_82.mret @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.ecall <= _T_82.ecall @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.ebreak <= _T_82.ebreak @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.postsync <= _T_82.postsync @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.presync <= _T_82.presync @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.csr_imm <= _T_82.csr_imm @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.csr_write <= _T_82.csr_write @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.csr_set <= _T_82.csr_set @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.csr_clr <= _T_82.csr_clr @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.csr_read <= _T_82.csr_read @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.word <= _T_82.word @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.half <= _T_82.half @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.by <= _T_82.by @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.jal <= _T_82.jal @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.blt <= _T_82.blt @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.bge <= _T_82.bge @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.bne <= _T_82.bne @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.beq <= _T_82.beq @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.condbr <= _T_82.condbr @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.unsign <= _T_82.unsign @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.slt <= _T_82.slt @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.srl <= _T_82.srl @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sra <= _T_82.sra @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sll <= _T_82.sll @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.lxor <= _T_82.lxor @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.lor <= _T_82.lor @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.land <= _T_82.land @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sub <= _T_82.sub @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.add <= _T_82.add @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.lsu <= _T_82.lsu @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.store <= _T_82.store @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.load <= _T_82.load @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.pc <= _T_82.pc @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.imm20 <= _T_82.imm20 @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.shimm5 <= _T_82.shimm5 @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.rd <= _T_82.rd @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.imm12 <= _T_82.imm12 @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.rs2 <= _T_82.rs2 @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.rs1 <= _T_82.rs1 @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.alu <= _T_82.alu @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.zba <= _T_82.zba @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sh3add <= _T_82.sh3add @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sh2add <= _T_82.sh2add @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sh1add <= _T_82.sh1add @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.zbf <= _T_82.zbf @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.bfp <= _T_82.bfp @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.zbr <= _T_82.zbr @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.crc32c_w <= _T_82.crc32c_w @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.crc32c_h <= _T_82.crc32c_h @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.crc32c_b <= _T_82.crc32c_b @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.crc32_w <= _T_82.crc32_w @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.crc32_h <= _T_82.crc32_h @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.crc32_b <= _T_82.crc32_b @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.zbp <= _T_82.zbp @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.unshfl <= _T_82.unshfl @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.shfl <= _T_82.shfl @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.zbc <= _T_82.zbc @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.clmulr <= _T_82.clmulr @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.clmulh <= _T_82.clmulh @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.clmul <= _T_82.clmul @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.zbe <= _T_82.zbe @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.bdep <= _T_82.bdep @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.bext <= _T_82.bext @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.zbs <= _T_82.zbs @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sbext <= _T_82.sbext @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sbinv <= _T_82.sbinv @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sbclr <= _T_82.sbclr @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sbset <= _T_82.sbset @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.zbb <= _T_82.zbb @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.gorc <= _T_82.gorc @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.grev <= _T_82.grev @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.ror <= _T_82.ror @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.rol <= _T_82.rol @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.packh <= _T_82.packh @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.packu <= _T_82.packu @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.pack <= _T_82.pack @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.max <= _T_82.max @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.min <= _T_82.min @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sro <= _T_82.sro @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.slo <= _T_82.slo @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sext_h <= _T_82.sext_h @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.sext_b <= _T_82.sext_b @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.pcnt <= _T_82.pcnt @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.ctz <= _T_82.ctz @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.clz <= _T_82.clz @[dec_decode_ctl.scala 283:23]
|
|
|
|
|
i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 284:23]
|
|
|
|
|
i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 285:23]
|
|
|
|
|
i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 286:23]
|
|
|
|
|
i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 287:23]
|
|
|
|
|
i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 288:23]
|
|
|
|
|
i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 289:23]
|
|
|
|
|
skip @[dec_decode_ctl.scala 282:50]
|
|
|
|
|
io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 293:36]
|
|
|
|
|
node _T_83 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 296:54]
|
|
|
|
|
node _T_84 = or(_T_83, i0_pja) @[dec_decode_ctl.scala 296:65]
|
|
|
|
|
node i0_predict_br = or(_T_84, i0_pret) @[dec_decode_ctl.scala 296:74]
|
|
|
|
|
node _T_85 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 297:65]
|
|
|
|
|
node _T_86 = and(_T_85, i0_brp_valid) @[dec_decode_ctl.scala 297:69]
|
|
|
|
|
node _T_87 = eq(_T_86, UInt<1>("h00")) @[dec_decode_ctl.scala 297:40]
|
|
|
|
|
node i0_predict_nt = and(_T_87, i0_predict_br) @[dec_decode_ctl.scala 297:85]
|
|
|
|
|
node _T_88 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 298:65]
|
|
|
|
|
node _T_89 = and(_T_88, i0_brp_valid) @[dec_decode_ctl.scala 298:69]
|
|
|
|
|
node i0_predict_t = and(_T_89, i0_predict_br) @[dec_decode_ctl.scala 298:85]
|
|
|
|
|
node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 299:40]
|
|
|
|
|
io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 301:37]
|
|
|
|
|
io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 302:37]
|
|
|
|
|
io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 305:33]
|
|
|
|
|
io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 306:33]
|
|
|
|
|
io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 307:33]
|
|
|
|
|
io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 308:33]
|
|
|
|
|
io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 309:33]
|
|
|
|
|
io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 310:33]
|
|
|
|
|
io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 311:33]
|
|
|
|
|
io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 312:33]
|
|
|
|
|
io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 313:33]
|
|
|
|
|
io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 314:33]
|
|
|
|
|
io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 315:33]
|
|
|
|
|
io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 316:33]
|
|
|
|
|
io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 317:33]
|
|
|
|
|
io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 318:33]
|
|
|
|
|
io.decode_exu.i0_ap.clz <= i0_dp.clz @[dec_decode_ctl.scala 319:33]
|
|
|
|
|
io.decode_exu.i0_ap.ctz <= i0_dp.ctz @[dec_decode_ctl.scala 320:33]
|
|
|
|
|
io.decode_exu.i0_ap.pcnt <= i0_dp.pcnt @[dec_decode_ctl.scala 321:33]
|
|
|
|
|
io.decode_exu.i0_ap.sext_b <= i0_dp.sext_b @[dec_decode_ctl.scala 322:33]
|
|
|
|
|
io.decode_exu.i0_ap.sext_h <= i0_dp.sext_h @[dec_decode_ctl.scala 323:33]
|
|
|
|
|
io.decode_exu.i0_ap.sh1add <= i0_dp.sh1add @[dec_decode_ctl.scala 324:33]
|
|
|
|
|
io.decode_exu.i0_ap.sh2add <= i0_dp.sh2add @[dec_decode_ctl.scala 325:33]
|
|
|
|
|
io.decode_exu.i0_ap.sh3add <= i0_dp.sh3add @[dec_decode_ctl.scala 326:33]
|
|
|
|
|
io.decode_exu.i0_ap.zba <= i0_dp.zba @[dec_decode_ctl.scala 327:33]
|
|
|
|
|
io.decode_exu.i0_ap.slo <= i0_dp.slo @[dec_decode_ctl.scala 328:33]
|
|
|
|
|
io.decode_exu.i0_ap.sro <= i0_dp.sro @[dec_decode_ctl.scala 329:33]
|
|
|
|
|
io.decode_exu.i0_ap.min <= i0_dp.min @[dec_decode_ctl.scala 330:33]
|
|
|
|
|
io.decode_exu.i0_ap.max <= i0_dp.max @[dec_decode_ctl.scala 331:33]
|
|
|
|
|
io.decode_exu.i0_ap.pack <= i0_dp.pack @[dec_decode_ctl.scala 332:33]
|
|
|
|
|
io.decode_exu.i0_ap.packu <= i0_dp.packu @[dec_decode_ctl.scala 333:33]
|
|
|
|
|
io.decode_exu.i0_ap.packh <= i0_dp.packh @[dec_decode_ctl.scala 334:33]
|
|
|
|
|
io.decode_exu.i0_ap.rol <= i0_dp.rol @[dec_decode_ctl.scala 335:33]
|
|
|
|
|
io.decode_exu.i0_ap.ror <= i0_dp.ror @[dec_decode_ctl.scala 336:33]
|
|
|
|
|
io.decode_exu.i0_ap.grev <= i0_dp.grev @[dec_decode_ctl.scala 337:33]
|
|
|
|
|
io.decode_exu.i0_ap.gorc <= i0_dp.gorc @[dec_decode_ctl.scala 338:33]
|
|
|
|
|
io.decode_exu.i0_ap.zbb <= i0_dp.zbb @[dec_decode_ctl.scala 339:33]
|
|
|
|
|
io.decode_exu.i0_ap.sbset <= i0_dp.sbset @[dec_decode_ctl.scala 340:33]
|
|
|
|
|
io.decode_exu.i0_ap.sbclr <= i0_dp.sbclr @[dec_decode_ctl.scala 341:33]
|
|
|
|
|
io.decode_exu.i0_ap.sbinv <= i0_dp.sbinv @[dec_decode_ctl.scala 342:33]
|
|
|
|
|
io.decode_exu.i0_ap.sbext <= i0_dp.sbext @[dec_decode_ctl.scala 343:33]
|
|
|
|
|
io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 344:33]
|
|
|
|
|
io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 345:33]
|
|
|
|
|
io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 346:33]
|
|
|
|
|
node _T_90 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 350:78]
|
|
|
|
|
node _T_91 = bits(_T_90, 0, 0) @[dec_decode_ctl.scala 350:137]
|
|
|
|
|
node _T_92 = shl(cam_write, 0) @[dec_decode_ctl.scala 350:158]
|
|
|
|
|
node _T_93 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 350:78]
|
|
|
|
|
node _T_94 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 350:120]
|
|
|
|
|
node _T_95 = bits(_T_93, 0, 0) @[dec_decode_ctl.scala 350:129]
|
|
|
|
|
node _T_96 = and(_T_94, _T_95) @[dec_decode_ctl.scala 350:126]
|
|
|
|
|
node _T_97 = bits(_T_96, 0, 0) @[dec_decode_ctl.scala 350:137]
|
|
|
|
|
node _T_98 = shl(cam_write, 1) @[dec_decode_ctl.scala 350:158]
|
|
|
|
|
node _T_99 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 350:78]
|
|
|
|
|
node _T_100 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 350:120]
|
|
|
|
|
node _T_101 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 350:129]
|
|
|
|
|
node _T_102 = and(_T_100, _T_101) @[dec_decode_ctl.scala 350:126]
|
|
|
|
|
node _T_103 = bits(_T_102, 0, 0) @[dec_decode_ctl.scala 350:120]
|
|
|
|
|
node _T_104 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 350:129]
|
|
|
|
|
node _T_105 = and(_T_103, _T_104) @[dec_decode_ctl.scala 350:126]
|
|
|
|
|
node _T_106 = bits(_T_105, 0, 0) @[dec_decode_ctl.scala 350:137]
|
|
|
|
|
node _T_107 = shl(cam_write, 2) @[dec_decode_ctl.scala 350:158]
|
|
|
|
|
node _T_108 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 350:78]
|
|
|
|
|
node _T_109 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 350:120]
|
|
|
|
|
node _T_110 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 350:129]
|
|
|
|
|
node _T_111 = and(_T_109, _T_110) @[dec_decode_ctl.scala 350:126]
|
|
|
|
|
node _T_112 = bits(_T_111, 0, 0) @[dec_decode_ctl.scala 350:120]
|
|
|
|
|
node _T_113 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 350:129]
|
|
|
|
|
node _T_114 = and(_T_112, _T_113) @[dec_decode_ctl.scala 350:126]
|
|
|
|
|
node _T_115 = bits(_T_114, 0, 0) @[dec_decode_ctl.scala 350:120]
|
|
|
|
|
node _T_116 = bits(_T_108, 0, 0) @[dec_decode_ctl.scala 350:129]
|
|
|
|
|
node _T_117 = and(_T_115, _T_116) @[dec_decode_ctl.scala 350:126]
|
|
|
|
|
node _T_118 = bits(_T_117, 0, 0) @[dec_decode_ctl.scala 350:137]
|
|
|
|
|
node _T_119 = shl(cam_write, 3) @[dec_decode_ctl.scala 350:158]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_120 = mux(_T_91, _T_92, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_121 = mux(_T_97, _T_98, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_122 = mux(_T_106, _T_107, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_123 = mux(_T_118, _T_119, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_124 = or(_T_120, _T_121) @[Mux.scala 27:72]
|
|
|
|
|
node _T_125 = or(_T_124, _T_122) @[Mux.scala 27:72]
|
|
|
|
|
node _T_126 = or(_T_125, _T_123) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_127 : UInt<4> @[Mux.scala 27:72]
|
|
|
|
|
_T_127 <= _T_126 @[Mux.scala 27:72]
|
2021-01-27 21:01:24 +08:00
|
|
|
cam_wen <= _T_127 @[dec_decode_ctl.scala 350:11]
|
|
|
|
|
cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 352:25]
|
|
|
|
|
node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 353:67]
|
|
|
|
|
node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 358:76]
|
|
|
|
|
node _T_128 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 361:48]
|
|
|
|
|
node nonblock_load_rd = mux(_T_128, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 361:31]
|
|
|
|
|
node _T_129 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 365:129]
|
2021-01-27 14:46:11 +08:00
|
|
|
reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_129 : @[Reg.scala 28:19]
|
|
|
|
|
nonblock_load_valid_m_delay <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-27 21:01:24 +08:00
|
|
|
node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 366:56]
|
|
|
|
|
node _T_130 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 368:66]
|
|
|
|
|
node _T_131 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_130) @[dec_decode_ctl.scala 368:45]
|
|
|
|
|
node _T_132 = and(_T_131, cam[0].valid) @[dec_decode_ctl.scala 368:87]
|
|
|
|
|
cam_inv_reset_val[0] <= _T_132 @[dec_decode_ctl.scala 368:26]
|
|
|
|
|
node _T_133 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 369:67]
|
|
|
|
|
node _T_134 = and(cam_data_reset, _T_133) @[dec_decode_ctl.scala 369:45]
|
|
|
|
|
node _T_135 = and(_T_134, cam_raw[0].valid) @[dec_decode_ctl.scala 369:88]
|
|
|
|
|
cam_data_reset_val[0] <= _T_135 @[dec_decode_ctl.scala 369:27]
|
|
|
|
|
wire _T_136 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_136.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_136.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_136.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_136.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
cam_in[0].bits.rd <= _T_136.bits.rd @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[0].bits.tag <= _T_136.bits.tag @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[0].bits.wb <= _T_136.bits.wb @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[0].valid <= _T_136.valid @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
node _T_137 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 373:32]
|
|
|
|
|
when _T_137 : @[dec_decode_ctl.scala 373:39]
|
|
|
|
|
cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 374:20]
|
|
|
|
|
skip @[dec_decode_ctl.scala 373:39]
|
|
|
|
|
node _T_138 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 376:17]
|
|
|
|
|
node _T_139 = bits(_T_138, 0, 0) @[dec_decode_ctl.scala 376:21]
|
|
|
|
|
when _T_139 : @[dec_decode_ctl.scala 376:28]
|
|
|
|
|
cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 377:27]
|
|
|
|
|
cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 378:32]
|
|
|
|
|
cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 379:32]
|
|
|
|
|
cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 380:32]
|
|
|
|
|
skip @[dec_decode_ctl.scala 376:28]
|
|
|
|
|
else : @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
node _T_140 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 381:37]
|
|
|
|
|
node _T_141 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 381:57]
|
|
|
|
|
node _T_142 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 381:85]
|
|
|
|
|
node _T_143 = and(_T_141, _T_142) @[dec_decode_ctl.scala 381:64]
|
|
|
|
|
node _T_144 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 381:123]
|
|
|
|
|
node _T_145 = and(_T_143, _T_144) @[dec_decode_ctl.scala 381:105]
|
|
|
|
|
node _T_146 = or(_T_140, _T_145) @[dec_decode_ctl.scala 381:44]
|
|
|
|
|
when _T_146 : @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 382:23]
|
|
|
|
|
skip @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
else : @[dec_decode_ctl.scala 383:16]
|
|
|
|
|
cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
skip @[dec_decode_ctl.scala 383:16]
|
|
|
|
|
node _T_147 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 386:37]
|
|
|
|
|
node _T_148 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 386:92]
|
|
|
|
|
node _T_149 = and(_T_147, _T_148) @[dec_decode_ctl.scala 386:44]
|
|
|
|
|
node _T_150 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 386:128]
|
|
|
|
|
node _T_151 = and(_T_149, _T_150) @[dec_decode_ctl.scala 386:113]
|
|
|
|
|
when _T_151 : @[dec_decode_ctl.scala 386:135]
|
|
|
|
|
cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 387:25]
|
|
|
|
|
skip @[dec_decode_ctl.scala 386:135]
|
|
|
|
|
when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 390:32]
|
|
|
|
|
cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 391:23]
|
|
|
|
|
skip @[dec_decode_ctl.scala 390:32]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_152 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}
|
|
|
|
|
_T_152.bits.rd <= cam_in[0].bits.rd
|
|
|
|
|
_T_152.bits.tag <= cam_in[0].bits.tag
|
|
|
|
|
_T_152.bits.wb <= cam_in[0].bits.wb
|
|
|
|
|
_T_152.valid <= cam_in[0].valid
|
|
|
|
|
node _T_153 = cat(cam_in[0].bits.wb, cam_in[0].bits.tag) @[lib.scala 494:61]
|
|
|
|
|
node _T_154 = cat(_T_153, cam_in[0].bits.rd) @[lib.scala 494:61]
|
|
|
|
|
node _T_155 = cat(_T_152.bits.wb, _T_152.bits.tag) @[lib.scala 494:74]
|
|
|
|
|
node _T_156 = cat(_T_155, _T_152.bits.rd) @[lib.scala 494:74]
|
|
|
|
|
node _T_157 = xor(_T_154, _T_156) @[lib.scala 494:68]
|
|
|
|
|
node _T_158 = orr(_T_157) @[lib.scala 494:82]
|
|
|
|
|
node _T_159 = xor(cam_in[0].valid, _T_152.valid) @[lib.scala 494:68]
|
|
|
|
|
node _T_160 = orr(_T_159) @[lib.scala 494:82]
|
|
|
|
|
node _T_161 = or(_T_158, _T_160) @[lib.scala 494:97]
|
|
|
|
|
wire _T_162 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46]
|
|
|
|
|
_T_162.bits.rd <= UInt<5>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_162.bits.tag <= UInt<3>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_162.bits.wb <= UInt<1>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_162.valid <= UInt<1>("h00") @[lib.scala 497:46]
|
|
|
|
|
reg _T_163 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_162)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_161 : @[Reg.scala 28:19]
|
|
|
|
|
_T_163.bits.rd <= cam_in[0].bits.rd @[Reg.scala 28:23]
|
|
|
|
|
_T_163.bits.tag <= cam_in[0].bits.tag @[Reg.scala 28:23]
|
|
|
|
|
_T_163.bits.wb <= cam_in[0].bits.wb @[Reg.scala 28:23]
|
|
|
|
|
_T_163.valid <= cam_in[0].valid @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_152.bits.rd <= _T_163.bits.rd @[lib.scala 497:16]
|
|
|
|
|
_T_152.bits.tag <= _T_163.bits.tag @[lib.scala 497:16]
|
|
|
|
|
_T_152.bits.wb <= _T_163.bits.wb @[lib.scala 497:16]
|
|
|
|
|
_T_152.valid <= _T_163.valid @[lib.scala 497:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
cam_raw[0].bits.rd <= _T_152.bits.rd @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[0].bits.tag <= _T_152.bits.tag @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[0].bits.wb <= _T_152.bits.wb @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[0].valid <= _T_152.valid @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
node _T_164 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 395:46]
|
|
|
|
|
node _T_165 = and(_T_164, cam_raw[0].valid) @[dec_decode_ctl.scala 395:71]
|
|
|
|
|
nonblock_load_write[0] <= _T_165 @[dec_decode_ctl.scala 395:28]
|
|
|
|
|
node _T_166 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 368:66]
|
|
|
|
|
node _T_167 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_166) @[dec_decode_ctl.scala 368:45]
|
|
|
|
|
node _T_168 = and(_T_167, cam[1].valid) @[dec_decode_ctl.scala 368:87]
|
|
|
|
|
cam_inv_reset_val[1] <= _T_168 @[dec_decode_ctl.scala 368:26]
|
|
|
|
|
node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 369:67]
|
|
|
|
|
node _T_170 = and(cam_data_reset, _T_169) @[dec_decode_ctl.scala 369:45]
|
|
|
|
|
node _T_171 = and(_T_170, cam_raw[1].valid) @[dec_decode_ctl.scala 369:88]
|
|
|
|
|
cam_data_reset_val[1] <= _T_171 @[dec_decode_ctl.scala 369:27]
|
|
|
|
|
wire _T_172 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_172.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_172.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_172.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_172.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
cam_in[1].bits.rd <= _T_172.bits.rd @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[1].bits.tag <= _T_172.bits.tag @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[1].bits.wb <= _T_172.bits.wb @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[1].valid <= _T_172.valid @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
node _T_173 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 373:32]
|
|
|
|
|
when _T_173 : @[dec_decode_ctl.scala 373:39]
|
|
|
|
|
cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 374:20]
|
|
|
|
|
skip @[dec_decode_ctl.scala 373:39]
|
|
|
|
|
node _T_174 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 376:17]
|
|
|
|
|
node _T_175 = bits(_T_174, 0, 0) @[dec_decode_ctl.scala 376:21]
|
|
|
|
|
when _T_175 : @[dec_decode_ctl.scala 376:28]
|
|
|
|
|
cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 377:27]
|
|
|
|
|
cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 378:32]
|
|
|
|
|
cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 379:32]
|
|
|
|
|
cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 380:32]
|
|
|
|
|
skip @[dec_decode_ctl.scala 376:28]
|
|
|
|
|
else : @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
node _T_176 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 381:37]
|
|
|
|
|
node _T_177 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 381:57]
|
|
|
|
|
node _T_178 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 381:85]
|
|
|
|
|
node _T_179 = and(_T_177, _T_178) @[dec_decode_ctl.scala 381:64]
|
|
|
|
|
node _T_180 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 381:123]
|
|
|
|
|
node _T_181 = and(_T_179, _T_180) @[dec_decode_ctl.scala 381:105]
|
|
|
|
|
node _T_182 = or(_T_176, _T_181) @[dec_decode_ctl.scala 381:44]
|
|
|
|
|
when _T_182 : @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 382:23]
|
|
|
|
|
skip @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
else : @[dec_decode_ctl.scala 383:16]
|
|
|
|
|
cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
skip @[dec_decode_ctl.scala 383:16]
|
|
|
|
|
node _T_183 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 386:37]
|
|
|
|
|
node _T_184 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 386:92]
|
|
|
|
|
node _T_185 = and(_T_183, _T_184) @[dec_decode_ctl.scala 386:44]
|
|
|
|
|
node _T_186 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 386:128]
|
|
|
|
|
node _T_187 = and(_T_185, _T_186) @[dec_decode_ctl.scala 386:113]
|
|
|
|
|
when _T_187 : @[dec_decode_ctl.scala 386:135]
|
|
|
|
|
cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 387:25]
|
|
|
|
|
skip @[dec_decode_ctl.scala 386:135]
|
|
|
|
|
when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 390:32]
|
|
|
|
|
cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 391:23]
|
|
|
|
|
skip @[dec_decode_ctl.scala 390:32]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_188 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}
|
|
|
|
|
_T_188.bits.rd <= cam_in[1].bits.rd
|
|
|
|
|
_T_188.bits.tag <= cam_in[1].bits.tag
|
|
|
|
|
_T_188.bits.wb <= cam_in[1].bits.wb
|
|
|
|
|
_T_188.valid <= cam_in[1].valid
|
|
|
|
|
node _T_189 = cat(cam_in[1].bits.wb, cam_in[1].bits.tag) @[lib.scala 494:61]
|
|
|
|
|
node _T_190 = cat(_T_189, cam_in[1].bits.rd) @[lib.scala 494:61]
|
|
|
|
|
node _T_191 = cat(_T_188.bits.wb, _T_188.bits.tag) @[lib.scala 494:74]
|
|
|
|
|
node _T_192 = cat(_T_191, _T_188.bits.rd) @[lib.scala 494:74]
|
|
|
|
|
node _T_193 = xor(_T_190, _T_192) @[lib.scala 494:68]
|
|
|
|
|
node _T_194 = orr(_T_193) @[lib.scala 494:82]
|
|
|
|
|
node _T_195 = xor(cam_in[1].valid, _T_188.valid) @[lib.scala 494:68]
|
|
|
|
|
node _T_196 = orr(_T_195) @[lib.scala 494:82]
|
|
|
|
|
node _T_197 = or(_T_194, _T_196) @[lib.scala 494:97]
|
|
|
|
|
wire _T_198 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46]
|
|
|
|
|
_T_198.bits.rd <= UInt<5>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_198.bits.tag <= UInt<3>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_198.bits.wb <= UInt<1>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_198.valid <= UInt<1>("h00") @[lib.scala 497:46]
|
|
|
|
|
reg _T_199 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_198)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_197 : @[Reg.scala 28:19]
|
|
|
|
|
_T_199.bits.rd <= cam_in[1].bits.rd @[Reg.scala 28:23]
|
|
|
|
|
_T_199.bits.tag <= cam_in[1].bits.tag @[Reg.scala 28:23]
|
|
|
|
|
_T_199.bits.wb <= cam_in[1].bits.wb @[Reg.scala 28:23]
|
|
|
|
|
_T_199.valid <= cam_in[1].valid @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_188.bits.rd <= _T_199.bits.rd @[lib.scala 497:16]
|
|
|
|
|
_T_188.bits.tag <= _T_199.bits.tag @[lib.scala 497:16]
|
|
|
|
|
_T_188.bits.wb <= _T_199.bits.wb @[lib.scala 497:16]
|
|
|
|
|
_T_188.valid <= _T_199.valid @[lib.scala 497:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
cam_raw[1].bits.rd <= _T_188.bits.rd @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[1].bits.tag <= _T_188.bits.tag @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[1].bits.wb <= _T_188.bits.wb @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[1].valid <= _T_188.valid @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
node _T_200 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 395:46]
|
|
|
|
|
node _T_201 = and(_T_200, cam_raw[1].valid) @[dec_decode_ctl.scala 395:71]
|
|
|
|
|
nonblock_load_write[1] <= _T_201 @[dec_decode_ctl.scala 395:28]
|
|
|
|
|
node _T_202 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 368:66]
|
|
|
|
|
node _T_203 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_202) @[dec_decode_ctl.scala 368:45]
|
|
|
|
|
node _T_204 = and(_T_203, cam[2].valid) @[dec_decode_ctl.scala 368:87]
|
|
|
|
|
cam_inv_reset_val[2] <= _T_204 @[dec_decode_ctl.scala 368:26]
|
|
|
|
|
node _T_205 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 369:67]
|
|
|
|
|
node _T_206 = and(cam_data_reset, _T_205) @[dec_decode_ctl.scala 369:45]
|
|
|
|
|
node _T_207 = and(_T_206, cam_raw[2].valid) @[dec_decode_ctl.scala 369:88]
|
|
|
|
|
cam_data_reset_val[2] <= _T_207 @[dec_decode_ctl.scala 369:27]
|
|
|
|
|
wire _T_208 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_208.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_208.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_208.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_208.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
cam_in[2].bits.rd <= _T_208.bits.rd @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[2].bits.tag <= _T_208.bits.tag @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[2].bits.wb <= _T_208.bits.wb @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[2].valid <= _T_208.valid @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
node _T_209 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 373:32]
|
|
|
|
|
when _T_209 : @[dec_decode_ctl.scala 373:39]
|
|
|
|
|
cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 374:20]
|
|
|
|
|
skip @[dec_decode_ctl.scala 373:39]
|
|
|
|
|
node _T_210 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 376:17]
|
|
|
|
|
node _T_211 = bits(_T_210, 0, 0) @[dec_decode_ctl.scala 376:21]
|
|
|
|
|
when _T_211 : @[dec_decode_ctl.scala 376:28]
|
|
|
|
|
cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 377:27]
|
|
|
|
|
cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 378:32]
|
|
|
|
|
cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 379:32]
|
|
|
|
|
cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 380:32]
|
|
|
|
|
skip @[dec_decode_ctl.scala 376:28]
|
|
|
|
|
else : @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
node _T_212 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 381:37]
|
|
|
|
|
node _T_213 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 381:57]
|
|
|
|
|
node _T_214 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 381:85]
|
|
|
|
|
node _T_215 = and(_T_213, _T_214) @[dec_decode_ctl.scala 381:64]
|
|
|
|
|
node _T_216 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 381:123]
|
|
|
|
|
node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 381:105]
|
|
|
|
|
node _T_218 = or(_T_212, _T_217) @[dec_decode_ctl.scala 381:44]
|
|
|
|
|
when _T_218 : @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 382:23]
|
|
|
|
|
skip @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
else : @[dec_decode_ctl.scala 383:16]
|
|
|
|
|
cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
skip @[dec_decode_ctl.scala 383:16]
|
|
|
|
|
node _T_219 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 386:37]
|
|
|
|
|
node _T_220 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 386:92]
|
|
|
|
|
node _T_221 = and(_T_219, _T_220) @[dec_decode_ctl.scala 386:44]
|
|
|
|
|
node _T_222 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 386:128]
|
|
|
|
|
node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 386:113]
|
|
|
|
|
when _T_223 : @[dec_decode_ctl.scala 386:135]
|
|
|
|
|
cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 387:25]
|
|
|
|
|
skip @[dec_decode_ctl.scala 386:135]
|
|
|
|
|
when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 390:32]
|
|
|
|
|
cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 391:23]
|
|
|
|
|
skip @[dec_decode_ctl.scala 390:32]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_224 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}
|
|
|
|
|
_T_224.bits.rd <= cam_in[2].bits.rd
|
|
|
|
|
_T_224.bits.tag <= cam_in[2].bits.tag
|
|
|
|
|
_T_224.bits.wb <= cam_in[2].bits.wb
|
|
|
|
|
_T_224.valid <= cam_in[2].valid
|
|
|
|
|
node _T_225 = cat(cam_in[2].bits.wb, cam_in[2].bits.tag) @[lib.scala 494:61]
|
|
|
|
|
node _T_226 = cat(_T_225, cam_in[2].bits.rd) @[lib.scala 494:61]
|
|
|
|
|
node _T_227 = cat(_T_224.bits.wb, _T_224.bits.tag) @[lib.scala 494:74]
|
|
|
|
|
node _T_228 = cat(_T_227, _T_224.bits.rd) @[lib.scala 494:74]
|
|
|
|
|
node _T_229 = xor(_T_226, _T_228) @[lib.scala 494:68]
|
|
|
|
|
node _T_230 = orr(_T_229) @[lib.scala 494:82]
|
|
|
|
|
node _T_231 = xor(cam_in[2].valid, _T_224.valid) @[lib.scala 494:68]
|
|
|
|
|
node _T_232 = orr(_T_231) @[lib.scala 494:82]
|
|
|
|
|
node _T_233 = or(_T_230, _T_232) @[lib.scala 494:97]
|
|
|
|
|
wire _T_234 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46]
|
|
|
|
|
_T_234.bits.rd <= UInt<5>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_234.bits.tag <= UInt<3>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_234.bits.wb <= UInt<1>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_234.valid <= UInt<1>("h00") @[lib.scala 497:46]
|
|
|
|
|
reg _T_235 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_234)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_233 : @[Reg.scala 28:19]
|
|
|
|
|
_T_235.bits.rd <= cam_in[2].bits.rd @[Reg.scala 28:23]
|
|
|
|
|
_T_235.bits.tag <= cam_in[2].bits.tag @[Reg.scala 28:23]
|
|
|
|
|
_T_235.bits.wb <= cam_in[2].bits.wb @[Reg.scala 28:23]
|
|
|
|
|
_T_235.valid <= cam_in[2].valid @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_224.bits.rd <= _T_235.bits.rd @[lib.scala 497:16]
|
|
|
|
|
_T_224.bits.tag <= _T_235.bits.tag @[lib.scala 497:16]
|
|
|
|
|
_T_224.bits.wb <= _T_235.bits.wb @[lib.scala 497:16]
|
|
|
|
|
_T_224.valid <= _T_235.valid @[lib.scala 497:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
cam_raw[2].bits.rd <= _T_224.bits.rd @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[2].bits.tag <= _T_224.bits.tag @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[2].bits.wb <= _T_224.bits.wb @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[2].valid <= _T_224.valid @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
node _T_236 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 395:46]
|
|
|
|
|
node _T_237 = and(_T_236, cam_raw[2].valid) @[dec_decode_ctl.scala 395:71]
|
|
|
|
|
nonblock_load_write[2] <= _T_237 @[dec_decode_ctl.scala 395:28]
|
|
|
|
|
node _T_238 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 368:66]
|
|
|
|
|
node _T_239 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_238) @[dec_decode_ctl.scala 368:45]
|
|
|
|
|
node _T_240 = and(_T_239, cam[3].valid) @[dec_decode_ctl.scala 368:87]
|
|
|
|
|
cam_inv_reset_val[3] <= _T_240 @[dec_decode_ctl.scala 368:26]
|
|
|
|
|
node _T_241 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 369:67]
|
|
|
|
|
node _T_242 = and(cam_data_reset, _T_241) @[dec_decode_ctl.scala 369:45]
|
|
|
|
|
node _T_243 = and(_T_242, cam_raw[3].valid) @[dec_decode_ctl.scala 369:88]
|
|
|
|
|
cam_data_reset_val[3] <= _T_243 @[dec_decode_ctl.scala 369:27]
|
|
|
|
|
wire _T_244 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_244.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_244.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_244.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
_T_244.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 370:28]
|
|
|
|
|
cam_in[3].bits.rd <= _T_244.bits.rd @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[3].bits.tag <= _T_244.bits.tag @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[3].bits.wb <= _T_244.bits.wb @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam_in[3].valid <= _T_244.valid @[dec_decode_ctl.scala 370:14]
|
|
|
|
|
cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 371:11]
|
|
|
|
|
node _T_245 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 373:32]
|
|
|
|
|
when _T_245 : @[dec_decode_ctl.scala 373:39]
|
|
|
|
|
cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 374:20]
|
|
|
|
|
skip @[dec_decode_ctl.scala 373:39]
|
|
|
|
|
node _T_246 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 376:17]
|
|
|
|
|
node _T_247 = bits(_T_246, 0, 0) @[dec_decode_ctl.scala 376:21]
|
|
|
|
|
when _T_247 : @[dec_decode_ctl.scala 376:28]
|
|
|
|
|
cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 377:27]
|
|
|
|
|
cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 378:32]
|
|
|
|
|
cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 379:32]
|
|
|
|
|
cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 380:32]
|
|
|
|
|
skip @[dec_decode_ctl.scala 376:28]
|
|
|
|
|
else : @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
node _T_248 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 381:37]
|
|
|
|
|
node _T_249 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 381:57]
|
|
|
|
|
node _T_250 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 381:85]
|
|
|
|
|
node _T_251 = and(_T_249, _T_250) @[dec_decode_ctl.scala 381:64]
|
|
|
|
|
node _T_252 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 381:123]
|
|
|
|
|
node _T_253 = and(_T_251, _T_252) @[dec_decode_ctl.scala 381:105]
|
|
|
|
|
node _T_254 = or(_T_248, _T_253) @[dec_decode_ctl.scala 381:44]
|
|
|
|
|
when _T_254 : @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 382:23]
|
|
|
|
|
skip @[dec_decode_ctl.scala 381:131]
|
|
|
|
|
else : @[dec_decode_ctl.scala 383:16]
|
|
|
|
|
cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 384:22]
|
|
|
|
|
skip @[dec_decode_ctl.scala 383:16]
|
|
|
|
|
node _T_255 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 386:37]
|
|
|
|
|
node _T_256 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 386:92]
|
|
|
|
|
node _T_257 = and(_T_255, _T_256) @[dec_decode_ctl.scala 386:44]
|
|
|
|
|
node _T_258 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 386:128]
|
|
|
|
|
node _T_259 = and(_T_257, _T_258) @[dec_decode_ctl.scala 386:113]
|
|
|
|
|
when _T_259 : @[dec_decode_ctl.scala 386:135]
|
|
|
|
|
cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 387:25]
|
|
|
|
|
skip @[dec_decode_ctl.scala 386:135]
|
|
|
|
|
when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 390:32]
|
|
|
|
|
cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 391:23]
|
|
|
|
|
skip @[dec_decode_ctl.scala 390:32]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_260 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}
|
|
|
|
|
_T_260.bits.rd <= cam_in[3].bits.rd
|
|
|
|
|
_T_260.bits.tag <= cam_in[3].bits.tag
|
|
|
|
|
_T_260.bits.wb <= cam_in[3].bits.wb
|
|
|
|
|
_T_260.valid <= cam_in[3].valid
|
|
|
|
|
node _T_261 = cat(cam_in[3].bits.wb, cam_in[3].bits.tag) @[lib.scala 494:61]
|
|
|
|
|
node _T_262 = cat(_T_261, cam_in[3].bits.rd) @[lib.scala 494:61]
|
|
|
|
|
node _T_263 = cat(_T_260.bits.wb, _T_260.bits.tag) @[lib.scala 494:74]
|
|
|
|
|
node _T_264 = cat(_T_263, _T_260.bits.rd) @[lib.scala 494:74]
|
|
|
|
|
node _T_265 = xor(_T_262, _T_264) @[lib.scala 494:68]
|
|
|
|
|
node _T_266 = orr(_T_265) @[lib.scala 494:82]
|
|
|
|
|
node _T_267 = xor(cam_in[3].valid, _T_260.valid) @[lib.scala 494:68]
|
|
|
|
|
node _T_268 = orr(_T_267) @[lib.scala 494:82]
|
|
|
|
|
node _T_269 = or(_T_266, _T_268) @[lib.scala 494:97]
|
|
|
|
|
wire _T_270 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[lib.scala 497:46]
|
|
|
|
|
_T_270.bits.rd <= UInt<5>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_270.bits.tag <= UInt<3>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_270.bits.wb <= UInt<1>("h00") @[lib.scala 497:46]
|
|
|
|
|
_T_270.valid <= UInt<1>("h00") @[lib.scala 497:46]
|
|
|
|
|
reg _T_271 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, clock with : (reset => (reset, _T_270)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_269 : @[Reg.scala 28:19]
|
|
|
|
|
_T_271.bits.rd <= cam_in[3].bits.rd @[Reg.scala 28:23]
|
|
|
|
|
_T_271.bits.tag <= cam_in[3].bits.tag @[Reg.scala 28:23]
|
|
|
|
|
_T_271.bits.wb <= cam_in[3].bits.wb @[Reg.scala 28:23]
|
|
|
|
|
_T_271.valid <= cam_in[3].valid @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_260.bits.rd <= _T_271.bits.rd @[lib.scala 497:16]
|
|
|
|
|
_T_260.bits.tag <= _T_271.bits.tag @[lib.scala 497:16]
|
|
|
|
|
_T_260.bits.wb <= _T_271.bits.wb @[lib.scala 497:16]
|
|
|
|
|
_T_260.valid <= _T_271.valid @[lib.scala 497:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
cam_raw[3].bits.rd <= _T_260.bits.rd @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[3].bits.tag <= _T_260.bits.tag @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[3].bits.wb <= _T_260.bits.wb @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
cam_raw[3].valid <= _T_260.valid @[dec_decode_ctl.scala 394:15]
|
|
|
|
|
node _T_272 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 395:46]
|
|
|
|
|
node _T_273 = and(_T_272, cam_raw[3].valid) @[dec_decode_ctl.scala 395:71]
|
|
|
|
|
nonblock_load_write[3] <= _T_273 @[dec_decode_ctl.scala 395:28]
|
|
|
|
|
io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 398:29]
|
|
|
|
|
node _T_274 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 400:49]
|
|
|
|
|
node nonblock_load_cancel = and(_T_274, i0_wen_r) @[dec_decode_ctl.scala 400:81]
|
|
|
|
|
node _T_275 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 401:108]
|
|
|
|
|
node _T_276 = or(_T_275, nonblock_load_write[2]) @[dec_decode_ctl.scala 401:108]
|
|
|
|
|
node _T_277 = or(_T_276, nonblock_load_write[3]) @[dec_decode_ctl.scala 401:108]
|
|
|
|
|
node _T_278 = bits(_T_277, 0, 0) @[dec_decode_ctl.scala 401:112]
|
|
|
|
|
node _T_279 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_278) @[dec_decode_ctl.scala 401:77]
|
|
|
|
|
node _T_280 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 401:122]
|
|
|
|
|
node _T_281 = and(_T_279, _T_280) @[dec_decode_ctl.scala 401:119]
|
|
|
|
|
io.dec_nonblock_load_wen <= _T_281 @[dec_decode_ctl.scala 401:28]
|
|
|
|
|
node _T_282 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 402:54]
|
|
|
|
|
node _T_283 = and(_T_282, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 402:66]
|
|
|
|
|
node _T_284 = and(_T_283, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 402:110]
|
|
|
|
|
node _T_285 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 402:161]
|
|
|
|
|
node _T_286 = and(_T_285, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 402:173]
|
|
|
|
|
node _T_287 = and(_T_286, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 402:217]
|
|
|
|
|
node i0_nonblock_boundary_stall = or(_T_284, _T_287) @[dec_decode_ctl.scala 402:142]
|
|
|
|
|
i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 404:26]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_288 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_289 = mux(_T_288, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_290 = and(_T_289, cam[0].bits.rd) @[dec_decode_ctl.scala 406:88]
|
|
|
|
|
node _T_291 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 406:137]
|
|
|
|
|
node _T_292 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 406:170]
|
|
|
|
|
node _T_293 = and(_T_291, _T_292) @[dec_decode_ctl.scala 406:152]
|
|
|
|
|
node _T_294 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 406:214]
|
|
|
|
|
node _T_295 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 406:247]
|
|
|
|
|
node _T_296 = and(_T_294, _T_295) @[dec_decode_ctl.scala 406:229]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_297 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_298 = mux(_T_297, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_299 = and(_T_298, cam[1].bits.rd) @[dec_decode_ctl.scala 406:88]
|
|
|
|
|
node _T_300 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 406:137]
|
|
|
|
|
node _T_301 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 406:170]
|
|
|
|
|
node _T_302 = and(_T_300, _T_301) @[dec_decode_ctl.scala 406:152]
|
|
|
|
|
node _T_303 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 406:214]
|
|
|
|
|
node _T_304 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 406:247]
|
|
|
|
|
node _T_305 = and(_T_303, _T_304) @[dec_decode_ctl.scala 406:229]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_306 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_307 = mux(_T_306, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_308 = and(_T_307, cam[2].bits.rd) @[dec_decode_ctl.scala 406:88]
|
|
|
|
|
node _T_309 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 406:137]
|
|
|
|
|
node _T_310 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 406:170]
|
|
|
|
|
node _T_311 = and(_T_309, _T_310) @[dec_decode_ctl.scala 406:152]
|
|
|
|
|
node _T_312 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 406:214]
|
|
|
|
|
node _T_313 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 406:247]
|
|
|
|
|
node _T_314 = and(_T_312, _T_313) @[dec_decode_ctl.scala 406:229]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_315 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_316 = mux(_T_315, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_317 = and(_T_316, cam[3].bits.rd) @[dec_decode_ctl.scala 406:88]
|
|
|
|
|
node _T_318 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 406:137]
|
|
|
|
|
node _T_319 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 406:170]
|
|
|
|
|
node _T_320 = and(_T_318, _T_319) @[dec_decode_ctl.scala 406:152]
|
|
|
|
|
node _T_321 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 406:214]
|
|
|
|
|
node _T_322 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 406:247]
|
|
|
|
|
node _T_323 = and(_T_321, _T_322) @[dec_decode_ctl.scala 406:229]
|
|
|
|
|
node _T_324 = or(_T_290, _T_299) @[dec_decode_ctl.scala 407:69]
|
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|
|
|
node _T_325 = or(_T_324, _T_308) @[dec_decode_ctl.scala 407:69]
|
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|
|
|
node waddr = or(_T_325, _T_317) @[dec_decode_ctl.scala 407:69]
|
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|
|
node _T_326 = or(_T_293, _T_302) @[dec_decode_ctl.scala 407:102]
|
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|
|
node _T_327 = or(_T_326, _T_311) @[dec_decode_ctl.scala 407:102]
|
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|
|
node ld_stall_1 = or(_T_327, _T_320) @[dec_decode_ctl.scala 407:102]
|
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|
node _T_328 = or(_T_296, _T_305) @[dec_decode_ctl.scala 407:134]
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|
node _T_329 = or(_T_328, _T_314) @[dec_decode_ctl.scala 407:134]
|
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|
node ld_stall_2 = or(_T_329, _T_323) @[dec_decode_ctl.scala 407:134]
|
|
|
|
|
io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 408:29]
|
|
|
|
|
node _T_330 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 409:38]
|
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|
|
|
node _T_331 = or(_T_330, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 409:51]
|
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|
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|
i0_nonblock_load_stall <= _T_331 @[dec_decode_ctl.scala 409:25]
|
|
|
|
|
node _T_332 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 418:34]
|
|
|
|
|
node i0_br_unpred = and(i0_dp.jal, _T_332) @[dec_decode_ctl.scala 418:32]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_333 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_334 = mux(_T_333, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_335 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 430:16]
|
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|
|
|
node _T_336 = bits(_T_335, 0, 0) @[dec_decode_ctl.scala 430:30]
|
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|
|
node _T_337 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 431:6]
|
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|
|
|
node _T_338 = and(_T_337, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 431:16]
|
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|
|
node _T_339 = bits(_T_338, 0, 0) @[dec_decode_ctl.scala 431:30]
|
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|
|
|
node _T_340 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 432:18]
|
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|
|
|
node _T_341 = and(csr_read, _T_340) @[dec_decode_ctl.scala 432:16]
|
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|
|
node _T_342 = bits(_T_341, 0, 0) @[dec_decode_ctl.scala 432:30]
|
|
|
|
|
node _T_343 = or(i0_dp.zbb, i0_dp.zbs) @[dec_decode_ctl.scala 433:16]
|
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|
|
node _T_344 = or(_T_343, i0_dp.zbe) @[dec_decode_ctl.scala 433:28]
|
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|
node _T_345 = or(_T_344, i0_dp.zbc) @[dec_decode_ctl.scala 433:40]
|
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|
node _T_346 = or(_T_345, i0_dp.zbp) @[dec_decode_ctl.scala 433:52]
|
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|
node _T_347 = or(_T_346, i0_dp.zbr) @[dec_decode_ctl.scala 433:65]
|
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|
|
node _T_348 = or(_T_347, i0_dp.zbf) @[dec_decode_ctl.scala 433:77]
|
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|
|
|
node _T_349 = or(_T_348, i0_dp.zba) @[dec_decode_ctl.scala 433:89]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_350 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16]
|
|
|
|
|
node _T_351 = mux(i0_dp.load, UInt<4>("h02"), _T_350) @[Mux.scala 98:16]
|
|
|
|
|
node _T_352 = mux(i0_dp.store, UInt<4>("h03"), _T_351) @[Mux.scala 98:16]
|
|
|
|
|
node _T_353 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_352) @[Mux.scala 98:16]
|
|
|
|
|
node _T_354 = mux(_T_349, UInt<4>("h0f"), _T_353) @[Mux.scala 98:16]
|
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|
|
|
node _T_355 = mux(_T_342, UInt<4>("h05"), _T_354) @[Mux.scala 98:16]
|
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|
|
node _T_356 = mux(_T_339, UInt<4>("h06"), _T_355) @[Mux.scala 98:16]
|
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|
|
node _T_357 = mux(_T_336, UInt<4>("h07"), _T_356) @[Mux.scala 98:16]
|
|
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|
|
node _T_358 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_357) @[Mux.scala 98:16]
|
|
|
|
|
node _T_359 = mux(i0_dp.ecall, UInt<4>("h09"), _T_358) @[Mux.scala 98:16]
|
|
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|
|
node _T_360 = mux(i0_dp.fence, UInt<4>("h0a"), _T_359) @[Mux.scala 98:16]
|
|
|
|
|
node _T_361 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_360) @[Mux.scala 98:16]
|
|
|
|
|
node _T_362 = mux(i0_dp.mret, UInt<4>("h0c"), _T_361) @[Mux.scala 98:16]
|
|
|
|
|
node _T_363 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_362) @[Mux.scala 98:16]
|
|
|
|
|
node _T_364 = mux(i0_dp.jal, UInt<4>("h0e"), _T_363) @[Mux.scala 98:16]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_365 = and(_T_334, _T_364) @[dec_decode_ctl.scala 422:49]
|
|
|
|
|
d_t.pmu_i0_itype <= _T_365 @[dec_decode_ctl.scala 422:21]
|
|
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|
|
inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 440:22]
|
2021-01-27 14:46:11 +08:00
|
|
|
i0_dec.clock <= clock
|
|
|
|
|
i0_dec.reset <= reset
|
2021-01-27 21:01:24 +08:00
|
|
|
i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 441:16]
|
|
|
|
|
i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 442:12]
|
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|
|
|
i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 442:12]
|
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|
|
|
i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 442:12]
|
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|
|
|
i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 442:12]
|
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|
|
|
i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.zba <= i0_dec.io.out.zba @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sh3add <= i0_dec.io.out.sh3add @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sh2add <= i0_dec.io.out.sh2add @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sh1add <= i0_dec.io.out.sh1add @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.zbf <= i0_dec.io.out.zbf @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.bfp <= i0_dec.io.out.bfp @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.zbr <= i0_dec.io.out.zbr @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.crc32c_w <= i0_dec.io.out.crc32c_w @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.crc32c_h <= i0_dec.io.out.crc32c_h @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.crc32c_b <= i0_dec.io.out.crc32c_b @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.crc32_w <= i0_dec.io.out.crc32_w @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.crc32_h <= i0_dec.io.out.crc32_h @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.crc32_b <= i0_dec.io.out.crc32_b @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.zbp <= i0_dec.io.out.zbp @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.unshfl <= i0_dec.io.out.unshfl @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.shfl <= i0_dec.io.out.shfl @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.zbc <= i0_dec.io.out.zbc @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.clmulr <= i0_dec.io.out.clmulr @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.clmulh <= i0_dec.io.out.clmulh @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.clmul <= i0_dec.io.out.clmul @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.zbe <= i0_dec.io.out.zbe @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.bdep <= i0_dec.io.out.bdep @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.bext <= i0_dec.io.out.bext @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.zbs <= i0_dec.io.out.zbs @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sbext <= i0_dec.io.out.sbext @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sbinv <= i0_dec.io.out.sbinv @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sbclr <= i0_dec.io.out.sbclr @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sbset <= i0_dec.io.out.sbset @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.zbb <= i0_dec.io.out.zbb @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.gorc <= i0_dec.io.out.gorc @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.grev <= i0_dec.io.out.grev @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.ror <= i0_dec.io.out.ror @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.rol <= i0_dec.io.out.rol @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.packh <= i0_dec.io.out.packh @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.packu <= i0_dec.io.out.packu @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.pack <= i0_dec.io.out.pack @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.max <= i0_dec.io.out.max @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.min <= i0_dec.io.out.min @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sro <= i0_dec.io.out.sro @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.slo <= i0_dec.io.out.slo @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sext_h <= i0_dec.io.out.sext_h @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.sext_b <= i0_dec.io.out.sext_b @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.pcnt <= i0_dec.io.out.pcnt @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.ctz <= i0_dec.io.out.ctz @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
i0_dp_raw.clz <= i0_dec.io.out.clz @[dec_decode_ctl.scala 442:12]
|
|
|
|
|
reg _T_366 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 444:45]
|
|
|
|
|
_T_366 <= io.lsu_idle_any @[dec_decode_ctl.scala 444:45]
|
|
|
|
|
lsu_idle <= _T_366 @[dec_decode_ctl.scala 444:11]
|
|
|
|
|
node _T_367 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 447:73]
|
|
|
|
|
node _T_368 = and(leak1_i1_stall, _T_367) @[dec_decode_ctl.scala 447:71]
|
|
|
|
|
node _T_369 = or(io.dec_tlu_flush_leak_one_r, _T_368) @[dec_decode_ctl.scala 447:53]
|
|
|
|
|
leak1_i1_stall_in <= _T_369 @[dec_decode_ctl.scala 447:21]
|
|
|
|
|
leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 448:14]
|
|
|
|
|
node _T_370 = and(io.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 449:45]
|
|
|
|
|
node _T_371 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 449:83]
|
|
|
|
|
node _T_372 = and(leak1_i0_stall, _T_371) @[dec_decode_ctl.scala 449:81]
|
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|
|
|
node _T_373 = or(_T_370, _T_372) @[dec_decode_ctl.scala 449:63]
|
|
|
|
|
leak1_i0_stall_in <= _T_373 @[dec_decode_ctl.scala 449:21]
|
|
|
|
|
node _T_374 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 453:29]
|
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|
|
|
node _T_375 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 453:36]
|
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|
|
|
node _T_376 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 453:46]
|
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|
|
|
node _T_377 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 453:53]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_378 = cat(_T_376, _T_377) @[Cat.scala 29:58]
|
|
|
|
|
node _T_379 = cat(_T_374, _T_375) @[Cat.scala 29:58]
|
|
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|
|
node i0_pcall_imm = cat(_T_379, _T_378) @[Cat.scala 29:58]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_380 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 454:46]
|
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|
|
|
node _T_381 = bits(_T_380, 0, 0) @[dec_decode_ctl.scala 454:51]
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|
|
node _T_382 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 454:71]
|
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|
|
node _T_383 = eq(_T_382, UInt<8>("h0ff")) @[dec_decode_ctl.scala 454:79]
|
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|
|
node _T_384 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 454:104]
|
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|
|
node _T_385 = eq(_T_384, UInt<8>("h00")) @[dec_decode_ctl.scala 454:112]
|
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|
|
node i0_pcall_12b_offset = mux(_T_381, _T_383, _T_385) @[dec_decode_ctl.scala 454:33]
|
|
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|
|
node _T_386 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 455:47]
|
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|
|
node _T_387 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 455:76]
|
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|
|
node _T_388 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 455:98]
|
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|
|
|
node _T_389 = or(_T_387, _T_388) @[dec_decode_ctl.scala 455:89]
|
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|
|
node i0_pcall_case = and(_T_386, _T_389) @[dec_decode_ctl.scala 455:65]
|
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|
|
node _T_390 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 456:47]
|
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|
|
|
node _T_391 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 456:76]
|
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|
|
|
node _T_392 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 456:98]
|
|
|
|
|
node _T_393 = or(_T_391, _T_392) @[dec_decode_ctl.scala 456:89]
|
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|
|
node _T_394 = eq(_T_393, UInt<1>("h00")) @[dec_decode_ctl.scala 456:67]
|
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|
|
|
node i0_pja_case = and(_T_390, _T_394) @[dec_decode_ctl.scala 456:65]
|
|
|
|
|
node _T_395 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 457:38]
|
|
|
|
|
i0_pcall_raw <= _T_395 @[dec_decode_ctl.scala 457:20]
|
|
|
|
|
node _T_396 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 458:38]
|
|
|
|
|
i0_pcall <= _T_396 @[dec_decode_ctl.scala 458:20]
|
|
|
|
|
node _T_397 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 459:38]
|
|
|
|
|
i0_pja_raw <= _T_397 @[dec_decode_ctl.scala 459:20]
|
|
|
|
|
node _T_398 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 460:38]
|
|
|
|
|
i0_pja <= _T_398 @[dec_decode_ctl.scala 460:20]
|
|
|
|
|
node _T_399 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 461:41]
|
|
|
|
|
node _T_400 = bits(_T_399, 0, 0) @[dec_decode_ctl.scala 461:55]
|
|
|
|
|
node _T_401 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 461:75]
|
|
|
|
|
node _T_402 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 461:90]
|
|
|
|
|
node _T_403 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 461:97]
|
|
|
|
|
node _T_404 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 461:103]
|
|
|
|
|
node _T_405 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 461:113]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_406 = cat(_T_404, _T_405) @[Cat.scala 29:58]
|
|
|
|
|
node _T_407 = cat(_T_402, _T_403) @[Cat.scala 29:58]
|
|
|
|
|
node _T_408 = cat(_T_407, _T_406) @[Cat.scala 29:58]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_409 = mux(_T_400, _T_401, _T_408) @[dec_decode_ctl.scala 461:26]
|
|
|
|
|
i0_br_offset <= _T_409 @[dec_decode_ctl.scala 461:20]
|
|
|
|
|
node _T_410 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 463:37]
|
|
|
|
|
node _T_411 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 463:65]
|
|
|
|
|
node _T_412 = and(_T_410, _T_411) @[dec_decode_ctl.scala 463:55]
|
|
|
|
|
node _T_413 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 463:89]
|
|
|
|
|
node _T_414 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 463:111]
|
|
|
|
|
node _T_415 = or(_T_413, _T_414) @[dec_decode_ctl.scala 463:101]
|
|
|
|
|
node i0_pret_case = and(_T_412, _T_415) @[dec_decode_ctl.scala 463:79]
|
|
|
|
|
node _T_416 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 464:32]
|
|
|
|
|
i0_pret_raw <= _T_416 @[dec_decode_ctl.scala 464:15]
|
|
|
|
|
node _T_417 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 465:32]
|
|
|
|
|
i0_pret <= _T_417 @[dec_decode_ctl.scala 465:15]
|
|
|
|
|
node _T_418 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 466:35]
|
|
|
|
|
node _T_419 = and(i0_dp.jal, _T_418) @[dec_decode_ctl.scala 466:32]
|
|
|
|
|
node _T_420 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 466:52]
|
|
|
|
|
node _T_421 = and(_T_419, _T_420) @[dec_decode_ctl.scala 466:50]
|
|
|
|
|
node _T_422 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 466:67]
|
|
|
|
|
node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 466:65]
|
|
|
|
|
i0_jal <= _T_423 @[dec_decode_ctl.scala 466:15]
|
|
|
|
|
io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 469:29]
|
|
|
|
|
io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 470:34]
|
|
|
|
|
io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 471:34]
|
|
|
|
|
io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 473:32]
|
|
|
|
|
io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 474:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 475:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 476:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.bext <= i0_dp.bext @[dec_decode_ctl.scala 477:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.bdep <= i0_dp.bdep @[dec_decode_ctl.scala 478:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.clmul <= i0_dp.clmul @[dec_decode_ctl.scala 479:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.clmulh <= i0_dp.clmulh @[dec_decode_ctl.scala 480:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.clmulr <= i0_dp.clmulr @[dec_decode_ctl.scala 481:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.grev <= i0_dp.grev @[dec_decode_ctl.scala 482:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.gorc <= i0_dp.gorc @[dec_decode_ctl.scala 483:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.shfl <= i0_dp.shfl @[dec_decode_ctl.scala 484:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.unshfl <= i0_dp.unshfl @[dec_decode_ctl.scala 485:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32_b <= i0_dp.crc32_b @[dec_decode_ctl.scala 486:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32_h <= i0_dp.crc32_h @[dec_decode_ctl.scala 487:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32_w <= i0_dp.crc32_w @[dec_decode_ctl.scala 488:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32c_b <= i0_dp.crc32c_b @[dec_decode_ctl.scala 489:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32c_h <= i0_dp.crc32c_h @[dec_decode_ctl.scala 490:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.crc32c_w <= i0_dp.crc32c_w @[dec_decode_ctl.scala 491:37]
|
|
|
|
|
io.decode_exu.mul_p.bits.bfp <= i0_dp.bfp @[dec_decode_ctl.scala 492:37]
|
|
|
|
|
wire _T_424 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.stack <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
_T_424.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 495:27]
|
|
|
|
|
io.lsu_p.bits.store_data_bypass_m <= _T_424.bits.store_data_bypass_m @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.load_ldst_bypass_d <= _T_424.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.store_data_bypass_d <= _T_424.bits.store_data_bypass_d @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.dma <= _T_424.bits.dma @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.unsign <= _T_424.bits.unsign @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.store <= _T_424.bits.store @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.load <= _T_424.bits.load @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.dword <= _T_424.bits.dword @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.word <= _T_424.bits.word @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.half <= _T_424.bits.half @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.by <= _T_424.bits.by @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.stack <= _T_424.bits.stack @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.bits.fast_int <= _T_424.bits.fast_int @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
io.lsu_p.valid <= _T_424.valid @[dec_decode_ctl.scala 495:12]
|
|
|
|
|
when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 496:40]
|
|
|
|
|
io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 497:29]
|
|
|
|
|
io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 498:29]
|
|
|
|
|
io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 499:29]
|
|
|
|
|
io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 500:24]
|
|
|
|
|
skip @[dec_decode_ctl.scala 496:40]
|
|
|
|
|
else : @[dec_decode_ctl.scala 503:15]
|
|
|
|
|
io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 504:35]
|
|
|
|
|
io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 505:40]
|
|
|
|
|
io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 506:40]
|
|
|
|
|
io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 507:40]
|
|
|
|
|
io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 508:40]
|
|
|
|
|
io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 509:40]
|
|
|
|
|
node _T_425 = eq(i0r.rs1, UInt<5>("h02")) @[dec_decode_ctl.scala 510:41]
|
|
|
|
|
io.lsu_p.bits.stack <= _T_425 @[dec_decode_ctl.scala 510:29]
|
|
|
|
|
io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 511:40]
|
|
|
|
|
io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 512:40]
|
|
|
|
|
io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 513:40]
|
|
|
|
|
io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 514:40]
|
|
|
|
|
skip @[dec_decode_ctl.scala 503:15]
|
|
|
|
|
node _T_426 = and(i0_dp.csr_read, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 518:47]
|
|
|
|
|
io.dec_alu.dec_csr_ren_d <= _T_426 @[dec_decode_ctl.scala 518:29]
|
|
|
|
|
node _T_427 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 519:56]
|
|
|
|
|
node _T_428 = and(i0_dp.csr_read, _T_427) @[dec_decode_ctl.scala 519:36]
|
|
|
|
|
csr_read <= _T_428 @[dec_decode_ctl.scala 519:18]
|
|
|
|
|
node _T_429 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 521:42]
|
|
|
|
|
node i0_csr_write = and(i0_dp.csr_write, _T_429) @[dec_decode_ctl.scala 521:40]
|
|
|
|
|
node _T_430 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 522:61]
|
|
|
|
|
node csr_clr_d = and(i0_dp.csr_clr, _T_430) @[dec_decode_ctl.scala 522:41]
|
|
|
|
|
node _T_431 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 523:59]
|
|
|
|
|
node csr_set_d = and(i0_dp.csr_set, _T_431) @[dec_decode_ctl.scala 523:39]
|
|
|
|
|
node _T_432 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 524:59]
|
|
|
|
|
node csr_write_d = and(i0_csr_write, _T_432) @[dec_decode_ctl.scala 524:39]
|
|
|
|
|
node _T_433 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 526:41]
|
|
|
|
|
node _T_434 = and(i0_csr_write, _T_433) @[dec_decode_ctl.scala 526:39]
|
|
|
|
|
i0_csr_write_only_d <= _T_434 @[dec_decode_ctl.scala 526:23]
|
|
|
|
|
node _T_435 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 527:42]
|
|
|
|
|
node _T_436 = or(_T_435, i0_csr_write) @[dec_decode_ctl.scala 527:58]
|
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|
node _T_437 = and(_T_436, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 527:74]
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|
io.dec_csr_wen_unq_d <= _T_437 @[dec_decode_ctl.scala 527:24]
|
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|
node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 529:34]
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node _T_438 = and(any_csr_d, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 530:37]
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|
io.dec_csr_any_unq_d <= _T_438 @[dec_decode_ctl.scala 530:24]
|
2021-01-27 14:46:11 +08:00
|
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|
node _T_439 = bits(io.dec_csr_any_unq_d, 0, 0) @[Bitwise.scala 72:15]
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|
node _T_440 = mux(_T_439, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
|
2021-01-27 21:01:24 +08:00
|
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|
node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 531:62]
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|
node _T_442 = and(_T_440, _T_441) @[dec_decode_ctl.scala 531:58]
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|
io.dec_csr_rdaddr_d <= _T_442 @[dec_decode_ctl.scala 531:24]
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node _T_443 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 532:53]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_444 = bits(_T_443, 0, 0) @[Bitwise.scala 72:15]
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|
node _T_445 = mux(_T_444, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
|
2021-01-27 21:01:24 +08:00
|
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|
node _T_446 = and(_T_445, r_d.bits.csrwaddr) @[dec_decode_ctl.scala 532:67]
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io.dec_csr_wraddr_r <= _T_446 @[dec_decode_ctl.scala 532:24]
|
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node _T_447 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 536:39]
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node _T_448 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 536:53]
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node _T_449 = and(_T_447, _T_448) @[dec_decode_ctl.scala 536:51]
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|
|
io.dec_csr_wen_r <= _T_449 @[dec_decode_ctl.scala 536:20]
|
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node _T_450 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 539:50]
|
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|
node _T_451 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 539:85]
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node _T_452 = or(_T_450, _T_451) @[dec_decode_ctl.scala 539:64]
|
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node _T_453 = and(_T_452, r_d.bits.csrwen) @[dec_decode_ctl.scala 539:100]
|
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node _T_454 = and(_T_453, r_d.valid) @[dec_decode_ctl.scala 539:118]
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node _T_455 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 539:132]
|
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|
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node _T_456 = and(_T_454, _T_455) @[dec_decode_ctl.scala 539:130]
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|
|
io.dec_csr_stall_int_ff <= _T_456 @[dec_decode_ctl.scala 539:27]
|
|
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|
|
reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 541:52]
|
|
|
|
|
csr_read_x <= csr_read @[dec_decode_ctl.scala 541:52]
|
|
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|
reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 542:51]
|
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|
|
csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 542:51]
|
|
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|
|
reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 543:51]
|
|
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|
|
csr_set_x <= csr_set_d @[dec_decode_ctl.scala 543:51]
|
|
|
|
|
reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 544:53]
|
|
|
|
|
csr_write_x <= csr_write_d @[dec_decode_ctl.scala 544:53]
|
|
|
|
|
reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 545:51]
|
|
|
|
|
csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 545:51]
|
|
|
|
|
node _T_457 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 548:27]
|
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|
|
node _T_458 = bits(any_csr_d, 0, 0) @[dec_decode_ctl.scala 548:60]
|
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|
|
node _T_459 = and(i0_x_data_en, _T_458) @[dec_decode_ctl.scala 548:48]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_460 = bits(_T_459, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
inst rvclkhdr of rvclkhdr @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr.clock <= clock
|
|
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|
|
rvclkhdr.reset <= reset
|
|
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|
|
rvclkhdr.io.clk <= clock @[lib.scala 406:18]
|
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|
|
rvclkhdr.io.en <= _T_460 @[lib.scala 407:17]
|
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|
|
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
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|
|
reg csrimm_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
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|
|
when _T_460 : @[Reg.scala 28:19]
|
|
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|
|
csrimm_x <= _T_457 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_461 = bits(any_csr_d, 0, 0) @[dec_decode_ctl.scala 549:74]
|
|
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|
|
node _T_462 = and(i0_x_data_en, _T_461) @[dec_decode_ctl.scala 549:62]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_463 = bits(_T_462, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_1.clock <= clock
|
|
|
|
|
rvclkhdr_1.reset <= reset
|
|
|
|
|
rvclkhdr_1.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_1.io.en <= _T_463 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg csr_rddata_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_463 : @[Reg.scala 28:19]
|
|
|
|
|
csr_rddata_x <= io.dec_csr_rddata_d @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_464 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 552:15]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire _T_465 : UInt<1>[27] @[lib.scala 12:48]
|
|
|
|
|
_T_465[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[10] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[11] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[12] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[13] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[14] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[15] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[16] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[17] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[18] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[19] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[20] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[21] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[22] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[23] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[24] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[25] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_465[26] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
node _T_466 = cat(_T_465[0], _T_465[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_467 = cat(_T_466, _T_465[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_468 = cat(_T_467, _T_465[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_469 = cat(_T_468, _T_465[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_470 = cat(_T_469, _T_465[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_471 = cat(_T_470, _T_465[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_472 = cat(_T_471, _T_465[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_473 = cat(_T_472, _T_465[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_474 = cat(_T_473, _T_465[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_475 = cat(_T_474, _T_465[10]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_476 = cat(_T_475, _T_465[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_477 = cat(_T_476, _T_465[12]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_478 = cat(_T_477, _T_465[13]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_479 = cat(_T_478, _T_465[14]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_480 = cat(_T_479, _T_465[15]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_481 = cat(_T_480, _T_465[16]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_482 = cat(_T_481, _T_465[17]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_483 = cat(_T_482, _T_465[18]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_484 = cat(_T_483, _T_465[19]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_485 = cat(_T_484, _T_465[20]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_486 = cat(_T_485, _T_465[21]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_487 = cat(_T_486, _T_465[22]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_488 = cat(_T_487, _T_465[23]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_489 = cat(_T_488, _T_465[24]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_490 = cat(_T_489, _T_465[25]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_491 = cat(_T_490, _T_465[26]) @[Cat.scala 29:58]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_492 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 552:53]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_493 = cat(_T_491, _T_492) @[Cat.scala 29:58]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_494 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 553:16]
|
|
|
|
|
node _T_495 = eq(_T_494, UInt<1>("h00")) @[dec_decode_ctl.scala 553:5]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_496 = mux(_T_464, _T_493, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_497 = mux(_T_495, io.decode_exu.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_498 = or(_T_496, _T_497) @[Mux.scala 27:72]
|
|
|
|
|
wire csr_mask_x : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
csr_mask_x <= _T_498 @[Mux.scala 27:72]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_499 = not(csr_mask_x) @[dec_decode_ctl.scala 556:38]
|
|
|
|
|
node _T_500 = and(csr_rddata_x, _T_499) @[dec_decode_ctl.scala 556:35]
|
|
|
|
|
node _T_501 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 557:35]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_502 = mux(csr_clr_x, _T_500, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_503 = mux(csr_set_x, _T_501, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_504 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_505 = or(_T_502, _T_503) @[Mux.scala 27:72]
|
|
|
|
|
node _T_506 = or(_T_505, _T_504) @[Mux.scala 27:72]
|
|
|
|
|
wire write_csr_data_x : UInt @[Mux.scala 27:72]
|
|
|
|
|
write_csr_data_x <= _T_506 @[Mux.scala 27:72]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_507 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 560:49]
|
|
|
|
|
node _T_508 = and(io.dec_tlu_flush_lower_r, _T_507) @[dec_decode_ctl.scala 560:47]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_509 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_510 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 560:145]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_511 = cat(_T_509, _T_510) @[Cat.scala 29:58]
|
2021-01-27 21:01:24 +08:00
|
|
|
node _T_512 = eq(write_csr_data, _T_511) @[dec_decode_ctl.scala 560:109]
|
|
|
|
|
node _T_513 = and(pause_stall, _T_512) @[dec_decode_ctl.scala 560:91]
|
|
|
|
|
node clear_pause = or(_T_508, _T_513) @[dec_decode_ctl.scala 560:76]
|
|
|
|
|
node _T_514 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 561:44]
|
|
|
|
|
node _T_515 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 561:61]
|
|
|
|
|
node _T_516 = and(_T_514, _T_515) @[dec_decode_ctl.scala 561:59]
|
|
|
|
|
pause_state_in <= _T_516 @[dec_decode_ctl.scala 561:18]
|
|
|
|
|
io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 562:22]
|
|
|
|
|
node _T_517 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 564:44]
|
|
|
|
|
node _T_518 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 564:64]
|
|
|
|
|
node _T_519 = and(_T_517, _T_518) @[dec_decode_ctl.scala 564:61]
|
|
|
|
|
node _T_520 = and(pause_stall, _T_519) @[dec_decode_ctl.scala 564:41]
|
|
|
|
|
io.dec_pause_state_cg <= _T_520 @[dec_decode_ctl.scala 564:25]
|
|
|
|
|
node _T_521 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 567:59]
|
|
|
|
|
node _T_522 = tail(_T_521, 1) @[dec_decode_ctl.scala 567:59]
|
|
|
|
|
node _T_523 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 568:8]
|
|
|
|
|
node write_csr_data_in = mux(pause_stall, _T_522, _T_523) @[dec_decode_ctl.scala 567:30]
|
|
|
|
|
node _T_524 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 569:34]
|
|
|
|
|
node _T_525 = or(_T_524, csr_write_x) @[dec_decode_ctl.scala 569:46]
|
|
|
|
|
node _T_526 = and(_T_525, csr_read_x) @[dec_decode_ctl.scala 569:61]
|
|
|
|
|
node _T_527 = or(_T_526, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 569:75]
|
|
|
|
|
node csr_data_wen = or(_T_527, pause_stall) @[dec_decode_ctl.scala 569:99]
|
2021-01-27 14:46:11 +08:00
|
|
|
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_2.clock <= clock
|
|
|
|
|
rvclkhdr_2.reset <= reset
|
|
|
|
|
rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_2.io.en <= csr_data_wen @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_528 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when csr_data_wen : @[Reg.scala 28:19]
|
|
|
|
|
_T_528 <= write_csr_data_in @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-27 21:01:24 +08:00
|
|
|
write_csr_data <= _T_528 @[dec_decode_ctl.scala 570:18]
|
|
|
|
|
node _T_529 = and(r_d.bits.csrwonly, r_d.valid) @[dec_decode_ctl.scala 576:50]
|
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|
|
|
node _T_530 = bits(_T_529, 0, 0) @[dec_decode_ctl.scala 576:63]
|
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|
|
node _T_531 = mux(_T_530, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 576:30]
|
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|
|
|
io.dec_csr_wrdata_r <= _T_531 @[dec_decode_ctl.scala 576:24]
|
|
|
|
|
node _T_532 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 578:43]
|
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|
|
|
node prior_csr_write = or(_T_532, wbd.bits.csrwonly) @[dec_decode_ctl.scala 578:63]
|
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|
|
node _T_533 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 580:76]
|
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|
|
node debug_fence_i = and(io.dec_debug_fence_d, _T_533) @[dec_decode_ctl.scala 580:48]
|
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|
|
node _T_534 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 581:76]
|
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|
|
node debug_fence_raw = and(io.dec_debug_fence_d, _T_534) @[dec_decode_ctl.scala 581:48]
|
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|
|
node _T_535 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 582:40]
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|
|
|
debug_fence <= _T_535 @[dec_decode_ctl.scala 582:21]
|
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|
|
node _T_536 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 585:34]
|
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|
|
node _T_537 = or(_T_536, debug_fence_i) @[dec_decode_ctl.scala 585:57]
|
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|
|
node _T_538 = or(_T_537, debug_fence_raw) @[dec_decode_ctl.scala 585:73]
|
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|
|
|
node i0_presync = or(_T_538, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 585:91]
|
|
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|
|
node _T_539 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 588:36]
|
|
|
|
|
node _T_540 = or(_T_539, debug_fence_i) @[dec_decode_ctl.scala 588:60]
|
|
|
|
|
node _T_541 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 588:104]
|
|
|
|
|
node _T_542 = eq(_T_541, UInt<11>("h07c2")) @[dec_decode_ctl.scala 588:112]
|
|
|
|
|
node _T_543 = and(i0_csr_write_only_d, _T_542) @[dec_decode_ctl.scala 588:99]
|
|
|
|
|
node i0_postsync = or(_T_540, _T_543) @[dec_decode_ctl.scala 588:76]
|
2021-01-28 15:16:34 +08:00
|
|
|
wire bitmanip_legal : UInt<1>
|
|
|
|
|
bitmanip_legal <= UInt<1>("h00")
|
|
|
|
|
node _T_544 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 590:40]
|
|
|
|
|
node _T_545 = or(_T_544, io.dec_csr_legal_d) @[dec_decode_ctl.scala 590:51]
|
|
|
|
|
node _T_546 = and(i0_dp.legal, _T_545) @[dec_decode_ctl.scala 590:37]
|
|
|
|
|
node i0_legal = and(_T_546, bitmanip_legal) @[dec_decode_ctl.scala 590:73]
|
|
|
|
|
wire _T_547 : UInt<1>[16] @[lib.scala 12:48]
|
|
|
|
|
_T_547[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[10] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[11] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[12] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[13] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[14] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_547[15] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
node _T_548 = cat(_T_547[0], _T_547[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_549 = cat(_T_548, _T_547[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_550 = cat(_T_549, _T_547[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_551 = cat(_T_550, _T_547[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_552 = cat(_T_551, _T_547[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_553 = cat(_T_552, _T_547[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_554 = cat(_T_553, _T_547[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_555 = cat(_T_554, _T_547[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_556 = cat(_T_555, _T_547[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_557 = cat(_T_556, _T_547[10]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_558 = cat(_T_557, _T_547[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_559 = cat(_T_558, _T_547[12]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_560 = cat(_T_559, _T_547[13]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_561 = cat(_T_560, _T_547[14]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_562 = cat(_T_561, _T_547[15]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_563 = cat(_T_562, io.dec_aln.ifu_i0_cinst) @[Cat.scala 29:58]
|
|
|
|
|
node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_563) @[dec_decode_ctl.scala 591:27]
|
|
|
|
|
node _T_564 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 594:49]
|
|
|
|
|
node shift_illegal = and(io.dec_i0_decode_d, _T_564) @[dec_decode_ctl.scala 594:47]
|
|
|
|
|
node _T_565 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 595:44]
|
|
|
|
|
node illegal_inst_en = and(shift_illegal, _T_565) @[dec_decode_ctl.scala 595:42]
|
2021-01-27 14:46:11 +08:00
|
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_3.clock <= clock
|
|
|
|
|
rvclkhdr_3.reset <= reset
|
|
|
|
|
rvclkhdr_3.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_3.io.en <= illegal_inst_en @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
2021-01-28 15:16:34 +08:00
|
|
|
reg _T_566 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2021-01-27 14:46:11 +08:00
|
|
|
when illegal_inst_en : @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
_T_566 <= i0_inst_d @[Reg.scala 28:23]
|
2021-01-27 14:46:11 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
io.dec_illegal_inst <= _T_566 @[dec_decode_ctl.scala 596:23]
|
|
|
|
|
node _T_567 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 597:40]
|
|
|
|
|
node _T_568 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 597:61]
|
|
|
|
|
node _T_569 = and(_T_567, _T_568) @[dec_decode_ctl.scala 597:59]
|
|
|
|
|
illegal_lockout_in <= _T_569 @[dec_decode_ctl.scala 597:22]
|
|
|
|
|
node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 598:42]
|
|
|
|
|
node _T_570 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 600:40]
|
|
|
|
|
node _T_571 = or(_T_570, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 600:59]
|
|
|
|
|
node _T_572 = or(_T_571, pause_stall) @[dec_decode_ctl.scala 600:92]
|
|
|
|
|
node _T_573 = or(_T_572, leak1_i0_stall) @[dec_decode_ctl.scala 600:106]
|
|
|
|
|
node _T_574 = or(_T_573, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 601:20]
|
|
|
|
|
node _T_575 = or(_T_574, postsync_stall) @[dec_decode_ctl.scala 601:45]
|
|
|
|
|
node _T_576 = or(_T_575, presync_stall) @[dec_decode_ctl.scala 601:62]
|
|
|
|
|
node _T_577 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 602:19]
|
|
|
|
|
node _T_578 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 602:36]
|
|
|
|
|
node _T_579 = and(_T_577, _T_578) @[dec_decode_ctl.scala 602:34]
|
|
|
|
|
node _T_580 = or(_T_576, _T_579) @[dec_decode_ctl.scala 601:79]
|
|
|
|
|
node _T_581 = or(_T_580, i0_nonblock_load_stall) @[dec_decode_ctl.scala 602:47]
|
|
|
|
|
node _T_582 = or(_T_581, i0_load_block_d) @[dec_decode_ctl.scala 602:72]
|
|
|
|
|
node _T_583 = or(_T_582, i0_nonblock_div_stall) @[dec_decode_ctl.scala 603:21]
|
|
|
|
|
node i0_block_raw_d = or(_T_583, i0_div_prior_div_stall) @[dec_decode_ctl.scala 603:45]
|
|
|
|
|
node _T_584 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 605:65]
|
|
|
|
|
node i0_store_stall_d = and(i0_dp.store, _T_584) @[dec_decode_ctl.scala 605:39]
|
|
|
|
|
node _T_585 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 606:63]
|
|
|
|
|
node i0_load_stall_d = and(i0_dp.load, _T_585) @[dec_decode_ctl.scala 606:38]
|
|
|
|
|
node _T_586 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 607:38]
|
|
|
|
|
node i0_block_d = or(_T_586, i0_load_stall_d) @[dec_decode_ctl.scala 607:57]
|
|
|
|
|
node _T_587 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 611:46]
|
|
|
|
|
node _T_588 = and(io.dec_ib0_valid_d, _T_587) @[dec_decode_ctl.scala 611:44]
|
|
|
|
|
node _T_589 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 611:63]
|
|
|
|
|
node _T_590 = and(_T_588, _T_589) @[dec_decode_ctl.scala 611:61]
|
|
|
|
|
node _T_591 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 611:91]
|
|
|
|
|
node _T_592 = and(_T_590, _T_591) @[dec_decode_ctl.scala 611:89]
|
|
|
|
|
io.dec_i0_decode_d <= _T_592 @[dec_decode_ctl.scala 611:22]
|
|
|
|
|
node _T_593 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 612:46]
|
|
|
|
|
node _T_594 = and(io.dec_ib0_valid_d, _T_593) @[dec_decode_ctl.scala 612:44]
|
|
|
|
|
node _T_595 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 612:63]
|
|
|
|
|
node _T_596 = and(_T_594, _T_595) @[dec_decode_ctl.scala 612:61]
|
|
|
|
|
node _T_597 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 612:91]
|
|
|
|
|
node i0_exudecode_d = and(_T_596, _T_597) @[dec_decode_ctl.scala 612:89]
|
|
|
|
|
node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 613:46]
|
|
|
|
|
io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[dec_decode_ctl.scala 616:28]
|
|
|
|
|
node _T_598 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 617:51]
|
|
|
|
|
node _T_599 = and(io.dec_ib0_valid_d, _T_598) @[dec_decode_ctl.scala 617:49]
|
|
|
|
|
io.dec_pmu_decode_stall <= _T_599 @[dec_decode_ctl.scala 617:27]
|
|
|
|
|
node _T_600 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 618:47]
|
|
|
|
|
node _T_601 = and(_T_600, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 618:54]
|
|
|
|
|
io.dec_pmu_postsync_stall <= _T_601 @[dec_decode_ctl.scala 618:29]
|
|
|
|
|
node _T_602 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 619:46]
|
|
|
|
|
node _T_603 = and(_T_602, io.dec_ib0_valid_d) @[dec_decode_ctl.scala 619:53]
|
|
|
|
|
io.dec_pmu_presync_stall <= _T_603 @[dec_decode_ctl.scala 619:29]
|
|
|
|
|
node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 623:41]
|
|
|
|
|
node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 624:31]
|
|
|
|
|
node _T_604 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 626:37]
|
|
|
|
|
presync_stall <= _T_604 @[dec_decode_ctl.scala 626:22]
|
|
|
|
|
node _T_605 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 628:56]
|
|
|
|
|
node _T_606 = or(i0_postsync, _T_605) @[dec_decode_ctl.scala 628:54]
|
|
|
|
|
node _T_607 = and(io.dec_i0_decode_d, _T_606) @[dec_decode_ctl.scala 628:39]
|
|
|
|
|
node _T_608 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 628:88]
|
|
|
|
|
node _T_609 = or(_T_607, _T_608) @[dec_decode_ctl.scala 628:69]
|
|
|
|
|
ps_stall_in <= _T_609 @[dec_decode_ctl.scala 628:15]
|
|
|
|
|
node _T_610 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 630:58]
|
|
|
|
|
io.dec_alu.dec_i0_alu_decode_d <= _T_610 @[dec_decode_ctl.scala 630:34]
|
|
|
|
|
node _T_611 = or(i0_dp.condbr, i0_dp.jal) @[dec_decode_ctl.scala 631:53]
|
|
|
|
|
node _T_612 = or(_T_611, i0_br_error_all) @[dec_decode_ctl.scala 631:65]
|
|
|
|
|
io.decode_exu.dec_i0_branch_d <= _T_612 @[dec_decode_ctl.scala 631:37]
|
|
|
|
|
node _T_613 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 633:40]
|
|
|
|
|
lsu_decode_d <= _T_613 @[dec_decode_ctl.scala 633:16]
|
|
|
|
|
node _T_614 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 634:40]
|
|
|
|
|
mul_decode_d <= _T_614 @[dec_decode_ctl.scala 634:16]
|
|
|
|
|
node _T_615 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 635:40]
|
|
|
|
|
div_decode_d <= _T_615 @[dec_decode_ctl.scala 635:16]
|
|
|
|
|
io.decode_exu.dec_qual_lsu_d <= i0_dp.lsu @[dec_decode_ctl.scala 636:32]
|
|
|
|
|
node _T_616 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 637:45]
|
|
|
|
|
node _T_617 = and(r_d.valid, _T_616) @[dec_decode_ctl.scala 637:43]
|
|
|
|
|
io.dec_tlu_i0_valid_r <= _T_617 @[dec_decode_ctl.scala 637:29]
|
|
|
|
|
d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 640:26]
|
|
|
|
|
node _T_618 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 641:40]
|
|
|
|
|
d_t.icaf <= _T_618 @[dec_decode_ctl.scala 641:26]
|
|
|
|
|
node _T_619 = and(io.dec_i0_icaf_second_d, i0_legal_decode_d) @[dec_decode_ctl.scala 642:58]
|
|
|
|
|
d_t.icaf_second <= _T_619 @[dec_decode_ctl.scala 642:30]
|
|
|
|
|
d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 643:26]
|
|
|
|
|
node _T_620 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 645:44]
|
|
|
|
|
node _T_621 = and(_T_620, i0_legal_decode_d) @[dec_decode_ctl.scala 645:61]
|
|
|
|
|
d_t.fence_i <= _T_621 @[dec_decode_ctl.scala 645:26]
|
|
|
|
|
d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 648:26]
|
|
|
|
|
d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 649:26]
|
|
|
|
|
d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 650:26]
|
|
|
|
|
wire _T_622 : UInt<1>[4] @[lib.scala 12:48]
|
|
|
|
|
_T_622[0] <= io.dec_i0_decode_d @[lib.scala 12:48]
|
|
|
|
|
_T_622[1] <= io.dec_i0_decode_d @[lib.scala 12:48]
|
|
|
|
|
_T_622[2] <= io.dec_i0_decode_d @[lib.scala 12:48]
|
|
|
|
|
_T_622[3] <= io.dec_i0_decode_d @[lib.scala 12:48]
|
|
|
|
|
node _T_623 = cat(_T_622[0], _T_622[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_624 = cat(_T_623, _T_622[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_625 = cat(_T_624, _T_622[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_626 = and(io.dec_i0_trigger_match_d, _T_625) @[dec_decode_ctl.scala 652:56]
|
|
|
|
|
d_t.i0trigger <= _T_626 @[dec_decode_ctl.scala 652:26]
|
|
|
|
|
node _T_627 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 655:60]
|
|
|
|
|
wire _T_628 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37]
|
|
|
|
|
_T_628.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_628.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_628.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_628.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_628.i0trigger <= UInt<4>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_628.fence_i <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_628.icaf_type <= UInt<2>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_628.icaf_second <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_628.icaf <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_628.legal <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
reg _T_629 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, clock with : (reset => (reset, _T_628)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_627 : @[Reg.scala 28:19]
|
|
|
|
|
_T_629.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[Reg.scala 28:23]
|
|
|
|
|
_T_629.pmu_divide <= d_t.pmu_divide @[Reg.scala 28:23]
|
|
|
|
|
_T_629.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[Reg.scala 28:23]
|
|
|
|
|
_T_629.pmu_i0_itype <= d_t.pmu_i0_itype @[Reg.scala 28:23]
|
|
|
|
|
_T_629.i0trigger <= d_t.i0trigger @[Reg.scala 28:23]
|
|
|
|
|
_T_629.fence_i <= d_t.fence_i @[Reg.scala 28:23]
|
|
|
|
|
_T_629.icaf_type <= d_t.icaf_type @[Reg.scala 28:23]
|
|
|
|
|
_T_629.icaf_second <= d_t.icaf_second @[Reg.scala 28:23]
|
|
|
|
|
_T_629.icaf <= d_t.icaf @[Reg.scala 28:23]
|
|
|
|
|
_T_629.legal <= d_t.legal @[Reg.scala 28:23]
|
2021-01-27 14:46:11 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
x_t.pmu_lsu_misaligned <= _T_629.pmu_lsu_misaligned @[dec_decode_ctl.scala 655:7]
|
|
|
|
|
x_t.pmu_divide <= _T_629.pmu_divide @[dec_decode_ctl.scala 655:7]
|
|
|
|
|
x_t.pmu_i0_br_unpred <= _T_629.pmu_i0_br_unpred @[dec_decode_ctl.scala 655:7]
|
|
|
|
|
x_t.pmu_i0_itype <= _T_629.pmu_i0_itype @[dec_decode_ctl.scala 655:7]
|
|
|
|
|
x_t.i0trigger <= _T_629.i0trigger @[dec_decode_ctl.scala 655:7]
|
|
|
|
|
x_t.fence_i <= _T_629.fence_i @[dec_decode_ctl.scala 655:7]
|
|
|
|
|
x_t.icaf_type <= _T_629.icaf_type @[dec_decode_ctl.scala 655:7]
|
|
|
|
|
x_t.icaf_second <= _T_629.icaf_second @[dec_decode_ctl.scala 655:7]
|
|
|
|
|
x_t.icaf <= _T_629.icaf @[dec_decode_ctl.scala 655:7]
|
|
|
|
|
x_t.legal <= _T_629.legal @[dec_decode_ctl.scala 655:7]
|
|
|
|
|
x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 657:10]
|
|
|
|
|
x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 657:10]
|
|
|
|
|
x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 657:10]
|
|
|
|
|
x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 657:10]
|
|
|
|
|
x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 657:10]
|
|
|
|
|
x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 657:10]
|
|
|
|
|
x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 657:10]
|
|
|
|
|
x_t_in.icaf_second <= x_t.icaf_second @[dec_decode_ctl.scala 657:10]
|
|
|
|
|
x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 657:10]
|
|
|
|
|
x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 657:10]
|
|
|
|
|
wire _T_630 : UInt<1>[4] @[lib.scala 12:48]
|
|
|
|
|
_T_630[0] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48]
|
|
|
|
|
_T_630[1] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48]
|
|
|
|
|
_T_630[2] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48]
|
|
|
|
|
_T_630[3] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48]
|
|
|
|
|
node _T_631 = cat(_T_630[0], _T_630[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_632 = cat(_T_631, _T_630[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_633 = cat(_T_632, _T_630[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_634 = not(_T_633) @[dec_decode_ctl.scala 658:39]
|
|
|
|
|
node _T_635 = and(x_t.i0trigger, _T_634) @[dec_decode_ctl.scala 658:37]
|
|
|
|
|
x_t_in.i0trigger <= _T_635 @[dec_decode_ctl.scala 658:20]
|
|
|
|
|
node _T_636 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 660:63]
|
|
|
|
|
wire _T_637 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 630:37]
|
|
|
|
|
_T_637.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_637.pmu_divide <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_637.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_637.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_637.i0trigger <= UInt<4>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_637.fence_i <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_637.icaf_type <= UInt<2>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_637.icaf_second <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_637.icaf <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_637.legal <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
reg _T_638 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, clock with : (reset => (reset, _T_637)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_636 : @[Reg.scala 28:19]
|
|
|
|
|
_T_638.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[Reg.scala 28:23]
|
|
|
|
|
_T_638.pmu_divide <= x_t_in.pmu_divide @[Reg.scala 28:23]
|
|
|
|
|
_T_638.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[Reg.scala 28:23]
|
|
|
|
|
_T_638.pmu_i0_itype <= x_t_in.pmu_i0_itype @[Reg.scala 28:23]
|
|
|
|
|
_T_638.i0trigger <= x_t_in.i0trigger @[Reg.scala 28:23]
|
|
|
|
|
_T_638.fence_i <= x_t_in.fence_i @[Reg.scala 28:23]
|
|
|
|
|
_T_638.icaf_type <= x_t_in.icaf_type @[Reg.scala 28:23]
|
|
|
|
|
_T_638.icaf_second <= x_t_in.icaf_second @[Reg.scala 28:23]
|
|
|
|
|
_T_638.icaf <= x_t_in.icaf @[Reg.scala 28:23]
|
|
|
|
|
_T_638.legal <= x_t_in.legal @[Reg.scala 28:23]
|
2021-01-27 14:46:11 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
r_t.pmu_lsu_misaligned <= _T_638.pmu_lsu_misaligned @[dec_decode_ctl.scala 660:7]
|
|
|
|
|
r_t.pmu_divide <= _T_638.pmu_divide @[dec_decode_ctl.scala 660:7]
|
|
|
|
|
r_t.pmu_i0_br_unpred <= _T_638.pmu_i0_br_unpred @[dec_decode_ctl.scala 660:7]
|
|
|
|
|
r_t.pmu_i0_itype <= _T_638.pmu_i0_itype @[dec_decode_ctl.scala 660:7]
|
|
|
|
|
r_t.i0trigger <= _T_638.i0trigger @[dec_decode_ctl.scala 660:7]
|
|
|
|
|
r_t.fence_i <= _T_638.fence_i @[dec_decode_ctl.scala 660:7]
|
|
|
|
|
r_t.icaf_type <= _T_638.icaf_type @[dec_decode_ctl.scala 660:7]
|
|
|
|
|
r_t.icaf_second <= _T_638.icaf_second @[dec_decode_ctl.scala 660:7]
|
|
|
|
|
r_t.icaf <= _T_638.icaf @[dec_decode_ctl.scala 660:7]
|
|
|
|
|
r_t.legal <= _T_638.legal @[dec_decode_ctl.scala 660:7]
|
|
|
|
|
r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 662:10]
|
|
|
|
|
r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 662:10]
|
|
|
|
|
r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 662:10]
|
|
|
|
|
r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 662:10]
|
|
|
|
|
r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 662:10]
|
|
|
|
|
r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 662:10]
|
|
|
|
|
r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 662:10]
|
|
|
|
|
r_t_in.icaf_second <= r_t.icaf_second @[dec_decode_ctl.scala 662:10]
|
|
|
|
|
r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 662:10]
|
|
|
|
|
r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 662:10]
|
|
|
|
|
node _T_639 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 664:61]
|
|
|
|
|
wire _T_640 : UInt<1>[4] @[lib.scala 12:48]
|
|
|
|
|
_T_640[0] <= _T_639 @[lib.scala 12:48]
|
|
|
|
|
_T_640[1] <= _T_639 @[lib.scala 12:48]
|
|
|
|
|
_T_640[2] <= _T_639 @[lib.scala 12:48]
|
|
|
|
|
_T_640[3] <= _T_639 @[lib.scala 12:48]
|
|
|
|
|
node _T_641 = cat(_T_640[0], _T_640[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_642 = cat(_T_641, _T_640[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_643 = cat(_T_642, _T_640[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_644 = and(_T_643, lsu_trigger_match_r) @[dec_decode_ctl.scala 664:82]
|
|
|
|
|
node _T_645 = or(_T_644, r_t.i0trigger) @[dec_decode_ctl.scala 664:105]
|
|
|
|
|
r_t_in.i0trigger <= _T_645 @[dec_decode_ctl.scala 664:33]
|
|
|
|
|
r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 665:33]
|
|
|
|
|
node _T_646 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 667:35]
|
|
|
|
|
when _T_646 : @[dec_decode_ctl.scala 667:43]
|
|
|
|
|
wire _T_647 : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 667:66]
|
|
|
|
|
_T_647.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
|
|
|
|
|
_T_647.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
|
|
|
|
|
_T_647.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
|
|
|
|
|
_T_647.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 667:66]
|
|
|
|
|
_T_647.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 667:66]
|
|
|
|
|
_T_647.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
|
|
|
|
|
_T_647.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 667:66]
|
|
|
|
|
_T_647.icaf_second <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
|
|
|
|
|
_T_647.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
|
|
|
|
|
_T_647.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 667:66]
|
|
|
|
|
r_t_in.pmu_lsu_misaligned <= _T_647.pmu_lsu_misaligned @[dec_decode_ctl.scala 667:51]
|
|
|
|
|
r_t_in.pmu_divide <= _T_647.pmu_divide @[dec_decode_ctl.scala 667:51]
|
|
|
|
|
r_t_in.pmu_i0_br_unpred <= _T_647.pmu_i0_br_unpred @[dec_decode_ctl.scala 667:51]
|
|
|
|
|
r_t_in.pmu_i0_itype <= _T_647.pmu_i0_itype @[dec_decode_ctl.scala 667:51]
|
|
|
|
|
r_t_in.i0trigger <= _T_647.i0trigger @[dec_decode_ctl.scala 667:51]
|
|
|
|
|
r_t_in.fence_i <= _T_647.fence_i @[dec_decode_ctl.scala 667:51]
|
|
|
|
|
r_t_in.icaf_type <= _T_647.icaf_type @[dec_decode_ctl.scala 667:51]
|
|
|
|
|
r_t_in.icaf_second <= _T_647.icaf_second @[dec_decode_ctl.scala 667:51]
|
|
|
|
|
r_t_in.icaf <= _T_647.icaf @[dec_decode_ctl.scala 667:51]
|
|
|
|
|
r_t_in.legal <= _T_647.legal @[dec_decode_ctl.scala 667:51]
|
|
|
|
|
skip @[dec_decode_ctl.scala 667:43]
|
|
|
|
|
io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 669:39]
|
|
|
|
|
io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 669:39]
|
|
|
|
|
io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 669:39]
|
|
|
|
|
io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 669:39]
|
|
|
|
|
io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 669:39]
|
|
|
|
|
io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 669:39]
|
|
|
|
|
io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 669:39]
|
|
|
|
|
io.dec_tlu_packet_r.icaf_second <= r_t_in.icaf_second @[dec_decode_ctl.scala 669:39]
|
|
|
|
|
io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 669:39]
|
|
|
|
|
io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 669:39]
|
|
|
|
|
node _T_648 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 670:58]
|
|
|
|
|
io.dec_tlu_packet_r.pmu_divide <= _T_648 @[dec_decode_ctl.scala 670:39]
|
|
|
|
|
node _T_649 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 674:46]
|
|
|
|
|
node _T_650 = and(io.dec_ib0_valid_d, _T_649) @[dec_decode_ctl.scala 674:44]
|
|
|
|
|
node _T_651 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 674:60]
|
|
|
|
|
node _T_652 = and(_T_650, _T_651) @[dec_decode_ctl.scala 674:58]
|
|
|
|
|
node _T_653 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 674:88]
|
|
|
|
|
node _T_654 = and(_T_652, _T_653) @[dec_decode_ctl.scala 674:86]
|
|
|
|
|
io.dec_i0_decode_d <= _T_654 @[dec_decode_ctl.scala 674:22]
|
|
|
|
|
node _T_655 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 676:16]
|
|
|
|
|
i0r.rs1 <= _T_655 @[dec_decode_ctl.scala 676:11]
|
|
|
|
|
node _T_656 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 677:16]
|
|
|
|
|
i0r.rs2 <= _T_656 @[dec_decode_ctl.scala 677:11]
|
|
|
|
|
node _T_657 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 678:16]
|
|
|
|
|
i0r.rd <= _T_657 @[dec_decode_ctl.scala 678:11]
|
|
|
|
|
node _T_658 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 680:60]
|
|
|
|
|
node _T_659 = and(i0_dp.rs1, _T_658) @[dec_decode_ctl.scala 680:49]
|
|
|
|
|
io.decode_exu.dec_i0_rs1_en_d <= _T_659 @[dec_decode_ctl.scala 680:35]
|
|
|
|
|
node _T_660 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 681:60]
|
|
|
|
|
node _T_661 = and(i0_dp.rs2, _T_660) @[dec_decode_ctl.scala 681:49]
|
|
|
|
|
io.decode_exu.dec_i0_rs2_en_d <= _T_661 @[dec_decode_ctl.scala 681:35]
|
|
|
|
|
node _T_662 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 682:48]
|
|
|
|
|
node i0_rd_en_d = and(i0_dp.rd, _T_662) @[dec_decode_ctl.scala 682:37]
|
|
|
|
|
io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 683:19]
|
|
|
|
|
io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 684:19]
|
|
|
|
|
node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 686:38]
|
|
|
|
|
node _T_663 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 687:27]
|
|
|
|
|
node i0_uiimm20 = and(_T_663, i0_dp.imm20) @[dec_decode_ctl.scala 687:38]
|
|
|
|
|
node _T_664 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 694:38]
|
|
|
|
|
wire _T_665 : UInt<1>[20] @[lib.scala 12:48]
|
|
|
|
|
_T_665[0] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[1] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[2] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[3] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[4] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[5] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[6] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[7] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[8] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[9] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[10] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[11] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[12] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[13] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[14] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[15] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[16] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[17] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[18] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
_T_665[19] <= _T_664 @[lib.scala 12:48]
|
|
|
|
|
node _T_666 = cat(_T_665[0], _T_665[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_667 = cat(_T_666, _T_665[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_668 = cat(_T_667, _T_665[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_669 = cat(_T_668, _T_665[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_670 = cat(_T_669, _T_665[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_671 = cat(_T_670, _T_665[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_672 = cat(_T_671, _T_665[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_673 = cat(_T_672, _T_665[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_674 = cat(_T_673, _T_665[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_675 = cat(_T_674, _T_665[10]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_676 = cat(_T_675, _T_665[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_677 = cat(_T_676, _T_665[12]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_678 = cat(_T_677, _T_665[13]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_679 = cat(_T_678, _T_665[14]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_680 = cat(_T_679, _T_665[15]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_681 = cat(_T_680, _T_665[16]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_682 = cat(_T_681, _T_665[17]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_683 = cat(_T_682, _T_665[18]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_684 = cat(_T_683, _T_665[19]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_685 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 694:46]
|
|
|
|
|
node _T_686 = cat(_T_684, _T_685) @[Cat.scala 29:58]
|
|
|
|
|
wire _T_687 : UInt<1>[27] @[lib.scala 12:48]
|
|
|
|
|
_T_687[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[10] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[11] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[12] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[13] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[14] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[15] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[16] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[17] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[18] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[19] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[20] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[21] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[22] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[23] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[24] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[25] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_687[26] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
node _T_688 = cat(_T_687[0], _T_687[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_689 = cat(_T_688, _T_687[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_690 = cat(_T_689, _T_687[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_691 = cat(_T_690, _T_687[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_692 = cat(_T_691, _T_687[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_693 = cat(_T_692, _T_687[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_694 = cat(_T_693, _T_687[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_695 = cat(_T_694, _T_687[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_696 = cat(_T_695, _T_687[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_697 = cat(_T_696, _T_687[10]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_698 = cat(_T_697, _T_687[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_699 = cat(_T_698, _T_687[12]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_700 = cat(_T_699, _T_687[13]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_701 = cat(_T_700, _T_687[14]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_702 = cat(_T_701, _T_687[15]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_703 = cat(_T_702, _T_687[16]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_704 = cat(_T_703, _T_687[17]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_705 = cat(_T_704, _T_687[18]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_706 = cat(_T_705, _T_687[19]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_707 = cat(_T_706, _T_687[20]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_708 = cat(_T_707, _T_687[21]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_709 = cat(_T_708, _T_687[22]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_710 = cat(_T_709, _T_687[23]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_711 = cat(_T_710, _T_687[24]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_712 = cat(_T_711, _T_687[25]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_713 = cat(_T_712, _T_687[26]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_714 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 695:43]
|
|
|
|
|
node _T_715 = cat(_T_713, _T_714) @[Cat.scala 29:58]
|
|
|
|
|
node _T_716 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 696:38]
|
|
|
|
|
wire _T_717 : UInt<1>[12] @[lib.scala 12:48]
|
|
|
|
|
_T_717[0] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
_T_717[1] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
_T_717[2] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
_T_717[3] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
_T_717[4] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
_T_717[5] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
_T_717[6] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
_T_717[7] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
_T_717[8] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
_T_717[9] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
_T_717[10] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
_T_717[11] <= _T_716 @[lib.scala 12:48]
|
|
|
|
|
node _T_718 = cat(_T_717[0], _T_717[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_719 = cat(_T_718, _T_717[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_720 = cat(_T_719, _T_717[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_721 = cat(_T_720, _T_717[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_722 = cat(_T_721, _T_717[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_723 = cat(_T_722, _T_717[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_724 = cat(_T_723, _T_717[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_725 = cat(_T_724, _T_717[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_726 = cat(_T_725, _T_717[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_727 = cat(_T_726, _T_717[10]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_728 = cat(_T_727, _T_717[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_729 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 696:46]
|
|
|
|
|
node _T_730 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 696:56]
|
|
|
|
|
node _T_731 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 696:63]
|
|
|
|
|
node _T_732 = cat(_T_731, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_733 = cat(_T_728, _T_729) @[Cat.scala 29:58]
|
|
|
|
|
node _T_734 = cat(_T_733, _T_730) @[Cat.scala 29:58]
|
|
|
|
|
node _T_735 = cat(_T_734, _T_732) @[Cat.scala 29:58]
|
|
|
|
|
node _T_736 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 697:30]
|
|
|
|
|
wire _T_737 : UInt<1>[12] @[lib.scala 12:48]
|
|
|
|
|
_T_737[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_737[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_737[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_737[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_737[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_737[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_737[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_737[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_737[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_737[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_737[10] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_737[11] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
node _T_738 = cat(_T_737[0], _T_737[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_739 = cat(_T_738, _T_737[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_740 = cat(_T_739, _T_737[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_741 = cat(_T_740, _T_737[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_742 = cat(_T_741, _T_737[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_743 = cat(_T_742, _T_737[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_744 = cat(_T_743, _T_737[7]) @[Cat.scala 29:58]
|
|
|
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|
node _T_745 = cat(_T_744, _T_737[8]) @[Cat.scala 29:58]
|
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|
|
|
node _T_746 = cat(_T_745, _T_737[9]) @[Cat.scala 29:58]
|
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|
|
|
node _T_747 = cat(_T_746, _T_737[10]) @[Cat.scala 29:58]
|
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|
|
node _T_748 = cat(_T_747, _T_737[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_749 = cat(_T_736, _T_748) @[Cat.scala 29:58]
|
|
|
|
|
node _T_750 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 698:26]
|
|
|
|
|
node _T_751 = bits(_T_750, 0, 0) @[dec_decode_ctl.scala 698:43]
|
|
|
|
|
wire _T_752 : UInt<1>[27] @[lib.scala 12:48]
|
|
|
|
|
_T_752[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
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|
|
_T_752[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[10] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[11] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[12] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[13] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[14] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[15] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[16] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[17] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[18] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[19] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[20] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[21] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[22] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[23] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[24] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[25] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_752[26] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
node _T_753 = cat(_T_752[0], _T_752[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_754 = cat(_T_753, _T_752[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_755 = cat(_T_754, _T_752[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_756 = cat(_T_755, _T_752[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_757 = cat(_T_756, _T_752[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_758 = cat(_T_757, _T_752[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_759 = cat(_T_758, _T_752[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_760 = cat(_T_759, _T_752[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_761 = cat(_T_760, _T_752[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_762 = cat(_T_761, _T_752[10]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_763 = cat(_T_762, _T_752[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_764 = cat(_T_763, _T_752[12]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_765 = cat(_T_764, _T_752[13]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_766 = cat(_T_765, _T_752[14]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_767 = cat(_T_766, _T_752[15]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_768 = cat(_T_767, _T_752[16]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_769 = cat(_T_768, _T_752[17]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_770 = cat(_T_769, _T_752[18]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_771 = cat(_T_770, _T_752[19]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_772 = cat(_T_771, _T_752[20]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_773 = cat(_T_772, _T_752[21]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_774 = cat(_T_773, _T_752[22]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_775 = cat(_T_774, _T_752[23]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_776 = cat(_T_775, _T_752[24]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_777 = cat(_T_776, _T_752[25]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_778 = cat(_T_777, _T_752[26]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_779 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 698:72]
|
|
|
|
|
node _T_780 = cat(_T_778, _T_779) @[Cat.scala 29:58]
|
|
|
|
|
node _T_781 = mux(i0_dp.imm12, _T_686, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_782 = mux(i0_dp.shimm5, _T_715, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_783 = mux(i0_jalimm20, _T_735, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_784 = mux(i0_uiimm20, _T_749, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_785 = mux(_T_751, _T_780, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_786 = or(_T_781, _T_782) @[Mux.scala 27:72]
|
2021-01-27 14:46:11 +08:00
|
|
|
node _T_787 = or(_T_786, _T_783) @[Mux.scala 27:72]
|
|
|
|
|
node _T_788 = or(_T_787, _T_784) @[Mux.scala 27:72]
|
2021-01-28 15:16:34 +08:00
|
|
|
node _T_789 = or(_T_788, _T_785) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_790 : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
_T_790 <= _T_789 @[Mux.scala 27:72]
|
|
|
|
|
io.decode_exu.dec_i0_immed_d <= _T_790 @[dec_decode_ctl.scala 693:32]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire bitmanip_zbb_legal : UInt<1>
|
|
|
|
|
bitmanip_zbb_legal <= UInt<1>("h00")
|
|
|
|
|
wire bitmanip_zbs_legal : UInt<1>
|
|
|
|
|
bitmanip_zbs_legal <= UInt<1>("h00")
|
|
|
|
|
wire bitmanip_zbe_legal : UInt<1>
|
|
|
|
|
bitmanip_zbe_legal <= UInt<1>("h00")
|
|
|
|
|
wire bitmanip_zbc_legal : UInt<1>
|
|
|
|
|
bitmanip_zbc_legal <= UInt<1>("h00")
|
|
|
|
|
wire bitmanip_zbp_legal : UInt<1>
|
|
|
|
|
bitmanip_zbp_legal <= UInt<1>("h00")
|
|
|
|
|
wire bitmanip_zbr_legal : UInt<1>
|
|
|
|
|
bitmanip_zbr_legal <= UInt<1>("h00")
|
|
|
|
|
wire bitmanip_zbf_legal : UInt<1>
|
|
|
|
|
bitmanip_zbf_legal <= UInt<1>("h00")
|
|
|
|
|
wire bitmanip_zba_legal : UInt<1>
|
|
|
|
|
bitmanip_zba_legal <= UInt<1>("h00")
|
|
|
|
|
wire bitmanip_zbb_zbp_legal : UInt<1>
|
|
|
|
|
bitmanip_zbb_zbp_legal <= UInt<1>("h00")
|
2021-01-28 15:16:34 +08:00
|
|
|
bitmanip_zbb_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 711:29]
|
|
|
|
|
bitmanip_zbs_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 716:29]
|
|
|
|
|
node _T_791 = eq(i0_dp.zbe, UInt<1>("h00")) @[dec_decode_ctl.scala 723:32]
|
|
|
|
|
bitmanip_zbe_legal <= _T_791 @[dec_decode_ctl.scala 723:29]
|
|
|
|
|
node _T_792 = eq(i0_dp.zbc, UInt<1>("h00")) @[dec_decode_ctl.scala 728:32]
|
|
|
|
|
bitmanip_zbc_legal <= _T_792 @[dec_decode_ctl.scala 728:29]
|
|
|
|
|
node _T_793 = eq(i0_dp.zbb, UInt<1>("h00")) @[dec_decode_ctl.scala 733:46]
|
|
|
|
|
node _T_794 = and(i0_dp.zbp, _T_793) @[dec_decode_ctl.scala 733:44]
|
|
|
|
|
node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_decode_ctl.scala 733:32]
|
|
|
|
|
bitmanip_zbp_legal <= _T_795 @[dec_decode_ctl.scala 733:29]
|
|
|
|
|
node _T_796 = eq(i0_dp.zbr, UInt<1>("h00")) @[dec_decode_ctl.scala 738:32]
|
|
|
|
|
bitmanip_zbr_legal <= _T_796 @[dec_decode_ctl.scala 738:29]
|
|
|
|
|
node _T_797 = eq(i0_dp.zbf, UInt<1>("h00")) @[dec_decode_ctl.scala 743:32]
|
|
|
|
|
bitmanip_zbf_legal <= _T_797 @[dec_decode_ctl.scala 743:29]
|
|
|
|
|
node _T_798 = eq(i0_dp.zba, UInt<1>("h00")) @[dec_decode_ctl.scala 748:32]
|
|
|
|
|
bitmanip_zba_legal <= _T_798 @[dec_decode_ctl.scala 748:29]
|
|
|
|
|
bitmanip_zbb_zbp_legal <= UInt<1>("h01") @[dec_decode_ctl.scala 751:29]
|
|
|
|
|
node _T_799 = and(bitmanip_zbb_legal, bitmanip_zbs_legal) @[dec_decode_ctl.scala 755:41]
|
|
|
|
|
node _T_800 = and(_T_799, bitmanip_zbe_legal) @[dec_decode_ctl.scala 755:62]
|
|
|
|
|
node _T_801 = and(_T_800, bitmanip_zbc_legal) @[dec_decode_ctl.scala 755:83]
|
|
|
|
|
node _T_802 = and(_T_801, bitmanip_zbp_legal) @[dec_decode_ctl.scala 755:104]
|
|
|
|
|
node _T_803 = and(_T_802, bitmanip_zbr_legal) @[dec_decode_ctl.scala 755:125]
|
|
|
|
|
node _T_804 = and(_T_803, bitmanip_zbf_legal) @[dec_decode_ctl.scala 755:146]
|
|
|
|
|
node _T_805 = and(_T_804, bitmanip_zba_legal) @[dec_decode_ctl.scala 755:167]
|
|
|
|
|
node _T_806 = and(_T_805, bitmanip_zbb_zbp_legal) @[dec_decode_ctl.scala 755:188]
|
|
|
|
|
bitmanip_legal <= _T_806 @[dec_decode_ctl.scala 755:18]
|
|
|
|
|
node _T_807 = and(io.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 756:46]
|
|
|
|
|
i0_legal_decode_d <= _T_807 @[dec_decode_ctl.scala 756:24]
|
|
|
|
|
node _T_808 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 758:44]
|
|
|
|
|
i0_d_c.mul <= _T_808 @[dec_decode_ctl.scala 758:29]
|
|
|
|
|
node _T_809 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 759:44]
|
|
|
|
|
i0_d_c.load <= _T_809 @[dec_decode_ctl.scala 759:29]
|
|
|
|
|
node _T_810 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 760:44]
|
|
|
|
|
i0_d_c.alu <= _T_810 @[dec_decode_ctl.scala 760:29]
|
|
|
|
|
wire _T_811 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 762:70]
|
|
|
|
|
_T_811.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70]
|
|
|
|
|
_T_811.load <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70]
|
|
|
|
|
_T_811.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 762:70]
|
|
|
|
|
node _T_812 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 762:92]
|
|
|
|
|
reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_811)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_812 : @[Reg.scala 28:19]
|
2021-01-27 14:46:11 +08:00
|
|
|
i0_x_c.alu <= i0_d_c.alu @[Reg.scala 28:23]
|
|
|
|
|
i0_x_c.load <= i0_d_c.load @[Reg.scala 28:23]
|
|
|
|
|
i0_x_c.mul <= i0_d_c.mul @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
wire _T_813 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 763:70]
|
|
|
|
|
_T_813.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70]
|
|
|
|
|
_T_813.load <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70]
|
|
|
|
|
_T_813.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 763:70]
|
|
|
|
|
node _T_814 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 763:92]
|
|
|
|
|
reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_813)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_814 : @[Reg.scala 28:19]
|
2021-01-27 14:46:11 +08:00
|
|
|
i0_r_c.alu <= i0_x_c.alu @[Reg.scala 28:23]
|
|
|
|
|
i0_r_c.load <= i0_x_c.load @[Reg.scala 28:23]
|
|
|
|
|
i0_r_c.mul <= i0_x_c.mul @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
node _T_815 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 764:83]
|
|
|
|
|
reg _T_816 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 764:72]
|
|
|
|
|
_T_816 <= _T_815 @[dec_decode_ctl.scala 764:72]
|
|
|
|
|
node _T_817 = cat(io.dec_i0_decode_d, _T_816) @[Cat.scala 29:58]
|
|
|
|
|
i0_pipe_en <= _T_817 @[dec_decode_ctl.scala 764:14]
|
|
|
|
|
node _T_818 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 766:43]
|
|
|
|
|
node _T_819 = orr(_T_818) @[dec_decode_ctl.scala 766:49]
|
|
|
|
|
node _T_820 = or(_T_819, io.clk_override) @[dec_decode_ctl.scala 766:53]
|
|
|
|
|
i0_x_ctl_en <= _T_820 @[dec_decode_ctl.scala 766:29]
|
|
|
|
|
node _T_821 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 767:43]
|
|
|
|
|
node _T_822 = orr(_T_821) @[dec_decode_ctl.scala 767:49]
|
|
|
|
|
node _T_823 = or(_T_822, io.clk_override) @[dec_decode_ctl.scala 767:53]
|
|
|
|
|
i0_r_ctl_en <= _T_823 @[dec_decode_ctl.scala 767:29]
|
|
|
|
|
node _T_824 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 768:43]
|
|
|
|
|
node _T_825 = orr(_T_824) @[dec_decode_ctl.scala 768:49]
|
|
|
|
|
node _T_826 = or(_T_825, io.clk_override) @[dec_decode_ctl.scala 768:53]
|
|
|
|
|
i0_wb_ctl_en <= _T_826 @[dec_decode_ctl.scala 768:29]
|
|
|
|
|
node _T_827 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 769:44]
|
|
|
|
|
node _T_828 = or(_T_827, io.clk_override) @[dec_decode_ctl.scala 769:50]
|
|
|
|
|
i0_x_data_en <= _T_828 @[dec_decode_ctl.scala 769:29]
|
|
|
|
|
node _T_829 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 770:44]
|
|
|
|
|
node _T_830 = or(_T_829, io.clk_override) @[dec_decode_ctl.scala 770:50]
|
|
|
|
|
i0_r_data_en <= _T_830 @[dec_decode_ctl.scala 770:29]
|
|
|
|
|
node _T_831 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 771:44]
|
|
|
|
|
node _T_832 = or(_T_831, io.clk_override) @[dec_decode_ctl.scala 771:50]
|
|
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|
|
i0_wb_data_en <= _T_832 @[dec_decode_ctl.scala 771:29]
|
|
|
|
|
node _T_833 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58]
|
|
|
|
|
io.decode_exu.dec_data_en <= _T_833 @[dec_decode_ctl.scala 773:38]
|
|
|
|
|
node _T_834 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58]
|
|
|
|
|
io.decode_exu.dec_ctl_en <= _T_834 @[dec_decode_ctl.scala 774:38]
|
|
|
|
|
d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 776:34]
|
|
|
|
|
node _T_835 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 777:50]
|
|
|
|
|
d_d.bits.i0v <= _T_835 @[dec_decode_ctl.scala 777:34]
|
|
|
|
|
d_d.valid <= io.dec_i0_decode_d @[dec_decode_ctl.scala 778:35]
|
|
|
|
|
node _T_836 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 780:50]
|
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|
|
|
d_d.bits.i0load <= _T_836 @[dec_decode_ctl.scala 780:34]
|
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|
|
node _T_837 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 781:50]
|
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|
|
d_d.bits.i0store <= _T_837 @[dec_decode_ctl.scala 781:34]
|
|
|
|
|
node _T_838 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 782:50]
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|
|
d_d.bits.i0div <= _T_838 @[dec_decode_ctl.scala 782:34]
|
|
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|
|
node _T_839 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 784:61]
|
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|
|
d_d.bits.csrwen <= _T_839 @[dec_decode_ctl.scala 784:34]
|
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|
|
node _T_840 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[dec_decode_ctl.scala 785:58]
|
|
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|
|
d_d.bits.csrwonly <= _T_840 @[dec_decode_ctl.scala 785:34]
|
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|
|
node _T_841 = bits(d_d.bits.csrwen, 0, 0) @[lib.scala 8:44]
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|
|
node _T_842 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 786:61]
|
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|
|
node _T_843 = mux(_T_841, _T_842, UInt<1>("h00")) @[dec_decode_ctl.scala 786:41]
|
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|
|
d_d.bits.csrwaddr <= _T_843 @[dec_decode_ctl.scala 786:34]
|
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|
|
node _T_844 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 788:63]
|
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|
|
wire _T_845 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37]
|
|
|
|
|
_T_845.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37]
|
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|
|
|
_T_845.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_845.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_845.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_845.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_845.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_845.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_845.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_845.valid <= UInt<1>("h00") @[lib.scala 630:37]
|
|
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|
|
reg _T_846 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_845)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_844 : @[Reg.scala 28:19]
|
|
|
|
|
_T_846.bits.csrwaddr <= d_d.bits.csrwaddr @[Reg.scala 28:23]
|
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|
|
|
_T_846.bits.csrwonly <= d_d.bits.csrwonly @[Reg.scala 28:23]
|
|
|
|
|
_T_846.bits.csrwen <= d_d.bits.csrwen @[Reg.scala 28:23]
|
|
|
|
|
_T_846.bits.i0v <= d_d.bits.i0v @[Reg.scala 28:23]
|
|
|
|
|
_T_846.bits.i0div <= d_d.bits.i0div @[Reg.scala 28:23]
|
|
|
|
|
_T_846.bits.i0store <= d_d.bits.i0store @[Reg.scala 28:23]
|
|
|
|
|
_T_846.bits.i0load <= d_d.bits.i0load @[Reg.scala 28:23]
|
|
|
|
|
_T_846.bits.i0rd <= d_d.bits.i0rd @[Reg.scala 28:23]
|
|
|
|
|
_T_846.valid <= d_d.valid @[Reg.scala 28:23]
|
2021-01-27 14:46:11 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
x_d.bits.csrwaddr <= _T_846.bits.csrwaddr @[dec_decode_ctl.scala 788:7]
|
|
|
|
|
x_d.bits.csrwonly <= _T_846.bits.csrwonly @[dec_decode_ctl.scala 788:7]
|
|
|
|
|
x_d.bits.csrwen <= _T_846.bits.csrwen @[dec_decode_ctl.scala 788:7]
|
|
|
|
|
x_d.bits.i0v <= _T_846.bits.i0v @[dec_decode_ctl.scala 788:7]
|
|
|
|
|
x_d.bits.i0div <= _T_846.bits.i0div @[dec_decode_ctl.scala 788:7]
|
|
|
|
|
x_d.bits.i0store <= _T_846.bits.i0store @[dec_decode_ctl.scala 788:7]
|
|
|
|
|
x_d.bits.i0load <= _T_846.bits.i0load @[dec_decode_ctl.scala 788:7]
|
|
|
|
|
x_d.bits.i0rd <= _T_846.bits.i0rd @[dec_decode_ctl.scala 788:7]
|
|
|
|
|
x_d.valid <= _T_846.valid @[dec_decode_ctl.scala 788:7]
|
|
|
|
|
wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 789:20]
|
|
|
|
|
x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 790:10]
|
|
|
|
|
x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 790:10]
|
|
|
|
|
x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 790:10]
|
|
|
|
|
x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 790:10]
|
|
|
|
|
x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 790:10]
|
|
|
|
|
x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 790:10]
|
|
|
|
|
x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 790:10]
|
|
|
|
|
x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 790:10]
|
|
|
|
|
x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 790:10]
|
|
|
|
|
node _T_847 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 791:49]
|
|
|
|
|
node _T_848 = and(x_d.bits.i0v, _T_847) @[dec_decode_ctl.scala 791:47]
|
|
|
|
|
node _T_849 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 791:78]
|
|
|
|
|
node _T_850 = and(_T_848, _T_849) @[dec_decode_ctl.scala 791:76]
|
|
|
|
|
x_d_in.bits.i0v <= _T_850 @[dec_decode_ctl.scala 791:27]
|
|
|
|
|
node _T_851 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 792:35]
|
|
|
|
|
node _T_852 = and(x_d.valid, _T_851) @[dec_decode_ctl.scala 792:33]
|
|
|
|
|
node _T_853 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 792:64]
|
|
|
|
|
node _T_854 = and(_T_852, _T_853) @[dec_decode_ctl.scala 792:62]
|
|
|
|
|
x_d_in.valid <= _T_854 @[dec_decode_ctl.scala 792:20]
|
|
|
|
|
node _T_855 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 794:65]
|
|
|
|
|
wire _T_856 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37]
|
|
|
|
|
_T_856.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_856.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_856.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_856.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_856.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_856.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_856.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_856.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_856.valid <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
reg _T_857 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_856)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_855 : @[Reg.scala 28:19]
|
|
|
|
|
_T_857.bits.csrwaddr <= x_d_in.bits.csrwaddr @[Reg.scala 28:23]
|
|
|
|
|
_T_857.bits.csrwonly <= x_d_in.bits.csrwonly @[Reg.scala 28:23]
|
|
|
|
|
_T_857.bits.csrwen <= x_d_in.bits.csrwen @[Reg.scala 28:23]
|
|
|
|
|
_T_857.bits.i0v <= x_d_in.bits.i0v @[Reg.scala 28:23]
|
|
|
|
|
_T_857.bits.i0div <= x_d_in.bits.i0div @[Reg.scala 28:23]
|
|
|
|
|
_T_857.bits.i0store <= x_d_in.bits.i0store @[Reg.scala 28:23]
|
|
|
|
|
_T_857.bits.i0load <= x_d_in.bits.i0load @[Reg.scala 28:23]
|
|
|
|
|
_T_857.bits.i0rd <= x_d_in.bits.i0rd @[Reg.scala 28:23]
|
|
|
|
|
_T_857.valid <= x_d_in.valid @[Reg.scala 28:23]
|
2021-01-27 14:46:11 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
r_d.bits.csrwaddr <= _T_857.bits.csrwaddr @[dec_decode_ctl.scala 794:7]
|
|
|
|
|
r_d.bits.csrwonly <= _T_857.bits.csrwonly @[dec_decode_ctl.scala 794:7]
|
|
|
|
|
r_d.bits.csrwen <= _T_857.bits.csrwen @[dec_decode_ctl.scala 794:7]
|
|
|
|
|
r_d.bits.i0v <= _T_857.bits.i0v @[dec_decode_ctl.scala 794:7]
|
|
|
|
|
r_d.bits.i0div <= _T_857.bits.i0div @[dec_decode_ctl.scala 794:7]
|
|
|
|
|
r_d.bits.i0store <= _T_857.bits.i0store @[dec_decode_ctl.scala 794:7]
|
|
|
|
|
r_d.bits.i0load <= _T_857.bits.i0load @[dec_decode_ctl.scala 794:7]
|
|
|
|
|
r_d.bits.i0rd <= _T_857.bits.i0rd @[dec_decode_ctl.scala 794:7]
|
|
|
|
|
r_d.valid <= _T_857.valid @[dec_decode_ctl.scala 794:7]
|
|
|
|
|
r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 795:10]
|
|
|
|
|
r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 795:10]
|
|
|
|
|
r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 795:10]
|
|
|
|
|
r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 795:10]
|
|
|
|
|
r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 795:10]
|
|
|
|
|
r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 795:10]
|
|
|
|
|
r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 795:10]
|
|
|
|
|
r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 795:10]
|
|
|
|
|
r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 795:10]
|
|
|
|
|
r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 796:22]
|
|
|
|
|
node _T_858 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 798:51]
|
|
|
|
|
node _T_859 = and(r_d.bits.i0v, _T_858) @[dec_decode_ctl.scala 798:49]
|
|
|
|
|
r_d_in.bits.i0v <= _T_859 @[dec_decode_ctl.scala 798:27]
|
|
|
|
|
node _T_860 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 799:37]
|
|
|
|
|
node _T_861 = and(r_d.valid, _T_860) @[dec_decode_ctl.scala 799:35]
|
|
|
|
|
r_d_in.valid <= _T_861 @[dec_decode_ctl.scala 799:20]
|
|
|
|
|
node _T_862 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 800:51]
|
|
|
|
|
node _T_863 = and(r_d.bits.i0load, _T_862) @[dec_decode_ctl.scala 800:49]
|
|
|
|
|
r_d_in.bits.i0load <= _T_863 @[dec_decode_ctl.scala 800:27]
|
|
|
|
|
node _T_864 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 801:51]
|
|
|
|
|
node _T_865 = and(r_d.bits.i0store, _T_864) @[dec_decode_ctl.scala 801:49]
|
|
|
|
|
r_d_in.bits.i0store <= _T_865 @[dec_decode_ctl.scala 801:27]
|
|
|
|
|
node _T_866 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 803:66]
|
|
|
|
|
wire _T_867 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 630:37]
|
|
|
|
|
_T_867.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_867.bits.csrwonly <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_867.bits.csrwen <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_867.bits.i0v <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_867.bits.i0div <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_867.bits.i0store <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_867.bits.i0load <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_867.bits.i0rd <= UInt<5>("h00") @[lib.scala 630:37]
|
|
|
|
|
_T_867.valid <= UInt<1>("h00") @[lib.scala 630:37]
|
|
|
|
|
reg _T_868 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, clock with : (reset => (reset, _T_867)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_866 : @[Reg.scala 28:19]
|
|
|
|
|
_T_868.bits.csrwaddr <= r_d_in.bits.csrwaddr @[Reg.scala 28:23]
|
|
|
|
|
_T_868.bits.csrwonly <= r_d_in.bits.csrwonly @[Reg.scala 28:23]
|
|
|
|
|
_T_868.bits.csrwen <= r_d_in.bits.csrwen @[Reg.scala 28:23]
|
|
|
|
|
_T_868.bits.i0v <= r_d_in.bits.i0v @[Reg.scala 28:23]
|
|
|
|
|
_T_868.bits.i0div <= r_d_in.bits.i0div @[Reg.scala 28:23]
|
|
|
|
|
_T_868.bits.i0store <= r_d_in.bits.i0store @[Reg.scala 28:23]
|
|
|
|
|
_T_868.bits.i0load <= r_d_in.bits.i0load @[Reg.scala 28:23]
|
|
|
|
|
_T_868.bits.i0rd <= r_d_in.bits.i0rd @[Reg.scala 28:23]
|
|
|
|
|
_T_868.valid <= r_d_in.valid @[Reg.scala 28:23]
|
2021-01-27 14:46:11 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
wbd.bits.csrwaddr <= _T_868.bits.csrwaddr @[dec_decode_ctl.scala 803:7]
|
|
|
|
|
wbd.bits.csrwonly <= _T_868.bits.csrwonly @[dec_decode_ctl.scala 803:7]
|
|
|
|
|
wbd.bits.csrwen <= _T_868.bits.csrwen @[dec_decode_ctl.scala 803:7]
|
|
|
|
|
wbd.bits.i0v <= _T_868.bits.i0v @[dec_decode_ctl.scala 803:7]
|
|
|
|
|
wbd.bits.i0div <= _T_868.bits.i0div @[dec_decode_ctl.scala 803:7]
|
|
|
|
|
wbd.bits.i0store <= _T_868.bits.i0store @[dec_decode_ctl.scala 803:7]
|
|
|
|
|
wbd.bits.i0load <= _T_868.bits.i0load @[dec_decode_ctl.scala 803:7]
|
|
|
|
|
wbd.bits.i0rd <= _T_868.bits.i0rd @[dec_decode_ctl.scala 803:7]
|
|
|
|
|
wbd.valid <= _T_868.valid @[dec_decode_ctl.scala 803:7]
|
|
|
|
|
io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 805:27]
|
|
|
|
|
node _T_869 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 806:47]
|
|
|
|
|
node _T_870 = and(r_d_in.bits.i0v, _T_869) @[dec_decode_ctl.scala 806:45]
|
|
|
|
|
i0_wen_r <= _T_870 @[dec_decode_ctl.scala 806:25]
|
|
|
|
|
node _T_871 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 807:49]
|
|
|
|
|
node _T_872 = and(i0_wen_r, _T_871) @[dec_decode_ctl.scala 807:47]
|
|
|
|
|
node _T_873 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 807:70]
|
|
|
|
|
node _T_874 = and(_T_872, _T_873) @[dec_decode_ctl.scala 807:68]
|
|
|
|
|
io.dec_i0_wen_r <= _T_874 @[dec_decode_ctl.scala 807:32]
|
|
|
|
|
io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 808:26]
|
|
|
|
|
node _T_875 = or(x_d.bits.i0v, x_d.bits.csrwen) @[dec_decode_ctl.scala 811:74]
|
|
|
|
|
node _T_876 = or(_T_875, debug_valid_x) @[dec_decode_ctl.scala 811:92]
|
|
|
|
|
node _T_877 = and(i0_r_data_en, _T_876) @[dec_decode_ctl.scala 811:58]
|
|
|
|
|
node _T_878 = eq(_T_877, UInt<1>("h01")) @[dec_decode_ctl.scala 811:110]
|
2021-01-27 14:46:11 +08:00
|
|
|
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_4.clock <= clock
|
|
|
|
|
rvclkhdr_4.reset <= reset
|
|
|
|
|
rvclkhdr_4.io.clk <= clock @[lib.scala 406:18]
|
2021-01-28 15:16:34 +08:00
|
|
|
rvclkhdr_4.io.en <= _T_878 @[lib.scala 407:17]
|
2021-01-27 14:46:11 +08:00
|
|
|
rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg i0_result_r_raw : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2021-01-28 15:16:34 +08:00
|
|
|
when _T_878 : @[Reg.scala 28:19]
|
2021-01-27 14:46:11 +08:00
|
|
|
i0_result_r_raw <= i0_result_x @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
node _T_879 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 817:47]
|
|
|
|
|
node _T_880 = bits(_T_879, 0, 0) @[dec_decode_ctl.scala 817:66]
|
|
|
|
|
node _T_881 = mux(_T_880, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 817:32]
|
|
|
|
|
i0_result_x <= _T_881 @[dec_decode_ctl.scala 817:26]
|
|
|
|
|
i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 818:26]
|
|
|
|
|
node _T_882 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 822:42]
|
|
|
|
|
node _T_883 = bits(_T_882, 0, 0) @[dec_decode_ctl.scala 822:61]
|
|
|
|
|
node _T_884 = mux(_T_883, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 822:27]
|
|
|
|
|
i0_result_corr_r <= _T_884 @[dec_decode_ctl.scala 822:21]
|
|
|
|
|
node _T_885 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 823:73]
|
|
|
|
|
node _T_886 = and(io.decode_exu.i0_ap.predict_nt, _T_885) @[dec_decode_ctl.scala 823:71]
|
|
|
|
|
node _T_887 = bits(_T_886, 0, 0) @[dec_decode_ctl.scala 823:85]
|
|
|
|
|
wire _T_888 : UInt<1>[10] @[lib.scala 12:48]
|
|
|
|
|
_T_888[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_888[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_888[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_888[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_888[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_888[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_888[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_888[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_888[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_888[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
node _T_889 = cat(_T_888[0], _T_888[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_890 = cat(_T_889, _T_888[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_891 = cat(_T_890, _T_888[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_892 = cat(_T_891, _T_888[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_893 = cat(_T_892, _T_888[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_894 = cat(_T_893, _T_888[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_895 = cat(_T_894, _T_888[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_896 = cat(_T_895, _T_888[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_897 = cat(_T_896, _T_888[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_898 = cat(_T_897, io.dec_i0_pc4_d) @[Cat.scala 29:58]
|
|
|
|
|
node _T_899 = cat(_T_898, i0_ap_pc2) @[Cat.scala 29:58]
|
|
|
|
|
node _T_900 = mux(_T_887, i0_br_offset, _T_899) @[dec_decode_ctl.scala 823:38]
|
|
|
|
|
io.dec_alu.dec_i0_br_immed_d <= _T_900 @[dec_decode_ctl.scala 823:32]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire last_br_immed_d : UInt<12>
|
|
|
|
|
last_br_immed_d <= UInt<1>("h00")
|
2021-01-28 15:16:34 +08:00
|
|
|
node _T_901 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 825:59]
|
|
|
|
|
wire _T_902 : UInt<1>[10] @[lib.scala 12:48]
|
|
|
|
|
_T_902[0] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_902[1] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_902[2] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_902[3] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_902[4] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_902[5] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_902[6] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_902[7] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_902[8] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
_T_902[9] <= UInt<1>("h00") @[lib.scala 12:48]
|
|
|
|
|
node _T_903 = cat(_T_902[0], _T_902[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_904 = cat(_T_903, _T_902[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_905 = cat(_T_904, _T_902[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_906 = cat(_T_905, _T_902[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_907 = cat(_T_906, _T_902[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_908 = cat(_T_907, _T_902[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_909 = cat(_T_908, _T_902[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_910 = cat(_T_909, _T_902[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_911 = cat(_T_910, _T_902[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_912 = cat(_T_911, io.dec_i0_pc4_d) @[Cat.scala 29:58]
|
|
|
|
|
node _T_913 = cat(_T_912, i0_ap_pc2) @[Cat.scala 29:58]
|
|
|
|
|
node _T_914 = mux(_T_901, _T_913, i0_br_offset) @[dec_decode_ctl.scala 825:25]
|
|
|
|
|
last_br_immed_d <= _T_914 @[dec_decode_ctl.scala 825:19]
|
2021-01-27 14:46:11 +08:00
|
|
|
wire last_br_immed_x : UInt<12>
|
|
|
|
|
last_br_immed_x <= UInt<1>("h00")
|
2021-01-28 15:16:34 +08:00
|
|
|
node _T_915 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 827:58]
|
2021-01-27 14:46:11 +08:00
|
|
|
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_5.clock <= clock
|
|
|
|
|
rvclkhdr_5.reset <= reset
|
|
|
|
|
rvclkhdr_5.io.clk <= clock @[lib.scala 406:18]
|
2021-01-28 15:16:34 +08:00
|
|
|
rvclkhdr_5.io.en <= _T_915 @[lib.scala 407:17]
|
2021-01-27 14:46:11 +08:00
|
|
|
rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
2021-01-28 15:16:34 +08:00
|
|
|
reg _T_916 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_915 : @[Reg.scala 28:19]
|
|
|
|
|
_T_916 <= last_br_immed_d @[Reg.scala 28:23]
|
2021-01-27 14:46:11 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
last_br_immed_x <= _T_916 @[dec_decode_ctl.scala 827:19]
|
|
|
|
|
node _T_917 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 831:45]
|
|
|
|
|
node _T_918 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 831:76]
|
|
|
|
|
node div_e1_to_r = or(_T_917, _T_918) @[dec_decode_ctl.scala 831:58]
|
|
|
|
|
node _T_919 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 833:48]
|
|
|
|
|
node _T_920 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 833:77]
|
|
|
|
|
node _T_921 = and(_T_919, _T_920) @[dec_decode_ctl.scala 833:60]
|
|
|
|
|
node _T_922 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 834:21]
|
|
|
|
|
node _T_923 = and(_T_922, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 834:33]
|
|
|
|
|
node _T_924 = or(_T_921, _T_923) @[dec_decode_ctl.scala 833:94]
|
|
|
|
|
node _T_925 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 835:21]
|
|
|
|
|
node _T_926 = and(_T_925, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 835:33]
|
|
|
|
|
node _T_927 = and(_T_926, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 835:60]
|
|
|
|
|
node div_flush = or(_T_924, _T_927) @[dec_decode_ctl.scala 834:62]
|
|
|
|
|
node _T_928 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 839:51]
|
|
|
|
|
node _T_929 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 840:26]
|
|
|
|
|
node _T_930 = and(io.dec_div_active, _T_929) @[dec_decode_ctl.scala 840:24]
|
|
|
|
|
node _T_931 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 840:56]
|
|
|
|
|
node _T_932 = and(_T_930, _T_931) @[dec_decode_ctl.scala 840:39]
|
|
|
|
|
node _T_933 = and(_T_932, i0_wen_r) @[dec_decode_ctl.scala 840:77]
|
|
|
|
|
node nonblock_div_cancel = or(_T_928, _T_933) @[dec_decode_ctl.scala 839:65]
|
|
|
|
|
node _T_934 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 842:61]
|
|
|
|
|
io.dec_div.dec_div_cancel <= _T_934 @[dec_decode_ctl.scala 842:37]
|
|
|
|
|
node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 843:55]
|
|
|
|
|
node _T_935 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 845:59]
|
|
|
|
|
node _T_936 = and(io.dec_div_active, _T_935) @[dec_decode_ctl.scala 845:57]
|
|
|
|
|
node _T_937 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 845:78]
|
|
|
|
|
node _T_938 = and(_T_936, _T_937) @[dec_decode_ctl.scala 845:76]
|
|
|
|
|
node _T_939 = or(i0_div_decode_d, _T_938) @[dec_decode_ctl.scala 845:36]
|
|
|
|
|
div_active_in <= _T_939 @[dec_decode_ctl.scala 845:17]
|
|
|
|
|
node _T_940 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 850:60]
|
|
|
|
|
node _T_941 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 850:99]
|
|
|
|
|
node _T_942 = and(_T_940, _T_941) @[dec_decode_ctl.scala 850:80]
|
|
|
|
|
node _T_943 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 851:36]
|
|
|
|
|
node _T_944 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 851:75]
|
|
|
|
|
node _T_945 = and(_T_943, _T_944) @[dec_decode_ctl.scala 851:56]
|
|
|
|
|
node _T_946 = or(_T_942, _T_945) @[dec_decode_ctl.scala 850:113]
|
|
|
|
|
i0_nonblock_div_stall <= _T_946 @[dec_decode_ctl.scala 850:26]
|
|
|
|
|
node trace_enable = not(io.dec_tlu_trace_disable) @[dec_decode_ctl.scala 858:22]
|
|
|
|
|
node _T_947 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 860:58]
|
2021-01-27 14:46:11 +08:00
|
|
|
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_6.clock <= clock
|
|
|
|
|
rvclkhdr_6.reset <= reset
|
|
|
|
|
rvclkhdr_6.io.clk <= clock @[lib.scala 406:18]
|
2021-01-28 15:16:34 +08:00
|
|
|
rvclkhdr_6.io.en <= _T_947 @[lib.scala 407:17]
|
2021-01-27 14:46:11 +08:00
|
|
|
rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
2021-01-28 15:16:34 +08:00
|
|
|
reg _T_948 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_947 : @[Reg.scala 28:19]
|
|
|
|
|
_T_948 <= i0r.rd @[Reg.scala 28:23]
|
2021-01-27 14:46:11 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
io.div_waddr_wb <= _T_948 @[dec_decode_ctl.scala 860:19]
|
|
|
|
|
node _T_949 = and(i0_x_data_en, trace_enable) @[dec_decode_ctl.scala 862:50]
|
|
|
|
|
node _T_950 = bits(_T_949, 0, 0) @[lib.scala 8:44]
|
2021-01-27 14:46:11 +08:00
|
|
|
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23]
|
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|
rvclkhdr_7.clock <= clock
|
|
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|
rvclkhdr_7.reset <= reset
|
|
|
|
|
rvclkhdr_7.io.clk <= clock @[lib.scala 406:18]
|
2021-01-28 15:16:34 +08:00
|
|
|
rvclkhdr_7.io.en <= _T_950 @[lib.scala 407:17]
|
2021-01-27 14:46:11 +08:00
|
|
|
rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
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|
|
reg i0_inst_x : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2021-01-28 15:16:34 +08:00
|
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|
when _T_950 : @[Reg.scala 28:19]
|
2021-01-27 14:46:11 +08:00
|
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|
i0_inst_x <= i0_inst_d @[Reg.scala 28:23]
|
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|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
node _T_951 = and(i0_r_data_en, trace_enable) @[dec_decode_ctl.scala 863:50]
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|
node _T_952 = bits(_T_951, 0, 0) @[lib.scala 8:44]
|
2021-01-27 14:46:11 +08:00
|
|
|
inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 404:23]
|
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|
rvclkhdr_8.clock <= clock
|
|
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|
|
rvclkhdr_8.reset <= reset
|
|
|
|
|
rvclkhdr_8.io.clk <= clock @[lib.scala 406:18]
|
2021-01-28 15:16:34 +08:00
|
|
|
rvclkhdr_8.io.en <= _T_952 @[lib.scala 407:17]
|
2021-01-27 14:46:11 +08:00
|
|
|
rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
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|
|
reg i0_inst_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2021-01-28 15:16:34 +08:00
|
|
|
when _T_952 : @[Reg.scala 28:19]
|
2021-01-27 14:46:11 +08:00
|
|
|
i0_inst_r <= i0_inst_x @[Reg.scala 28:23]
|
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|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
node _T_953 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 865:51]
|
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|
|
node _T_954 = bits(_T_953, 0, 0) @[lib.scala 8:44]
|
2021-01-27 14:46:11 +08:00
|
|
|
inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_9.clock <= clock
|
|
|
|
|
rvclkhdr_9.reset <= reset
|
|
|
|
|
rvclkhdr_9.io.clk <= clock @[lib.scala 406:18]
|
2021-01-28 15:16:34 +08:00
|
|
|
rvclkhdr_9.io.en <= _T_954 @[lib.scala 407:17]
|
2021-01-27 14:46:11 +08:00
|
|
|
rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg i0_inst_wb : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2021-01-28 15:16:34 +08:00
|
|
|
when _T_954 : @[Reg.scala 28:19]
|
2021-01-27 14:46:11 +08:00
|
|
|
i0_inst_wb <= i0_inst_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
node _T_955 = and(i0_wb_data_en, trace_enable) @[dec_decode_ctl.scala 866:54]
|
|
|
|
|
node _T_956 = bits(_T_955, 0, 0) @[lib.scala 8:44]
|
2021-01-27 14:46:11 +08:00
|
|
|
inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_10.clock <= clock
|
|
|
|
|
rvclkhdr_10.reset <= reset
|
|
|
|
|
rvclkhdr_10.io.clk <= clock @[lib.scala 406:18]
|
2021-01-28 15:16:34 +08:00
|
|
|
rvclkhdr_10.io.en <= _T_956 @[lib.scala 407:17]
|
2021-01-27 14:46:11 +08:00
|
|
|
rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg i0_pc_wb : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2021-01-28 15:16:34 +08:00
|
|
|
when _T_956 : @[Reg.scala 28:19]
|
2021-01-27 14:46:11 +08:00
|
|
|
i0_pc_wb <= io.dec_tlu_i0_pc_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
io.dec_i0_inst_wb <= i0_inst_wb @[dec_decode_ctl.scala 868:21]
|
|
|
|
|
io.dec_i0_pc_wb <= i0_pc_wb @[dec_decode_ctl.scala 869:19]
|
|
|
|
|
node _T_957 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 870:67]
|
|
|
|
|
wire _T_958 : UInt<31> @[lib.scala 648:38]
|
|
|
|
|
_T_958 <= UInt<1>("h00") @[lib.scala 648:38]
|
|
|
|
|
reg dec_i0_pc_r : UInt, clock with : (reset => (reset, _T_958)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_957 : @[Reg.scala 28:19]
|
2021-01-27 14:46:11 +08:00
|
|
|
dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
2021-01-28 15:16:34 +08:00
|
|
|
io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 872:27]
|
|
|
|
|
node _T_959 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_960 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_961 = bits(_T_959, 12, 1) @[lib.scala 68:24]
|
|
|
|
|
node _T_962 = bits(_T_960, 12, 1) @[lib.scala 68:40]
|
|
|
|
|
node _T_963 = add(_T_961, _T_962) @[lib.scala 68:31]
|
|
|
|
|
node _T_964 = bits(_T_959, 31, 13) @[lib.scala 69:20]
|
|
|
|
|
node _T_965 = add(_T_964, UInt<1>("h01")) @[lib.scala 69:27]
|
|
|
|
|
node _T_966 = tail(_T_965, 1) @[lib.scala 69:27]
|
|
|
|
|
node _T_967 = bits(_T_959, 31, 13) @[lib.scala 70:20]
|
|
|
|
|
node _T_968 = sub(_T_967, UInt<1>("h01")) @[lib.scala 70:27]
|
|
|
|
|
node _T_969 = tail(_T_968, 1) @[lib.scala 70:27]
|
|
|
|
|
node _T_970 = bits(_T_960, 12, 12) @[lib.scala 71:22]
|
|
|
|
|
node _T_971 = bits(_T_963, 12, 12) @[lib.scala 72:39]
|
|
|
|
|
node _T_972 = eq(_T_971, UInt<1>("h00")) @[lib.scala 72:28]
|
|
|
|
|
node _T_973 = xor(_T_970, _T_972) @[lib.scala 72:26]
|
|
|
|
|
node _T_974 = bits(_T_973, 0, 0) @[lib.scala 72:64]
|
|
|
|
|
node _T_975 = bits(_T_959, 31, 13) @[lib.scala 72:76]
|
|
|
|
|
node _T_976 = eq(_T_970, UInt<1>("h00")) @[lib.scala 73:20]
|
|
|
|
|
node _T_977 = bits(_T_963, 12, 12) @[lib.scala 73:39]
|
|
|
|
|
node _T_978 = and(_T_976, _T_977) @[lib.scala 73:26]
|
|
|
|
|
node _T_979 = bits(_T_978, 0, 0) @[lib.scala 73:64]
|
|
|
|
|
node _T_980 = bits(_T_963, 12, 12) @[lib.scala 74:39]
|
|
|
|
|
node _T_981 = eq(_T_980, UInt<1>("h00")) @[lib.scala 74:28]
|
|
|
|
|
node _T_982 = and(_T_970, _T_981) @[lib.scala 74:26]
|
|
|
|
|
node _T_983 = bits(_T_982, 0, 0) @[lib.scala 74:64]
|
|
|
|
|
node _T_984 = mux(_T_974, _T_975, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_985 = mux(_T_979, _T_966, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_986 = mux(_T_983, _T_969, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_987 = or(_T_984, _T_985) @[Mux.scala 27:72]
|
|
|
|
|
node _T_988 = or(_T_987, _T_986) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_989 : UInt<19> @[Mux.scala 27:72]
|
|
|
|
|
_T_989 <= _T_988 @[Mux.scala 27:72]
|
|
|
|
|
node _T_990 = bits(_T_963, 11, 0) @[lib.scala 74:94]
|
|
|
|
|
node _T_991 = cat(_T_989, _T_990) @[Cat.scala 29:58]
|
|
|
|
|
node temp_pred_correct_npc_x = cat(_T_991, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_992 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 877:62]
|
|
|
|
|
io.decode_exu.pred_correct_npc_x <= _T_992 @[dec_decode_ctl.scala 877:36]
|
|
|
|
|
node _T_993 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 881:59]
|
|
|
|
|
node _T_994 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 881:91]
|
|
|
|
|
node i0_rs1_depend_i0_x = and(_T_993, _T_994) @[dec_decode_ctl.scala 881:74]
|
|
|
|
|
node _T_995 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 882:59]
|
|
|
|
|
node _T_996 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 882:91]
|
|
|
|
|
node i0_rs1_depend_i0_r = and(_T_995, _T_996) @[dec_decode_ctl.scala 882:74]
|
|
|
|
|
node _T_997 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 884:59]
|
|
|
|
|
node _T_998 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 884:91]
|
|
|
|
|
node i0_rs2_depend_i0_x = and(_T_997, _T_998) @[dec_decode_ctl.scala 884:74]
|
|
|
|
|
node _T_999 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 885:59]
|
|
|
|
|
node _T_1000 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 885:91]
|
|
|
|
|
node i0_rs2_depend_i0_r = and(_T_999, _T_1000) @[dec_decode_ctl.scala 885:74]
|
|
|
|
|
node _T_1001 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 887:44]
|
|
|
|
|
node _T_1002 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 887:81]
|
|
|
|
|
wire _T_1003 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 887:109]
|
|
|
|
|
_T_1003.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109]
|
|
|
|
|
_T_1003.load <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109]
|
|
|
|
|
_T_1003.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 887:109]
|
|
|
|
|
node _T_1004 = mux(_T_1002, i0_r_c, _T_1003) @[dec_decode_ctl.scala 887:61]
|
|
|
|
|
node _T_1005 = mux(_T_1001, i0_x_c, _T_1004) @[dec_decode_ctl.scala 887:24]
|
|
|
|
|
i0_rs1_class_d.alu <= _T_1005.alu @[dec_decode_ctl.scala 887:18]
|
|
|
|
|
i0_rs1_class_d.load <= _T_1005.load @[dec_decode_ctl.scala 887:18]
|
|
|
|
|
i0_rs1_class_d.mul <= _T_1005.mul @[dec_decode_ctl.scala 887:18]
|
|
|
|
|
node _T_1006 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 888:44]
|
|
|
|
|
node _T_1007 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 888:83]
|
|
|
|
|
node _T_1008 = mux(_T_1007, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 888:63]
|
|
|
|
|
node _T_1009 = mux(_T_1006, UInt<2>("h01"), _T_1008) @[dec_decode_ctl.scala 888:24]
|
|
|
|
|
i0_rs1_depth_d <= _T_1009 @[dec_decode_ctl.scala 888:18]
|
|
|
|
|
node _T_1010 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 889:44]
|
|
|
|
|
node _T_1011 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 889:81]
|
|
|
|
|
wire _T_1012 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 889:109]
|
|
|
|
|
_T_1012.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109]
|
|
|
|
|
_T_1012.load <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109]
|
|
|
|
|
_T_1012.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 889:109]
|
|
|
|
|
node _T_1013 = mux(_T_1011, i0_r_c, _T_1012) @[dec_decode_ctl.scala 889:61]
|
|
|
|
|
node _T_1014 = mux(_T_1010, i0_x_c, _T_1013) @[dec_decode_ctl.scala 889:24]
|
|
|
|
|
i0_rs2_class_d.alu <= _T_1014.alu @[dec_decode_ctl.scala 889:18]
|
|
|
|
|
i0_rs2_class_d.load <= _T_1014.load @[dec_decode_ctl.scala 889:18]
|
|
|
|
|
i0_rs2_class_d.mul <= _T_1014.mul @[dec_decode_ctl.scala 889:18]
|
|
|
|
|
node _T_1015 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 890:44]
|
|
|
|
|
node _T_1016 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 890:83]
|
|
|
|
|
node _T_1017 = mux(_T_1016, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 890:63]
|
|
|
|
|
node _T_1018 = mux(_T_1015, UInt<2>("h01"), _T_1017) @[dec_decode_ctl.scala 890:24]
|
|
|
|
|
i0_rs2_depth_d <= _T_1018 @[dec_decode_ctl.scala 890:18]
|
|
|
|
|
i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 900:21]
|
|
|
|
|
node _T_1019 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 901:43]
|
|
|
|
|
node _T_1020 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 901:74]
|
|
|
|
|
node _T_1021 = and(_T_1019, _T_1020) @[dec_decode_ctl.scala 901:58]
|
|
|
|
|
node _T_1022 = and(_T_1021, i0_rs1_class_d.load) @[dec_decode_ctl.scala 901:78]
|
|
|
|
|
load_ldst_bypass_d <= _T_1022 @[dec_decode_ctl.scala 901:27]
|
|
|
|
|
node _T_1023 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 902:59]
|
|
|
|
|
node _T_1024 = and(i0_dp.store, _T_1023) @[dec_decode_ctl.scala 902:43]
|
|
|
|
|
node _T_1025 = and(_T_1024, i0_rs2_class_d.load) @[dec_decode_ctl.scala 902:63]
|
|
|
|
|
store_data_bypass_d <= _T_1025 @[dec_decode_ctl.scala 902:25]
|
|
|
|
|
store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 903:25]
|
|
|
|
|
node _T_1026 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 907:73]
|
|
|
|
|
node _T_1027 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 907:130]
|
|
|
|
|
node i0_rs1_nonblock_load_bypass_en_d = and(_T_1026, _T_1027) @[dec_decode_ctl.scala 907:100]
|
|
|
|
|
node _T_1028 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 909:73]
|
|
|
|
|
node _T_1029 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 909:130]
|
|
|
|
|
node i0_rs2_nonblock_load_bypass_en_d = and(_T_1028, _T_1029) @[dec_decode_ctl.scala 909:100]
|
|
|
|
|
node _T_1030 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 912:41]
|
|
|
|
|
node _T_1031 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 912:66]
|
|
|
|
|
node _T_1032 = and(_T_1030, _T_1031) @[dec_decode_ctl.scala 912:45]
|
|
|
|
|
node _T_1033 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 912:104]
|
|
|
|
|
node _T_1034 = and(_T_1033, i0_rs1_class_d.load) @[dec_decode_ctl.scala 912:108]
|
|
|
|
|
node _T_1035 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 912:149]
|
|
|
|
|
node _T_1036 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 912:175]
|
|
|
|
|
node _T_1037 = or(_T_1036, i0_rs1_class_d.load) @[dec_decode_ctl.scala 912:196]
|
|
|
|
|
node _T_1038 = and(_T_1035, _T_1037) @[dec_decode_ctl.scala 912:153]
|
|
|
|
|
node _T_1039 = cat(_T_1032, _T_1034) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1040 = cat(_T_1039, _T_1038) @[Cat.scala 29:58]
|
|
|
|
|
i0_rs1bypass <= _T_1040 @[dec_decode_ctl.scala 912:18]
|
|
|
|
|
node _T_1041 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 914:41]
|
|
|
|
|
node _T_1042 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 914:67]
|
|
|
|
|
node _T_1043 = and(_T_1041, _T_1042) @[dec_decode_ctl.scala 914:45]
|
|
|
|
|
node _T_1044 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 914:105]
|
|
|
|
|
node _T_1045 = and(_T_1044, i0_rs2_class_d.load) @[dec_decode_ctl.scala 914:109]
|
|
|
|
|
node _T_1046 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 914:149]
|
|
|
|
|
node _T_1047 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 914:175]
|
|
|
|
|
node _T_1048 = or(_T_1047, i0_rs2_class_d.load) @[dec_decode_ctl.scala 914:196]
|
|
|
|
|
node _T_1049 = and(_T_1046, _T_1048) @[dec_decode_ctl.scala 914:153]
|
|
|
|
|
node _T_1050 = cat(_T_1043, _T_1045) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1051 = cat(_T_1050, _T_1049) @[Cat.scala 29:58]
|
|
|
|
|
i0_rs2bypass <= _T_1051 @[dec_decode_ctl.scala 914:18]
|
|
|
|
|
node _T_1052 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 916:66]
|
|
|
|
|
node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[dec_decode_ctl.scala 916:53]
|
|
|
|
|
node _T_1054 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 916:85]
|
|
|
|
|
node _T_1055 = eq(_T_1054, UInt<1>("h00")) @[dec_decode_ctl.scala 916:72]
|
|
|
|
|
node _T_1056 = and(_T_1053, _T_1055) @[dec_decode_ctl.scala 916:70]
|
|
|
|
|
node _T_1057 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 916:104]
|
|
|
|
|
node _T_1058 = eq(_T_1057, UInt<1>("h00")) @[dec_decode_ctl.scala 916:91]
|
|
|
|
|
node _T_1059 = and(_T_1056, _T_1058) @[dec_decode_ctl.scala 916:89]
|
|
|
|
|
node _T_1060 = and(_T_1059, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 916:108]
|
|
|
|
|
node _T_1061 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 916:155]
|
|
|
|
|
node _T_1062 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 916:171]
|
|
|
|
|
node _T_1063 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 916:187]
|
|
|
|
|
node _T_1064 = cat(_T_1062, _T_1063) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1065 = cat(_T_1060, _T_1061) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1066 = cat(_T_1065, _T_1064) @[Cat.scala 29:58]
|
|
|
|
|
io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_1066 @[dec_decode_ctl.scala 916:45]
|
|
|
|
|
node _T_1067 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 917:66]
|
|
|
|
|
node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[dec_decode_ctl.scala 917:53]
|
|
|
|
|
node _T_1069 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 917:85]
|
|
|
|
|
node _T_1070 = eq(_T_1069, UInt<1>("h00")) @[dec_decode_ctl.scala 917:72]
|
|
|
|
|
node _T_1071 = and(_T_1068, _T_1070) @[dec_decode_ctl.scala 917:70]
|
|
|
|
|
node _T_1072 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 917:104]
|
|
|
|
|
node _T_1073 = eq(_T_1072, UInt<1>("h00")) @[dec_decode_ctl.scala 917:91]
|
|
|
|
|
node _T_1074 = and(_T_1071, _T_1073) @[dec_decode_ctl.scala 917:89]
|
|
|
|
|
node _T_1075 = and(_T_1074, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 917:108]
|
|
|
|
|
node _T_1076 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 917:155]
|
|
|
|
|
node _T_1077 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 917:171]
|
|
|
|
|
node _T_1078 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 917:187]
|
|
|
|
|
node _T_1079 = cat(_T_1077, _T_1078) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1080 = cat(_T_1075, _T_1076) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1081 = cat(_T_1080, _T_1079) @[Cat.scala 29:58]
|
|
|
|
|
io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_1081 @[dec_decode_ctl.scala 917:45]
|
|
|
|
|
io.decode_exu.dec_i0_result_r <= i0_result_r @[dec_decode_ctl.scala 919:41]
|
|
|
|
|
node _T_1082 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 921:68]
|
|
|
|
|
node _T_1083 = and(io.dec_ib0_valid_d, _T_1082) @[dec_decode_ctl.scala 921:50]
|
|
|
|
|
node _T_1084 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 921:89]
|
|
|
|
|
node _T_1085 = and(_T_1083, _T_1084) @[dec_decode_ctl.scala 921:87]
|
|
|
|
|
node _T_1086 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 921:123]
|
|
|
|
|
node _T_1087 = and(_T_1085, _T_1086) @[dec_decode_ctl.scala 921:121]
|
|
|
|
|
node _T_1088 = or(_T_1087, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 921:140]
|
|
|
|
|
io.dec_lsu_valid_raw_d <= _T_1088 @[dec_decode_ctl.scala 921:26]
|
|
|
|
|
node _T_1089 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 923:6]
|
|
|
|
|
node _T_1090 = and(_T_1089, i0_dp.lsu) @[dec_decode_ctl.scala 923:38]
|
|
|
|
|
node _T_1091 = and(_T_1090, i0_dp.load) @[dec_decode_ctl.scala 923:50]
|
|
|
|
|
node _T_1092 = bits(_T_1091, 0, 0) @[dec_decode_ctl.scala 923:64]
|
|
|
|
|
node _T_1093 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 923:81]
|
|
|
|
|
node _T_1094 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 924:6]
|
|
|
|
|
node _T_1095 = and(_T_1094, i0_dp.lsu) @[dec_decode_ctl.scala 924:38]
|
|
|
|
|
node _T_1096 = and(_T_1095, i0_dp.store) @[dec_decode_ctl.scala 924:50]
|
|
|
|
|
node _T_1097 = bits(_T_1096, 0, 0) @[dec_decode_ctl.scala 924:65]
|
|
|
|
|
node _T_1098 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 924:85]
|
|
|
|
|
node _T_1099 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 924:95]
|
|
|
|
|
node _T_1100 = cat(_T_1098, _T_1099) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1101 = mux(_T_1092, _T_1093, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1102 = mux(_T_1097, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1103 = or(_T_1101, _T_1102) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_1104 : UInt<12> @[Mux.scala 27:72]
|
|
|
|
|
_T_1104 <= _T_1103 @[Mux.scala 27:72]
|
|
|
|
|
io.dec_lsu_offset_d <= _T_1104 @[dec_decode_ctl.scala 922:23]
|
2021-01-27 14:46:11 +08:00
|
|
|
|
|
|
|
|
extmodule gated_latch_11 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_11 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_11 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_12 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_12 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_12 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_13 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_13 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_13 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_14 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_14 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_14 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_15 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_15 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_15 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_16 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_16 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_16 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_17 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_17 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_17 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_18 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_18 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_18 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_19 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_19 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_19 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_20 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_20 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_20 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_21 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_21 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_21 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_22 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_22 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_22 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_23 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_23 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_23 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_24 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_24 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_24 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_25 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_25 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_25 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_26 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_26 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_26 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_27 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_27 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_27 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_28 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_28 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_28 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_29 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_29 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_29 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_30 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_30 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_30 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_31 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_31 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_31 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_32 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_32 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_32 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_33 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_33 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_33 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_34 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_34 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_34 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_35 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_35 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_35 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_36 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_36 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_36 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_37 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_37 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_37 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_38 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_38 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_38 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_39 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_39 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_39 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_40 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_40 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_40 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_41 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_41 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_41 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
module dec_gpr_ctl :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : AsyncReset
|
|
|
|
|
output io : {flip raddr0 : UInt<5>, flip raddr1 : UInt<5>, flip wen0 : UInt<1>, flip waddr0 : UInt<5>, flip wd0 : UInt<32>, flip wen1 : UInt<1>, flip waddr1 : UInt<5>, flip wd1 : UInt<32>, flip wen2 : UInt<1>, flip waddr2 : UInt<5>, flip wd2 : UInt<32>, flip scan_mode : UInt<1>, flip gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}
|
|
|
|
|
|
|
|
|
|
wire w0v : UInt<1>[32] @[dec_gpr_ctl.scala 27:30]
|
|
|
|
|
w0v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
w0v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 28:13]
|
|
|
|
|
wire w1v : UInt<1>[32] @[dec_gpr_ctl.scala 30:30]
|
|
|
|
|
w1v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
w1v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 31:13]
|
|
|
|
|
wire w2v : UInt<1>[32] @[dec_gpr_ctl.scala 33:30]
|
|
|
|
|
w2v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
w2v[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 34:13]
|
|
|
|
|
wire gpr_in : UInt<32>[32] @[dec_gpr_ctl.scala 36:30]
|
|
|
|
|
gpr_in[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
gpr_in[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 37:16]
|
|
|
|
|
wire gpr_out : UInt<32>[32] @[dec_gpr_ctl.scala 39:30]
|
|
|
|
|
gpr_out[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[1] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[2] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[3] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[4] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[5] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[6] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[7] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[8] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[9] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[10] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[11] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[12] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[13] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[14] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[15] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[16] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[17] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[18] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[19] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[20] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[21] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[22] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[23] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[24] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[25] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[26] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[27] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[28] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[29] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[30] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
gpr_out[31] <= UInt<1>("h00") @[dec_gpr_ctl.scala 40:17]
|
|
|
|
|
wire gpr_wr_en : UInt<32>
|
|
|
|
|
gpr_wr_en <= UInt<1>("h00")
|
|
|
|
|
w0v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 43:15]
|
|
|
|
|
w1v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 44:15]
|
|
|
|
|
w2v[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 45:15]
|
|
|
|
|
gpr_out[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 46:19]
|
|
|
|
|
gpr_in[0] <= UInt<1>("h00") @[dec_gpr_ctl.scala 47:18]
|
|
|
|
|
io.gpr_exu.gpr_i0_rs1_d <= UInt<1>("h00") @[dec_gpr_ctl.scala 48:32]
|
|
|
|
|
io.gpr_exu.gpr_i0_rs2_d <= UInt<1>("h00") @[dec_gpr_ctl.scala 49:32]
|
|
|
|
|
node _T = eq(io.waddr0, UInt<1>("h01")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_1 = and(io.wen0, _T) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[1] <= _T_1 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_2 = eq(io.waddr1, UInt<1>("h01")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_3 = and(io.wen1, _T_2) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[1] <= _T_3 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_4 = eq(io.waddr2, UInt<1>("h01")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_5 = and(io.wen2, _T_4) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[1] <= _T_5 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_6 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_7 = mux(_T_6, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_8 = and(_T_7, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_9 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_10 = mux(_T_9, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_11 = and(_T_10, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_12 = or(_T_8, _T_11) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_13 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_14 = mux(_T_13, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_15 = and(_T_14, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_16 = or(_T_12, _T_15) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[1] <= _T_16 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_17 = eq(io.waddr0, UInt<2>("h02")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_18 = and(io.wen0, _T_17) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[2] <= _T_18 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_19 = eq(io.waddr1, UInt<2>("h02")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_20 = and(io.wen1, _T_19) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[2] <= _T_20 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_21 = eq(io.waddr2, UInt<2>("h02")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_22 = and(io.wen2, _T_21) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[2] <= _T_22 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_23 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_24 = mux(_T_23, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_25 = and(_T_24, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_26 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_27 = mux(_T_26, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_28 = and(_T_27, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_29 = or(_T_25, _T_28) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_30 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_31 = mux(_T_30, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_32 = and(_T_31, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_33 = or(_T_29, _T_32) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[2] <= _T_33 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_34 = eq(io.waddr0, UInt<2>("h03")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_35 = and(io.wen0, _T_34) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[3] <= _T_35 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_36 = eq(io.waddr1, UInt<2>("h03")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_37 = and(io.wen1, _T_36) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[3] <= _T_37 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_38 = eq(io.waddr2, UInt<2>("h03")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_39 = and(io.wen2, _T_38) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[3] <= _T_39 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_40 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_41 = mux(_T_40, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_42 = and(_T_41, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_43 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_44 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_45 = and(_T_44, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_46 = or(_T_42, _T_45) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_47 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_48 = mux(_T_47, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_49 = and(_T_48, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_50 = or(_T_46, _T_49) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[3] <= _T_50 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_51 = eq(io.waddr0, UInt<3>("h04")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_52 = and(io.wen0, _T_51) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[4] <= _T_52 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_53 = eq(io.waddr1, UInt<3>("h04")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_54 = and(io.wen1, _T_53) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[4] <= _T_54 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_55 = eq(io.waddr2, UInt<3>("h04")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_56 = and(io.wen2, _T_55) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[4] <= _T_56 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_57 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_58 = mux(_T_57, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_59 = and(_T_58, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_60 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_61 = mux(_T_60, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_62 = and(_T_61, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_63 = or(_T_59, _T_62) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_64 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_65 = mux(_T_64, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_66 = and(_T_65, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_67 = or(_T_63, _T_66) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[4] <= _T_67 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_68 = eq(io.waddr0, UInt<3>("h05")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_69 = and(io.wen0, _T_68) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[5] <= _T_69 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_70 = eq(io.waddr1, UInt<3>("h05")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_71 = and(io.wen1, _T_70) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[5] <= _T_71 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_72 = eq(io.waddr2, UInt<3>("h05")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_73 = and(io.wen2, _T_72) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[5] <= _T_73 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_74 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_75 = mux(_T_74, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_76 = and(_T_75, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_77 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_78 = mux(_T_77, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_79 = and(_T_78, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_80 = or(_T_76, _T_79) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_81 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_82 = mux(_T_81, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_83 = and(_T_82, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_84 = or(_T_80, _T_83) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[5] <= _T_84 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_85 = eq(io.waddr0, UInt<3>("h06")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_86 = and(io.wen0, _T_85) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[6] <= _T_86 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_87 = eq(io.waddr1, UInt<3>("h06")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_88 = and(io.wen1, _T_87) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[6] <= _T_88 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_89 = eq(io.waddr2, UInt<3>("h06")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_90 = and(io.wen2, _T_89) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[6] <= _T_90 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_91 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_93 = and(_T_92, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_94 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_96 = and(_T_95, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_97 = or(_T_93, _T_96) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_98 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_100 = and(_T_99, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_101 = or(_T_97, _T_100) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[6] <= _T_101 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_102 = eq(io.waddr0, UInt<3>("h07")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_103 = and(io.wen0, _T_102) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[7] <= _T_103 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_104 = eq(io.waddr1, UInt<3>("h07")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_105 = and(io.wen1, _T_104) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[7] <= _T_105 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_106 = eq(io.waddr2, UInt<3>("h07")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_107 = and(io.wen2, _T_106) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[7] <= _T_107 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_108 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_109 = mux(_T_108, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_110 = and(_T_109, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_111 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_113 = and(_T_112, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_114 = or(_T_110, _T_113) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_115 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_116 = mux(_T_115, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_117 = and(_T_116, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_118 = or(_T_114, _T_117) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[7] <= _T_118 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_119 = eq(io.waddr0, UInt<4>("h08")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_120 = and(io.wen0, _T_119) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[8] <= _T_120 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_121 = eq(io.waddr1, UInt<4>("h08")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_122 = and(io.wen1, _T_121) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[8] <= _T_122 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_123 = eq(io.waddr2, UInt<4>("h08")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_124 = and(io.wen2, _T_123) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[8] <= _T_124 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_125 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_127 = and(_T_126, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_128 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_129 = mux(_T_128, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_130 = and(_T_129, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_131 = or(_T_127, _T_130) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_132 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_133 = mux(_T_132, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_134 = and(_T_133, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_135 = or(_T_131, _T_134) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[8] <= _T_135 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_136 = eq(io.waddr0, UInt<4>("h09")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_137 = and(io.wen0, _T_136) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[9] <= _T_137 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_138 = eq(io.waddr1, UInt<4>("h09")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_139 = and(io.wen1, _T_138) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[9] <= _T_139 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_140 = eq(io.waddr2, UInt<4>("h09")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_141 = and(io.wen2, _T_140) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[9] <= _T_141 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_142 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_143 = mux(_T_142, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_144 = and(_T_143, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_145 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_146 = mux(_T_145, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_147 = and(_T_146, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_148 = or(_T_144, _T_147) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_149 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_150 = mux(_T_149, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_151 = and(_T_150, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_152 = or(_T_148, _T_151) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[9] <= _T_152 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_153 = eq(io.waddr0, UInt<4>("h0a")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_154 = and(io.wen0, _T_153) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[10] <= _T_154 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_155 = eq(io.waddr1, UInt<4>("h0a")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_156 = and(io.wen1, _T_155) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[10] <= _T_156 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_157 = eq(io.waddr2, UInt<4>("h0a")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_158 = and(io.wen2, _T_157) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[10] <= _T_158 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_159 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_160 = mux(_T_159, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_161 = and(_T_160, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_162 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_163 = mux(_T_162, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_164 = and(_T_163, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_165 = or(_T_161, _T_164) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_166 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_167 = mux(_T_166, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_168 = and(_T_167, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_169 = or(_T_165, _T_168) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[10] <= _T_169 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_170 = eq(io.waddr0, UInt<4>("h0b")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_171 = and(io.wen0, _T_170) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[11] <= _T_171 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_172 = eq(io.waddr1, UInt<4>("h0b")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_173 = and(io.wen1, _T_172) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[11] <= _T_173 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_174 = eq(io.waddr2, UInt<4>("h0b")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_175 = and(io.wen2, _T_174) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[11] <= _T_175 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_176 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_177 = mux(_T_176, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_178 = and(_T_177, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_179 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_180 = mux(_T_179, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_181 = and(_T_180, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_182 = or(_T_178, _T_181) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_183 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_184 = mux(_T_183, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_185 = and(_T_184, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_186 = or(_T_182, _T_185) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[11] <= _T_186 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_187 = eq(io.waddr0, UInt<4>("h0c")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_188 = and(io.wen0, _T_187) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[12] <= _T_188 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_189 = eq(io.waddr1, UInt<4>("h0c")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_190 = and(io.wen1, _T_189) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[12] <= _T_190 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_191 = eq(io.waddr2, UInt<4>("h0c")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_192 = and(io.wen2, _T_191) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[12] <= _T_192 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_193 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_194 = mux(_T_193, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_195 = and(_T_194, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_196 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_197 = mux(_T_196, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_198 = and(_T_197, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_199 = or(_T_195, _T_198) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_200 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_202 = and(_T_201, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_203 = or(_T_199, _T_202) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[12] <= _T_203 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_204 = eq(io.waddr0, UInt<4>("h0d")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_205 = and(io.wen0, _T_204) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[13] <= _T_205 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_206 = eq(io.waddr1, UInt<4>("h0d")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_207 = and(io.wen1, _T_206) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[13] <= _T_207 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_208 = eq(io.waddr2, UInt<4>("h0d")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_209 = and(io.wen2, _T_208) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[13] <= _T_209 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_210 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_211 = mux(_T_210, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_212 = and(_T_211, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_213 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_214 = mux(_T_213, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_215 = and(_T_214, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_216 = or(_T_212, _T_215) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_217 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_218 = mux(_T_217, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_219 = and(_T_218, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_220 = or(_T_216, _T_219) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[13] <= _T_220 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_221 = eq(io.waddr0, UInt<4>("h0e")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_222 = and(io.wen0, _T_221) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[14] <= _T_222 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_223 = eq(io.waddr1, UInt<4>("h0e")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_224 = and(io.wen1, _T_223) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[14] <= _T_224 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_225 = eq(io.waddr2, UInt<4>("h0e")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_226 = and(io.wen2, _T_225) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[14] <= _T_226 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_227 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_228 = mux(_T_227, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_229 = and(_T_228, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_230 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_231 = mux(_T_230, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_232 = and(_T_231, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_233 = or(_T_229, _T_232) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_234 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_236 = and(_T_235, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_237 = or(_T_233, _T_236) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[14] <= _T_237 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_238 = eq(io.waddr0, UInt<4>("h0f")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_239 = and(io.wen0, _T_238) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[15] <= _T_239 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_240 = eq(io.waddr1, UInt<4>("h0f")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_241 = and(io.wen1, _T_240) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[15] <= _T_241 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_242 = eq(io.waddr2, UInt<4>("h0f")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_243 = and(io.wen2, _T_242) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[15] <= _T_243 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_244 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_245 = mux(_T_244, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_246 = and(_T_245, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_247 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_248 = mux(_T_247, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_249 = and(_T_248, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_250 = or(_T_246, _T_249) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_251 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_252 = mux(_T_251, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_253 = and(_T_252, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_254 = or(_T_250, _T_253) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[15] <= _T_254 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_255 = eq(io.waddr0, UInt<5>("h010")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_256 = and(io.wen0, _T_255) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[16] <= _T_256 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_257 = eq(io.waddr1, UInt<5>("h010")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_258 = and(io.wen1, _T_257) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[16] <= _T_258 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_259 = eq(io.waddr2, UInt<5>("h010")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_260 = and(io.wen2, _T_259) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[16] <= _T_260 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_261 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_262 = mux(_T_261, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_263 = and(_T_262, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_264 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_265 = mux(_T_264, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_266 = and(_T_265, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_267 = or(_T_263, _T_266) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_268 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_269 = mux(_T_268, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_270 = and(_T_269, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_271 = or(_T_267, _T_270) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[16] <= _T_271 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_272 = eq(io.waddr0, UInt<5>("h011")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_273 = and(io.wen0, _T_272) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[17] <= _T_273 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_274 = eq(io.waddr1, UInt<5>("h011")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_275 = and(io.wen1, _T_274) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[17] <= _T_275 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_276 = eq(io.waddr2, UInt<5>("h011")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_277 = and(io.wen2, _T_276) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[17] <= _T_277 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_278 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_279 = mux(_T_278, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_280 = and(_T_279, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_281 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_282 = mux(_T_281, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_283 = and(_T_282, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_284 = or(_T_280, _T_283) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_285 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_286 = mux(_T_285, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_287 = and(_T_286, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_288 = or(_T_284, _T_287) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[17] <= _T_288 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_289 = eq(io.waddr0, UInt<5>("h012")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_290 = and(io.wen0, _T_289) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[18] <= _T_290 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_291 = eq(io.waddr1, UInt<5>("h012")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_292 = and(io.wen1, _T_291) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[18] <= _T_292 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_293 = eq(io.waddr2, UInt<5>("h012")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_294 = and(io.wen2, _T_293) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[18] <= _T_294 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_295 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_297 = and(_T_296, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_298 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_300 = and(_T_299, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_301 = or(_T_297, _T_300) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_302 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_303 = mux(_T_302, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_304 = and(_T_303, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_305 = or(_T_301, _T_304) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[18] <= _T_305 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_306 = eq(io.waddr0, UInt<5>("h013")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_307 = and(io.wen0, _T_306) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[19] <= _T_307 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_308 = eq(io.waddr1, UInt<5>("h013")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_309 = and(io.wen1, _T_308) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[19] <= _T_309 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_310 = eq(io.waddr2, UInt<5>("h013")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_311 = and(io.wen2, _T_310) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[19] <= _T_311 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_312 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_313 = mux(_T_312, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_314 = and(_T_313, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_315 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_316 = mux(_T_315, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_317 = and(_T_316, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_318 = or(_T_314, _T_317) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_319 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_320 = mux(_T_319, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_321 = and(_T_320, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_322 = or(_T_318, _T_321) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[19] <= _T_322 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_323 = eq(io.waddr0, UInt<5>("h014")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_324 = and(io.wen0, _T_323) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[20] <= _T_324 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_325 = eq(io.waddr1, UInt<5>("h014")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_326 = and(io.wen1, _T_325) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[20] <= _T_326 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_327 = eq(io.waddr2, UInt<5>("h014")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_328 = and(io.wen2, _T_327) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[20] <= _T_328 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_329 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_330 = mux(_T_329, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_331 = and(_T_330, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_332 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_333 = mux(_T_332, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_334 = and(_T_333, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_335 = or(_T_331, _T_334) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_336 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_337 = mux(_T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_338 = and(_T_337, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_339 = or(_T_335, _T_338) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[20] <= _T_339 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_340 = eq(io.waddr0, UInt<5>("h015")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_341 = and(io.wen0, _T_340) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[21] <= _T_341 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_342 = eq(io.waddr1, UInt<5>("h015")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_343 = and(io.wen1, _T_342) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[21] <= _T_343 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_344 = eq(io.waddr2, UInt<5>("h015")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_345 = and(io.wen2, _T_344) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[21] <= _T_345 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_346 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_347 = mux(_T_346, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_348 = and(_T_347, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_349 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_350 = mux(_T_349, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_351 = and(_T_350, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_352 = or(_T_348, _T_351) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_353 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_354 = mux(_T_353, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_355 = and(_T_354, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_356 = or(_T_352, _T_355) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[21] <= _T_356 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_357 = eq(io.waddr0, UInt<5>("h016")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_358 = and(io.wen0, _T_357) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[22] <= _T_358 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_359 = eq(io.waddr1, UInt<5>("h016")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_360 = and(io.wen1, _T_359) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[22] <= _T_360 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_361 = eq(io.waddr2, UInt<5>("h016")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_362 = and(io.wen2, _T_361) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[22] <= _T_362 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_363 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_364 = mux(_T_363, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_365 = and(_T_364, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_366 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_367 = mux(_T_366, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_368 = and(_T_367, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_369 = or(_T_365, _T_368) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_370 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_371 = mux(_T_370, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_372 = and(_T_371, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_373 = or(_T_369, _T_372) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[22] <= _T_373 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_374 = eq(io.waddr0, UInt<5>("h017")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_375 = and(io.wen0, _T_374) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[23] <= _T_375 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_376 = eq(io.waddr1, UInt<5>("h017")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_377 = and(io.wen1, _T_376) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[23] <= _T_377 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_378 = eq(io.waddr2, UInt<5>("h017")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_379 = and(io.wen2, _T_378) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[23] <= _T_379 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_380 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_382 = and(_T_381, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_383 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_384 = mux(_T_383, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_385 = and(_T_384, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_386 = or(_T_382, _T_385) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_387 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_388 = mux(_T_387, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_389 = and(_T_388, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_390 = or(_T_386, _T_389) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[23] <= _T_390 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_391 = eq(io.waddr0, UInt<5>("h018")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_392 = and(io.wen0, _T_391) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[24] <= _T_392 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_393 = eq(io.waddr1, UInt<5>("h018")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_394 = and(io.wen1, _T_393) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[24] <= _T_394 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_395 = eq(io.waddr2, UInt<5>("h018")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_396 = and(io.wen2, _T_395) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[24] <= _T_396 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_397 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_398 = mux(_T_397, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_399 = and(_T_398, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_400 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_401 = mux(_T_400, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_402 = and(_T_401, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_403 = or(_T_399, _T_402) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_404 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_405 = mux(_T_404, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_406 = and(_T_405, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_407 = or(_T_403, _T_406) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[24] <= _T_407 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_408 = eq(io.waddr0, UInt<5>("h019")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_409 = and(io.wen0, _T_408) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[25] <= _T_409 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_410 = eq(io.waddr1, UInt<5>("h019")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_411 = and(io.wen1, _T_410) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[25] <= _T_411 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_412 = eq(io.waddr2, UInt<5>("h019")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_413 = and(io.wen2, _T_412) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[25] <= _T_413 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_414 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_416 = and(_T_415, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_417 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_418 = mux(_T_417, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_419 = and(_T_418, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_420 = or(_T_416, _T_419) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_421 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_422 = mux(_T_421, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_423 = and(_T_422, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_424 = or(_T_420, _T_423) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[25] <= _T_424 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_425 = eq(io.waddr0, UInt<5>("h01a")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_426 = and(io.wen0, _T_425) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[26] <= _T_426 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_427 = eq(io.waddr1, UInt<5>("h01a")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_428 = and(io.wen1, _T_427) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[26] <= _T_428 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_429 = eq(io.waddr2, UInt<5>("h01a")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_430 = and(io.wen2, _T_429) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[26] <= _T_430 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_431 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_432 = mux(_T_431, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_433 = and(_T_432, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_434 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_435 = mux(_T_434, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_436 = and(_T_435, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_437 = or(_T_433, _T_436) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_438 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_440 = and(_T_439, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_441 = or(_T_437, _T_440) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[26] <= _T_441 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_442 = eq(io.waddr0, UInt<5>("h01b")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_443 = and(io.wen0, _T_442) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[27] <= _T_443 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_444 = eq(io.waddr1, UInt<5>("h01b")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_445 = and(io.wen1, _T_444) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[27] <= _T_445 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_446 = eq(io.waddr2, UInt<5>("h01b")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_447 = and(io.wen2, _T_446) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[27] <= _T_447 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_448 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_450 = and(_T_449, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_451 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_452 = mux(_T_451, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_453 = and(_T_452, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_454 = or(_T_450, _T_453) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_455 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_457 = and(_T_456, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_458 = or(_T_454, _T_457) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[27] <= _T_458 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_459 = eq(io.waddr0, UInt<5>("h01c")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_460 = and(io.wen0, _T_459) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[28] <= _T_460 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_461 = eq(io.waddr1, UInt<5>("h01c")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_462 = and(io.wen1, _T_461) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[28] <= _T_462 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_463 = eq(io.waddr2, UInt<5>("h01c")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_464 = and(io.wen2, _T_463) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[28] <= _T_464 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_465 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_467 = and(_T_466, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_468 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_470 = and(_T_469, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_471 = or(_T_467, _T_470) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_472 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_473 = mux(_T_472, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_474 = and(_T_473, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_475 = or(_T_471, _T_474) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[28] <= _T_475 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_476 = eq(io.waddr0, UInt<5>("h01d")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_477 = and(io.wen0, _T_476) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[29] <= _T_477 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_478 = eq(io.waddr1, UInt<5>("h01d")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_479 = and(io.wen1, _T_478) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[29] <= _T_479 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_480 = eq(io.waddr2, UInt<5>("h01d")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_481 = and(io.wen2, _T_480) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[29] <= _T_481 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_482 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_483 = mux(_T_482, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_484 = and(_T_483, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_485 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_486 = mux(_T_485, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_487 = and(_T_486, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_488 = or(_T_484, _T_487) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_489 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_490 = mux(_T_489, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_491 = and(_T_490, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_492 = or(_T_488, _T_491) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[29] <= _T_492 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_493 = eq(io.waddr0, UInt<5>("h01e")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_494 = and(io.wen0, _T_493) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[30] <= _T_494 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_495 = eq(io.waddr1, UInt<5>("h01e")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_496 = and(io.wen1, _T_495) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[30] <= _T_496 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_497 = eq(io.waddr2, UInt<5>("h01e")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_498 = and(io.wen2, _T_497) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[30] <= _T_498 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_499 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_500 = mux(_T_499, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_501 = and(_T_500, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_502 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_503 = mux(_T_502, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_504 = and(_T_503, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_505 = or(_T_501, _T_504) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_506 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_507 = mux(_T_506, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_508 = and(_T_507, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_509 = or(_T_505, _T_508) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[30] <= _T_509 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_510 = eq(io.waddr0, UInt<5>("h01f")) @[dec_gpr_ctl.scala 52:52]
|
|
|
|
|
node _T_511 = and(io.wen0, _T_510) @[dec_gpr_ctl.scala 52:40]
|
|
|
|
|
w0v[31] <= _T_511 @[dec_gpr_ctl.scala 52:28]
|
|
|
|
|
node _T_512 = eq(io.waddr1, UInt<5>("h01f")) @[dec_gpr_ctl.scala 53:52]
|
|
|
|
|
node _T_513 = and(io.wen1, _T_512) @[dec_gpr_ctl.scala 53:40]
|
|
|
|
|
w1v[31] <= _T_513 @[dec_gpr_ctl.scala 53:28]
|
|
|
|
|
node _T_514 = eq(io.waddr2, UInt<5>("h01f")) @[dec_gpr_ctl.scala 54:52]
|
|
|
|
|
node _T_515 = and(io.wen2, _T_514) @[dec_gpr_ctl.scala 54:40]
|
|
|
|
|
w2v[31] <= _T_515 @[dec_gpr_ctl.scala 54:28]
|
|
|
|
|
node _T_516 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_517 = mux(_T_516, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_518 = and(_T_517, io.wd0) @[dec_gpr_ctl.scala 55:49]
|
|
|
|
|
node _T_519 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_520 = mux(_T_519, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_521 = and(_T_520, io.wd1) @[dec_gpr_ctl.scala 55:78]
|
|
|
|
|
node _T_522 = or(_T_518, _T_521) @[dec_gpr_ctl.scala 55:59]
|
|
|
|
|
node _T_523 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_524 = mux(_T_523, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_525 = and(_T_524, io.wd2) @[dec_gpr_ctl.scala 55:107]
|
|
|
|
|
node _T_526 = or(_T_522, _T_525) @[dec_gpr_ctl.scala 55:88]
|
|
|
|
|
gpr_in[31] <= _T_526 @[dec_gpr_ctl.scala 55:28]
|
|
|
|
|
node _T_527 = cat(w0v[1], w0v[0]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_528 = cat(w0v[2], _T_527) @[Cat.scala 29:58]
|
|
|
|
|
node _T_529 = cat(w0v[3], _T_528) @[Cat.scala 29:58]
|
|
|
|
|
node _T_530 = cat(w0v[4], _T_529) @[Cat.scala 29:58]
|
|
|
|
|
node _T_531 = cat(w0v[5], _T_530) @[Cat.scala 29:58]
|
|
|
|
|
node _T_532 = cat(w0v[6], _T_531) @[Cat.scala 29:58]
|
|
|
|
|
node _T_533 = cat(w0v[7], _T_532) @[Cat.scala 29:58]
|
|
|
|
|
node _T_534 = cat(w0v[8], _T_533) @[Cat.scala 29:58]
|
|
|
|
|
node _T_535 = cat(w0v[9], _T_534) @[Cat.scala 29:58]
|
|
|
|
|
node _T_536 = cat(w0v[10], _T_535) @[Cat.scala 29:58]
|
|
|
|
|
node _T_537 = cat(w0v[11], _T_536) @[Cat.scala 29:58]
|
|
|
|
|
node _T_538 = cat(w0v[12], _T_537) @[Cat.scala 29:58]
|
|
|
|
|
node _T_539 = cat(w0v[13], _T_538) @[Cat.scala 29:58]
|
|
|
|
|
node _T_540 = cat(w0v[14], _T_539) @[Cat.scala 29:58]
|
|
|
|
|
node _T_541 = cat(w0v[15], _T_540) @[Cat.scala 29:58]
|
|
|
|
|
node _T_542 = cat(w0v[16], _T_541) @[Cat.scala 29:58]
|
|
|
|
|
node _T_543 = cat(w0v[17], _T_542) @[Cat.scala 29:58]
|
|
|
|
|
node _T_544 = cat(w0v[18], _T_543) @[Cat.scala 29:58]
|
|
|
|
|
node _T_545 = cat(w0v[19], _T_544) @[Cat.scala 29:58]
|
|
|
|
|
node _T_546 = cat(w0v[20], _T_545) @[Cat.scala 29:58]
|
|
|
|
|
node _T_547 = cat(w0v[21], _T_546) @[Cat.scala 29:58]
|
|
|
|
|
node _T_548 = cat(w0v[22], _T_547) @[Cat.scala 29:58]
|
|
|
|
|
node _T_549 = cat(w0v[23], _T_548) @[Cat.scala 29:58]
|
|
|
|
|
node _T_550 = cat(w0v[24], _T_549) @[Cat.scala 29:58]
|
|
|
|
|
node _T_551 = cat(w0v[25], _T_550) @[Cat.scala 29:58]
|
|
|
|
|
node _T_552 = cat(w0v[26], _T_551) @[Cat.scala 29:58]
|
|
|
|
|
node _T_553 = cat(w0v[27], _T_552) @[Cat.scala 29:58]
|
|
|
|
|
node _T_554 = cat(w0v[28], _T_553) @[Cat.scala 29:58]
|
|
|
|
|
node _T_555 = cat(w0v[29], _T_554) @[Cat.scala 29:58]
|
|
|
|
|
node _T_556 = cat(w0v[30], _T_555) @[Cat.scala 29:58]
|
|
|
|
|
node _T_557 = cat(w0v[31], _T_556) @[Cat.scala 29:58]
|
|
|
|
|
node _T_558 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_559 = cat(w1v[2], _T_558) @[Cat.scala 29:58]
|
|
|
|
|
node _T_560 = cat(w1v[3], _T_559) @[Cat.scala 29:58]
|
|
|
|
|
node _T_561 = cat(w1v[4], _T_560) @[Cat.scala 29:58]
|
|
|
|
|
node _T_562 = cat(w1v[5], _T_561) @[Cat.scala 29:58]
|
|
|
|
|
node _T_563 = cat(w1v[6], _T_562) @[Cat.scala 29:58]
|
|
|
|
|
node _T_564 = cat(w1v[7], _T_563) @[Cat.scala 29:58]
|
|
|
|
|
node _T_565 = cat(w1v[8], _T_564) @[Cat.scala 29:58]
|
|
|
|
|
node _T_566 = cat(w1v[9], _T_565) @[Cat.scala 29:58]
|
|
|
|
|
node _T_567 = cat(w1v[10], _T_566) @[Cat.scala 29:58]
|
|
|
|
|
node _T_568 = cat(w1v[11], _T_567) @[Cat.scala 29:58]
|
|
|
|
|
node _T_569 = cat(w1v[12], _T_568) @[Cat.scala 29:58]
|
|
|
|
|
node _T_570 = cat(w1v[13], _T_569) @[Cat.scala 29:58]
|
|
|
|
|
node _T_571 = cat(w1v[14], _T_570) @[Cat.scala 29:58]
|
|
|
|
|
node _T_572 = cat(w1v[15], _T_571) @[Cat.scala 29:58]
|
|
|
|
|
node _T_573 = cat(w1v[16], _T_572) @[Cat.scala 29:58]
|
|
|
|
|
node _T_574 = cat(w1v[17], _T_573) @[Cat.scala 29:58]
|
|
|
|
|
node _T_575 = cat(w1v[18], _T_574) @[Cat.scala 29:58]
|
|
|
|
|
node _T_576 = cat(w1v[19], _T_575) @[Cat.scala 29:58]
|
|
|
|
|
node _T_577 = cat(w1v[20], _T_576) @[Cat.scala 29:58]
|
|
|
|
|
node _T_578 = cat(w1v[21], _T_577) @[Cat.scala 29:58]
|
|
|
|
|
node _T_579 = cat(w1v[22], _T_578) @[Cat.scala 29:58]
|
|
|
|
|
node _T_580 = cat(w1v[23], _T_579) @[Cat.scala 29:58]
|
|
|
|
|
node _T_581 = cat(w1v[24], _T_580) @[Cat.scala 29:58]
|
|
|
|
|
node _T_582 = cat(w1v[25], _T_581) @[Cat.scala 29:58]
|
|
|
|
|
node _T_583 = cat(w1v[26], _T_582) @[Cat.scala 29:58]
|
|
|
|
|
node _T_584 = cat(w1v[27], _T_583) @[Cat.scala 29:58]
|
|
|
|
|
node _T_585 = cat(w1v[28], _T_584) @[Cat.scala 29:58]
|
|
|
|
|
node _T_586 = cat(w1v[29], _T_585) @[Cat.scala 29:58]
|
|
|
|
|
node _T_587 = cat(w1v[30], _T_586) @[Cat.scala 29:58]
|
|
|
|
|
node _T_588 = cat(w1v[31], _T_587) @[Cat.scala 29:58]
|
|
|
|
|
node _T_589 = or(_T_557, _T_588) @[dec_gpr_ctl.scala 57:57]
|
|
|
|
|
node _T_590 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_591 = cat(w2v[2], _T_590) @[Cat.scala 29:58]
|
|
|
|
|
node _T_592 = cat(w2v[3], _T_591) @[Cat.scala 29:58]
|
|
|
|
|
node _T_593 = cat(w2v[4], _T_592) @[Cat.scala 29:58]
|
|
|
|
|
node _T_594 = cat(w2v[5], _T_593) @[Cat.scala 29:58]
|
|
|
|
|
node _T_595 = cat(w2v[6], _T_594) @[Cat.scala 29:58]
|
|
|
|
|
node _T_596 = cat(w2v[7], _T_595) @[Cat.scala 29:58]
|
|
|
|
|
node _T_597 = cat(w2v[8], _T_596) @[Cat.scala 29:58]
|
|
|
|
|
node _T_598 = cat(w2v[9], _T_597) @[Cat.scala 29:58]
|
|
|
|
|
node _T_599 = cat(w2v[10], _T_598) @[Cat.scala 29:58]
|
|
|
|
|
node _T_600 = cat(w2v[11], _T_599) @[Cat.scala 29:58]
|
|
|
|
|
node _T_601 = cat(w2v[12], _T_600) @[Cat.scala 29:58]
|
|
|
|
|
node _T_602 = cat(w2v[13], _T_601) @[Cat.scala 29:58]
|
|
|
|
|
node _T_603 = cat(w2v[14], _T_602) @[Cat.scala 29:58]
|
|
|
|
|
node _T_604 = cat(w2v[15], _T_603) @[Cat.scala 29:58]
|
|
|
|
|
node _T_605 = cat(w2v[16], _T_604) @[Cat.scala 29:58]
|
|
|
|
|
node _T_606 = cat(w2v[17], _T_605) @[Cat.scala 29:58]
|
|
|
|
|
node _T_607 = cat(w2v[18], _T_606) @[Cat.scala 29:58]
|
|
|
|
|
node _T_608 = cat(w2v[19], _T_607) @[Cat.scala 29:58]
|
|
|
|
|
node _T_609 = cat(w2v[20], _T_608) @[Cat.scala 29:58]
|
|
|
|
|
node _T_610 = cat(w2v[21], _T_609) @[Cat.scala 29:58]
|
|
|
|
|
node _T_611 = cat(w2v[22], _T_610) @[Cat.scala 29:58]
|
|
|
|
|
node _T_612 = cat(w2v[23], _T_611) @[Cat.scala 29:58]
|
|
|
|
|
node _T_613 = cat(w2v[24], _T_612) @[Cat.scala 29:58]
|
|
|
|
|
node _T_614 = cat(w2v[25], _T_613) @[Cat.scala 29:58]
|
|
|
|
|
node _T_615 = cat(w2v[26], _T_614) @[Cat.scala 29:58]
|
|
|
|
|
node _T_616 = cat(w2v[27], _T_615) @[Cat.scala 29:58]
|
|
|
|
|
node _T_617 = cat(w2v[28], _T_616) @[Cat.scala 29:58]
|
|
|
|
|
node _T_618 = cat(w2v[29], _T_617) @[Cat.scala 29:58]
|
|
|
|
|
node _T_619 = cat(w2v[30], _T_618) @[Cat.scala 29:58]
|
|
|
|
|
node _T_620 = cat(w2v[31], _T_619) @[Cat.scala 29:58]
|
|
|
|
|
node _T_621 = or(_T_589, _T_620) @[dec_gpr_ctl.scala 57:95]
|
|
|
|
|
gpr_wr_en <= _T_621 @[dec_gpr_ctl.scala 57:18]
|
|
|
|
|
node _T_622 = bits(gpr_wr_en, 1, 1) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr of rvclkhdr_11 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr.clock <= clock
|
|
|
|
|
rvclkhdr.reset <= reset
|
|
|
|
|
rvclkhdr.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr.io.en <= _T_622 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_623 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_622 : @[Reg.scala 28:19]
|
|
|
|
|
_T_623 <= gpr_in[1] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[1] <= _T_623 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_624 = bits(gpr_wr_en, 2, 2) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_1 of rvclkhdr_12 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_1.clock <= clock
|
|
|
|
|
rvclkhdr_1.reset <= reset
|
|
|
|
|
rvclkhdr_1.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_1.io.en <= _T_624 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_625 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_624 : @[Reg.scala 28:19]
|
|
|
|
|
_T_625 <= gpr_in[2] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[2] <= _T_625 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_626 = bits(gpr_wr_en, 3, 3) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_2 of rvclkhdr_13 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_2.clock <= clock
|
|
|
|
|
rvclkhdr_2.reset <= reset
|
|
|
|
|
rvclkhdr_2.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_2.io.en <= _T_626 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_627 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_626 : @[Reg.scala 28:19]
|
|
|
|
|
_T_627 <= gpr_in[3] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[3] <= _T_627 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_628 = bits(gpr_wr_en, 4, 4) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_3 of rvclkhdr_14 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_3.clock <= clock
|
|
|
|
|
rvclkhdr_3.reset <= reset
|
|
|
|
|
rvclkhdr_3.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_3.io.en <= _T_628 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_629 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_628 : @[Reg.scala 28:19]
|
|
|
|
|
_T_629 <= gpr_in[4] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[4] <= _T_629 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_630 = bits(gpr_wr_en, 5, 5) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_4 of rvclkhdr_15 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_4.clock <= clock
|
|
|
|
|
rvclkhdr_4.reset <= reset
|
|
|
|
|
rvclkhdr_4.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_4.io.en <= _T_630 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_631 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_630 : @[Reg.scala 28:19]
|
|
|
|
|
_T_631 <= gpr_in[5] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[5] <= _T_631 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_632 = bits(gpr_wr_en, 6, 6) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_5 of rvclkhdr_16 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_5.clock <= clock
|
|
|
|
|
rvclkhdr_5.reset <= reset
|
|
|
|
|
rvclkhdr_5.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_5.io.en <= _T_632 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_633 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_632 : @[Reg.scala 28:19]
|
|
|
|
|
_T_633 <= gpr_in[6] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[6] <= _T_633 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_634 = bits(gpr_wr_en, 7, 7) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_6 of rvclkhdr_17 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_6.clock <= clock
|
|
|
|
|
rvclkhdr_6.reset <= reset
|
|
|
|
|
rvclkhdr_6.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_6.io.en <= _T_634 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_635 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_634 : @[Reg.scala 28:19]
|
|
|
|
|
_T_635 <= gpr_in[7] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[7] <= _T_635 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_636 = bits(gpr_wr_en, 8, 8) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_7 of rvclkhdr_18 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_7.clock <= clock
|
|
|
|
|
rvclkhdr_7.reset <= reset
|
|
|
|
|
rvclkhdr_7.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_7.io.en <= _T_636 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_637 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_636 : @[Reg.scala 28:19]
|
|
|
|
|
_T_637 <= gpr_in[8] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[8] <= _T_637 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_638 = bits(gpr_wr_en, 9, 9) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_8 of rvclkhdr_19 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_8.clock <= clock
|
|
|
|
|
rvclkhdr_8.reset <= reset
|
|
|
|
|
rvclkhdr_8.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_8.io.en <= _T_638 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_639 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_638 : @[Reg.scala 28:19]
|
|
|
|
|
_T_639 <= gpr_in[9] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[9] <= _T_639 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_640 = bits(gpr_wr_en, 10, 10) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_9 of rvclkhdr_20 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_9.clock <= clock
|
|
|
|
|
rvclkhdr_9.reset <= reset
|
|
|
|
|
rvclkhdr_9.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_9.io.en <= _T_640 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_641 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_640 : @[Reg.scala 28:19]
|
|
|
|
|
_T_641 <= gpr_in[10] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[10] <= _T_641 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_642 = bits(gpr_wr_en, 11, 11) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_10 of rvclkhdr_21 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_10.clock <= clock
|
|
|
|
|
rvclkhdr_10.reset <= reset
|
|
|
|
|
rvclkhdr_10.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_10.io.en <= _T_642 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_643 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_642 : @[Reg.scala 28:19]
|
|
|
|
|
_T_643 <= gpr_in[11] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[11] <= _T_643 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_644 = bits(gpr_wr_en, 12, 12) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_11 of rvclkhdr_22 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_11.clock <= clock
|
|
|
|
|
rvclkhdr_11.reset <= reset
|
|
|
|
|
rvclkhdr_11.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_11.io.en <= _T_644 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_645 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_644 : @[Reg.scala 28:19]
|
|
|
|
|
_T_645 <= gpr_in[12] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[12] <= _T_645 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_646 = bits(gpr_wr_en, 13, 13) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_12 of rvclkhdr_23 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_12.clock <= clock
|
|
|
|
|
rvclkhdr_12.reset <= reset
|
|
|
|
|
rvclkhdr_12.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_12.io.en <= _T_646 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_12.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_647 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_646 : @[Reg.scala 28:19]
|
|
|
|
|
_T_647 <= gpr_in[13] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[13] <= _T_647 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_648 = bits(gpr_wr_en, 14, 14) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_13 of rvclkhdr_24 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_13.clock <= clock
|
|
|
|
|
rvclkhdr_13.reset <= reset
|
|
|
|
|
rvclkhdr_13.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_13.io.en <= _T_648 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_13.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_649 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_648 : @[Reg.scala 28:19]
|
|
|
|
|
_T_649 <= gpr_in[14] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[14] <= _T_649 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_650 = bits(gpr_wr_en, 15, 15) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_14 of rvclkhdr_25 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_14.clock <= clock
|
|
|
|
|
rvclkhdr_14.reset <= reset
|
|
|
|
|
rvclkhdr_14.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_14.io.en <= _T_650 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_14.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_651 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_650 : @[Reg.scala 28:19]
|
|
|
|
|
_T_651 <= gpr_in[15] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[15] <= _T_651 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_652 = bits(gpr_wr_en, 16, 16) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_15 of rvclkhdr_26 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_15.clock <= clock
|
|
|
|
|
rvclkhdr_15.reset <= reset
|
|
|
|
|
rvclkhdr_15.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_15.io.en <= _T_652 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_15.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_653 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_652 : @[Reg.scala 28:19]
|
|
|
|
|
_T_653 <= gpr_in[16] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[16] <= _T_653 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_654 = bits(gpr_wr_en, 17, 17) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_16 of rvclkhdr_27 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_16.clock <= clock
|
|
|
|
|
rvclkhdr_16.reset <= reset
|
|
|
|
|
rvclkhdr_16.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_16.io.en <= _T_654 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_16.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_655 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_654 : @[Reg.scala 28:19]
|
|
|
|
|
_T_655 <= gpr_in[17] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[17] <= _T_655 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_656 = bits(gpr_wr_en, 18, 18) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_17 of rvclkhdr_28 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_17.clock <= clock
|
|
|
|
|
rvclkhdr_17.reset <= reset
|
|
|
|
|
rvclkhdr_17.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_17.io.en <= _T_656 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_17.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_657 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_656 : @[Reg.scala 28:19]
|
|
|
|
|
_T_657 <= gpr_in[18] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[18] <= _T_657 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_658 = bits(gpr_wr_en, 19, 19) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_18 of rvclkhdr_29 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_18.clock <= clock
|
|
|
|
|
rvclkhdr_18.reset <= reset
|
|
|
|
|
rvclkhdr_18.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_18.io.en <= _T_658 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_18.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_659 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_658 : @[Reg.scala 28:19]
|
|
|
|
|
_T_659 <= gpr_in[19] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[19] <= _T_659 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_660 = bits(gpr_wr_en, 20, 20) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_19 of rvclkhdr_30 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_19.clock <= clock
|
|
|
|
|
rvclkhdr_19.reset <= reset
|
|
|
|
|
rvclkhdr_19.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_19.io.en <= _T_660 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_19.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_661 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_660 : @[Reg.scala 28:19]
|
|
|
|
|
_T_661 <= gpr_in[20] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[20] <= _T_661 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_662 = bits(gpr_wr_en, 21, 21) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_20 of rvclkhdr_31 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_20.clock <= clock
|
|
|
|
|
rvclkhdr_20.reset <= reset
|
|
|
|
|
rvclkhdr_20.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_20.io.en <= _T_662 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_20.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_663 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_662 : @[Reg.scala 28:19]
|
|
|
|
|
_T_663 <= gpr_in[21] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[21] <= _T_663 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_664 = bits(gpr_wr_en, 22, 22) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_21 of rvclkhdr_32 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_21.clock <= clock
|
|
|
|
|
rvclkhdr_21.reset <= reset
|
|
|
|
|
rvclkhdr_21.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_21.io.en <= _T_664 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_21.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_665 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_664 : @[Reg.scala 28:19]
|
|
|
|
|
_T_665 <= gpr_in[22] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[22] <= _T_665 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_666 = bits(gpr_wr_en, 23, 23) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_22 of rvclkhdr_33 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_22.clock <= clock
|
|
|
|
|
rvclkhdr_22.reset <= reset
|
|
|
|
|
rvclkhdr_22.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_22.io.en <= _T_666 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_22.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_667 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_666 : @[Reg.scala 28:19]
|
|
|
|
|
_T_667 <= gpr_in[23] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[23] <= _T_667 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_668 = bits(gpr_wr_en, 24, 24) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_23 of rvclkhdr_34 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_23.clock <= clock
|
|
|
|
|
rvclkhdr_23.reset <= reset
|
|
|
|
|
rvclkhdr_23.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_23.io.en <= _T_668 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_23.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_669 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_668 : @[Reg.scala 28:19]
|
|
|
|
|
_T_669 <= gpr_in[24] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[24] <= _T_669 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_670 = bits(gpr_wr_en, 25, 25) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_24 of rvclkhdr_35 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_24.clock <= clock
|
|
|
|
|
rvclkhdr_24.reset <= reset
|
|
|
|
|
rvclkhdr_24.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_24.io.en <= _T_670 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_24.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_671 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_670 : @[Reg.scala 28:19]
|
|
|
|
|
_T_671 <= gpr_in[25] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[25] <= _T_671 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_672 = bits(gpr_wr_en, 26, 26) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_25 of rvclkhdr_36 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_25.clock <= clock
|
|
|
|
|
rvclkhdr_25.reset <= reset
|
|
|
|
|
rvclkhdr_25.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_25.io.en <= _T_672 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_25.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_673 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_672 : @[Reg.scala 28:19]
|
|
|
|
|
_T_673 <= gpr_in[26] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[26] <= _T_673 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_674 = bits(gpr_wr_en, 27, 27) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_26 of rvclkhdr_37 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_26.clock <= clock
|
|
|
|
|
rvclkhdr_26.reset <= reset
|
|
|
|
|
rvclkhdr_26.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_26.io.en <= _T_674 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_26.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_675 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_674 : @[Reg.scala 28:19]
|
|
|
|
|
_T_675 <= gpr_in[27] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[27] <= _T_675 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_676 = bits(gpr_wr_en, 28, 28) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_27 of rvclkhdr_38 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_27.clock <= clock
|
|
|
|
|
rvclkhdr_27.reset <= reset
|
|
|
|
|
rvclkhdr_27.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_27.io.en <= _T_676 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_27.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_677 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_676 : @[Reg.scala 28:19]
|
|
|
|
|
_T_677 <= gpr_in[28] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[28] <= _T_677 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_678 = bits(gpr_wr_en, 29, 29) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_28 of rvclkhdr_39 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_28.clock <= clock
|
|
|
|
|
rvclkhdr_28.reset <= reset
|
|
|
|
|
rvclkhdr_28.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_28.io.en <= _T_678 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_28.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_679 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_678 : @[Reg.scala 28:19]
|
|
|
|
|
_T_679 <= gpr_in[29] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
gpr_out[29] <= _T_679 @[dec_gpr_ctl.scala 61:27]
|
|
|
|
|
node _T_680 = bits(gpr_wr_en, 30, 30) @[dec_gpr_ctl.scala 61:55]
|
|
|
|
|
inst rvclkhdr_29 of rvclkhdr_40 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_29.clock <= clock
|
|
|
|
|
rvclkhdr_29.reset <= reset
|
|
|
|
|
rvclkhdr_29.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_29.io.en <= _T_680 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_29.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_681 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_680 : @[Reg.scala 28:19]
|
|
|
|
|
_T_681 <= gpr_in[30] @[Reg.scala 28:23]
|
|
|
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skip @[Reg.scala 28:19]
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gpr_out[30] <= _T_681 @[dec_gpr_ctl.scala 61:27]
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node _T_682 = bits(gpr_wr_en, 31, 31) @[dec_gpr_ctl.scala 61:55]
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inst rvclkhdr_30 of rvclkhdr_41 @[lib.scala 404:23]
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rvclkhdr_30.clock <= clock
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rvclkhdr_30.reset <= reset
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rvclkhdr_30.io.clk <= clock @[lib.scala 406:18]
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rvclkhdr_30.io.en <= _T_682 @[lib.scala 407:17]
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rvclkhdr_30.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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reg _T_683 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_682 : @[Reg.scala 28:19]
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_T_683 <= gpr_in[31] @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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gpr_out[31] <= _T_683 @[dec_gpr_ctl.scala 61:27]
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node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[dec_gpr_ctl.scala 64:72]
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node _T_685 = bits(_T_684, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[dec_gpr_ctl.scala 64:72]
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node _T_687 = bits(_T_686, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[dec_gpr_ctl.scala 64:72]
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node _T_689 = bits(_T_688, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[dec_gpr_ctl.scala 64:72]
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node _T_691 = bits(_T_690, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[dec_gpr_ctl.scala 64:72]
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node _T_693 = bits(_T_692, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[dec_gpr_ctl.scala 64:72]
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node _T_695 = bits(_T_694, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[dec_gpr_ctl.scala 64:72]
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node _T_697 = bits(_T_696, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[dec_gpr_ctl.scala 64:72]
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node _T_699 = bits(_T_698, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[dec_gpr_ctl.scala 64:72]
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|
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node _T_701 = bits(_T_700, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[dec_gpr_ctl.scala 64:72]
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|
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node _T_703 = bits(_T_702, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[dec_gpr_ctl.scala 64:72]
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node _T_705 = bits(_T_704, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
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node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[dec_gpr_ctl.scala 64:72]
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node _T_707 = bits(_T_706, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
|
node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[dec_gpr_ctl.scala 64:72]
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|
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node _T_709 = bits(_T_708, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[dec_gpr_ctl.scala 64:72]
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node _T_711 = bits(_T_710, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
|
node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[dec_gpr_ctl.scala 64:72]
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|
|
node _T_713 = bits(_T_712, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[dec_gpr_ctl.scala 64:72]
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|
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node _T_715 = bits(_T_714, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[dec_gpr_ctl.scala 64:72]
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|
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node _T_717 = bits(_T_716, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
|
node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[dec_gpr_ctl.scala 64:72]
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|
|
node _T_719 = bits(_T_718, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[dec_gpr_ctl.scala 64:72]
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|
node _T_721 = bits(_T_720, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
|
node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[dec_gpr_ctl.scala 64:72]
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|
|
node _T_723 = bits(_T_722, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
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|
|
node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[dec_gpr_ctl.scala 64:72]
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|
|
node _T_725 = bits(_T_724, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
|
node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[dec_gpr_ctl.scala 64:72]
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|
|
node _T_727 = bits(_T_726, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
|
node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[dec_gpr_ctl.scala 64:72]
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|
|
node _T_729 = bits(_T_728, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
|
node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[dec_gpr_ctl.scala 64:72]
|
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|
|
node _T_731 = bits(_T_730, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
|
node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[dec_gpr_ctl.scala 64:72]
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|
|
node _T_733 = bits(_T_732, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
|
node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[dec_gpr_ctl.scala 64:72]
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|
|
node _T_735 = bits(_T_734, 0, 0) @[dec_gpr_ctl.scala 64:80]
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|
|
node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[dec_gpr_ctl.scala 64:72]
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|
|
node _T_737 = bits(_T_736, 0, 0) @[dec_gpr_ctl.scala 64:80]
|
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|
|
node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[dec_gpr_ctl.scala 64:72]
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|
|
node _T_739 = bits(_T_738, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[dec_gpr_ctl.scala 64:72]
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node _T_741 = bits(_T_740, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[dec_gpr_ctl.scala 64:72]
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node _T_743 = bits(_T_742, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[dec_gpr_ctl.scala 64:72]
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node _T_745 = bits(_T_744, 0, 0) @[dec_gpr_ctl.scala 64:80]
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node _T_746 = mux(_T_685, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_747 = mux(_T_687, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_748 = mux(_T_689, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_749 = mux(_T_691, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_750 = mux(_T_693, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_751 = mux(_T_695, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_752 = mux(_T_697, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_753 = mux(_T_699, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_754 = mux(_T_701, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_755 = mux(_T_703, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_756 = mux(_T_705, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_757 = mux(_T_707, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72]
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|
|
node _T_758 = mux(_T_709, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_759 = mux(_T_711, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_760 = mux(_T_713, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
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node _T_761 = mux(_T_715, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_762 = mux(_T_717, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72]
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|
|
node _T_763 = mux(_T_719, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_764 = mux(_T_721, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_765 = mux(_T_723, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_766 = mux(_T_725, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_767 = mux(_T_727, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_768 = mux(_T_729, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_769 = mux(_T_731, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_770 = mux(_T_733, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_771 = mux(_T_735, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_772 = mux(_T_737, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_773 = mux(_T_739, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_774 = mux(_T_741, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_775 = mux(_T_743, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_776 = mux(_T_745, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72]
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|
|
node _T_777 = or(_T_746, _T_747) @[Mux.scala 27:72]
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|
node _T_778 = or(_T_777, _T_748) @[Mux.scala 27:72]
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|
node _T_779 = or(_T_778, _T_749) @[Mux.scala 27:72]
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node _T_780 = or(_T_779, _T_750) @[Mux.scala 27:72]
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|
node _T_781 = or(_T_780, _T_751) @[Mux.scala 27:72]
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|
node _T_782 = or(_T_781, _T_752) @[Mux.scala 27:72]
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|
node _T_783 = or(_T_782, _T_753) @[Mux.scala 27:72]
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|
node _T_784 = or(_T_783, _T_754) @[Mux.scala 27:72]
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|
node _T_785 = or(_T_784, _T_755) @[Mux.scala 27:72]
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|
node _T_786 = or(_T_785, _T_756) @[Mux.scala 27:72]
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|
node _T_787 = or(_T_786, _T_757) @[Mux.scala 27:72]
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|
node _T_788 = or(_T_787, _T_758) @[Mux.scala 27:72]
|
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|
node _T_789 = or(_T_788, _T_759) @[Mux.scala 27:72]
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|
node _T_790 = or(_T_789, _T_760) @[Mux.scala 27:72]
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|
node _T_791 = or(_T_790, _T_761) @[Mux.scala 27:72]
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|
node _T_792 = or(_T_791, _T_762) @[Mux.scala 27:72]
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node _T_793 = or(_T_792, _T_763) @[Mux.scala 27:72]
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|
node _T_794 = or(_T_793, _T_764) @[Mux.scala 27:72]
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|
node _T_795 = or(_T_794, _T_765) @[Mux.scala 27:72]
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|
node _T_796 = or(_T_795, _T_766) @[Mux.scala 27:72]
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|
node _T_797 = or(_T_796, _T_767) @[Mux.scala 27:72]
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node _T_798 = or(_T_797, _T_768) @[Mux.scala 27:72]
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|
node _T_799 = or(_T_798, _T_769) @[Mux.scala 27:72]
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|
node _T_800 = or(_T_799, _T_770) @[Mux.scala 27:72]
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|
node _T_801 = or(_T_800, _T_771) @[Mux.scala 27:72]
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|
node _T_802 = or(_T_801, _T_772) @[Mux.scala 27:72]
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|
node _T_803 = or(_T_802, _T_773) @[Mux.scala 27:72]
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|
node _T_804 = or(_T_803, _T_774) @[Mux.scala 27:72]
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|
node _T_805 = or(_T_804, _T_775) @[Mux.scala 27:72]
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|
node _T_806 = or(_T_805, _T_776) @[Mux.scala 27:72]
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|
wire _T_807 : UInt<32> @[Mux.scala 27:72]
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|
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|
|
_T_807 <= _T_806 @[Mux.scala 27:72]
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|
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|
|
io.gpr_exu.gpr_i0_rs1_d <= _T_807 @[dec_gpr_ctl.scala 64:32]
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|
|
node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[dec_gpr_ctl.scala 65:72]
|
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|
|
node _T_809 = bits(_T_808, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
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|
|
node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[dec_gpr_ctl.scala 65:72]
|
|
|
|
|
node _T_811 = bits(_T_810, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
|
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|
|
node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[dec_gpr_ctl.scala 65:72]
|
|
|
|
|
node _T_813 = bits(_T_812, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
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|
|
node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[dec_gpr_ctl.scala 65:72]
|
|
|
|
|
node _T_815 = bits(_T_814, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
|
|
|
|
node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[dec_gpr_ctl.scala 65:72]
|
|
|
|
|
node _T_817 = bits(_T_816, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
|
|
|
|
node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[dec_gpr_ctl.scala 65:72]
|
|
|
|
|
node _T_819 = bits(_T_818, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
|
|
|
|
node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[dec_gpr_ctl.scala 65:72]
|
|
|
|
|
node _T_821 = bits(_T_820, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
|
|
|
|
node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[dec_gpr_ctl.scala 65:72]
|
|
|
|
|
node _T_823 = bits(_T_822, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
|
|
|
|
node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[dec_gpr_ctl.scala 65:72]
|
|
|
|
|
node _T_825 = bits(_T_824, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
|
|
|
|
node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[dec_gpr_ctl.scala 65:72]
|
|
|
|
|
node _T_827 = bits(_T_826, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
|
|
|
|
node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[dec_gpr_ctl.scala 65:72]
|
|
|
|
|
node _T_829 = bits(_T_828, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
|
|
|
|
node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[dec_gpr_ctl.scala 65:72]
|
|
|
|
|
node _T_831 = bits(_T_830, 0, 0) @[dec_gpr_ctl.scala 65:80]
|
|
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node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[dec_gpr_ctl.scala 65:72]
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node _T_833 = bits(_T_832, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[dec_gpr_ctl.scala 65:72]
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node _T_835 = bits(_T_834, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[dec_gpr_ctl.scala 65:72]
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node _T_837 = bits(_T_836, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[dec_gpr_ctl.scala 65:72]
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node _T_839 = bits(_T_838, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[dec_gpr_ctl.scala 65:72]
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node _T_841 = bits(_T_840, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[dec_gpr_ctl.scala 65:72]
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node _T_843 = bits(_T_842, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[dec_gpr_ctl.scala 65:72]
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node _T_845 = bits(_T_844, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[dec_gpr_ctl.scala 65:72]
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node _T_847 = bits(_T_846, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[dec_gpr_ctl.scala 65:72]
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node _T_849 = bits(_T_848, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[dec_gpr_ctl.scala 65:72]
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node _T_851 = bits(_T_850, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[dec_gpr_ctl.scala 65:72]
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node _T_853 = bits(_T_852, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[dec_gpr_ctl.scala 65:72]
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node _T_855 = bits(_T_854, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[dec_gpr_ctl.scala 65:72]
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node _T_857 = bits(_T_856, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[dec_gpr_ctl.scala 65:72]
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node _T_859 = bits(_T_858, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[dec_gpr_ctl.scala 65:72]
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node _T_861 = bits(_T_860, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[dec_gpr_ctl.scala 65:72]
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node _T_863 = bits(_T_862, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[dec_gpr_ctl.scala 65:72]
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node _T_865 = bits(_T_864, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[dec_gpr_ctl.scala 65:72]
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node _T_867 = bits(_T_866, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[dec_gpr_ctl.scala 65:72]
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node _T_869 = bits(_T_868, 0, 0) @[dec_gpr_ctl.scala 65:80]
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node _T_870 = mux(_T_809, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_871 = mux(_T_811, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_872 = mux(_T_813, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_873 = mux(_T_815, gpr_out[4], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_874 = mux(_T_817, gpr_out[5], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_875 = mux(_T_819, gpr_out[6], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_876 = mux(_T_821, gpr_out[7], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_877 = mux(_T_823, gpr_out[8], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_878 = mux(_T_825, gpr_out[9], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_879 = mux(_T_827, gpr_out[10], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_880 = mux(_T_829, gpr_out[11], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_881 = mux(_T_831, gpr_out[12], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_882 = mux(_T_833, gpr_out[13], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_883 = mux(_T_835, gpr_out[14], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_884 = mux(_T_837, gpr_out[15], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_885 = mux(_T_839, gpr_out[16], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_886 = mux(_T_841, gpr_out[17], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_887 = mux(_T_843, gpr_out[18], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_888 = mux(_T_845, gpr_out[19], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_889 = mux(_T_847, gpr_out[20], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_890 = mux(_T_849, gpr_out[21], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_891 = mux(_T_851, gpr_out[22], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_892 = mux(_T_853, gpr_out[23], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_893 = mux(_T_855, gpr_out[24], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_894 = mux(_T_857, gpr_out[25], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_895 = mux(_T_859, gpr_out[26], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_896 = mux(_T_861, gpr_out[27], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_897 = mux(_T_863, gpr_out[28], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_898 = mux(_T_865, gpr_out[29], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_899 = mux(_T_867, gpr_out[30], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_900 = mux(_T_869, gpr_out[31], UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_901 = or(_T_870, _T_871) @[Mux.scala 27:72]
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node _T_902 = or(_T_901, _T_872) @[Mux.scala 27:72]
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node _T_903 = or(_T_902, _T_873) @[Mux.scala 27:72]
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node _T_904 = or(_T_903, _T_874) @[Mux.scala 27:72]
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node _T_905 = or(_T_904, _T_875) @[Mux.scala 27:72]
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node _T_906 = or(_T_905, _T_876) @[Mux.scala 27:72]
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node _T_907 = or(_T_906, _T_877) @[Mux.scala 27:72]
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node _T_908 = or(_T_907, _T_878) @[Mux.scala 27:72]
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node _T_909 = or(_T_908, _T_879) @[Mux.scala 27:72]
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node _T_910 = or(_T_909, _T_880) @[Mux.scala 27:72]
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node _T_911 = or(_T_910, _T_881) @[Mux.scala 27:72]
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node _T_912 = or(_T_911, _T_882) @[Mux.scala 27:72]
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node _T_913 = or(_T_912, _T_883) @[Mux.scala 27:72]
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node _T_914 = or(_T_913, _T_884) @[Mux.scala 27:72]
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node _T_915 = or(_T_914, _T_885) @[Mux.scala 27:72]
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node _T_916 = or(_T_915, _T_886) @[Mux.scala 27:72]
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node _T_917 = or(_T_916, _T_887) @[Mux.scala 27:72]
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node _T_918 = or(_T_917, _T_888) @[Mux.scala 27:72]
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node _T_919 = or(_T_918, _T_889) @[Mux.scala 27:72]
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node _T_920 = or(_T_919, _T_890) @[Mux.scala 27:72]
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node _T_921 = or(_T_920, _T_891) @[Mux.scala 27:72]
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node _T_922 = or(_T_921, _T_892) @[Mux.scala 27:72]
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node _T_923 = or(_T_922, _T_893) @[Mux.scala 27:72]
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node _T_924 = or(_T_923, _T_894) @[Mux.scala 27:72]
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node _T_925 = or(_T_924, _T_895) @[Mux.scala 27:72]
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node _T_926 = or(_T_925, _T_896) @[Mux.scala 27:72]
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node _T_927 = or(_T_926, _T_897) @[Mux.scala 27:72]
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node _T_928 = or(_T_927, _T_898) @[Mux.scala 27:72]
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node _T_929 = or(_T_928, _T_899) @[Mux.scala 27:72]
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node _T_930 = or(_T_929, _T_900) @[Mux.scala 27:72]
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wire _T_931 : UInt<32> @[Mux.scala 27:72]
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_T_931 <= _T_930 @[Mux.scala 27:72]
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io.gpr_exu.gpr_i0_rs2_d <= _T_931 @[dec_gpr_ctl.scala 65:32]
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module int_exc :
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input clock : Clock
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input reset : AsyncReset
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output io : {mhwakeup_ready : UInt<1>, ext_int_ready : UInt<1>, ce_int_ready : UInt<1>, soft_int_ready : UInt<1>, timer_int_ready : UInt<1>, int_timer0_int_hold : UInt<1>, int_timer1_int_hold : UInt<1>, internal_dbg_halt_timers : UInt<1>, take_ext_int_start : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip take_ext_int_start_d1 : UInt<1>, flip take_ext_int_start_d2 : UInt<1>, flip take_ext_int_start_d3 : UInt<1>, ext_int_freeze : UInt<1>, take_ext_int : UInt<1>, fast_int_meicpct : UInt<1>, ignore_ext_int_due_to_lsu_stall : UInt<1>, take_ce_int : UInt<1>, take_soft_int : UInt<1>, take_timer_int : UInt<1>, take_int_timer0_int : UInt<1>, take_int_timer1_int : UInt<1>, take_reset : UInt<1>, take_nmi : UInt<1>, synchronous_flush_r : UInt<1>, tlu_flush_lower_r : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, interrupt_valid_r_d1 : UInt<1>, i0_exception_valid_r_d1 : UInt<1>, exc_or_int_valid_r_d1 : UInt<1>, exc_cause_wb : UInt<5>, i0_valid_wb : UInt<1>, trigger_hit_r_d1 : UInt<1>, take_nmi_r_d1 : UInt<1>, pause_expired_wb : UInt<1>, interrupt_valid_r : UInt<1>, exc_cause_r : UInt<5>, i0_exception_valid_r : UInt<1>, tlu_flush_path_r_d1 : UInt<31>, exc_or_int_valid_r : UInt<1>, flip free_l2clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip mstatus_mie_ns : UInt<1>, flip mip : UInt<6>, flip mie_ns : UInt<6>, flip mret_r : UInt<1>, flip pmu_fw_tlu_halted_f : UInt<1>, flip int_timer0_int_hold_f : UInt<1>, flip int_timer1_int_hold_f : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip dcsr_single_step_running : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip internal_pmu_fw_halt_mode : UInt<1>, flip i_cpu_halt_req_d1 : UInt<1>, flip ebreak_to_debug_mode_r : UInt<1>, flip lsu_fir_error : UInt<2>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_meicpct : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, flip dec_csr_any_unq_d : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip reset_delayed : UInt<1>, flip mpc_reset_run_req : UInt<1>, flip nmi_int_detected : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip dcsr : UInt<16>, flip mtvec : UInt<31>, flip tlu_i0_commit_cmt : UInt<1>, flip i0_trigger_hit_r : UInt<1>, flip pause_expired_r : UInt<1>, flip nmi_vec : UInt<31>, flip lsu_i0_rfnpc_r : UInt<1>, flip fence_i_r : UInt<1>, flip iccm_repair_state_rfnpc : UInt<1>, flip i_cpu_run_req_d1 : UInt<1>, flip rfpc_i0_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip trigger_hit_dmode_r : UInt<1>, flip take_halt : UInt<1>, flip rst_vec : UInt<31>, flip lsu_fir_addr : UInt<31>, flip dec_tlu_i0_pc_r : U
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node _T = eq(io.lsu_error_pkt_r.bits.exc_type, UInt<1>("h00")) @[dec_tlu_ctl.scala 3017:48]
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node lsu_exc_ma_r = and(io.lsu_i0_exc_r, _T) @[dec_tlu_ctl.scala 3017:46]
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node lsu_exc_acc_r = and(io.lsu_i0_exc_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 3018:46]
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node lsu_exc_st_r = and(io.lsu_i0_exc_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 3019:46]
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node _T_1 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 3031:49]
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node _T_2 = or(_T_1, io.illegal_r) @[dec_tlu_ctl.scala 3031:62]
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node _T_3 = or(_T_2, io.inst_acc_r) @[dec_tlu_ctl.scala 3031:77]
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node _T_4 = not(io.rfpc_i0_r) @[dec_tlu_ctl.scala 3031:96]
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node _T_5 = and(_T_3, _T_4) @[dec_tlu_ctl.scala 3031:94]
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node _T_6 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 3031:112]
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node _T_7 = and(_T_5, _T_6) @[dec_tlu_ctl.scala 3031:110]
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io.i0_exception_valid_r <= _T_7 @[dec_tlu_ctl.scala 3031:33]
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node _T_8 = bits(io.take_nmi, 0, 0) @[Bitwise.scala 72:15]
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node _T_9 = mux(_T_8, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
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node _T_10 = not(_T_9) @[dec_tlu_ctl.scala 3039:27]
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node _T_11 = bits(io.take_ext_int, 0, 0) @[dec_tlu_ctl.scala 3040:35]
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node _T_12 = bits(io.take_timer_int, 0, 0) @[dec_tlu_ctl.scala 3041:38]
|
|
|
|
|
node _T_13 = bits(io.take_soft_int, 0, 0) @[dec_tlu_ctl.scala 3042:36]
|
|
|
|
|
node _T_14 = bits(io.take_int_timer0_int, 0, 0) @[dec_tlu_ctl.scala 3043:43]
|
|
|
|
|
node _T_15 = bits(io.take_int_timer1_int, 0, 0) @[dec_tlu_ctl.scala 3044:42]
|
|
|
|
|
node _T_16 = bits(io.take_ce_int, 0, 0) @[dec_tlu_ctl.scala 3045:34]
|
|
|
|
|
node _T_17 = bits(io.illegal_r, 0, 0) @[dec_tlu_ctl.scala 3046:32]
|
|
|
|
|
node _T_18 = bits(io.ecall_r, 0, 0) @[dec_tlu_ctl.scala 3047:30]
|
|
|
|
|
node _T_19 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 3048:34]
|
|
|
|
|
node _T_20 = or(io.ebreak_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 3049:31]
|
|
|
|
|
node _T_21 = bits(_T_20, 0, 0) @[dec_tlu_ctl.scala 3049:55]
|
|
|
|
|
node _T_22 = eq(lsu_exc_st_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3050:33]
|
|
|
|
|
node _T_23 = and(lsu_exc_ma_r, _T_22) @[dec_tlu_ctl.scala 3050:31]
|
|
|
|
|
node _T_24 = bits(_T_23, 0, 0) @[dec_tlu_ctl.scala 3050:48]
|
|
|
|
|
node _T_25 = eq(lsu_exc_st_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3051:34]
|
|
|
|
|
node _T_26 = and(lsu_exc_acc_r, _T_25) @[dec_tlu_ctl.scala 3051:32]
|
|
|
|
|
node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 3051:49]
|
|
|
|
|
node _T_28 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 3052:31]
|
|
|
|
|
node _T_29 = bits(_T_28, 0, 0) @[dec_tlu_ctl.scala 3052:48]
|
|
|
|
|
node _T_30 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 3053:32]
|
|
|
|
|
node _T_31 = bits(_T_30, 0, 0) @[dec_tlu_ctl.scala 3053:49]
|
|
|
|
|
node _T_32 = mux(_T_11, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_33 = mux(_T_12, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_34 = mux(_T_13, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_35 = mux(_T_14, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_36 = mux(_T_15, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_37 = mux(_T_16, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_38 = mux(_T_17, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_39 = mux(_T_18, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_40 = mux(_T_19, UInt<5>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_41 = mux(_T_21, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_42 = mux(_T_24, UInt<5>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_43 = mux(_T_27, UInt<5>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_44 = mux(_T_29, UInt<5>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_45 = mux(_T_31, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_46 = or(_T_32, _T_33) @[Mux.scala 27:72]
|
|
|
|
|
node _T_47 = or(_T_46, _T_34) @[Mux.scala 27:72]
|
|
|
|
|
node _T_48 = or(_T_47, _T_35) @[Mux.scala 27:72]
|
|
|
|
|
node _T_49 = or(_T_48, _T_36) @[Mux.scala 27:72]
|
|
|
|
|
node _T_50 = or(_T_49, _T_37) @[Mux.scala 27:72]
|
|
|
|
|
node _T_51 = or(_T_50, _T_38) @[Mux.scala 27:72]
|
|
|
|
|
node _T_52 = or(_T_51, _T_39) @[Mux.scala 27:72]
|
|
|
|
|
node _T_53 = or(_T_52, _T_40) @[Mux.scala 27:72]
|
|
|
|
|
node _T_54 = or(_T_53, _T_41) @[Mux.scala 27:72]
|
|
|
|
|
node _T_55 = or(_T_54, _T_42) @[Mux.scala 27:72]
|
|
|
|
|
node _T_56 = or(_T_55, _T_43) @[Mux.scala 27:72]
|
|
|
|
|
node _T_57 = or(_T_56, _T_44) @[Mux.scala 27:72]
|
|
|
|
|
node _T_58 = or(_T_57, _T_45) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_59 : UInt<5> @[Mux.scala 27:72]
|
|
|
|
|
_T_59 <= _T_58 @[Mux.scala 27:72]
|
|
|
|
|
node _T_60 = and(_T_10, _T_59) @[dec_tlu_ctl.scala 3039:48]
|
|
|
|
|
io.exc_cause_r <= _T_60 @[dec_tlu_ctl.scala 3039:24]
|
|
|
|
|
node _T_61 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3064:31]
|
|
|
|
|
node _T_62 = and(_T_61, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3064:56]
|
|
|
|
|
node _T_63 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 3064:84]
|
|
|
|
|
node _T_64 = and(_T_62, _T_63) @[dec_tlu_ctl.scala 3064:76]
|
|
|
|
|
node _T_65 = bits(io.mie_ns, 2, 2) @[dec_tlu_ctl.scala 3064:108]
|
|
|
|
|
node _T_66 = and(_T_64, _T_65) @[dec_tlu_ctl.scala 3064:97]
|
|
|
|
|
io.mhwakeup_ready <= _T_66 @[dec_tlu_ctl.scala 3064:28]
|
|
|
|
|
node _T_67 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3065:31]
|
|
|
|
|
node _T_68 = and(_T_67, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3065:56]
|
|
|
|
|
node _T_69 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 3065:84]
|
|
|
|
|
node _T_70 = and(_T_68, _T_69) @[dec_tlu_ctl.scala 3065:76]
|
|
|
|
|
node _T_71 = bits(io.mie_ns, 2, 2) @[dec_tlu_ctl.scala 3065:108]
|
|
|
|
|
node _T_72 = and(_T_70, _T_71) @[dec_tlu_ctl.scala 3065:97]
|
|
|
|
|
node _T_73 = not(io.ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 3065:121]
|
|
|
|
|
node _T_74 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 3065:119]
|
|
|
|
|
io.ext_int_ready <= _T_74 @[dec_tlu_ctl.scala 3065:28]
|
|
|
|
|
node _T_75 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3066:31]
|
|
|
|
|
node _T_76 = and(_T_75, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3066:56]
|
|
|
|
|
node _T_77 = dshr(io.mip, UInt<3>("h05")) @[dec_tlu_ctl.scala 3066:84]
|
|
|
|
|
node _T_78 = bits(_T_77, 0, 0) @[dec_tlu_ctl.scala 3066:84]
|
|
|
|
|
node _T_79 = and(_T_76, _T_78) @[dec_tlu_ctl.scala 3066:76]
|
|
|
|
|
node _T_80 = bits(io.mie_ns, 5, 5) @[dec_tlu_ctl.scala 3066:108]
|
|
|
|
|
node _T_81 = and(_T_79, _T_80) @[dec_tlu_ctl.scala 3066:97]
|
|
|
|
|
io.ce_int_ready <= _T_81 @[dec_tlu_ctl.scala 3066:28]
|
|
|
|
|
node _T_82 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3067:31]
|
|
|
|
|
node _T_83 = and(_T_82, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3067:56]
|
|
|
|
|
node _T_84 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 3067:84]
|
|
|
|
|
node _T_85 = and(_T_83, _T_84) @[dec_tlu_ctl.scala 3067:76]
|
|
|
|
|
node _T_86 = bits(io.mie_ns, 0, 0) @[dec_tlu_ctl.scala 3067:108]
|
|
|
|
|
node _T_87 = and(_T_85, _T_86) @[dec_tlu_ctl.scala 3067:97]
|
|
|
|
|
io.soft_int_ready <= _T_87 @[dec_tlu_ctl.scala 3067:28]
|
|
|
|
|
node _T_88 = eq(io.dec_csr_stall_int_ff, UInt<1>("h00")) @[dec_tlu_ctl.scala 3068:31]
|
|
|
|
|
node _T_89 = and(_T_88, io.mstatus_mie_ns) @[dec_tlu_ctl.scala 3068:56]
|
|
|
|
|
node _T_90 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 3068:84]
|
|
|
|
|
node _T_91 = and(_T_89, _T_90) @[dec_tlu_ctl.scala 3068:76]
|
|
|
|
|
node _T_92 = bits(io.mie_ns, 1, 1) @[dec_tlu_ctl.scala 3068:108]
|
|
|
|
|
node _T_93 = and(_T_91, _T_92) @[dec_tlu_ctl.scala 3068:97]
|
|
|
|
|
io.timer_int_ready <= _T_93 @[dec_tlu_ctl.scala 3068:28]
|
|
|
|
|
node _T_94 = bits(io.mie_ns, 4, 4) @[dec_tlu_ctl.scala 3071:68]
|
|
|
|
|
node int_timer0_int_possible = and(io.mstatus_mie_ns, _T_94) @[dec_tlu_ctl.scala 3071:57]
|
|
|
|
|
node _T_95 = dshr(io.mip, UInt<3>("h04")) @[dec_tlu_ctl.scala 3072:42]
|
|
|
|
|
node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 3072:42]
|
|
|
|
|
node int_timer0_int_ready = and(_T_96, int_timer0_int_possible) @[dec_tlu_ctl.scala 3072:55]
|
|
|
|
|
node _T_97 = bits(io.mie_ns, 3, 3) @[dec_tlu_ctl.scala 3073:68]
|
|
|
|
|
node int_timer1_int_possible = and(io.mstatus_mie_ns, _T_97) @[dec_tlu_ctl.scala 3073:57]
|
|
|
|
|
node _T_98 = dshr(io.mip, UInt<2>("h03")) @[dec_tlu_ctl.scala 3074:42]
|
|
|
|
|
node _T_99 = bits(_T_98, 0, 0) @[dec_tlu_ctl.scala 3074:42]
|
|
|
|
|
node int_timer1_int_ready = and(_T_99, int_timer1_int_possible) @[dec_tlu_ctl.scala 3074:55]
|
|
|
|
|
node _T_100 = or(io.dec_csr_stall_int_ff, io.synchronous_flush_r) @[dec_tlu_ctl.scala 3078:57]
|
|
|
|
|
node _T_101 = or(_T_100, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 3078:82]
|
|
|
|
|
node int_timer_stalled = or(_T_101, io.mret_r) @[dec_tlu_ctl.scala 3078:109]
|
|
|
|
|
node _T_102 = or(io.pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 3080:83]
|
|
|
|
|
node _T_103 = and(int_timer0_int_ready, _T_102) @[dec_tlu_ctl.scala 3080:57]
|
|
|
|
|
node _T_104 = and(int_timer0_int_possible, io.int_timer0_int_hold_f) @[dec_tlu_ctl.scala 3080:132]
|
|
|
|
|
node _T_105 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3080:161]
|
|
|
|
|
node _T_106 = and(_T_104, _T_105) @[dec_tlu_ctl.scala 3080:159]
|
|
|
|
|
node _T_107 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 3080:185]
|
|
|
|
|
node _T_108 = and(_T_106, _T_107) @[dec_tlu_ctl.scala 3080:183]
|
|
|
|
|
node _T_109 = not(io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 3080:210]
|
|
|
|
|
node _T_110 = and(_T_108, _T_109) @[dec_tlu_ctl.scala 3080:208]
|
|
|
|
|
node _T_111 = or(_T_103, _T_110) @[dec_tlu_ctl.scala 3080:105]
|
|
|
|
|
io.int_timer0_int_hold <= _T_111 @[dec_tlu_ctl.scala 3080:32]
|
|
|
|
|
node _T_112 = or(io.pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 3081:83]
|
|
|
|
|
node _T_113 = and(int_timer1_int_ready, _T_112) @[dec_tlu_ctl.scala 3081:57]
|
|
|
|
|
node _T_114 = and(int_timer1_int_possible, io.int_timer1_int_hold_f) @[dec_tlu_ctl.scala 3081:132]
|
|
|
|
|
node _T_115 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3081:161]
|
|
|
|
|
node _T_116 = and(_T_114, _T_115) @[dec_tlu_ctl.scala 3081:159]
|
|
|
|
|
node _T_117 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 3081:185]
|
|
|
|
|
node _T_118 = and(_T_116, _T_117) @[dec_tlu_ctl.scala 3081:183]
|
|
|
|
|
node _T_119 = not(io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 3081:210]
|
|
|
|
|
node _T_120 = and(_T_118, _T_119) @[dec_tlu_ctl.scala 3081:208]
|
|
|
|
|
node _T_121 = or(_T_113, _T_120) @[dec_tlu_ctl.scala 3081:105]
|
|
|
|
|
io.int_timer1_int_hold <= _T_121 @[dec_tlu_ctl.scala 3081:32]
|
|
|
|
|
node _T_122 = not(io.dcsr_single_step_running) @[dec_tlu_ctl.scala 3083:70]
|
|
|
|
|
node _T_123 = and(io.internal_dbg_halt_mode_f, _T_122) @[dec_tlu_ctl.scala 3083:68]
|
|
|
|
|
io.internal_dbg_halt_timers <= _T_123 @[dec_tlu_ctl.scala 3083:37]
|
|
|
|
|
node _T_124 = not(io.dcsr_single_step_running) @[dec_tlu_ctl.scala 3085:63]
|
|
|
|
|
node _T_125 = or(_T_124, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 3085:92]
|
|
|
|
|
node _T_126 = and(io.internal_dbg_halt_mode, _T_125) @[dec_tlu_ctl.scala 3085:60]
|
|
|
|
|
node _T_127 = or(_T_126, io.internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 3085:118]
|
|
|
|
|
node _T_128 = or(_T_127, io.i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 3085:149]
|
|
|
|
|
node _T_129 = or(_T_128, io.take_nmi) @[dec_tlu_ctl.scala 3085:172]
|
|
|
|
|
node _T_130 = or(_T_129, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 3085:186]
|
|
|
|
|
node _T_131 = or(_T_130, io.synchronous_flush_r) @[dec_tlu_ctl.scala 3085:214]
|
|
|
|
|
node _T_132 = or(_T_131, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 3085:240]
|
|
|
|
|
node _T_133 = or(_T_132, io.mret_r) @[dec_tlu_ctl.scala 3085:267]
|
|
|
|
|
node block_interrupts = or(_T_133, io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 3085:279]
|
|
|
|
|
node _T_134 = not(block_interrupts) @[dec_tlu_ctl.scala 3093:61]
|
|
|
|
|
node _T_135 = and(io.ext_int_ready, _T_134) @[dec_tlu_ctl.scala 3093:59]
|
|
|
|
|
io.take_ext_int_start <= _T_135 @[dec_tlu_ctl.scala 3093:39]
|
|
|
|
|
node _T_136 = or(io.take_ext_int_start, io.take_ext_int_start_d1) @[dec_tlu_ctl.scala 3094:60]
|
|
|
|
|
node _T_137 = or(_T_136, io.take_ext_int_start_d2) @[dec_tlu_ctl.scala 3094:87]
|
|
|
|
|
node _T_138 = or(_T_137, io.take_ext_int_start_d3) @[dec_tlu_ctl.scala 3094:114]
|
|
|
|
|
io.ext_int_freeze <= _T_138 @[dec_tlu_ctl.scala 3094:35]
|
|
|
|
|
node _T_139 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 3095:81]
|
|
|
|
|
node _T_140 = not(_T_139) @[dec_tlu_ctl.scala 3095:63]
|
|
|
|
|
node _T_141 = and(io.take_ext_int_start_d3, _T_140) @[dec_tlu_ctl.scala 3095:61]
|
|
|
|
|
io.take_ext_int <= _T_141 @[dec_tlu_ctl.scala 3095:33]
|
|
|
|
|
node _T_142 = and(io.csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 3096:63]
|
|
|
|
|
io.fast_int_meicpct <= _T_142 @[dec_tlu_ctl.scala 3096:37]
|
|
|
|
|
io.ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 3097:52]
|
|
|
|
|
node _T_143 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3110:46]
|
|
|
|
|
node _T_144 = and(io.ce_int_ready, _T_143) @[dec_tlu_ctl.scala 3110:44]
|
|
|
|
|
node _T_145 = not(block_interrupts) @[dec_tlu_ctl.scala 3110:66]
|
|
|
|
|
node _T_146 = and(_T_144, _T_145) @[dec_tlu_ctl.scala 3110:64]
|
|
|
|
|
io.take_ce_int <= _T_146 @[dec_tlu_ctl.scala 3110:25]
|
|
|
|
|
node _T_147 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3111:49]
|
|
|
|
|
node _T_148 = and(io.soft_int_ready, _T_147) @[dec_tlu_ctl.scala 3111:47]
|
|
|
|
|
node _T_149 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3111:69]
|
|
|
|
|
node _T_150 = and(_T_148, _T_149) @[dec_tlu_ctl.scala 3111:67]
|
|
|
|
|
node _T_151 = not(block_interrupts) @[dec_tlu_ctl.scala 3111:88]
|
|
|
|
|
node _T_152 = and(_T_150, _T_151) @[dec_tlu_ctl.scala 3111:86]
|
|
|
|
|
io.take_soft_int <= _T_152 @[dec_tlu_ctl.scala 3111:26]
|
|
|
|
|
node _T_153 = not(io.soft_int_ready) @[dec_tlu_ctl.scala 3112:51]
|
|
|
|
|
node _T_154 = and(io.timer_int_ready, _T_153) @[dec_tlu_ctl.scala 3112:49]
|
|
|
|
|
node _T_155 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3112:72]
|
|
|
|
|
node _T_156 = and(_T_154, _T_155) @[dec_tlu_ctl.scala 3112:70]
|
|
|
|
|
node _T_157 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3112:92]
|
|
|
|
|
node _T_158 = and(_T_156, _T_157) @[dec_tlu_ctl.scala 3112:90]
|
|
|
|
|
node _T_159 = not(block_interrupts) @[dec_tlu_ctl.scala 3112:111]
|
|
|
|
|
node _T_160 = and(_T_158, _T_159) @[dec_tlu_ctl.scala 3112:109]
|
|
|
|
|
io.take_timer_int <= _T_160 @[dec_tlu_ctl.scala 3112:27]
|
|
|
|
|
node _T_161 = or(int_timer0_int_ready, io.int_timer0_int_hold_f) @[dec_tlu_ctl.scala 3113:57]
|
|
|
|
|
node _T_162 = and(_T_161, int_timer0_int_possible) @[dec_tlu_ctl.scala 3113:85]
|
|
|
|
|
node _T_163 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 3113:113]
|
|
|
|
|
node _T_164 = and(_T_162, _T_163) @[dec_tlu_ctl.scala 3113:111]
|
|
|
|
|
node _T_165 = not(io.timer_int_ready) @[dec_tlu_ctl.scala 3113:140]
|
|
|
|
|
node _T_166 = and(_T_164, _T_165) @[dec_tlu_ctl.scala 3113:138]
|
|
|
|
|
node _T_167 = not(io.soft_int_ready) @[dec_tlu_ctl.scala 3113:162]
|
|
|
|
|
node _T_168 = and(_T_166, _T_167) @[dec_tlu_ctl.scala 3113:160]
|
|
|
|
|
node _T_169 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3113:183]
|
|
|
|
|
node _T_170 = and(_T_168, _T_169) @[dec_tlu_ctl.scala 3113:181]
|
|
|
|
|
node _T_171 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3113:203]
|
|
|
|
|
node _T_172 = and(_T_170, _T_171) @[dec_tlu_ctl.scala 3113:201]
|
|
|
|
|
node _T_173 = not(block_interrupts) @[dec_tlu_ctl.scala 3113:222]
|
|
|
|
|
node _T_174 = and(_T_172, _T_173) @[dec_tlu_ctl.scala 3113:220]
|
|
|
|
|
io.take_int_timer0_int <= _T_174 @[dec_tlu_ctl.scala 3113:32]
|
|
|
|
|
node _T_175 = or(int_timer1_int_ready, io.int_timer1_int_hold_f) @[dec_tlu_ctl.scala 3114:57]
|
|
|
|
|
node _T_176 = and(_T_175, int_timer1_int_possible) @[dec_tlu_ctl.scala 3114:85]
|
|
|
|
|
node _T_177 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 3114:113]
|
|
|
|
|
node _T_178 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 3114:111]
|
|
|
|
|
node _T_179 = or(int_timer0_int_ready, io.int_timer0_int_hold_f) @[dec_tlu_ctl.scala 3114:163]
|
|
|
|
|
node _T_180 = not(_T_179) @[dec_tlu_ctl.scala 3114:140]
|
|
|
|
|
node _T_181 = and(_T_178, _T_180) @[dec_tlu_ctl.scala 3114:138]
|
|
|
|
|
node _T_182 = not(io.timer_int_ready) @[dec_tlu_ctl.scala 3114:193]
|
|
|
|
|
node _T_183 = and(_T_181, _T_182) @[dec_tlu_ctl.scala 3114:191]
|
|
|
|
|
node _T_184 = not(io.soft_int_ready) @[dec_tlu_ctl.scala 3114:215]
|
|
|
|
|
node _T_185 = and(_T_183, _T_184) @[dec_tlu_ctl.scala 3114:213]
|
|
|
|
|
node _T_186 = not(io.ext_int_ready) @[dec_tlu_ctl.scala 3114:236]
|
|
|
|
|
node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 3114:234]
|
|
|
|
|
node _T_188 = not(io.ce_int_ready) @[dec_tlu_ctl.scala 3114:256]
|
|
|
|
|
node _T_189 = and(_T_187, _T_188) @[dec_tlu_ctl.scala 3114:254]
|
|
|
|
|
node _T_190 = not(block_interrupts) @[dec_tlu_ctl.scala 3114:275]
|
|
|
|
|
node _T_191 = and(_T_189, _T_190) @[dec_tlu_ctl.scala 3114:273]
|
|
|
|
|
io.take_int_timer1_int <= _T_191 @[dec_tlu_ctl.scala 3114:32]
|
|
|
|
|
node _T_192 = and(io.reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 3115:43]
|
|
|
|
|
io.take_reset <= _T_192 @[dec_tlu_ctl.scala 3115:23]
|
|
|
|
|
node _T_193 = not(io.internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 3116:46]
|
|
|
|
|
node _T_194 = and(io.nmi_int_detected, _T_193) @[dec_tlu_ctl.scala 3116:44]
|
|
|
|
|
node _T_195 = not(io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 3116:79]
|
|
|
|
|
node _T_196 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 3116:148]
|
|
|
|
|
node _T_197 = and(io.dcsr_single_step_running_f, _T_196) @[dec_tlu_ctl.scala 3116:139]
|
|
|
|
|
node _T_198 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 3116:164]
|
|
|
|
|
node _T_199 = and(_T_197, _T_198) @[dec_tlu_ctl.scala 3116:162]
|
|
|
|
|
node _T_200 = not(io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 3116:189]
|
|
|
|
|
node _T_201 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 3116:187]
|
|
|
|
|
node _T_202 = or(_T_195, _T_201) @[dec_tlu_ctl.scala 3116:106]
|
|
|
|
|
node _T_203 = and(_T_194, _T_202) @[dec_tlu_ctl.scala 3116:76]
|
|
|
|
|
node _T_204 = not(io.synchronous_flush_r) @[dec_tlu_ctl.scala 3116:220]
|
|
|
|
|
node _T_205 = and(_T_203, _T_204) @[dec_tlu_ctl.scala 3116:218]
|
|
|
|
|
node _T_206 = not(io.mret_r) @[dec_tlu_ctl.scala 3116:246]
|
|
|
|
|
node _T_207 = and(_T_205, _T_206) @[dec_tlu_ctl.scala 3116:244]
|
|
|
|
|
node _T_208 = not(io.take_reset) @[dec_tlu_ctl.scala 3116:259]
|
|
|
|
|
node _T_209 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 3116:257]
|
|
|
|
|
node _T_210 = not(io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 3116:276]
|
|
|
|
|
node _T_211 = and(_T_209, _T_210) @[dec_tlu_ctl.scala 3116:274]
|
|
|
|
|
node _T_212 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 3116:306]
|
|
|
|
|
node _T_213 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 3116:375]
|
|
|
|
|
node _T_214 = and(io.take_ext_int_start_d3, _T_213) @[dec_tlu_ctl.scala 3116:356]
|
|
|
|
|
node _T_215 = or(_T_212, _T_214) @[dec_tlu_ctl.scala 3116:328]
|
|
|
|
|
node _T_216 = and(_T_211, _T_215) @[dec_tlu_ctl.scala 3116:303]
|
|
|
|
|
io.take_nmi <= _T_216 @[dec_tlu_ctl.scala 3116:21]
|
|
|
|
|
node _T_217 = or(io.take_ext_int, io.take_timer_int) @[dec_tlu_ctl.scala 3120:49]
|
|
|
|
|
node _T_218 = or(_T_217, io.take_soft_int) @[dec_tlu_ctl.scala 3120:69]
|
|
|
|
|
node _T_219 = or(_T_218, io.take_nmi) @[dec_tlu_ctl.scala 3120:88]
|
|
|
|
|
node _T_220 = or(_T_219, io.take_ce_int) @[dec_tlu_ctl.scala 3120:102]
|
|
|
|
|
node _T_221 = or(_T_220, io.take_int_timer0_int) @[dec_tlu_ctl.scala 3120:119]
|
|
|
|
|
node _T_222 = or(_T_221, io.take_int_timer1_int) @[dec_tlu_ctl.scala 3120:144]
|
|
|
|
|
io.interrupt_valid_r <= _T_222 @[dec_tlu_ctl.scala 3120:30]
|
|
|
|
|
node _T_223 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 3125:42]
|
|
|
|
|
node _T_224 = cat(_T_223, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_225 = cat(UInt<25>("h00"), io.exc_cause_r) @[Cat.scala 29:58]
|
|
|
|
|
node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_227 = add(_T_224, _T_226) @[dec_tlu_ctl.scala 3125:59]
|
|
|
|
|
node vectored_path = tail(_T_227, 1) @[dec_tlu_ctl.scala 3125:59]
|
|
|
|
|
node _T_228 = bits(io.take_nmi, 0, 0) @[dec_tlu_ctl.scala 3126:46]
|
|
|
|
|
node _T_229 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 3126:78]
|
|
|
|
|
node _T_230 = eq(_T_229, UInt<1>("h01")) @[dec_tlu_ctl.scala 3126:82]
|
|
|
|
|
node _T_231 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 3126:118]
|
|
|
|
|
node _T_232 = cat(_T_231, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_233 = mux(_T_230, vectored_path, _T_232) @[dec_tlu_ctl.scala 3126:69]
|
|
|
|
|
node interrupt_path = mux(_T_228, io.nmi_vec, _T_233) @[dec_tlu_ctl.scala 3126:33]
|
|
|
|
|
node _T_234 = or(io.lsu_i0_rfnpc_r, io.fence_i_r) @[dec_tlu_ctl.scala 3127:44]
|
|
|
|
|
node _T_235 = or(_T_234, io.iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 3127:59]
|
|
|
|
|
node _T_236 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3127:113]
|
|
|
|
|
node _T_237 = and(io.i_cpu_run_req_d1, _T_236) @[dec_tlu_ctl.scala 3127:111]
|
|
|
|
|
node _T_238 = or(_T_235, _T_237) @[dec_tlu_ctl.scala 3127:88]
|
|
|
|
|
node _T_239 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 3127:154]
|
|
|
|
|
node _T_240 = and(io.rfpc_i0_r, _T_239) @[dec_tlu_ctl.scala 3127:152]
|
|
|
|
|
node sel_npc_r = or(_T_238, _T_240) @[dec_tlu_ctl.scala 3127:136]
|
|
|
|
|
node _T_241 = and(io.i_cpu_run_req_d1, io.pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 3128:51]
|
|
|
|
|
node sel_npc_resume = or(_T_241, io.pause_expired_r) @[dec_tlu_ctl.scala 3128:77]
|
|
|
|
|
node _T_242 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 3129:74]
|
|
|
|
|
node _T_243 = eq(_T_242, UInt<1>("h00")) @[dec_tlu_ctl.scala 3129:55]
|
|
|
|
|
node sel_fir_addr = and(io.take_ext_int_start_d3, _T_243) @[dec_tlu_ctl.scala 3129:53]
|
|
|
|
|
node _T_244 = or(io.i0_exception_valid_r, io.rfpc_i0_r) @[dec_tlu_ctl.scala 3130:60]
|
|
|
|
|
node _T_245 = or(_T_244, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 3130:75]
|
|
|
|
|
node _T_246 = or(_T_245, io.fence_i_r) @[dec_tlu_ctl.scala 3130:96]
|
|
|
|
|
node _T_247 = or(_T_246, io.lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 3130:111]
|
|
|
|
|
node _T_248 = or(_T_247, io.iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 3130:131]
|
|
|
|
|
node _T_249 = or(_T_248, io.debug_resume_req_f) @[dec_tlu_ctl.scala 3130:161]
|
|
|
|
|
node _T_250 = or(_T_249, sel_npc_resume) @[dec_tlu_ctl.scala 3130:186]
|
|
|
|
|
node _T_251 = or(_T_250, io.dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 3130:204]
|
|
|
|
|
node _T_252 = or(_T_251, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 3130:232]
|
|
|
|
|
io.synchronous_flush_r <= _T_252 @[dec_tlu_ctl.scala 3130:33]
|
|
|
|
|
node _T_253 = or(io.interrupt_valid_r, io.mret_r) @[dec_tlu_ctl.scala 3131:54]
|
|
|
|
|
node _T_254 = or(_T_253, io.synchronous_flush_r) @[dec_tlu_ctl.scala 3131:66]
|
|
|
|
|
node _T_255 = or(_T_254, io.take_halt) @[dec_tlu_ctl.scala 3131:91]
|
|
|
|
|
node _T_256 = or(_T_255, io.take_reset) @[dec_tlu_ctl.scala 3131:106]
|
|
|
|
|
node _T_257 = or(_T_256, io.take_ext_int_start) @[dec_tlu_ctl.scala 3131:122]
|
|
|
|
|
io.tlu_flush_lower_r <= _T_257 @[dec_tlu_ctl.scala 3131:30]
|
|
|
|
|
node _T_258 = bits(io.take_reset, 0, 0) @[dec_tlu_ctl.scala 3133:50]
|
|
|
|
|
node _T_259 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 3134:32]
|
|
|
|
|
node _T_260 = eq(io.take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 3135:29]
|
|
|
|
|
node _T_261 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3135:47]
|
|
|
|
|
node _T_262 = and(_T_260, _T_261) @[dec_tlu_ctl.scala 3135:36]
|
|
|
|
|
node _T_263 = eq(io.take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 3136:29]
|
|
|
|
|
node _T_264 = eq(io.rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3136:50]
|
|
|
|
|
node _T_265 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 3136:36]
|
|
|
|
|
node _T_266 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3136:80]
|
|
|
|
|
node _T_267 = and(_T_265, _T_266) @[dec_tlu_ctl.scala 3136:57]
|
|
|
|
|
node _T_268 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3136:98]
|
|
|
|
|
node _T_269 = and(_T_267, _T_268) @[dec_tlu_ctl.scala 3136:87]
|
|
|
|
|
node _T_270 = eq(io.interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 3137:38]
|
|
|
|
|
node _T_271 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 3137:59]
|
|
|
|
|
node _T_272 = and(_T_270, _T_271) @[dec_tlu_ctl.scala 3137:45]
|
|
|
|
|
node _T_273 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 3138:43]
|
|
|
|
|
node _T_274 = not(io.trigger_hit_dmode_r) @[dec_tlu_ctl.scala 3138:89]
|
|
|
|
|
node _T_275 = and(io.i0_trigger_hit_r, _T_274) @[dec_tlu_ctl.scala 3138:87]
|
|
|
|
|
node _T_276 = or(_T_273, _T_275) @[dec_tlu_ctl.scala 3138:64]
|
|
|
|
|
node _T_277 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 3138:117]
|
|
|
|
|
node _T_278 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 3138:115]
|
|
|
|
|
node _T_279 = not(sel_fir_addr) @[dec_tlu_ctl.scala 3138:141]
|
|
|
|
|
node _T_280 = and(_T_278, _T_279) @[dec_tlu_ctl.scala 3138:139]
|
|
|
|
|
node _T_281 = bits(_T_280, 0, 0) @[dec_tlu_ctl.scala 3138:156]
|
|
|
|
|
node _T_282 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 3138:184]
|
|
|
|
|
node _T_283 = cat(_T_282, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_284 = not(io.take_nmi) @[dec_tlu_ctl.scala 3139:18]
|
|
|
|
|
node _T_285 = and(_T_284, io.mret_r) @[dec_tlu_ctl.scala 3139:31]
|
|
|
|
|
node _T_286 = bits(_T_285, 0, 0) @[dec_tlu_ctl.scala 3139:44]
|
|
|
|
|
node _T_287 = not(io.take_nmi) @[dec_tlu_ctl.scala 3140:18]
|
|
|
|
|
node _T_288 = and(_T_287, io.debug_resume_req_f) @[dec_tlu_ctl.scala 3140:31]
|
|
|
|
|
node _T_289 = bits(_T_288, 0, 0) @[dec_tlu_ctl.scala 3140:56]
|
|
|
|
|
node _T_290 = not(io.take_nmi) @[dec_tlu_ctl.scala 3141:18]
|
|
|
|
|
node _T_291 = and(_T_290, sel_npc_resume) @[dec_tlu_ctl.scala 3141:31]
|
|
|
|
|
node _T_292 = bits(_T_291, 0, 0) @[dec_tlu_ctl.scala 3141:49]
|
|
|
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node _T_293 = mux(_T_259, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_294 = mux(_T_262, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_295 = mux(_T_269, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_296 = mux(_T_272, interrupt_path, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_297 = mux(_T_281, _T_283, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_298 = mux(_T_286, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_299 = mux(_T_289, io.dpc, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_300 = mux(_T_292, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_301 = or(_T_293, _T_294) @[Mux.scala 27:72]
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node _T_302 = or(_T_301, _T_295) @[Mux.scala 27:72]
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node _T_303 = or(_T_302, _T_296) @[Mux.scala 27:72]
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node _T_304 = or(_T_303, _T_297) @[Mux.scala 27:72]
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node _T_305 = or(_T_304, _T_298) @[Mux.scala 27:72]
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node _T_306 = or(_T_305, _T_299) @[Mux.scala 27:72]
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node _T_307 = or(_T_306, _T_300) @[Mux.scala 27:72]
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wire _T_308 : UInt<31> @[Mux.scala 27:72]
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_T_308 <= _T_307 @[Mux.scala 27:72]
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node tlu_flush_path_r = mux(_T_258, io.rst_vec, _T_308) @[dec_tlu_ctl.scala 3133:35]
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node _T_309 = bits(io.tlu_flush_lower_r, 0, 0) @[lib.scala 8:44]
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wire _T_310 : UInt<31> @[lib.scala 648:38]
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_T_310 <= UInt<1>("h00") @[lib.scala 648:38]
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reg _T_311 : UInt, clock with : (reset => (reset, _T_310)) @[Reg.scala 27:20]
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when _T_309 : @[Reg.scala 28:19]
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_T_311 <= tlu_flush_path_r @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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io.tlu_flush_path_r_d1 <= _T_311 @[dec_tlu_ctl.scala 3144:31]
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io.dec_tlu_flush_lower_wb <= io.tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 3146:41]
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io.dec_tlu_flush_lower_r <= io.tlu_flush_lower_r @[dec_tlu_ctl.scala 3148:41]
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io.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 3149:41]
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node _T_312 = or(io.lsu_exc_valid_r, io.i0_exception_valid_r) @[dec_tlu_ctl.scala 3152:53]
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node _T_313 = or(_T_312, io.interrupt_valid_r) @[dec_tlu_ctl.scala 3152:79]
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node _T_314 = not(io.trigger_hit_dmode_r) @[dec_tlu_ctl.scala 3152:127]
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node _T_315 = and(io.i0_trigger_hit_r, _T_314) @[dec_tlu_ctl.scala 3152:125]
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node _T_316 = or(_T_313, _T_315) @[dec_tlu_ctl.scala 3152:102]
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io.exc_or_int_valid_r <= _T_316 @[dec_tlu_ctl.scala 3152:31]
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wire _T_317 : UInt
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_T_317 <= UInt<1>("h00")
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node _T_318 = xor(io.interrupt_valid_r, _T_317) @[lib.scala 448:21]
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node _T_319 = orr(_T_318) @[lib.scala 448:29]
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reg _T_320 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_319 : @[Reg.scala 28:19]
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_T_320 <= io.interrupt_valid_r @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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_T_317 <= _T_320 @[lib.scala 451:16]
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io.interrupt_valid_r_d1 <= _T_317 @[dec_tlu_ctl.scala 3154:59]
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wire _T_321 : UInt
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|
_T_321 <= UInt<1>("h00")
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node _T_322 = xor(io.i0_exception_valid_r, _T_321) @[lib.scala 448:21]
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node _T_323 = orr(_T_322) @[lib.scala 448:29]
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reg _T_324 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_323 : @[Reg.scala 28:19]
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_T_324 <= io.i0_exception_valid_r @[Reg.scala 28:23]
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|
skip @[Reg.scala 28:19]
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_T_321 <= _T_324 @[lib.scala 451:16]
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io.i0_exception_valid_r_d1 <= _T_321 @[dec_tlu_ctl.scala 3155:51]
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wire _T_325 : UInt
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|
_T_325 <= UInt<1>("h00")
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node _T_326 = xor(io.exc_or_int_valid_r, _T_325) @[lib.scala 448:21]
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node _T_327 = orr(_T_326) @[lib.scala 448:29]
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reg _T_328 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
when _T_327 : @[Reg.scala 28:19]
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|
_T_328 <= io.exc_or_int_valid_r @[Reg.scala 28:23]
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|
skip @[Reg.scala 28:19]
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_T_325 <= _T_328 @[lib.scala 451:16]
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io.exc_or_int_valid_r_d1 <= _T_325 @[dec_tlu_ctl.scala 3156:53]
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wire _T_329 : UInt
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|
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|
|
_T_329 <= UInt<1>("h00")
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|
|
node _T_330 = xor(io.exc_cause_r, _T_329) @[lib.scala 448:21]
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|
node _T_331 = orr(_T_330) @[lib.scala 448:29]
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reg _T_332 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
when _T_331 : @[Reg.scala 28:19]
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|
_T_332 <= io.exc_cause_r @[Reg.scala 28:23]
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|
skip @[Reg.scala 28:19]
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|
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|
|
_T_329 <= _T_332 @[lib.scala 451:16]
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|
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|
|
io.exc_cause_wb <= _T_329 @[dec_tlu_ctl.scala 3157:65]
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|
node _T_333 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 3158:104]
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|
node _T_334 = and(io.tlu_i0_commit_cmt, _T_333) @[dec_tlu_ctl.scala 3158:102]
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|
|
wire _T_335 : UInt
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|
|
|
|
_T_335 <= UInt<1>("h00")
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|
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|
|
node _T_336 = xor(_T_334, _T_335) @[lib.scala 448:21]
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|
|
node _T_337 = orr(_T_336) @[lib.scala 448:29]
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|
reg _T_338 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
|
when _T_337 : @[Reg.scala 28:19]
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|
_T_338 <= _T_334 @[Reg.scala 28:23]
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|
|
skip @[Reg.scala 28:19]
|
|
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|
|
_T_335 <= _T_338 @[lib.scala 451:16]
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|
io.i0_valid_wb <= _T_335 @[dec_tlu_ctl.scala 3158:71]
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|
|
wire _T_339 : UInt
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|
|
|
|
_T_339 <= UInt<1>("h00")
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|
|
node _T_340 = xor(io.i0_trigger_hit_r, _T_339) @[lib.scala 448:21]
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|
|
node _T_341 = orr(_T_340) @[lib.scala 448:29]
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|
|
reg _T_342 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
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|
|
when _T_341 : @[Reg.scala 28:19]
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|
|
|
|
_T_342 <= io.i0_trigger_hit_r @[Reg.scala 28:23]
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|
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|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_339 <= _T_342 @[lib.scala 451:16]
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|
|
io.trigger_hit_r_d1 <= _T_339 @[dec_tlu_ctl.scala 3159:63]
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|
wire _T_343 : UInt
|
|
|
|
|
_T_343 <= UInt<1>("h00")
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|
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|
|
node _T_344 = xor(io.take_nmi, _T_343) @[lib.scala 448:21]
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|
|
node _T_345 = orr(_T_344) @[lib.scala 448:29]
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|
reg _T_346 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
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|
|
when _T_345 : @[Reg.scala 28:19]
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|
|
_T_346 <= io.take_nmi @[Reg.scala 28:23]
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|
skip @[Reg.scala 28:19]
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|
|
_T_343 <= _T_346 @[lib.scala 451:16]
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|
|
io.take_nmi_r_d1 <= _T_343 @[dec_tlu_ctl.scala 3160:73]
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|
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|
|
wire _T_347 : UInt
|
|
|
|
|
_T_347 <= UInt<1>("h00")
|
|
|
|
|
node _T_348 = xor(io.pause_expired_r, _T_347) @[lib.scala 448:21]
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|
|
node _T_349 = orr(_T_348) @[lib.scala 448:29]
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|
reg _T_350 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
|
|
|
when _T_349 : @[Reg.scala 28:19]
|
|
|
|
|
_T_350 <= io.pause_expired_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_347 <= _T_350 @[lib.scala 451:16]
|
|
|
|
|
io.pause_expired_wb <= _T_347 @[dec_tlu_ctl.scala 3161:69]
|
|
|
|
|
|
|
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|
|
module perf_mux_and_flops :
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|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : AsyncReset
|
|
|
|
|
output io : {mhpmc_inc_r : UInt<1>[4], flip mcountinhibit : UInt<7>, flip mhpme_vec : UInt<10>[4], flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip illegal_r : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, mstatus : UInt<2>, flip mie : UInt<6>, flip ifu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip i0_trigger_hit_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip rfpc_i0_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, mcyclel_cout_f : UInt<1>, minstret_enable_f : UInt<1>, minstretl_cout_f : UInt<1>, fw_halted : UInt<1>, meicidpl : UInt<4>, icache_rd_valid_f : UInt<1>, icache_wr_valid_f : UInt<1>, mhpmc_inc_r_d1 : UInt<1>[4], perfcnt_halted_d1 : UInt<1>, mdseac_locked_f : UInt<1>, lsu_single_ecc_error_r_d1 : UInt<1>, lsu_exc_valid_r_d1 : UInt<1>, lsu_i0_exc_r_d1 : UInt<1>, take_ext_int_start_d1 : UInt<1>, take_ext_int_start_d2 : UInt<1>, take_ext_int_start_d3 : UInt<1>, ext_int_freeze_d1 : UInt<1>, mip : UInt<6>, flip mdseac_locked_ns : UInt<1>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_i0_exc_r : UInt<1>, flip take_ext_int_start : UInt<1>, flip ext_int_freeze : UInt<1>, flip mip_ns : UInt<6>, flip mcyclel_cout : UInt<1>, flip wr_mcycleh_r : UInt<1>, flip mcyclel_cout_in : UInt<1>, flip minstret_enable : UInt<1>, flip minstretl_cout_ns : UInt<1>, flip fw_halted_ns : UInt<1>, flip meicidpl_ns : UInt<4>, flip icache_rd_valid : UInt<1>, flip icache_wr_valid : UInt<1>, flip perfcnt_halted : UInt<1>, flip mstatus_ns : UInt<2>, flip scan_mode : UInt<1>, flip free_l2clk : Clock}
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|
|
node _T = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15]
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|
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|
|
node _T_1 = mux(_T, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
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|
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|
|
node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1) @[dec_tlu_ctl.scala 2795:66]
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|
node _T_2 = bits(io.mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2797:57]
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|
node _T_3 = not(_T_2) @[dec_tlu_ctl.scala 2797:40]
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|
node _T_4 = eq(io.mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42]
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|
node _T_5 = bits(_T_4, 0, 0) @[dec_tlu_ctl.scala 2798:70]
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|
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|
node _T_6 = eq(io.mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42]
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|
node _T_7 = bits(_T_6, 0, 0) @[dec_tlu_ctl.scala 2799:70]
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|
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|
|
node _T_8 = eq(io.mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42]
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|
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|
|
node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 2800:70]
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|
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|
|
node _T_10 = eq(io.mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42]
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|
|
node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 2801:70]
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|
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|
|
node _T_12 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104]
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|
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|
|
node _T_13 = and(io.tlu_i0_commit_cmt, _T_12) @[dec_tlu_ctl.scala 2801:102]
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|
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|
|
node _T_14 = eq(io.mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42]
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|
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|
|
node _T_15 = bits(_T_14, 0, 0) @[dec_tlu_ctl.scala 2802:70]
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|
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|
|
node _T_16 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104]
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|
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|
|
node _T_17 = and(io.tlu_i0_commit_cmt, _T_16) @[dec_tlu_ctl.scala 2802:102]
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|
|
|
|
node _T_18 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125]
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|
|
|
|
node _T_19 = and(_T_17, _T_18) @[dec_tlu_ctl.scala 2802:123]
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|
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|
|
node _T_20 = eq(io.mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42]
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|
|
node _T_21 = bits(_T_20, 0, 0) @[dec_tlu_ctl.scala 2803:70]
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|
|
|
|
node _T_22 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102]
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|
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|
|
node _T_23 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125]
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|
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|
|
node _T_24 = and(_T_22, _T_23) @[dec_tlu_ctl.scala 2803:123]
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|
|
node _T_25 = eq(io.mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42]
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|
|
node _T_26 = bits(_T_25, 0, 0) @[dec_tlu_ctl.scala 2805:70]
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|
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|
|
node _T_27 = eq(io.mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42]
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|
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|
|
node _T_28 = bits(_T_27, 0, 0) @[dec_tlu_ctl.scala 2806:70]
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|
|
|
|
node _T_29 = eq(io.mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42]
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|
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|
|
node _T_30 = bits(_T_29, 0, 0) @[dec_tlu_ctl.scala 2807:70]
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|
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|
|
node _T_31 = eq(io.mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42]
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|
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|
|
node _T_32 = bits(_T_31, 0, 0) @[dec_tlu_ctl.scala 2808:70]
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|
|
|
|
node _T_33 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99]
|
|
|
|
|
node _T_34 = eq(io.mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42]
|
|
|
|
|
node _T_35 = bits(_T_34, 0, 0) @[dec_tlu_ctl.scala 2809:70]
|
|
|
|
|
node _T_36 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113]
|
|
|
|
|
node _T_37 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138]
|
|
|
|
|
node _T_38 = and(_T_36, _T_37) @[dec_tlu_ctl.scala 2809:136]
|
|
|
|
|
node _T_39 = eq(io.mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42]
|
|
|
|
|
node _T_40 = bits(_T_39, 0, 0) @[dec_tlu_ctl.scala 2810:70]
|
|
|
|
|
node _T_41 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99]
|
|
|
|
|
node _T_42 = eq(io.mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42]
|
|
|
|
|
node _T_43 = bits(_T_42, 0, 0) @[dec_tlu_ctl.scala 2811:70]
|
|
|
|
|
node _T_44 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99]
|
|
|
|
|
node _T_45 = eq(io.mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42]
|
|
|
|
|
node _T_46 = bits(_T_45, 0, 0) @[dec_tlu_ctl.scala 2812:70]
|
|
|
|
|
node _T_47 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99]
|
|
|
|
|
node _T_48 = and(_T_47, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108]
|
|
|
|
|
node _T_49 = eq(io.mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42]
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|
|
|
|
node _T_50 = bits(_T_49, 0, 0) @[dec_tlu_ctl.scala 2813:70]
|
|
|
|
|
node _T_51 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99]
|
|
|
|
|
node _T_52 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150]
|
|
|
|
|
node _T_53 = and(_T_51, _T_52) @[dec_tlu_ctl.scala 2813:109]
|
|
|
|
|
node _T_54 = eq(io.mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42]
|
|
|
|
|
node _T_55 = bits(_T_54, 0, 0) @[dec_tlu_ctl.scala 2815:67]
|
|
|
|
|
node _T_56 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97]
|
|
|
|
|
node _T_57 = eq(io.mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42]
|
|
|
|
|
node _T_58 = bits(_T_57, 0, 0) @[dec_tlu_ctl.scala 2816:67]
|
|
|
|
|
node _T_59 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97]
|
|
|
|
|
node _T_60 = eq(io.mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42]
|
|
|
|
|
node _T_61 = bits(_T_60, 0, 0) @[dec_tlu_ctl.scala 2817:67]
|
|
|
|
|
node _T_62 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97]
|
|
|
|
|
node _T_63 = eq(io.mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42]
|
|
|
|
|
node _T_64 = bits(_T_63, 0, 0) @[dec_tlu_ctl.scala 2818:67]
|
|
|
|
|
node _T_65 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97]
|
|
|
|
|
node _T_66 = eq(io.mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42]
|
|
|
|
|
node _T_67 = bits(_T_66, 0, 0) @[dec_tlu_ctl.scala 2819:67]
|
|
|
|
|
node _T_68 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97]
|
|
|
|
|
node _T_69 = eq(io.mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42]
|
|
|
|
|
node _T_70 = bits(_T_69, 0, 0) @[dec_tlu_ctl.scala 2820:67]
|
|
|
|
|
node _T_71 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97]
|
|
|
|
|
node _T_72 = eq(io.mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42]
|
|
|
|
|
node _T_73 = bits(_T_72, 0, 0) @[dec_tlu_ctl.scala 2821:67]
|
|
|
|
|
node _T_74 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97]
|
|
|
|
|
node _T_75 = eq(io.mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42]
|
|
|
|
|
node _T_76 = bits(_T_75, 0, 0) @[dec_tlu_ctl.scala 2822:67]
|
|
|
|
|
node _T_77 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97]
|
|
|
|
|
node _T_78 = eq(io.mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42]
|
|
|
|
|
node _T_79 = bits(_T_78, 0, 0) @[dec_tlu_ctl.scala 2823:67]
|
|
|
|
|
node _T_80 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97]
|
|
|
|
|
node _T_81 = eq(io.mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42]
|
|
|
|
|
node _T_82 = bits(_T_81, 0, 0) @[dec_tlu_ctl.scala 2824:67]
|
|
|
|
|
node _T_83 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97]
|
|
|
|
|
node _T_84 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130]
|
|
|
|
|
node _T_85 = or(_T_83, _T_84) @[dec_tlu_ctl.scala 2824:109]
|
|
|
|
|
node _T_86 = eq(io.mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42]
|
|
|
|
|
node _T_87 = bits(_T_86, 0, 0) @[dec_tlu_ctl.scala 2826:70]
|
|
|
|
|
node _T_88 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103]
|
|
|
|
|
node _T_89 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128]
|
|
|
|
|
node _T_90 = and(_T_88, _T_89) @[dec_tlu_ctl.scala 2826:126]
|
|
|
|
|
node _T_91 = eq(io.mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42]
|
|
|
|
|
node _T_92 = bits(_T_91, 0, 0) @[dec_tlu_ctl.scala 2827:70]
|
|
|
|
|
node _T_93 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105]
|
|
|
|
|
node _T_94 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130]
|
|
|
|
|
node _T_95 = and(_T_93, _T_94) @[dec_tlu_ctl.scala 2827:128]
|
|
|
|
|
node _T_96 = eq(io.mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42]
|
|
|
|
|
node _T_97 = bits(_T_96, 0, 0) @[dec_tlu_ctl.scala 2828:70]
|
|
|
|
|
node _T_98 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118]
|
|
|
|
|
node _T_99 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143]
|
|
|
|
|
node _T_100 = and(_T_98, _T_99) @[dec_tlu_ctl.scala 2828:141]
|
|
|
|
|
node _T_101 = eq(io.mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42]
|
|
|
|
|
node _T_102 = bits(_T_101, 0, 0) @[dec_tlu_ctl.scala 2829:70]
|
|
|
|
|
node _T_103 = eq(io.mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42]
|
|
|
|
|
node _T_104 = bits(_T_103, 0, 0) @[dec_tlu_ctl.scala 2830:70]
|
|
|
|
|
node _T_105 = eq(io.mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42]
|
|
|
|
|
node _T_106 = bits(_T_105, 0, 0) @[dec_tlu_ctl.scala 2831:70]
|
|
|
|
|
node _T_107 = eq(io.mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42]
|
|
|
|
|
node _T_108 = bits(_T_107, 0, 0) @[dec_tlu_ctl.scala 2832:70]
|
|
|
|
|
node _T_109 = eq(io.mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42]
|
|
|
|
|
node _T_110 = bits(_T_109, 0, 0) @[dec_tlu_ctl.scala 2833:70]
|
|
|
|
|
node _T_111 = eq(io.mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42]
|
|
|
|
|
node _T_112 = bits(_T_111, 0, 0) @[dec_tlu_ctl.scala 2834:70]
|
|
|
|
|
node _T_113 = eq(io.mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42]
|
|
|
|
|
node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 2835:70]
|
|
|
|
|
node _T_115 = eq(io.mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42]
|
|
|
|
|
node _T_116 = bits(_T_115, 0, 0) @[dec_tlu_ctl.scala 2836:70]
|
|
|
|
|
node _T_117 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106]
|
|
|
|
|
node _T_118 = or(_T_117, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128]
|
|
|
|
|
node _T_119 = eq(io.mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42]
|
|
|
|
|
node _T_120 = bits(_T_119, 0, 0) @[dec_tlu_ctl.scala 2837:70]
|
|
|
|
|
node _T_121 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100]
|
|
|
|
|
node _T_122 = or(_T_121, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125]
|
|
|
|
|
node _T_123 = eq(io.mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42]
|
|
|
|
|
node _T_124 = bits(_T_123, 0, 0) @[dec_tlu_ctl.scala 2838:70]
|
|
|
|
|
node _T_125 = eq(io.mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42]
|
|
|
|
|
node _T_126 = bits(_T_125, 0, 0) @[dec_tlu_ctl.scala 2839:70]
|
|
|
|
|
node _T_127 = eq(io.mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42]
|
|
|
|
|
node _T_128 = bits(_T_127, 0, 0) @[dec_tlu_ctl.scala 2840:70]
|
|
|
|
|
node _T_129 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105]
|
|
|
|
|
node _T_130 = and(_T_129, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137]
|
|
|
|
|
node _T_131 = eq(io.mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42]
|
|
|
|
|
node _T_132 = bits(_T_131, 0, 0) @[dec_tlu_ctl.scala 2842:70]
|
|
|
|
|
node _T_133 = eq(io.mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42]
|
|
|
|
|
node _T_134 = bits(_T_133, 0, 0) @[dec_tlu_ctl.scala 2843:70]
|
|
|
|
|
node _T_135 = eq(io.mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42]
|
|
|
|
|
node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 2844:70]
|
|
|
|
|
node _T_137 = eq(io.mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42]
|
|
|
|
|
node _T_138 = bits(_T_137, 0, 0) @[dec_tlu_ctl.scala 2845:70]
|
|
|
|
|
node _T_139 = eq(io.mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42]
|
|
|
|
|
node _T_140 = bits(_T_139, 0, 0) @[dec_tlu_ctl.scala 2846:70]
|
|
|
|
|
node _T_141 = eq(io.mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42]
|
|
|
|
|
node _T_142 = bits(_T_141, 0, 0) @[dec_tlu_ctl.scala 2847:70]
|
|
|
|
|
node _T_143 = eq(io.mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42]
|
|
|
|
|
node _T_144 = bits(_T_143, 0, 0) @[dec_tlu_ctl.scala 2848:70]
|
|
|
|
|
node _T_145 = eq(io.mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42]
|
|
|
|
|
node _T_146 = bits(_T_145, 0, 0) @[dec_tlu_ctl.scala 2849:70]
|
|
|
|
|
node _T_147 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92]
|
|
|
|
|
node _T_148 = bits(_T_147, 0, 0) @[dec_tlu_ctl.scala 2849:92]
|
|
|
|
|
node _T_149 = not(_T_148) @[dec_tlu_ctl.scala 2849:81]
|
|
|
|
|
node _T_150 = eq(io.mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42]
|
|
|
|
|
node _T_151 = bits(_T_150, 0, 0) @[dec_tlu_ctl.scala 2850:70]
|
|
|
|
|
node _T_152 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92]
|
|
|
|
|
node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 2850:92]
|
|
|
|
|
node _T_154 = not(_T_153) @[dec_tlu_ctl.scala 2850:81]
|
|
|
|
|
node _T_155 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115]
|
|
|
|
|
node _T_156 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129]
|
|
|
|
|
node _T_157 = and(_T_155, _T_156) @[dec_tlu_ctl.scala 2850:121]
|
|
|
|
|
node _T_158 = orr(_T_157) @[dec_tlu_ctl.scala 2850:136]
|
|
|
|
|
node _T_159 = and(_T_154, _T_158) @[dec_tlu_ctl.scala 2850:106]
|
|
|
|
|
node _T_160 = eq(io.mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42]
|
|
|
|
|
node _T_161 = bits(_T_160, 0, 0) @[dec_tlu_ctl.scala 2851:70]
|
|
|
|
|
node _T_162 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99]
|
|
|
|
|
node _T_163 = eq(io.mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42]
|
|
|
|
|
node _T_164 = bits(_T_163, 0, 0) @[dec_tlu_ctl.scala 2852:70]
|
|
|
|
|
node _T_165 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102]
|
|
|
|
|
node _T_166 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133]
|
|
|
|
|
node _T_167 = and(_T_165, _T_166) @[dec_tlu_ctl.scala 2852:131]
|
|
|
|
|
node _T_168 = eq(io.mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42]
|
|
|
|
|
node _T_169 = bits(_T_168, 0, 0) @[dec_tlu_ctl.scala 2853:70]
|
|
|
|
|
node _T_170 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102]
|
|
|
|
|
node _T_171 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134]
|
|
|
|
|
node _T_172 = and(_T_170, _T_171) @[dec_tlu_ctl.scala 2853:132]
|
|
|
|
|
node _T_173 = eq(io.mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42]
|
|
|
|
|
node _T_174 = bits(_T_173, 0, 0) @[dec_tlu_ctl.scala 2855:70]
|
|
|
|
|
node _T_175 = eq(io.mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42]
|
|
|
|
|
node _T_176 = bits(_T_175, 0, 0) @[dec_tlu_ctl.scala 2856:70]
|
|
|
|
|
node _T_177 = eq(io.mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42]
|
|
|
|
|
node _T_178 = bits(_T_177, 0, 0) @[dec_tlu_ctl.scala 2857:70]
|
|
|
|
|
node _T_179 = eq(io.mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42]
|
|
|
|
|
node _T_180 = bits(_T_179, 0, 0) @[dec_tlu_ctl.scala 2858:70]
|
|
|
|
|
node _T_181 = eq(io.mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42]
|
|
|
|
|
node _T_182 = bits(_T_181, 0, 0) @[dec_tlu_ctl.scala 2859:70]
|
|
|
|
|
node _T_183 = mux(_T_5, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_184 = mux(_T_7, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_185 = mux(_T_9, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
|
node _T_186 = mux(_T_11, _T_13, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
|
node _T_187 = mux(_T_15, _T_19, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_188 = mux(_T_21, _T_24, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_189 = mux(_T_26, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_190 = mux(_T_28, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_191 = mux(_T_30, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_192 = mux(_T_32, _T_33, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_193 = mux(_T_35, _T_38, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_194 = mux(_T_40, _T_41, UInt<1>("h00")) @[Mux.scala 27:72]
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|
|
|
|
node _T_195 = mux(_T_43, _T_44, UInt<1>("h00")) @[Mux.scala 27:72]
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|
|
|
|
node _T_196 = mux(_T_46, _T_48, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
node _T_197 = mux(_T_50, _T_53, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
|
node _T_198 = mux(_T_55, _T_56, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
node _T_199 = mux(_T_58, _T_59, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
|
node _T_200 = mux(_T_61, _T_62, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_201 = mux(_T_64, _T_65, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
|
node _T_202 = mux(_T_67, _T_68, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_203 = mux(_T_70, _T_71, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
|
node _T_204 = mux(_T_73, _T_74, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
node _T_205 = mux(_T_76, _T_77, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
|
node _T_206 = mux(_T_79, _T_80, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_207 = mux(_T_82, _T_85, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_208 = mux(_T_87, _T_90, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_209 = mux(_T_92, _T_95, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_210 = mux(_T_97, _T_100, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_211 = mux(_T_102, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_212 = mux(_T_104, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_213 = mux(_T_106, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_214 = mux(_T_108, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_215 = mux(_T_110, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_216 = mux(_T_112, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
node _T_217 = mux(_T_114, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_218 = mux(_T_116, _T_118, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
node _T_219 = mux(_T_120, _T_122, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_220 = mux(_T_124, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_221 = mux(_T_126, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_222 = mux(_T_128, _T_130, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_223 = mux(_T_132, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_224 = mux(_T_134, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_225 = mux(_T_136, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_226 = mux(_T_138, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
node _T_227 = mux(_T_140, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_228 = mux(_T_142, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_229 = mux(_T_144, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_230 = mux(_T_146, _T_149, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_231 = mux(_T_151, _T_159, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_232 = mux(_T_161, _T_162, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_233 = mux(_T_164, _T_167, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
node _T_234 = mux(_T_169, _T_172, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_235 = mux(_T_174, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_236 = mux(_T_176, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_237 = mux(_T_178, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_238 = mux(_T_180, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_239 = mux(_T_182, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_240 = or(_T_183, _T_184) @[Mux.scala 27:72]
|
|
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|
|
node _T_241 = or(_T_240, _T_185) @[Mux.scala 27:72]
|
|
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|
|
node _T_242 = or(_T_241, _T_186) @[Mux.scala 27:72]
|
|
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|
|
node _T_243 = or(_T_242, _T_187) @[Mux.scala 27:72]
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|
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|
node _T_244 = or(_T_243, _T_188) @[Mux.scala 27:72]
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|
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|
node _T_245 = or(_T_244, _T_189) @[Mux.scala 27:72]
|
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|
node _T_246 = or(_T_245, _T_190) @[Mux.scala 27:72]
|
|
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|
|
node _T_247 = or(_T_246, _T_191) @[Mux.scala 27:72]
|
|
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|
|
node _T_248 = or(_T_247, _T_192) @[Mux.scala 27:72]
|
|
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|
node _T_249 = or(_T_248, _T_193) @[Mux.scala 27:72]
|
|
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|
|
node _T_250 = or(_T_249, _T_194) @[Mux.scala 27:72]
|
|
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|
node _T_251 = or(_T_250, _T_195) @[Mux.scala 27:72]
|
|
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|
node _T_252 = or(_T_251, _T_196) @[Mux.scala 27:72]
|
|
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|
|
node _T_253 = or(_T_252, _T_197) @[Mux.scala 27:72]
|
|
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|
|
node _T_254 = or(_T_253, _T_198) @[Mux.scala 27:72]
|
|
|
|
|
node _T_255 = or(_T_254, _T_199) @[Mux.scala 27:72]
|
|
|
|
|
node _T_256 = or(_T_255, _T_200) @[Mux.scala 27:72]
|
|
|
|
|
node _T_257 = or(_T_256, _T_201) @[Mux.scala 27:72]
|
|
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|
|
node _T_258 = or(_T_257, _T_202) @[Mux.scala 27:72]
|
|
|
|
|
node _T_259 = or(_T_258, _T_203) @[Mux.scala 27:72]
|
|
|
|
|
node _T_260 = or(_T_259, _T_204) @[Mux.scala 27:72]
|
|
|
|
|
node _T_261 = or(_T_260, _T_205) @[Mux.scala 27:72]
|
|
|
|
|
node _T_262 = or(_T_261, _T_206) @[Mux.scala 27:72]
|
|
|
|
|
node _T_263 = or(_T_262, _T_207) @[Mux.scala 27:72]
|
|
|
|
|
node _T_264 = or(_T_263, _T_208) @[Mux.scala 27:72]
|
|
|
|
|
node _T_265 = or(_T_264, _T_209) @[Mux.scala 27:72]
|
|
|
|
|
node _T_266 = or(_T_265, _T_210) @[Mux.scala 27:72]
|
|
|
|
|
node _T_267 = or(_T_266, _T_211) @[Mux.scala 27:72]
|
|
|
|
|
node _T_268 = or(_T_267, _T_212) @[Mux.scala 27:72]
|
|
|
|
|
node _T_269 = or(_T_268, _T_213) @[Mux.scala 27:72]
|
|
|
|
|
node _T_270 = or(_T_269, _T_214) @[Mux.scala 27:72]
|
|
|
|
|
node _T_271 = or(_T_270, _T_215) @[Mux.scala 27:72]
|
|
|
|
|
node _T_272 = or(_T_271, _T_216) @[Mux.scala 27:72]
|
|
|
|
|
node _T_273 = or(_T_272, _T_217) @[Mux.scala 27:72]
|
|
|
|
|
node _T_274 = or(_T_273, _T_218) @[Mux.scala 27:72]
|
|
|
|
|
node _T_275 = or(_T_274, _T_219) @[Mux.scala 27:72]
|
|
|
|
|
node _T_276 = or(_T_275, _T_220) @[Mux.scala 27:72]
|
|
|
|
|
node _T_277 = or(_T_276, _T_221) @[Mux.scala 27:72]
|
|
|
|
|
node _T_278 = or(_T_277, _T_222) @[Mux.scala 27:72]
|
|
|
|
|
node _T_279 = or(_T_278, _T_223) @[Mux.scala 27:72]
|
|
|
|
|
node _T_280 = or(_T_279, _T_224) @[Mux.scala 27:72]
|
|
|
|
|
node _T_281 = or(_T_280, _T_225) @[Mux.scala 27:72]
|
|
|
|
|
node _T_282 = or(_T_281, _T_226) @[Mux.scala 27:72]
|
|
|
|
|
node _T_283 = or(_T_282, _T_227) @[Mux.scala 27:72]
|
|
|
|
|
node _T_284 = or(_T_283, _T_228) @[Mux.scala 27:72]
|
|
|
|
|
node _T_285 = or(_T_284, _T_229) @[Mux.scala 27:72]
|
|
|
|
|
node _T_286 = or(_T_285, _T_230) @[Mux.scala 27:72]
|
|
|
|
|
node _T_287 = or(_T_286, _T_231) @[Mux.scala 27:72]
|
|
|
|
|
node _T_288 = or(_T_287, _T_232) @[Mux.scala 27:72]
|
|
|
|
|
node _T_289 = or(_T_288, _T_233) @[Mux.scala 27:72]
|
|
|
|
|
node _T_290 = or(_T_289, _T_234) @[Mux.scala 27:72]
|
|
|
|
|
node _T_291 = or(_T_290, _T_235) @[Mux.scala 27:72]
|
|
|
|
|
node _T_292 = or(_T_291, _T_236) @[Mux.scala 27:72]
|
|
|
|
|
node _T_293 = or(_T_292, _T_237) @[Mux.scala 27:72]
|
|
|
|
|
node _T_294 = or(_T_293, _T_238) @[Mux.scala 27:72]
|
|
|
|
|
node _T_295 = or(_T_294, _T_239) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_296 : UInt<1> @[Mux.scala 27:72]
|
|
|
|
|
_T_296 <= _T_295 @[Mux.scala 27:72]
|
|
|
|
|
node _T_297 = and(_T_3, _T_296) @[dec_tlu_ctl.scala 2797:63]
|
|
|
|
|
io.mhpmc_inc_r[0] <= _T_297 @[dec_tlu_ctl.scala 2797:35]
|
|
|
|
|
node _T_298 = bits(io.mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2797:57]
|
|
|
|
|
node _T_299 = not(_T_298) @[dec_tlu_ctl.scala 2797:40]
|
|
|
|
|
node _T_300 = eq(io.mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42]
|
|
|
|
|
node _T_301 = bits(_T_300, 0, 0) @[dec_tlu_ctl.scala 2798:70]
|
|
|
|
|
node _T_302 = eq(io.mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42]
|
|
|
|
|
node _T_303 = bits(_T_302, 0, 0) @[dec_tlu_ctl.scala 2799:70]
|
|
|
|
|
node _T_304 = eq(io.mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42]
|
|
|
|
|
node _T_305 = bits(_T_304, 0, 0) @[dec_tlu_ctl.scala 2800:70]
|
|
|
|
|
node _T_306 = eq(io.mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42]
|
|
|
|
|
node _T_307 = bits(_T_306, 0, 0) @[dec_tlu_ctl.scala 2801:70]
|
|
|
|
|
node _T_308 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104]
|
|
|
|
|
node _T_309 = and(io.tlu_i0_commit_cmt, _T_308) @[dec_tlu_ctl.scala 2801:102]
|
|
|
|
|
node _T_310 = eq(io.mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42]
|
|
|
|
|
node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 2802:70]
|
|
|
|
|
node _T_312 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104]
|
|
|
|
|
node _T_313 = and(io.tlu_i0_commit_cmt, _T_312) @[dec_tlu_ctl.scala 2802:102]
|
|
|
|
|
node _T_314 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125]
|
|
|
|
|
node _T_315 = and(_T_313, _T_314) @[dec_tlu_ctl.scala 2802:123]
|
|
|
|
|
node _T_316 = eq(io.mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42]
|
|
|
|
|
node _T_317 = bits(_T_316, 0, 0) @[dec_tlu_ctl.scala 2803:70]
|
|
|
|
|
node _T_318 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102]
|
|
|
|
|
node _T_319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125]
|
|
|
|
|
node _T_320 = and(_T_318, _T_319) @[dec_tlu_ctl.scala 2803:123]
|
|
|
|
|
node _T_321 = eq(io.mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42]
|
|
|
|
|
node _T_322 = bits(_T_321, 0, 0) @[dec_tlu_ctl.scala 2805:70]
|
|
|
|
|
node _T_323 = eq(io.mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42]
|
|
|
|
|
node _T_324 = bits(_T_323, 0, 0) @[dec_tlu_ctl.scala 2806:70]
|
|
|
|
|
node _T_325 = eq(io.mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42]
|
|
|
|
|
node _T_326 = bits(_T_325, 0, 0) @[dec_tlu_ctl.scala 2807:70]
|
|
|
|
|
node _T_327 = eq(io.mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42]
|
|
|
|
|
node _T_328 = bits(_T_327, 0, 0) @[dec_tlu_ctl.scala 2808:70]
|
|
|
|
|
node _T_329 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99]
|
|
|
|
|
node _T_330 = eq(io.mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42]
|
|
|
|
|
node _T_331 = bits(_T_330, 0, 0) @[dec_tlu_ctl.scala 2809:70]
|
|
|
|
|
node _T_332 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113]
|
|
|
|
|
node _T_333 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138]
|
|
|
|
|
node _T_334 = and(_T_332, _T_333) @[dec_tlu_ctl.scala 2809:136]
|
|
|
|
|
node _T_335 = eq(io.mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42]
|
|
|
|
|
node _T_336 = bits(_T_335, 0, 0) @[dec_tlu_ctl.scala 2810:70]
|
|
|
|
|
node _T_337 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99]
|
|
|
|
|
node _T_338 = eq(io.mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42]
|
|
|
|
|
node _T_339 = bits(_T_338, 0, 0) @[dec_tlu_ctl.scala 2811:70]
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|
|
|
|
node _T_340 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99]
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|
|
node _T_341 = eq(io.mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42]
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|
node _T_342 = bits(_T_341, 0, 0) @[dec_tlu_ctl.scala 2812:70]
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node _T_343 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99]
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|
|
|
|
node _T_344 = and(_T_343, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108]
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node _T_345 = eq(io.mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42]
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node _T_346 = bits(_T_345, 0, 0) @[dec_tlu_ctl.scala 2813:70]
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|
node _T_347 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99]
|
|
|
|
|
node _T_348 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150]
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|
|
|
|
node _T_349 = and(_T_347, _T_348) @[dec_tlu_ctl.scala 2813:109]
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|
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|
|
node _T_350 = eq(io.mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42]
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|
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|
node _T_351 = bits(_T_350, 0, 0) @[dec_tlu_ctl.scala 2815:67]
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|
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|
|
node _T_352 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97]
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|
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node _T_353 = eq(io.mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42]
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node _T_354 = bits(_T_353, 0, 0) @[dec_tlu_ctl.scala 2816:67]
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node _T_355 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97]
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node _T_356 = eq(io.mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42]
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node _T_357 = bits(_T_356, 0, 0) @[dec_tlu_ctl.scala 2817:67]
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node _T_358 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97]
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node _T_359 = eq(io.mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42]
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node _T_360 = bits(_T_359, 0, 0) @[dec_tlu_ctl.scala 2818:67]
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|
node _T_361 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97]
|
|
|
|
|
node _T_362 = eq(io.mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42]
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|
node _T_363 = bits(_T_362, 0, 0) @[dec_tlu_ctl.scala 2819:67]
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|
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|
|
node _T_364 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97]
|
|
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|
node _T_365 = eq(io.mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42]
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|
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node _T_366 = bits(_T_365, 0, 0) @[dec_tlu_ctl.scala 2820:67]
|
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|
|
node _T_367 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97]
|
|
|
|
|
node _T_368 = eq(io.mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42]
|
|
|
|
|
node _T_369 = bits(_T_368, 0, 0) @[dec_tlu_ctl.scala 2821:67]
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|
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|
|
node _T_370 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97]
|
|
|
|
|
node _T_371 = eq(io.mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42]
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|
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|
|
node _T_372 = bits(_T_371, 0, 0) @[dec_tlu_ctl.scala 2822:67]
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|
|
node _T_373 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97]
|
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|
node _T_374 = eq(io.mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42]
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|
node _T_375 = bits(_T_374, 0, 0) @[dec_tlu_ctl.scala 2823:67]
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|
node _T_376 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97]
|
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|
node _T_377 = eq(io.mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42]
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|
node _T_378 = bits(_T_377, 0, 0) @[dec_tlu_ctl.scala 2824:67]
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|
node _T_379 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97]
|
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|
node _T_380 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130]
|
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|
|
node _T_381 = or(_T_379, _T_380) @[dec_tlu_ctl.scala 2824:109]
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|
node _T_382 = eq(io.mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42]
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|
|
node _T_383 = bits(_T_382, 0, 0) @[dec_tlu_ctl.scala 2826:70]
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|
node _T_384 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103]
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node _T_385 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128]
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node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 2826:126]
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|
node _T_387 = eq(io.mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42]
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|
node _T_388 = bits(_T_387, 0, 0) @[dec_tlu_ctl.scala 2827:70]
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|
|
node _T_389 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105]
|
|
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|
|
node _T_390 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130]
|
|
|
|
|
node _T_391 = and(_T_389, _T_390) @[dec_tlu_ctl.scala 2827:128]
|
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|
|
node _T_392 = eq(io.mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42]
|
|
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|
|
node _T_393 = bits(_T_392, 0, 0) @[dec_tlu_ctl.scala 2828:70]
|
|
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|
|
node _T_394 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118]
|
|
|
|
|
node _T_395 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143]
|
|
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|
|
node _T_396 = and(_T_394, _T_395) @[dec_tlu_ctl.scala 2828:141]
|
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|
node _T_397 = eq(io.mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42]
|
|
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|
|
node _T_398 = bits(_T_397, 0, 0) @[dec_tlu_ctl.scala 2829:70]
|
|
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|
|
node _T_399 = eq(io.mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42]
|
|
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|
|
node _T_400 = bits(_T_399, 0, 0) @[dec_tlu_ctl.scala 2830:70]
|
|
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|
|
node _T_401 = eq(io.mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42]
|
|
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|
|
node _T_402 = bits(_T_401, 0, 0) @[dec_tlu_ctl.scala 2831:70]
|
|
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|
|
node _T_403 = eq(io.mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42]
|
|
|
|
|
node _T_404 = bits(_T_403, 0, 0) @[dec_tlu_ctl.scala 2832:70]
|
|
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|
|
node _T_405 = eq(io.mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42]
|
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|
|
node _T_406 = bits(_T_405, 0, 0) @[dec_tlu_ctl.scala 2833:70]
|
|
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|
|
node _T_407 = eq(io.mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42]
|
|
|
|
|
node _T_408 = bits(_T_407, 0, 0) @[dec_tlu_ctl.scala 2834:70]
|
|
|
|
|
node _T_409 = eq(io.mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42]
|
|
|
|
|
node _T_410 = bits(_T_409, 0, 0) @[dec_tlu_ctl.scala 2835:70]
|
|
|
|
|
node _T_411 = eq(io.mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42]
|
|
|
|
|
node _T_412 = bits(_T_411, 0, 0) @[dec_tlu_ctl.scala 2836:70]
|
|
|
|
|
node _T_413 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106]
|
|
|
|
|
node _T_414 = or(_T_413, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128]
|
|
|
|
|
node _T_415 = eq(io.mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42]
|
|
|
|
|
node _T_416 = bits(_T_415, 0, 0) @[dec_tlu_ctl.scala 2837:70]
|
|
|
|
|
node _T_417 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100]
|
|
|
|
|
node _T_418 = or(_T_417, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125]
|
|
|
|
|
node _T_419 = eq(io.mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42]
|
|
|
|
|
node _T_420 = bits(_T_419, 0, 0) @[dec_tlu_ctl.scala 2838:70]
|
|
|
|
|
node _T_421 = eq(io.mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42]
|
|
|
|
|
node _T_422 = bits(_T_421, 0, 0) @[dec_tlu_ctl.scala 2839:70]
|
|
|
|
|
node _T_423 = eq(io.mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42]
|
|
|
|
|
node _T_424 = bits(_T_423, 0, 0) @[dec_tlu_ctl.scala 2840:70]
|
|
|
|
|
node _T_425 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105]
|
|
|
|
|
node _T_426 = and(_T_425, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137]
|
|
|
|
|
node _T_427 = eq(io.mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42]
|
|
|
|
|
node _T_428 = bits(_T_427, 0, 0) @[dec_tlu_ctl.scala 2842:70]
|
|
|
|
|
node _T_429 = eq(io.mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42]
|
|
|
|
|
node _T_430 = bits(_T_429, 0, 0) @[dec_tlu_ctl.scala 2843:70]
|
|
|
|
|
node _T_431 = eq(io.mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42]
|
|
|
|
|
node _T_432 = bits(_T_431, 0, 0) @[dec_tlu_ctl.scala 2844:70]
|
|
|
|
|
node _T_433 = eq(io.mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42]
|
|
|
|
|
node _T_434 = bits(_T_433, 0, 0) @[dec_tlu_ctl.scala 2845:70]
|
|
|
|
|
node _T_435 = eq(io.mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42]
|
|
|
|
|
node _T_436 = bits(_T_435, 0, 0) @[dec_tlu_ctl.scala 2846:70]
|
|
|
|
|
node _T_437 = eq(io.mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42]
|
|
|
|
|
node _T_438 = bits(_T_437, 0, 0) @[dec_tlu_ctl.scala 2847:70]
|
|
|
|
|
node _T_439 = eq(io.mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42]
|
|
|
|
|
node _T_440 = bits(_T_439, 0, 0) @[dec_tlu_ctl.scala 2848:70]
|
|
|
|
|
node _T_441 = eq(io.mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42]
|
|
|
|
|
node _T_442 = bits(_T_441, 0, 0) @[dec_tlu_ctl.scala 2849:70]
|
|
|
|
|
node _T_443 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92]
|
|
|
|
|
node _T_444 = bits(_T_443, 0, 0) @[dec_tlu_ctl.scala 2849:92]
|
|
|
|
|
node _T_445 = not(_T_444) @[dec_tlu_ctl.scala 2849:81]
|
|
|
|
|
node _T_446 = eq(io.mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42]
|
|
|
|
|
node _T_447 = bits(_T_446, 0, 0) @[dec_tlu_ctl.scala 2850:70]
|
|
|
|
|
node _T_448 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92]
|
|
|
|
|
node _T_449 = bits(_T_448, 0, 0) @[dec_tlu_ctl.scala 2850:92]
|
|
|
|
|
node _T_450 = not(_T_449) @[dec_tlu_ctl.scala 2850:81]
|
|
|
|
|
node _T_451 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115]
|
|
|
|
|
node _T_452 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129]
|
|
|
|
|
node _T_453 = and(_T_451, _T_452) @[dec_tlu_ctl.scala 2850:121]
|
|
|
|
|
node _T_454 = orr(_T_453) @[dec_tlu_ctl.scala 2850:136]
|
|
|
|
|
node _T_455 = and(_T_450, _T_454) @[dec_tlu_ctl.scala 2850:106]
|
|
|
|
|
node _T_456 = eq(io.mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42]
|
|
|
|
|
node _T_457 = bits(_T_456, 0, 0) @[dec_tlu_ctl.scala 2851:70]
|
|
|
|
|
node _T_458 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99]
|
|
|
|
|
node _T_459 = eq(io.mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42]
|
|
|
|
|
node _T_460 = bits(_T_459, 0, 0) @[dec_tlu_ctl.scala 2852:70]
|
|
|
|
|
node _T_461 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102]
|
|
|
|
|
node _T_462 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133]
|
|
|
|
|
node _T_463 = and(_T_461, _T_462) @[dec_tlu_ctl.scala 2852:131]
|
|
|
|
|
node _T_464 = eq(io.mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42]
|
|
|
|
|
node _T_465 = bits(_T_464, 0, 0) @[dec_tlu_ctl.scala 2853:70]
|
|
|
|
|
node _T_466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102]
|
|
|
|
|
node _T_467 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134]
|
|
|
|
|
node _T_468 = and(_T_466, _T_467) @[dec_tlu_ctl.scala 2853:132]
|
|
|
|
|
node _T_469 = eq(io.mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42]
|
|
|
|
|
node _T_470 = bits(_T_469, 0, 0) @[dec_tlu_ctl.scala 2855:70]
|
|
|
|
|
node _T_471 = eq(io.mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42]
|
|
|
|
|
node _T_472 = bits(_T_471, 0, 0) @[dec_tlu_ctl.scala 2856:70]
|
|
|
|
|
node _T_473 = eq(io.mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42]
|
|
|
|
|
node _T_474 = bits(_T_473, 0, 0) @[dec_tlu_ctl.scala 2857:70]
|
|
|
|
|
node _T_475 = eq(io.mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42]
|
|
|
|
|
node _T_476 = bits(_T_475, 0, 0) @[dec_tlu_ctl.scala 2858:70]
|
|
|
|
|
node _T_477 = eq(io.mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42]
|
|
|
|
|
node _T_478 = bits(_T_477, 0, 0) @[dec_tlu_ctl.scala 2859:70]
|
|
|
|
|
node _T_479 = mux(_T_301, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_480 = mux(_T_303, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_481 = mux(_T_305, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_482 = mux(_T_307, _T_309, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_483 = mux(_T_311, _T_315, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_484 = mux(_T_317, _T_320, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_485 = mux(_T_322, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_486 = mux(_T_324, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_487 = mux(_T_326, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_488 = mux(_T_328, _T_329, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_489 = mux(_T_331, _T_334, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_490 = mux(_T_336, _T_337, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_491 = mux(_T_339, _T_340, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_492 = mux(_T_342, _T_344, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_493 = mux(_T_346, _T_349, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_494 = mux(_T_351, _T_352, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_495 = mux(_T_354, _T_355, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_496 = mux(_T_357, _T_358, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_497 = mux(_T_360, _T_361, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_498 = mux(_T_363, _T_364, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_499 = mux(_T_366, _T_367, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_500 = mux(_T_369, _T_370, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_501 = mux(_T_372, _T_373, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_502 = mux(_T_375, _T_376, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_503 = mux(_T_378, _T_381, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_504 = mux(_T_383, _T_386, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_505 = mux(_T_388, _T_391, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_506 = mux(_T_393, _T_396, UInt<1>("h00")) @[Mux.scala 27:72]
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|
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|
|
node _T_507 = mux(_T_398, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_508 = mux(_T_400, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_509 = mux(_T_402, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_510 = mux(_T_404, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_511 = mux(_T_406, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_512 = mux(_T_408, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_513 = mux(_T_410, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
node _T_514 = mux(_T_412, _T_414, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_515 = mux(_T_416, _T_418, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_516 = mux(_T_420, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_517 = mux(_T_422, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_518 = mux(_T_424, _T_426, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_519 = mux(_T_428, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_520 = mux(_T_430, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_521 = mux(_T_432, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_522 = mux(_T_434, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_523 = mux(_T_436, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_524 = mux(_T_438, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_525 = mux(_T_440, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_526 = mux(_T_442, _T_445, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_527 = mux(_T_447, _T_455, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_528 = mux(_T_457, _T_458, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_529 = mux(_T_460, _T_463, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_530 = mux(_T_465, _T_468, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_531 = mux(_T_470, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_532 = mux(_T_472, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_533 = mux(_T_474, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_534 = mux(_T_476, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_535 = mux(_T_478, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_536 = or(_T_479, _T_480) @[Mux.scala 27:72]
|
|
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|
node _T_537 = or(_T_536, _T_481) @[Mux.scala 27:72]
|
|
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|
|
node _T_538 = or(_T_537, _T_482) @[Mux.scala 27:72]
|
|
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|
|
node _T_539 = or(_T_538, _T_483) @[Mux.scala 27:72]
|
|
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|
node _T_540 = or(_T_539, _T_484) @[Mux.scala 27:72]
|
|
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|
|
node _T_541 = or(_T_540, _T_485) @[Mux.scala 27:72]
|
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|
|
node _T_542 = or(_T_541, _T_486) @[Mux.scala 27:72]
|
|
|
|
|
node _T_543 = or(_T_542, _T_487) @[Mux.scala 27:72]
|
|
|
|
|
node _T_544 = or(_T_543, _T_488) @[Mux.scala 27:72]
|
|
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|
|
node _T_545 = or(_T_544, _T_489) @[Mux.scala 27:72]
|
|
|
|
|
node _T_546 = or(_T_545, _T_490) @[Mux.scala 27:72]
|
|
|
|
|
node _T_547 = or(_T_546, _T_491) @[Mux.scala 27:72]
|
|
|
|
|
node _T_548 = or(_T_547, _T_492) @[Mux.scala 27:72]
|
|
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|
|
node _T_549 = or(_T_548, _T_493) @[Mux.scala 27:72]
|
|
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|
|
node _T_550 = or(_T_549, _T_494) @[Mux.scala 27:72]
|
|
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|
|
node _T_551 = or(_T_550, _T_495) @[Mux.scala 27:72]
|
|
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|
|
node _T_552 = or(_T_551, _T_496) @[Mux.scala 27:72]
|
|
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|
|
node _T_553 = or(_T_552, _T_497) @[Mux.scala 27:72]
|
|
|
|
|
node _T_554 = or(_T_553, _T_498) @[Mux.scala 27:72]
|
|
|
|
|
node _T_555 = or(_T_554, _T_499) @[Mux.scala 27:72]
|
|
|
|
|
node _T_556 = or(_T_555, _T_500) @[Mux.scala 27:72]
|
|
|
|
|
node _T_557 = or(_T_556, _T_501) @[Mux.scala 27:72]
|
|
|
|
|
node _T_558 = or(_T_557, _T_502) @[Mux.scala 27:72]
|
|
|
|
|
node _T_559 = or(_T_558, _T_503) @[Mux.scala 27:72]
|
|
|
|
|
node _T_560 = or(_T_559, _T_504) @[Mux.scala 27:72]
|
|
|
|
|
node _T_561 = or(_T_560, _T_505) @[Mux.scala 27:72]
|
|
|
|
|
node _T_562 = or(_T_561, _T_506) @[Mux.scala 27:72]
|
|
|
|
|
node _T_563 = or(_T_562, _T_507) @[Mux.scala 27:72]
|
|
|
|
|
node _T_564 = or(_T_563, _T_508) @[Mux.scala 27:72]
|
|
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|
|
node _T_565 = or(_T_564, _T_509) @[Mux.scala 27:72]
|
|
|
|
|
node _T_566 = or(_T_565, _T_510) @[Mux.scala 27:72]
|
|
|
|
|
node _T_567 = or(_T_566, _T_511) @[Mux.scala 27:72]
|
|
|
|
|
node _T_568 = or(_T_567, _T_512) @[Mux.scala 27:72]
|
|
|
|
|
node _T_569 = or(_T_568, _T_513) @[Mux.scala 27:72]
|
|
|
|
|
node _T_570 = or(_T_569, _T_514) @[Mux.scala 27:72]
|
|
|
|
|
node _T_571 = or(_T_570, _T_515) @[Mux.scala 27:72]
|
|
|
|
|
node _T_572 = or(_T_571, _T_516) @[Mux.scala 27:72]
|
|
|
|
|
node _T_573 = or(_T_572, _T_517) @[Mux.scala 27:72]
|
|
|
|
|
node _T_574 = or(_T_573, _T_518) @[Mux.scala 27:72]
|
|
|
|
|
node _T_575 = or(_T_574, _T_519) @[Mux.scala 27:72]
|
|
|
|
|
node _T_576 = or(_T_575, _T_520) @[Mux.scala 27:72]
|
|
|
|
|
node _T_577 = or(_T_576, _T_521) @[Mux.scala 27:72]
|
|
|
|
|
node _T_578 = or(_T_577, _T_522) @[Mux.scala 27:72]
|
|
|
|
|
node _T_579 = or(_T_578, _T_523) @[Mux.scala 27:72]
|
|
|
|
|
node _T_580 = or(_T_579, _T_524) @[Mux.scala 27:72]
|
|
|
|
|
node _T_581 = or(_T_580, _T_525) @[Mux.scala 27:72]
|
|
|
|
|
node _T_582 = or(_T_581, _T_526) @[Mux.scala 27:72]
|
|
|
|
|
node _T_583 = or(_T_582, _T_527) @[Mux.scala 27:72]
|
|
|
|
|
node _T_584 = or(_T_583, _T_528) @[Mux.scala 27:72]
|
|
|
|
|
node _T_585 = or(_T_584, _T_529) @[Mux.scala 27:72]
|
|
|
|
|
node _T_586 = or(_T_585, _T_530) @[Mux.scala 27:72]
|
|
|
|
|
node _T_587 = or(_T_586, _T_531) @[Mux.scala 27:72]
|
|
|
|
|
node _T_588 = or(_T_587, _T_532) @[Mux.scala 27:72]
|
|
|
|
|
node _T_589 = or(_T_588, _T_533) @[Mux.scala 27:72]
|
|
|
|
|
node _T_590 = or(_T_589, _T_534) @[Mux.scala 27:72]
|
|
|
|
|
node _T_591 = or(_T_590, _T_535) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_592 : UInt<1> @[Mux.scala 27:72]
|
|
|
|
|
_T_592 <= _T_591 @[Mux.scala 27:72]
|
|
|
|
|
node _T_593 = and(_T_299, _T_592) @[dec_tlu_ctl.scala 2797:63]
|
|
|
|
|
io.mhpmc_inc_r[1] <= _T_593 @[dec_tlu_ctl.scala 2797:35]
|
|
|
|
|
node _T_594 = bits(io.mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2797:57]
|
|
|
|
|
node _T_595 = not(_T_594) @[dec_tlu_ctl.scala 2797:40]
|
|
|
|
|
node _T_596 = eq(io.mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42]
|
|
|
|
|
node _T_597 = bits(_T_596, 0, 0) @[dec_tlu_ctl.scala 2798:70]
|
|
|
|
|
node _T_598 = eq(io.mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42]
|
|
|
|
|
node _T_599 = bits(_T_598, 0, 0) @[dec_tlu_ctl.scala 2799:70]
|
|
|
|
|
node _T_600 = eq(io.mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42]
|
|
|
|
|
node _T_601 = bits(_T_600, 0, 0) @[dec_tlu_ctl.scala 2800:70]
|
|
|
|
|
node _T_602 = eq(io.mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42]
|
|
|
|
|
node _T_603 = bits(_T_602, 0, 0) @[dec_tlu_ctl.scala 2801:70]
|
|
|
|
|
node _T_604 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104]
|
|
|
|
|
node _T_605 = and(io.tlu_i0_commit_cmt, _T_604) @[dec_tlu_ctl.scala 2801:102]
|
|
|
|
|
node _T_606 = eq(io.mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42]
|
|
|
|
|
node _T_607 = bits(_T_606, 0, 0) @[dec_tlu_ctl.scala 2802:70]
|
|
|
|
|
node _T_608 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104]
|
|
|
|
|
node _T_609 = and(io.tlu_i0_commit_cmt, _T_608) @[dec_tlu_ctl.scala 2802:102]
|
|
|
|
|
node _T_610 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125]
|
|
|
|
|
node _T_611 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2802:123]
|
|
|
|
|
node _T_612 = eq(io.mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42]
|
|
|
|
|
node _T_613 = bits(_T_612, 0, 0) @[dec_tlu_ctl.scala 2803:70]
|
|
|
|
|
node _T_614 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102]
|
|
|
|
|
node _T_615 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125]
|
|
|
|
|
node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 2803:123]
|
|
|
|
|
node _T_617 = eq(io.mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42]
|
|
|
|
|
node _T_618 = bits(_T_617, 0, 0) @[dec_tlu_ctl.scala 2805:70]
|
|
|
|
|
node _T_619 = eq(io.mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42]
|
|
|
|
|
node _T_620 = bits(_T_619, 0, 0) @[dec_tlu_ctl.scala 2806:70]
|
|
|
|
|
node _T_621 = eq(io.mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42]
|
|
|
|
|
node _T_622 = bits(_T_621, 0, 0) @[dec_tlu_ctl.scala 2807:70]
|
|
|
|
|
node _T_623 = eq(io.mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42]
|
|
|
|
|
node _T_624 = bits(_T_623, 0, 0) @[dec_tlu_ctl.scala 2808:70]
|
|
|
|
|
node _T_625 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99]
|
|
|
|
|
node _T_626 = eq(io.mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42]
|
|
|
|
|
node _T_627 = bits(_T_626, 0, 0) @[dec_tlu_ctl.scala 2809:70]
|
|
|
|
|
node _T_628 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113]
|
|
|
|
|
node _T_629 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138]
|
|
|
|
|
node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2809:136]
|
|
|
|
|
node _T_631 = eq(io.mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42]
|
|
|
|
|
node _T_632 = bits(_T_631, 0, 0) @[dec_tlu_ctl.scala 2810:70]
|
|
|
|
|
node _T_633 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99]
|
|
|
|
|
node _T_634 = eq(io.mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42]
|
|
|
|
|
node _T_635 = bits(_T_634, 0, 0) @[dec_tlu_ctl.scala 2811:70]
|
|
|
|
|
node _T_636 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99]
|
|
|
|
|
node _T_637 = eq(io.mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42]
|
|
|
|
|
node _T_638 = bits(_T_637, 0, 0) @[dec_tlu_ctl.scala 2812:70]
|
|
|
|
|
node _T_639 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99]
|
|
|
|
|
node _T_640 = and(_T_639, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108]
|
|
|
|
|
node _T_641 = eq(io.mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42]
|
|
|
|
|
node _T_642 = bits(_T_641, 0, 0) @[dec_tlu_ctl.scala 2813:70]
|
|
|
|
|
node _T_643 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99]
|
|
|
|
|
node _T_644 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150]
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|
node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2813:109]
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node _T_646 = eq(io.mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42]
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|
node _T_647 = bits(_T_646, 0, 0) @[dec_tlu_ctl.scala 2815:67]
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node _T_648 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97]
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node _T_649 = eq(io.mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42]
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node _T_650 = bits(_T_649, 0, 0) @[dec_tlu_ctl.scala 2816:67]
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node _T_651 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97]
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node _T_652 = eq(io.mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42]
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node _T_653 = bits(_T_652, 0, 0) @[dec_tlu_ctl.scala 2817:67]
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node _T_654 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97]
|
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node _T_655 = eq(io.mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42]
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node _T_656 = bits(_T_655, 0, 0) @[dec_tlu_ctl.scala 2818:67]
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node _T_657 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97]
|
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node _T_658 = eq(io.mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42]
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node _T_659 = bits(_T_658, 0, 0) @[dec_tlu_ctl.scala 2819:67]
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node _T_660 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97]
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|
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node _T_661 = eq(io.mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42]
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node _T_662 = bits(_T_661, 0, 0) @[dec_tlu_ctl.scala 2820:67]
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node _T_663 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97]
|
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|
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node _T_664 = eq(io.mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42]
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node _T_665 = bits(_T_664, 0, 0) @[dec_tlu_ctl.scala 2821:67]
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node _T_666 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97]
|
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|
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node _T_667 = eq(io.mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42]
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node _T_668 = bits(_T_667, 0, 0) @[dec_tlu_ctl.scala 2822:67]
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|
node _T_669 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97]
|
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node _T_670 = eq(io.mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42]
|
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|
node _T_671 = bits(_T_670, 0, 0) @[dec_tlu_ctl.scala 2823:67]
|
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|
node _T_672 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97]
|
|
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|
|
node _T_673 = eq(io.mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42]
|
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|
|
node _T_674 = bits(_T_673, 0, 0) @[dec_tlu_ctl.scala 2824:67]
|
|
|
|
|
node _T_675 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97]
|
|
|
|
|
node _T_676 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130]
|
|
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|
|
node _T_677 = or(_T_675, _T_676) @[dec_tlu_ctl.scala 2824:109]
|
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|
|
node _T_678 = eq(io.mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42]
|
|
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|
|
node _T_679 = bits(_T_678, 0, 0) @[dec_tlu_ctl.scala 2826:70]
|
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|
|
node _T_680 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103]
|
|
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|
|
node _T_681 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128]
|
|
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|
|
node _T_682 = and(_T_680, _T_681) @[dec_tlu_ctl.scala 2826:126]
|
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|
|
node _T_683 = eq(io.mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42]
|
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|
|
node _T_684 = bits(_T_683, 0, 0) @[dec_tlu_ctl.scala 2827:70]
|
|
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|
|
node _T_685 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105]
|
|
|
|
|
node _T_686 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130]
|
|
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|
|
node _T_687 = and(_T_685, _T_686) @[dec_tlu_ctl.scala 2827:128]
|
|
|
|
|
node _T_688 = eq(io.mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42]
|
|
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|
|
node _T_689 = bits(_T_688, 0, 0) @[dec_tlu_ctl.scala 2828:70]
|
|
|
|
|
node _T_690 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118]
|
|
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|
|
node _T_691 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143]
|
|
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|
node _T_692 = and(_T_690, _T_691) @[dec_tlu_ctl.scala 2828:141]
|
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|
node _T_693 = eq(io.mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42]
|
|
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|
|
node _T_694 = bits(_T_693, 0, 0) @[dec_tlu_ctl.scala 2829:70]
|
|
|
|
|
node _T_695 = eq(io.mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42]
|
|
|
|
|
node _T_696 = bits(_T_695, 0, 0) @[dec_tlu_ctl.scala 2830:70]
|
|
|
|
|
node _T_697 = eq(io.mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42]
|
|
|
|
|
node _T_698 = bits(_T_697, 0, 0) @[dec_tlu_ctl.scala 2831:70]
|
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|
|
node _T_699 = eq(io.mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42]
|
|
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|
|
node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2832:70]
|
|
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|
|
node _T_701 = eq(io.mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42]
|
|
|
|
|
node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2833:70]
|
|
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|
|
node _T_703 = eq(io.mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42]
|
|
|
|
|
node _T_704 = bits(_T_703, 0, 0) @[dec_tlu_ctl.scala 2834:70]
|
|
|
|
|
node _T_705 = eq(io.mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42]
|
|
|
|
|
node _T_706 = bits(_T_705, 0, 0) @[dec_tlu_ctl.scala 2835:70]
|
|
|
|
|
node _T_707 = eq(io.mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42]
|
|
|
|
|
node _T_708 = bits(_T_707, 0, 0) @[dec_tlu_ctl.scala 2836:70]
|
|
|
|
|
node _T_709 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106]
|
|
|
|
|
node _T_710 = or(_T_709, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128]
|
|
|
|
|
node _T_711 = eq(io.mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42]
|
|
|
|
|
node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2837:70]
|
|
|
|
|
node _T_713 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100]
|
|
|
|
|
node _T_714 = or(_T_713, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125]
|
|
|
|
|
node _T_715 = eq(io.mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42]
|
|
|
|
|
node _T_716 = bits(_T_715, 0, 0) @[dec_tlu_ctl.scala 2838:70]
|
|
|
|
|
node _T_717 = eq(io.mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42]
|
|
|
|
|
node _T_718 = bits(_T_717, 0, 0) @[dec_tlu_ctl.scala 2839:70]
|
|
|
|
|
node _T_719 = eq(io.mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42]
|
|
|
|
|
node _T_720 = bits(_T_719, 0, 0) @[dec_tlu_ctl.scala 2840:70]
|
|
|
|
|
node _T_721 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105]
|
|
|
|
|
node _T_722 = and(_T_721, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137]
|
|
|
|
|
node _T_723 = eq(io.mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42]
|
|
|
|
|
node _T_724 = bits(_T_723, 0, 0) @[dec_tlu_ctl.scala 2842:70]
|
|
|
|
|
node _T_725 = eq(io.mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42]
|
|
|
|
|
node _T_726 = bits(_T_725, 0, 0) @[dec_tlu_ctl.scala 2843:70]
|
|
|
|
|
node _T_727 = eq(io.mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42]
|
|
|
|
|
node _T_728 = bits(_T_727, 0, 0) @[dec_tlu_ctl.scala 2844:70]
|
|
|
|
|
node _T_729 = eq(io.mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42]
|
|
|
|
|
node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2845:70]
|
|
|
|
|
node _T_731 = eq(io.mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42]
|
|
|
|
|
node _T_732 = bits(_T_731, 0, 0) @[dec_tlu_ctl.scala 2846:70]
|
|
|
|
|
node _T_733 = eq(io.mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42]
|
|
|
|
|
node _T_734 = bits(_T_733, 0, 0) @[dec_tlu_ctl.scala 2847:70]
|
|
|
|
|
node _T_735 = eq(io.mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42]
|
|
|
|
|
node _T_736 = bits(_T_735, 0, 0) @[dec_tlu_ctl.scala 2848:70]
|
|
|
|
|
node _T_737 = eq(io.mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42]
|
|
|
|
|
node _T_738 = bits(_T_737, 0, 0) @[dec_tlu_ctl.scala 2849:70]
|
|
|
|
|
node _T_739 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92]
|
|
|
|
|
node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2849:92]
|
|
|
|
|
node _T_741 = not(_T_740) @[dec_tlu_ctl.scala 2849:81]
|
|
|
|
|
node _T_742 = eq(io.mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42]
|
|
|
|
|
node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2850:70]
|
|
|
|
|
node _T_744 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92]
|
|
|
|
|
node _T_745 = bits(_T_744, 0, 0) @[dec_tlu_ctl.scala 2850:92]
|
|
|
|
|
node _T_746 = not(_T_745) @[dec_tlu_ctl.scala 2850:81]
|
|
|
|
|
node _T_747 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115]
|
|
|
|
|
node _T_748 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129]
|
|
|
|
|
node _T_749 = and(_T_747, _T_748) @[dec_tlu_ctl.scala 2850:121]
|
|
|
|
|
node _T_750 = orr(_T_749) @[dec_tlu_ctl.scala 2850:136]
|
|
|
|
|
node _T_751 = and(_T_746, _T_750) @[dec_tlu_ctl.scala 2850:106]
|
|
|
|
|
node _T_752 = eq(io.mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42]
|
|
|
|
|
node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2851:70]
|
|
|
|
|
node _T_754 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99]
|
|
|
|
|
node _T_755 = eq(io.mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42]
|
|
|
|
|
node _T_756 = bits(_T_755, 0, 0) @[dec_tlu_ctl.scala 2852:70]
|
|
|
|
|
node _T_757 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102]
|
|
|
|
|
node _T_758 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133]
|
|
|
|
|
node _T_759 = and(_T_757, _T_758) @[dec_tlu_ctl.scala 2852:131]
|
|
|
|
|
node _T_760 = eq(io.mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42]
|
|
|
|
|
node _T_761 = bits(_T_760, 0, 0) @[dec_tlu_ctl.scala 2853:70]
|
|
|
|
|
node _T_762 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102]
|
|
|
|
|
node _T_763 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134]
|
|
|
|
|
node _T_764 = and(_T_762, _T_763) @[dec_tlu_ctl.scala 2853:132]
|
|
|
|
|
node _T_765 = eq(io.mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42]
|
|
|
|
|
node _T_766 = bits(_T_765, 0, 0) @[dec_tlu_ctl.scala 2855:70]
|
|
|
|
|
node _T_767 = eq(io.mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42]
|
|
|
|
|
node _T_768 = bits(_T_767, 0, 0) @[dec_tlu_ctl.scala 2856:70]
|
|
|
|
|
node _T_769 = eq(io.mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42]
|
|
|
|
|
node _T_770 = bits(_T_769, 0, 0) @[dec_tlu_ctl.scala 2857:70]
|
|
|
|
|
node _T_771 = eq(io.mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42]
|
|
|
|
|
node _T_772 = bits(_T_771, 0, 0) @[dec_tlu_ctl.scala 2858:70]
|
|
|
|
|
node _T_773 = eq(io.mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42]
|
|
|
|
|
node _T_774 = bits(_T_773, 0, 0) @[dec_tlu_ctl.scala 2859:70]
|
|
|
|
|
node _T_775 = mux(_T_597, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_776 = mux(_T_599, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_777 = mux(_T_601, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_778 = mux(_T_603, _T_605, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_779 = mux(_T_607, _T_611, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_780 = mux(_T_613, _T_616, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_781 = mux(_T_618, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_782 = mux(_T_620, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_783 = mux(_T_622, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_784 = mux(_T_624, _T_625, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_785 = mux(_T_627, _T_630, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_786 = mux(_T_632, _T_633, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_787 = mux(_T_635, _T_636, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_788 = mux(_T_638, _T_640, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_789 = mux(_T_642, _T_645, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_790 = mux(_T_647, _T_648, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_791 = mux(_T_650, _T_651, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_792 = mux(_T_653, _T_654, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_793 = mux(_T_656, _T_657, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_794 = mux(_T_659, _T_660, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_795 = mux(_T_662, _T_663, UInt<1>("h00")) @[Mux.scala 27:72]
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|
|
node _T_796 = mux(_T_665, _T_666, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_797 = mux(_T_668, _T_669, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
node _T_798 = mux(_T_671, _T_672, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_799 = mux(_T_674, _T_677, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_800 = mux(_T_679, _T_682, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_801 = mux(_T_684, _T_687, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_802 = mux(_T_689, _T_692, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_803 = mux(_T_694, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_804 = mux(_T_696, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_805 = mux(_T_698, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_806 = mux(_T_700, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_807 = mux(_T_702, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_808 = mux(_T_704, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_809 = mux(_T_706, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_810 = mux(_T_708, _T_710, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_811 = mux(_T_712, _T_714, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_812 = mux(_T_716, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_813 = mux(_T_718, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_814 = mux(_T_720, _T_722, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_815 = mux(_T_724, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
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node _T_816 = mux(_T_726, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_817 = mux(_T_728, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_818 = mux(_T_730, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_819 = mux(_T_732, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_820 = mux(_T_734, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_821 = mux(_T_736, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_822 = mux(_T_738, _T_741, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_823 = mux(_T_743, _T_751, UInt<1>("h00")) @[Mux.scala 27:72]
|
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node _T_824 = mux(_T_753, _T_754, UInt<1>("h00")) @[Mux.scala 27:72]
|
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node _T_825 = mux(_T_756, _T_759, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_826 = mux(_T_761, _T_764, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_827 = mux(_T_766, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_828 = mux(_T_768, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_829 = mux(_T_770, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_830 = mux(_T_772, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_831 = mux(_T_774, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_832 = or(_T_775, _T_776) @[Mux.scala 27:72]
|
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|
node _T_833 = or(_T_832, _T_777) @[Mux.scala 27:72]
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node _T_834 = or(_T_833, _T_778) @[Mux.scala 27:72]
|
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node _T_835 = or(_T_834, _T_779) @[Mux.scala 27:72]
|
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node _T_836 = or(_T_835, _T_780) @[Mux.scala 27:72]
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|
node _T_837 = or(_T_836, _T_781) @[Mux.scala 27:72]
|
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node _T_838 = or(_T_837, _T_782) @[Mux.scala 27:72]
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node _T_839 = or(_T_838, _T_783) @[Mux.scala 27:72]
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node _T_840 = or(_T_839, _T_784) @[Mux.scala 27:72]
|
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node _T_841 = or(_T_840, _T_785) @[Mux.scala 27:72]
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|
node _T_842 = or(_T_841, _T_786) @[Mux.scala 27:72]
|
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|
node _T_843 = or(_T_842, _T_787) @[Mux.scala 27:72]
|
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|
node _T_844 = or(_T_843, _T_788) @[Mux.scala 27:72]
|
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|
node _T_845 = or(_T_844, _T_789) @[Mux.scala 27:72]
|
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|
node _T_846 = or(_T_845, _T_790) @[Mux.scala 27:72]
|
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|
node _T_847 = or(_T_846, _T_791) @[Mux.scala 27:72]
|
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|
node _T_848 = or(_T_847, _T_792) @[Mux.scala 27:72]
|
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|
node _T_849 = or(_T_848, _T_793) @[Mux.scala 27:72]
|
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|
node _T_850 = or(_T_849, _T_794) @[Mux.scala 27:72]
|
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|
node _T_851 = or(_T_850, _T_795) @[Mux.scala 27:72]
|
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|
node _T_852 = or(_T_851, _T_796) @[Mux.scala 27:72]
|
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|
node _T_853 = or(_T_852, _T_797) @[Mux.scala 27:72]
|
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|
node _T_854 = or(_T_853, _T_798) @[Mux.scala 27:72]
|
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|
node _T_855 = or(_T_854, _T_799) @[Mux.scala 27:72]
|
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|
node _T_856 = or(_T_855, _T_800) @[Mux.scala 27:72]
|
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|
node _T_857 = or(_T_856, _T_801) @[Mux.scala 27:72]
|
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|
node _T_858 = or(_T_857, _T_802) @[Mux.scala 27:72]
|
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|
node _T_859 = or(_T_858, _T_803) @[Mux.scala 27:72]
|
|
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|
node _T_860 = or(_T_859, _T_804) @[Mux.scala 27:72]
|
|
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|
node _T_861 = or(_T_860, _T_805) @[Mux.scala 27:72]
|
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|
node _T_862 = or(_T_861, _T_806) @[Mux.scala 27:72]
|
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|
node _T_863 = or(_T_862, _T_807) @[Mux.scala 27:72]
|
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|
node _T_864 = or(_T_863, _T_808) @[Mux.scala 27:72]
|
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|
node _T_865 = or(_T_864, _T_809) @[Mux.scala 27:72]
|
|
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|
node _T_866 = or(_T_865, _T_810) @[Mux.scala 27:72]
|
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|
node _T_867 = or(_T_866, _T_811) @[Mux.scala 27:72]
|
|
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|
node _T_868 = or(_T_867, _T_812) @[Mux.scala 27:72]
|
|
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|
|
node _T_869 = or(_T_868, _T_813) @[Mux.scala 27:72]
|
|
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|
node _T_870 = or(_T_869, _T_814) @[Mux.scala 27:72]
|
|
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|
node _T_871 = or(_T_870, _T_815) @[Mux.scala 27:72]
|
|
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|
node _T_872 = or(_T_871, _T_816) @[Mux.scala 27:72]
|
|
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|
node _T_873 = or(_T_872, _T_817) @[Mux.scala 27:72]
|
|
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|
node _T_874 = or(_T_873, _T_818) @[Mux.scala 27:72]
|
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|
node _T_875 = or(_T_874, _T_819) @[Mux.scala 27:72]
|
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|
node _T_876 = or(_T_875, _T_820) @[Mux.scala 27:72]
|
|
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|
|
node _T_877 = or(_T_876, _T_821) @[Mux.scala 27:72]
|
|
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|
node _T_878 = or(_T_877, _T_822) @[Mux.scala 27:72]
|
|
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|
|
node _T_879 = or(_T_878, _T_823) @[Mux.scala 27:72]
|
|
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|
|
node _T_880 = or(_T_879, _T_824) @[Mux.scala 27:72]
|
|
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|
node _T_881 = or(_T_880, _T_825) @[Mux.scala 27:72]
|
|
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|
|
node _T_882 = or(_T_881, _T_826) @[Mux.scala 27:72]
|
|
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|
|
node _T_883 = or(_T_882, _T_827) @[Mux.scala 27:72]
|
|
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|
|
node _T_884 = or(_T_883, _T_828) @[Mux.scala 27:72]
|
|
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|
|
node _T_885 = or(_T_884, _T_829) @[Mux.scala 27:72]
|
|
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|
|
node _T_886 = or(_T_885, _T_830) @[Mux.scala 27:72]
|
|
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|
|
node _T_887 = or(_T_886, _T_831) @[Mux.scala 27:72]
|
|
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|
|
wire _T_888 : UInt<1> @[Mux.scala 27:72]
|
|
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|
|
_T_888 <= _T_887 @[Mux.scala 27:72]
|
|
|
|
|
node _T_889 = and(_T_595, _T_888) @[dec_tlu_ctl.scala 2797:63]
|
|
|
|
|
io.mhpmc_inc_r[2] <= _T_889 @[dec_tlu_ctl.scala 2797:35]
|
|
|
|
|
node _T_890 = bits(io.mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2797:57]
|
|
|
|
|
node _T_891 = not(_T_890) @[dec_tlu_ctl.scala 2797:40]
|
|
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|
|
node _T_892 = eq(io.mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2798:42]
|
|
|
|
|
node _T_893 = bits(_T_892, 0, 0) @[dec_tlu_ctl.scala 2798:70]
|
|
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|
|
node _T_894 = eq(io.mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2799:42]
|
|
|
|
|
node _T_895 = bits(_T_894, 0, 0) @[dec_tlu_ctl.scala 2799:70]
|
|
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|
|
node _T_896 = eq(io.mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2800:42]
|
|
|
|
|
node _T_897 = bits(_T_896, 0, 0) @[dec_tlu_ctl.scala 2800:70]
|
|
|
|
|
node _T_898 = eq(io.mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2801:42]
|
|
|
|
|
node _T_899 = bits(_T_898, 0, 0) @[dec_tlu_ctl.scala 2801:70]
|
|
|
|
|
node _T_900 = not(io.illegal_r) @[dec_tlu_ctl.scala 2801:104]
|
|
|
|
|
node _T_901 = and(io.tlu_i0_commit_cmt, _T_900) @[dec_tlu_ctl.scala 2801:102]
|
|
|
|
|
node _T_902 = eq(io.mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2802:42]
|
|
|
|
|
node _T_903 = bits(_T_902, 0, 0) @[dec_tlu_ctl.scala 2802:70]
|
|
|
|
|
node _T_904 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2802:104]
|
|
|
|
|
node _T_905 = and(io.tlu_i0_commit_cmt, _T_904) @[dec_tlu_ctl.scala 2802:102]
|
|
|
|
|
node _T_906 = not(io.illegal_r) @[dec_tlu_ctl.scala 2802:125]
|
|
|
|
|
node _T_907 = and(_T_905, _T_906) @[dec_tlu_ctl.scala 2802:123]
|
|
|
|
|
node _T_908 = eq(io.mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2803:42]
|
|
|
|
|
node _T_909 = bits(_T_908, 0, 0) @[dec_tlu_ctl.scala 2803:70]
|
|
|
|
|
node _T_910 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2803:102]
|
|
|
|
|
node _T_911 = not(io.illegal_r) @[dec_tlu_ctl.scala 2803:125]
|
|
|
|
|
node _T_912 = and(_T_910, _T_911) @[dec_tlu_ctl.scala 2803:123]
|
|
|
|
|
node _T_913 = eq(io.mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2805:42]
|
|
|
|
|
node _T_914 = bits(_T_913, 0, 0) @[dec_tlu_ctl.scala 2805:70]
|
|
|
|
|
node _T_915 = eq(io.mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2806:42]
|
|
|
|
|
node _T_916 = bits(_T_915, 0, 0) @[dec_tlu_ctl.scala 2806:70]
|
|
|
|
|
node _T_917 = eq(io.mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2807:42]
|
|
|
|
|
node _T_918 = bits(_T_917, 0, 0) @[dec_tlu_ctl.scala 2807:70]
|
|
|
|
|
node _T_919 = eq(io.mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2808:42]
|
|
|
|
|
node _T_920 = bits(_T_919, 0, 0) @[dec_tlu_ctl.scala 2808:70]
|
|
|
|
|
node _T_921 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2808:99]
|
|
|
|
|
node _T_922 = eq(io.mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2809:42]
|
|
|
|
|
node _T_923 = bits(_T_922, 0, 0) @[dec_tlu_ctl.scala 2809:70]
|
|
|
|
|
node _T_924 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2809:113]
|
|
|
|
|
node _T_925 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2809:138]
|
|
|
|
|
node _T_926 = and(_T_924, _T_925) @[dec_tlu_ctl.scala 2809:136]
|
|
|
|
|
node _T_927 = eq(io.mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2810:42]
|
|
|
|
|
node _T_928 = bits(_T_927, 0, 0) @[dec_tlu_ctl.scala 2810:70]
|
|
|
|
|
node _T_929 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2810:99]
|
|
|
|
|
node _T_930 = eq(io.mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2811:42]
|
|
|
|
|
node _T_931 = bits(_T_930, 0, 0) @[dec_tlu_ctl.scala 2811:70]
|
|
|
|
|
node _T_932 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2811:99]
|
|
|
|
|
node _T_933 = eq(io.mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2812:42]
|
|
|
|
|
node _T_934 = bits(_T_933, 0, 0) @[dec_tlu_ctl.scala 2812:70]
|
|
|
|
|
node _T_935 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2812:99]
|
|
|
|
|
node _T_936 = and(_T_935, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2812:108]
|
|
|
|
|
node _T_937 = eq(io.mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2813:42]
|
|
|
|
|
node _T_938 = bits(_T_937, 0, 0) @[dec_tlu_ctl.scala 2813:70]
|
|
|
|
|
node _T_939 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2813:99]
|
|
|
|
|
node _T_940 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2813:150]
|
|
|
|
|
node _T_941 = and(_T_939, _T_940) @[dec_tlu_ctl.scala 2813:109]
|
|
|
|
|
node _T_942 = eq(io.mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2815:42]
|
|
|
|
|
node _T_943 = bits(_T_942, 0, 0) @[dec_tlu_ctl.scala 2815:67]
|
|
|
|
|
node _T_944 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2815:97]
|
|
|
|
|
node _T_945 = eq(io.mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2816:42]
|
|
|
|
|
node _T_946 = bits(_T_945, 0, 0) @[dec_tlu_ctl.scala 2816:67]
|
|
|
|
|
node _T_947 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2816:97]
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node _T_948 = eq(io.mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2817:42]
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node _T_949 = bits(_T_948, 0, 0) @[dec_tlu_ctl.scala 2817:67]
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node _T_950 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2817:97]
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node _T_951 = eq(io.mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2818:42]
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node _T_952 = bits(_T_951, 0, 0) @[dec_tlu_ctl.scala 2818:67]
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node _T_953 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2818:97]
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node _T_954 = eq(io.mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2819:42]
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node _T_955 = bits(_T_954, 0, 0) @[dec_tlu_ctl.scala 2819:67]
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node _T_956 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2819:97]
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node _T_957 = eq(io.mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2820:42]
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node _T_958 = bits(_T_957, 0, 0) @[dec_tlu_ctl.scala 2820:67]
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node _T_959 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2820:97]
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node _T_960 = eq(io.mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2821:42]
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node _T_961 = bits(_T_960, 0, 0) @[dec_tlu_ctl.scala 2821:67]
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node _T_962 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2821:97]
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node _T_963 = eq(io.mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2822:42]
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node _T_964 = bits(_T_963, 0, 0) @[dec_tlu_ctl.scala 2822:67]
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node _T_965 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2822:97]
|
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node _T_966 = eq(io.mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2823:42]
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node _T_967 = bits(_T_966, 0, 0) @[dec_tlu_ctl.scala 2823:67]
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node _T_968 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2823:97]
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node _T_969 = eq(io.mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2824:42]
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node _T_970 = bits(_T_969, 0, 0) @[dec_tlu_ctl.scala 2824:67]
|
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node _T_971 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2824:97]
|
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node _T_972 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2824:130]
|
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node _T_973 = or(_T_971, _T_972) @[dec_tlu_ctl.scala 2824:109]
|
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node _T_974 = eq(io.mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2826:42]
|
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|
|
node _T_975 = bits(_T_974, 0, 0) @[dec_tlu_ctl.scala 2826:70]
|
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node _T_976 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2826:103]
|
|
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|
node _T_977 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2826:128]
|
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node _T_978 = and(_T_976, _T_977) @[dec_tlu_ctl.scala 2826:126]
|
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node _T_979 = eq(io.mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2827:42]
|
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|
|
node _T_980 = bits(_T_979, 0, 0) @[dec_tlu_ctl.scala 2827:70]
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|
node _T_981 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2827:105]
|
|
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|
|
node _T_982 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2827:130]
|
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|
|
node _T_983 = and(_T_981, _T_982) @[dec_tlu_ctl.scala 2827:128]
|
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|
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node _T_984 = eq(io.mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2828:42]
|
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node _T_985 = bits(_T_984, 0, 0) @[dec_tlu_ctl.scala 2828:70]
|
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|
|
node _T_986 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2828:118]
|
|
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|
node _T_987 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2828:143]
|
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|
node _T_988 = and(_T_986, _T_987) @[dec_tlu_ctl.scala 2828:141]
|
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node _T_989 = eq(io.mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2829:42]
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node _T_990 = bits(_T_989, 0, 0) @[dec_tlu_ctl.scala 2829:70]
|
|
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|
node _T_991 = eq(io.mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2830:42]
|
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node _T_992 = bits(_T_991, 0, 0) @[dec_tlu_ctl.scala 2830:70]
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|
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node _T_993 = eq(io.mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2831:42]
|
|
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|
node _T_994 = bits(_T_993, 0, 0) @[dec_tlu_ctl.scala 2831:70]
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|
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node _T_995 = eq(io.mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2832:42]
|
|
|
|
|
node _T_996 = bits(_T_995, 0, 0) @[dec_tlu_ctl.scala 2832:70]
|
|
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|
|
node _T_997 = eq(io.mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2833:42]
|
|
|
|
|
node _T_998 = bits(_T_997, 0, 0) @[dec_tlu_ctl.scala 2833:70]
|
|
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|
|
node _T_999 = eq(io.mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2834:42]
|
|
|
|
|
node _T_1000 = bits(_T_999, 0, 0) @[dec_tlu_ctl.scala 2834:70]
|
|
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|
|
node _T_1001 = eq(io.mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2835:42]
|
|
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|
|
node _T_1002 = bits(_T_1001, 0, 0) @[dec_tlu_ctl.scala 2835:70]
|
|
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|
|
node _T_1003 = eq(io.mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2836:42]
|
|
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|
|
node _T_1004 = bits(_T_1003, 0, 0) @[dec_tlu_ctl.scala 2836:70]
|
|
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|
|
node _T_1005 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2836:106]
|
|
|
|
|
node _T_1006 = or(_T_1005, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2836:128]
|
|
|
|
|
node _T_1007 = eq(io.mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2837:42]
|
|
|
|
|
node _T_1008 = bits(_T_1007, 0, 0) @[dec_tlu_ctl.scala 2837:70]
|
|
|
|
|
node _T_1009 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2837:100]
|
|
|
|
|
node _T_1010 = or(_T_1009, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2837:125]
|
|
|
|
|
node _T_1011 = eq(io.mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2838:42]
|
|
|
|
|
node _T_1012 = bits(_T_1011, 0, 0) @[dec_tlu_ctl.scala 2838:70]
|
|
|
|
|
node _T_1013 = eq(io.mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2839:42]
|
|
|
|
|
node _T_1014 = bits(_T_1013, 0, 0) @[dec_tlu_ctl.scala 2839:70]
|
|
|
|
|
node _T_1015 = eq(io.mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2840:42]
|
|
|
|
|
node _T_1016 = bits(_T_1015, 0, 0) @[dec_tlu_ctl.scala 2840:70]
|
|
|
|
|
node _T_1017 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2840:105]
|
|
|
|
|
node _T_1018 = and(_T_1017, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2840:137]
|
|
|
|
|
node _T_1019 = eq(io.mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2842:42]
|
|
|
|
|
node _T_1020 = bits(_T_1019, 0, 0) @[dec_tlu_ctl.scala 2842:70]
|
|
|
|
|
node _T_1021 = eq(io.mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2843:42]
|
|
|
|
|
node _T_1022 = bits(_T_1021, 0, 0) @[dec_tlu_ctl.scala 2843:70]
|
|
|
|
|
node _T_1023 = eq(io.mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2844:42]
|
|
|
|
|
node _T_1024 = bits(_T_1023, 0, 0) @[dec_tlu_ctl.scala 2844:70]
|
|
|
|
|
node _T_1025 = eq(io.mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2845:42]
|
|
|
|
|
node _T_1026 = bits(_T_1025, 0, 0) @[dec_tlu_ctl.scala 2845:70]
|
|
|
|
|
node _T_1027 = eq(io.mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2846:42]
|
|
|
|
|
node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2846:70]
|
|
|
|
|
node _T_1029 = eq(io.mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2847:42]
|
|
|
|
|
node _T_1030 = bits(_T_1029, 0, 0) @[dec_tlu_ctl.scala 2847:70]
|
|
|
|
|
node _T_1031 = eq(io.mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2848:42]
|
|
|
|
|
node _T_1032 = bits(_T_1031, 0, 0) @[dec_tlu_ctl.scala 2848:70]
|
|
|
|
|
node _T_1033 = eq(io.mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2849:42]
|
|
|
|
|
node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2849:70]
|
|
|
|
|
node _T_1035 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2849:92]
|
|
|
|
|
node _T_1036 = bits(_T_1035, 0, 0) @[dec_tlu_ctl.scala 2849:92]
|
|
|
|
|
node _T_1037 = not(_T_1036) @[dec_tlu_ctl.scala 2849:81]
|
|
|
|
|
node _T_1038 = eq(io.mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2850:42]
|
|
|
|
|
node _T_1039 = bits(_T_1038, 0, 0) @[dec_tlu_ctl.scala 2850:70]
|
|
|
|
|
node _T_1040 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2850:92]
|
|
|
|
|
node _T_1041 = bits(_T_1040, 0, 0) @[dec_tlu_ctl.scala 2850:92]
|
|
|
|
|
node _T_1042 = not(_T_1041) @[dec_tlu_ctl.scala 2850:81]
|
|
|
|
|
node _T_1043 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2850:115]
|
|
|
|
|
node _T_1044 = bits(io.mie, 5, 0) @[dec_tlu_ctl.scala 2850:129]
|
|
|
|
|
node _T_1045 = and(_T_1043, _T_1044) @[dec_tlu_ctl.scala 2850:121]
|
|
|
|
|
node _T_1046 = orr(_T_1045) @[dec_tlu_ctl.scala 2850:136]
|
|
|
|
|
node _T_1047 = and(_T_1042, _T_1046) @[dec_tlu_ctl.scala 2850:106]
|
|
|
|
|
node _T_1048 = eq(io.mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2851:42]
|
|
|
|
|
node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2851:70]
|
|
|
|
|
node _T_1050 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2851:99]
|
|
|
|
|
node _T_1051 = eq(io.mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2852:42]
|
|
|
|
|
node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2852:70]
|
|
|
|
|
node _T_1053 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2852:102]
|
|
|
|
|
node _T_1054 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2852:133]
|
|
|
|
|
node _T_1055 = and(_T_1053, _T_1054) @[dec_tlu_ctl.scala 2852:131]
|
|
|
|
|
node _T_1056 = eq(io.mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2853:42]
|
|
|
|
|
node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2853:70]
|
|
|
|
|
node _T_1058 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2853:102]
|
|
|
|
|
node _T_1059 = eq(io.illegal_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 2853:134]
|
|
|
|
|
node _T_1060 = and(_T_1058, _T_1059) @[dec_tlu_ctl.scala 2853:132]
|
|
|
|
|
node _T_1061 = eq(io.mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2855:42]
|
|
|
|
|
node _T_1062 = bits(_T_1061, 0, 0) @[dec_tlu_ctl.scala 2855:70]
|
|
|
|
|
node _T_1063 = eq(io.mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2856:42]
|
|
|
|
|
node _T_1064 = bits(_T_1063, 0, 0) @[dec_tlu_ctl.scala 2856:70]
|
|
|
|
|
node _T_1065 = eq(io.mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2857:42]
|
|
|
|
|
node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2857:70]
|
|
|
|
|
node _T_1067 = eq(io.mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2858:42]
|
|
|
|
|
node _T_1068 = bits(_T_1067, 0, 0) @[dec_tlu_ctl.scala 2858:70]
|
|
|
|
|
node _T_1069 = eq(io.mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2859:42]
|
|
|
|
|
node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2859:70]
|
|
|
|
|
node _T_1071 = mux(_T_893, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1072 = mux(_T_895, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1073 = mux(_T_897, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1074 = mux(_T_899, _T_901, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1075 = mux(_T_903, _T_907, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1076 = mux(_T_909, _T_912, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1077 = mux(_T_914, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1078 = mux(_T_916, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1079 = mux(_T_918, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1080 = mux(_T_920, _T_921, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1081 = mux(_T_923, _T_926, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1082 = mux(_T_928, _T_929, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1083 = mux(_T_931, _T_932, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1084 = mux(_T_934, _T_936, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1085 = mux(_T_938, _T_941, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1086 = mux(_T_943, _T_944, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1087 = mux(_T_946, _T_947, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1088 = mux(_T_949, _T_950, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1089 = mux(_T_952, _T_953, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1090 = mux(_T_955, _T_956, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1091 = mux(_T_958, _T_959, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1092 = mux(_T_961, _T_962, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1093 = mux(_T_964, _T_965, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1094 = mux(_T_967, _T_968, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1095 = mux(_T_970, _T_973, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1096 = mux(_T_975, _T_978, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1097 = mux(_T_980, _T_983, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1098 = mux(_T_985, _T_988, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1099 = mux(_T_990, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1100 = mux(_T_992, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1101 = mux(_T_994, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1102 = mux(_T_996, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1103 = mux(_T_998, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1104 = mux(_T_1000, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1105 = mux(_T_1002, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1106 = mux(_T_1004, _T_1006, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1107 = mux(_T_1008, _T_1010, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1108 = mux(_T_1012, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1109 = mux(_T_1014, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1110 = mux(_T_1016, _T_1018, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1111 = mux(_T_1020, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1112 = mux(_T_1022, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1113 = mux(_T_1024, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1114 = mux(_T_1026, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1115 = mux(_T_1028, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1116 = mux(_T_1030, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1117 = mux(_T_1032, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1118 = mux(_T_1034, _T_1037, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1119 = mux(_T_1039, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1120 = mux(_T_1049, _T_1050, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1121 = mux(_T_1052, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1122 = mux(_T_1057, _T_1060, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1123 = mux(_T_1062, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1124 = mux(_T_1064, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1125 = mux(_T_1066, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1126 = mux(_T_1068, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1127 = mux(_T_1070, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1128 = or(_T_1071, _T_1072) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1129 = or(_T_1128, _T_1073) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1130 = or(_T_1129, _T_1074) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1131 = or(_T_1130, _T_1075) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1132 = or(_T_1131, _T_1076) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1133 = or(_T_1132, _T_1077) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1134 = or(_T_1133, _T_1078) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1135 = or(_T_1134, _T_1079) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1136 = or(_T_1135, _T_1080) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1137 = or(_T_1136, _T_1081) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1138 = or(_T_1137, _T_1082) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1139 = or(_T_1138, _T_1083) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1140 = or(_T_1139, _T_1084) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1141 = or(_T_1140, _T_1085) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1142 = or(_T_1141, _T_1086) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1143 = or(_T_1142, _T_1087) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1144 = or(_T_1143, _T_1088) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1145 = or(_T_1144, _T_1089) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1146 = or(_T_1145, _T_1090) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1147 = or(_T_1146, _T_1091) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1148 = or(_T_1147, _T_1092) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1149 = or(_T_1148, _T_1093) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1150 = or(_T_1149, _T_1094) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1151 = or(_T_1150, _T_1095) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1152 = or(_T_1151, _T_1096) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1153 = or(_T_1152, _T_1097) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1154 = or(_T_1153, _T_1098) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1155 = or(_T_1154, _T_1099) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1156 = or(_T_1155, _T_1100) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1157 = or(_T_1156, _T_1101) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1158 = or(_T_1157, _T_1102) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1159 = or(_T_1158, _T_1103) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1160 = or(_T_1159, _T_1104) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1161 = or(_T_1160, _T_1105) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1162 = or(_T_1161, _T_1106) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1163 = or(_T_1162, _T_1107) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1164 = or(_T_1163, _T_1108) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1165 = or(_T_1164, _T_1109) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1166 = or(_T_1165, _T_1110) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1167 = or(_T_1166, _T_1111) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1168 = or(_T_1167, _T_1112) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1169 = or(_T_1168, _T_1113) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1170 = or(_T_1169, _T_1114) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1171 = or(_T_1170, _T_1115) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1172 = or(_T_1171, _T_1116) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1173 = or(_T_1172, _T_1117) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1174 = or(_T_1173, _T_1118) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1175 = or(_T_1174, _T_1119) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1176 = or(_T_1175, _T_1120) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1177 = or(_T_1176, _T_1121) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1178 = or(_T_1177, _T_1122) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1179 = or(_T_1178, _T_1123) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1180 = or(_T_1179, _T_1124) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1181 = or(_T_1180, _T_1125) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1182 = or(_T_1181, _T_1126) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1183 = or(_T_1182, _T_1127) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_1184 : UInt<1> @[Mux.scala 27:72]
|
|
|
|
|
_T_1184 <= _T_1183 @[Mux.scala 27:72]
|
|
|
|
|
node _T_1185 = and(_T_891, _T_1184) @[dec_tlu_ctl.scala 2797:63]
|
|
|
|
|
io.mhpmc_inc_r[3] <= _T_1185 @[dec_tlu_ctl.scala 2797:35]
|
|
|
|
|
wire _T_1186 : UInt<1>
|
|
|
|
|
_T_1186 <= UInt<1>("h00")
|
|
|
|
|
node _T_1187 = xor(io.mdseac_locked_ns, _T_1186) @[lib.scala 470:21]
|
|
|
|
|
node _T_1188 = orr(_T_1187) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1189 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1188 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1189 <= io.mdseac_locked_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1186 <= _T_1189 @[lib.scala 473:16]
|
|
|
|
|
io.mdseac_locked_f <= _T_1186 @[dec_tlu_ctl.scala 2870:52]
|
|
|
|
|
wire _T_1190 : UInt<1>
|
|
|
|
|
_T_1190 <= UInt<1>("h00")
|
|
|
|
|
node _T_1191 = xor(io.lsu_single_ecc_error_r, _T_1190) @[lib.scala 470:21]
|
|
|
|
|
node _T_1192 = orr(_T_1191) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1193 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1192 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1193 <= io.lsu_single_ecc_error_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1190 <= _T_1193 @[lib.scala 473:16]
|
|
|
|
|
io.lsu_single_ecc_error_r_d1 <= _T_1190 @[dec_tlu_ctl.scala 2871:52]
|
|
|
|
|
wire _T_1194 : UInt
|
|
|
|
|
_T_1194 <= UInt<1>("h00")
|
|
|
|
|
node _T_1195 = xor(io.lsu_exc_valid_r, _T_1194) @[lib.scala 448:21]
|
|
|
|
|
node _T_1196 = orr(_T_1195) @[lib.scala 448:29]
|
|
|
|
|
reg _T_1197 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1196 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1197 <= io.lsu_exc_valid_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1194 <= _T_1197 @[lib.scala 451:16]
|
|
|
|
|
io.lsu_exc_valid_r_d1 <= _T_1194 @[dec_tlu_ctl.scala 2872:52]
|
|
|
|
|
wire _T_1198 : UInt<1>
|
|
|
|
|
_T_1198 <= UInt<1>("h00")
|
|
|
|
|
node _T_1199 = xor(io.lsu_i0_exc_r, _T_1198) @[lib.scala 470:21]
|
|
|
|
|
node _T_1200 = orr(_T_1199) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1201 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1200 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1201 <= io.lsu_i0_exc_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1198 <= _T_1201 @[lib.scala 473:16]
|
|
|
|
|
io.lsu_i0_exc_r_d1 <= _T_1198 @[dec_tlu_ctl.scala 2873:52]
|
|
|
|
|
wire _T_1202 : UInt<1>
|
|
|
|
|
_T_1202 <= UInt<1>("h00")
|
|
|
|
|
node _T_1203 = xor(io.take_ext_int_start, _T_1202) @[lib.scala 470:21]
|
|
|
|
|
node _T_1204 = orr(_T_1203) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1205 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1204 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1205 <= io.take_ext_int_start @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1202 <= _T_1205 @[lib.scala 473:16]
|
|
|
|
|
io.take_ext_int_start_d1 <= _T_1202 @[dec_tlu_ctl.scala 2874:52]
|
|
|
|
|
wire _T_1206 : UInt<1>
|
|
|
|
|
_T_1206 <= UInt<1>("h00")
|
|
|
|
|
node _T_1207 = xor(io.take_ext_int_start_d1, _T_1206) @[lib.scala 470:21]
|
|
|
|
|
node _T_1208 = orr(_T_1207) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1209 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1208 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1209 <= io.take_ext_int_start_d1 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1206 <= _T_1209 @[lib.scala 473:16]
|
|
|
|
|
io.take_ext_int_start_d2 <= _T_1206 @[dec_tlu_ctl.scala 2875:52]
|
|
|
|
|
wire _T_1210 : UInt<1>
|
|
|
|
|
_T_1210 <= UInt<1>("h00")
|
|
|
|
|
node _T_1211 = xor(io.take_ext_int_start_d2, _T_1210) @[lib.scala 470:21]
|
|
|
|
|
node _T_1212 = orr(_T_1211) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1213 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1212 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1213 <= io.take_ext_int_start_d2 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1210 <= _T_1213 @[lib.scala 473:16]
|
|
|
|
|
io.take_ext_int_start_d3 <= _T_1210 @[dec_tlu_ctl.scala 2876:52]
|
|
|
|
|
wire _T_1214 : UInt<1>
|
|
|
|
|
_T_1214 <= UInt<1>("h00")
|
|
|
|
|
node _T_1215 = xor(io.ext_int_freeze, _T_1214) @[lib.scala 470:21]
|
|
|
|
|
node _T_1216 = orr(_T_1215) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1217 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1216 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1217 <= io.ext_int_freeze @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1214 <= _T_1217 @[lib.scala 473:16]
|
|
|
|
|
io.ext_int_freeze_d1 <= _T_1214 @[dec_tlu_ctl.scala 2877:52]
|
|
|
|
|
wire _T_1218 : UInt
|
|
|
|
|
_T_1218 <= UInt<1>("h00")
|
|
|
|
|
node _T_1219 = xor(io.mip_ns, _T_1218) @[lib.scala 448:21]
|
|
|
|
|
node _T_1220 = orr(_T_1219) @[lib.scala 448:29]
|
|
|
|
|
reg _T_1221 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1220 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1221 <= io.mip_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1218 <= _T_1221 @[lib.scala 451:16]
|
|
|
|
|
io.mip <= _T_1218 @[dec_tlu_ctl.scala 2878:52]
|
|
|
|
|
node _T_1222 = not(io.wr_mcycleh_r) @[dec_tlu_ctl.scala 2879:80]
|
|
|
|
|
node _T_1223 = and(io.mcyclel_cout, _T_1222) @[dec_tlu_ctl.scala 2879:78]
|
|
|
|
|
node _T_1224 = and(_T_1223, io.mcyclel_cout_in) @[dec_tlu_ctl.scala 2879:97]
|
|
|
|
|
wire _T_1225 : UInt<1>
|
|
|
|
|
_T_1225 <= UInt<1>("h00")
|
|
|
|
|
node _T_1226 = xor(_T_1224, _T_1225) @[lib.scala 470:21]
|
|
|
|
|
node _T_1227 = orr(_T_1226) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1228 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1227 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1228 <= _T_1224 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1225 <= _T_1228 @[lib.scala 473:16]
|
|
|
|
|
io.mcyclel_cout_f <= _T_1225 @[dec_tlu_ctl.scala 2879:52]
|
|
|
|
|
wire _T_1229 : UInt<1>
|
|
|
|
|
_T_1229 <= UInt<1>("h00")
|
|
|
|
|
node _T_1230 = xor(io.minstret_enable, _T_1229) @[lib.scala 470:21]
|
|
|
|
|
node _T_1231 = orr(_T_1230) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1232 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1231 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1232 <= io.minstret_enable @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1229 <= _T_1232 @[lib.scala 473:16]
|
|
|
|
|
io.minstret_enable_f <= _T_1229 @[dec_tlu_ctl.scala 2880:52]
|
|
|
|
|
wire _T_1233 : UInt<1>
|
|
|
|
|
_T_1233 <= UInt<1>("h00")
|
|
|
|
|
node _T_1234 = xor(io.minstretl_cout_ns, _T_1233) @[lib.scala 470:21]
|
|
|
|
|
node _T_1235 = orr(_T_1234) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1236 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1235 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1236 <= io.minstretl_cout_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1233 <= _T_1236 @[lib.scala 473:16]
|
|
|
|
|
io.minstretl_cout_f <= _T_1233 @[dec_tlu_ctl.scala 2881:52]
|
|
|
|
|
wire _T_1237 : UInt<1>
|
|
|
|
|
_T_1237 <= UInt<1>("h00")
|
|
|
|
|
node _T_1238 = xor(io.fw_halted_ns, _T_1237) @[lib.scala 470:21]
|
|
|
|
|
node _T_1239 = orr(_T_1238) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1240 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1239 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1240 <= io.fw_halted_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1237 <= _T_1240 @[lib.scala 473:16]
|
|
|
|
|
io.fw_halted <= _T_1237 @[dec_tlu_ctl.scala 2882:52]
|
|
|
|
|
wire _T_1241 : UInt
|
|
|
|
|
_T_1241 <= UInt<1>("h00")
|
|
|
|
|
node _T_1242 = xor(io.meicidpl_ns, _T_1241) @[lib.scala 448:21]
|
|
|
|
|
node _T_1243 = orr(_T_1242) @[lib.scala 448:29]
|
|
|
|
|
reg _T_1244 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1243 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1244 <= io.meicidpl_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1241 <= _T_1244 @[lib.scala 451:16]
|
|
|
|
|
io.meicidpl <= _T_1241 @[dec_tlu_ctl.scala 2883:52]
|
|
|
|
|
wire _T_1245 : UInt<1>
|
|
|
|
|
_T_1245 <= UInt<1>("h00")
|
|
|
|
|
node _T_1246 = xor(io.icache_rd_valid, _T_1245) @[lib.scala 470:21]
|
|
|
|
|
node _T_1247 = orr(_T_1246) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1248 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1247 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1248 <= io.icache_rd_valid @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1245 <= _T_1248 @[lib.scala 473:16]
|
|
|
|
|
io.icache_rd_valid_f <= _T_1245 @[dec_tlu_ctl.scala 2884:52]
|
|
|
|
|
wire _T_1249 : UInt<1>
|
|
|
|
|
_T_1249 <= UInt<1>("h00")
|
|
|
|
|
node _T_1250 = xor(io.icache_wr_valid, _T_1249) @[lib.scala 470:21]
|
|
|
|
|
node _T_1251 = orr(_T_1250) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1252 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1251 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1252 <= io.icache_wr_valid @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1249 <= _T_1252 @[lib.scala 473:16]
|
|
|
|
|
io.icache_wr_valid_f <= _T_1249 @[dec_tlu_ctl.scala 2885:52]
|
|
|
|
|
wire _T_1253 : UInt<1>[4]
|
|
|
|
|
_T_1253[0] <= io.mhpmc_inc_r[0]
|
|
|
|
|
_T_1253[1] <= io.mhpmc_inc_r[1]
|
|
|
|
|
_T_1253[2] <= io.mhpmc_inc_r[2]
|
|
|
|
|
_T_1253[3] <= io.mhpmc_inc_r[3]
|
|
|
|
|
node _T_1254 = xor(io.mhpmc_inc_r[0], _T_1253[0]) @[lib.scala 518:68]
|
|
|
|
|
node _T_1255 = orr(_T_1254) @[lib.scala 518:82]
|
|
|
|
|
node _T_1256 = xor(io.mhpmc_inc_r[1], _T_1253[1]) @[lib.scala 518:68]
|
|
|
|
|
node _T_1257 = orr(_T_1256) @[lib.scala 518:82]
|
|
|
|
|
node _T_1258 = xor(io.mhpmc_inc_r[2], _T_1253[2]) @[lib.scala 518:68]
|
|
|
|
|
node _T_1259 = orr(_T_1258) @[lib.scala 518:82]
|
|
|
|
|
node _T_1260 = xor(io.mhpmc_inc_r[3], _T_1253[3]) @[lib.scala 518:68]
|
|
|
|
|
node _T_1261 = orr(_T_1260) @[lib.scala 518:82]
|
|
|
|
|
node _T_1262 = or(_T_1255, _T_1257) @[lib.scala 518:97]
|
|
|
|
|
node _T_1263 = or(_T_1262, _T_1259) @[lib.scala 518:97]
|
|
|
|
|
node _T_1264 = or(_T_1263, _T_1261) @[lib.scala 518:97]
|
|
|
|
|
wire _T_1265 : UInt<1>[4] @[lib.scala 521:46]
|
|
|
|
|
_T_1265[0] <= UInt<1>("h00") @[lib.scala 521:46]
|
|
|
|
|
_T_1265[1] <= UInt<1>("h00") @[lib.scala 521:46]
|
|
|
|
|
_T_1265[2] <= UInt<1>("h00") @[lib.scala 521:46]
|
|
|
|
|
_T_1265[3] <= UInt<1>("h00") @[lib.scala 521:46]
|
|
|
|
|
reg _T_1266 : UInt<1>[4], io.free_l2clk with : (reset => (reset, _T_1265)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1264 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1266[0] <= io.mhpmc_inc_r[0] @[Reg.scala 28:23]
|
|
|
|
|
_T_1266[1] <= io.mhpmc_inc_r[1] @[Reg.scala 28:23]
|
|
|
|
|
_T_1266[2] <= io.mhpmc_inc_r[2] @[Reg.scala 28:23]
|
|
|
|
|
_T_1266[3] <= io.mhpmc_inc_r[3] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1253[0] <= _T_1266[0] @[lib.scala 521:16]
|
|
|
|
|
_T_1253[1] <= _T_1266[1] @[lib.scala 521:16]
|
|
|
|
|
_T_1253[2] <= _T_1266[2] @[lib.scala 521:16]
|
|
|
|
|
_T_1253[3] <= _T_1266[3] @[lib.scala 521:16]
|
|
|
|
|
io.mhpmc_inc_r_d1[0] <= _T_1253[0] @[dec_tlu_ctl.scala 2886:52]
|
|
|
|
|
io.mhpmc_inc_r_d1[1] <= _T_1253[1] @[dec_tlu_ctl.scala 2886:52]
|
|
|
|
|
io.mhpmc_inc_r_d1[2] <= _T_1253[2] @[dec_tlu_ctl.scala 2886:52]
|
|
|
|
|
io.mhpmc_inc_r_d1[3] <= _T_1253[3] @[dec_tlu_ctl.scala 2886:52]
|
|
|
|
|
wire _T_1267 : UInt<1>
|
|
|
|
|
_T_1267 <= UInt<1>("h00")
|
|
|
|
|
node _T_1268 = xor(io.perfcnt_halted, _T_1267) @[lib.scala 470:21]
|
|
|
|
|
node _T_1269 = orr(_T_1268) @[lib.scala 470:29]
|
|
|
|
|
reg _T_1270 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1269 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1270 <= io.perfcnt_halted @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1267 <= _T_1270 @[lib.scala 473:16]
|
|
|
|
|
io.perfcnt_halted_d1 <= _T_1267 @[dec_tlu_ctl.scala 2887:52]
|
|
|
|
|
wire _T_1271 : UInt
|
|
|
|
|
_T_1271 <= UInt<1>("h00")
|
|
|
|
|
node _T_1272 = xor(io.mstatus_ns, _T_1271) @[lib.scala 448:21]
|
|
|
|
|
node _T_1273 = orr(_T_1272) @[lib.scala 448:29]
|
|
|
|
|
reg _T_1274 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1273 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1274 <= io.mstatus_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_1271 <= _T_1274 @[lib.scala 451:16]
|
|
|
|
|
io.mstatus <= _T_1271 @[dec_tlu_ctl.scala 2888:52]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_42 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_42 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_42 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_43 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_43 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_43 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_44 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_44 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_44 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_45 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_45 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_45 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
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|
|
extmodule gated_latch_46 :
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|
|
output Q : Clock
|
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|
|
input CK : Clock
|
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|
|
input EN : UInt<1>
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|
|
input SE : UInt<1>
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|
defname = gated_latch
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module rvclkhdr_46 :
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|
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input clock : Clock
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|
|
input reset : Reset
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|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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|
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|
|
|
inst clkhdr of gated_latch_46 @[lib.scala 334:26]
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|
|
clkhdr.SE is invalid
|
|
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|
|
clkhdr.EN is invalid
|
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|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
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|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
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|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_47 :
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output Q : Clock
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|
|
input CK : Clock
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|
|
input EN : UInt<1>
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|
|
input SE : UInt<1>
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|
|
defname = gated_latch
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module rvclkhdr_47 :
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|
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input clock : Clock
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|
|
input reset : Reset
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|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_47 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
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|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
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|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
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|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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|
|
extmodule gated_latch_48 :
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|
|
output Q : Clock
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|
|
input CK : Clock
|
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|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
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|
|
module rvclkhdr_48 :
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|
|
input clock : Clock
|
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|
|
input reset : Reset
|
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|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_48 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
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|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
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|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
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|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
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|
|
extmodule gated_latch_49 :
|
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|
|
output Q : Clock
|
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|
|
input CK : Clock
|
|
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|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
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|
|
|
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|
|
module rvclkhdr_49 :
|
|
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|
|
input clock : Clock
|
|
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|
|
input reset : Reset
|
|
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|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_49 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
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|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_50 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_50 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_50 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_51 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_51 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_51 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_52 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_52 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_52 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_53 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_53 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_53 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
module perf_csr :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : AsyncReset
|
|
|
|
|
output io : {flip free_l2clk : Clock, flip scan_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dcsr : UInt<16>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip mhpme_vec : UInt<10>[4], flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip mhpmc_inc_r : UInt<1>[4], flip mhpmc_inc_r_d1 : UInt<1>[4], flip perfcnt_halted_d1 : UInt<1>, mhpmc3h : UInt<32>, mhpmc3 : UInt<32>, mhpmc4h : UInt<32>, mhpmc4 : UInt<32>, mhpmc5h : UInt<32>, mhpmc5 : UInt<32>, mhpmc6h : UInt<32>, mhpmc6 : UInt<32>, mhpme3 : UInt<10>, mhpme4 : UInt<10>, mhpme5 : UInt<10>, mhpme6 : UInt<10>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>}
|
|
|
|
|
|
|
|
|
|
node _T = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2578:63]
|
|
|
|
|
node _T_1 = and(io.dec_tlu_dbg_halted, _T) @[dec_tlu_ctl.scala 2578:54]
|
|
|
|
|
node perfcnt_halted = or(_T_1, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2578:77]
|
|
|
|
|
node _T_2 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2579:77]
|
|
|
|
|
node _T_3 = and(io.dec_tlu_dbg_halted, _T_2) @[dec_tlu_ctl.scala 2579:68]
|
|
|
|
|
node _T_4 = eq(_T_3, UInt<1>("h00")) @[dec_tlu_ctl.scala 2579:44]
|
|
|
|
|
node _T_5 = bits(_T_4, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_6 = mux(_T_5, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_7 = bits(io.mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2579:114]
|
|
|
|
|
node _T_8 = bits(io.mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2579:133]
|
|
|
|
|
node _T_9 = bits(io.mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2579:152]
|
|
|
|
|
node _T_10 = bits(io.mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2579:171]
|
|
|
|
|
node _T_11 = cat(_T_9, _T_10) @[Cat.scala 29:58]
|
|
|
|
|
node _T_12 = cat(_T_7, _T_8) @[Cat.scala 29:58]
|
|
|
|
|
node _T_13 = cat(_T_12, _T_11) @[Cat.scala 29:58]
|
|
|
|
|
node perfcnt_during_sleep = and(_T_6, _T_13) @[dec_tlu_ctl.scala 2579:93]
|
|
|
|
|
node _T_14 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2582:101]
|
|
|
|
|
node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2582:80]
|
|
|
|
|
node _T_16 = and(io.perfcnt_halted_d1, _T_15) @[dec_tlu_ctl.scala 2582:78]
|
|
|
|
|
node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2582:55]
|
|
|
|
|
node _T_18 = and(io.mhpmc_inc_r_d1[0], _T_17) @[dec_tlu_ctl.scala 2582:53]
|
|
|
|
|
io.dec_tlu_perfcnt0 <= _T_18 @[dec_tlu_ctl.scala 2582:29]
|
|
|
|
|
node _T_19 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2583:101]
|
|
|
|
|
node _T_20 = eq(_T_19, UInt<1>("h00")) @[dec_tlu_ctl.scala 2583:80]
|
|
|
|
|
node _T_21 = and(io.perfcnt_halted_d1, _T_20) @[dec_tlu_ctl.scala 2583:78]
|
|
|
|
|
node _T_22 = eq(_T_21, UInt<1>("h00")) @[dec_tlu_ctl.scala 2583:55]
|
|
|
|
|
node _T_23 = and(io.mhpmc_inc_r_d1[1], _T_22) @[dec_tlu_ctl.scala 2583:53]
|
|
|
|
|
io.dec_tlu_perfcnt1 <= _T_23 @[dec_tlu_ctl.scala 2583:29]
|
|
|
|
|
node _T_24 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2584:101]
|
|
|
|
|
node _T_25 = eq(_T_24, UInt<1>("h00")) @[dec_tlu_ctl.scala 2584:80]
|
|
|
|
|
node _T_26 = and(io.perfcnt_halted_d1, _T_25) @[dec_tlu_ctl.scala 2584:78]
|
|
|
|
|
node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2584:55]
|
|
|
|
|
node _T_28 = and(io.mhpmc_inc_r_d1[2], _T_27) @[dec_tlu_ctl.scala 2584:53]
|
|
|
|
|
io.dec_tlu_perfcnt2 <= _T_28 @[dec_tlu_ctl.scala 2584:29]
|
|
|
|
|
node _T_29 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2585:101]
|
|
|
|
|
node _T_30 = eq(_T_29, UInt<1>("h00")) @[dec_tlu_ctl.scala 2585:80]
|
|
|
|
|
node _T_31 = and(io.perfcnt_halted_d1, _T_30) @[dec_tlu_ctl.scala 2585:78]
|
|
|
|
|
node _T_32 = eq(_T_31, UInt<1>("h00")) @[dec_tlu_ctl.scala 2585:55]
|
|
|
|
|
node _T_33 = and(io.mhpmc_inc_r_d1[3], _T_32) @[dec_tlu_ctl.scala 2585:53]
|
|
|
|
|
io.dec_tlu_perfcnt3 <= _T_33 @[dec_tlu_ctl.scala 2585:29]
|
|
|
|
|
node _T_34 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2591:72]
|
|
|
|
|
node _T_35 = eq(_T_34, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2591:79]
|
|
|
|
|
node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_35) @[dec_tlu_ctl.scala 2591:50]
|
|
|
|
|
node _T_36 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2592:30]
|
|
|
|
|
node _T_37 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2592:68]
|
|
|
|
|
node _T_38 = or(_T_36, _T_37) @[dec_tlu_ctl.scala 2592:46]
|
|
|
|
|
node _T_39 = orr(io.mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2592:96]
|
|
|
|
|
node mhpmc3_wr_en1 = and(_T_38, _T_39) @[dec_tlu_ctl.scala 2592:73]
|
|
|
|
|
node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2593:43]
|
|
|
|
|
node _T_40 = bits(io.mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2596:41]
|
|
|
|
|
node _T_41 = bits(io.mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2596:57]
|
|
|
|
|
node _T_42 = cat(_T_40, _T_41) @[Cat.scala 29:58]
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|
|
node _T_43 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58]
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|
|
node _T_44 = add(_T_42, _T_43) @[dec_tlu_ctl.scala 2596:65]
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node mhpmc3_incr = tail(_T_44, 1) @[dec_tlu_ctl.scala 2596:65]
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node _T_45 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2597:43]
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node _T_46 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2597:83]
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|
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node mhpmc3_ns = mux(_T_45, io.dec_csr_wrdata_r, _T_46) @[dec_tlu_ctl.scala 2597:28]
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node _T_47 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2599:52]
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inst rvclkhdr of rvclkhdr_42 @[lib.scala 404:23]
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|
|
rvclkhdr.clock <= clock
|
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|
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rvclkhdr.reset <= reset
|
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|
|
rvclkhdr.io.clk <= io.free_l2clk @[lib.scala 406:18]
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rvclkhdr.io.en <= _T_47 @[lib.scala 407:17]
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rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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reg _T_48 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
when _T_47 : @[Reg.scala 28:19]
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_T_48 <= mhpmc3_ns @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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|
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io.mhpmc3 <= _T_48 @[dec_tlu_ctl.scala 2599:19]
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node _T_49 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2601:73]
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node _T_50 = eq(_T_49, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2601:80]
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node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_50) @[dec_tlu_ctl.scala 2601:51]
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node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2602:45]
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node _T_51 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2603:45]
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node _T_52 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2603:85]
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node mhpmc3h_ns = mux(_T_51, io.dec_csr_wrdata_r, _T_52) @[dec_tlu_ctl.scala 2603:29]
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node _T_53 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2605:56]
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inst rvclkhdr_1 of rvclkhdr_43 @[lib.scala 404:23]
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|
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rvclkhdr_1.clock <= clock
|
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|
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rvclkhdr_1.reset <= reset
|
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|
|
rvclkhdr_1.io.clk <= io.free_l2clk @[lib.scala 406:18]
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|
|
rvclkhdr_1.io.en <= _T_53 @[lib.scala 407:17]
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|
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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|
|
reg _T_54 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
|
when _T_53 : @[Reg.scala 28:19]
|
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|
|
_T_54 <= mhpmc3h_ns @[Reg.scala 28:23]
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|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mhpmc3h <= _T_54 @[dec_tlu_ctl.scala 2605:20]
|
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|
|
node _T_55 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2612:72]
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|
|
node _T_56 = eq(_T_55, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2612:79]
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|
|
node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_56) @[dec_tlu_ctl.scala 2612:50]
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node _T_57 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2613:30]
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|
node _T_58 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2613:68]
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|
|
node _T_59 = or(_T_57, _T_58) @[dec_tlu_ctl.scala 2613:46]
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|
|
node _T_60 = orr(io.mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2613:96]
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|
|
node mhpmc4_wr_en1 = and(_T_59, _T_60) @[dec_tlu_ctl.scala 2613:73]
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|
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|
|
node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2614:43]
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|
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|
|
node _T_61 = bits(io.mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2618:41]
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|
|
node _T_62 = bits(io.mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2618:57]
|
|
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|
|
node _T_63 = cat(_T_61, _T_62) @[Cat.scala 29:58]
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|
|
node _T_64 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
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|
|
node _T_65 = add(_T_63, _T_64) @[dec_tlu_ctl.scala 2618:65]
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|
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|
|
node mhpmc4_incr = tail(_T_65, 1) @[dec_tlu_ctl.scala 2618:65]
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|
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|
|
node _T_66 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2619:43]
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|
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|
|
node _T_67 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2619:70]
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|
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|
|
node _T_68 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2619:89]
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|
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|
|
node mhpmc4_ns = mux(_T_66, _T_67, _T_68) @[dec_tlu_ctl.scala 2619:28]
|
|
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|
|
node _T_69 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2620:53]
|
|
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|
|
inst rvclkhdr_2 of rvclkhdr_44 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_2.clock <= clock
|
|
|
|
|
rvclkhdr_2.reset <= reset
|
|
|
|
|
rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_2.io.en <= _T_69 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_70 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_69 : @[Reg.scala 28:19]
|
|
|
|
|
_T_70 <= mhpmc4_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mhpmc4 <= _T_70 @[dec_tlu_ctl.scala 2620:19]
|
|
|
|
|
node _T_71 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2622:73]
|
|
|
|
|
node _T_72 = eq(_T_71, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2622:80]
|
|
|
|
|
node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_72) @[dec_tlu_ctl.scala 2622:51]
|
|
|
|
|
node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2623:45]
|
|
|
|
|
node _T_73 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2624:45]
|
|
|
|
|
node _T_74 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2624:85]
|
|
|
|
|
node mhpmc4h_ns = mux(_T_73, io.dec_csr_wrdata_r, _T_74) @[dec_tlu_ctl.scala 2624:29]
|
|
|
|
|
node _T_75 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2625:56]
|
|
|
|
|
inst rvclkhdr_3 of rvclkhdr_45 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_3.clock <= clock
|
|
|
|
|
rvclkhdr_3.reset <= reset
|
|
|
|
|
rvclkhdr_3.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_3.io.en <= _T_75 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_76 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_75 : @[Reg.scala 28:19]
|
|
|
|
|
_T_76 <= mhpmc4h_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mhpmc4h <= _T_76 @[dec_tlu_ctl.scala 2625:20]
|
|
|
|
|
node _T_77 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2631:72]
|
|
|
|
|
node _T_78 = eq(_T_77, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2631:79]
|
|
|
|
|
node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_78) @[dec_tlu_ctl.scala 2631:50]
|
|
|
|
|
node _T_79 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2632:30]
|
|
|
|
|
node _T_80 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2632:68]
|
|
|
|
|
node _T_81 = or(_T_79, _T_80) @[dec_tlu_ctl.scala 2632:46]
|
|
|
|
|
node _T_82 = orr(io.mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2632:96]
|
|
|
|
|
node mhpmc5_wr_en1 = and(_T_81, _T_82) @[dec_tlu_ctl.scala 2632:73]
|
|
|
|
|
node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2633:43]
|
|
|
|
|
node _T_83 = bits(io.mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2635:41]
|
|
|
|
|
node _T_84 = bits(io.mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2635:57]
|
|
|
|
|
node _T_85 = cat(_T_83, _T_84) @[Cat.scala 29:58]
|
|
|
|
|
node _T_86 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_87 = add(_T_85, _T_86) @[dec_tlu_ctl.scala 2635:65]
|
|
|
|
|
node mhpmc5_incr = tail(_T_87, 1) @[dec_tlu_ctl.scala 2635:65]
|
|
|
|
|
node _T_88 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2636:43]
|
|
|
|
|
node _T_89 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2636:83]
|
|
|
|
|
node mhpmc5_ns = mux(_T_88, io.dec_csr_wrdata_r, _T_89) @[dec_tlu_ctl.scala 2636:28]
|
|
|
|
|
node _T_90 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2638:53]
|
|
|
|
|
inst rvclkhdr_4 of rvclkhdr_46 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_4.clock <= clock
|
|
|
|
|
rvclkhdr_4.reset <= reset
|
|
|
|
|
rvclkhdr_4.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_4.io.en <= _T_90 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_91 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_90 : @[Reg.scala 28:19]
|
|
|
|
|
_T_91 <= mhpmc5_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mhpmc5 <= _T_91 @[dec_tlu_ctl.scala 2638:19]
|
|
|
|
|
node _T_92 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2640:73]
|
|
|
|
|
node _T_93 = eq(_T_92, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2640:80]
|
|
|
|
|
node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_93) @[dec_tlu_ctl.scala 2640:51]
|
|
|
|
|
node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2641:45]
|
|
|
|
|
node _T_94 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2642:45]
|
|
|
|
|
node _T_95 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2642:85]
|
|
|
|
|
node mhpmc5h_ns = mux(_T_94, io.dec_csr_wrdata_r, _T_95) @[dec_tlu_ctl.scala 2642:29]
|
|
|
|
|
node _T_96 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2644:56]
|
|
|
|
|
inst rvclkhdr_5 of rvclkhdr_47 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_5.clock <= clock
|
|
|
|
|
rvclkhdr_5.reset <= reset
|
|
|
|
|
rvclkhdr_5.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_5.io.en <= _T_96 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_97 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_96 : @[Reg.scala 28:19]
|
|
|
|
|
_T_97 <= mhpmc5h_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mhpmc5h <= _T_97 @[dec_tlu_ctl.scala 2644:20]
|
|
|
|
|
node _T_98 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2651:72]
|
|
|
|
|
node _T_99 = eq(_T_98, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2651:79]
|
|
|
|
|
node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_99) @[dec_tlu_ctl.scala 2651:50]
|
|
|
|
|
node _T_100 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2652:30]
|
|
|
|
|
node _T_101 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2652:68]
|
|
|
|
|
node _T_102 = or(_T_100, _T_101) @[dec_tlu_ctl.scala 2652:46]
|
|
|
|
|
node _T_103 = orr(io.mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2652:96]
|
|
|
|
|
node mhpmc6_wr_en1 = and(_T_102, _T_103) @[dec_tlu_ctl.scala 2652:73]
|
|
|
|
|
node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2653:43]
|
|
|
|
|
node _T_104 = bits(io.mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2655:41]
|
|
|
|
|
node _T_105 = bits(io.mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2655:57]
|
|
|
|
|
node _T_106 = cat(_T_104, _T_105) @[Cat.scala 29:58]
|
|
|
|
|
node _T_107 = cat(UInt<63>("h00"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_108 = add(_T_106, _T_107) @[dec_tlu_ctl.scala 2655:65]
|
|
|
|
|
node mhpmc6_incr = tail(_T_108, 1) @[dec_tlu_ctl.scala 2655:65]
|
|
|
|
|
node _T_109 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2656:43]
|
|
|
|
|
node _T_110 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2656:83]
|
|
|
|
|
node mhpmc6_ns = mux(_T_109, io.dec_csr_wrdata_r, _T_110) @[dec_tlu_ctl.scala 2656:28]
|
|
|
|
|
node _T_111 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2659:53]
|
|
|
|
|
inst rvclkhdr_6 of rvclkhdr_48 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_6.clock <= clock
|
|
|
|
|
rvclkhdr_6.reset <= reset
|
|
|
|
|
rvclkhdr_6.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_6.io.en <= _T_111 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_112 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_111 : @[Reg.scala 28:19]
|
|
|
|
|
_T_112 <= mhpmc6_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mhpmc6 <= _T_112 @[dec_tlu_ctl.scala 2659:19]
|
|
|
|
|
node _T_113 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2661:73]
|
|
|
|
|
node _T_114 = eq(_T_113, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2661:80]
|
|
|
|
|
node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_114) @[dec_tlu_ctl.scala 2661:51]
|
|
|
|
|
node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2662:45]
|
|
|
|
|
node _T_115 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2663:45]
|
|
|
|
|
node _T_116 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2663:85]
|
|
|
|
|
node mhpmc6h_ns = mux(_T_115, io.dec_csr_wrdata_r, _T_116) @[dec_tlu_ctl.scala 2663:29]
|
|
|
|
|
node _T_117 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2665:56]
|
|
|
|
|
inst rvclkhdr_7 of rvclkhdr_49 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_7.clock <= clock
|
|
|
|
|
rvclkhdr_7.reset <= reset
|
|
|
|
|
rvclkhdr_7.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_7.io.en <= _T_117 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_118 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_117 : @[Reg.scala 28:19]
|
|
|
|
|
_T_118 <= mhpmc6h_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mhpmc6h <= _T_118 @[dec_tlu_ctl.scala 2665:20]
|
|
|
|
|
node _T_119 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2671:50]
|
|
|
|
|
node _T_120 = gt(_T_119, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2671:56]
|
|
|
|
|
node _T_121 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2671:94]
|
|
|
|
|
node _T_122 = orr(_T_121) @[dec_tlu_ctl.scala 2671:102]
|
|
|
|
|
node _T_123 = or(_T_120, _T_122) @[dec_tlu_ctl.scala 2671:72]
|
|
|
|
|
node _T_124 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2672:38]
|
|
|
|
|
node _T_125 = lt(_T_124, UInt<10>("h0200")) @[dec_tlu_ctl.scala 2672:44]
|
|
|
|
|
node _T_126 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2672:82]
|
|
|
|
|
node _T_127 = gt(_T_126, UInt<10>("h038")) @[dec_tlu_ctl.scala 2672:88]
|
|
|
|
|
node _T_128 = and(_T_125, _T_127) @[dec_tlu_ctl.scala 2672:60]
|
|
|
|
|
node _T_129 = or(_T_123, _T_128) @[dec_tlu_ctl.scala 2671:107]
|
|
|
|
|
node _T_130 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2673:38]
|
|
|
|
|
node _T_131 = lt(_T_130, UInt<10>("h036")) @[dec_tlu_ctl.scala 2673:44]
|
|
|
|
|
node _T_132 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2673:82]
|
|
|
|
|
node _T_133 = gt(_T_132, UInt<10>("h032")) @[dec_tlu_ctl.scala 2673:88]
|
|
|
|
|
node _T_134 = and(_T_131, _T_133) @[dec_tlu_ctl.scala 2673:60]
|
|
|
|
|
node _T_135 = or(_T_129, _T_134) @[dec_tlu_ctl.scala 2672:103]
|
|
|
|
|
node _T_136 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2674:37]
|
|
|
|
|
node _T_137 = eq(_T_136, UInt<10>("h01d")) @[dec_tlu_ctl.scala 2674:43]
|
|
|
|
|
node _T_138 = or(_T_135, _T_137) @[dec_tlu_ctl.scala 2673:103]
|
|
|
|
|
node _T_139 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2674:81]
|
|
|
|
|
node _T_140 = eq(_T_139, UInt<10>("h021")) @[dec_tlu_ctl.scala 2674:87]
|
|
|
|
|
node zero_event_r = or(_T_138, _T_140) @[dec_tlu_ctl.scala 2674:59]
|
|
|
|
|
node _T_141 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2676:71]
|
|
|
|
|
node event_r = mux(zero_event_r, UInt<10>("h00"), _T_141) @[dec_tlu_ctl.scala 2676:26]
|
|
|
|
|
node _T_142 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2677:70]
|
|
|
|
|
node _T_143 = eq(_T_142, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2677:77]
|
|
|
|
|
node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_143) @[dec_tlu_ctl.scala 2677:48]
|
|
|
|
|
node _T_144 = bits(wr_mhpme3_r, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
inst rvclkhdr_8 of rvclkhdr_50 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_8.clock <= clock
|
|
|
|
|
rvclkhdr_8.reset <= reset
|
|
|
|
|
rvclkhdr_8.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_8.io.en <= _T_144 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_145 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_144 : @[Reg.scala 28:19]
|
|
|
|
|
_T_145 <= event_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mhpme3 <= _T_145 @[dec_tlu_ctl.scala 2679:19]
|
|
|
|
|
node _T_146 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2684:70]
|
|
|
|
|
node _T_147 = eq(_T_146, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2684:77]
|
|
|
|
|
node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_147) @[dec_tlu_ctl.scala 2684:48]
|
|
|
|
|
node _T_148 = bits(wr_mhpme4_r, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
inst rvclkhdr_9 of rvclkhdr_51 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_9.clock <= clock
|
|
|
|
|
rvclkhdr_9.reset <= reset
|
|
|
|
|
rvclkhdr_9.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_9.io.en <= _T_148 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_149 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_148 : @[Reg.scala 28:19]
|
|
|
|
|
_T_149 <= event_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mhpme4 <= _T_149 @[dec_tlu_ctl.scala 2685:19]
|
|
|
|
|
node _T_150 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2691:70]
|
|
|
|
|
node _T_151 = eq(_T_150, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2691:77]
|
|
|
|
|
node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_151) @[dec_tlu_ctl.scala 2691:48]
|
|
|
|
|
node _T_152 = bits(wr_mhpme5_r, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
inst rvclkhdr_10 of rvclkhdr_52 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_10.clock <= clock
|
|
|
|
|
rvclkhdr_10.reset <= reset
|
|
|
|
|
rvclkhdr_10.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_10.io.en <= _T_152 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_152 : @[Reg.scala 28:19]
|
|
|
|
|
_T_153 <= event_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mhpme5 <= _T_153 @[dec_tlu_ctl.scala 2692:19]
|
|
|
|
|
node _T_154 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2698:70]
|
|
|
|
|
node _T_155 = eq(_T_154, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2698:77]
|
|
|
|
|
node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_155) @[dec_tlu_ctl.scala 2698:48]
|
|
|
|
|
node _T_156 = bits(wr_mhpme6_r, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
inst rvclkhdr_11 of rvclkhdr_53 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_11.clock <= clock
|
|
|
|
|
rvclkhdr_11.reset <= reset
|
|
|
|
|
rvclkhdr_11.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_11.io.en <= _T_156 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_157 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_156 : @[Reg.scala 28:19]
|
|
|
|
|
_T_157 <= event_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mhpme6 <= _T_157 @[dec_tlu_ctl.scala 2699:19]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_54 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_54 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_54 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_55 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_55 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_55 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_56 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_56 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_56 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_57 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_57 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_57 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_58 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_58 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_58 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_59 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_59 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_59 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_60 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_60 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_60 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_61 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_61 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_61 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_62 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_62 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_62 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_63 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_63 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_63 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_64 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_64 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_64 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_65 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_65 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_65 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_66 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_66 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_66 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_67 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_67 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_67 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_68 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_68 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_68 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_69 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_69 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_69 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_70 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_70 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_70 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_71 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_71 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_71 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_72 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_72 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_72 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_73 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_73 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_73 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_74 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_74 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_74 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_75 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_75 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_75 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_76 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_76 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_76 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_77 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_77 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_77 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_78 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_78 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_78 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_79 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_79 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_79 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_80 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_80 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_80 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_81 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_81 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_81 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_82 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_82 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_82 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_83 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_83 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_83 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_84 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_84 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_84 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_85 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_85 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_85 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
extmodule gated_latch_86 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_86 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_86 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_87 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_87 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_87 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_88 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_88 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_88 @[lib.scala 334:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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module csr_tlu :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip free_l2clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_picio_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_trace_disable : UInt<1>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip cs
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wire miccme_ce_req : UInt<1>
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miccme_ce_req <= UInt<1>("h00")
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wire mice_ce_req : UInt<1>
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mice_ce_req <= UInt<1>("h00")
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wire mdccme_ce_req : UInt<1>
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mdccme_ce_req <= UInt<1>("h00")
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wire pc_r_d1 : UInt<31>
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pc_r_d1 <= UInt<1>("h00")
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wire mpmc_b_ns : UInt<1>
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mpmc_b_ns <= UInt<1>("h00")
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wire mpmc_b : UInt<1>
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mpmc_b <= UInt<1>("h00")
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wire mcycleh : UInt<32>
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mcycleh <= UInt<1>("h00")
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wire wr_minstreth_r : UInt<1>
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wr_minstreth_r <= UInt<1>("h00")
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wire minstretl : UInt<32>
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minstretl <= UInt<1>("h00")
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wire minstreth : UInt<32>
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minstreth <= UInt<1>("h00")
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wire mfdc_ns : UInt<16>
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mfdc_ns <= UInt<1>("h00")
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wire mfdc_int : UInt<16>
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mfdc_int <= UInt<1>("h00")
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wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1413:47]
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wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1414:73]
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wire wr_meicpct_r : UInt<1>
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wr_meicpct_r <= UInt<1>("h00")
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wire force_halt_ctr_f : UInt<32>
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force_halt_ctr_f <= UInt<1>("h00")
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wire mdccmect_inc : UInt<27>
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mdccmect_inc <= UInt<1>("h00")
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wire miccmect_inc : UInt<27>
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miccmect_inc <= UInt<1>("h00")
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wire micect_inc : UInt<27>
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micect_inc <= UInt<1>("h00")
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wire mdseac_en : UInt<1>
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mdseac_en <= UInt<1>("h00")
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wire mie : UInt<6>
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mie <= UInt<1>("h00")
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wire mcyclel : UInt<32>
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mcyclel <= UInt<1>("h00")
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wire mscratch : UInt<32>
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mscratch <= UInt<1>("h00")
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wire mcause : UInt<32>
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mcause <= UInt<1>("h00")
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wire mscause : UInt<4>
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mscause <= UInt<1>("h00")
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wire mtval : UInt<32>
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mtval <= UInt<1>("h00")
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wire meicurpl : UInt<4>
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meicurpl <= UInt<1>("h00")
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wire meipt : UInt<4>
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meipt <= UInt<1>("h00")
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wire mfdc : UInt<19>
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mfdc <= UInt<1>("h00")
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wire mtsel : UInt<2>
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mtsel <= UInt<1>("h00")
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wire micect : UInt<32>
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micect <= UInt<1>("h00")
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wire miccmect : UInt<32>
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miccmect <= UInt<1>("h00")
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wire mdccmect : UInt<32>
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mdccmect <= UInt<1>("h00")
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wire mfdht : UInt<6>
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mfdht <= UInt<1>("h00")
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wire mfdhs : UInt<2>
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mfdhs <= UInt<1>("h00")
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wire mcountinhibit : UInt<7>
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mcountinhibit <= UInt<1>("h00")
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wire mpmc : UInt<1>
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mpmc <= UInt<1>("h00")
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wire dicad1 : UInt<32>
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dicad1 <= UInt<1>("h00")
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inst perfmux_flop of perf_mux_and_flops @[dec_tlu_ctl.scala 1455:34]
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perfmux_flop.clock <= clock
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perfmux_flop.reset <= reset
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inst perf_csrs of perf_csr @[dec_tlu_ctl.scala 1456:31]
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perf_csrs.clock <= clock
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perf_csrs.reset <= reset
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node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1472:52]
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node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1472:50]
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node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1472:75]
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node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1472:73]
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io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1472:30]
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node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1473:71]
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node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1473:78]
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node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1473:49]
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node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1476:35]
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node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1476:46]
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node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1479:18]
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node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1479:32]
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node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1479:57]
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node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1479:81]
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node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1479:81]
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node _T_12 = cat(_T_11, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1480:31]
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node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1480:56]
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node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1480:89]
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node _T_16 = cat(_T_15, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1481:30]
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node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1481:28]
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node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1481:54]
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node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1481:83]
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node _T_21 = cat(UInt<1>("h01"), _T_20) @[Cat.scala 29:58]
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node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1482:39]
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node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1482:63]
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node _T_24 = cat(_T_23, UInt<1>("h01")) @[Cat.scala 29:58]
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node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1483:33]
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node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1483:31]
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node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1483:57]
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node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1483:90]
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node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1483:114]
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node _T_30 = cat(_T_28, _T_29) @[Cat.scala 29:58]
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node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:18]
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node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:34]
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node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1484:32]
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node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:59]
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node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1484:57]
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node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1484:72]
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node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1484:70]
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node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1484:94]
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node _T_39 = mux(_T_9, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_40 = mux(_T_14, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_41 = mux(_T_19, _T_21, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_42 = mux(_T_22, _T_24, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_43 = mux(_T_27, _T_30, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_44 = mux(_T_38, io.mstatus, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_45 = or(_T_39, _T_40) @[Mux.scala 27:72]
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node _T_46 = or(_T_45, _T_41) @[Mux.scala 27:72]
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node _T_47 = or(_T_46, _T_42) @[Mux.scala 27:72]
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node _T_48 = or(_T_47, _T_43) @[Mux.scala 27:72]
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node _T_49 = or(_T_48, _T_44) @[Mux.scala 27:72]
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wire mstatus_ns : UInt<2> @[Mux.scala 27:72]
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mstatus_ns <= _T_49 @[Mux.scala 27:72]
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node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1489:40]
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node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1489:40]
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node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1489:57]
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node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1489:97]
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node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1489:88]
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node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1489:54]
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io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1489:27]
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node _T_56 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1500:69]
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node _T_57 = eq(_T_56, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1500:76]
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node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_57) @[dec_tlu_ctl.scala 1500:47]
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node _T_58 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1501:47]
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node _T_59 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1501:75]
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node mtvec_ns = cat(_T_58, _T_59) @[Cat.scala 29:58]
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node _T_60 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1502:49]
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inst rvclkhdr of rvclkhdr_54 @[lib.scala 404:23]
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rvclkhdr.clock <= clock
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rvclkhdr.reset <= reset
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rvclkhdr.io.clk <= clock @[lib.scala 406:18]
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rvclkhdr.io.en <= _T_60 @[lib.scala 407:17]
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rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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reg _T_61 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_60 : @[Reg.scala 28:19]
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_T_61 <= mtvec_ns @[Reg.scala 28:23]
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|
skip @[Reg.scala 28:19]
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|
|
io.mtvec <= _T_61 @[dec_tlu_ctl.scala 1502:18]
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node _T_62 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1514:37]
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node ce_int = or(_T_62, mice_ce_req) @[dec_tlu_ctl.scala 1514:53]
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node _T_63 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58]
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node _T_64 = cat(_T_63, io.soft_int_sync) @[Cat.scala 29:58]
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node _T_65 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58]
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node _T_66 = cat(_T_65, io.dec_timer_t1_pulse) @[Cat.scala 29:58]
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|
node mip_ns = cat(_T_66, _T_64) @[Cat.scala 29:58]
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node _T_67 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1530:67]
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node _T_68 = eq(_T_67, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1530:74]
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node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_68) @[dec_tlu_ctl.scala 1530:45]
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node _T_69 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1531:35]
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node _T_70 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1531:66]
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node _T_71 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1531:95]
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node _T_72 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1531:120]
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node _T_73 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1531:144]
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node _T_74 = cat(_T_72, _T_73) @[Cat.scala 29:58]
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|
node _T_75 = cat(_T_70, _T_71) @[Cat.scala 29:58]
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|
node _T_76 = cat(_T_75, _T_74) @[Cat.scala 29:58]
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|
|
node _T_77 = mux(_T_69, _T_76, mie) @[dec_tlu_ctl.scala 1531:25]
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|
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|
|
io.mie_ns <= _T_77 @[dec_tlu_ctl.scala 1531:19]
|
|
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|
|
reg _T_78 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1533:24]
|
|
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|
|
_T_78 <= io.mie_ns @[dec_tlu_ctl.scala 1533:24]
|
|
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|
|
mie <= _T_78 @[dec_tlu_ctl.scala 1532:13]
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|
|
node _T_79 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1539:70]
|
|
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|
|
node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_79) @[dec_tlu_ctl.scala 1539:61]
|
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|
|
node _T_80 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1541:71]
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|
|
node _T_81 = eq(_T_80, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1541:78]
|
|
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|
|
node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_81) @[dec_tlu_ctl.scala 1541:49]
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|
|
node _T_82 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1543:87]
|
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|
|
node _T_83 = and(io.dec_tlu_dbg_halted, _T_82) @[dec_tlu_ctl.scala 1543:78]
|
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|
|
node _T_84 = or(kill_ebreak_count_r, _T_83) @[dec_tlu_ctl.scala 1543:53]
|
|
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|
|
node _T_85 = or(_T_84, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1543:101]
|
|
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|
|
node _T_86 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1543:143]
|
|
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|
|
node _T_87 = or(_T_85, _T_86) @[dec_tlu_ctl.scala 1543:128]
|
|
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|
|
node mcyclel_cout_in = not(_T_87) @[dec_tlu_ctl.scala 1543:31]
|
|
|
|
|
wire mcyclel_inc1 : UInt<9>
|
|
|
|
|
mcyclel_inc1 <= UInt<1>("h00")
|
|
|
|
|
wire mcyclel_inc2 : UInt<25>
|
|
|
|
|
mcyclel_inc2 <= UInt<1>("h00")
|
|
|
|
|
node _T_88 = bits(mcyclel, 7, 0) @[dec_tlu_ctl.scala 1548:32]
|
|
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|
|
node _T_89 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58]
|
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|
|
node _T_90 = add(_T_88, _T_89) @[dec_tlu_ctl.scala 1548:38]
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|
|
mcyclel_inc1 <= _T_90 @[dec_tlu_ctl.scala 1548:22]
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|
|
node _T_91 = bits(mcyclel, 31, 8) @[dec_tlu_ctl.scala 1549:32]
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|
|
node _T_92 = bits(mcyclel_inc1, 8, 8) @[dec_tlu_ctl.scala 1549:70]
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|
node _T_93 = cat(UInt<23>("h00"), _T_92) @[Cat.scala 29:58]
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|
|
node _T_94 = add(_T_91, _T_93) @[dec_tlu_ctl.scala 1549:39]
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|
|
mcyclel_inc2 <= _T_94 @[dec_tlu_ctl.scala 1549:22]
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|
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|
|
node _T_95 = bits(mcyclel_inc2, 23, 0) @[dec_tlu_ctl.scala 1550:47]
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|
|
node _T_96 = bits(mcyclel_inc1, 7, 0) @[dec_tlu_ctl.scala 1550:66]
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|
|
|
node mcyclel_inc = cat(_T_95, _T_96) @[Cat.scala 29:58]
|
|
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|
|
node _T_97 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1551:43]
|
|
|
|
|
node _T_98 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1551:83]
|
|
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|
|
node mcyclel_ns = mux(_T_97, io.dec_csr_wrdata_r, _T_98) @[dec_tlu_ctl.scala 1551:29]
|
|
|
|
|
node _T_99 = bits(mcyclel_inc2, 24, 24) @[dec_tlu_ctl.scala 1552:40]
|
|
|
|
|
node mcyclel_cout = bits(_T_99, 0, 0) @[dec_tlu_ctl.scala 1552:45]
|
|
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|
|
node _T_100 = bits(mcyclel_ns, 31, 8) @[dec_tlu_ctl.scala 1553:41]
|
|
|
|
|
node _T_101 = bits(mcyclel_inc1, 8, 8) @[dec_tlu_ctl.scala 1553:78]
|
|
|
|
|
node _T_102 = and(_T_101, mcyclel_cout_in) @[dec_tlu_ctl.scala 1553:82]
|
|
|
|
|
node _T_103 = bits(_T_102, 0, 0) @[dec_tlu_ctl.scala 1553:108]
|
|
|
|
|
node _T_104 = or(wr_mcyclel_r, _T_103) @[dec_tlu_ctl.scala 1553:63]
|
|
|
|
|
node _T_105 = bits(_T_104, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
inst rvclkhdr_1 of rvclkhdr_55 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_1.clock <= clock
|
|
|
|
|
rvclkhdr_1.reset <= reset
|
|
|
|
|
rvclkhdr_1.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_1.io.en <= _T_105 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_106 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_105 : @[Reg.scala 28:19]
|
|
|
|
|
_T_106 <= _T_100 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_107 = bits(mcyclel_ns, 7, 0) @[dec_tlu_ctl.scala 1553:163]
|
|
|
|
|
node _T_108 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1553:184]
|
|
|
|
|
node _T_109 = bits(_T_108, 0, 0) @[dec_tlu_ctl.scala 1553:210]
|
|
|
|
|
inst rvclkhdr_2 of rvclkhdr_56 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_2.clock <= clock
|
|
|
|
|
rvclkhdr_2.reset <= reset
|
|
|
|
|
rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_2.io.en <= _T_109 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_110 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_109 : @[Reg.scala 28:19]
|
|
|
|
|
_T_110 <= _T_107 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_111 = cat(_T_106, _T_110) @[Cat.scala 29:58]
|
|
|
|
|
mcyclel <= _T_111 @[dec_tlu_ctl.scala 1553:17]
|
|
|
|
|
node _T_112 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1560:71]
|
|
|
|
|
node _T_113 = eq(_T_112, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1560:78]
|
|
|
|
|
node wr_mcycleh_r = and(io.dec_csr_wen_r_mod, _T_113) @[dec_tlu_ctl.scala 1560:49]
|
|
|
|
|
node _T_114 = cat(UInt<31>("h00"), perfmux_flop.io.mcyclel_cout_f) @[Cat.scala 29:58]
|
|
|
|
|
node _T_115 = add(mcycleh, _T_114) @[dec_tlu_ctl.scala 1562:35]
|
|
|
|
|
node mcycleh_inc = tail(_T_115, 1) @[dec_tlu_ctl.scala 1562:35]
|
|
|
|
|
node _T_116 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1563:43]
|
|
|
|
|
node mcycleh_ns = mux(_T_116, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1563:29]
|
|
|
|
|
node _T_117 = or(wr_mcycleh_r, perfmux_flop.io.mcyclel_cout_f) @[dec_tlu_ctl.scala 1565:53]
|
|
|
|
|
node _T_118 = bits(_T_117, 0, 0) @[dec_tlu_ctl.scala 1565:87]
|
|
|
|
|
inst rvclkhdr_3 of rvclkhdr_57 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_3.clock <= clock
|
|
|
|
|
rvclkhdr_3.reset <= reset
|
|
|
|
|
rvclkhdr_3.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_3.io.en <= _T_118 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_119 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_118 : @[Reg.scala 28:19]
|
|
|
|
|
_T_119 <= mcycleh_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mcycleh <= _T_119 @[dec_tlu_ctl.scala 1565:17]
|
|
|
|
|
node _T_120 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1579:81]
|
|
|
|
|
node _T_121 = or(_T_120, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1579:94]
|
|
|
|
|
node _T_122 = or(_T_121, io.illegal_r) @[dec_tlu_ctl.scala 1579:122]
|
|
|
|
|
node _T_123 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1579:152]
|
|
|
|
|
node _T_124 = or(_T_122, _T_123) @[dec_tlu_ctl.scala 1579:137]
|
|
|
|
|
node _T_125 = eq(_T_124, UInt<1>("h00")) @[dec_tlu_ctl.scala 1579:67]
|
|
|
|
|
node _T_126 = and(io.dec_tlu_i0_valid_r, _T_125) @[dec_tlu_ctl.scala 1579:65]
|
|
|
|
|
node i0_valid_no_ebreak_ecall_r = bits(_T_126, 0, 0) @[dec_tlu_ctl.scala 1579:164]
|
|
|
|
|
node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1581:73]
|
|
|
|
|
node _T_128 = eq(_T_127, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1581:80]
|
|
|
|
|
node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1581:51]
|
|
|
|
|
wire minstretl_inc1 : UInt<9>
|
|
|
|
|
minstretl_inc1 <= UInt<1>("h00")
|
|
|
|
|
wire minstretl_inc2 : UInt<25>
|
|
|
|
|
minstretl_inc2 <= UInt<1>("h00")
|
|
|
|
|
node _T_129 = bits(minstretl, 7, 0) @[dec_tlu_ctl.scala 1585:36]
|
|
|
|
|
node _T_130 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_131 = add(_T_129, _T_130) @[dec_tlu_ctl.scala 1585:42]
|
|
|
|
|
minstretl_inc1 <= _T_131 @[dec_tlu_ctl.scala 1585:24]
|
|
|
|
|
node _T_132 = bits(minstretl, 31, 8) @[dec_tlu_ctl.scala 1586:36]
|
|
|
|
|
node _T_133 = bits(minstretl_inc1, 8, 8) @[dec_tlu_ctl.scala 1586:75]
|
|
|
|
|
node _T_134 = cat(UInt<23>("h00"), _T_133) @[Cat.scala 29:58]
|
|
|
|
|
node _T_135 = add(_T_132, _T_134) @[dec_tlu_ctl.scala 1586:43]
|
|
|
|
|
minstretl_inc2 <= _T_135 @[dec_tlu_ctl.scala 1586:24]
|
|
|
|
|
node minstretl_cout = bits(minstretl_inc2, 24, 24) @[dec_tlu_ctl.scala 1587:44]
|
|
|
|
|
node _T_136 = bits(minstretl_inc2, 23, 0) @[dec_tlu_ctl.scala 1588:47]
|
|
|
|
|
node _T_137 = bits(minstretl_inc1, 7, 0) @[dec_tlu_ctl.scala 1588:68]
|
|
|
|
|
node minstretl_inc = cat(_T_136, _T_137) @[Cat.scala 29:58]
|
|
|
|
|
node _T_138 = and(i0_valid_no_ebreak_ecall_r, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 1589:59]
|
|
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|
|
node minstret_enable = or(_T_138, wr_minstretl_r) @[dec_tlu_ctl.scala 1589:83]
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|
|
node _T_139 = eq(wr_minstreth_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1590:50]
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|
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|
|
node _T_140 = and(minstretl_cout, _T_139) @[dec_tlu_ctl.scala 1590:48]
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|
|
node _T_141 = and(_T_140, i0_valid_no_ebreak_ecall_r) @[dec_tlu_ctl.scala 1590:66]
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|
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|
|
node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1590:97]
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|
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|
|
node minstretl_cout_ns = and(_T_141, _T_142) @[dec_tlu_ctl.scala 1590:95]
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|
|
node _T_143 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1593:47]
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|
|
node _T_144 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1593:90]
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|
|
node minstretl_ns = mux(_T_143, io.dec_csr_wrdata_r, _T_144) @[dec_tlu_ctl.scala 1593:31]
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|
|
node _T_145 = bits(minstretl_ns, 31, 8) @[dec_tlu_ctl.scala 1595:45]
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|
|
node _T_146 = bits(minstretl_inc1, 8, 8) @[dec_tlu_ctl.scala 1595:84]
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|
|
node _T_147 = and(_T_146, minstret_enable) @[dec_tlu_ctl.scala 1595:88]
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|
|
node _T_148 = or(wr_minstretl_r, _T_147) @[dec_tlu_ctl.scala 1595:67]
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|
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node _T_149 = bits(_T_148, 0, 0) @[lib.scala 8:44]
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|
|
inst rvclkhdr_4 of rvclkhdr_58 @[lib.scala 404:23]
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|
|
rvclkhdr_4.clock <= clock
|
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|
|
rvclkhdr_4.reset <= reset
|
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|
|
rvclkhdr_4.io.clk <= clock @[lib.scala 406:18]
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|
|
rvclkhdr_4.io.en <= _T_149 @[lib.scala 407:17]
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|
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rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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|
reg _T_150 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
|
when _T_149 : @[Reg.scala 28:19]
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|
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_T_150 <= _T_145 @[Reg.scala 28:23]
|
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|
|
skip @[Reg.scala 28:19]
|
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|
|
node _T_151 = bits(minstretl_ns, 7, 0) @[dec_tlu_ctl.scala 1595:146]
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|
|
node _T_152 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1595:168]
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|
|
inst rvclkhdr_5 of rvclkhdr_59 @[lib.scala 404:23]
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|
|
rvclkhdr_5.clock <= clock
|
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|
|
rvclkhdr_5.reset <= reset
|
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|
|
|
rvclkhdr_5.io.clk <= clock @[lib.scala 406:18]
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|
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rvclkhdr_5.io.en <= _T_152 @[lib.scala 407:17]
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|
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rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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|
|
reg _T_153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
|
when _T_152 : @[Reg.scala 28:19]
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_T_153 <= _T_151 @[Reg.scala 28:23]
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|
|
skip @[Reg.scala 28:19]
|
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|
|
node _T_154 = cat(_T_150, _T_153) @[Cat.scala 29:58]
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|
|
minstretl <= _T_154 @[dec_tlu_ctl.scala 1595:19]
|
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|
|
node _T_155 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1605:71]
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|
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node _T_156 = eq(_T_155, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1605:78]
|
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|
|
node _T_157 = and(io.dec_csr_wen_r_mod, _T_156) @[dec_tlu_ctl.scala 1605:49]
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|
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node _T_158 = bits(_T_157, 0, 0) @[dec_tlu_ctl.scala 1605:94]
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|
|
wr_minstreth_r <= _T_158 @[dec_tlu_ctl.scala 1605:24]
|
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|
|
node _T_159 = cat(UInt<31>("h00"), perfmux_flop.io.minstretl_cout_f) @[Cat.scala 29:58]
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|
|
node _T_160 = add(minstreth, _T_159) @[dec_tlu_ctl.scala 1609:39]
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|
|
node minstreth_inc = tail(_T_160, 1) @[dec_tlu_ctl.scala 1609:39]
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|
|
node _T_161 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1610:48]
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|
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|
|
node minstreth_ns = mux(_T_161, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1610:32]
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|
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|
|
node _T_162 = and(perfmux_flop.io.minstret_enable_f, perfmux_flop.io.minstretl_cout_f) @[dec_tlu_ctl.scala 1612:79]
|
|
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|
|
node _T_163 = or(_T_162, wr_minstreth_r) @[dec_tlu_ctl.scala 1612:116]
|
|
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|
|
node _T_164 = bits(_T_163, 0, 0) @[lib.scala 8:44]
|
|
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|
|
inst rvclkhdr_6 of rvclkhdr_60 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_6.clock <= clock
|
|
|
|
|
rvclkhdr_6.reset <= reset
|
|
|
|
|
rvclkhdr_6.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_6.io.en <= _T_164 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
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|
|
reg _T_165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
|
|
|
when _T_164 : @[Reg.scala 28:19]
|
|
|
|
|
_T_165 <= minstreth_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
minstreth <= _T_165 @[dec_tlu_ctl.scala 1612:19]
|
|
|
|
|
node _T_166 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1620:72]
|
|
|
|
|
node _T_167 = eq(_T_166, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1620:79]
|
|
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|
|
node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_167) @[dec_tlu_ctl.scala 1620:50]
|
|
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|
|
node _T_168 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1622:62]
|
|
|
|
|
inst rvclkhdr_7 of rvclkhdr_61 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_7.clock <= clock
|
|
|
|
|
rvclkhdr_7.reset <= reset
|
|
|
|
|
rvclkhdr_7.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_7.io.en <= _T_168 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_169 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_168 : @[Reg.scala 28:19]
|
|
|
|
|
_T_169 <= io.dec_csr_wrdata_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mscratch <= _T_169 @[dec_tlu_ctl.scala 1622:18]
|
|
|
|
|
node _T_170 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1631:29]
|
|
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|
|
node _T_171 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1631:54]
|
|
|
|
|
node _T_172 = and(_T_170, _T_171) @[dec_tlu_ctl.scala 1631:52]
|
|
|
|
|
node sel_exu_npc_r = and(_T_172, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1631:79]
|
|
|
|
|
node _T_173 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1632:31]
|
|
|
|
|
node _T_174 = and(_T_173, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1632:54]
|
|
|
|
|
node _T_175 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1632:82]
|
|
|
|
|
node sel_flush_npc_r = and(_T_174, _T_175) @[dec_tlu_ctl.scala 1632:80]
|
|
|
|
|
node _T_176 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1633:30]
|
|
|
|
|
node _T_177 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1633:47]
|
|
|
|
|
node sel_hold_npc_r = and(_T_176, _T_177) @[dec_tlu_ctl.scala 1633:45]
|
|
|
|
|
node _T_178 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1636:31]
|
|
|
|
|
node _T_179 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1637:18]
|
|
|
|
|
node _T_180 = and(_T_179, io.reset_delayed) @[dec_tlu_ctl.scala 1637:40]
|
|
|
|
|
node _T_181 = bits(_T_180, 0, 0) @[dec_tlu_ctl.scala 1637:60]
|
|
|
|
|
node _T_182 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1638:33]
|
|
|
|
|
node _T_183 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1639:32]
|
|
|
|
|
node _T_184 = mux(_T_178, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_185 = mux(_T_181, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_186 = mux(_T_182, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_187 = mux(_T_183, io.npc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_188 = or(_T_184, _T_185) @[Mux.scala 27:72]
|
|
|
|
|
node _T_189 = or(_T_188, _T_186) @[Mux.scala 27:72]
|
|
|
|
|
node _T_190 = or(_T_189, _T_187) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_191 : UInt<31> @[Mux.scala 27:72]
|
|
|
|
|
_T_191 <= _T_190 @[Mux.scala 27:72]
|
|
|
|
|
io.npc_r <= _T_191 @[dec_tlu_ctl.scala 1635:18]
|
|
|
|
|
node _T_192 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1641:58]
|
|
|
|
|
node _T_193 = or(_T_192, io.reset_delayed) @[dec_tlu_ctl.scala 1641:76]
|
|
|
|
|
node _T_194 = bits(_T_193, 0, 0) @[dec_tlu_ctl.scala 1641:96]
|
|
|
|
|
wire _T_195 : UInt<31> @[lib.scala 648:38]
|
|
|
|
|
_T_195 <= UInt<1>("h00") @[lib.scala 648:38]
|
|
|
|
|
reg _T_196 : UInt, clock with : (reset => (reset, _T_195)) @[Reg.scala 27:20]
|
|
|
|
|
when _T_194 : @[Reg.scala 28:19]
|
|
|
|
|
_T_196 <= io.npc_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.npc_r_d1 <= _T_196 @[dec_tlu_ctl.scala 1641:21]
|
|
|
|
|
node _T_197 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1644:28]
|
|
|
|
|
node _T_198 = and(_T_197, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1644:51]
|
|
|
|
|
node pc0_valid_r = bits(_T_198, 0, 0) @[dec_tlu_ctl.scala 1644:76]
|
|
|
|
|
node _T_199 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1648:17]
|
|
|
|
|
node _T_200 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_201 = mux(_T_199, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_202 = or(_T_200, _T_201) @[Mux.scala 27:72]
|
|
|
|
|
wire pc_r : UInt<31> @[Mux.scala 27:72]
|
|
|
|
|
pc_r <= _T_202 @[Mux.scala 27:72]
|
|
|
|
|
wire _T_203 : UInt<31> @[lib.scala 648:38]
|
|
|
|
|
_T_203 <= UInt<1>("h00") @[lib.scala 648:38]
|
|
|
|
|
reg _T_204 : UInt, clock with : (reset => (reset, _T_203)) @[Reg.scala 27:20]
|
|
|
|
|
when pc0_valid_r : @[Reg.scala 28:19]
|
|
|
|
|
_T_204 <= pc_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
pc_r_d1 <= _T_204 @[dec_tlu_ctl.scala 1650:17]
|
|
|
|
|
node _T_205 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1652:68]
|
|
|
|
|
node _T_206 = eq(_T_205, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1652:75]
|
|
|
|
|
node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_206) @[dec_tlu_ctl.scala 1652:46]
|
|
|
|
|
node _T_207 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1655:42]
|
|
|
|
|
node _T_208 = or(_T_207, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1655:63]
|
|
|
|
|
node _T_209 = bits(_T_208, 0, 0) @[dec_tlu_ctl.scala 1655:95]
|
|
|
|
|
node _T_210 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1656:40]
|
|
|
|
|
node _T_211 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1657:30]
|
|
|
|
|
node _T_212 = and(wr_mepc_r, _T_211) @[dec_tlu_ctl.scala 1657:28]
|
|
|
|
|
node _T_213 = bits(_T_212, 0, 0) @[dec_tlu_ctl.scala 1657:54]
|
|
|
|
|
node _T_214 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1657:119]
|
|
|
|
|
node _T_215 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1658:18]
|
|
|
|
|
node _T_216 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1658:31]
|
|
|
|
|
node _T_217 = and(_T_215, _T_216) @[dec_tlu_ctl.scala 1658:29]
|
|
|
|
|
node _T_218 = bits(_T_217, 0, 0) @[dec_tlu_ctl.scala 1658:55]
|
|
|
|
|
node _T_219 = mux(_T_209, pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_220 = mux(_T_210, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_221 = mux(_T_213, _T_214, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_222 = mux(_T_218, io.mepc, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_223 = or(_T_219, _T_220) @[Mux.scala 27:72]
|
|
|
|
|
node _T_224 = or(_T_223, _T_221) @[Mux.scala 27:72]
|
|
|
|
|
node _T_225 = or(_T_224, _T_222) @[Mux.scala 27:72]
|
|
|
|
|
wire mepc_ns : UInt<31> @[Mux.scala 27:72]
|
|
|
|
|
mepc_ns <= _T_225 @[Mux.scala 27:72]
|
|
|
|
|
node _T_226 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1660:59]
|
|
|
|
|
node _T_227 = or(_T_226, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1660:80]
|
|
|
|
|
node _T_228 = or(_T_227, io.interrupt_valid_r) @[dec_tlu_ctl.scala 1660:111]
|
|
|
|
|
node _T_229 = or(_T_228, wr_mepc_r) @[dec_tlu_ctl.scala 1660:134]
|
|
|
|
|
node _T_230 = bits(_T_229, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
inst rvclkhdr_8 of rvclkhdr_62 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_8.clock <= clock
|
|
|
|
|
rvclkhdr_8.reset <= reset
|
|
|
|
|
rvclkhdr_8.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_8.io.en <= _T_230 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_231 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_230 : @[Reg.scala 28:19]
|
|
|
|
|
_T_231 <= mepc_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mepc <= _T_231 @[dec_tlu_ctl.scala 1660:17]
|
|
|
|
|
node _T_232 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1668:70]
|
|
|
|
|
node _T_233 = eq(_T_232, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1668:77]
|
|
|
|
|
node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_233) @[dec_tlu_ctl.scala 1668:48]
|
|
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node _T_234 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1669:58]
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node mcause_sel_nmi_store = and(_T_234, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1669:72]
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node _T_235 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1670:57]
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node mcause_sel_nmi_load = and(_T_235, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1670:71]
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node _T_236 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1671:55]
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node _T_237 = and(_T_236, io.take_ext_int_start_d3) @[dec_tlu_ctl.scala 1671:69]
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node _T_238 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1671:115]
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node _T_239 = and(_T_237, _T_238) @[dec_tlu_ctl.scala 1671:96]
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node _T_240 = eq(io.nmi_int_detected_f, UInt<1>("h00")) @[dec_tlu_ctl.scala 1671:121]
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node mcause_sel_nmi_ext = and(_T_239, _T_240) @[dec_tlu_ctl.scala 1671:119]
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node _T_241 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1678:58]
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node _T_242 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1678:81]
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node _T_243 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1678:104]
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node _T_244 = not(_T_243) @[dec_tlu_ctl.scala 1678:87]
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node _T_245 = and(_T_242, _T_244) @[dec_tlu_ctl.scala 1678:85]
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node mcause_fir_error_type = cat(_T_241, _T_245) @[Cat.scala 29:58]
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node _T_246 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1681:38]
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node _T_247 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1682:37]
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node _T_248 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1683:36]
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node _T_249 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58]
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node _T_250 = cat(_T_249, mcause_fir_error_type) @[Cat.scala 29:58]
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node _T_251 = eq(io.take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 1684:42]
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node _T_252 = and(io.exc_or_int_valid_r, _T_251) @[dec_tlu_ctl.scala 1684:40]
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node _T_253 = bits(_T_252, 0, 0) @[dec_tlu_ctl.scala 1684:56]
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node _T_254 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58]
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node _T_255 = cat(_T_254, io.exc_cause_r) @[Cat.scala 29:58]
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node _T_256 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1685:32]
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node _T_257 = and(wr_mcause_r, _T_256) @[dec_tlu_ctl.scala 1685:30]
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node _T_258 = bits(_T_257, 0, 0) @[dec_tlu_ctl.scala 1685:56]
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node _T_259 = eq(wr_mcause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1686:18]
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node _T_260 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1686:33]
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node _T_261 = and(_T_259, _T_260) @[dec_tlu_ctl.scala 1686:31]
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node _T_262 = bits(_T_261, 0, 0) @[dec_tlu_ctl.scala 1686:57]
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node _T_263 = mux(_T_246, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_264 = mux(_T_247, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_265 = mux(_T_248, _T_250, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_266 = mux(_T_253, _T_255, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_267 = mux(_T_258, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_268 = mux(_T_262, mcause, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_269 = or(_T_263, _T_264) @[Mux.scala 27:72]
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node _T_270 = or(_T_269, _T_265) @[Mux.scala 27:72]
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node _T_271 = or(_T_270, _T_266) @[Mux.scala 27:72]
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node _T_272 = or(_T_271, _T_267) @[Mux.scala 27:72]
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node _T_273 = or(_T_272, _T_268) @[Mux.scala 27:72]
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wire mcause_ns : UInt<32> @[Mux.scala 27:72]
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mcause_ns <= _T_273 @[Mux.scala 27:72]
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node _T_274 = or(io.exc_or_int_valid_r, wr_mcause_r) @[dec_tlu_ctl.scala 1688:58]
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node _T_275 = bits(_T_274, 0, 0) @[lib.scala 8:44]
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inst rvclkhdr_9 of rvclkhdr_63 @[lib.scala 404:23]
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rvclkhdr_9.clock <= clock
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rvclkhdr_9.reset <= reset
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rvclkhdr_9.io.clk <= clock @[lib.scala 406:18]
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rvclkhdr_9.io.en <= _T_275 @[lib.scala 407:17]
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rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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reg _T_276 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_275 : @[Reg.scala 28:19]
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_T_276 <= mcause_ns @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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mcause <= _T_276 @[dec_tlu_ctl.scala 1688:16]
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node _T_277 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1695:71]
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node _T_278 = eq(_T_277, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1695:78]
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node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_278) @[dec_tlu_ctl.scala 1695:49]
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node _T_279 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1697:63]
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node _T_280 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58]
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|
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node ifu_mscause = mux(_T_279, UInt<4>("h09"), _T_280) @[dec_tlu_ctl.scala 1697:31]
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node _T_281 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1700:33]
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node _T_282 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1701:37]
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node _T_283 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1702:29]
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node _T_284 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1703:31]
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node _T_285 = mux(_T_281, io.lsu_error_pkt_r.bits.mscause, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_286 = mux(_T_282, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_287 = mux(_T_283, UInt<4>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_288 = mux(_T_284, ifu_mscause, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_289 = or(_T_285, _T_286) @[Mux.scala 27:72]
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node _T_290 = or(_T_289, _T_287) @[Mux.scala 27:72]
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node _T_291 = or(_T_290, _T_288) @[Mux.scala 27:72]
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|
wire mscause_type : UInt<4> @[Mux.scala 27:72]
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|
|
mscause_type <= _T_291 @[Mux.scala 27:72]
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node _T_292 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1707:41]
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node _T_293 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1708:33]
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node _T_294 = and(wr_mscause_r, _T_293) @[dec_tlu_ctl.scala 1708:31]
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node _T_295 = bits(_T_294, 0, 0) @[dec_tlu_ctl.scala 1708:57]
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node _T_296 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1708:96]
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node _T_297 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1709:18]
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node _T_298 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1709:34]
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node _T_299 = and(_T_297, _T_298) @[dec_tlu_ctl.scala 1709:32]
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node _T_300 = bits(_T_299, 0, 0) @[dec_tlu_ctl.scala 1709:58]
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node _T_301 = mux(_T_292, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_302 = mux(_T_295, _T_296, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_303 = mux(_T_300, mscause, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_304 = or(_T_301, _T_302) @[Mux.scala 27:72]
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node _T_305 = or(_T_304, _T_303) @[Mux.scala 27:72]
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wire mscause_ns : UInt<4> @[Mux.scala 27:72]
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|
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mscause_ns <= _T_305 @[Mux.scala 27:72]
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reg _T_306 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1711:54]
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|
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_T_306 <= mscause_ns @[dec_tlu_ctl.scala 1711:54]
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mscause <= _T_306 @[dec_tlu_ctl.scala 1711:17]
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node _T_307 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1718:69]
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node _T_308 = eq(_T_307, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1718:76]
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node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_308) @[dec_tlu_ctl.scala 1718:47]
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node _T_309 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1719:90]
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node _T_310 = and(io.inst_acc_r, _T_309) @[dec_tlu_ctl.scala 1719:88]
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node _T_311 = or(io.ebreak_r, _T_310) @[dec_tlu_ctl.scala 1719:71]
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node _T_312 = or(_T_311, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1719:113]
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node _T_313 = and(io.exc_or_int_valid_r, _T_312) @[dec_tlu_ctl.scala 1719:56]
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node _T_314 = not(io.take_nmi) @[dec_tlu_ctl.scala 1719:147]
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node mtval_capture_pc_r = and(_T_313, _T_314) @[dec_tlu_ctl.scala 1719:145]
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node _T_315 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1720:79]
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node _T_316 = and(io.exc_or_int_valid_r, _T_315) @[dec_tlu_ctl.scala 1720:62]
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node _T_317 = not(io.take_nmi) @[dec_tlu_ctl.scala 1720:105]
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|
node mtval_capture_pc_plus2_r = and(_T_316, _T_317) @[dec_tlu_ctl.scala 1720:103]
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node _T_318 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1721:58]
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node _T_319 = not(io.take_nmi) @[dec_tlu_ctl.scala 1721:75]
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|
node mtval_capture_inst_r = and(_T_318, _T_319) @[dec_tlu_ctl.scala 1721:73]
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node _T_320 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1722:57]
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|
node _T_321 = not(io.take_nmi) @[dec_tlu_ctl.scala 1722:80]
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|
node mtval_capture_lsu_r = and(_T_320, _T_321) @[dec_tlu_ctl.scala 1722:78]
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node _T_322 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1723:53]
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node _T_323 = and(io.exc_or_int_valid_r, _T_322) @[dec_tlu_ctl.scala 1723:51]
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node _T_324 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1723:75]
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node _T_325 = and(_T_323, _T_324) @[dec_tlu_ctl.scala 1723:73]
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node _T_326 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1723:99]
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node _T_327 = and(_T_325, _T_326) @[dec_tlu_ctl.scala 1723:97]
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node _T_328 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1723:122]
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|
node mtval_clear_r = and(_T_327, _T_328) @[dec_tlu_ctl.scala 1723:120]
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|
node _T_329 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1727:38]
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node _T_330 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58]
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|
node _T_331 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1728:44]
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|
node _T_332 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1728:96]
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node _T_333 = tail(_T_332, 1) @[dec_tlu_ctl.scala 1728:96]
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node _T_334 = cat(_T_333, UInt<1>("h00")) @[Cat.scala 29:58]
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|
node _T_335 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1729:40]
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|
node _T_336 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1730:39]
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|
node _T_337 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1731:31]
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|
node _T_338 = and(wr_mtval_r, _T_337) @[dec_tlu_ctl.scala 1731:29]
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|
node _T_339 = bits(_T_338, 0, 0) @[dec_tlu_ctl.scala 1731:61]
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|
node _T_340 = not(io.take_nmi) @[dec_tlu_ctl.scala 1732:18]
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|
node _T_341 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1732:33]
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|
|
node _T_342 = and(_T_340, _T_341) @[dec_tlu_ctl.scala 1732:31]
|
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|
|
node _T_343 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1732:47]
|
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|
|
|
node _T_344 = and(_T_342, _T_343) @[dec_tlu_ctl.scala 1732:45]
|
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|
|
node _T_345 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1732:69]
|
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|
|
node _T_346 = and(_T_344, _T_345) @[dec_tlu_ctl.scala 1732:67]
|
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|
|
node _T_347 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1732:93]
|
|
|
|
|
node _T_348 = and(_T_346, _T_347) @[dec_tlu_ctl.scala 1732:91]
|
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|
|
|
node _T_349 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1732:110]
|
|
|
|
|
node _T_350 = and(_T_348, _T_349) @[dec_tlu_ctl.scala 1732:108]
|
|
|
|
|
node _T_351 = bits(_T_350, 0, 0) @[dec_tlu_ctl.scala 1732:132]
|
|
|
|
|
node _T_352 = mux(_T_329, _T_330, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_353 = mux(_T_331, _T_334, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_354 = mux(_T_335, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_355 = mux(_T_336, io.lsu_error_pkt_addr_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_356 = mux(_T_339, io.dec_csr_wrdata_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_357 = mux(_T_351, mtval, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_358 = or(_T_352, _T_353) @[Mux.scala 27:72]
|
|
|
|
|
node _T_359 = or(_T_358, _T_354) @[Mux.scala 27:72]
|
|
|
|
|
node _T_360 = or(_T_359, _T_355) @[Mux.scala 27:72]
|
|
|
|
|
node _T_361 = or(_T_360, _T_356) @[Mux.scala 27:72]
|
|
|
|
|
node _T_362 = or(_T_361, _T_357) @[Mux.scala 27:72]
|
|
|
|
|
wire mtval_ns : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
mtval_ns <= _T_362 @[Mux.scala 27:72]
|
|
|
|
|
node _T_363 = or(io.tlu_flush_lower_r, wr_mtval_r) @[dec_tlu_ctl.scala 1734:55]
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node _T_364 = bits(_T_363, 0, 0) @[lib.scala 8:44]
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inst rvclkhdr_10 of rvclkhdr_64 @[lib.scala 404:23]
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rvclkhdr_10.clock <= clock
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rvclkhdr_10.reset <= reset
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|
rvclkhdr_10.io.clk <= clock @[lib.scala 406:18]
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rvclkhdr_10.io.en <= _T_364 @[lib.scala 407:17]
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rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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reg _T_365 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_364 : @[Reg.scala 28:19]
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_T_365 <= mtval_ns @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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mtval <= _T_365 @[dec_tlu_ctl.scala 1734:15]
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wire mcgc_int : UInt<10>
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mcgc_int <= UInt<1>("h00")
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node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1752:68]
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node _T_367 = eq(_T_366, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1752:75]
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node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1752:46]
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node _T_368 = bits(wr_mcgc_r, 0, 0) @[lib.scala 8:44]
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node _T_369 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1753:62]
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node _T_370 = not(_T_369) @[dec_tlu_ctl.scala 1753:42]
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node _T_371 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1753:86]
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node _T_372 = cat(_T_370, _T_371) @[Cat.scala 29:58]
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node mcgc_ns = mux(_T_368, _T_372, mcgc_int) @[dec_tlu_ctl.scala 1753:26]
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node _T_373 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1754:46]
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inst rvclkhdr_11 of rvclkhdr_65 @[lib.scala 404:23]
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rvclkhdr_11.clock <= clock
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rvclkhdr_11.reset <= reset
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|
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rvclkhdr_11.io.clk <= clock @[lib.scala 406:18]
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rvclkhdr_11.io.en <= _T_373 @[lib.scala 407:17]
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rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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reg _T_374 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
when _T_373 : @[Reg.scala 28:19]
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_T_374 <= mcgc_ns @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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|
|
mcgc_int <= _T_374 @[dec_tlu_ctl.scala 1754:18]
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node _T_375 = bits(mcgc_int, 9, 9) @[dec_tlu_ctl.scala 1755:33]
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node _T_376 = not(_T_375) @[dec_tlu_ctl.scala 1755:24]
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node _T_377 = bits(mcgc_int, 8, 0) @[dec_tlu_ctl.scala 1755:46]
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node mcgc = cat(_T_376, _T_377) @[Cat.scala 29:58]
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node _T_378 = bits(mcgc, 9, 9) @[dec_tlu_ctl.scala 1756:46]
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|
io.dec_tlu_picio_clk_override <= _T_378 @[dec_tlu_ctl.scala 1756:39]
|
2021-01-28 15:16:34 +08:00
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|
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node _T_379 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1757:46]
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|
|
io.dec_tlu_misc_clk_override <= _T_379 @[dec_tlu_ctl.scala 1757:39]
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|
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node _T_380 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1758:46]
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|
|
io.dec_tlu_dec_clk_override <= _T_380 @[dec_tlu_ctl.scala 1758:39]
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|
|
node _T_381 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1759:46]
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|
|
io.dec_tlu_ifu_clk_override <= _T_381 @[dec_tlu_ctl.scala 1759:39]
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|
|
node _T_382 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1760:46]
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|
|
io.dec_tlu_lsu_clk_override <= _T_382 @[dec_tlu_ctl.scala 1760:39]
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|
|
node _T_383 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1761:46]
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|
|
io.dec_tlu_bus_clk_override <= _T_383 @[dec_tlu_ctl.scala 1761:39]
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|
|
node _T_384 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1762:46]
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|
|
io.dec_tlu_pic_clk_override <= _T_384 @[dec_tlu_ctl.scala 1762:39]
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|
|
node _T_385 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1763:46]
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|
|
io.dec_tlu_dccm_clk_override <= _T_385 @[dec_tlu_ctl.scala 1763:39]
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|
|
node _T_386 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1764:46]
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|
|
io.dec_tlu_icm_clk_override <= _T_386 @[dec_tlu_ctl.scala 1764:39]
|
2021-01-27 14:46:11 +08:00
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|
node _T_387 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1785:68]
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|
node _T_388 = eq(_T_387, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1785:75]
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|
|
node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_388) @[dec_tlu_ctl.scala 1785:46]
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|
|
node _T_389 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1789:46]
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|
|
inst rvclkhdr_12 of rvclkhdr_66 @[lib.scala 404:23]
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|
|
|
rvclkhdr_12.clock <= clock
|
|
|
|
|
rvclkhdr_12.reset <= reset
|
|
|
|
|
rvclkhdr_12.io.clk <= clock @[lib.scala 406:18]
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|
|
|
|
rvclkhdr_12.io.en <= _T_389 @[lib.scala 407:17]
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|
|
|
|
rvclkhdr_12.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
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|
|
reg _T_390 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
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|
|
when _T_389 : @[Reg.scala 28:19]
|
|
|
|
|
_T_390 <= mfdc_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mfdc_int <= _T_390 @[dec_tlu_ctl.scala 1789:18]
|
|
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|
|
node _T_391 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1795:52]
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|
|
node _T_392 = not(_T_391) @[dec_tlu_ctl.scala 1795:32]
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|
|
node _T_393 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1795:79]
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|
|
node _T_394 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1795:103]
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|
|
node _T_395 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1795:131]
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|
|
node _T_396 = not(_T_395) @[dec_tlu_ctl.scala 1795:111]
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|
|
node _T_397 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1795:155]
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|
|
|
node _T_398 = cat(_T_396, _T_397) @[Cat.scala 29:58]
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|
|
node _T_399 = cat(_T_392, _T_393) @[Cat.scala 29:58]
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|
|
node _T_400 = cat(_T_399, _T_394) @[Cat.scala 29:58]
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|
|
node _T_401 = cat(_T_400, _T_398) @[Cat.scala 29:58]
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|
|
|
mfdc_ns <= _T_401 @[dec_tlu_ctl.scala 1795:25]
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|
|
node _T_402 = bits(mfdc_int, 15, 13) @[dec_tlu_ctl.scala 1796:41]
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|
|
node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1796:32]
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|
|
node _T_404 = bits(mfdc_int, 12, 12) @[dec_tlu_ctl.scala 1796:66]
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|
|
node _T_405 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1796:80]
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|
|
node _T_406 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1796:97]
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|
|
node _T_407 = not(_T_406) @[dec_tlu_ctl.scala 1796:88]
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|
|
node _T_408 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1796:110]
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|
|
node _T_409 = cat(_T_405, _T_407) @[Cat.scala 29:58]
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|
|
|
|
node _T_410 = cat(_T_409, _T_408) @[Cat.scala 29:58]
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|
|
|
|
node _T_411 = cat(_T_403, UInt<3>("h00")) @[Cat.scala 29:58]
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|
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|
|
node _T_412 = cat(_T_411, _T_404) @[Cat.scala 29:58]
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|
|
node _T_413 = cat(_T_412, _T_410) @[Cat.scala 29:58]
|
|
|
|
|
mfdc <= _T_413 @[dec_tlu_ctl.scala 1796:25]
|
|
|
|
|
node _T_414 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1806:53]
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|
|
|
|
io.dec_tlu_dma_qos_prty <= _T_414 @[dec_tlu_ctl.scala 1806:46]
|
|
|
|
|
node _T_415 = bits(mfdc, 12, 12) @[dec_tlu_ctl.scala 1807:53]
|
|
|
|
|
io.dec_tlu_trace_disable <= _T_415 @[dec_tlu_ctl.scala 1807:46]
|
|
|
|
|
node _T_416 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1808:53]
|
|
|
|
|
io.dec_tlu_external_ldfwd_disable <= _T_416 @[dec_tlu_ctl.scala 1808:46]
|
|
|
|
|
node _T_417 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1809:53]
|
|
|
|
|
io.dec_tlu_core_ecc_disable <= _T_417 @[dec_tlu_ctl.scala 1809:46]
|
|
|
|
|
node _T_418 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1810:53]
|
|
|
|
|
io.dec_tlu_sideeffect_posted_disable <= _T_418 @[dec_tlu_ctl.scala 1810:46]
|
|
|
|
|
node _T_419 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1811:53]
|
|
|
|
|
io.dec_tlu_bpred_disable <= _T_419 @[dec_tlu_ctl.scala 1811:46]
|
|
|
|
|
node _T_420 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1812:53]
|
|
|
|
|
io.dec_tlu_wb_coalescing_disable <= _T_420 @[dec_tlu_ctl.scala 1812:46]
|
|
|
|
|
node _T_421 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1813:53]
|
|
|
|
|
io.dec_tlu_pipelining_disable <= _T_421 @[dec_tlu_ctl.scala 1813:46]
|
|
|
|
|
node _T_422 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1822:77]
|
|
|
|
|
node _T_423 = eq(_T_422, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1822:84]
|
|
|
|
|
node _T_424 = and(io.dec_csr_wen_r_mod, _T_423) @[dec_tlu_ctl.scala 1822:55]
|
|
|
|
|
node _T_425 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1822:96]
|
|
|
|
|
node _T_426 = and(_T_424, _T_425) @[dec_tlu_ctl.scala 1822:94]
|
|
|
|
|
node _T_427 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1822:120]
|
|
|
|
|
node _T_428 = and(_T_426, _T_427) @[dec_tlu_ctl.scala 1822:118]
|
|
|
|
|
io.dec_tlu_wr_pause_r <= _T_428 @[dec_tlu_ctl.scala 1822:31]
|
|
|
|
|
node _T_429 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1829:68]
|
|
|
|
|
node _T_430 = eq(_T_429, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1829:75]
|
|
|
|
|
node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_430) @[dec_tlu_ctl.scala 1829:46]
|
|
|
|
|
node _T_431 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1832:46]
|
|
|
|
|
node _T_432 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1832:71]
|
|
|
|
|
node _T_433 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1832:98]
|
|
|
|
|
node _T_434 = not(_T_433) @[dec_tlu_ctl.scala 1832:78]
|
|
|
|
|
node _T_435 = and(_T_432, _T_434) @[dec_tlu_ctl.scala 1832:76]
|
|
|
|
|
node _T_436 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1833:36]
|
|
|
|
|
node _T_437 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1833:61]
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|
|
|
|
node _T_438 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1833:88]
|
|
|
|
|
node _T_439 = not(_T_438) @[dec_tlu_ctl.scala 1833:68]
|
|
|
|
|
node _T_440 = and(_T_437, _T_439) @[dec_tlu_ctl.scala 1833:66]
|
|
|
|
|
node _T_441 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1834:36]
|
|
|
|
|
node _T_442 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1834:61]
|
|
|
|
|
node _T_443 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1834:88]
|
|
|
|
|
node _T_444 = not(_T_443) @[dec_tlu_ctl.scala 1834:68]
|
|
|
|
|
node _T_445 = and(_T_442, _T_444) @[dec_tlu_ctl.scala 1834:66]
|
|
|
|
|
node _T_446 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1835:36]
|
|
|
|
|
node _T_447 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1835:61]
|
|
|
|
|
node _T_448 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1835:88]
|
|
|
|
|
node _T_449 = not(_T_448) @[dec_tlu_ctl.scala 1835:68]
|
|
|
|
|
node _T_450 = and(_T_447, _T_449) @[dec_tlu_ctl.scala 1835:66]
|
|
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|
|
node _T_451 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1836:36]
|
|
|
|
|
node _T_452 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1836:61]
|
|
|
|
|
node _T_453 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1836:88]
|
|
|
|
|
node _T_454 = not(_T_453) @[dec_tlu_ctl.scala 1836:68]
|
|
|
|
|
node _T_455 = and(_T_452, _T_454) @[dec_tlu_ctl.scala 1836:66]
|
|
|
|
|
node _T_456 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1837:36]
|
|
|
|
|
node _T_457 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1837:61]
|
|
|
|
|
node _T_458 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1837:88]
|
|
|
|
|
node _T_459 = not(_T_458) @[dec_tlu_ctl.scala 1837:68]
|
|
|
|
|
node _T_460 = and(_T_457, _T_459) @[dec_tlu_ctl.scala 1837:66]
|
|
|
|
|
node _T_461 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1838:36]
|
|
|
|
|
node _T_462 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1838:61]
|
|
|
|
|
node _T_463 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1838:88]
|
|
|
|
|
node _T_464 = not(_T_463) @[dec_tlu_ctl.scala 1838:68]
|
|
|
|
|
node _T_465 = and(_T_462, _T_464) @[dec_tlu_ctl.scala 1838:66]
|
|
|
|
|
node _T_466 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1839:36]
|
|
|
|
|
node _T_467 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1839:61]
|
|
|
|
|
node _T_468 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1839:88]
|
|
|
|
|
node _T_469 = not(_T_468) @[dec_tlu_ctl.scala 1839:68]
|
|
|
|
|
node _T_470 = and(_T_467, _T_469) @[dec_tlu_ctl.scala 1839:66]
|
|
|
|
|
node _T_471 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1840:36]
|
|
|
|
|
node _T_472 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1840:61]
|
|
|
|
|
node _T_473 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1840:88]
|
|
|
|
|
node _T_474 = not(_T_473) @[dec_tlu_ctl.scala 1840:68]
|
|
|
|
|
node _T_475 = and(_T_472, _T_474) @[dec_tlu_ctl.scala 1840:66]
|
|
|
|
|
node _T_476 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1841:36]
|
|
|
|
|
node _T_477 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1841:61]
|
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|
|
node _T_478 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1841:88]
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|
node _T_479 = not(_T_478) @[dec_tlu_ctl.scala 1841:68]
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|
node _T_480 = and(_T_477, _T_479) @[dec_tlu_ctl.scala 1841:66]
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|
node _T_481 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1842:36]
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|
|
node _T_482 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1842:61]
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|
|
node _T_483 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1842:88]
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|
node _T_484 = not(_T_483) @[dec_tlu_ctl.scala 1842:68]
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|
|
node _T_485 = and(_T_482, _T_484) @[dec_tlu_ctl.scala 1842:66]
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|
|
node _T_486 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1843:36]
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|
node _T_487 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1843:61]
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|
node _T_488 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1843:88]
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node _T_489 = not(_T_488) @[dec_tlu_ctl.scala 1843:68]
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|
node _T_490 = and(_T_487, _T_489) @[dec_tlu_ctl.scala 1843:65]
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node _T_491 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1844:36]
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node _T_492 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1844:61]
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node _T_493 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1844:88]
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node _T_494 = not(_T_493) @[dec_tlu_ctl.scala 1844:68]
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node _T_495 = and(_T_492, _T_494) @[dec_tlu_ctl.scala 1844:65]
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node _T_496 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1845:36]
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node _T_497 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1845:61]
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node _T_498 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1845:88]
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node _T_499 = not(_T_498) @[dec_tlu_ctl.scala 1845:68]
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node _T_500 = and(_T_497, _T_499) @[dec_tlu_ctl.scala 1845:65]
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node _T_501 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1846:36]
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node _T_502 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1846:61]
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node _T_503 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1846:88]
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node _T_504 = not(_T_503) @[dec_tlu_ctl.scala 1846:68]
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node _T_505 = and(_T_502, _T_504) @[dec_tlu_ctl.scala 1846:65]
|
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|
node _T_506 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1847:36]
|
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|
|
node _T_507 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1847:61]
|
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|
|
node _T_508 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1847:88]
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node _T_509 = not(_T_508) @[dec_tlu_ctl.scala 1847:68]
|
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|
|
node _T_510 = and(_T_507, _T_509) @[dec_tlu_ctl.scala 1847:65]
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|
|
node _T_511 = cat(_T_506, _T_510) @[Cat.scala 29:58]
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|
node _T_512 = cat(_T_501, _T_505) @[Cat.scala 29:58]
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|
node _T_513 = cat(_T_512, _T_511) @[Cat.scala 29:58]
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|
node _T_514 = cat(_T_496, _T_500) @[Cat.scala 29:58]
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|
|
node _T_515 = cat(_T_491, _T_495) @[Cat.scala 29:58]
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|
node _T_516 = cat(_T_515, _T_514) @[Cat.scala 29:58]
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node _T_517 = cat(_T_516, _T_513) @[Cat.scala 29:58]
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|
node _T_518 = cat(_T_486, _T_490) @[Cat.scala 29:58]
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|
|
node _T_519 = cat(_T_481, _T_485) @[Cat.scala 29:58]
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|
node _T_520 = cat(_T_519, _T_518) @[Cat.scala 29:58]
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|
|
node _T_521 = cat(_T_476, _T_480) @[Cat.scala 29:58]
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|
|
node _T_522 = cat(_T_471, _T_475) @[Cat.scala 29:58]
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|
node _T_523 = cat(_T_522, _T_521) @[Cat.scala 29:58]
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|
node _T_524 = cat(_T_523, _T_520) @[Cat.scala 29:58]
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|
node _T_525 = cat(_T_524, _T_517) @[Cat.scala 29:58]
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|
node _T_526 = cat(_T_466, _T_470) @[Cat.scala 29:58]
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|
node _T_527 = cat(_T_461, _T_465) @[Cat.scala 29:58]
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|
node _T_528 = cat(_T_527, _T_526) @[Cat.scala 29:58]
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|
node _T_529 = cat(_T_456, _T_460) @[Cat.scala 29:58]
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|
node _T_530 = cat(_T_451, _T_455) @[Cat.scala 29:58]
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|
node _T_531 = cat(_T_530, _T_529) @[Cat.scala 29:58]
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|
node _T_532 = cat(_T_531, _T_528) @[Cat.scala 29:58]
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|
node _T_533 = cat(_T_446, _T_450) @[Cat.scala 29:58]
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|
node _T_534 = cat(_T_441, _T_445) @[Cat.scala 29:58]
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|
|
node _T_535 = cat(_T_534, _T_533) @[Cat.scala 29:58]
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|
|
node _T_536 = cat(_T_436, _T_440) @[Cat.scala 29:58]
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|
|
node _T_537 = cat(_T_431, _T_435) @[Cat.scala 29:58]
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|
|
node _T_538 = cat(_T_537, _T_536) @[Cat.scala 29:58]
|
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|
|
node _T_539 = cat(_T_538, _T_535) @[Cat.scala 29:58]
|
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|
|
node _T_540 = cat(_T_539, _T_532) @[Cat.scala 29:58]
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|
|
node mrac_in = cat(_T_540, _T_525) @[Cat.scala 29:58]
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|
|
node _T_541 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1850:45]
|
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|
|
inst rvclkhdr_13 of rvclkhdr_67 @[lib.scala 404:23]
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|
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|
|
rvclkhdr_13.clock <= clock
|
|
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|
|
rvclkhdr_13.reset <= reset
|
|
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|
|
rvclkhdr_13.io.clk <= clock @[lib.scala 406:18]
|
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|
|
rvclkhdr_13.io.en <= _T_541 @[lib.scala 407:17]
|
|
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|
|
rvclkhdr_13.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
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|
|
reg mrac : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
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|
|
when _T_541 : @[Reg.scala 28:19]
|
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|
|
mrac <= mrac_in @[Reg.scala 28:23]
|
|
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|
|
skip @[Reg.scala 28:19]
|
|
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|
|
io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1852:28]
|
|
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|
|
node _T_542 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1860:69]
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|
|
node _T_543 = eq(_T_542, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1860:76]
|
|
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|
|
node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_543) @[dec_tlu_ctl.scala 1860:47]
|
|
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|
|
node _T_544 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1870:66]
|
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|
|
node _T_545 = and(io.mdseac_locked_f, _T_544) @[dec_tlu_ctl.scala 1870:64]
|
|
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|
|
node _T_546 = or(mdseac_en, _T_545) @[dec_tlu_ctl.scala 1870:42]
|
|
|
|
|
io.mdseac_locked_ns <= _T_546 @[dec_tlu_ctl.scala 1870:29]
|
|
|
|
|
node _T_547 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1872:56]
|
|
|
|
|
node _T_548 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1872:93]
|
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|
|
node _T_549 = and(_T_547, _T_548) @[dec_tlu_ctl.scala 1872:91]
|
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|
|
node _T_550 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1872:118]
|
|
|
|
|
node _T_551 = and(_T_549, _T_550) @[dec_tlu_ctl.scala 1872:116]
|
|
|
|
|
mdseac_en <= _T_551 @[dec_tlu_ctl.scala 1872:19]
|
|
|
|
|
node _T_552 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1874:71]
|
|
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|
|
inst rvclkhdr_14 of rvclkhdr_68 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_14.clock <= clock
|
|
|
|
|
rvclkhdr_14.reset <= reset
|
|
|
|
|
rvclkhdr_14.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_14.io.en <= _T_552 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_14.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg mdseac : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_552 : @[Reg.scala 28:19]
|
|
|
|
|
mdseac <= io.lsu_imprecise_error_addr_any @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_553 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1883:69]
|
|
|
|
|
node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_553) @[dec_tlu_ctl.scala 1883:46]
|
|
|
|
|
node _T_554 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1887:58]
|
|
|
|
|
node _T_555 = and(wr_mpmc_r, _T_554) @[dec_tlu_ctl.scala 1887:37]
|
|
|
|
|
node _T_556 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1887:64]
|
|
|
|
|
node _T_557 = and(_T_555, _T_556) @[dec_tlu_ctl.scala 1887:62]
|
|
|
|
|
node _T_558 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1887:96]
|
|
|
|
|
node _T_559 = and(_T_557, _T_558) @[dec_tlu_ctl.scala 1887:94]
|
|
|
|
|
io.fw_halt_req <= _T_559 @[dec_tlu_ctl.scala 1887:24]
|
|
|
|
|
wire fw_halted_ns : UInt<1>
|
|
|
|
|
fw_halted_ns <= UInt<1>("h00")
|
|
|
|
|
node _T_560 = or(io.fw_halt_req, perfmux_flop.io.fw_halted) @[dec_tlu_ctl.scala 1890:41]
|
|
|
|
|
node _T_561 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1890:72]
|
|
|
|
|
node _T_562 = and(_T_560, _T_561) @[dec_tlu_ctl.scala 1890:70]
|
|
|
|
|
fw_halted_ns <= _T_562 @[dec_tlu_ctl.scala 1890:22]
|
|
|
|
|
node _T_563 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1891:36]
|
|
|
|
|
node _T_564 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1891:64]
|
|
|
|
|
node _T_565 = not(_T_564) @[dec_tlu_ctl.scala 1891:44]
|
|
|
|
|
node _T_566 = not(mpmc) @[dec_tlu_ctl.scala 1891:69]
|
|
|
|
|
node _T_567 = mux(_T_563, _T_565, _T_566) @[dec_tlu_ctl.scala 1891:25]
|
|
|
|
|
mpmc_b_ns <= _T_567 @[dec_tlu_ctl.scala 1891:19]
|
|
|
|
|
reg _T_568 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1893:51]
|
|
|
|
|
_T_568 <= mpmc_b_ns @[dec_tlu_ctl.scala 1893:51]
|
|
|
|
|
mpmc_b <= _T_568 @[dec_tlu_ctl.scala 1893:16]
|
|
|
|
|
node _T_569 = not(mpmc_b) @[dec_tlu_ctl.scala 1896:17]
|
|
|
|
|
mpmc <= _T_569 @[dec_tlu_ctl.scala 1896:14]
|
|
|
|
|
node _T_570 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1905:47]
|
|
|
|
|
node _T_571 = gt(_T_570, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1905:55]
|
|
|
|
|
node _T_572 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1905:99]
|
|
|
|
|
node csr_sat = mux(_T_571, UInt<5>("h01a"), _T_572) @[dec_tlu_ctl.scala 1905:26]
|
|
|
|
|
node _T_573 = eq(io.dec_csr_wraddr_r, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1907:71]
|
|
|
|
|
node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_573) @[dec_tlu_ctl.scala 1907:48]
|
|
|
|
|
node _T_574 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1908:29]
|
|
|
|
|
node _T_575 = cat(UInt<26>("h00"), io.ic_perr_r) @[Cat.scala 29:58]
|
|
|
|
|
node _T_576 = add(_T_574, _T_575) @[dec_tlu_ctl.scala 1908:36]
|
|
|
|
|
node _T_577 = tail(_T_576, 1) @[dec_tlu_ctl.scala 1908:36]
|
|
|
|
|
micect_inc <= _T_577 @[dec_tlu_ctl.scala 1908:20]
|
|
|
|
|
node _T_578 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1909:42]
|
|
|
|
|
node _T_579 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1909:82]
|
|
|
|
|
node _T_580 = cat(csr_sat, _T_579) @[Cat.scala 29:58]
|
|
|
|
|
node _T_581 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1909:102]
|
|
|
|
|
node _T_582 = cat(_T_581, micect_inc) @[Cat.scala 29:58]
|
|
|
|
|
node micect_ns = mux(_T_578, _T_580, _T_582) @[dec_tlu_ctl.scala 1909:29]
|
|
|
|
|
node _T_583 = or(wr_micect_r, io.ic_perr_r) @[dec_tlu_ctl.scala 1911:49]
|
|
|
|
|
node _T_584 = bits(_T_583, 0, 0) @[dec_tlu_ctl.scala 1911:65]
|
|
|
|
|
inst rvclkhdr_15 of rvclkhdr_69 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_15.clock <= clock
|
|
|
|
|
rvclkhdr_15.reset <= reset
|
|
|
|
|
rvclkhdr_15.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_15.io.en <= _T_584 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_15.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_585 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_584 : @[Reg.scala 28:19]
|
|
|
|
|
_T_585 <= micect_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
micect <= _T_585 @[dec_tlu_ctl.scala 1911:16]
|
|
|
|
|
node _T_586 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1913:55]
|
|
|
|
|
node _T_587 = dshl(UInt<32>("h0ffffffff"), _T_586) @[dec_tlu_ctl.scala 1913:46]
|
|
|
|
|
node _T_588 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1913:86]
|
|
|
|
|
node _T_589 = cat(UInt<5>("h00"), _T_588) @[Cat.scala 29:58]
|
|
|
|
|
node _T_590 = and(_T_587, _T_589) @[dec_tlu_ctl.scala 1913:64]
|
|
|
|
|
node _T_591 = orr(_T_590) @[dec_tlu_ctl.scala 1913:95]
|
|
|
|
|
mice_ce_req <= _T_591 @[dec_tlu_ctl.scala 1913:21]
|
|
|
|
|
node _T_592 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1922:76]
|
|
|
|
|
node _T_593 = eq(_T_592, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1922:83]
|
|
|
|
|
node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_593) @[dec_tlu_ctl.scala 1922:54]
|
|
|
|
|
node _T_594 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1923:33]
|
|
|
|
|
node _T_595 = or(io.iccm_sbecc_r, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1923:74]
|
|
|
|
|
node _T_596 = cat(UInt<26>("h00"), _T_595) @[Cat.scala 29:58]
|
|
|
|
|
node _T_597 = add(_T_594, _T_596) @[dec_tlu_ctl.scala 1923:40]
|
|
|
|
|
node _T_598 = tail(_T_597, 1) @[dec_tlu_ctl.scala 1923:40]
|
|
|
|
|
miccmect_inc <= _T_598 @[dec_tlu_ctl.scala 1923:22]
|
|
|
|
|
node _T_599 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1924:52]
|
|
|
|
|
node _T_600 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1924:92]
|
|
|
|
|
node _T_601 = cat(csr_sat, _T_600) @[Cat.scala 29:58]
|
|
|
|
|
node _T_602 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1924:114]
|
|
|
|
|
node _T_603 = cat(_T_602, miccmect_inc) @[Cat.scala 29:58]
|
|
|
|
|
node miccmect_ns = mux(_T_599, _T_601, _T_603) @[dec_tlu_ctl.scala 1924:37]
|
|
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|
|
node _T_604 = or(wr_miccmect_r, io.iccm_sbecc_r) @[dec_tlu_ctl.scala 1926:55]
|
|
|
|
|
node _T_605 = or(_T_604, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1926:73]
|
|
|
|
|
node _T_606 = bits(_T_605, 0, 0) @[dec_tlu_ctl.scala 1926:97]
|
|
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|
|
inst rvclkhdr_16 of rvclkhdr_70 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_16.clock <= clock
|
|
|
|
|
rvclkhdr_16.reset <= reset
|
|
|
|
|
rvclkhdr_16.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_16.io.en <= _T_606 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_16.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_607 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_606 : @[Reg.scala 28:19]
|
|
|
|
|
_T_607 <= miccmect_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
miccmect <= _T_607 @[dec_tlu_ctl.scala 1926:18]
|
|
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|
|
node _T_608 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1928:59]
|
|
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|
|
node _T_609 = dshl(UInt<32>("h0ffffffff"), _T_608) @[dec_tlu_ctl.scala 1928:48]
|
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|
|
|
node _T_610 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1928:92]
|
|
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|
|
node _T_611 = cat(UInt<5>("h00"), _T_610) @[Cat.scala 29:58]
|
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|
|
node _T_612 = and(_T_609, _T_611) @[dec_tlu_ctl.scala 1928:68]
|
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|
|
node _T_613 = orr(_T_612) @[dec_tlu_ctl.scala 1928:101]
|
|
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|
|
miccme_ce_req <= _T_613 @[dec_tlu_ctl.scala 1928:23]
|
|
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|
|
node _T_614 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1937:76]
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|
|
node _T_615 = eq(_T_614, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1937:83]
|
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|
|
node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_615) @[dec_tlu_ctl.scala 1937:54]
|
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|
|
node _T_616 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1938:33]
|
|
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|
|
node _T_617 = cat(UInt<26>("h00"), perfmux_flop.io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58]
|
|
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|
|
node _T_618 = add(_T_616, _T_617) @[dec_tlu_ctl.scala 1938:40]
|
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|
|
node _T_619 = tail(_T_618, 1) @[dec_tlu_ctl.scala 1938:40]
|
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|
|
mdccmect_inc <= _T_619 @[dec_tlu_ctl.scala 1938:22]
|
|
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|
|
node _T_620 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1939:52]
|
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|
|
node _T_621 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1939:92]
|
|
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|
|
node _T_622 = cat(csr_sat, _T_621) @[Cat.scala 29:58]
|
|
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|
|
node _T_623 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1939:114]
|
|
|
|
|
node _T_624 = cat(_T_623, mdccmect_inc) @[Cat.scala 29:58]
|
|
|
|
|
node mdccmect_ns = mux(_T_620, _T_622, _T_624) @[dec_tlu_ctl.scala 1939:37]
|
|
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|
|
node _T_625 = or(wr_mdccmect_r, perfmux_flop.io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1941:56]
|
|
|
|
|
node _T_626 = bits(_T_625, 0, 0) @[dec_tlu_ctl.scala 1941:103]
|
|
|
|
|
inst rvclkhdr_17 of rvclkhdr_71 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_17.clock <= clock
|
|
|
|
|
rvclkhdr_17.reset <= reset
|
|
|
|
|
rvclkhdr_17.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_17.io.en <= _T_626 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_17.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_627 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_626 : @[Reg.scala 28:19]
|
|
|
|
|
_T_627 <= mdccmect_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mdccmect <= _T_627 @[dec_tlu_ctl.scala 1941:18]
|
|
|
|
|
node _T_628 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1942:59]
|
|
|
|
|
node _T_629 = dshl(UInt<32>("h0ffffffff"), _T_628) @[dec_tlu_ctl.scala 1942:48]
|
|
|
|
|
node _T_630 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1942:92]
|
|
|
|
|
node _T_631 = cat(UInt<5>("h00"), _T_630) @[Cat.scala 29:58]
|
|
|
|
|
node _T_632 = and(_T_629, _T_631) @[dec_tlu_ctl.scala 1942:68]
|
|
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|
|
node _T_633 = orr(_T_632) @[dec_tlu_ctl.scala 1942:101]
|
|
|
|
|
mdccme_ce_req <= _T_633 @[dec_tlu_ctl.scala 1942:23]
|
|
|
|
|
node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1952:69]
|
|
|
|
|
node _T_635 = eq(_T_634, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1952:76]
|
|
|
|
|
node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 1952:47]
|
|
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|
|
node _T_636 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1954:39]
|
|
|
|
|
node _T_637 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1954:66]
|
|
|
|
|
node mfdht_ns = mux(_T_636, _T_637, mfdht) @[dec_tlu_ctl.scala 1954:27]
|
|
|
|
|
node _T_638 = bits(wr_mfdht_r, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
reg _T_639 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_638 : @[Reg.scala 28:19]
|
|
|
|
|
_T_639 <= mfdht_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mfdht <= _T_639 @[dec_tlu_ctl.scala 1956:15]
|
|
|
|
|
node _T_640 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1965:69]
|
|
|
|
|
node _T_641 = eq(_T_640, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1965:76]
|
|
|
|
|
node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_641) @[dec_tlu_ctl.scala 1965:47]
|
|
|
|
|
node _T_642 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1967:39]
|
|
|
|
|
node _T_643 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1967:67]
|
|
|
|
|
node _T_644 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1968:42]
|
|
|
|
|
node _T_645 = and(io.dbg_tlu_halted, _T_644) @[dec_tlu_ctl.scala 1968:40]
|
|
|
|
|
node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 1968:64]
|
|
|
|
|
node _T_647 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1968:77]
|
|
|
|
|
node _T_648 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1968:97]
|
|
|
|
|
node _T_649 = cat(_T_647, _T_648) @[Cat.scala 29:58]
|
|
|
|
|
node _T_650 = mux(_T_646, _T_649, mfdhs) @[dec_tlu_ctl.scala 1968:20]
|
|
|
|
|
node mfdhs_ns = mux(_T_642, _T_643, _T_650) @[dec_tlu_ctl.scala 1967:27]
|
|
|
|
|
node _T_651 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1970:76]
|
|
|
|
|
node _T_652 = bits(_T_651, 0, 0) @[dec_tlu_ctl.scala 1970:97]
|
|
|
|
|
reg _T_653 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_652 : @[Reg.scala 28:19]
|
|
|
|
|
_T_653 <= mfdhs_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mfdhs <= _T_653 @[dec_tlu_ctl.scala 1970:15]
|
|
|
|
|
node _T_654 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1972:54]
|
|
|
|
|
node _T_655 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1972:81]
|
|
|
|
|
node _T_656 = tail(_T_655, 1) @[dec_tlu_ctl.scala 1972:81]
|
|
|
|
|
node _T_657 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1973:41]
|
|
|
|
|
node _T_658 = mux(_T_657, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1973:20]
|
|
|
|
|
node force_halt_ctr = mux(_T_654, _T_656, _T_658) @[dec_tlu_ctl.scala 1972:33]
|
|
|
|
|
node _T_659 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1975:56]
|
|
|
|
|
inst rvclkhdr_18 of rvclkhdr_72 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_18.clock <= clock
|
|
|
|
|
rvclkhdr_18.reset <= reset
|
|
|
|
|
rvclkhdr_18.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_18.io.en <= _T_659 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_18.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_660 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_659 : @[Reg.scala 28:19]
|
|
|
|
|
_T_660 <= force_halt_ctr @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
force_halt_ctr_f <= _T_660 @[dec_tlu_ctl.scala 1975:26]
|
|
|
|
|
node _T_661 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1977:31]
|
|
|
|
|
node _T_662 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1977:86]
|
|
|
|
|
node _T_663 = dshl(UInt<32>("h0ffffffff"), _T_662) @[dec_tlu_ctl.scala 1977:78]
|
|
|
|
|
node _T_664 = and(force_halt_ctr_f, _T_663) @[dec_tlu_ctl.scala 1977:55]
|
|
|
|
|
node _T_665 = orr(_T_664) @[dec_tlu_ctl.scala 1977:94]
|
|
|
|
|
node _T_666 = and(_T_661, _T_665) @[dec_tlu_ctl.scala 1977:35]
|
|
|
|
|
io.force_halt <= _T_666 @[dec_tlu_ctl.scala 1977:23]
|
|
|
|
|
node _T_667 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1985:69]
|
|
|
|
|
node _T_668 = eq(_T_667, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1985:76]
|
|
|
|
|
node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_668) @[dec_tlu_ctl.scala 1985:47]
|
|
|
|
|
node _T_669 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1987:47]
|
|
|
|
|
node _T_670 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1987:66]
|
|
|
|
|
inst rvclkhdr_19 of rvclkhdr_73 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_19.clock <= clock
|
|
|
|
|
rvclkhdr_19.reset <= reset
|
|
|
|
|
rvclkhdr_19.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_19.io.en <= _T_670 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_19.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg meivt : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_670 : @[Reg.scala 28:19]
|
|
|
|
|
meivt <= _T_669 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_671 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1999:56]
|
|
|
|
|
inst rvclkhdr_20 of rvclkhdr_74 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_20.clock <= clock
|
|
|
|
|
rvclkhdr_20.reset <= reset
|
|
|
|
|
rvclkhdr_20.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_20.io.en <= _T_671 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_20.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg meihap : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_671 : @[Reg.scala 28:19]
|
|
|
|
|
meihap <= io.pic_claimid @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_672 = cat(meivt, meihap) @[Cat.scala 29:58]
|
|
|
|
|
io.dec_tlu_meihap <= _T_672 @[dec_tlu_ctl.scala 2000:27]
|
|
|
|
|
node _T_673 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2009:72]
|
|
|
|
|
node _T_674 = eq(_T_673, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 2009:79]
|
|
|
|
|
node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_674) @[dec_tlu_ctl.scala 2009:50]
|
|
|
|
|
node _T_675 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 2010:45]
|
|
|
|
|
node _T_676 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2010:72]
|
|
|
|
|
node meicurpl_ns = mux(_T_675, _T_676, meicurpl) @[dec_tlu_ctl.scala 2010:30]
|
|
|
|
|
reg _T_677 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2012:53]
|
|
|
|
|
_T_677 <= meicurpl_ns @[dec_tlu_ctl.scala 2012:53]
|
|
|
|
|
meicurpl <= _T_677 @[dec_tlu_ctl.scala 2012:18]
|
|
|
|
|
io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 2014:29]
|
|
|
|
|
node _T_678 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2024:73]
|
|
|
|
|
node _T_679 = eq(_T_678, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 2024:80]
|
|
|
|
|
node _T_680 = and(io.dec_csr_wen_r_mod, _T_679) @[dec_tlu_ctl.scala 2024:51]
|
|
|
|
|
node wr_meicidpl_r = or(_T_680, io.take_ext_int_start) @[dec_tlu_ctl.scala 2024:95]
|
|
|
|
|
node _T_681 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 2026:44]
|
|
|
|
|
node _T_682 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 2027:35]
|
|
|
|
|
node _T_683 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2027:62]
|
|
|
|
|
node _T_684 = mux(_T_682, _T_683, perfmux_flop.io.meicidpl) @[dec_tlu_ctl.scala 2027:20]
|
|
|
|
|
node meicidpl_ns = mux(_T_681, io.pic_pl, _T_684) @[dec_tlu_ctl.scala 2026:30]
|
|
|
|
|
node _T_685 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2036:69]
|
|
|
|
|
node _T_686 = eq(_T_685, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 2036:76]
|
|
|
|
|
node _T_687 = and(io.dec_csr_wen_r_mod, _T_686) @[dec_tlu_ctl.scala 2036:47]
|
|
|
|
|
node _T_688 = or(_T_687, io.take_ext_int_start) @[dec_tlu_ctl.scala 2036:90]
|
|
|
|
|
wr_meicpct_r <= _T_688 @[dec_tlu_ctl.scala 2036:22]
|
|
|
|
|
node _T_689 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2045:69]
|
|
|
|
|
node _T_690 = eq(_T_689, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2045:76]
|
|
|
|
|
node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_690) @[dec_tlu_ctl.scala 2045:47]
|
|
|
|
|
node _T_691 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2046:39]
|
|
|
|
|
node _T_692 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2046:66]
|
|
|
|
|
node meipt_ns = mux(_T_691, _T_692, meipt) @[dec_tlu_ctl.scala 2046:27]
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reg _T_693 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2048:50]
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|
|
_T_693 <= meipt_ns @[dec_tlu_ctl.scala 2048:50]
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|
meipt <= _T_693 @[dec_tlu_ctl.scala 2048:15]
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io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2050:26]
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node _T_694 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2076:96]
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node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_694) @[dec_tlu_ctl.scala 2076:73]
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node _T_695 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2079:47]
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node _T_696 = and(io.dcsr_single_step_done_f, _T_695) @[dec_tlu_ctl.scala 2079:45]
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node _T_697 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2079:79]
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node _T_698 = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2079:77]
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node _T_699 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2079:114]
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node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2079:112]
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node _T_701 = bits(_T_700, 0, 0) @[dec_tlu_ctl.scala 2079:134]
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node _T_702 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2080:38]
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node _T_703 = and(io.debug_halt_req, _T_702) @[dec_tlu_ctl.scala 2080:36]
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node _T_704 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2080:70]
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node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 2080:68]
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node _T_706 = bits(_T_705, 0, 0) @[dec_tlu_ctl.scala 2080:104]
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node _T_707 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2081:49]
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node _T_708 = and(io.ebreak_to_debug_mode_r_d1, _T_707) @[dec_tlu_ctl.scala 2081:47]
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node _T_709 = bits(_T_708, 0, 0) @[dec_tlu_ctl.scala 2081:83]
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node _T_710 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2082:51]
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node _T_711 = mux(_T_701, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_712 = mux(_T_706, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_713 = mux(_T_709, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_714 = mux(_T_710, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_715 = or(_T_711, _T_712) @[Mux.scala 27:72]
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node _T_716 = or(_T_715, _T_713) @[Mux.scala 27:72]
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node _T_717 = or(_T_716, _T_714) @[Mux.scala 27:72]
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wire dcsr_cause : UInt<3> @[Mux.scala 27:72]
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dcsr_cause <= _T_717 @[Mux.scala 27:72]
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node _T_718 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2084:53]
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node _T_719 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2084:98]
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node _T_720 = eq(_T_719, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2084:105]
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node wr_dcsr_r = and(_T_718, _T_720) @[dec_tlu_ctl.scala 2084:76]
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node _T_721 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2090:76]
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node _T_722 = eq(_T_721, UInt<3>("h03")) @[dec_tlu_ctl.scala 2090:82]
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node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_722) @[dec_tlu_ctl.scala 2090:66]
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node _T_723 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2091:66]
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node _T_724 = or(_T_723, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2091:85]
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node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_724) @[dec_tlu_ctl.scala 2091:63]
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node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2093:55]
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node _T_725 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2094:51]
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node _T_726 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2094:71]
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node _T_727 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2094:98]
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node _T_728 = cat(_T_727, UInt<2>("h03")) @[Cat.scala 29:58]
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node _T_729 = cat(_T_726, dcsr_cause) @[Cat.scala 29:58]
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node _T_730 = cat(_T_729, _T_728) @[Cat.scala 29:58]
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node _T_731 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2095:31]
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node _T_732 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2095:62]
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node _T_733 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2095:97]
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node _T_734 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2095:123]
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node _T_735 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2095:167]
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node _T_736 = or(nmi_in_debug_mode, _T_735) @[dec_tlu_ctl.scala 2095:158]
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node _T_737 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2095:191]
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node _T_738 = cat(_T_737, UInt<2>("h03")) @[Cat.scala 29:58]
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|
node _T_739 = cat(UInt<2>("h00"), _T_736) @[Cat.scala 29:58]
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|
node _T_740 = cat(_T_739, _T_738) @[Cat.scala 29:58]
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node _T_741 = cat(UInt<1>("h00"), _T_734) @[Cat.scala 29:58]
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|
node _T_742 = cat(_T_732, UInt<3>("h00")) @[Cat.scala 29:58]
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|
node _T_743 = cat(_T_742, _T_733) @[Cat.scala 29:58]
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|
node _T_744 = cat(_T_743, _T_741) @[Cat.scala 29:58]
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|
node _T_745 = cat(_T_744, _T_740) @[Cat.scala 29:58]
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|
node _T_746 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2095:224]
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|
node _T_747 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2095:258]
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|
|
node _T_748 = cat(_T_747, UInt<2>("h03")) @[Cat.scala 29:58]
|
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|
node _T_749 = cat(_T_746, nmi_in_debug_mode) @[Cat.scala 29:58]
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|
node _T_750 = cat(_T_749, _T_748) @[Cat.scala 29:58]
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|
node _T_751 = mux(_T_731, _T_745, _T_750) @[dec_tlu_ctl.scala 2095:20]
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|
|
node dcsr_ns = mux(_T_725, _T_730, _T_751) @[dec_tlu_ctl.scala 2094:26]
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|
node _T_752 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2098:61]
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|
node _T_753 = or(_T_752, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2098:73]
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|
node _T_754 = or(_T_753, io.take_nmi) @[dec_tlu_ctl.scala 2098:101]
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|
|
node _T_755 = bits(_T_754, 0, 0) @[dec_tlu_ctl.scala 2098:116]
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|
inst rvclkhdr_21 of rvclkhdr_75 @[lib.scala 404:23]
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|
|
rvclkhdr_21.clock <= clock
|
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|
|
rvclkhdr_21.reset <= reset
|
|
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|
|
rvclkhdr_21.io.clk <= io.free_l2clk @[lib.scala 406:18]
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|
|
rvclkhdr_21.io.en <= _T_755 @[lib.scala 407:17]
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|
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|
|
rvclkhdr_21.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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|
|
reg _T_756 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
|
when _T_755 : @[Reg.scala 28:19]
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|
|
_T_756 <= dcsr_ns @[Reg.scala 28:23]
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|
|
skip @[Reg.scala 28:19]
|
|
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|
|
io.dcsr <= _T_756 @[dec_tlu_ctl.scala 2098:17]
|
|
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|
|
node _T_757 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2106:52]
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|
|
node _T_758 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2106:97]
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|
|
node _T_759 = eq(_T_758, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2106:104]
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|
|
node wr_dpc_r = and(_T_757, _T_759) @[dec_tlu_ctl.scala 2106:75]
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|
|
node _T_760 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2107:51]
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|
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|
|
node _T_761 = and(io.dbg_tlu_halted, _T_760) @[dec_tlu_ctl.scala 2107:49]
|
|
|
|
|
node _T_762 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2107:74]
|
|
|
|
|
node dpc_capture_npc = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2107:72]
|
|
|
|
|
node _T_763 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2111:18]
|
|
|
|
|
node _T_764 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2111:36]
|
|
|
|
|
node _T_765 = and(_T_763, _T_764) @[dec_tlu_ctl.scala 2111:34]
|
|
|
|
|
node _T_766 = and(_T_765, wr_dpc_r) @[dec_tlu_ctl.scala 2111:53]
|
|
|
|
|
node _T_767 = bits(_T_766, 0, 0) @[dec_tlu_ctl.scala 2111:65]
|
|
|
|
|
node _T_768 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2111:94]
|
|
|
|
|
node _T_769 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2112:34]
|
|
|
|
|
node _T_770 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2113:18]
|
|
|
|
|
node _T_771 = and(_T_770, dpc_capture_npc) @[dec_tlu_ctl.scala 2113:34]
|
|
|
|
|
node _T_772 = bits(_T_771, 0, 0) @[dec_tlu_ctl.scala 2113:53]
|
|
|
|
|
node _T_773 = mux(_T_767, _T_768, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_774 = mux(_T_769, pc_r, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_775 = mux(_T_772, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72]
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|
|
|
|
node _T_776 = or(_T_773, _T_774) @[Mux.scala 27:72]
|
|
|
|
|
node _T_777 = or(_T_776, _T_775) @[Mux.scala 27:72]
|
|
|
|
|
wire dpc_ns : UInt<31> @[Mux.scala 27:72]
|
|
|
|
|
dpc_ns <= _T_777 @[Mux.scala 27:72]
|
|
|
|
|
node _T_778 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2115:43]
|
|
|
|
|
node _T_779 = or(_T_778, dpc_capture_npc) @[dec_tlu_ctl.scala 2115:60]
|
|
|
|
|
node _T_780 = bits(_T_779, 0, 0) @[dec_tlu_ctl.scala 2115:79]
|
|
|
|
|
inst rvclkhdr_22 of rvclkhdr_76 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_22.clock <= clock
|
|
|
|
|
rvclkhdr_22.reset <= reset
|
|
|
|
|
rvclkhdr_22.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_22.io.en <= _T_780 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_22.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_781 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_780 : @[Reg.scala 28:19]
|
|
|
|
|
_T_781 <= dpc_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.dpc <= _T_781 @[dec_tlu_ctl.scala 2115:16]
|
|
|
|
|
node _T_782 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2129:50]
|
|
|
|
|
node _T_783 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2129:75]
|
|
|
|
|
node _T_784 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2129:103]
|
|
|
|
|
node _T_785 = cat(_T_782, _T_783) @[Cat.scala 29:58]
|
|
|
|
|
node dicawics_ns = cat(_T_785, _T_784) @[Cat.scala 29:58]
|
|
|
|
|
node _T_786 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2130:57]
|
|
|
|
|
node _T_787 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2130:102]
|
|
|
|
|
node _T_788 = eq(_T_787, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2130:109]
|
|
|
|
|
node wr_dicawics_r = and(_T_786, _T_788) @[dec_tlu_ctl.scala 2130:80]
|
|
|
|
|
node _T_789 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2132:57]
|
|
|
|
|
inst rvclkhdr_23 of rvclkhdr_77 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_23.clock <= clock
|
|
|
|
|
rvclkhdr_23.reset <= reset
|
|
|
|
|
rvclkhdr_23.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_23.io.en <= _T_789 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_23.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg dicawics : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_789 : @[Reg.scala 28:19]
|
|
|
|
|
dicawics <= dicawics_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_790 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2148:55]
|
|
|
|
|
node _T_791 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2148:100]
|
|
|
|
|
node _T_792 = eq(_T_791, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2148:107]
|
|
|
|
|
node wr_dicad0_r = and(_T_790, _T_792) @[dec_tlu_ctl.scala 2148:78]
|
|
|
|
|
node _T_793 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2149:41]
|
|
|
|
|
node _T_794 = bits(io.ifu_ic_debug_rd_data, 31, 0) @[dec_tlu_ctl.scala 2149:93]
|
|
|
|
|
node dicad0_ns = mux(_T_793, io.dec_csr_wrdata_r, _T_794) @[dec_tlu_ctl.scala 2149:28]
|
|
|
|
|
node _T_795 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2151:53]
|
|
|
|
|
node _T_796 = bits(_T_795, 0, 0) @[dec_tlu_ctl.scala 2151:86]
|
|
|
|
|
inst rvclkhdr_24 of rvclkhdr_78 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_24.clock <= clock
|
|
|
|
|
rvclkhdr_24.reset <= reset
|
|
|
|
|
rvclkhdr_24.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_24.io.en <= _T_796 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_24.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg dicad0 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_796 : @[Reg.scala 28:19]
|
|
|
|
|
dicad0 <= dicad0_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_797 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2161:56]
|
|
|
|
|
node _T_798 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2161:101]
|
|
|
|
|
node _T_799 = eq(_T_798, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2161:108]
|
|
|
|
|
node wr_dicad0h_r = and(_T_797, _T_799) @[dec_tlu_ctl.scala 2161:79]
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node _T_800 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2163:43]
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node _T_801 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2163:95]
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node dicad0h_ns = mux(_T_800, io.dec_csr_wrdata_r, _T_801) @[dec_tlu_ctl.scala 2163:29]
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node _T_802 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2165:55]
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node _T_803 = bits(_T_802, 0, 0) @[dec_tlu_ctl.scala 2165:88]
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inst rvclkhdr_25 of rvclkhdr_79 @[lib.scala 404:23]
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rvclkhdr_25.clock <= clock
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rvclkhdr_25.reset <= reset
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rvclkhdr_25.io.clk <= clock @[lib.scala 406:18]
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rvclkhdr_25.io.en <= _T_803 @[lib.scala 407:17]
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rvclkhdr_25.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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reg dicad0h : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_803 : @[Reg.scala 28:19]
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dicad0h <= dicad0h_ns @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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wire _T_804 : UInt<7>
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_T_804 <= UInt<1>("h00")
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node _T_805 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2173:63]
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node _T_806 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2173:108]
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node _T_807 = eq(_T_806, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2173:115]
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node _T_808 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2173:86]
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node _T_809 = bits(_T_808, 0, 0) @[dec_tlu_ctl.scala 2175:49]
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node _T_810 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2175:76]
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node _T_811 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2175:106]
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node _T_812 = mux(_T_809, _T_810, _T_811) @[dec_tlu_ctl.scala 2175:36]
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node _T_813 = or(_T_808, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2177:61]
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node _T_814 = bits(_T_813, 0, 0) @[dec_tlu_ctl.scala 2177:94]
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inst rvclkhdr_26 of rvclkhdr_80 @[lib.scala 404:23]
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|
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rvclkhdr_26.clock <= clock
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|
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rvclkhdr_26.reset <= reset
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|
|
rvclkhdr_26.io.clk <= clock @[lib.scala 406:18]
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|
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rvclkhdr_26.io.en <= _T_814 @[lib.scala 407:17]
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|
|
rvclkhdr_26.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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reg _T_815 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
|
when _T_814 : @[Reg.scala 28:19]
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|
|
_T_815 <= _T_812 @[Reg.scala 28:23]
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|
|
skip @[Reg.scala 28:19]
|
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|
|
_T_804 <= _T_815 @[dec_tlu_ctl.scala 2177:28]
|
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|
|
node _T_816 = cat(UInt<25>("h00"), _T_804) @[Cat.scala 29:58]
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|
|
dicad1 <= _T_816 @[dec_tlu_ctl.scala 2178:24]
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node _T_817 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2200:76]
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node _T_818 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2200:90]
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|
|
node _T_819 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2200:104]
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|
|
node _T_820 = cat(_T_817, _T_818) @[Cat.scala 29:58]
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|
node _T_821 = cat(_T_820, _T_819) @[Cat.scala 29:58]
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|
io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_821 @[dec_tlu_ctl.scala 2200:63]
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|
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io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2203:48]
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|
|
node _T_822 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2205:59]
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|
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node _T_823 = and(_T_822, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2205:82]
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|
node _T_824 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2205:105]
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|
|
node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 2205:103]
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|
|
node _T_826 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2205:149]
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|
|
node _T_827 = eq(_T_826, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2205:156]
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|
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|
|
node icache_rd_valid = and(_T_825, _T_827) @[dec_tlu_ctl.scala 2205:127]
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|
|
node _T_828 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2206:59]
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|
|
node _T_829 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2206:104]
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|
|
node _T_830 = eq(_T_829, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2206:111]
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|
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|
|
node icache_wr_valid = and(_T_828, _T_830) @[dec_tlu_ctl.scala 2206:82]
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|
|
io.dec_tlu_ic_diag_pkt.icache_rd_valid <= perfmux_flop.io.icache_rd_valid_f @[dec_tlu_ctl.scala 2211:48]
|
|
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|
|
io.dec_tlu_ic_diag_pkt.icache_wr_valid <= perfmux_flop.io.icache_wr_valid_f @[dec_tlu_ctl.scala 2212:48]
|
|
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|
|
node _T_831 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2220:69]
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|
|
node _T_832 = eq(_T_831, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2220:76]
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|
|
node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_832) @[dec_tlu_ctl.scala 2220:47]
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|
|
node _T_833 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2221:39]
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|
|
node _T_834 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2221:66]
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|
|
node mtsel_ns = mux(_T_833, _T_834, mtsel) @[dec_tlu_ctl.scala 2221:27]
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|
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|
|
reg _T_835 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2223:50]
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|
|
_T_835 <= mtsel_ns @[dec_tlu_ctl.scala 2223:50]
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|
|
mtsel <= _T_835 @[dec_tlu_ctl.scala 2223:15]
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|
|
node _T_836 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2258:45]
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|
node _T_837 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2258:71]
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|
node _T_838 = not(_T_837) @[dec_tlu_ctl.scala 2258:51]
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|
|
node tdata_load = and(_T_836, _T_838) @[dec_tlu_ctl.scala 2258:49]
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|
|
node _T_839 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2260:47]
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|
node _T_840 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2260:73]
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node _T_841 = not(_T_840) @[dec_tlu_ctl.scala 2260:53]
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|
node tdata_opcode = and(_T_839, _T_841) @[dec_tlu_ctl.scala 2260:51]
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|
|
node _T_842 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2262:48]
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|
node _T_843 = and(_T_842, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2262:53]
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|
node _T_844 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2262:97]
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|
|
node tdata_action = and(_T_843, _T_844) @[dec_tlu_ctl.scala 2262:76]
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|
|
node _T_845 = bits(mtsel, 0, 0) @[dec_tlu_ctl.scala 2265:36]
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|
|
node _T_846 = bits(mtsel, 1, 1) @[dec_tlu_ctl.scala 2266:26]
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|
|
node _T_847 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2266:51]
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|
node _T_848 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2266:75]
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|
|
node _T_849 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2266:113]
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|
|
node _T_850 = not(_T_849) @[dec_tlu_ctl.scala 2266:93]
|
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|
|
node _T_851 = and(_T_848, _T_850) @[dec_tlu_ctl.scala 2266:91]
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|
|
node _T_852 = not(_T_851) @[dec_tlu_ctl.scala 2266:58]
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|
|
node _T_853 = and(_T_847, _T_852) @[dec_tlu_ctl.scala 2266:56]
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|
|
node _T_854 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2267:44]
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|
|
|
|
node _T_855 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2267:68]
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|
|
|
|
node _T_856 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2267:106]
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|
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|
|
node _T_857 = not(_T_856) @[dec_tlu_ctl.scala 2267:86]
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|
|
node _T_858 = and(_T_855, _T_857) @[dec_tlu_ctl.scala 2267:84]
|
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|
|
|
node _T_859 = not(_T_858) @[dec_tlu_ctl.scala 2267:51]
|
|
|
|
|
node _T_860 = and(_T_854, _T_859) @[dec_tlu_ctl.scala 2267:49]
|
|
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|
|
node _T_861 = mux(_T_846, _T_853, _T_860) @[dec_tlu_ctl.scala 2266:20]
|
|
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|
|
node tdata_chain = mux(_T_845, UInt<1>("h00"), _T_861) @[dec_tlu_ctl.scala 2265:30]
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|
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|
|
node _T_862 = bits(mtsel, 1, 1) @[dec_tlu_ctl.scala 2270:41]
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|
|
node _T_863 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2270:65]
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|
|
node _T_864 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2270:89]
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|
|
node _T_865 = not(_T_864) @[dec_tlu_ctl.scala 2270:73]
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|
|
|
|
node _T_866 = bits(io.mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 2270:122]
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|
|
|
node _T_867 = and(_T_865, _T_866) @[dec_tlu_ctl.scala 2270:105]
|
|
|
|
|
node _T_868 = and(_T_863, _T_867) @[dec_tlu_ctl.scala 2270:70]
|
|
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|
|
node _T_869 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2271:36]
|
|
|
|
|
node _T_870 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2271:60]
|
|
|
|
|
node _T_871 = not(_T_870) @[dec_tlu_ctl.scala 2271:44]
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|
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|
|
node _T_872 = bits(io.mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 2271:93]
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|
|
node _T_873 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2271:76]
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|
|
node _T_874 = and(_T_869, _T_873) @[dec_tlu_ctl.scala 2271:41]
|
|
|
|
|
node tdata_kill_write = mux(_T_862, _T_868, _T_874) @[dec_tlu_ctl.scala 2270:35]
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|
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|
|
node _T_875 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2273:54]
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|
|
|
|
node _T_876 = and(_T_875, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2273:59]
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|
|
|
|
node _T_877 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2273:101]
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|
|
node _T_878 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2273:157]
|
|
|
|
|
node _T_879 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2273:197]
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|
|
|
|
node _T_880 = cat(_T_879, tdata_load) @[Cat.scala 29:58]
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|
|
node _T_881 = cat(_T_878, tdata_opcode) @[Cat.scala 29:58]
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|
|
node _T_882 = cat(_T_881, _T_880) @[Cat.scala 29:58]
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|
|
|
|
node _T_883 = cat(tdata_action, tdata_chain) @[Cat.scala 29:58]
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|
|
node _T_884 = cat(_T_876, _T_877) @[Cat.scala 29:58]
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|
|
node _T_885 = cat(_T_884, _T_883) @[Cat.scala 29:58]
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|
|
node tdata_wrdata_r = cat(_T_885, _T_882) @[Cat.scala 29:58]
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|
|
node _T_886 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:120]
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|
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|
|
node _T_887 = eq(_T_886, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:127]
|
|
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|
|
node _T_888 = and(io.dec_csr_wen_r_mod, _T_887) @[dec_tlu_ctl.scala 2276:98]
|
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|
|
node _T_889 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2276:149]
|
|
|
|
|
node _T_890 = and(_T_888, _T_889) @[dec_tlu_ctl.scala 2276:140]
|
|
|
|
|
node _T_891 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2276:182]
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|
|
|
|
node _T_892 = eq(_T_891, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:166]
|
|
|
|
|
node _T_893 = or(_T_892, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:198]
|
|
|
|
|
node _T_894 = and(_T_890, _T_893) @[dec_tlu_ctl.scala 2276:163]
|
|
|
|
|
node _T_895 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:269]
|
|
|
|
|
node _T_896 = eq(_T_895, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:276]
|
|
|
|
|
node _T_897 = and(io.dec_csr_wen_r_mod, _T_896) @[dec_tlu_ctl.scala 2276:247]
|
|
|
|
|
node _T_898 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2276:298]
|
|
|
|
|
node _T_899 = and(_T_897, _T_898) @[dec_tlu_ctl.scala 2276:289]
|
|
|
|
|
node _T_900 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2276:331]
|
|
|
|
|
node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:315]
|
|
|
|
|
node _T_902 = or(_T_901, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:347]
|
|
|
|
|
node _T_903 = and(_T_899, _T_902) @[dec_tlu_ctl.scala 2276:312]
|
|
|
|
|
node _T_904 = eq(tdata_kill_write, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:373]
|
|
|
|
|
node _T_905 = and(_T_903, _T_904) @[dec_tlu_ctl.scala 2276:371]
|
|
|
|
|
node _T_906 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:120]
|
|
|
|
|
node _T_907 = eq(_T_906, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:127]
|
|
|
|
|
node _T_908 = and(io.dec_csr_wen_r_mod, _T_907) @[dec_tlu_ctl.scala 2276:98]
|
|
|
|
|
node _T_909 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:149]
|
|
|
|
|
node _T_910 = and(_T_908, _T_909) @[dec_tlu_ctl.scala 2276:140]
|
|
|
|
|
node _T_911 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2276:182]
|
|
|
|
|
node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:166]
|
|
|
|
|
node _T_913 = or(_T_912, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:198]
|
|
|
|
|
node _T_914 = and(_T_910, _T_913) @[dec_tlu_ctl.scala 2276:163]
|
|
|
|
|
node _T_915 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2276:269]
|
|
|
|
|
node _T_916 = eq(_T_915, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2276:276]
|
|
|
|
|
node _T_917 = and(io.dec_csr_wen_r_mod, _T_916) @[dec_tlu_ctl.scala 2276:247]
|
|
|
|
|
node _T_918 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:298]
|
|
|
|
|
node _T_919 = and(_T_917, _T_918) @[dec_tlu_ctl.scala 2276:289]
|
|
|
|
|
node _T_920 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2276:331]
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|
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node _T_921 = eq(_T_920, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:315]
|
|
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|
|
node _T_922 = or(_T_921, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2276:347]
|
|
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|
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node _T_923 = and(_T_919, _T_922) @[dec_tlu_ctl.scala 2276:312]
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|
|
node _T_924 = eq(tdata_kill_write, UInt<1>("h00")) @[dec_tlu_ctl.scala 2276:373]
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|
|
node _T_925 = and(_T_923, _T_924) @[dec_tlu_ctl.scala 2276:371]
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|
|
wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2276:49]
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|
|
wr_mtdata1_t_r[0] <= _T_894 @[dec_tlu_ctl.scala 2276:49]
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wr_mtdata1_t_r[1] <= _T_905 @[dec_tlu_ctl.scala 2276:49]
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wr_mtdata1_t_r[2] <= _T_914 @[dec_tlu_ctl.scala 2276:49]
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wr_mtdata1_t_r[3] <= _T_925 @[dec_tlu_ctl.scala 2276:49]
|
|
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node _T_926 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2278:77]
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node _T_927 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2278:120]
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node _T_928 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2278:144]
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node _T_929 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2278:165]
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node _T_930 = or(_T_928, _T_929) @[dec_tlu_ctl.scala 2278:148]
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node _T_931 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2278:185]
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node _T_932 = cat(_T_927, _T_930) @[Cat.scala 29:58]
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node _T_933 = cat(_T_932, _T_931) @[Cat.scala 29:58]
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node _T_934 = mux(_T_926, tdata_wrdata_r, _T_933) @[dec_tlu_ctl.scala 2278:58]
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node _T_935 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2278:77]
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node _T_936 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2278:120]
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node _T_937 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2278:144]
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node _T_938 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2278:165]
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node _T_939 = or(_T_937, _T_938) @[dec_tlu_ctl.scala 2278:148]
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node _T_940 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2278:185]
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node _T_941 = cat(_T_936, _T_939) @[Cat.scala 29:58]
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node _T_942 = cat(_T_941, _T_940) @[Cat.scala 29:58]
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node _T_943 = mux(_T_935, tdata_wrdata_r, _T_942) @[dec_tlu_ctl.scala 2278:58]
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node _T_944 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2278:77]
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node _T_945 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2278:120]
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node _T_946 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2278:144]
|
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|
node _T_947 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2278:165]
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|
node _T_948 = or(_T_946, _T_947) @[dec_tlu_ctl.scala 2278:148]
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|
node _T_949 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2278:185]
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node _T_950 = cat(_T_945, _T_948) @[Cat.scala 29:58]
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node _T_951 = cat(_T_950, _T_949) @[Cat.scala 29:58]
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node _T_952 = mux(_T_944, tdata_wrdata_r, _T_951) @[dec_tlu_ctl.scala 2278:58]
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node _T_953 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2278:77]
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node _T_954 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2278:120]
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node _T_955 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2278:144]
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node _T_956 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2278:165]
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node _T_957 = or(_T_955, _T_956) @[dec_tlu_ctl.scala 2278:148]
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|
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node _T_958 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2278:185]
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|
node _T_959 = cat(_T_954, _T_957) @[Cat.scala 29:58]
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node _T_960 = cat(_T_959, _T_958) @[Cat.scala 29:58]
|
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node _T_961 = mux(_T_953, tdata_wrdata_r, _T_960) @[dec_tlu_ctl.scala 2278:58]
|
|
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|
|
wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2278:49]
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|
|
|
mtdata1_t_ns[0] <= _T_934 @[dec_tlu_ctl.scala 2278:49]
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|
|
mtdata1_t_ns[1] <= _T_943 @[dec_tlu_ctl.scala 2278:49]
|
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|
mtdata1_t_ns[2] <= _T_952 @[dec_tlu_ctl.scala 2278:49]
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|
|
mtdata1_t_ns[3] <= _T_961 @[dec_tlu_ctl.scala 2278:49]
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|
|
node _T_962 = bits(io.trigger_enabled, 0, 0) @[dec_tlu_ctl.scala 2282:91]
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|
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node _T_963 = or(_T_962, wr_mtdata1_t_r[0]) @[dec_tlu_ctl.scala 2282:95]
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|
|
node _T_964 = bits(_T_963, 0, 0) @[lib.scala 8:44]
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|
|
inst rvclkhdr_27 of rvclkhdr_81 @[lib.scala 404:23]
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|
|
rvclkhdr_27.clock <= clock
|
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|
|
rvclkhdr_27.reset <= reset
|
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|
|
rvclkhdr_27.io.clk <= clock @[lib.scala 406:18]
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|
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|
|
rvclkhdr_27.io.en <= _T_964 @[lib.scala 407:17]
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|
|
rvclkhdr_27.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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|
|
reg _T_965 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
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|
|
when _T_964 : @[Reg.scala 28:19]
|
|
|
|
|
_T_965 <= mtdata1_t_ns[0] @[Reg.scala 28:23]
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|
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|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mtdata1_t[0] <= _T_965 @[dec_tlu_ctl.scala 2282:47]
|
|
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|
|
node _T_966 = bits(io.trigger_enabled, 1, 1) @[dec_tlu_ctl.scala 2282:91]
|
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|
|
node _T_967 = or(_T_966, wr_mtdata1_t_r[1]) @[dec_tlu_ctl.scala 2282:95]
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|
|
node _T_968 = bits(_T_967, 0, 0) @[lib.scala 8:44]
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|
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|
|
inst rvclkhdr_28 of rvclkhdr_82 @[lib.scala 404:23]
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|
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|
|
rvclkhdr_28.clock <= clock
|
|
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|
|
rvclkhdr_28.reset <= reset
|
|
|
|
|
rvclkhdr_28.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_28.io.en <= _T_968 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_28.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
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|
|
reg _T_969 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
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|
|
when _T_968 : @[Reg.scala 28:19]
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|
|
_T_969 <= mtdata1_t_ns[1] @[Reg.scala 28:23]
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|
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|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mtdata1_t[1] <= _T_969 @[dec_tlu_ctl.scala 2282:47]
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|
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|
|
node _T_970 = bits(io.trigger_enabled, 2, 2) @[dec_tlu_ctl.scala 2282:91]
|
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|
|
node _T_971 = or(_T_970, wr_mtdata1_t_r[2]) @[dec_tlu_ctl.scala 2282:95]
|
|
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|
|
node _T_972 = bits(_T_971, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
inst rvclkhdr_29 of rvclkhdr_83 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_29.clock <= clock
|
|
|
|
|
rvclkhdr_29.reset <= reset
|
|
|
|
|
rvclkhdr_29.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_29.io.en <= _T_972 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_29.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_973 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_972 : @[Reg.scala 28:19]
|
|
|
|
|
_T_973 <= mtdata1_t_ns[2] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mtdata1_t[2] <= _T_973 @[dec_tlu_ctl.scala 2282:47]
|
|
|
|
|
node _T_974 = bits(io.trigger_enabled, 3, 3) @[dec_tlu_ctl.scala 2282:91]
|
|
|
|
|
node _T_975 = or(_T_974, wr_mtdata1_t_r[3]) @[dec_tlu_ctl.scala 2282:95]
|
|
|
|
|
node _T_976 = bits(_T_975, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
inst rvclkhdr_30 of rvclkhdr_84 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_30.clock <= clock
|
|
|
|
|
rvclkhdr_30.reset <= reset
|
|
|
|
|
rvclkhdr_30.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_30.io.en <= _T_976 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_30.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_977 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_976 : @[Reg.scala 28:19]
|
|
|
|
|
_T_977 <= mtdata1_t_ns[3] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.mtdata1_t[3] <= _T_977 @[dec_tlu_ctl.scala 2282:47]
|
|
|
|
|
node _T_978 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2285:66]
|
|
|
|
|
node _T_979 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2285:112]
|
|
|
|
|
node _T_980 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2285:150]
|
|
|
|
|
node _T_981 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2285:182]
|
|
|
|
|
node _T_982 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2285:214]
|
|
|
|
|
node _T_983 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2285:246]
|
|
|
|
|
node _T_984 = cat(UInt<3>("h00"), _T_983) @[Cat.scala 29:58]
|
|
|
|
|
node _T_985 = cat(_T_981, UInt<3>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_986 = cat(_T_985, _T_982) @[Cat.scala 29:58]
|
|
|
|
|
node _T_987 = cat(_T_986, _T_984) @[Cat.scala 29:58]
|
|
|
|
|
node _T_988 = cat(_T_980, UInt<6>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_989 = cat(UInt<4>("h02"), _T_979) @[Cat.scala 29:58]
|
|
|
|
|
node _T_990 = cat(_T_989, UInt<6>("h01f")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_991 = cat(_T_990, _T_988) @[Cat.scala 29:58]
|
|
|
|
|
node _T_992 = cat(_T_991, _T_987) @[Cat.scala 29:58]
|
|
|
|
|
node _T_993 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2285:66]
|
|
|
|
|
node _T_994 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2285:112]
|
|
|
|
|
node _T_995 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2285:150]
|
|
|
|
|
node _T_996 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2285:182]
|
|
|
|
|
node _T_997 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2285:214]
|
|
|
|
|
node _T_998 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2285:246]
|
|
|
|
|
node _T_999 = cat(UInt<3>("h00"), _T_998) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1000 = cat(_T_996, UInt<3>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1001 = cat(_T_1000, _T_997) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1002 = cat(_T_1001, _T_999) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1003 = cat(_T_995, UInt<6>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1004 = cat(UInt<4>("h02"), _T_994) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1005 = cat(_T_1004, UInt<6>("h01f")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1006 = cat(_T_1005, _T_1003) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1007 = cat(_T_1006, _T_1002) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1008 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2285:66]
|
|
|
|
|
node _T_1009 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2285:112]
|
|
|
|
|
node _T_1010 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2285:150]
|
|
|
|
|
node _T_1011 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2285:182]
|
|
|
|
|
node _T_1012 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2285:214]
|
|
|
|
|
node _T_1013 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2285:246]
|
|
|
|
|
node _T_1014 = cat(UInt<3>("h00"), _T_1013) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1015 = cat(_T_1011, UInt<3>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1016 = cat(_T_1015, _T_1012) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1017 = cat(_T_1016, _T_1014) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1018 = cat(_T_1010, UInt<6>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1019 = cat(UInt<4>("h02"), _T_1009) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1020 = cat(_T_1019, UInt<6>("h01f")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1021 = cat(_T_1020, _T_1018) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1022 = cat(_T_1021, _T_1017) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1023 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2285:66]
|
|
|
|
|
node _T_1024 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2285:112]
|
|
|
|
|
node _T_1025 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2285:150]
|
|
|
|
|
node _T_1026 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2285:182]
|
|
|
|
|
node _T_1027 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2285:214]
|
|
|
|
|
node _T_1028 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2285:246]
|
|
|
|
|
node _T_1029 = cat(UInt<3>("h00"), _T_1028) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1030 = cat(_T_1026, UInt<3>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1031 = cat(_T_1030, _T_1027) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1032 = cat(_T_1031, _T_1029) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1033 = cat(_T_1025, UInt<6>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1034 = cat(UInt<4>("h02"), _T_1024) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1035 = cat(_T_1034, UInt<6>("h01f")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1036 = cat(_T_1035, _T_1033) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1037 = cat(_T_1036, _T_1032) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1038 = mux(_T_978, _T_992, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1039 = mux(_T_993, _T_1007, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1040 = mux(_T_1008, _T_1022, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1041 = mux(_T_1023, _T_1037, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1042 = or(_T_1038, _T_1039) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1043 = or(_T_1042, _T_1040) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1044 = or(_T_1043, _T_1041) @[Mux.scala 27:72]
|
|
|
|
|
wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
mtdata1_tsel_out <= _T_1044 @[Mux.scala 27:72]
|
|
|
|
|
node _T_1045 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2287:66]
|
|
|
|
|
io.trigger_pkt_any[0].select <= _T_1045 @[dec_tlu_ctl.scala 2287:48]
|
|
|
|
|
node _T_1046 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2288:69]
|
|
|
|
|
io.trigger_pkt_any[0].match_pkt <= _T_1046 @[dec_tlu_ctl.scala 2288:51]
|
|
|
|
|
node _T_1047 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2289:66]
|
|
|
|
|
io.trigger_pkt_any[0].store <= _T_1047 @[dec_tlu_ctl.scala 2289:48]
|
|
|
|
|
node _T_1048 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2290:66]
|
|
|
|
|
io.trigger_pkt_any[0].load <= _T_1048 @[dec_tlu_ctl.scala 2290:48]
|
|
|
|
|
node _T_1049 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2291:66]
|
|
|
|
|
io.trigger_pkt_any[0].execute <= _T_1049 @[dec_tlu_ctl.scala 2291:48]
|
|
|
|
|
node _T_1050 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2292:66]
|
|
|
|
|
io.trigger_pkt_any[0].m <= _T_1050 @[dec_tlu_ctl.scala 2292:48]
|
|
|
|
|
node _T_1051 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2287:66]
|
|
|
|
|
io.trigger_pkt_any[1].select <= _T_1051 @[dec_tlu_ctl.scala 2287:48]
|
|
|
|
|
node _T_1052 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2288:69]
|
|
|
|
|
io.trigger_pkt_any[1].match_pkt <= _T_1052 @[dec_tlu_ctl.scala 2288:51]
|
|
|
|
|
node _T_1053 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2289:66]
|
|
|
|
|
io.trigger_pkt_any[1].store <= _T_1053 @[dec_tlu_ctl.scala 2289:48]
|
|
|
|
|
node _T_1054 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2290:66]
|
|
|
|
|
io.trigger_pkt_any[1].load <= _T_1054 @[dec_tlu_ctl.scala 2290:48]
|
|
|
|
|
node _T_1055 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2291:66]
|
|
|
|
|
io.trigger_pkt_any[1].execute <= _T_1055 @[dec_tlu_ctl.scala 2291:48]
|
|
|
|
|
node _T_1056 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2292:66]
|
|
|
|
|
io.trigger_pkt_any[1].m <= _T_1056 @[dec_tlu_ctl.scala 2292:48]
|
|
|
|
|
node _T_1057 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2287:66]
|
|
|
|
|
io.trigger_pkt_any[2].select <= _T_1057 @[dec_tlu_ctl.scala 2287:48]
|
|
|
|
|
node _T_1058 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2288:69]
|
|
|
|
|
io.trigger_pkt_any[2].match_pkt <= _T_1058 @[dec_tlu_ctl.scala 2288:51]
|
|
|
|
|
node _T_1059 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2289:66]
|
|
|
|
|
io.trigger_pkt_any[2].store <= _T_1059 @[dec_tlu_ctl.scala 2289:48]
|
|
|
|
|
node _T_1060 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2290:66]
|
|
|
|
|
io.trigger_pkt_any[2].load <= _T_1060 @[dec_tlu_ctl.scala 2290:48]
|
|
|
|
|
node _T_1061 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2291:66]
|
|
|
|
|
io.trigger_pkt_any[2].execute <= _T_1061 @[dec_tlu_ctl.scala 2291:48]
|
|
|
|
|
node _T_1062 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2292:66]
|
|
|
|
|
io.trigger_pkt_any[2].m <= _T_1062 @[dec_tlu_ctl.scala 2292:48]
|
|
|
|
|
node _T_1063 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2287:66]
|
|
|
|
|
io.trigger_pkt_any[3].select <= _T_1063 @[dec_tlu_ctl.scala 2287:48]
|
|
|
|
|
node _T_1064 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2288:69]
|
|
|
|
|
io.trigger_pkt_any[3].match_pkt <= _T_1064 @[dec_tlu_ctl.scala 2288:51]
|
|
|
|
|
node _T_1065 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2289:66]
|
|
|
|
|
io.trigger_pkt_any[3].store <= _T_1065 @[dec_tlu_ctl.scala 2289:48]
|
|
|
|
|
node _T_1066 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2290:66]
|
|
|
|
|
io.trigger_pkt_any[3].load <= _T_1066 @[dec_tlu_ctl.scala 2290:48]
|
|
|
|
|
node _T_1067 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2291:66]
|
|
|
|
|
io.trigger_pkt_any[3].execute <= _T_1067 @[dec_tlu_ctl.scala 2291:48]
|
|
|
|
|
node _T_1068 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2292:66]
|
|
|
|
|
io.trigger_pkt_any[3].m <= _T_1068 @[dec_tlu_ctl.scala 2292:48]
|
|
|
|
|
node _T_1069 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98]
|
|
|
|
|
node _T_1070 = eq(_T_1069, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105]
|
|
|
|
|
node _T_1071 = and(io.dec_csr_wen_r_mod, _T_1070) @[dec_tlu_ctl.scala 2299:76]
|
|
|
|
|
node _T_1072 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2299:127]
|
|
|
|
|
node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2299:118]
|
|
|
|
|
node _T_1074 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2299:160]
|
|
|
|
|
node _T_1075 = not(_T_1074) @[dec_tlu_ctl.scala 2299:144]
|
|
|
|
|
node _T_1076 = or(_T_1075, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176]
|
|
|
|
|
node _T_1077 = and(_T_1073, _T_1076) @[dec_tlu_ctl.scala 2299:141]
|
|
|
|
|
node _T_1078 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98]
|
|
|
|
|
node _T_1079 = eq(_T_1078, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105]
|
|
|
|
|
node _T_1080 = and(io.dec_csr_wen_r_mod, _T_1079) @[dec_tlu_ctl.scala 2299:76]
|
|
|
|
|
node _T_1081 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2299:127]
|
|
|
|
|
node _T_1082 = and(_T_1080, _T_1081) @[dec_tlu_ctl.scala 2299:118]
|
|
|
|
|
node _T_1083 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2299:160]
|
|
|
|
|
node _T_1084 = not(_T_1083) @[dec_tlu_ctl.scala 2299:144]
|
|
|
|
|
node _T_1085 = or(_T_1084, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176]
|
|
|
|
|
node _T_1086 = and(_T_1082, _T_1085) @[dec_tlu_ctl.scala 2299:141]
|
|
|
|
|
node _T_1087 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98]
|
|
|
|
|
node _T_1088 = eq(_T_1087, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105]
|
|
|
|
|
node _T_1089 = and(io.dec_csr_wen_r_mod, _T_1088) @[dec_tlu_ctl.scala 2299:76]
|
|
|
|
|
node _T_1090 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2299:127]
|
|
|
|
|
node _T_1091 = and(_T_1089, _T_1090) @[dec_tlu_ctl.scala 2299:118]
|
|
|
|
|
node _T_1092 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2299:160]
|
|
|
|
|
node _T_1093 = not(_T_1092) @[dec_tlu_ctl.scala 2299:144]
|
|
|
|
|
node _T_1094 = or(_T_1093, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176]
|
|
|
|
|
node _T_1095 = and(_T_1091, _T_1094) @[dec_tlu_ctl.scala 2299:141]
|
|
|
|
|
node _T_1096 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2299:98]
|
|
|
|
|
node _T_1097 = eq(_T_1096, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2299:105]
|
|
|
|
|
node _T_1098 = and(io.dec_csr_wen_r_mod, _T_1097) @[dec_tlu_ctl.scala 2299:76]
|
|
|
|
|
node _T_1099 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2299:127]
|
|
|
|
|
node _T_1100 = and(_T_1098, _T_1099) @[dec_tlu_ctl.scala 2299:118]
|
|
|
|
|
node _T_1101 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2299:160]
|
|
|
|
|
node _T_1102 = not(_T_1101) @[dec_tlu_ctl.scala 2299:144]
|
|
|
|
|
node _T_1103 = or(_T_1102, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2299:176]
|
|
|
|
|
node _T_1104 = and(_T_1100, _T_1103) @[dec_tlu_ctl.scala 2299:141]
|
|
|
|
|
wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2299:49]
|
|
|
|
|
wr_mtdata2_t_r[0] <= _T_1077 @[dec_tlu_ctl.scala 2299:49]
|
|
|
|
|
wr_mtdata2_t_r[1] <= _T_1086 @[dec_tlu_ctl.scala 2299:49]
|
|
|
|
|
wr_mtdata2_t_r[2] <= _T_1095 @[dec_tlu_ctl.scala 2299:49]
|
|
|
|
|
wr_mtdata2_t_r[3] <= _T_1104 @[dec_tlu_ctl.scala 2299:49]
|
|
|
|
|
node _T_1105 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2300:92]
|
|
|
|
|
inst rvclkhdr_31 of rvclkhdr_85 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_31.clock <= clock
|
|
|
|
|
rvclkhdr_31.reset <= reset
|
|
|
|
|
rvclkhdr_31.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_31.io.en <= _T_1105 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_31.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_1106 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1105 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1106 <= io.dec_csr_wrdata_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mtdata2_t[0] <= _T_1106 @[dec_tlu_ctl.scala 2300:44]
|
|
|
|
|
node _T_1107 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2300:92]
|
|
|
|
|
inst rvclkhdr_32 of rvclkhdr_86 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_32.clock <= clock
|
|
|
|
|
rvclkhdr_32.reset <= reset
|
|
|
|
|
rvclkhdr_32.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_32.io.en <= _T_1107 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_32.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_1108 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1107 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1108 <= io.dec_csr_wrdata_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mtdata2_t[1] <= _T_1108 @[dec_tlu_ctl.scala 2300:44]
|
|
|
|
|
node _T_1109 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2300:92]
|
|
|
|
|
inst rvclkhdr_33 of rvclkhdr_87 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_33.clock <= clock
|
|
|
|
|
rvclkhdr_33.reset <= reset
|
|
|
|
|
rvclkhdr_33.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_33.io.en <= _T_1109 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_33.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_1110 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1109 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1110 <= io.dec_csr_wrdata_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mtdata2_t[2] <= _T_1110 @[dec_tlu_ctl.scala 2300:44]
|
|
|
|
|
node _T_1111 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2300:92]
|
|
|
|
|
inst rvclkhdr_34 of rvclkhdr_88 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_34.clock <= clock
|
|
|
|
|
rvclkhdr_34.reset <= reset
|
|
|
|
|
rvclkhdr_34.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_34.io.en <= _T_1111 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_34.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_1112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1111 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1112 <= io.dec_csr_wrdata_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mtdata2_t[3] <= _T_1112 @[dec_tlu_ctl.scala 2300:44]
|
|
|
|
|
node _T_1113 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2304:65]
|
|
|
|
|
node _T_1114 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2304:65]
|
|
|
|
|
node _T_1115 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2304:65]
|
|
|
|
|
node _T_1116 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2304:65]
|
|
|
|
|
node _T_1117 = mux(_T_1113, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1118 = mux(_T_1114, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1119 = mux(_T_1115, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1120 = mux(_T_1116, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1121 = or(_T_1117, _T_1118) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1122 = or(_T_1121, _T_1119) @[Mux.scala 27:72]
|
|
|
|
|
node _T_1123 = or(_T_1122, _T_1120) @[Mux.scala 27:72]
|
|
|
|
|
wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
mtdata2_tsel_out <= _T_1123 @[Mux.scala 27:72]
|
|
|
|
|
io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2305:59]
|
|
|
|
|
io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2305:59]
|
|
|
|
|
io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2305:59]
|
|
|
|
|
io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2305:59]
|
|
|
|
|
mhpme_vec[0] <= perf_csrs.io.mhpme3 @[dec_tlu_ctl.scala 2313:22]
|
|
|
|
|
mhpme_vec[1] <= perf_csrs.io.mhpme4 @[dec_tlu_ctl.scala 2314:22]
|
|
|
|
|
mhpme_vec[2] <= perf_csrs.io.mhpme5 @[dec_tlu_ctl.scala 2315:22]
|
|
|
|
|
mhpme_vec[3] <= perf_csrs.io.mhpme6 @[dec_tlu_ctl.scala 2316:22]
|
|
|
|
|
perfmux_flop.io.mcountinhibit <= mcountinhibit @[dec_tlu_ctl.scala 2321:57]
|
|
|
|
|
perfmux_flop.io.mhpme_vec[0] <= mhpme_vec[0] @[dec_tlu_ctl.scala 2322:57]
|
|
|
|
|
perfmux_flop.io.mhpme_vec[1] <= mhpme_vec[1] @[dec_tlu_ctl.scala 2322:57]
|
|
|
|
|
perfmux_flop.io.mhpme_vec[2] <= mhpme_vec[2] @[dec_tlu_ctl.scala 2322:57]
|
|
|
|
|
perfmux_flop.io.mhpme_vec[3] <= mhpme_vec[3] @[dec_tlu_ctl.scala 2322:57]
|
|
|
|
|
perfmux_flop.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 2323:57]
|
|
|
|
|
perfmux_flop.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 2324:57]
|
|
|
|
|
perfmux_flop.io.tlu_i0_commit_cmt <= io.tlu_i0_commit_cmt @[dec_tlu_ctl.scala 2325:57]
|
|
|
|
|
perfmux_flop.io.illegal_r <= io.illegal_r @[dec_tlu_ctl.scala 2326:57]
|
|
|
|
|
perfmux_flop.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 2327:57]
|
|
|
|
|
perfmux_flop.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 2328:57]
|
|
|
|
|
perfmux_flop.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 2329:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 2330:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 2330:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 2330:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 2330:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 2330:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 2330:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 2330:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_packet_r.icaf_second <= io.dec_tlu_packet_r.icaf_second @[dec_tlu_ctl.scala 2330:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 2330:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 2330:57]
|
|
|
|
|
perfmux_flop.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 2331:57]
|
|
|
|
|
perfmux_flop.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 2332:57]
|
|
|
|
|
perfmux_flop.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 2333:57]
|
|
|
|
|
perfmux_flop.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 2334:57]
|
|
|
|
|
perfmux_flop.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 2335:57]
|
|
|
|
|
perfmux_flop.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 2336:57]
|
|
|
|
|
perfmux_flop.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 2337:57]
|
|
|
|
|
perfmux_flop.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[dec_tlu_ctl.scala 2338:57]
|
|
|
|
|
perfmux_flop.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[dec_tlu_ctl.scala 2339:57]
|
|
|
|
|
perfmux_flop.io.i0_exception_valid_r <= io.i0_exception_valid_r @[dec_tlu_ctl.scala 2340:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_pmu_fw_halted <= io.dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 2341:57]
|
|
|
|
|
perfmux_flop.io.dma_pmu_any_read <= io.dma_pmu_any_read @[dec_tlu_ctl.scala 2342:57]
|
|
|
|
|
perfmux_flop.io.dma_pmu_any_write <= io.dma_pmu_any_write @[dec_tlu_ctl.scala 2343:57]
|
|
|
|
|
perfmux_flop.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[dec_tlu_ctl.scala 2344:57]
|
|
|
|
|
perfmux_flop.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[dec_tlu_ctl.scala 2345:57]
|
|
|
|
|
perfmux_flop.io.lsu_pmu_load_external_r <= io.lsu_pmu_load_external_r @[dec_tlu_ctl.scala 2346:57]
|
|
|
|
|
perfmux_flop.io.lsu_pmu_store_external_r <= io.lsu_pmu_store_external_r @[dec_tlu_ctl.scala 2347:57]
|
|
|
|
|
io.mstatus <= perfmux_flop.io.mstatus @[dec_tlu_ctl.scala 2348:26]
|
|
|
|
|
io.mip <= perfmux_flop.io.mip @[dec_tlu_ctl.scala 2349:18]
|
|
|
|
|
perfmux_flop.io.mie <= mie @[dec_tlu_ctl.scala 2350:57]
|
|
|
|
|
perfmux_flop.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 2351:57]
|
|
|
|
|
perfmux_flop.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 2352:57]
|
|
|
|
|
perfmux_flop.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 2353:57]
|
|
|
|
|
perfmux_flop.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[dec_tlu_ctl.scala 2354:57]
|
|
|
|
|
perfmux_flop.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[dec_tlu_ctl.scala 2355:57]
|
|
|
|
|
perfmux_flop.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 2356:57]
|
|
|
|
|
perfmux_flop.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 2357:57]
|
|
|
|
|
perfmux_flop.io.i0_trigger_hit_r <= io.i0_trigger_hit_r @[dec_tlu_ctl.scala 2358:57]
|
|
|
|
|
perfmux_flop.io.lsu_exc_valid_r <= io.lsu_exc_valid_r @[dec_tlu_ctl.scala 2359:57]
|
|
|
|
|
perfmux_flop.io.take_timer_int <= io.take_timer_int @[dec_tlu_ctl.scala 2360:57]
|
|
|
|
|
perfmux_flop.io.take_int_timer0_int <= io.take_int_timer0_int @[dec_tlu_ctl.scala 2361:57]
|
|
|
|
|
perfmux_flop.io.take_int_timer1_int <= io.take_int_timer1_int @[dec_tlu_ctl.scala 2362:57]
|
|
|
|
|
perfmux_flop.io.take_ext_int <= io.take_ext_int @[dec_tlu_ctl.scala 2363:57]
|
|
|
|
|
perfmux_flop.io.tlu_flush_lower_r <= io.tlu_flush_lower_r @[dec_tlu_ctl.scala 2364:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_br0_error_r <= io.dec_tlu_br0_error_r @[dec_tlu_ctl.scala 2365:57]
|
|
|
|
|
perfmux_flop.io.rfpc_i0_r <= io.rfpc_i0_r @[dec_tlu_ctl.scala 2366:57]
|
|
|
|
|
perfmux_flop.io.dec_tlu_br0_start_error_r <= io.dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 2367:57]
|
|
|
|
|
io.mdseac_locked_f <= perfmux_flop.io.mdseac_locked_f @[dec_tlu_ctl.scala 2378:42]
|
|
|
|
|
io.lsu_exc_valid_r_d1 <= perfmux_flop.io.lsu_exc_valid_r_d1 @[dec_tlu_ctl.scala 2380:42]
|
|
|
|
|
io.take_ext_int_start_d1 <= perfmux_flop.io.take_ext_int_start_d1 @[dec_tlu_ctl.scala 2382:42]
|
|
|
|
|
io.take_ext_int_start_d2 <= perfmux_flop.io.take_ext_int_start_d2 @[dec_tlu_ctl.scala 2383:42]
|
|
|
|
|
io.take_ext_int_start_d3 <= perfmux_flop.io.take_ext_int_start_d3 @[dec_tlu_ctl.scala 2384:42]
|
|
|
|
|
io.ext_int_freeze_d1 <= perfmux_flop.io.ext_int_freeze_d1 @[dec_tlu_ctl.scala 2385:42]
|
|
|
|
|
perfmux_flop.io.mdseac_locked_ns <= io.mdseac_locked_ns @[dec_tlu_ctl.scala 2389:55]
|
|
|
|
|
perfmux_flop.io.lsu_single_ecc_error_r <= io.lsu_single_ecc_error_r @[dec_tlu_ctl.scala 2390:55]
|
|
|
|
|
perfmux_flop.io.lsu_i0_exc_r <= io.lsu_i0_exc_r @[dec_tlu_ctl.scala 2391:55]
|
|
|
|
|
perfmux_flop.io.take_ext_int_start <= io.take_ext_int_start @[dec_tlu_ctl.scala 2392:55]
|
|
|
|
|
perfmux_flop.io.ext_int_freeze <= io.ext_int_freeze @[dec_tlu_ctl.scala 2393:55]
|
|
|
|
|
perfmux_flop.io.mip_ns <= mip_ns @[dec_tlu_ctl.scala 2394:55]
|
|
|
|
|
perfmux_flop.io.mcyclel_cout <= mcyclel_cout @[dec_tlu_ctl.scala 2395:55]
|
|
|
|
|
perfmux_flop.io.wr_mcycleh_r <= wr_mcycleh_r @[dec_tlu_ctl.scala 2396:55]
|
|
|
|
|
perfmux_flop.io.mcyclel_cout_in <= mcyclel_cout_in @[dec_tlu_ctl.scala 2397:55]
|
|
|
|
|
perfmux_flop.io.minstret_enable <= minstret_enable @[dec_tlu_ctl.scala 2398:55]
|
|
|
|
|
perfmux_flop.io.minstretl_cout_ns <= minstretl_cout_ns @[dec_tlu_ctl.scala 2399:55]
|
|
|
|
|
perfmux_flop.io.fw_halted_ns <= fw_halted_ns @[dec_tlu_ctl.scala 2400:55]
|
|
|
|
|
perfmux_flop.io.meicidpl_ns <= meicidpl_ns @[dec_tlu_ctl.scala 2401:55]
|
|
|
|
|
perfmux_flop.io.icache_rd_valid <= icache_rd_valid @[dec_tlu_ctl.scala 2402:55]
|
|
|
|
|
perfmux_flop.io.icache_wr_valid <= icache_wr_valid @[dec_tlu_ctl.scala 2403:55]
|
|
|
|
|
node _T_1124 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2404:91]
|
|
|
|
|
node _T_1125 = and(io.dec_tlu_dbg_halted, _T_1124) @[dec_tlu_ctl.scala 2404:82]
|
|
|
|
|
node _T_1126 = or(_T_1125, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2404:105]
|
|
|
|
|
perfmux_flop.io.perfcnt_halted <= _T_1126 @[dec_tlu_ctl.scala 2404:55]
|
|
|
|
|
perfmux_flop.io.mstatus_ns <= mstatus_ns @[dec_tlu_ctl.scala 2405:55]
|
|
|
|
|
perfmux_flop.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 2406:55]
|
|
|
|
|
perfmux_flop.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 2407:56]
|
|
|
|
|
perf_csrs.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 2411:50]
|
|
|
|
|
perf_csrs.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 2412:50]
|
|
|
|
|
perf_csrs.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 2413:50]
|
|
|
|
|
perf_csrs.io.dcsr <= io.dcsr @[dec_tlu_ctl.scala 2414:50]
|
|
|
|
|
perf_csrs.io.dec_tlu_pmu_fw_halted <= io.dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 2415:50]
|
|
|
|
|
perf_csrs.io.mhpme_vec[0] <= mhpme_vec[0] @[dec_tlu_ctl.scala 2416:50]
|
|
|
|
|
perf_csrs.io.mhpme_vec[1] <= mhpme_vec[1] @[dec_tlu_ctl.scala 2416:50]
|
|
|
|
|
perf_csrs.io.mhpme_vec[2] <= mhpme_vec[2] @[dec_tlu_ctl.scala 2416:50]
|
|
|
|
|
perf_csrs.io.mhpme_vec[3] <= mhpme_vec[3] @[dec_tlu_ctl.scala 2416:50]
|
|
|
|
|
perf_csrs.io.dec_csr_wen_r_mod <= io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 2417:50]
|
|
|
|
|
perf_csrs.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 2418:50]
|
|
|
|
|
perf_csrs.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 2419:50]
|
|
|
|
|
perf_csrs.io.mhpmc_inc_r[0] <= perfmux_flop.io.mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2420:50]
|
|
|
|
|
perf_csrs.io.mhpmc_inc_r[1] <= perfmux_flop.io.mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2420:50]
|
|
|
|
|
perf_csrs.io.mhpmc_inc_r[2] <= perfmux_flop.io.mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2420:50]
|
|
|
|
|
perf_csrs.io.mhpmc_inc_r[3] <= perfmux_flop.io.mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2420:50]
|
|
|
|
|
perf_csrs.io.mhpmc_inc_r_d1[0] <= perfmux_flop.io.mhpmc_inc_r_d1[0] @[dec_tlu_ctl.scala 2421:50]
|
|
|
|
|
perf_csrs.io.mhpmc_inc_r_d1[1] <= perfmux_flop.io.mhpmc_inc_r_d1[1] @[dec_tlu_ctl.scala 2421:50]
|
|
|
|
|
perf_csrs.io.mhpmc_inc_r_d1[2] <= perfmux_flop.io.mhpmc_inc_r_d1[2] @[dec_tlu_ctl.scala 2421:50]
|
|
|
|
|
perf_csrs.io.mhpmc_inc_r_d1[3] <= perfmux_flop.io.mhpmc_inc_r_d1[3] @[dec_tlu_ctl.scala 2421:50]
|
|
|
|
|
perf_csrs.io.perfcnt_halted_d1 <= perfmux_flop.io.perfcnt_halted_d1 @[dec_tlu_ctl.scala 2422:50]
|
|
|
|
|
io.dec_tlu_perfcnt0 <= perf_csrs.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 2436:29]
|
|
|
|
|
io.dec_tlu_perfcnt1 <= perf_csrs.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 2437:29]
|
|
|
|
|
io.dec_tlu_perfcnt2 <= perf_csrs.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 2438:29]
|
|
|
|
|
io.dec_tlu_perfcnt3 <= perf_csrs.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 2439:29]
|
|
|
|
|
node _T_1127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2455:77]
|
|
|
|
|
node _T_1128 = eq(_T_1127, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2455:84]
|
|
|
|
|
node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_1128) @[dec_tlu_ctl.scala 2455:55]
|
|
|
|
|
node _T_1129 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2457:61]
|
|
|
|
|
wire temp_ncount0 : UInt<1>
|
|
|
|
|
temp_ncount0 <= _T_1129
|
|
|
|
|
node _T_1130 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2458:61]
|
|
|
|
|
wire temp_ncount1 : UInt<1>
|
|
|
|
|
temp_ncount1 <= _T_1130
|
|
|
|
|
node _T_1131 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2459:62]
|
|
|
|
|
wire temp_ncount6_2 : UInt<5>
|
|
|
|
|
temp_ncount6_2 <= _T_1131
|
|
|
|
|
node _T_1132 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2460:81]
|
|
|
|
|
node _T_1133 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2460:110]
|
|
|
|
|
reg _T_1134 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1133 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1134 <= _T_1132 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
temp_ncount6_2 <= _T_1134 @[dec_tlu_ctl.scala 2460:24]
|
|
|
|
|
node _T_1135 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2462:79]
|
|
|
|
|
node _T_1136 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2462:106]
|
|
|
|
|
reg _T_1137 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_1136 : @[Reg.scala 28:19]
|
|
|
|
|
_T_1137 <= _T_1135 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
temp_ncount0 <= _T_1137 @[dec_tlu_ctl.scala 2462:22]
|
|
|
|
|
node _T_1138 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1139 = cat(_T_1138, temp_ncount0) @[Cat.scala 29:58]
|
|
|
|
|
mcountinhibit <= _T_1139 @[dec_tlu_ctl.scala 2463:23]
|
|
|
|
|
node _T_1140 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2468:42]
|
|
|
|
|
node _T_1141 = and(_T_1140, io.i0_valid_wb) @[dec_tlu_ctl.scala 2468:68]
|
|
|
|
|
io.dec_tlu_i0_valid_wb1 <= _T_1141 @[dec_tlu_ctl.scala 2468:39]
|
|
|
|
|
node _T_1142 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2469:42]
|
|
|
|
|
node _T_1143 = or(io.i0_exception_valid_r_d1, perfmux_flop.io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2469:98]
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node _T_1144 = eq(io.trigger_hit_dmode_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 2469:158]
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node _T_1145 = and(io.trigger_hit_r_d1, _T_1144) @[dec_tlu_ctl.scala 2469:156]
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node _T_1146 = or(_T_1143, _T_1145) @[dec_tlu_ctl.scala 2469:133]
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node _T_1147 = and(_T_1142, _T_1146) @[dec_tlu_ctl.scala 2469:68]
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io.dec_tlu_i0_exc_valid_wb1 <= _T_1147 @[dec_tlu_ctl.scala 2469:39]
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node _T_1148 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2470:49]
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node _T_1149 = bits(_T_1148, 0, 0) @[Bitwise.scala 72:15]
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node _T_1150 = mux(_T_1149, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
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node dec_tlu_exc_cause_wb1_raw = and(_T_1150, io.exc_cause_wb) @[dec_tlu_ctl.scala 2470:77]
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node _T_1151 = eq(io.dec_tlu_trace_disable, UInt<1>("h00")) @[dec_tlu_ctl.scala 2471:42]
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node dec_tlu_int_valid_wb1_raw = and(_T_1151, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2471:68]
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wire dec_tlu_exc_cause_wb2 : UInt
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dec_tlu_exc_cause_wb2 <= UInt<1>("h00")
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node _T_1152 = xor(dec_tlu_exc_cause_wb1_raw, dec_tlu_exc_cause_wb2) @[lib.scala 448:21]
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node _T_1153 = orr(_T_1152) @[lib.scala 448:29]
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reg _T_1154 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_1153 : @[Reg.scala 28:19]
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_T_1154 <= dec_tlu_exc_cause_wb1_raw @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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dec_tlu_exc_cause_wb2 <= _T_1154 @[lib.scala 451:16]
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wire dec_tlu_int_valid_wb2 : UInt<1>
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dec_tlu_int_valid_wb2 <= UInt<1>("h00")
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node _T_1155 = xor(dec_tlu_int_valid_wb1_raw, dec_tlu_int_valid_wb2) @[lib.scala 470:21]
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node _T_1156 = orr(_T_1155) @[lib.scala 470:29]
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reg _T_1157 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_1156 : @[Reg.scala 28:19]
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_T_1157 <= dec_tlu_int_valid_wb1_raw @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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dec_tlu_int_valid_wb2 <= _T_1157 @[lib.scala 473:16]
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node _T_1158 = mux(dec_tlu_int_valid_wb2, dec_tlu_exc_cause_wb2, dec_tlu_exc_cause_wb1_raw) @[dec_tlu_ctl.scala 2477:40]
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io.dec_tlu_exc_cause_wb1 <= _T_1158 @[dec_tlu_ctl.scala 2477:34]
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io.dec_tlu_int_valid_wb1 <= dec_tlu_int_valid_wb2 @[dec_tlu_ctl.scala 2478:34]
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io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2479:31]
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node _T_1159 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2486:37]
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node _T_1160 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2487:42]
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node _T_1161 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2488:40]
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node _T_1162 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2489:39]
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node _T_1163 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2490:40]
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node _T_1164 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58]
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node _T_1165 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2491:40]
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node _T_1166 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2491:103]
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node _T_1167 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2491:128]
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node _T_1168 = cat(UInt<3>("h00"), _T_1167) @[Cat.scala 29:58]
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node _T_1169 = cat(_T_1168, UInt<3>("h00")) @[Cat.scala 29:58]
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node _T_1170 = cat(UInt<3>("h00"), _T_1166) @[Cat.scala 29:58]
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node _T_1171 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58]
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node _T_1172 = cat(_T_1171, _T_1170) @[Cat.scala 29:58]
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node _T_1173 = cat(_T_1172, _T_1169) @[Cat.scala 29:58]
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node _T_1174 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2492:38]
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node _T_1175 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2492:70]
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node _T_1176 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2492:96]
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node _T_1177 = cat(_T_1175, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_1178 = cat(_T_1177, _T_1176) @[Cat.scala 29:58]
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node _T_1179 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2493:36]
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node _T_1180 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2493:78]
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node _T_1181 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2493:102]
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node _T_1182 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2493:123]
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node _T_1183 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2493:144]
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node _T_1184 = cat(_T_1183, UInt<3>("h00")) @[Cat.scala 29:58]
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node _T_1185 = cat(_T_1182, UInt<3>("h00")) @[Cat.scala 29:58]
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node _T_1186 = cat(_T_1185, _T_1184) @[Cat.scala 29:58]
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node _T_1187 = cat(_T_1181, UInt<3>("h00")) @[Cat.scala 29:58]
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node _T_1188 = cat(UInt<1>("h00"), _T_1180) @[Cat.scala 29:58]
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node _T_1189 = cat(_T_1188, UInt<16>("h00")) @[Cat.scala 29:58]
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node _T_1190 = cat(_T_1189, _T_1187) @[Cat.scala 29:58]
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node _T_1191 = cat(_T_1190, _T_1186) @[Cat.scala 29:58]
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node _T_1192 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2494:36]
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node _T_1193 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2494:75]
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node _T_1194 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2494:96]
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node _T_1195 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2494:114]
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node _T_1196 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2494:132]
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node _T_1197 = cat(_T_1196, UInt<3>("h00")) @[Cat.scala 29:58]
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node _T_1198 = cat(_T_1195, UInt<3>("h00")) @[Cat.scala 29:58]
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node _T_1199 = cat(_T_1198, _T_1197) @[Cat.scala 29:58]
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node _T_1200 = cat(_T_1194, UInt<3>("h00")) @[Cat.scala 29:58]
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node _T_1201 = cat(UInt<1>("h00"), _T_1193) @[Cat.scala 29:58]
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node _T_1202 = cat(_T_1201, UInt<16>("h00")) @[Cat.scala 29:58]
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node _T_1203 = cat(_T_1202, _T_1200) @[Cat.scala 29:58]
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node _T_1204 = cat(_T_1203, _T_1199) @[Cat.scala 29:58]
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|
node _T_1205 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2495:40]
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|
node _T_1206 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2495:65]
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|
node _T_1207 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2496:40]
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|
node _T_1208 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2496:69]
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node _T_1209 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2497:42]
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node _T_1210 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2497:72]
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node _T_1211 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2498:42]
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node _T_1212 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2498:72]
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node _T_1213 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2499:41]
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node _T_1214 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2499:66]
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|
node _T_1215 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2500:37]
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node _T_1216 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58]
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|
node _T_1217 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2501:39]
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|
node _T_1218 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2501:64]
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|
|
node _T_1219 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2502:40]
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|
node _T_1220 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2502:80]
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|
node _T_1221 = cat(UInt<28>("h00"), _T_1220) @[Cat.scala 29:58]
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node _T_1222 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2503:38]
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node _T_1223 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2503:63]
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node _T_1224 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2504:37]
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node _T_1225 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2504:62]
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|
node _T_1226 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2505:39]
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|
node _T_1227 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2505:64]
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|
node _T_1228 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2506:38]
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|
node _T_1229 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58]
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|
node _T_1230 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2507:39]
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|
node _T_1231 = cat(meivt, meihap) @[Cat.scala 29:58]
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|
node _T_1232 = cat(_T_1231, UInt<2>("h00")) @[Cat.scala 29:58]
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|
node _T_1233 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2508:41]
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node _T_1234 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2508:81]
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|
node _T_1235 = cat(UInt<28>("h00"), _T_1234) @[Cat.scala 29:58]
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|
node _T_1236 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2509:41]
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|
node _T_1237 = bits(perfmux_flop.io.meicidpl, 3, 0) @[dec_tlu_ctl.scala 2509:97]
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|
|
node _T_1238 = cat(UInt<28>("h00"), _T_1237) @[Cat.scala 29:58]
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|
|
|
node _T_1239 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2510:38]
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|
node _T_1240 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2510:78]
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|
|
node _T_1241 = cat(UInt<28>("h00"), _T_1240) @[Cat.scala 29:58]
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|
|
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|
node _T_1242 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2511:37]
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|
node _T_1243 = bits(mcgc, 9, 0) @[dec_tlu_ctl.scala 2511:77]
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|
|
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|
node _T_1244 = cat(UInt<22>("h00"), _T_1243) @[Cat.scala 29:58]
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|
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|
node _T_1245 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2512:37]
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|
node _T_1246 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2512:77]
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|
|
node _T_1247 = cat(UInt<13>("h00"), _T_1246) @[Cat.scala 29:58]
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|
|
node _T_1248 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2513:37]
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|
|
node _T_1249 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2513:85]
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|
|
node _T_1250 = cat(UInt<16>("h04000"), _T_1249) @[Cat.scala 29:58]
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|
|
|
|
node _T_1251 = cat(_T_1250, UInt<2>("h03")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1252 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2514:36]
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|
|
|
|
node _T_1253 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1254 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2515:39]
|
|
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|
node _T_1255 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2515:64]
|
|
|
|
|
node _T_1256 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2516:40]
|
|
|
|
|
node _T_1257 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2516:65]
|
|
|
|
|
node _T_1258 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2517:39]
|
|
|
|
|
node _T_1259 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2517:64]
|
|
|
|
|
node _T_1260 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2518:41]
|
|
|
|
|
node _T_1261 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2518:80]
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|
|
|
node _T_1262 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2518:104]
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|
|
|
node _T_1263 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2518:131]
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|
|
|
|
node _T_1264 = cat(UInt<3>("h00"), _T_1263) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1265 = cat(_T_1264, UInt<3>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1266 = cat(UInt<2>("h00"), _T_1262) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1267 = cat(UInt<7>("h00"), _T_1261) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1268 = cat(_T_1267, _T_1266) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1269 = cat(_T_1268, _T_1265) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1270 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2519:38]
|
|
|
|
|
node _T_1271 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2519:78]
|
|
|
|
|
node _T_1272 = cat(UInt<30>("h00"), _T_1271) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1273 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2520:40]
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|
|
|
|
node _T_1274 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2520:74]
|
|
|
|
|
node _T_1275 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2521:40]
|
|
|
|
|
node _T_1276 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2521:74]
|
|
|
|
|
node _T_1277 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2522:39]
|
|
|
|
|
node _T_1278 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2522:64]
|
|
|
|
|
node _T_1279 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2523:41]
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|
|
|
|
node _T_1280 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2523:66]
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|
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|
|
node _T_1281 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2524:41]
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|
|
|
|
node _T_1282 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2524:66]
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node _T_1283 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2525:39]
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node _T_1284 = bits(perf_csrs.io.mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2525:77]
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node _T_1285 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2526:39]
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node _T_1286 = bits(perf_csrs.io.mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2526:77]
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node _T_1287 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2527:39]
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node _T_1288 = bits(perf_csrs.io.mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2527:77]
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node _T_1289 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2528:39]
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node _T_1290 = bits(perf_csrs.io.mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2528:77]
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node _T_1291 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2529:40]
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node _T_1292 = bits(perf_csrs.io.mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2529:78]
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node _T_1293 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2530:40]
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node _T_1294 = bits(perf_csrs.io.mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2530:78]
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node _T_1295 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2531:40]
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node _T_1296 = bits(perf_csrs.io.mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2531:78]
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node _T_1297 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2532:40]
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node _T_1298 = bits(perf_csrs.io.mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2532:78]
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node _T_1299 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2533:38]
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node _T_1300 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2533:78]
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node _T_1301 = cat(UInt<26>("h00"), _T_1300) @[Cat.scala 29:58]
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node _T_1302 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2534:38]
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node _T_1303 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2534:78]
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node _T_1304 = cat(UInt<30>("h00"), _T_1303) @[Cat.scala 29:58]
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node _T_1305 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2535:39]
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node _T_1306 = bits(perf_csrs.io.mhpme3, 9, 0) @[dec_tlu_ctl.scala 2535:92]
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node _T_1307 = cat(UInt<22>("h00"), _T_1306) @[Cat.scala 29:58]
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node _T_1308 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2536:39]
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node _T_1309 = bits(perf_csrs.io.mhpme4, 9, 0) @[dec_tlu_ctl.scala 2536:92]
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node _T_1310 = cat(UInt<22>("h00"), _T_1309) @[Cat.scala 29:58]
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node _T_1311 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2537:39]
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node _T_1312 = bits(perf_csrs.io.mhpme5, 9, 0) @[dec_tlu_ctl.scala 2537:91]
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node _T_1313 = cat(UInt<22>("h00"), _T_1312) @[Cat.scala 29:58]
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node _T_1314 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2538:39]
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node _T_1315 = bits(perf_csrs.io.mhpme6, 9, 0) @[dec_tlu_ctl.scala 2538:91]
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node _T_1316 = cat(UInt<22>("h00"), _T_1315) @[Cat.scala 29:58]
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node _T_1317 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2539:46]
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node _T_1318 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2539:86]
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node _T_1319 = cat(UInt<25>("h00"), _T_1318) @[Cat.scala 29:58]
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node _T_1320 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2540:37]
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node _T_1321 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58]
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node _T_1322 = cat(_T_1321, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_1323 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2541:37]
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node _T_1324 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2541:76]
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node _T_1325 = mux(_T_1159, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1326 = mux(_T_1160, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1327 = mux(_T_1161, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1328 = mux(_T_1162, UInt<32>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1329 = mux(_T_1163, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1330 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1331 = mux(_T_1174, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1332 = mux(_T_1179, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1333 = mux(_T_1192, _T_1204, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1334 = mux(_T_1205, _T_1206, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1335 = mux(_T_1207, _T_1208, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1336 = mux(_T_1209, _T_1210, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1337 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1338 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1339 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1340 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1341 = mux(_T_1219, _T_1221, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1342 = mux(_T_1222, _T_1223, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1343 = mux(_T_1224, _T_1225, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1344 = mux(_T_1226, _T_1227, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1345 = mux(_T_1228, _T_1229, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1346 = mux(_T_1230, _T_1232, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1347 = mux(_T_1233, _T_1235, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1348 = mux(_T_1236, _T_1238, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1349 = mux(_T_1239, _T_1241, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1350 = mux(_T_1242, _T_1244, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1351 = mux(_T_1245, _T_1247, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1352 = mux(_T_1248, _T_1251, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1353 = mux(_T_1252, _T_1253, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1354 = mux(_T_1254, _T_1255, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1355 = mux(_T_1256, _T_1257, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1356 = mux(_T_1258, _T_1259, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1357 = mux(_T_1260, _T_1269, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1358 = mux(_T_1270, _T_1272, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1359 = mux(_T_1273, _T_1274, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1360 = mux(_T_1275, _T_1276, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1361 = mux(_T_1277, _T_1278, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1362 = mux(_T_1279, _T_1280, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1363 = mux(_T_1281, _T_1282, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1364 = mux(_T_1283, _T_1284, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1365 = mux(_T_1285, _T_1286, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1366 = mux(_T_1287, _T_1288, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1367 = mux(_T_1289, _T_1290, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1368 = mux(_T_1291, _T_1292, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1369 = mux(_T_1293, _T_1294, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1370 = mux(_T_1295, _T_1296, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1371 = mux(_T_1297, _T_1298, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1372 = mux(_T_1299, _T_1301, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1373 = mux(_T_1302, _T_1304, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1374 = mux(_T_1305, _T_1307, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1375 = mux(_T_1308, _T_1310, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1376 = mux(_T_1311, _T_1313, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1377 = mux(_T_1314, _T_1316, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1378 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1379 = mux(_T_1320, _T_1322, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1380 = mux(_T_1323, _T_1324, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_1381 = or(_T_1325, _T_1326) @[Mux.scala 27:72]
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node _T_1382 = or(_T_1381, _T_1327) @[Mux.scala 27:72]
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node _T_1383 = or(_T_1382, _T_1328) @[Mux.scala 27:72]
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node _T_1384 = or(_T_1383, _T_1329) @[Mux.scala 27:72]
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node _T_1385 = or(_T_1384, _T_1330) @[Mux.scala 27:72]
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node _T_1386 = or(_T_1385, _T_1331) @[Mux.scala 27:72]
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node _T_1387 = or(_T_1386, _T_1332) @[Mux.scala 27:72]
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node _T_1388 = or(_T_1387, _T_1333) @[Mux.scala 27:72]
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node _T_1389 = or(_T_1388, _T_1334) @[Mux.scala 27:72]
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node _T_1390 = or(_T_1389, _T_1335) @[Mux.scala 27:72]
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node _T_1391 = or(_T_1390, _T_1336) @[Mux.scala 27:72]
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node _T_1392 = or(_T_1391, _T_1337) @[Mux.scala 27:72]
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node _T_1393 = or(_T_1392, _T_1338) @[Mux.scala 27:72]
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node _T_1394 = or(_T_1393, _T_1339) @[Mux.scala 27:72]
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node _T_1395 = or(_T_1394, _T_1340) @[Mux.scala 27:72]
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node _T_1396 = or(_T_1395, _T_1341) @[Mux.scala 27:72]
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node _T_1397 = or(_T_1396, _T_1342) @[Mux.scala 27:72]
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node _T_1398 = or(_T_1397, _T_1343) @[Mux.scala 27:72]
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node _T_1399 = or(_T_1398, _T_1344) @[Mux.scala 27:72]
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node _T_1400 = or(_T_1399, _T_1345) @[Mux.scala 27:72]
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node _T_1401 = or(_T_1400, _T_1346) @[Mux.scala 27:72]
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node _T_1402 = or(_T_1401, _T_1347) @[Mux.scala 27:72]
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node _T_1403 = or(_T_1402, _T_1348) @[Mux.scala 27:72]
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node _T_1404 = or(_T_1403, _T_1349) @[Mux.scala 27:72]
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node _T_1405 = or(_T_1404, _T_1350) @[Mux.scala 27:72]
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node _T_1406 = or(_T_1405, _T_1351) @[Mux.scala 27:72]
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node _T_1407 = or(_T_1406, _T_1352) @[Mux.scala 27:72]
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node _T_1408 = or(_T_1407, _T_1353) @[Mux.scala 27:72]
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node _T_1409 = or(_T_1408, _T_1354) @[Mux.scala 27:72]
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node _T_1410 = or(_T_1409, _T_1355) @[Mux.scala 27:72]
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node _T_1411 = or(_T_1410, _T_1356) @[Mux.scala 27:72]
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node _T_1412 = or(_T_1411, _T_1357) @[Mux.scala 27:72]
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node _T_1413 = or(_T_1412, _T_1358) @[Mux.scala 27:72]
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node _T_1414 = or(_T_1413, _T_1359) @[Mux.scala 27:72]
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node _T_1415 = or(_T_1414, _T_1360) @[Mux.scala 27:72]
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node _T_1416 = or(_T_1415, _T_1361) @[Mux.scala 27:72]
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node _T_1417 = or(_T_1416, _T_1362) @[Mux.scala 27:72]
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node _T_1418 = or(_T_1417, _T_1363) @[Mux.scala 27:72]
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node _T_1419 = or(_T_1418, _T_1364) @[Mux.scala 27:72]
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node _T_1420 = or(_T_1419, _T_1365) @[Mux.scala 27:72]
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node _T_1421 = or(_T_1420, _T_1366) @[Mux.scala 27:72]
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node _T_1422 = or(_T_1421, _T_1367) @[Mux.scala 27:72]
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node _T_1423 = or(_T_1422, _T_1368) @[Mux.scala 27:72]
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node _T_1424 = or(_T_1423, _T_1369) @[Mux.scala 27:72]
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node _T_1425 = or(_T_1424, _T_1370) @[Mux.scala 27:72]
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node _T_1426 = or(_T_1425, _T_1371) @[Mux.scala 27:72]
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node _T_1427 = or(_T_1426, _T_1372) @[Mux.scala 27:72]
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node _T_1428 = or(_T_1427, _T_1373) @[Mux.scala 27:72]
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node _T_1429 = or(_T_1428, _T_1374) @[Mux.scala 27:72]
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node _T_1430 = or(_T_1429, _T_1375) @[Mux.scala 27:72]
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node _T_1431 = or(_T_1430, _T_1376) @[Mux.scala 27:72]
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node _T_1432 = or(_T_1431, _T_1377) @[Mux.scala 27:72]
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node _T_1433 = or(_T_1432, _T_1378) @[Mux.scala 27:72]
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node _T_1434 = or(_T_1433, _T_1379) @[Mux.scala 27:72]
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node _T_1435 = or(_T_1434, _T_1380) @[Mux.scala 27:72]
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wire _T_1436 : UInt @[Mux.scala 27:72]
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|
|
_T_1436 <= _T_1435 @[Mux.scala 27:72]
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|
io.dec_csr_rddata_d <= _T_1436 @[dec_tlu_ctl.scala 2485:28]
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extmodule gated_latch_89 :
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output Q : Clock
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|
input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_89 :
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input clock : Clock
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|
input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_89 @[lib.scala 334:26]
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clkhdr.SE is invalid
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|
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clkhdr.EN is invalid
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|
|
clkhdr.CK is invalid
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|
|
clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_90 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_90 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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|
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inst clkhdr of gated_latch_90 @[lib.scala 334:26]
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|
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clkhdr.SE is invalid
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|
|
clkhdr.EN is invalid
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|
|
clkhdr.CK is invalid
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|
|
clkhdr.Q is invalid
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|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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clkhdr.EN <= io.en @[lib.scala 337:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_91 :
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|
|
output Q : Clock
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|
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input CK : Clock
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|
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input EN : UInt<1>
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|
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input SE : UInt<1>
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|
|
defname = gated_latch
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module rvclkhdr_91 :
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|
|
input clock : Clock
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|
|
input reset : Reset
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|
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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|
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|
|
inst clkhdr of gated_latch_91 @[lib.scala 334:26]
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|
|
clkhdr.SE is invalid
|
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|
|
clkhdr.EN is invalid
|
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|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
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|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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|
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clkhdr.CK <= io.clk @[lib.scala 336:18]
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|
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clkhdr.EN <= io.en @[lib.scala 337:18]
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|
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clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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extmodule gated_latch_92 :
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|
|
output Q : Clock
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|
|
input CK : Clock
|
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|
|
input EN : UInt<1>
|
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|
|
input SE : UInt<1>
|
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|
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|
|
defname = gated_latch
|
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|
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module rvclkhdr_92 :
|
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|
|
input clock : Clock
|
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|
|
input reset : Reset
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|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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|
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|
|
inst clkhdr of gated_latch_92 @[lib.scala 334:26]
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|
|
clkhdr.SE is invalid
|
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|
|
clkhdr.EN is invalid
|
|
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|
|
clkhdr.CK is invalid
|
|
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|
|
clkhdr.Q is invalid
|
|
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|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
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|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
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|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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|
|
extmodule gated_latch_93 :
|
|
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|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
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|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
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|
|
|
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|
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|
|
module rvclkhdr_93 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_93 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
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|
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|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
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|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
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|
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|
|
|
|
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|
|
extmodule gated_latch_94 :
|
|
|
|
|
output Q : Clock
|
|
|
|
|
input CK : Clock
|
|
|
|
|
input EN : UInt<1>
|
|
|
|
|
input SE : UInt<1>
|
|
|
|
|
|
|
|
|
|
defname = gated_latch
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module rvclkhdr_94 :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : Reset
|
|
|
|
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
|
|
|
|
|
|
|
|
|
inst clkhdr of gated_latch_94 @[lib.scala 334:26]
|
|
|
|
|
clkhdr.SE is invalid
|
|
|
|
|
clkhdr.EN is invalid
|
|
|
|
|
clkhdr.CK is invalid
|
|
|
|
|
clkhdr.Q is invalid
|
|
|
|
|
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
|
|
|
|
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
|
|
|
|
clkhdr.EN <= io.en @[lib.scala 337:18]
|
|
|
|
|
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
|
|
|
|
|
|
|
|
|
module dec_timer_ctl :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : AsyncReset
|
|
|
|
|
output io : {flip free_l2clk : Clock, flip csr_wr_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>}
|
|
|
|
|
|
|
|
|
|
wire mitctl1 : UInt<4>
|
|
|
|
|
mitctl1 <= UInt<1>("h00")
|
|
|
|
|
wire mitctl0 : UInt<3>
|
|
|
|
|
mitctl0 <= UInt<1>("h00")
|
|
|
|
|
wire mitb1 : UInt<32>
|
|
|
|
|
mitb1 <= UInt<1>("h00")
|
|
|
|
|
wire mitb0 : UInt<32>
|
|
|
|
|
mitb0 <= UInt<1>("h00")
|
|
|
|
|
wire mitcnt1 : UInt<32>
|
|
|
|
|
mitcnt1 <= UInt<1>("h00")
|
|
|
|
|
wire mitcnt0 : UInt<32>
|
|
|
|
|
mitcnt0 <= UInt<1>("h00")
|
|
|
|
|
node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 3277:36]
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|
|
|
|
node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 3278:36]
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|
|
|
|
io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 3280:31]
|
|
|
|
|
io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 3281:31]
|
|
|
|
|
node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 3288:72]
|
|
|
|
|
node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 3288:49]
|
|
|
|
|
node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 3290:37]
|
|
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|
|
node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 3290:56]
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|
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|
|
node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 3290:85]
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|
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|
|
node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 3290:76]
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|
|
node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 3290:53]
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|
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|
|
node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 3290:112]
|
|
|
|
|
node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 3290:147]
|
|
|
|
|
node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 3290:138]
|
|
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|
|
node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 3290:109]
|
|
|
|
|
node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 3290:173]
|
|
|
|
|
node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 3290:171]
|
|
|
|
|
wire mitcnt0_inc1 : UInt<9>
|
|
|
|
|
mitcnt0_inc1 <= UInt<1>("h00")
|
|
|
|
|
wire mitcnt0_inc2 : UInt<24>
|
|
|
|
|
mitcnt0_inc2 <= UInt<1>("h00")
|
|
|
|
|
node _T_11 = bits(mitcnt0, 7, 0) @[dec_tlu_ctl.scala 3293:32]
|
|
|
|
|
node _T_12 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58]
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|
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|
|
node _T_13 = add(_T_11, _T_12) @[dec_tlu_ctl.scala 3293:38]
|
|
|
|
|
node _T_14 = tail(_T_13, 1) @[dec_tlu_ctl.scala 3293:38]
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|
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|
|
mitcnt0_inc1 <= _T_14 @[dec_tlu_ctl.scala 3293:22]
|
|
|
|
|
node mitcnt0_inc_cout = bits(mitcnt0_inc1, 8, 8) @[dec_tlu_ctl.scala 3294:44]
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|
|
|
|
node _T_15 = bits(mitcnt0, 31, 8) @[dec_tlu_ctl.scala 3295:32]
|
|
|
|
|
node _T_16 = cat(UInt<23>("h00"), mitcnt0_inc_cout) @[Cat.scala 29:58]
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|
|
|
|
node _T_17 = add(_T_15, _T_16) @[dec_tlu_ctl.scala 3295:39]
|
|
|
|
|
node _T_18 = tail(_T_17, 1) @[dec_tlu_ctl.scala 3295:39]
|
|
|
|
|
mitcnt0_inc2 <= _T_18 @[dec_tlu_ctl.scala 3295:22]
|
|
|
|
|
node _T_19 = bits(mitcnt0_inc1, 7, 0) @[dec_tlu_ctl.scala 3296:56]
|
|
|
|
|
node mitcnt0_inc = cat(mitcnt0_inc2, _T_19) @[Cat.scala 29:58]
|
|
|
|
|
node _T_20 = bits(wr_mitcnt0_r, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
node _T_21 = bits(mit0_match_ns, 0, 0) @[lib.scala 8:44]
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|
|
|
|
node _T_22 = mux(_T_21, UInt<1>("h00"), mitcnt0_inc) @[dec_tlu_ctl.scala 3298:69]
|
|
|
|
|
node mitcnt0_ns = mux(_T_20, io.dec_csr_wrdata_r, _T_22) @[dec_tlu_ctl.scala 3298:30]
|
|
|
|
|
node _T_23 = bits(mitcnt0_ns, 31, 8) @[dec_tlu_ctl.scala 3301:48]
|
|
|
|
|
node _T_24 = and(mitcnt0_inc_ok, mitcnt0_inc_cout) @[dec_tlu_ctl.scala 3301:87]
|
|
|
|
|
node _T_25 = or(wr_mitcnt0_r, _T_24) @[dec_tlu_ctl.scala 3301:69]
|
|
|
|
|
node _T_26 = or(_T_25, mit0_match_ns) @[dec_tlu_ctl.scala 3301:107]
|
|
|
|
|
node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 3301:124]
|
|
|
|
|
inst rvclkhdr of rvclkhdr_89 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr.clock <= clock
|
|
|
|
|
rvclkhdr.reset <= reset
|
|
|
|
|
rvclkhdr.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr.io.en <= _T_27 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_28 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_27 : @[Reg.scala 28:19]
|
|
|
|
|
_T_28 <= _T_23 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_29 = bits(mitcnt0_ns, 7, 0) @[dec_tlu_ctl.scala 3302:34]
|
|
|
|
|
node _T_30 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 3302:54]
|
|
|
|
|
node _T_31 = or(_T_30, mit0_match_ns) @[dec_tlu_ctl.scala 3302:71]
|
|
|
|
|
node _T_32 = bits(_T_31, 0, 0) @[dec_tlu_ctl.scala 3302:88]
|
|
|
|
|
inst rvclkhdr_1 of rvclkhdr_90 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_1.clock <= clock
|
|
|
|
|
rvclkhdr_1.reset <= reset
|
|
|
|
|
rvclkhdr_1.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_1.io.en <= _T_32 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_33 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_32 : @[Reg.scala 28:19]
|
|
|
|
|
_T_33 <= _T_29 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_34 = cat(_T_28, _T_33) @[Cat.scala 29:58]
|
|
|
|
|
mitcnt0 <= _T_34 @[dec_tlu_ctl.scala 3301:25]
|
|
|
|
|
node _T_35 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 3309:72]
|
|
|
|
|
node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_35) @[dec_tlu_ctl.scala 3309:49]
|
|
|
|
|
node _T_36 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 3311:37]
|
|
|
|
|
node _T_37 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 3311:56]
|
|
|
|
|
node _T_38 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 3311:85]
|
|
|
|
|
node _T_39 = or(_T_37, _T_38) @[dec_tlu_ctl.scala 3311:76]
|
|
|
|
|
node _T_40 = and(_T_36, _T_39) @[dec_tlu_ctl.scala 3311:53]
|
|
|
|
|
node _T_41 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 3311:112]
|
|
|
|
|
node _T_42 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 3311:147]
|
|
|
|
|
node _T_43 = or(_T_41, _T_42) @[dec_tlu_ctl.scala 3311:138]
|
|
|
|
|
node _T_44 = and(_T_40, _T_43) @[dec_tlu_ctl.scala 3311:109]
|
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|
node _T_45 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 3311:173]
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|
node _T_46 = and(_T_44, _T_45) @[dec_tlu_ctl.scala 3311:171]
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|
node _T_47 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 3311:213]
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|
node _T_48 = not(_T_47) @[dec_tlu_ctl.scala 3311:205]
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|
node _T_49 = or(_T_48, mit0_match_ns) @[dec_tlu_ctl.scala 3311:217]
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|
|
node mitcnt1_inc_ok = and(_T_46, _T_49) @[dec_tlu_ctl.scala 3311:202]
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|
|
wire mitcnt1_inc1 : UInt<9>
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|
|
mitcnt1_inc1 <= UInt<1>("h00")
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|
wire mitcnt1_inc2 : UInt<24>
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|
|
mitcnt1_inc2 <= UInt<1>("h00")
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|
|
node _T_50 = bits(mitcnt1, 7, 0) @[dec_tlu_ctl.scala 3316:32]
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|
|
node _T_51 = cat(UInt<7>("h00"), UInt<1>("h01")) @[Cat.scala 29:58]
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|
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node _T_52 = add(_T_50, _T_51) @[dec_tlu_ctl.scala 3316:38]
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node _T_53 = tail(_T_52, 1) @[dec_tlu_ctl.scala 3316:38]
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mitcnt1_inc1 <= _T_53 @[dec_tlu_ctl.scala 3316:22]
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|
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node mitcnt1_inc_cout = bits(mitcnt1_inc1, 8, 8) @[dec_tlu_ctl.scala 3317:44]
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|
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node _T_54 = bits(mitcnt1, 31, 8) @[dec_tlu_ctl.scala 3318:32]
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node _T_55 = cat(UInt<23>("h00"), mitcnt1_inc_cout) @[Cat.scala 29:58]
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node _T_56 = add(_T_54, _T_55) @[dec_tlu_ctl.scala 3318:39]
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node _T_57 = tail(_T_56, 1) @[dec_tlu_ctl.scala 3318:39]
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mitcnt1_inc2 <= _T_57 @[dec_tlu_ctl.scala 3318:22]
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node _T_58 = bits(mitcnt1_inc1, 7, 0) @[dec_tlu_ctl.scala 3319:56]
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|
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node mitcnt1_inc = cat(mitcnt1_inc2, _T_58) @[Cat.scala 29:58]
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node _T_59 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 3321:43]
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node _T_60 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 3321:90]
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node _T_61 = mux(_T_60, UInt<1>("h00"), mitcnt1_inc) @[dec_tlu_ctl.scala 3321:75]
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node mitcnt1_ns = mux(_T_59, io.dec_csr_wrdata_r, _T_61) @[dec_tlu_ctl.scala 3321:29]
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node _T_62 = bits(mitcnt1_ns, 31, 8) @[dec_tlu_ctl.scala 3323:48]
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node _T_63 = and(mitcnt1_inc_ok, mitcnt1_inc_cout) @[dec_tlu_ctl.scala 3323:87]
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node _T_64 = or(wr_mitcnt1_r, _T_63) @[dec_tlu_ctl.scala 3323:69]
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node _T_65 = or(_T_64, mit1_match_ns) @[dec_tlu_ctl.scala 3323:107]
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node _T_66 = bits(_T_65, 0, 0) @[dec_tlu_ctl.scala 3323:124]
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|
inst rvclkhdr_2 of rvclkhdr_91 @[lib.scala 404:23]
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|
|
rvclkhdr_2.clock <= clock
|
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|
|
rvclkhdr_2.reset <= reset
|
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|
|
rvclkhdr_2.io.clk <= io.free_l2clk @[lib.scala 406:18]
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|
|
rvclkhdr_2.io.en <= _T_66 @[lib.scala 407:17]
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|
|
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
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|
|
reg _T_67 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_66 : @[Reg.scala 28:19]
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|
|
_T_67 <= _T_62 @[Reg.scala 28:23]
|
|
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|
|
skip @[Reg.scala 28:19]
|
|
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|
|
node _T_68 = bits(mitcnt1_ns, 7, 0) @[dec_tlu_ctl.scala 3324:34]
|
|
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|
|
node _T_69 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 3324:54]
|
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|
|
node _T_70 = or(_T_69, mit1_match_ns) @[dec_tlu_ctl.scala 3324:71]
|
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|
|
node _T_71 = bits(_T_70, 0, 0) @[dec_tlu_ctl.scala 3324:88]
|
|
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|
|
inst rvclkhdr_3 of rvclkhdr_92 @[lib.scala 404:23]
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|
|
|
|
rvclkhdr_3.clock <= clock
|
|
|
|
|
rvclkhdr_3.reset <= reset
|
|
|
|
|
rvclkhdr_3.io.clk <= io.free_l2clk @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_3.io.en <= _T_71 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg _T_72 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_71 : @[Reg.scala 28:19]
|
|
|
|
|
_T_72 <= _T_68 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_73 = cat(_T_67, _T_72) @[Cat.scala 29:58]
|
|
|
|
|
mitcnt1 <= _T_73 @[dec_tlu_ctl.scala 3323:25]
|
|
|
|
|
node _T_74 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 3333:70]
|
|
|
|
|
node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_74) @[dec_tlu_ctl.scala 3333:47]
|
|
|
|
|
node _T_75 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 3334:38]
|
|
|
|
|
node _T_76 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 3334:71]
|
|
|
|
|
inst rvclkhdr_4 of rvclkhdr_93 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_4.clock <= clock
|
|
|
|
|
rvclkhdr_4.reset <= reset
|
|
|
|
|
rvclkhdr_4.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_4.io.en <= _T_76 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg mitb0_b : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_76 : @[Reg.scala 28:19]
|
|
|
|
|
mitb0_b <= _T_75 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_77 = not(mitb0_b) @[dec_tlu_ctl.scala 3335:22]
|
|
|
|
|
mitb0 <= _T_77 @[dec_tlu_ctl.scala 3335:19]
|
|
|
|
|
node _T_78 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 3342:69]
|
|
|
|
|
node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_78) @[dec_tlu_ctl.scala 3342:47]
|
|
|
|
|
node _T_79 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 3343:29]
|
|
|
|
|
node _T_80 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 3343:62]
|
|
|
|
|
inst rvclkhdr_5 of rvclkhdr_94 @[lib.scala 404:23]
|
|
|
|
|
rvclkhdr_5.clock <= clock
|
|
|
|
|
rvclkhdr_5.reset <= reset
|
|
|
|
|
rvclkhdr_5.io.clk <= clock @[lib.scala 406:18]
|
|
|
|
|
rvclkhdr_5.io.en <= _T_80 @[lib.scala 407:17]
|
|
|
|
|
rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
|
|
|
|
reg mitb1_b : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_80 : @[Reg.scala 28:19]
|
|
|
|
|
mitb1_b <= _T_79 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_81 = not(mitb1_b) @[dec_tlu_ctl.scala 3344:18]
|
|
|
|
|
mitb1 <= _T_81 @[dec_tlu_ctl.scala 3344:15]
|
|
|
|
|
node _T_82 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 3355:72]
|
|
|
|
|
node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_82) @[dec_tlu_ctl.scala 3355:49]
|
|
|
|
|
node _T_83 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 3356:45]
|
|
|
|
|
node _T_84 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 3356:72]
|
|
|
|
|
node _T_85 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 3356:86]
|
|
|
|
|
node mitctl0_ns = mux(_T_83, _T_84, _T_85) @[dec_tlu_ctl.scala 3356:31]
|
|
|
|
|
node _T_86 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 3358:41]
|
|
|
|
|
node mitctl0_0_b_ns = not(_T_86) @[dec_tlu_ctl.scala 3358:30]
|
|
|
|
|
node _T_87 = bits(wr_mitctl0_r, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
reg mitctl0_0_b : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_87 : @[Reg.scala 28:19]
|
|
|
|
|
mitctl0_0_b <= mitctl0_0_b_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_88 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 3360:82]
|
|
|
|
|
node _T_89 = bits(wr_mitctl0_r, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
reg _T_90 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_89 : @[Reg.scala 28:19]
|
|
|
|
|
_T_90 <= _T_88 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_91 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 3360:107]
|
|
|
|
|
node _T_92 = cat(_T_90, _T_91) @[Cat.scala 29:58]
|
|
|
|
|
mitctl0 <= _T_92 @[dec_tlu_ctl.scala 3360:31]
|
|
|
|
|
node _T_93 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 3370:71]
|
|
|
|
|
node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_93) @[dec_tlu_ctl.scala 3370:49]
|
|
|
|
|
node _T_94 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 3371:45]
|
|
|
|
|
node _T_95 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 3371:71]
|
|
|
|
|
node _T_96 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 3371:85]
|
|
|
|
|
node mitctl1_ns = mux(_T_94, _T_95, _T_96) @[dec_tlu_ctl.scala 3371:31]
|
|
|
|
|
node _T_97 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 3372:40]
|
|
|
|
|
node mitctl1_0_b_ns = not(_T_97) @[dec_tlu_ctl.scala 3372:29]
|
|
|
|
|
node _T_98 = bits(wr_mitctl1_r, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
reg mitctl1_0_b : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_98 : @[Reg.scala 28:19]
|
|
|
|
|
mitctl1_0_b <= mitctl1_0_b_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_99 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 3374:67]
|
|
|
|
|
node _T_100 = bits(wr_mitctl1_r, 0, 0) @[lib.scala 8:44]
|
|
|
|
|
reg _T_101 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_100 : @[Reg.scala 28:19]
|
|
|
|
|
_T_101 <= _T_99 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_102 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 3374:92]
|
|
|
|
|
node _T_103 = cat(_T_101, _T_102) @[Cat.scala 29:58]
|
|
|
|
|
mitctl1 <= _T_103 @[dec_tlu_ctl.scala 3374:16]
|
|
|
|
|
node _T_104 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 3376:51]
|
|
|
|
|
node _T_105 = or(_T_104, io.csr_mitb1) @[dec_tlu_ctl.scala 3376:68]
|
|
|
|
|
node _T_106 = or(_T_105, io.csr_mitb0) @[dec_tlu_ctl.scala 3376:83]
|
|
|
|
|
node _T_107 = or(_T_106, io.csr_mitctl0) @[dec_tlu_ctl.scala 3376:98]
|
|
|
|
|
node _T_108 = or(_T_107, io.csr_mitctl1) @[dec_tlu_ctl.scala 3376:115]
|
|
|
|
|
io.dec_timer_read_d <= _T_108 @[dec_tlu_ctl.scala 3376:33]
|
|
|
|
|
node _T_109 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 3378:32]
|
|
|
|
|
node _T_110 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 3378:51]
|
|
|
|
|
node _T_111 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 3379:32]
|
|
|
|
|
node _T_112 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 3380:30]
|
|
|
|
|
node _T_113 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 3381:30]
|
|
|
|
|
node _T_114 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 3382:32]
|
|
|
|
|
node _T_115 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_116 = cat(_T_115, mitctl0) @[Cat.scala 29:58]
|
|
|
|
|
node _T_117 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 3383:32]
|
|
|
|
|
node _T_118 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_119 = cat(_T_118, mitctl1) @[Cat.scala 29:58]
|
|
|
|
|
node _T_120 = mux(_T_109, _T_110, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_121 = mux(_T_111, mitcnt1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_122 = mux(_T_112, mitb0, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_123 = mux(_T_113, mitb1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_124 = mux(_T_114, _T_116, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_125 = mux(_T_117, _T_119, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_126 = or(_T_120, _T_121) @[Mux.scala 27:72]
|
|
|
|
|
node _T_127 = or(_T_126, _T_122) @[Mux.scala 27:72]
|
|
|
|
|
node _T_128 = or(_T_127, _T_123) @[Mux.scala 27:72]
|
|
|
|
|
node _T_129 = or(_T_128, _T_124) @[Mux.scala 27:72]
|
|
|
|
|
node _T_130 = or(_T_129, _T_125) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_131 : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
_T_131 <= _T_130 @[Mux.scala 27:72]
|
|
|
|
|
io.dec_timer_rddata_d <= _T_131 @[dec_tlu_ctl.scala 3377:33]
|
|
|
|
|
|
|
|
|
|
module dec_decode_csr_read :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : AsyncReset
|
|
|
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output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_meicpct : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}}
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node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 3173:198]
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node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 3173:198]
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node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 3173:198]
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node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 3175:57]
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node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 3173:198]
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node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 3173:198]
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node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 3176:57]
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node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 3173:198]
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node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 3173:198]
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node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 3177:57]
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node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 3173:198]
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node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 3173:198]
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node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 3178:57]
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node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 3173:198]
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node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 3179:57]
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node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 3173:198]
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node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 3173:198]
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node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 3173:198]
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node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 3180:57]
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node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 3173:198]
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node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 3173:198]
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node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 3173:198]
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node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 3181:57]
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node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 3173:198]
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node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 3182:65]
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node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 3173:198]
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node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 3173:198]
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node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 3173:198]
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node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 3183:65]
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node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 3173:198]
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node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 3173:198]
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node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 3173:198]
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node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 3173:198]
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node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 3184:57]
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node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 3173:198]
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node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 3173:198]
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node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 3173:198]
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node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 3173:198]
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node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 3173:198]
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node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 3185:57]
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node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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|
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|
|
node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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|
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|
|
node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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|
|
node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 3173:198]
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node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 3173:198]
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node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 3173:198]
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node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 3173:198]
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node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 3173:198]
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|
io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 3186:57]
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|
node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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|
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node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 3173:198]
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node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 3173:198]
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|
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|
|
node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 3187:57]
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|
|
node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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|
|
node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
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|
|
node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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|
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|
|
node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
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|
|
node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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|
node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 3173:198]
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node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 3173:198]
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|
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node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 3173:198]
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|
io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 3188:57]
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|
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node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
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node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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|
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node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 3173:198]
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|
io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 3189:57]
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|
|
node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
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node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 3173:198]
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node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 3173:198]
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|
io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 3190:57]
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|
|
node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 3173:198]
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node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 3173:198]
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|
io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 3191:57]
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node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 3192:57]
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|
|
node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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|
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|
|
node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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|
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|
|
node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 3193:57]
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|
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|
|
node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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|
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|
|
node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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|
|
node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
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|
|
node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 3194:57]
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|
|
node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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|
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|
|
node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 3195:57]
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|
|
node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 3196:57]
|
|
|
|
|
node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 3197:57]
|
|
|
|
|
node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
|
node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 3198:57]
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|
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|
|
node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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|
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|
|
node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 3173:198]
|
|
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|
|
io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 3199:57]
|
|
|
|
|
node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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|
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|
|
node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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|
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|
node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 3200:57]
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node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 3173:198]
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node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 3173:198]
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node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 3201:57]
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|
|
node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
|
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|
node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
|
|
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|
|
node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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|
|
node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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|
|
node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 3202:57]
|
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|
|
node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
|
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|
|
node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
|
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|
|
node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
|
|
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|
|
node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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|
|
node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 3203:57]
|
|
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|
|
node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
|
|
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|
|
node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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|
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|
|
node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
|
|
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|
|
node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
|
|
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|
|
node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
|
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|
|
node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 3204:65]
|
|
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|
|
node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
|
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|
|
node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
|
|
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|
|
node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
|
|
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|
|
node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
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|
|
node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
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|
|
node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 3173:198]
|
|
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|
|
node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 3205:57]
|
|
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|
|
node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
|
|
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|
|
node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 3206:57]
|
|
|
|
|
node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 3207:57]
|
|
|
|
|
node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 3208:57]
|
|
|
|
|
node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 3209:57]
|
|
|
|
|
node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 3210:57]
|
|
|
|
|
node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 3173:198]
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|
io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 3211:57]
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|
node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 3173:198]
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node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 3173:198]
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node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 3173:198]
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node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 3173:198]
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node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 3212:57]
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node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 3173:198]
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node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 3173:198]
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node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 3173:198]
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node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 3173:198]
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node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 3173:198]
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node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 3213:57]
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|
node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 3173:198]
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node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 3173:198]
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node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 3173:198]
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node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 3173:198]
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node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 3214:57]
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node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 3173:198]
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node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 3173:198]
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node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 3173:198]
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node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 3173:198]
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node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 3173:198]
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node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 3215:57]
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node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 3216:57]
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|
|
node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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|
|
node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
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|
|
node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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|
|
node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
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|
|
node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
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|
|
node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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|
|
node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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|
|
node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 3217:57]
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|
|
node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 3173:198]
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|
|
io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 3218:57]
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|
node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
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|
|
node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
|
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|
node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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|
node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
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|
|
node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 3173:198]
|
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|
node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 3173:198]
|
|
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|
|
io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 3219:57]
|
|
|
|
|
node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 3173:198]
|
|
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|
|
node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 3220:49]
|
|
|
|
|
node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 3221:57]
|
|
|
|
|
node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 3173:198]
|
|
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|
|
io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 3222:57]
|
|
|
|
|
node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 3223:57]
|
|
|
|
|
node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 3224:57]
|
|
|
|
|
node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 3225:57]
|
|
|
|
|
node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 3173:198]
|
|
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|
|
io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 3226:57]
|
|
|
|
|
node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 3227:57]
|
|
|
|
|
node _T_628 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_630 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_631 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_632 = eq(_T_631, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_633 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_634 = and(_T_633, _T_630) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_635 = and(_T_634, _T_632) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_meicpct <= _T_635 @[dec_tlu_ctl.scala 3229:57]
|
|
|
|
|
node _T_636 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_637 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_638 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_639 = eq(_T_638, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_640 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_641 = eq(_T_640, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_642 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_643 = eq(_T_642, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_644 = and(_T_636, _T_637) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_645 = and(_T_644, _T_639) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_646 = and(_T_645, _T_641) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_647 = and(_T_646, _T_643) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_micect <= _T_647 @[dec_tlu_ctl.scala 3231:57]
|
|
|
|
|
node _T_648 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_649 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_650 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_652 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_653 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_654 = and(_T_653, _T_651) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_655 = and(_T_654, _T_652) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_miccmect <= _T_655 @[dec_tlu_ctl.scala 3232:57]
|
|
|
|
|
node _T_656 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_657 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_658 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_659 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_660 = eq(_T_659, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_661 = and(_T_656, _T_657) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_662 = and(_T_661, _T_658) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_663 = and(_T_662, _T_660) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mdccmect <= _T_663 @[dec_tlu_ctl.scala 3233:57]
|
|
|
|
|
node _T_664 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_665 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_666 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_667 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_668 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_669 = eq(_T_668, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_670 = and(_T_664, _T_665) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_671 = and(_T_670, _T_666) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_672 = and(_T_671, _T_667) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_673 = and(_T_672, _T_669) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mfdht <= _T_673 @[dec_tlu_ctl.scala 3234:57]
|
|
|
|
|
node _T_674 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_675 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_676 = eq(_T_675, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_677 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_678 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_679 = and(_T_674, _T_676) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_680 = and(_T_679, _T_677) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_681 = and(_T_680, _T_678) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
io.csr_pkt.csr_mfdhs <= _T_681 @[dec_tlu_ctl.scala 3235:57]
|
|
|
|
|
node _T_682 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_684 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_685 = eq(_T_684, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_686 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_687 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_688 = eq(_T_687, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_689 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_690 = eq(_T_689, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_693 = and(_T_683, _T_685) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_694 = and(_T_693, _T_686) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_695 = and(_T_694, _T_688) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_696 = and(_T_695, _T_690) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_697 = and(_T_696, _T_692) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_dicawics <= _T_697 @[dec_tlu_ctl.scala 3236:57]
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node _T_698 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_699 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_701 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_702 = eq(_T_701, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_703 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 3173:198]
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node _T_704 = and(_T_703, _T_700) @[dec_tlu_ctl.scala 3173:198]
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node _T_705 = and(_T_704, _T_702) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_dicad0h <= _T_705 @[dec_tlu_ctl.scala 3237:57]
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node _T_706 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_707 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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node _T_710 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_712 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_713 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 3173:198]
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node _T_714 = and(_T_713, _T_709) @[dec_tlu_ctl.scala 3173:198]
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node _T_715 = and(_T_714, _T_711) @[dec_tlu_ctl.scala 3173:198]
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node _T_716 = and(_T_715, _T_712) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_dicad0 <= _T_716 @[dec_tlu_ctl.scala 3238:57]
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node _T_717 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_718 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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node _T_719 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_720 = eq(_T_719, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
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node _T_721 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_722 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_723 = eq(_T_722, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_724 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 3173:198]
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node _T_725 = and(_T_724, _T_720) @[dec_tlu_ctl.scala 3173:198]
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node _T_726 = and(_T_725, _T_721) @[dec_tlu_ctl.scala 3173:198]
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node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 3173:198]
|
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io.csr_pkt.csr_dicad1 <= _T_727 @[dec_tlu_ctl.scala 3239:57]
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node _T_728 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_729 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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node _T_730 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_732 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_733 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_734 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 3173:198]
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node _T_735 = and(_T_734, _T_731) @[dec_tlu_ctl.scala 3173:198]
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node _T_736 = and(_T_735, _T_732) @[dec_tlu_ctl.scala 3173:198]
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node _T_737 = and(_T_736, _T_733) @[dec_tlu_ctl.scala 3173:198]
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io.csr_pkt.csr_dicago <= _T_737 @[dec_tlu_ctl.scala 3240:57]
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node _T_738 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_739 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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node _T_740 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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node _T_741 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_742 = eq(_T_741, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_743 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_744 = and(_T_738, _T_739) @[dec_tlu_ctl.scala 3173:198]
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node _T_745 = and(_T_744, _T_740) @[dec_tlu_ctl.scala 3173:198]
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node _T_746 = and(_T_745, _T_742) @[dec_tlu_ctl.scala 3173:198]
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node _T_747 = and(_T_746, _T_743) @[dec_tlu_ctl.scala 3173:198]
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node _T_748 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_749 = eq(_T_748, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_750 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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node _T_751 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_752 = eq(_T_751, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_753 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_755 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_756 = eq(_T_755, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_757 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_758 = eq(_T_757, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_759 = and(_T_749, _T_750) @[dec_tlu_ctl.scala 3173:198]
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node _T_760 = and(_T_759, _T_752) @[dec_tlu_ctl.scala 3173:198]
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node _T_761 = and(_T_760, _T_754) @[dec_tlu_ctl.scala 3173:198]
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node _T_762 = and(_T_761, _T_756) @[dec_tlu_ctl.scala 3173:198]
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node _T_763 = and(_T_762, _T_758) @[dec_tlu_ctl.scala 3173:198]
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node _T_764 = or(_T_747, _T_763) @[dec_tlu_ctl.scala 3241:81]
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node _T_765 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_766 = eq(_T_765, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_767 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_768 = eq(_T_767, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_769 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_770 = eq(_T_769, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_771 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_773 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_774 = eq(_T_773, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_775 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_776 = and(_T_766, _T_768) @[dec_tlu_ctl.scala 3173:198]
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node _T_777 = and(_T_776, _T_770) @[dec_tlu_ctl.scala 3173:198]
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node _T_778 = and(_T_777, _T_772) @[dec_tlu_ctl.scala 3173:198]
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node _T_779 = and(_T_778, _T_774) @[dec_tlu_ctl.scala 3173:198]
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node _T_780 = and(_T_779, _T_775) @[dec_tlu_ctl.scala 3173:198]
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node _T_781 = or(_T_764, _T_780) @[dec_tlu_ctl.scala 3241:121]
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node _T_782 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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node _T_783 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_784 = eq(_T_783, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_785 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_786 = eq(_T_785, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
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|
|
node _T_787 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_788 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_790 = and(_T_782, _T_784) @[dec_tlu_ctl.scala 3173:198]
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node _T_791 = and(_T_790, _T_786) @[dec_tlu_ctl.scala 3173:198]
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node _T_792 = and(_T_791, _T_787) @[dec_tlu_ctl.scala 3173:198]
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node _T_793 = and(_T_792, _T_789) @[dec_tlu_ctl.scala 3173:198]
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node _T_794 = or(_T_781, _T_793) @[dec_tlu_ctl.scala 3241:155]
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node _T_795 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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node _T_796 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_798 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_799 = eq(_T_798, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_800 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_801 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_802 = eq(_T_801, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_803 = and(_T_795, _T_797) @[dec_tlu_ctl.scala 3173:198]
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node _T_804 = and(_T_803, _T_799) @[dec_tlu_ctl.scala 3173:198]
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node _T_805 = and(_T_804, _T_800) @[dec_tlu_ctl.scala 3173:198]
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node _T_806 = and(_T_805, _T_802) @[dec_tlu_ctl.scala 3173:198]
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node _T_807 = or(_T_794, _T_806) @[dec_tlu_ctl.scala 3242:49]
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node _T_808 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_809 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_810 = eq(_T_809, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_811 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_813 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_814 = eq(_T_813, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_815 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_816 = eq(_T_815, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
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node _T_817 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_818 = and(_T_808, _T_810) @[dec_tlu_ctl.scala 3173:198]
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node _T_819 = and(_T_818, _T_812) @[dec_tlu_ctl.scala 3173:198]
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node _T_820 = and(_T_819, _T_814) @[dec_tlu_ctl.scala 3173:198]
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node _T_821 = and(_T_820, _T_816) @[dec_tlu_ctl.scala 3173:198]
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node _T_822 = and(_T_821, _T_817) @[dec_tlu_ctl.scala 3173:198]
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node _T_823 = or(_T_807, _T_822) @[dec_tlu_ctl.scala 3242:89]
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|
io.csr_pkt.presync <= _T_823 @[dec_tlu_ctl.scala 3241:34]
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|
|
node _T_824 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_825 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_826 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_827 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_828 = eq(_T_827, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
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|
|
node _T_829 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_830 = and(_T_824, _T_825) @[dec_tlu_ctl.scala 3173:198]
|
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|
node _T_831 = and(_T_830, _T_826) @[dec_tlu_ctl.scala 3173:198]
|
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|
node _T_832 = and(_T_831, _T_828) @[dec_tlu_ctl.scala 3173:198]
|
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|
node _T_833 = and(_T_832, _T_829) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_834 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
|
|
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|
|
node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
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|
|
node _T_836 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
|
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|
node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
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|
node _T_838 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
|
|
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|
|
node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
node _T_840 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
|
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|
|
node _T_841 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_842 = and(_T_835, _T_837) @[dec_tlu_ctl.scala 3173:198]
|
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|
node _T_843 = and(_T_842, _T_839) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_844 = and(_T_843, _T_840) @[dec_tlu_ctl.scala 3173:198]
|
|
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|
|
node _T_845 = and(_T_844, _T_841) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_846 = or(_T_833, _T_845) @[dec_tlu_ctl.scala 3243:81]
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|
node _T_847 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_848 = eq(_T_847, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
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node _T_849 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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|
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node _T_853 = and(_T_848, _T_849) @[dec_tlu_ctl.scala 3173:198]
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node _T_854 = and(_T_853, _T_851) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_855 = and(_T_854, _T_852) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_856 = or(_T_846, _T_855) @[dec_tlu_ctl.scala 3243:121]
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node _T_857 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_858 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_859 = eq(_T_858, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_860 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_861 = eq(_T_860, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_862 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_863 = and(_T_857, _T_859) @[dec_tlu_ctl.scala 3173:198]
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node _T_864 = and(_T_863, _T_861) @[dec_tlu_ctl.scala 3173:198]
|
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node _T_865 = and(_T_864, _T_862) @[dec_tlu_ctl.scala 3173:198]
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node _T_866 = or(_T_856, _T_865) @[dec_tlu_ctl.scala 3243:162]
|
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node _T_867 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
|
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|
node _T_868 = eq(_T_867, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_869 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
|
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node _T_870 = eq(_T_869, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
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|
|
node _T_871 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_872 = eq(_T_871, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
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|
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node _T_873 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
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node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
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|
|
node _T_875 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
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|
node _T_876 = eq(_T_875, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
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node _T_877 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
|
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node _T_878 = eq(_T_877, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
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|
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node _T_879 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
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node _T_880 = eq(_T_879, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
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|
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|
node _T_881 = and(_T_868, _T_870) @[dec_tlu_ctl.scala 3173:198]
|
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node _T_882 = and(_T_881, _T_872) @[dec_tlu_ctl.scala 3173:198]
|
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|
node _T_883 = and(_T_882, _T_874) @[dec_tlu_ctl.scala 3173:198]
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node _T_884 = and(_T_883, _T_876) @[dec_tlu_ctl.scala 3173:198]
|
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node _T_885 = and(_T_884, _T_878) @[dec_tlu_ctl.scala 3173:198]
|
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node _T_886 = and(_T_885, _T_880) @[dec_tlu_ctl.scala 3173:198]
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node _T_887 = or(_T_866, _T_886) @[dec_tlu_ctl.scala 3244:57]
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|
node _T_888 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_889 = eq(_T_888, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
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|
|
node _T_890 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
|
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|
node _T_891 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
|
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node _T_892 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
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|
node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
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|
|
node _T_894 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
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|
node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
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node _T_896 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_898 = and(_T_889, _T_890) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_899 = and(_T_898, _T_891) @[dec_tlu_ctl.scala 3173:198]
|
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|
node _T_900 = and(_T_899, _T_893) @[dec_tlu_ctl.scala 3173:198]
|
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|
node _T_901 = and(_T_900, _T_895) @[dec_tlu_ctl.scala 3173:198]
|
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|
node _T_902 = and(_T_901, _T_897) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_903 = or(_T_887, _T_902) @[dec_tlu_ctl.scala 3244:97]
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node _T_904 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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|
|
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|
node _T_905 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
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|
node _T_906 = eq(_T_905, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_907 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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|
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|
|
node _T_908 = eq(_T_907, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_909 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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|
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|
|
node _T_910 = eq(_T_909, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
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|
|
node _T_911 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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|
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node _T_912 = and(_T_904, _T_906) @[dec_tlu_ctl.scala 3173:198]
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node _T_913 = and(_T_912, _T_908) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_914 = and(_T_913, _T_910) @[dec_tlu_ctl.scala 3173:198]
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node _T_915 = and(_T_914, _T_911) @[dec_tlu_ctl.scala 3173:198]
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|
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node _T_916 = or(_T_903, _T_915) @[dec_tlu_ctl.scala 3244:130]
|
|
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|
|
io.csr_pkt.postsync <= _T_916 @[dec_tlu_ctl.scala 3243:30]
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|
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|
|
node _T_917 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_919 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_920 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_921 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_922 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_923 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_924 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_925 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_926 = eq(_T_925, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_927 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_928 = eq(_T_927, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_929 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_930 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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|
|
|
|
node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_932 = and(_T_918, _T_919) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_933 = and(_T_932, _T_920) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_934 = and(_T_933, _T_921) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_935 = and(_T_934, _T_922) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_936 = and(_T_935, _T_923) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_937 = and(_T_936, _T_924) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_938 = and(_T_937, _T_926) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_939 = and(_T_938, _T_928) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_940 = and(_T_939, _T_929) @[dec_tlu_ctl.scala 3173:198]
|
|
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|
|
node _T_941 = and(_T_940, _T_931) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
|
node _T_942 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_943 = eq(_T_942, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_944 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_945 = eq(_T_944, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_946 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_947 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_948 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_950 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_952 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_953 = eq(_T_952, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_954 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_955 = eq(_T_954, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_956 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_957 = eq(_T_956, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_958 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_959 = eq(_T_958, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_960 = and(_T_943, _T_945) @[dec_tlu_ctl.scala 3173:198]
|
|
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|
|
node _T_961 = and(_T_960, _T_946) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_962 = and(_T_961, _T_947) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
|
node _T_963 = and(_T_962, _T_949) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
node _T_964 = and(_T_963, _T_951) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_965 = and(_T_964, _T_953) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_966 = and(_T_965, _T_955) @[dec_tlu_ctl.scala 3173:198]
|
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|
node _T_967 = and(_T_966, _T_957) @[dec_tlu_ctl.scala 3173:198]
|
|
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|
|
node _T_968 = and(_T_967, _T_959) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_969 = or(_T_941, _T_968) @[dec_tlu_ctl.scala 3246:81]
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|
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|
|
node _T_970 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_971 = eq(_T_970, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_972 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_973 = eq(_T_972, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_974 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_975 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_976 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_977 = eq(_T_976, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_978 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_979 = eq(_T_978, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_980 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_983 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
|
|
|
|
|
node _T_984 = eq(_T_983, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
|
|
|
|
|
node _T_985 = and(_T_971, _T_973) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_986 = and(_T_985, _T_974) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_987 = and(_T_986, _T_975) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_988 = and(_T_987, _T_977) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_989 = and(_T_988, _T_979) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_992 = and(_T_991, _T_984) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_993 = or(_T_969, _T_992) @[dec_tlu_ctl.scala 3246:129]
|
|
|
|
|
node _T_994 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_995 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
|
|
|
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|
node _T_996 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_997 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_998 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_999 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1001 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1003 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1005 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_1006 = eq(_T_1005, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1007 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_1008 = eq(_T_1007, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_1009 = and(_T_994, _T_995) @[dec_tlu_ctl.scala 3173:198]
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node _T_1010 = and(_T_1009, _T_996) @[dec_tlu_ctl.scala 3173:198]
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node _T_1011 = and(_T_1010, _T_997) @[dec_tlu_ctl.scala 3173:198]
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node _T_1012 = and(_T_1011, _T_998) @[dec_tlu_ctl.scala 3173:198]
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node _T_1013 = and(_T_1012, _T_1000) @[dec_tlu_ctl.scala 3173:198]
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node _T_1014 = and(_T_1013, _T_1002) @[dec_tlu_ctl.scala 3173:198]
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node _T_1015 = and(_T_1014, _T_1004) @[dec_tlu_ctl.scala 3173:198]
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node _T_1016 = and(_T_1015, _T_1006) @[dec_tlu_ctl.scala 3173:198]
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node _T_1017 = and(_T_1016, _T_1008) @[dec_tlu_ctl.scala 3173:198]
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node _T_1018 = or(_T_993, _T_1017) @[dec_tlu_ctl.scala 3247:73]
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node _T_1019 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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node _T_1020 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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node _T_1021 = eq(_T_1020, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1022 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1023 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1024 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1026 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1028 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_1030 = and(_T_1019, _T_1021) @[dec_tlu_ctl.scala 3173:198]
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node _T_1031 = and(_T_1030, _T_1022) @[dec_tlu_ctl.scala 3173:198]
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node _T_1032 = and(_T_1031, _T_1023) @[dec_tlu_ctl.scala 3173:198]
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node _T_1033 = and(_T_1032, _T_1025) @[dec_tlu_ctl.scala 3173:198]
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node _T_1034 = and(_T_1033, _T_1027) @[dec_tlu_ctl.scala 3173:198]
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node _T_1035 = and(_T_1034, _T_1029) @[dec_tlu_ctl.scala 3173:198]
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node _T_1036 = or(_T_1018, _T_1035) @[dec_tlu_ctl.scala 3247:121]
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node _T_1037 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_1038 = eq(_T_1037, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1039 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_1040 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1041 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1042 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_1043 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_1044 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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node _T_1045 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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node _T_1046 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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node _T_1047 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_1048 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_1049 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_1050 = and(_T_1038, _T_1039) @[dec_tlu_ctl.scala 3173:198]
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node _T_1051 = and(_T_1050, _T_1040) @[dec_tlu_ctl.scala 3173:198]
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node _T_1052 = and(_T_1051, _T_1041) @[dec_tlu_ctl.scala 3173:198]
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node _T_1053 = and(_T_1052, _T_1042) @[dec_tlu_ctl.scala 3173:198]
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node _T_1054 = and(_T_1053, _T_1043) @[dec_tlu_ctl.scala 3173:198]
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node _T_1055 = and(_T_1054, _T_1044) @[dec_tlu_ctl.scala 3173:198]
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node _T_1056 = and(_T_1055, _T_1045) @[dec_tlu_ctl.scala 3173:198]
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node _T_1057 = and(_T_1056, _T_1046) @[dec_tlu_ctl.scala 3173:198]
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node _T_1058 = and(_T_1057, _T_1047) @[dec_tlu_ctl.scala 3173:198]
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node _T_1059 = and(_T_1058, _T_1048) @[dec_tlu_ctl.scala 3173:198]
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node _T_1060 = and(_T_1059, _T_1049) @[dec_tlu_ctl.scala 3173:198]
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node _T_1061 = or(_T_1036, _T_1060) @[dec_tlu_ctl.scala 3248:73]
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node _T_1062 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_1063 = eq(_T_1062, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1064 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_1065 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1066 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1067 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_1068 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_1069 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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node _T_1070 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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node _T_1071 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_1072 = eq(_T_1071, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1073 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_1074 = eq(_T_1073, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1075 = and(_T_1063, _T_1064) @[dec_tlu_ctl.scala 3173:198]
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node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 3173:198]
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node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 3173:198]
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node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 3173:198]
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node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 3173:198]
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node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 3173:198]
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node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 3173:198]
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node _T_1082 = and(_T_1081, _T_1072) @[dec_tlu_ctl.scala 3173:198]
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node _T_1083 = and(_T_1082, _T_1074) @[dec_tlu_ctl.scala 3173:198]
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node _T_1084 = or(_T_1061, _T_1083) @[dec_tlu_ctl.scala 3248:121]
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node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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node _T_1086 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1087 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1088 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_1089 = eq(_T_1088, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1090 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_1091 = eq(_T_1090, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1094 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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node _T_1095 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_1096 = eq(_T_1095, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1097 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_1098 = eq(_T_1097, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1099 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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node _T_1100 = and(_T_1085, _T_1086) @[dec_tlu_ctl.scala 3173:198]
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node _T_1101 = and(_T_1100, _T_1087) @[dec_tlu_ctl.scala 3173:198]
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node _T_1102 = and(_T_1101, _T_1089) @[dec_tlu_ctl.scala 3173:198]
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node _T_1103 = and(_T_1102, _T_1091) @[dec_tlu_ctl.scala 3173:198]
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node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 3173:198]
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node _T_1105 = and(_T_1104, _T_1094) @[dec_tlu_ctl.scala 3173:198]
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node _T_1106 = and(_T_1105, _T_1096) @[dec_tlu_ctl.scala 3173:198]
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node _T_1107 = and(_T_1106, _T_1098) @[dec_tlu_ctl.scala 3173:198]
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node _T_1108 = and(_T_1107, _T_1099) @[dec_tlu_ctl.scala 3173:198]
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node _T_1109 = or(_T_1084, _T_1108) @[dec_tlu_ctl.scala 3249:73]
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node _T_1110 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_1111 = eq(_T_1110, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1112 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_1113 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1114 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1115 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_1116 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1118 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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node _T_1119 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_1120 = eq(_T_1119, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1121 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_1122 = eq(_T_1121, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1123 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1125 = and(_T_1111, _T_1112) @[dec_tlu_ctl.scala 3173:198]
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node _T_1126 = and(_T_1125, _T_1113) @[dec_tlu_ctl.scala 3173:198]
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node _T_1127 = and(_T_1126, _T_1114) @[dec_tlu_ctl.scala 3173:198]
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node _T_1128 = and(_T_1127, _T_1115) @[dec_tlu_ctl.scala 3173:198]
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node _T_1129 = and(_T_1128, _T_1117) @[dec_tlu_ctl.scala 3173:198]
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node _T_1130 = and(_T_1129, _T_1118) @[dec_tlu_ctl.scala 3173:198]
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node _T_1131 = and(_T_1130, _T_1120) @[dec_tlu_ctl.scala 3173:198]
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node _T_1132 = and(_T_1131, _T_1122) @[dec_tlu_ctl.scala 3173:198]
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node _T_1133 = and(_T_1132, _T_1124) @[dec_tlu_ctl.scala 3173:198]
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node _T_1134 = or(_T_1109, _T_1133) @[dec_tlu_ctl.scala 3249:129]
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node _T_1135 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_1136 = eq(_T_1135, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1137 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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node _T_1138 = eq(_T_1137, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1139 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1140 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1141 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_1142 = eq(_T_1141, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1143 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_1144 = eq(_T_1143, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1145 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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node _T_1146 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_1147 = and(_T_1136, _T_1138) @[dec_tlu_ctl.scala 3173:198]
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node _T_1148 = and(_T_1147, _T_1139) @[dec_tlu_ctl.scala 3173:198]
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node _T_1149 = and(_T_1148, _T_1140) @[dec_tlu_ctl.scala 3173:198]
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node _T_1150 = and(_T_1149, _T_1142) @[dec_tlu_ctl.scala 3173:198]
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node _T_1151 = and(_T_1150, _T_1144) @[dec_tlu_ctl.scala 3173:198]
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node _T_1152 = and(_T_1151, _T_1145) @[dec_tlu_ctl.scala 3173:198]
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node _T_1153 = and(_T_1152, _T_1146) @[dec_tlu_ctl.scala 3173:198]
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node _T_1154 = or(_T_1134, _T_1153) @[dec_tlu_ctl.scala 3250:73]
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node _T_1155 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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node _T_1156 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1157 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1158 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1160 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1162 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1164 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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node _T_1165 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_1166 = eq(_T_1165, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1167 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_1168 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_1169 = eq(_T_1168, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1170 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_1172 = and(_T_1155, _T_1156) @[dec_tlu_ctl.scala 3173:198]
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node _T_1173 = and(_T_1172, _T_1157) @[dec_tlu_ctl.scala 3173:198]
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node _T_1174 = and(_T_1173, _T_1159) @[dec_tlu_ctl.scala 3173:198]
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node _T_1175 = and(_T_1174, _T_1161) @[dec_tlu_ctl.scala 3173:198]
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node _T_1176 = and(_T_1175, _T_1163) @[dec_tlu_ctl.scala 3173:198]
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node _T_1177 = and(_T_1176, _T_1164) @[dec_tlu_ctl.scala 3173:198]
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node _T_1178 = and(_T_1177, _T_1166) @[dec_tlu_ctl.scala 3173:198]
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node _T_1179 = and(_T_1178, _T_1167) @[dec_tlu_ctl.scala 3173:198]
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node _T_1180 = and(_T_1179, _T_1169) @[dec_tlu_ctl.scala 3173:198]
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node _T_1181 = and(_T_1180, _T_1171) @[dec_tlu_ctl.scala 3173:198]
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node _T_1182 = or(_T_1154, _T_1181) @[dec_tlu_ctl.scala 3250:129]
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node _T_1183 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1185 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_1186 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1187 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1188 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_1189 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_1190 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_1191 = eq(_T_1190, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1192 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_1193 = eq(_T_1192, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1194 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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node _T_1195 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_1196 = and(_T_1184, _T_1185) @[dec_tlu_ctl.scala 3173:198]
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node _T_1197 = and(_T_1196, _T_1186) @[dec_tlu_ctl.scala 3173:198]
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node _T_1198 = and(_T_1197, _T_1187) @[dec_tlu_ctl.scala 3173:198]
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node _T_1199 = and(_T_1198, _T_1188) @[dec_tlu_ctl.scala 3173:198]
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node _T_1200 = and(_T_1199, _T_1189) @[dec_tlu_ctl.scala 3173:198]
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node _T_1201 = and(_T_1200, _T_1191) @[dec_tlu_ctl.scala 3173:198]
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node _T_1202 = and(_T_1201, _T_1193) @[dec_tlu_ctl.scala 3173:198]
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node _T_1203 = and(_T_1202, _T_1194) @[dec_tlu_ctl.scala 3173:198]
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node _T_1204 = and(_T_1203, _T_1195) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_1205 = or(_T_1182, _T_1204) @[dec_tlu_ctl.scala 3251:65]
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node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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|
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|
|
node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
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node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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|
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node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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|
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node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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node _T_1216 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_1217 = eq(_T_1216, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
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|
node _T_1218 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 3173:198]
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node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 3173:198]
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node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 3173:198]
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node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 3173:198]
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node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 3173:198]
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node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
node _T_1225 = and(_T_1224, _T_1215) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 3251:121]
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|
|
|
|
node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1230 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1231 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1232 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1233 = eq(_T_1232, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1234 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1235 = eq(_T_1234, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1243 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1244 = and(_T_1229, _T_1230) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_1245 = and(_T_1244, _T_1231) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_1246 = and(_T_1245, _T_1233) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_1247 = and(_T_1246, _T_1235) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1248 = and(_T_1247, _T_1237) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1249 = and(_T_1248, _T_1238) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1250 = and(_T_1249, _T_1240) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1251 = and(_T_1250, _T_1242) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1252 = and(_T_1251, _T_1243) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1253 = or(_T_1228, _T_1252) @[dec_tlu_ctl.scala 3252:73]
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|
|
|
|
node _T_1254 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1256 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1258 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1259 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1260 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1262 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1264 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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|
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|
|
node _T_1266 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1267 = and(_T_1255, _T_1257) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_1268 = and(_T_1267, _T_1258) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1269 = and(_T_1268, _T_1259) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1270 = and(_T_1269, _T_1261) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1271 = and(_T_1270, _T_1263) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1272 = and(_T_1271, _T_1264) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1273 = and(_T_1272, _T_1265) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1274 = and(_T_1273, _T_1266) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1275 = or(_T_1253, _T_1274) @[dec_tlu_ctl.scala 3252:129]
|
|
|
|
|
node _T_1276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1277 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1279 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1280 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1281 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1282 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1283 = eq(_T_1282, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1284 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1285 = eq(_T_1284, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1286 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1287 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1288 = eq(_T_1287, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1289 = and(_T_1276, _T_1278) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1290 = and(_T_1289, _T_1279) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1291 = and(_T_1290, _T_1280) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1292 = and(_T_1291, _T_1281) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1293 = and(_T_1292, _T_1283) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1294 = and(_T_1293, _T_1285) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1295 = and(_T_1294, _T_1286) @[dec_tlu_ctl.scala 3173:198]
|
|
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node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 3173:198]
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node _T_1297 = or(_T_1275, _T_1296) @[dec_tlu_ctl.scala 3253:73]
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node _T_1298 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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node _T_1299 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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node _T_1300 = eq(_T_1299, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1301 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1302 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1303 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_1304 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1306 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_1307 = eq(_T_1306, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1308 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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node _T_1309 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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node _T_1310 = eq(_T_1309, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1311 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_1313 = and(_T_1298, _T_1300) @[dec_tlu_ctl.scala 3173:198]
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node _T_1314 = and(_T_1313, _T_1301) @[dec_tlu_ctl.scala 3173:198]
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node _T_1315 = and(_T_1314, _T_1302) @[dec_tlu_ctl.scala 3173:198]
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node _T_1316 = and(_T_1315, _T_1303) @[dec_tlu_ctl.scala 3173:198]
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node _T_1317 = and(_T_1316, _T_1305) @[dec_tlu_ctl.scala 3173:198]
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node _T_1318 = and(_T_1317, _T_1307) @[dec_tlu_ctl.scala 3173:198]
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node _T_1319 = and(_T_1318, _T_1308) @[dec_tlu_ctl.scala 3173:198]
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node _T_1320 = and(_T_1319, _T_1310) @[dec_tlu_ctl.scala 3173:198]
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node _T_1321 = and(_T_1320, _T_1312) @[dec_tlu_ctl.scala 3173:198]
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node _T_1322 = or(_T_1297, _T_1321) @[dec_tlu_ctl.scala 3253:129]
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node _T_1323 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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node _T_1324 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1326 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1327 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1328 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1330 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_1331 = eq(_T_1330, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1332 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:106]
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node _T_1333 = and(_T_1323, _T_1325) @[dec_tlu_ctl.scala 3173:198]
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node _T_1334 = and(_T_1333, _T_1326) @[dec_tlu_ctl.scala 3173:198]
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node _T_1335 = and(_T_1334, _T_1327) @[dec_tlu_ctl.scala 3173:198]
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node _T_1336 = and(_T_1335, _T_1329) @[dec_tlu_ctl.scala 3173:198]
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node _T_1337 = and(_T_1336, _T_1331) @[dec_tlu_ctl.scala 3173:198]
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node _T_1338 = and(_T_1337, _T_1332) @[dec_tlu_ctl.scala 3173:198]
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node _T_1339 = or(_T_1322, _T_1338) @[dec_tlu_ctl.scala 3254:73]
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node _T_1340 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_1341 = eq(_T_1340, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1342 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_1343 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1344 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1345 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_1346 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_1347 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1349 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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node _T_1350 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1352 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_1353 = and(_T_1341, _T_1342) @[dec_tlu_ctl.scala 3173:198]
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node _T_1354 = and(_T_1353, _T_1343) @[dec_tlu_ctl.scala 3173:198]
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node _T_1355 = and(_T_1354, _T_1344) @[dec_tlu_ctl.scala 3173:198]
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node _T_1356 = and(_T_1355, _T_1345) @[dec_tlu_ctl.scala 3173:198]
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node _T_1357 = and(_T_1356, _T_1346) @[dec_tlu_ctl.scala 3173:198]
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node _T_1358 = and(_T_1357, _T_1348) @[dec_tlu_ctl.scala 3173:198]
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node _T_1359 = and(_T_1358, _T_1349) @[dec_tlu_ctl.scala 3173:198]
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node _T_1360 = and(_T_1359, _T_1351) @[dec_tlu_ctl.scala 3173:198]
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node _T_1361 = and(_T_1360, _T_1352) @[dec_tlu_ctl.scala 3173:198]
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node _T_1362 = or(_T_1339, _T_1361) @[dec_tlu_ctl.scala 3254:129]
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node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_1373 = eq(_T_1372, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1374 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_1375 = eq(_T_1374, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 3173:198]
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node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 3173:198]
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node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 3173:198]
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node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 3173:198]
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node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 3173:198]
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node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 3173:198]
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node _T_1382 = and(_T_1381, _T_1373) @[dec_tlu_ctl.scala 3173:198]
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node _T_1383 = and(_T_1382, _T_1375) @[dec_tlu_ctl.scala 3173:198]
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node _T_1384 = or(_T_1362, _T_1383) @[dec_tlu_ctl.scala 3255:73]
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node _T_1385 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_1386 = eq(_T_1385, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1387 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_1388 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1389 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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node _T_1390 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_1391 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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node _T_1392 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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node _T_1393 = eq(_T_1392, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1394 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1396 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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node _T_1397 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1399 = and(_T_1386, _T_1387) @[dec_tlu_ctl.scala 3173:198]
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node _T_1400 = and(_T_1399, _T_1388) @[dec_tlu_ctl.scala 3173:198]
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node _T_1401 = and(_T_1400, _T_1389) @[dec_tlu_ctl.scala 3173:198]
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node _T_1402 = and(_T_1401, _T_1390) @[dec_tlu_ctl.scala 3173:198]
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node _T_1403 = and(_T_1402, _T_1391) @[dec_tlu_ctl.scala 3173:198]
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node _T_1404 = and(_T_1403, _T_1393) @[dec_tlu_ctl.scala 3173:198]
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node _T_1405 = and(_T_1404, _T_1395) @[dec_tlu_ctl.scala 3173:198]
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node _T_1406 = and(_T_1405, _T_1396) @[dec_tlu_ctl.scala 3173:198]
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node _T_1407 = and(_T_1406, _T_1398) @[dec_tlu_ctl.scala 3173:198]
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node _T_1408 = or(_T_1384, _T_1407) @[dec_tlu_ctl.scala 3255:129]
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node _T_1409 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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node _T_1410 = eq(_T_1409, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1411 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:106]
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node _T_1412 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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node _T_1413 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
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node _T_1414 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:106]
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node _T_1415 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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|
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node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
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node _T_1417 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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node _T_1418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1424 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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|
node _T_1426 = and(_T_1410, _T_1411) @[dec_tlu_ctl.scala 3173:198]
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node _T_1427 = and(_T_1426, _T_1412) @[dec_tlu_ctl.scala 3173:198]
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node _T_1428 = and(_T_1427, _T_1413) @[dec_tlu_ctl.scala 3173:198]
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node _T_1429 = and(_T_1428, _T_1414) @[dec_tlu_ctl.scala 3173:198]
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node _T_1430 = and(_T_1429, _T_1416) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_1431 = and(_T_1430, _T_1417) @[dec_tlu_ctl.scala 3173:198]
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node _T_1432 = and(_T_1431, _T_1419) @[dec_tlu_ctl.scala 3173:198]
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node _T_1433 = and(_T_1432, _T_1421) @[dec_tlu_ctl.scala 3173:198]
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node _T_1434 = and(_T_1433, _T_1423) @[dec_tlu_ctl.scala 3173:198]
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node _T_1435 = and(_T_1434, _T_1425) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_1436 = or(_T_1408, _T_1435) @[dec_tlu_ctl.scala 3256:73]
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|
|
|
node _T_1437 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1438 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1440 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1441 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_1442 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
node _T_1444 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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|
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|
|
node _T_1445 = eq(_T_1444, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
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node _T_1446 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:106]
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node _T_1447 = and(_T_1437, _T_1439) @[dec_tlu_ctl.scala 3173:198]
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node _T_1448 = and(_T_1447, _T_1440) @[dec_tlu_ctl.scala 3173:198]
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|
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node _T_1449 = and(_T_1448, _T_1441) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
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node _T_1450 = and(_T_1449, _T_1443) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_1451 = and(_T_1450, _T_1445) @[dec_tlu_ctl.scala 3173:198]
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|
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node _T_1452 = and(_T_1451, _T_1446) @[dec_tlu_ctl.scala 3173:198]
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node _T_1453 = or(_T_1436, _T_1452) @[dec_tlu_ctl.scala 3256:121]
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node _T_1454 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_1455 = eq(_T_1454, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
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node _T_1456 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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|
|
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|
node _T_1457 = eq(_T_1456, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1458 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1459 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1460 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1461 = eq(_T_1460, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1462 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1463 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1464 = eq(_T_1463, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1465 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1467 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
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node _T_1469 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 3173:149]
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node _T_1470 = eq(_T_1469, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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node _T_1471 = and(_T_1455, _T_1457) @[dec_tlu_ctl.scala 3173:198]
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node _T_1472 = and(_T_1471, _T_1458) @[dec_tlu_ctl.scala 3173:198]
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node _T_1473 = and(_T_1472, _T_1459) @[dec_tlu_ctl.scala 3173:198]
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node _T_1474 = and(_T_1473, _T_1461) @[dec_tlu_ctl.scala 3173:198]
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|
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node _T_1475 = and(_T_1474, _T_1462) @[dec_tlu_ctl.scala 3173:198]
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|
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|
node _T_1476 = and(_T_1475, _T_1464) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
node _T_1477 = and(_T_1476, _T_1466) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1478 = and(_T_1477, _T_1468) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
node _T_1479 = and(_T_1478, _T_1470) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_1480 = or(_T_1453, _T_1479) @[dec_tlu_ctl.scala 3257:81]
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|
node _T_1481 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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|
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|
node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1483 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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|
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|
node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1485 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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|
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|
node _T_1486 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1487 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1488 = eq(_T_1487, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1489 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1491 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1492 = eq(_T_1491, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1493 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1494 = eq(_T_1493, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1495 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1497 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 3173:185]
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|
|
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|
node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:165]
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|
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|
|
node _T_1499 = and(_T_1482, _T_1484) @[dec_tlu_ctl.scala 3173:198]
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node _T_1500 = and(_T_1499, _T_1485) @[dec_tlu_ctl.scala 3173:198]
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|
|
node _T_1501 = and(_T_1500, _T_1486) @[dec_tlu_ctl.scala 3173:198]
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|
node _T_1502 = and(_T_1501, _T_1488) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
|
node _T_1503 = and(_T_1502, _T_1490) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
|
node _T_1504 = and(_T_1503, _T_1492) @[dec_tlu_ctl.scala 3173:198]
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|
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|
node _T_1505 = and(_T_1504, _T_1494) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
node _T_1506 = and(_T_1505, _T_1496) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1507 = and(_T_1506, _T_1498) @[dec_tlu_ctl.scala 3173:198]
|
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|
|
|
node _T_1508 = or(_T_1480, _T_1507) @[dec_tlu_ctl.scala 3257:129]
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|
|
|
node _T_1509 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
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|
|
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|
node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1511 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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|
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|
node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1513 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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|
|
node _T_1514 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_1515 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
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|
|
node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1517 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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|
node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
node _T_1519 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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|
node _T_1520 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1521 = and(_T_1510, _T_1512) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
node _T_1522 = and(_T_1521, _T_1513) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
node _T_1523 = and(_T_1522, _T_1514) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1524 = and(_T_1523, _T_1516) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1525 = and(_T_1524, _T_1518) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1526 = and(_T_1525, _T_1519) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1527 = and(_T_1526, _T_1520) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1528 = or(_T_1508, _T_1527) @[dec_tlu_ctl.scala 3258:65]
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|
|
|
|
node _T_1529 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1530 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1531 = eq(_T_1530, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1532 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1533 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1534 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1536 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1537 = eq(_T_1536, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1538 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1539 = and(_T_1529, _T_1531) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1540 = and(_T_1539, _T_1532) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1541 = and(_T_1540, _T_1533) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1542 = and(_T_1541, _T_1535) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1543 = and(_T_1542, _T_1537) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1544 = and(_T_1543, _T_1538) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1545 = or(_T_1528, _T_1544) @[dec_tlu_ctl.scala 3258:121]
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|
|
|
|
node _T_1546 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1547 = eq(_T_1546, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1548 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1550 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1551 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1552 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1553 = eq(_T_1552, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1556 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1558 = and(_T_1547, _T_1549) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1559 = and(_T_1558, _T_1550) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1560 = and(_T_1559, _T_1551) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1561 = and(_T_1560, _T_1553) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1562 = and(_T_1561, _T_1555) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1563 = and(_T_1562, _T_1556) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1564 = and(_T_1563, _T_1557) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1565 = or(_T_1545, _T_1564) @[dec_tlu_ctl.scala 3259:81]
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|
|
|
|
node _T_1566 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1567 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1568 = eq(_T_1567, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
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|
|
|
|
node _T_1569 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1570 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 3173:106]
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|
|
|
|
node _T_1571 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 3173:149]
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|
|
|
|
node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1573 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 3173:149]
|
|
|
|
|
node _T_1574 = eq(_T_1573, UInt<1>("h00")) @[dec_tlu_ctl.scala 3173:129]
|
|
|
|
|
node _T_1575 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 3173:106]
|
|
|
|
|
node _T_1576 = and(_T_1566, _T_1568) @[dec_tlu_ctl.scala 3173:198]
|
|
|
|
|
node _T_1577 = and(_T_1576, _T_1569) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1578 = and(_T_1577, _T_1570) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
node _T_1579 = and(_T_1578, _T_1572) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1580 = and(_T_1579, _T_1574) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1581 = and(_T_1580, _T_1575) @[dec_tlu_ctl.scala 3173:198]
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|
|
|
|
node _T_1582 = or(_T_1565, _T_1581) @[dec_tlu_ctl.scala 3259:137]
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|
|
|
|
io.csr_pkt.legal <= _T_1582 @[dec_tlu_ctl.scala 3246:26]
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|
|
module dec_tlu_ctl :
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|
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input clock : Clock
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|
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|
|
input reset : AsyncReset
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output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}, flip free_clk : Clock, flip free_l2clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_second : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_tlu_core_empty : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_trace_disable : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_picio_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bit
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wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 162:67]
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wire pause_expired_wb : UInt<1>
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pause_expired_wb <= UInt<1>("h00")
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wire take_nmi_r_d1 : UInt<1>
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take_nmi_r_d1 <= UInt<1>("h00")
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wire exc_or_int_valid_r_d1 : UInt<1>
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exc_or_int_valid_r_d1 <= UInt<1>("h00")
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wire interrupt_valid_r_d1 : UInt<1>
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interrupt_valid_r_d1 <= UInt<1>("h00")
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wire tlu_flush_lower_r : UInt<1>
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tlu_flush_lower_r <= UInt<1>("h00")
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wire synchronous_flush_r : UInt<1>
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synchronous_flush_r <= UInt<1>("h00")
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wire interrupt_valid_r : UInt<1>
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interrupt_valid_r <= UInt<1>("h00")
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wire take_nmi : UInt<1>
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take_nmi <= UInt<1>("h00")
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wire take_reset : UInt<1>
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take_reset <= UInt<1>("h00")
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wire take_int_timer1_int : UInt<1>
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take_int_timer1_int <= UInt<1>("h00")
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wire take_int_timer0_int : UInt<1>
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take_int_timer0_int <= UInt<1>("h00")
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wire take_timer_int : UInt<1>
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take_timer_int <= UInt<1>("h00")
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wire take_soft_int : UInt<1>
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take_soft_int <= UInt<1>("h00")
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wire take_ce_int : UInt<1>
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take_ce_int <= UInt<1>("h00")
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wire take_ext_int_start : UInt<1>
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take_ext_int_start <= UInt<1>("h00")
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wire ext_int_freeze : UInt<1>
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ext_int_freeze <= UInt<1>("h00")
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wire take_ext_int_start_d2 : UInt<1>
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take_ext_int_start_d2 <= UInt<1>("h00")
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wire take_ext_int_start_d3 : UInt<1>
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take_ext_int_start_d3 <= UInt<1>("h00")
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wire fast_int_meicpct : UInt<1>
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fast_int_meicpct <= UInt<1>("h00")
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wire ignore_ext_int_due_to_lsu_stall : UInt<1>
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ignore_ext_int_due_to_lsu_stall <= UInt<1>("h00")
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wire take_ext_int : UInt<1>
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take_ext_int <= UInt<1>("h00")
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wire internal_dbg_halt_timers : UInt<1>
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internal_dbg_halt_timers <= UInt<1>("h00")
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wire int_timer1_int_hold : UInt<1>
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int_timer1_int_hold <= UInt<1>("h00")
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wire int_timer0_int_hold : UInt<1>
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int_timer0_int_hold <= UInt<1>("h00")
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wire mhwakeup_ready : UInt<1>
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mhwakeup_ready <= UInt<1>("h00")
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wire ext_int_ready : UInt<1>
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ext_int_ready <= UInt<1>("h00")
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wire ce_int_ready : UInt<1>
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ce_int_ready <= UInt<1>("h00")
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wire soft_int_ready : UInt<1>
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soft_int_ready <= UInt<1>("h00")
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wire timer_int_ready : UInt<1>
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timer_int_ready <= UInt<1>("h00")
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wire ebreak_to_debug_mode_r_d1 : UInt<1>
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ebreak_to_debug_mode_r_d1 <= UInt<1>("h00")
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wire ebreak_to_debug_mode_r : UInt<1>
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ebreak_to_debug_mode_r <= UInt<1>("h00")
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wire inst_acc_r : UInt<1>
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inst_acc_r <= UInt<1>("h00")
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wire inst_acc_r_raw : UInt<1>
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inst_acc_r_raw <= UInt<1>("h00")
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wire iccm_sbecc_r : UInt<1>
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iccm_sbecc_r <= UInt<1>("h00")
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wire ic_perr_r : UInt<1>
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ic_perr_r <= UInt<1>("h00")
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wire fence_i_r : UInt<1>
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fence_i_r <= UInt<1>("h00")
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wire ebreak_r : UInt<1>
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ebreak_r <= UInt<1>("h00")
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wire ecall_r : UInt<1>
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ecall_r <= UInt<1>("h00")
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wire illegal_r : UInt<1>
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illegal_r <= UInt<1>("h00")
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wire mret_r : UInt<1>
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mret_r <= UInt<1>("h00")
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wire iccm_repair_state_ns : UInt<1>
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iccm_repair_state_ns <= UInt<1>("h00")
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wire rfpc_i0_r : UInt<1>
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rfpc_i0_r <= UInt<1>("h00")
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wire tlu_i0_kill_writeb_r : UInt<1>
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tlu_i0_kill_writeb_r <= UInt<1>("h00")
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wire lsu_exc_valid_r_d1 : UInt<1>
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lsu_exc_valid_r_d1 <= UInt<1>("h00")
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wire lsu_i0_exc_r_raw : UInt<1>
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lsu_i0_exc_r_raw <= UInt<1>("h00")
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wire mdseac_locked_f : UInt<1>
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mdseac_locked_f <= UInt<1>("h00")
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wire i_cpu_run_req_d1 : UInt<1>
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i_cpu_run_req_d1 <= UInt<1>("h00")
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wire cpu_run_ack : UInt<1>
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cpu_run_ack <= UInt<1>("h00")
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wire cpu_halt_status : UInt<1>
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cpu_halt_status <= UInt<1>("h00")
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wire cpu_halt_ack : UInt<1>
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cpu_halt_ack <= UInt<1>("h00")
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wire pmu_fw_tlu_halted : UInt<1>
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pmu_fw_tlu_halted <= UInt<1>("h00")
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wire internal_pmu_fw_halt_mode : UInt<1>
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internal_pmu_fw_halt_mode <= UInt<1>("h00")
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wire pmu_fw_halt_req_ns : UInt<1>
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pmu_fw_halt_req_ns <= UInt<1>("h00")
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wire pmu_fw_halt_req_f : UInt<1>
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pmu_fw_halt_req_f <= UInt<1>("h00")
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wire pmu_fw_tlu_halted_f : UInt<1>
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pmu_fw_tlu_halted_f <= UInt<1>("h00")
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wire int_timer0_int_hold_f : UInt<1>
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int_timer0_int_hold_f <= UInt<1>("h00")
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wire int_timer1_int_hold_f : UInt<1>
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int_timer1_int_hold_f <= UInt<1>("h00")
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wire trigger_hit_dmode_r : UInt<1>
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trigger_hit_dmode_r <= UInt<1>("h00")
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wire i0_trigger_hit_r : UInt<1>
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i0_trigger_hit_r <= UInt<1>("h00")
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wire pause_expired_r : UInt<1>
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pause_expired_r <= UInt<1>("h00")
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wire dec_tlu_pmu_fw_halted : UInt<1>
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dec_tlu_pmu_fw_halted <= UInt<1>("h00")
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wire dec_tlu_flush_noredir_r_d1 : UInt<1>
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dec_tlu_flush_noredir_r_d1 <= UInt<1>("h00")
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wire halt_taken_f : UInt<1>
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halt_taken_f <= UInt<1>("h00")
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wire lsu_idle_any_f : UInt<1>
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lsu_idle_any_f <= UInt<1>("h00")
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wire ifu_miss_state_idle_f : UInt<1>
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ifu_miss_state_idle_f <= UInt<1>("h00")
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wire dbg_tlu_halted_f : UInt<1>
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dbg_tlu_halted_f <= UInt<1>("h00")
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wire debug_halt_req_f : UInt<1>
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debug_halt_req_f <= UInt<1>("h00")
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wire debug_resume_req_f_raw : UInt<1>
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debug_resume_req_f_raw <= UInt<1>("h00")
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wire debug_resume_req_f : UInt<1>
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debug_resume_req_f <= UInt<1>("h00")
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wire trigger_hit_dmode_r_d1 : UInt<1>
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trigger_hit_dmode_r_d1 <= UInt<1>("h00")
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wire dcsr_single_step_done_f : UInt<1>
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dcsr_single_step_done_f <= UInt<1>("h00")
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wire debug_halt_req_d1 : UInt<1>
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debug_halt_req_d1 <= UInt<1>("h00")
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wire request_debug_mode_r_d1 : UInt<1>
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request_debug_mode_r_d1 <= UInt<1>("h00")
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wire request_debug_mode_done_f : UInt<1>
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request_debug_mode_done_f <= UInt<1>("h00")
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wire dcsr_single_step_running_f : UInt<1>
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dcsr_single_step_running_f <= UInt<1>("h00")
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wire dec_tlu_flush_pause_r_d1 : UInt<1>
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dec_tlu_flush_pause_r_d1 <= UInt<1>("h00")
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wire dbg_halt_req_held : UInt<1>
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dbg_halt_req_held <= UInt<1>("h00")
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wire debug_halt_req_ns : UInt<1>
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debug_halt_req_ns <= UInt<1>("h00")
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wire internal_dbg_halt_mode : UInt<1>
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internal_dbg_halt_mode <= UInt<1>("h00")
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wire core_empty : UInt<1>
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core_empty <= UInt<1>("h00")
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wire dbg_halt_req_final : UInt<1>
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dbg_halt_req_final <= UInt<1>("h00")
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wire debug_brkpt_status_ns : UInt<1>
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debug_brkpt_status_ns <= UInt<1>("h00")
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wire mpc_debug_halt_ack_ns : UInt<1>
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mpc_debug_halt_ack_ns <= UInt<1>("h00")
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wire mpc_debug_run_ack_ns : UInt<1>
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mpc_debug_run_ack_ns <= UInt<1>("h00")
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wire mpc_halt_state_ns : UInt<1>
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mpc_halt_state_ns <= UInt<1>("h00")
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wire mpc_run_state_ns : UInt<1>
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mpc_run_state_ns <= UInt<1>("h00")
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wire dbg_halt_state_ns : UInt<1>
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dbg_halt_state_ns <= UInt<1>("h00")
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wire dbg_run_state_ns : UInt<1>
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dbg_run_state_ns <= UInt<1>("h00")
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wire dbg_halt_state_f : UInt<1>
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dbg_halt_state_f <= UInt<1>("h00")
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wire mpc_halt_state_f : UInt<1>
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mpc_halt_state_f <= UInt<1>("h00")
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wire nmi_int_detected : UInt<1>
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nmi_int_detected <= UInt<1>("h00")
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wire nmi_lsu_load_type : UInt<1>
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nmi_lsu_load_type <= UInt<1>("h00")
|
|
|
|
|
wire nmi_lsu_store_type : UInt<1>
|
|
|
|
|
nmi_lsu_store_type <= UInt<1>("h00")
|
|
|
|
|
wire reset_delayed : UInt<1>
|
|
|
|
|
reset_delayed <= UInt<1>("h00")
|
|
|
|
|
wire debug_mode_status : UInt<1>
|
|
|
|
|
debug_mode_status <= UInt<1>("h00")
|
|
|
|
|
wire e5_valid : UInt<1>
|
|
|
|
|
e5_valid <= UInt<1>("h00")
|
|
|
|
|
wire ic_perr_r_d1 : UInt<1>
|
|
|
|
|
ic_perr_r_d1 <= UInt<1>("h00")
|
|
|
|
|
wire iccm_sbecc_r_d1 : UInt<1>
|
|
|
|
|
iccm_sbecc_r_d1 <= UInt<1>("h00")
|
|
|
|
|
wire npc_r : UInt<31>
|
|
|
|
|
npc_r <= UInt<1>("h00")
|
|
|
|
|
wire npc_r_d1 : UInt<31>
|
|
|
|
|
npc_r_d1 <= UInt<1>("h00")
|
|
|
|
|
wire mie_ns : UInt<6>
|
|
|
|
|
mie_ns <= UInt<1>("h00")
|
|
|
|
|
wire mepc : UInt<31>
|
|
|
|
|
mepc <= UInt<1>("h00")
|
|
|
|
|
wire mdseac_locked_ns : UInt<1>
|
|
|
|
|
mdseac_locked_ns <= UInt<1>("h00")
|
|
|
|
|
wire force_halt : UInt<1>
|
|
|
|
|
force_halt <= UInt<1>("h00")
|
|
|
|
|
wire dpc : UInt<31>
|
|
|
|
|
dpc <= UInt<1>("h00")
|
|
|
|
|
wire mstatus_mie_ns : UInt<1>
|
|
|
|
|
mstatus_mie_ns <= UInt<1>("h00")
|
|
|
|
|
wire dec_csr_wen_r_mod : UInt<1>
|
|
|
|
|
dec_csr_wen_r_mod <= UInt<1>("h00")
|
|
|
|
|
wire fw_halt_req : UInt<1>
|
|
|
|
|
fw_halt_req <= UInt<1>("h00")
|
|
|
|
|
wire mstatus : UInt<2>
|
|
|
|
|
mstatus <= UInt<1>("h00")
|
|
|
|
|
wire dcsr : UInt<16>
|
|
|
|
|
dcsr <= UInt<1>("h00")
|
|
|
|
|
wire mtvec : UInt<31>
|
|
|
|
|
mtvec <= UInt<1>("h00")
|
|
|
|
|
wire mip : UInt<6>
|
|
|
|
|
mip <= UInt<1>("h00")
|
|
|
|
|
wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_meicpct : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 278:47]
|
|
|
|
|
wire dec_tlu_mpc_halted_only_ns : UInt<1>
|
|
|
|
|
dec_tlu_mpc_halted_only_ns <= UInt<1>("h00")
|
|
|
|
|
node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 281:39]
|
|
|
|
|
node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 281:57]
|
|
|
|
|
dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 281:36]
|
|
|
|
|
inst int_exc of int_exc @[dec_tlu_ctl.scala 282:29]
|
|
|
|
|
int_exc.clock <= clock
|
|
|
|
|
int_exc.reset <= reset
|
|
|
|
|
inst csr of csr_tlu @[dec_tlu_ctl.scala 283:23]
|
|
|
|
|
csr.clock <= clock
|
|
|
|
|
csr.reset <= reset
|
|
|
|
|
inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 284:30]
|
|
|
|
|
int_timers.clock <= clock
|
|
|
|
|
int_timers.reset <= reset
|
|
|
|
|
int_timers.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 285:65]
|
|
|
|
|
int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 286:57]
|
|
|
|
|
int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 287:49]
|
|
|
|
|
int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 289:49]
|
|
|
|
|
int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 290:49]
|
|
|
|
|
int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 291:57]
|
|
|
|
|
int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 292:57]
|
|
|
|
|
int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 293:57]
|
|
|
|
|
int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 294:57]
|
|
|
|
|
int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 295:57]
|
|
|
|
|
int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 296:57]
|
|
|
|
|
int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 297:49]
|
|
|
|
|
int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 298:49]
|
|
|
|
|
int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 299:47]
|
|
|
|
|
node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58]
|
|
|
|
|
node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58]
|
|
|
|
|
node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58]
|
|
|
|
|
node _T_5 = cat(io.nmi_int, io.timer_int) @[Cat.scala 29:58]
|
|
|
|
|
node _T_6 = cat(_T_5, _T_4) @[Cat.scala 29:58]
|
|
|
|
|
node _T_7 = cat(_T_6, _T_3) @[Cat.scala 29:58]
|
|
|
|
|
reg _T_8 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:81]
|
|
|
|
|
_T_8 <= _T_7 @[lib.scala 37:81]
|
|
|
|
|
reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:58]
|
|
|
|
|
syncro_ff <= _T_8 @[lib.scala 37:58]
|
|
|
|
|
node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 311:75]
|
|
|
|
|
node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 312:67]
|
|
|
|
|
node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 313:67]
|
|
|
|
|
node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 314:59]
|
|
|
|
|
node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 315:59]
|
|
|
|
|
node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 316:51]
|
|
|
|
|
node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 317:59]
|
|
|
|
|
node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 320:59]
|
|
|
|
|
node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 320:75]
|
|
|
|
|
int_timers.io.csr_wr_clk <= clock @[dec_tlu_ctl.scala 321:52]
|
|
|
|
|
node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 325:35]
|
|
|
|
|
node _T_11 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 326:55]
|
|
|
|
|
node _T_12 = or(_T_11, interrupt_valid_r) @[dec_tlu_ctl.scala 326:74]
|
|
|
|
|
node _T_13 = or(_T_12, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 326:94]
|
|
|
|
|
node _T_14 = or(_T_13, reset_delayed) @[dec_tlu_ctl.scala 326:117]
|
|
|
|
|
node _T_15 = or(_T_14, pause_expired_r) @[dec_tlu_ctl.scala 326:133]
|
|
|
|
|
node _T_16 = or(_T_15, pause_expired_wb) @[dec_tlu_ctl.scala 326:151]
|
|
|
|
|
node _T_17 = or(_T_16, ic_perr_r) @[dec_tlu_ctl.scala 326:170]
|
|
|
|
|
node _T_18 = or(_T_17, iccm_sbecc_r) @[dec_tlu_ctl.scala 326:183]
|
|
|
|
|
node flush_clkvalid = or(_T_18, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 326:199]
|
|
|
|
|
node _T_19 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 329:50]
|
|
|
|
|
node _T_20 = bits(_T_19, 0, 0) @[dec_tlu_ctl.scala 329:66]
|
|
|
|
|
node _T_21 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 330:54]
|
|
|
|
|
node _T_22 = bits(_T_21, 0, 0) @[dec_tlu_ctl.scala 330:72]
|
|
|
|
|
wire ifu_ic_error_start_f : UInt<1>
|
|
|
|
|
ifu_ic_error_start_f <= UInt<1>("h00")
|
|
|
|
|
node _T_23 = xor(io.tlu_mem.ifu_ic_error_start, ifu_ic_error_start_f) @[lib.scala 470:21]
|
|
|
|
|
node _T_24 = orr(_T_23) @[lib.scala 470:29]
|
|
|
|
|
reg _T_25 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_24 : @[Reg.scala 28:19]
|
|
|
|
|
_T_25 <= io.tlu_mem.ifu_ic_error_start @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
ifu_ic_error_start_f <= _T_25 @[lib.scala 473:16]
|
|
|
|
|
wire ifu_iccm_rd_ecc_single_err_f : UInt<1>
|
|
|
|
|
ifu_iccm_rd_ecc_single_err_f <= UInt<1>("h00")
|
|
|
|
|
node _T_26 = xor(io.tlu_mem.ifu_iccm_rd_ecc_single_err, ifu_iccm_rd_ecc_single_err_f) @[lib.scala 470:21]
|
|
|
|
|
node _T_27 = orr(_T_26) @[lib.scala 470:29]
|
|
|
|
|
reg _T_28 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_27 : @[Reg.scala 28:19]
|
|
|
|
|
_T_28 <= io.tlu_mem.ifu_iccm_rd_ecc_single_err @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
ifu_iccm_rd_ecc_single_err_f <= _T_28 @[lib.scala 473:16]
|
|
|
|
|
wire iccm_repair_state_d1 : UInt
|
|
|
|
|
iccm_repair_state_d1 <= UInt<1>("h00")
|
|
|
|
|
node _T_29 = xor(iccm_repair_state_ns, iccm_repair_state_d1) @[lib.scala 448:21]
|
|
|
|
|
node _T_30 = orr(_T_29) @[lib.scala 448:29]
|
|
|
|
|
reg _T_31 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_30 : @[Reg.scala 28:19]
|
|
|
|
|
_T_31 <= iccm_repair_state_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
iccm_repair_state_d1 <= _T_31 @[lib.scala 451:16]
|
|
|
|
|
wire _T_32 : UInt
|
|
|
|
|
_T_32 <= UInt<1>("h00")
|
|
|
|
|
node _T_33 = xor(io.dec_tlu_i0_valid_r, _T_32) @[lib.scala 448:21]
|
|
|
|
|
node _T_34 = orr(_T_33) @[lib.scala 448:29]
|
|
|
|
|
reg _T_35 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_34 : @[Reg.scala 28:19]
|
|
|
|
|
_T_35 <= io.dec_tlu_i0_valid_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_32 <= _T_35 @[lib.scala 451:16]
|
|
|
|
|
e5_valid <= _T_32 @[dec_tlu_ctl.scala 338:75]
|
|
|
|
|
wire _T_36 : UInt
|
|
|
|
|
_T_36 <= UInt<1>("h00")
|
|
|
|
|
node _T_37 = xor(internal_dbg_halt_mode, _T_36) @[lib.scala 448:21]
|
|
|
|
|
node _T_38 = orr(_T_37) @[lib.scala 448:29]
|
|
|
|
|
reg _T_39 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_38 : @[Reg.scala 28:19]
|
|
|
|
|
_T_39 <= internal_dbg_halt_mode @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_36 <= _T_39 @[lib.scala 451:16]
|
|
|
|
|
debug_mode_status <= _T_36 @[dec_tlu_ctl.scala 339:51]
|
|
|
|
|
wire lsu_pmu_load_external_r : UInt<1>
|
|
|
|
|
lsu_pmu_load_external_r <= UInt<1>("h00")
|
|
|
|
|
node _T_40 = xor(io.lsu_tlu.lsu_pmu_load_external_m, lsu_pmu_load_external_r) @[lib.scala 470:21]
|
|
|
|
|
node _T_41 = orr(_T_40) @[lib.scala 470:29]
|
|
|
|
|
reg _T_42 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_41 : @[Reg.scala 28:19]
|
|
|
|
|
_T_42 <= io.lsu_tlu.lsu_pmu_load_external_m @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
lsu_pmu_load_external_r <= _T_42 @[lib.scala 473:16]
|
|
|
|
|
wire lsu_pmu_store_external_r : UInt<1>
|
|
|
|
|
lsu_pmu_store_external_r <= UInt<1>("h00")
|
|
|
|
|
node _T_43 = xor(io.lsu_tlu.lsu_pmu_store_external_m, lsu_pmu_store_external_r) @[lib.scala 470:21]
|
|
|
|
|
node _T_44 = orr(_T_43) @[lib.scala 470:29]
|
|
|
|
|
reg _T_45 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_44 : @[Reg.scala 28:19]
|
|
|
|
|
_T_45 <= io.lsu_tlu.lsu_pmu_store_external_m @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
lsu_pmu_store_external_r <= _T_45 @[lib.scala 473:16]
|
|
|
|
|
wire tlu_flush_lower_r_d1 : UInt
|
|
|
|
|
tlu_flush_lower_r_d1 <= UInt<1>("h00")
|
|
|
|
|
node _T_46 = xor(tlu_flush_lower_r, tlu_flush_lower_r_d1) @[lib.scala 448:21]
|
|
|
|
|
node _T_47 = orr(_T_46) @[lib.scala 448:29]
|
|
|
|
|
reg _T_48 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_47 : @[Reg.scala 28:19]
|
|
|
|
|
_T_48 <= tlu_flush_lower_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
tlu_flush_lower_r_d1 <= _T_48 @[lib.scala 451:16]
|
|
|
|
|
wire _T_49 : UInt
|
|
|
|
|
_T_49 <= UInt<1>("h00")
|
|
|
|
|
node _T_50 = xor(tlu_i0_kill_writeb_r, _T_49) @[lib.scala 448:21]
|
|
|
|
|
node _T_51 = orr(_T_50) @[lib.scala 448:29]
|
|
|
|
|
reg _T_52 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_51 : @[Reg.scala 28:19]
|
|
|
|
|
_T_52 <= tlu_i0_kill_writeb_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_49 <= _T_52 @[lib.scala 451:16]
|
|
|
|
|
io.dec_tlu_i0_kill_writeb_wb <= _T_49 @[dec_tlu_ctl.scala 343:41]
|
|
|
|
|
wire internal_dbg_halt_mode_f2 : UInt
|
|
|
|
|
internal_dbg_halt_mode_f2 <= UInt<1>("h00")
|
|
|
|
|
node _T_53 = xor(debug_mode_status, internal_dbg_halt_mode_f2) @[lib.scala 448:21]
|
|
|
|
|
node _T_54 = orr(_T_53) @[lib.scala 448:29]
|
|
|
|
|
reg _T_55 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_54 : @[Reg.scala 28:19]
|
|
|
|
|
_T_55 <= debug_mode_status @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
internal_dbg_halt_mode_f2 <= _T_55 @[lib.scala 451:16]
|
|
|
|
|
wire _T_56 : UInt
|
|
|
|
|
_T_56 <= UInt<1>("h00")
|
|
|
|
|
node _T_57 = xor(force_halt, _T_56) @[lib.scala 448:21]
|
|
|
|
|
node _T_58 = orr(_T_57) @[lib.scala 448:29]
|
|
|
|
|
reg _T_59 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_58 : @[Reg.scala 28:19]
|
|
|
|
|
_T_59 <= force_halt @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_56 <= _T_59 @[lib.scala 451:16]
|
|
|
|
|
io.tlu_mem.dec_tlu_force_halt <= _T_56 @[dec_tlu_ctl.scala 345:41]
|
|
|
|
|
io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 349:41]
|
|
|
|
|
wire nmi_int_delayed : UInt<1>
|
|
|
|
|
nmi_int_delayed <= UInt<1>("h00")
|
|
|
|
|
node _T_60 = xor(nmi_int_sync, nmi_int_delayed) @[lib.scala 470:21]
|
|
|
|
|
node _T_61 = orr(_T_60) @[lib.scala 470:29]
|
|
|
|
|
reg _T_62 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_61 : @[Reg.scala 28:19]
|
|
|
|
|
_T_62 <= nmi_int_sync @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
nmi_int_delayed <= _T_62 @[lib.scala 473:16]
|
|
|
|
|
wire nmi_int_detected_f : UInt
|
|
|
|
|
nmi_int_detected_f <= UInt<1>("h00")
|
|
|
|
|
node _T_63 = xor(nmi_int_detected, nmi_int_detected_f) @[lib.scala 448:21]
|
|
|
|
|
node _T_64 = orr(_T_63) @[lib.scala 448:29]
|
|
|
|
|
reg _T_65 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_64 : @[Reg.scala 28:19]
|
|
|
|
|
_T_65 <= nmi_int_detected @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
nmi_int_detected_f <= _T_65 @[lib.scala 451:16]
|
|
|
|
|
wire nmi_lsu_load_type_f : UInt
|
|
|
|
|
nmi_lsu_load_type_f <= UInt<1>("h00")
|
|
|
|
|
node _T_66 = xor(nmi_lsu_load_type, nmi_lsu_load_type_f) @[lib.scala 448:21]
|
|
|
|
|
node _T_67 = orr(_T_66) @[lib.scala 448:29]
|
|
|
|
|
reg _T_68 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_67 : @[Reg.scala 28:19]
|
|
|
|
|
_T_68 <= nmi_lsu_load_type @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
nmi_lsu_load_type_f <= _T_68 @[lib.scala 451:16]
|
|
|
|
|
wire nmi_lsu_store_type_f : UInt
|
|
|
|
|
nmi_lsu_store_type_f <= UInt<1>("h00")
|
|
|
|
|
node _T_69 = xor(nmi_lsu_store_type, nmi_lsu_store_type_f) @[lib.scala 448:21]
|
|
|
|
|
node _T_70 = orr(_T_69) @[lib.scala 448:29]
|
|
|
|
|
reg _T_71 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_70 : @[Reg.scala 28:19]
|
|
|
|
|
_T_71 <= nmi_lsu_store_type @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
nmi_lsu_store_type_f <= _T_71 @[lib.scala 451:16]
|
|
|
|
|
wire nmi_fir_type : UInt<1>
|
|
|
|
|
nmi_fir_type <= UInt<1>("h00")
|
|
|
|
|
node _T_72 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 357:32]
|
|
|
|
|
node _T_73 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 357:96]
|
|
|
|
|
node _T_74 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 357:49]
|
|
|
|
|
node _T_75 = not(nmi_fir_type) @[dec_tlu_ctl.scala 357:146]
|
|
|
|
|
node nmi_lsu_detected = and(_T_74, _T_75) @[dec_tlu_ctl.scala 357:144]
|
|
|
|
|
node _T_76 = not(nmi_int_delayed) @[dec_tlu_ctl.scala 360:45]
|
|
|
|
|
node _T_77 = and(nmi_int_sync, _T_76) @[dec_tlu_ctl.scala 360:43]
|
|
|
|
|
node _T_78 = or(_T_77, nmi_lsu_detected) @[dec_tlu_ctl.scala 360:63]
|
|
|
|
|
node _T_79 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 360:106]
|
|
|
|
|
node _T_80 = and(nmi_int_detected_f, _T_79) @[dec_tlu_ctl.scala 360:104]
|
|
|
|
|
node _T_81 = or(_T_78, _T_80) @[dec_tlu_ctl.scala 360:82]
|
|
|
|
|
node _T_82 = or(_T_81, nmi_fir_type) @[dec_tlu_ctl.scala 360:122]
|
|
|
|
|
nmi_int_detected <= _T_82 @[dec_tlu_ctl.scala 360:26]
|
|
|
|
|
node _T_83 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 362:49]
|
|
|
|
|
node _T_84 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 362:121]
|
|
|
|
|
node _T_85 = and(nmi_int_detected_f, _T_84) @[dec_tlu_ctl.scala 362:119]
|
|
|
|
|
node _T_86 = not(_T_85) @[dec_tlu_ctl.scala 362:98]
|
|
|
|
|
node _T_87 = and(_T_83, _T_86) @[dec_tlu_ctl.scala 362:95]
|
|
|
|
|
node _T_88 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 362:164]
|
|
|
|
|
node _T_89 = and(nmi_lsu_load_type_f, _T_88) @[dec_tlu_ctl.scala 362:162]
|
|
|
|
|
node _T_90 = or(_T_87, _T_89) @[dec_tlu_ctl.scala 362:138]
|
|
|
|
|
nmi_lsu_load_type <= _T_90 @[dec_tlu_ctl.scala 362:28]
|
|
|
|
|
node _T_91 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 363:49]
|
|
|
|
|
node _T_92 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 363:121]
|
|
|
|
|
node _T_93 = and(nmi_int_detected_f, _T_92) @[dec_tlu_ctl.scala 363:119]
|
|
|
|
|
node _T_94 = not(_T_93) @[dec_tlu_ctl.scala 363:98]
|
|
|
|
|
node _T_95 = and(_T_91, _T_94) @[dec_tlu_ctl.scala 363:96]
|
|
|
|
|
node _T_96 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 363:164]
|
|
|
|
|
node _T_97 = and(nmi_lsu_store_type_f, _T_96) @[dec_tlu_ctl.scala 363:162]
|
|
|
|
|
node _T_98 = or(_T_95, _T_97) @[dec_tlu_ctl.scala 363:138]
|
|
|
|
|
nmi_lsu_store_type <= _T_98 @[dec_tlu_ctl.scala 363:28]
|
|
|
|
|
node _T_99 = not(nmi_int_detected_f) @[dec_tlu_ctl.scala 365:25]
|
|
|
|
|
node _T_100 = and(_T_99, csr.io.take_ext_int_start_d3) @[dec_tlu_ctl.scala 365:45]
|
|
|
|
|
node _T_101 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 365:95]
|
|
|
|
|
node _T_102 = and(_T_100, _T_101) @[dec_tlu_ctl.scala 365:76]
|
|
|
|
|
nmi_fir_type <= _T_102 @[dec_tlu_ctl.scala 365:22]
|
|
|
|
|
wire reset_detect : UInt
|
|
|
|
|
reset_detect <= UInt<1>("h00")
|
|
|
|
|
node _T_103 = xor(UInt<1>("h01"), reset_detect) @[lib.scala 448:21]
|
|
|
|
|
node _T_104 = orr(_T_103) @[lib.scala 448:29]
|
|
|
|
|
reg _T_105 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_104 : @[Reg.scala 28:19]
|
|
|
|
|
_T_105 <= UInt<1>("h01") @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
reset_detect <= _T_105 @[lib.scala 451:16]
|
|
|
|
|
wire reset_detected : UInt
|
|
|
|
|
reset_detected <= UInt<1>("h00")
|
|
|
|
|
node _T_106 = xor(reset_detect, reset_detected) @[lib.scala 448:21]
|
|
|
|
|
node _T_107 = orr(_T_106) @[lib.scala 448:29]
|
|
|
|
|
reg _T_108 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_107 : @[Reg.scala 28:19]
|
|
|
|
|
_T_108 <= reset_detect @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
reset_detected <= _T_108 @[lib.scala 451:16]
|
|
|
|
|
node _T_109 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 369:64]
|
|
|
|
|
reset_delayed <= _T_109 @[dec_tlu_ctl.scala 369:49]
|
|
|
|
|
node _T_110 = eq(csr.io.ext_int_freeze_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 376:69]
|
|
|
|
|
node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_110) @[dec_tlu_ctl.scala 376:67]
|
|
|
|
|
wire mpc_debug_halt_req_sync_f : UInt<1>
|
|
|
|
|
mpc_debug_halt_req_sync_f <= UInt<1>("h00")
|
|
|
|
|
node _T_111 = xor(mpc_debug_halt_req_sync, mpc_debug_halt_req_sync_f) @[lib.scala 470:21]
|
|
|
|
|
node _T_112 = orr(_T_111) @[lib.scala 470:29]
|
|
|
|
|
reg _T_113 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_112 : @[Reg.scala 28:19]
|
|
|
|
|
_T_113 <= mpc_debug_halt_req_sync @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mpc_debug_halt_req_sync_f <= _T_113 @[lib.scala 473:16]
|
|
|
|
|
wire mpc_debug_run_req_sync_f : UInt<1>
|
|
|
|
|
mpc_debug_run_req_sync_f <= UInt<1>("h00")
|
|
|
|
|
node _T_114 = xor(mpc_debug_run_req_sync, mpc_debug_run_req_sync_f) @[lib.scala 470:21]
|
|
|
|
|
node _T_115 = orr(_T_114) @[lib.scala 470:29]
|
|
|
|
|
reg _T_116 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_115 : @[Reg.scala 28:19]
|
|
|
|
|
_T_116 <= mpc_debug_run_req_sync @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mpc_debug_run_req_sync_f <= _T_116 @[lib.scala 473:16]
|
|
|
|
|
wire _T_117 : UInt
|
|
|
|
|
_T_117 <= UInt<1>("h00")
|
|
|
|
|
node _T_118 = xor(mpc_halt_state_ns, _T_117) @[lib.scala 448:21]
|
|
|
|
|
node _T_119 = orr(_T_118) @[lib.scala 448:29]
|
|
|
|
|
reg _T_120 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_119 : @[Reg.scala 28:19]
|
|
|
|
|
_T_120 <= mpc_halt_state_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_117 <= _T_120 @[lib.scala 451:16]
|
|
|
|
|
mpc_halt_state_f <= _T_117 @[dec_tlu_ctl.scala 379:62]
|
|
|
|
|
wire mpc_run_state_f : UInt
|
|
|
|
|
mpc_run_state_f <= UInt<1>("h00")
|
|
|
|
|
node _T_121 = xor(mpc_run_state_ns, mpc_run_state_f) @[lib.scala 448:21]
|
|
|
|
|
node _T_122 = orr(_T_121) @[lib.scala 448:29]
|
|
|
|
|
reg _T_123 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_122 : @[Reg.scala 28:19]
|
|
|
|
|
_T_123 <= mpc_run_state_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mpc_run_state_f <= _T_123 @[lib.scala 451:16]
|
|
|
|
|
wire debug_brkpt_status_f : UInt
|
|
|
|
|
debug_brkpt_status_f <= UInt<1>("h00")
|
|
|
|
|
node _T_124 = xor(debug_brkpt_status_ns, debug_brkpt_status_f) @[lib.scala 448:21]
|
|
|
|
|
node _T_125 = orr(_T_124) @[lib.scala 448:29]
|
|
|
|
|
reg _T_126 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_125 : @[Reg.scala 28:19]
|
|
|
|
|
_T_126 <= debug_brkpt_status_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
debug_brkpt_status_f <= _T_126 @[lib.scala 451:16]
|
|
|
|
|
wire mpc_debug_halt_ack_f : UInt
|
|
|
|
|
mpc_debug_halt_ack_f <= UInt<1>("h00")
|
|
|
|
|
node _T_127 = xor(mpc_debug_halt_ack_ns, mpc_debug_halt_ack_f) @[lib.scala 448:21]
|
|
|
|
|
node _T_128 = orr(_T_127) @[lib.scala 448:29]
|
|
|
|
|
reg _T_129 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_128 : @[Reg.scala 28:19]
|
|
|
|
|
_T_129 <= mpc_debug_halt_ack_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mpc_debug_halt_ack_f <= _T_129 @[lib.scala 451:16]
|
|
|
|
|
wire mpc_debug_run_ack_f : UInt
|
|
|
|
|
mpc_debug_run_ack_f <= UInt<1>("h00")
|
|
|
|
|
node _T_130 = xor(mpc_debug_run_ack_ns, mpc_debug_run_ack_f) @[lib.scala 448:21]
|
|
|
|
|
node _T_131 = orr(_T_130) @[lib.scala 448:29]
|
|
|
|
|
reg _T_132 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_131 : @[Reg.scala 28:19]
|
|
|
|
|
_T_132 <= mpc_debug_run_ack_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
mpc_debug_run_ack_f <= _T_132 @[lib.scala 451:16]
|
|
|
|
|
wire _T_133 : UInt
|
|
|
|
|
_T_133 <= UInt<1>("h00")
|
|
|
|
|
node _T_134 = xor(dbg_halt_state_ns, _T_133) @[lib.scala 448:21]
|
|
|
|
|
node _T_135 = orr(_T_134) @[lib.scala 448:29]
|
|
|
|
|
reg _T_136 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_135 : @[Reg.scala 28:19]
|
|
|
|
|
_T_136 <= dbg_halt_state_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_133 <= _T_136 @[lib.scala 451:16]
|
|
|
|
|
dbg_halt_state_f <= _T_133 @[dec_tlu_ctl.scala 384:62]
|
|
|
|
|
wire dbg_run_state_f : UInt
|
|
|
|
|
dbg_run_state_f <= UInt<1>("h00")
|
|
|
|
|
node _T_137 = xor(dbg_run_state_ns, dbg_run_state_f) @[lib.scala 448:21]
|
|
|
|
|
node _T_138 = orr(_T_137) @[lib.scala 448:29]
|
|
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|
|
reg _T_139 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_138 : @[Reg.scala 28:19]
|
|
|
|
|
_T_139 <= dbg_run_state_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
dbg_run_state_f <= _T_139 @[lib.scala 451:16]
|
|
|
|
|
wire _T_140 : UInt
|
|
|
|
|
_T_140 <= UInt<1>("h00")
|
|
|
|
|
node _T_141 = xor(dec_tlu_mpc_halted_only_ns, _T_140) @[lib.scala 448:21]
|
|
|
|
|
node _T_142 = orr(_T_141) @[lib.scala 448:29]
|
|
|
|
|
reg _T_143 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_142 : @[Reg.scala 28:19]
|
|
|
|
|
_T_143 <= dec_tlu_mpc_halted_only_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_140 <= _T_143 @[lib.scala 451:16]
|
|
|
|
|
io.dec_tlu_mpc_halted_only <= _T_140 @[dec_tlu_ctl.scala 386:42]
|
|
|
|
|
node _T_144 = not(mpc_debug_halt_req_sync_f) @[dec_tlu_ctl.scala 390:71]
|
|
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|
|
node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_144) @[dec_tlu_ctl.scala 390:69]
|
|
|
|
|
node _T_145 = not(mpc_debug_run_req_sync_f) @[dec_tlu_ctl.scala 391:70]
|
|
|
|
|
node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_145) @[dec_tlu_ctl.scala 391:68]
|
|
|
|
|
node _T_146 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[dec_tlu_ctl.scala 393:48]
|
|
|
|
|
node _T_147 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 393:99]
|
|
|
|
|
node _T_148 = and(reset_delayed, _T_147) @[dec_tlu_ctl.scala 393:97]
|
|
|
|
|
node _T_149 = or(_T_146, _T_148) @[dec_tlu_ctl.scala 393:80]
|
|
|
|
|
node _T_150 = not(mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 393:125]
|
|
|
|
|
node _T_151 = and(_T_149, _T_150) @[dec_tlu_ctl.scala 393:123]
|
|
|
|
|
mpc_halt_state_ns <= _T_151 @[dec_tlu_ctl.scala 393:27]
|
|
|
|
|
node _T_152 = not(mpc_debug_run_ack_f) @[dec_tlu_ctl.scala 394:80]
|
|
|
|
|
node _T_153 = and(mpc_debug_run_req_sync_pulse, _T_152) @[dec_tlu_ctl.scala 394:78]
|
|
|
|
|
node _T_154 = or(mpc_run_state_f, _T_153) @[dec_tlu_ctl.scala 394:46]
|
|
|
|
|
node _T_155 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 394:133]
|
|
|
|
|
node _T_156 = and(debug_mode_status, _T_155) @[dec_tlu_ctl.scala 394:131]
|
|
|
|
|
node _T_157 = and(_T_154, _T_156) @[dec_tlu_ctl.scala 394:103]
|
|
|
|
|
mpc_run_state_ns <= _T_157 @[dec_tlu_ctl.scala 394:26]
|
|
|
|
|
node _T_158 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 397:70]
|
|
|
|
|
node _T_159 = or(_T_158, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 397:96]
|
|
|
|
|
node _T_160 = or(_T_159, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 397:121]
|
|
|
|
|
node _T_161 = or(dbg_halt_state_f, _T_160) @[dec_tlu_ctl.scala 397:48]
|
|
|
|
|
node _T_162 = not(io.dbg_resume_req) @[dec_tlu_ctl.scala 397:153]
|
|
|
|
|
node _T_163 = and(_T_161, _T_162) @[dec_tlu_ctl.scala 397:151]
|
|
|
|
|
dbg_halt_state_ns <= _T_163 @[dec_tlu_ctl.scala 397:27]
|
|
|
|
|
node _T_164 = or(dbg_run_state_f, io.dbg_resume_req) @[dec_tlu_ctl.scala 398:46]
|
|
|
|
|
node _T_165 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 398:97]
|
|
|
|
|
node _T_166 = and(debug_mode_status, _T_165) @[dec_tlu_ctl.scala 398:95]
|
|
|
|
|
node _T_167 = and(_T_164, _T_166) @[dec_tlu_ctl.scala 398:67]
|
|
|
|
|
dbg_run_state_ns <= _T_167 @[dec_tlu_ctl.scala 398:26]
|
|
|
|
|
node _T_168 = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 401:39]
|
|
|
|
|
node _T_169 = and(_T_168, mpc_halt_state_f) @[dec_tlu_ctl.scala 401:57]
|
|
|
|
|
dec_tlu_mpc_halted_only_ns <= _T_169 @[dec_tlu_ctl.scala 401:36]
|
|
|
|
|
node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 404:59]
|
|
|
|
|
node _T_170 = or(debug_brkpt_valid, debug_brkpt_status_f) @[dec_tlu_ctl.scala 405:53]
|
|
|
|
|
node _T_171 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 405:105]
|
|
|
|
|
node _T_172 = and(internal_dbg_halt_mode, _T_171) @[dec_tlu_ctl.scala 405:103]
|
|
|
|
|
node _T_173 = and(_T_170, _T_172) @[dec_tlu_ctl.scala 405:77]
|
|
|
|
|
debug_brkpt_status_ns <= _T_173 @[dec_tlu_ctl.scala 405:31]
|
|
|
|
|
node _T_174 = and(mpc_halt_state_f, debug_mode_status) @[dec_tlu_ctl.scala 408:51]
|
|
|
|
|
node _T_175 = and(_T_174, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 408:78]
|
|
|
|
|
node _T_176 = and(_T_175, core_empty) @[dec_tlu_ctl.scala 408:104]
|
|
|
|
|
mpc_debug_halt_ack_ns <= _T_176 @[dec_tlu_ctl.scala 408:31]
|
|
|
|
|
node _T_177 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 409:59]
|
|
|
|
|
node _T_178 = and(mpc_debug_run_req_sync, _T_177) @[dec_tlu_ctl.scala 409:57]
|
|
|
|
|
node _T_179 = not(mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 409:80]
|
|
|
|
|
node _T_180 = and(_T_178, _T_179) @[dec_tlu_ctl.scala 409:78]
|
|
|
|
|
node _T_181 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 409:129]
|
|
|
|
|
node _T_182 = or(_T_180, _T_181) @[dec_tlu_ctl.scala 409:106]
|
|
|
|
|
mpc_debug_run_ack_ns <= _T_182 @[dec_tlu_ctl.scala 409:30]
|
|
|
|
|
io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[dec_tlu_ctl.scala 412:31]
|
|
|
|
|
io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[dec_tlu_ctl.scala 413:31]
|
|
|
|
|
io.debug_brkpt_status <= debug_brkpt_status_f @[dec_tlu_ctl.scala 414:31]
|
|
|
|
|
node _T_183 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 417:53]
|
|
|
|
|
node dbg_halt_req_held_ns = and(_T_183, csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 417:74]
|
|
|
|
|
node _T_184 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 418:48]
|
|
|
|
|
node _T_185 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 418:71]
|
|
|
|
|
node _T_186 = and(_T_184, _T_185) @[dec_tlu_ctl.scala 418:69]
|
|
|
|
|
dbg_halt_req_final <= _T_186 @[dec_tlu_ctl.scala 418:28]
|
|
|
|
|
node _T_187 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 421:50]
|
|
|
|
|
node _T_188 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 421:95]
|
|
|
|
|
node _T_189 = and(reset_delayed, _T_188) @[dec_tlu_ctl.scala 421:93]
|
|
|
|
|
node _T_190 = or(_T_187, _T_189) @[dec_tlu_ctl.scala 421:76]
|
|
|
|
|
node _T_191 = not(debug_mode_status) @[dec_tlu_ctl.scala 421:121]
|
|
|
|
|
node _T_192 = and(_T_190, _T_191) @[dec_tlu_ctl.scala 421:119]
|
|
|
|
|
node _T_193 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 421:149]
|
|
|
|
|
node debug_halt_req = and(_T_192, _T_193) @[dec_tlu_ctl.scala 421:147]
|
|
|
|
|
node _T_194 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 423:32]
|
|
|
|
|
node _T_195 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 423:75]
|
|
|
|
|
node _T_196 = and(mpc_run_state_ns, _T_195) @[dec_tlu_ctl.scala 423:73]
|
|
|
|
|
node _T_197 = not(mpc_halt_state_ns) @[dec_tlu_ctl.scala 423:117]
|
|
|
|
|
node _T_198 = and(dbg_run_state_ns, _T_197) @[dec_tlu_ctl.scala 423:115]
|
|
|
|
|
node _T_199 = or(_T_196, _T_198) @[dec_tlu_ctl.scala 423:95]
|
|
|
|
|
node debug_resume_req = and(_T_194, _T_199) @[dec_tlu_ctl.scala 423:52]
|
|
|
|
|
node _T_200 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 428:43]
|
|
|
|
|
node _T_201 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 428:66]
|
|
|
|
|
node _T_202 = and(_T_200, _T_201) @[dec_tlu_ctl.scala 428:64]
|
|
|
|
|
node _T_203 = not(mret_r) @[dec_tlu_ctl.scala 428:89]
|
|
|
|
|
node _T_204 = and(_T_202, _T_203) @[dec_tlu_ctl.scala 428:87]
|
|
|
|
|
node _T_205 = not(halt_taken_f) @[dec_tlu_ctl.scala 428:99]
|
|
|
|
|
node _T_206 = and(_T_204, _T_205) @[dec_tlu_ctl.scala 428:97]
|
|
|
|
|
node _T_207 = not(dec_tlu_flush_noredir_r_d1) @[dec_tlu_ctl.scala 428:115]
|
|
|
|
|
node _T_208 = and(_T_206, _T_207) @[dec_tlu_ctl.scala 428:113]
|
|
|
|
|
node _T_209 = not(take_reset) @[dec_tlu_ctl.scala 428:145]
|
|
|
|
|
node take_halt = and(_T_208, _T_209) @[dec_tlu_ctl.scala 428:143]
|
|
|
|
|
node _T_210 = eq(dec_tlu_flush_pause_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:56]
|
|
|
|
|
node _T_211 = and(dec_tlu_flush_noredir_r_d1, _T_210) @[dec_tlu_ctl.scala 431:54]
|
|
|
|
|
node _T_212 = eq(csr.io.take_ext_int_start_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:84]
|
|
|
|
|
node _T_213 = and(_T_211, _T_212) @[dec_tlu_ctl.scala 431:82]
|
|
|
|
|
node _T_214 = eq(dbg_tlu_halted_f, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:133]
|
|
|
|
|
node _T_215 = and(halt_taken_f, _T_214) @[dec_tlu_ctl.scala 431:131]
|
|
|
|
|
node _T_216 = eq(pmu_fw_tlu_halted_f, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:153]
|
|
|
|
|
node _T_217 = and(_T_215, _T_216) @[dec_tlu_ctl.scala 431:151]
|
|
|
|
|
node _T_218 = eq(interrupt_valid_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 431:176]
|
|
|
|
|
node _T_219 = and(_T_217, _T_218) @[dec_tlu_ctl.scala 431:174]
|
|
|
|
|
node halt_taken = or(_T_213, _T_219) @[dec_tlu_ctl.scala 431:115]
|
|
|
|
|
node _T_220 = and(io.lsu_idle_any, lsu_idle_any_f) @[dec_tlu_ctl.scala 435:53]
|
|
|
|
|
node _T_221 = and(_T_220, io.tlu_mem.ifu_miss_state_idle) @[dec_tlu_ctl.scala 435:70]
|
|
|
|
|
node _T_222 = and(_T_221, ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 435:103]
|
|
|
|
|
node _T_223 = not(debug_halt_req) @[dec_tlu_ctl.scala 435:129]
|
|
|
|
|
node _T_224 = and(_T_222, _T_223) @[dec_tlu_ctl.scala 435:127]
|
|
|
|
|
node _T_225 = not(debug_halt_req_d1) @[dec_tlu_ctl.scala 435:147]
|
|
|
|
|
node _T_226 = and(_T_224, _T_225) @[dec_tlu_ctl.scala 435:145]
|
|
|
|
|
node _T_227 = not(io.dec_div_active) @[dec_tlu_ctl.scala 435:168]
|
|
|
|
|
node _T_228 = and(_T_226, _T_227) @[dec_tlu_ctl.scala 435:166]
|
|
|
|
|
node _T_229 = or(force_halt, _T_228) @[dec_tlu_ctl.scala 435:34]
|
|
|
|
|
core_empty <= _T_229 @[dec_tlu_ctl.scala 435:20]
|
|
|
|
|
io.dec_tlu_core_empty <= core_empty @[dec_tlu_ctl.scala 436:31]
|
|
|
|
|
node _T_230 = not(debug_mode_status) @[dec_tlu_ctl.scala 441:37]
|
|
|
|
|
node _T_231 = and(_T_230, debug_halt_req) @[dec_tlu_ctl.scala 441:63]
|
|
|
|
|
node _T_232 = or(_T_231, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 441:81]
|
|
|
|
|
node _T_233 = or(_T_232, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 441:107]
|
|
|
|
|
node enter_debug_halt_req = or(_T_233, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 441:132]
|
|
|
|
|
node _T_234 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 444:111]
|
|
|
|
|
node _T_235 = not(_T_234) @[dec_tlu_ctl.scala 444:106]
|
|
|
|
|
node _T_236 = and(debug_resume_req_f, _T_235) @[dec_tlu_ctl.scala 444:104]
|
|
|
|
|
node _T_237 = not(_T_236) @[dec_tlu_ctl.scala 444:83]
|
|
|
|
|
node _T_238 = and(debug_mode_status, _T_237) @[dec_tlu_ctl.scala 444:81]
|
|
|
|
|
node _T_239 = or(debug_halt_req_ns, _T_238) @[dec_tlu_ctl.scala 444:53]
|
|
|
|
|
internal_dbg_halt_mode <= _T_239 @[dec_tlu_ctl.scala 444:32]
|
|
|
|
|
node _T_240 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 447:67]
|
|
|
|
|
node allow_dbg_halt_csr_write = and(debug_mode_status, _T_240) @[dec_tlu_ctl.scala 447:65]
|
|
|
|
|
node _T_241 = and(debug_halt_req_f, core_empty) @[dec_tlu_ctl.scala 452:48]
|
|
|
|
|
node _T_242 = and(_T_241, halt_taken) @[dec_tlu_ctl.scala 452:61]
|
|
|
|
|
node _T_243 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 452:97]
|
|
|
|
|
node _T_244 = and(dbg_tlu_halted_f, _T_243) @[dec_tlu_ctl.scala 452:95]
|
|
|
|
|
node dbg_tlu_halted = or(_T_242, _T_244) @[dec_tlu_ctl.scala 452:75]
|
|
|
|
|
node _T_245 = not(dbg_tlu_halted) @[dec_tlu_ctl.scala 454:73]
|
|
|
|
|
node _T_246 = and(debug_halt_req_f, _T_245) @[dec_tlu_ctl.scala 454:71]
|
|
|
|
|
node _T_247 = or(enter_debug_halt_req, _T_246) @[dec_tlu_ctl.scala 454:51]
|
|
|
|
|
debug_halt_req_ns <= _T_247 @[dec_tlu_ctl.scala 454:27]
|
|
|
|
|
node _T_248 = and(debug_resume_req_f, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 455:49]
|
|
|
|
|
node resume_ack_ns = and(_T_248, dbg_run_state_ns) @[dec_tlu_ctl.scala 455:68]
|
|
|
|
|
node _T_249 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 457:61]
|
|
|
|
|
node _T_250 = and(io.dec_tlu_i0_valid_r, _T_249) @[dec_tlu_ctl.scala 457:59]
|
|
|
|
|
node _T_251 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 457:90]
|
|
|
|
|
node _T_252 = and(_T_250, _T_251) @[dec_tlu_ctl.scala 457:84]
|
|
|
|
|
node _T_253 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 457:104]
|
|
|
|
|
node dcsr_single_step_done = and(_T_252, _T_253) @[dec_tlu_ctl.scala 457:102]
|
|
|
|
|
node _T_254 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 459:66]
|
|
|
|
|
node _T_255 = and(debug_resume_req_f, _T_254) @[dec_tlu_ctl.scala 459:60]
|
|
|
|
|
node _T_256 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 459:111]
|
|
|
|
|
node _T_257 = and(dcsr_single_step_running_f, _T_256) @[dec_tlu_ctl.scala 459:109]
|
|
|
|
|
node dcsr_single_step_running = or(_T_255, _T_257) @[dec_tlu_ctl.scala 459:79]
|
|
|
|
|
node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 461:53]
|
|
|
|
|
node _T_258 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 464:57]
|
|
|
|
|
node _T_259 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 464:112]
|
|
|
|
|
node _T_260 = and(request_debug_mode_r_d1, _T_259) @[dec_tlu_ctl.scala 464:110]
|
|
|
|
|
node request_debug_mode_r = or(_T_258, _T_260) @[dec_tlu_ctl.scala 464:83]
|
|
|
|
|
node _T_261 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 466:64]
|
|
|
|
|
node _T_262 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 466:95]
|
|
|
|
|
node request_debug_mode_done = and(_T_261, _T_262) @[dec_tlu_ctl.scala 466:93]
|
|
|
|
|
wire _T_263 : UInt<1>
|
|
|
|
|
_T_263 <= UInt<1>("h00")
|
|
|
|
|
node _T_264 = xor(io.tlu_ifc.dec_tlu_flush_noredir_wb, _T_263) @[lib.scala 470:21]
|
|
|
|
|
node _T_265 = orr(_T_264) @[lib.scala 470:29]
|
|
|
|
|
reg _T_266 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_265 : @[Reg.scala 28:19]
|
|
|
|
|
_T_266 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_263 <= _T_266 @[lib.scala 473:16]
|
|
|
|
|
dec_tlu_flush_noredir_r_d1 <= _T_263 @[dec_tlu_ctl.scala 468:51]
|
|
|
|
|
wire _T_267 : UInt
|
|
|
|
|
_T_267 <= UInt<1>("h00")
|
|
|
|
|
node _T_268 = xor(halt_taken, _T_267) @[lib.scala 448:21]
|
|
|
|
|
node _T_269 = orr(_T_268) @[lib.scala 448:29]
|
|
|
|
|
reg _T_270 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_269 : @[Reg.scala 28:19]
|
|
|
|
|
_T_270 <= halt_taken @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_267 <= _T_270 @[lib.scala 451:16]
|
|
|
|
|
halt_taken_f <= _T_267 @[dec_tlu_ctl.scala 469:65]
|
|
|
|
|
wire _T_271 : UInt
|
|
|
|
|
_T_271 <= UInt<1>("h00")
|
|
|
|
|
node _T_272 = xor(io.lsu_idle_any, _T_271) @[lib.scala 448:21]
|
|
|
|
|
node _T_273 = orr(_T_272) @[lib.scala 448:29]
|
|
|
|
|
reg _T_274 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_273 : @[Reg.scala 28:19]
|
|
|
|
|
_T_274 <= io.lsu_idle_any @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_271 <= _T_274 @[lib.scala 451:16]
|
|
|
|
|
lsu_idle_any_f <= _T_271 @[dec_tlu_ctl.scala 470:63]
|
|
|
|
|
wire _T_275 : UInt<1>
|
|
|
|
|
_T_275 <= UInt<1>("h00")
|
|
|
|
|
node _T_276 = xor(io.tlu_mem.ifu_miss_state_idle, _T_275) @[lib.scala 470:21]
|
|
|
|
|
node _T_277 = orr(_T_276) @[lib.scala 470:29]
|
|
|
|
|
reg _T_278 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_277 : @[Reg.scala 28:19]
|
|
|
|
|
_T_278 <= io.tlu_mem.ifu_miss_state_idle @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_275 <= _T_278 @[lib.scala 473:16]
|
|
|
|
|
ifu_miss_state_idle_f <= _T_275 @[dec_tlu_ctl.scala 471:53]
|
|
|
|
|
wire _T_279 : UInt
|
|
|
|
|
_T_279 <= UInt<1>("h00")
|
|
|
|
|
node _T_280 = xor(dbg_tlu_halted, _T_279) @[lib.scala 448:21]
|
|
|
|
|
node _T_281 = orr(_T_280) @[lib.scala 448:29]
|
|
|
|
|
reg _T_282 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_281 : @[Reg.scala 28:19]
|
|
|
|
|
_T_282 <= dbg_tlu_halted @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_279 <= _T_282 @[lib.scala 451:16]
|
|
|
|
|
dbg_tlu_halted_f <= _T_279 @[dec_tlu_ctl.scala 472:63]
|
|
|
|
|
wire _T_283 : UInt
|
|
|
|
|
_T_283 <= UInt<1>("h00")
|
|
|
|
|
node _T_284 = xor(resume_ack_ns, _T_283) @[lib.scala 448:21]
|
|
|
|
|
node _T_285 = orr(_T_284) @[lib.scala 448:29]
|
|
|
|
|
reg _T_286 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_285 : @[Reg.scala 28:19]
|
|
|
|
|
_T_286 <= resume_ack_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_283 <= _T_286 @[lib.scala 451:16]
|
|
|
|
|
io.dec_tlu_resume_ack <= _T_283 @[dec_tlu_ctl.scala 473:53]
|
|
|
|
|
wire _T_287 : UInt
|
|
|
|
|
_T_287 <= UInt<1>("h00")
|
|
|
|
|
node _T_288 = xor(debug_halt_req_ns, _T_287) @[lib.scala 448:21]
|
|
|
|
|
node _T_289 = orr(_T_288) @[lib.scala 448:29]
|
|
|
|
|
reg _T_290 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_289 : @[Reg.scala 28:19]
|
|
|
|
|
_T_290 <= debug_halt_req_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_287 <= _T_290 @[lib.scala 451:16]
|
|
|
|
|
debug_halt_req_f <= _T_287 @[dec_tlu_ctl.scala 474:63]
|
|
|
|
|
wire _T_291 : UInt
|
|
|
|
|
_T_291 <= UInt<1>("h00")
|
|
|
|
|
node _T_292 = xor(debug_resume_req, _T_291) @[lib.scala 448:21]
|
|
|
|
|
node _T_293 = orr(_T_292) @[lib.scala 448:29]
|
|
|
|
|
reg _T_294 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_293 : @[Reg.scala 28:19]
|
|
|
|
|
_T_294 <= debug_resume_req @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_291 <= _T_294 @[lib.scala 451:16]
|
|
|
|
|
debug_resume_req_f_raw <= _T_291 @[dec_tlu_ctl.scala 475:57]
|
|
|
|
|
wire _T_295 : UInt
|
|
|
|
|
_T_295 <= UInt<1>("h00")
|
|
|
|
|
node _T_296 = xor(trigger_hit_dmode_r, _T_295) @[lib.scala 448:21]
|
|
|
|
|
node _T_297 = orr(_T_296) @[lib.scala 448:29]
|
|
|
|
|
reg _T_298 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_297 : @[Reg.scala 28:19]
|
|
|
|
|
_T_298 <= trigger_hit_dmode_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_295 <= _T_298 @[lib.scala 451:16]
|
|
|
|
|
trigger_hit_dmode_r_d1 <= _T_295 @[dec_tlu_ctl.scala 476:51]
|
|
|
|
|
wire _T_299 : UInt
|
|
|
|
|
_T_299 <= UInt<1>("h00")
|
|
|
|
|
node _T_300 = xor(dcsr_single_step_done, _T_299) @[lib.scala 448:21]
|
|
|
|
|
node _T_301 = orr(_T_300) @[lib.scala 448:29]
|
|
|
|
|
reg _T_302 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_301 : @[Reg.scala 28:19]
|
|
|
|
|
_T_302 <= dcsr_single_step_done @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_299 <= _T_302 @[lib.scala 451:16]
|
|
|
|
|
dcsr_single_step_done_f <= _T_299 @[dec_tlu_ctl.scala 477:51]
|
|
|
|
|
wire _T_303 : UInt
|
|
|
|
|
_T_303 <= UInt<1>("h00")
|
|
|
|
|
node _T_304 = xor(debug_halt_req, _T_303) @[lib.scala 448:21]
|
|
|
|
|
node _T_305 = orr(_T_304) @[lib.scala 448:29]
|
|
|
|
|
reg _T_306 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_305 : @[Reg.scala 28:19]
|
|
|
|
|
_T_306 <= debug_halt_req @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_303 <= _T_306 @[lib.scala 451:16]
|
|
|
|
|
debug_halt_req_d1 <= _T_303 @[dec_tlu_ctl.scala 478:63]
|
|
|
|
|
wire dec_tlu_wr_pause_r_d1 : UInt
|
|
|
|
|
dec_tlu_wr_pause_r_d1 <= UInt<1>("h00")
|
|
|
|
|
node _T_307 = xor(io.dec_tlu_wr_pause_r, dec_tlu_wr_pause_r_d1) @[lib.scala 448:21]
|
|
|
|
|
node _T_308 = orr(_T_307) @[lib.scala 448:29]
|
|
|
|
|
reg _T_309 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_308 : @[Reg.scala 28:19]
|
|
|
|
|
_T_309 <= io.dec_tlu_wr_pause_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
dec_tlu_wr_pause_r_d1 <= _T_309 @[lib.scala 451:16]
|
|
|
|
|
wire dec_pause_state_f : UInt
|
|
|
|
|
dec_pause_state_f <= UInt<1>("h00")
|
|
|
|
|
node _T_310 = xor(io.dec_pause_state, dec_pause_state_f) @[lib.scala 448:21]
|
|
|
|
|
node _T_311 = orr(_T_310) @[lib.scala 448:29]
|
|
|
|
|
reg _T_312 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_311 : @[Reg.scala 28:19]
|
|
|
|
|
_T_312 <= io.dec_pause_state @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
dec_pause_state_f <= _T_312 @[lib.scala 451:16]
|
|
|
|
|
wire _T_313 : UInt
|
|
|
|
|
_T_313 <= UInt<1>("h00")
|
|
|
|
|
node _T_314 = xor(request_debug_mode_r, _T_313) @[lib.scala 448:21]
|
|
|
|
|
node _T_315 = orr(_T_314) @[lib.scala 448:29]
|
|
|
|
|
reg _T_316 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_315 : @[Reg.scala 28:19]
|
|
|
|
|
_T_316 <= request_debug_mode_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_313 <= _T_316 @[lib.scala 451:16]
|
|
|
|
|
request_debug_mode_r_d1 <= _T_313 @[dec_tlu_ctl.scala 481:49]
|
|
|
|
|
wire _T_317 : UInt
|
|
|
|
|
_T_317 <= UInt<1>("h00")
|
|
|
|
|
node _T_318 = xor(request_debug_mode_done, _T_317) @[lib.scala 448:21]
|
|
|
|
|
node _T_319 = orr(_T_318) @[lib.scala 448:29]
|
|
|
|
|
reg _T_320 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_319 : @[Reg.scala 28:19]
|
|
|
|
|
_T_320 <= request_debug_mode_done @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_317 <= _T_320 @[lib.scala 451:16]
|
|
|
|
|
request_debug_mode_done_f <= _T_317 @[dec_tlu_ctl.scala 482:49]
|
|
|
|
|
wire _T_321 : UInt
|
|
|
|
|
_T_321 <= UInt<1>("h00")
|
|
|
|
|
node _T_322 = xor(dcsr_single_step_running, _T_321) @[lib.scala 448:21]
|
|
|
|
|
node _T_323 = orr(_T_322) @[lib.scala 448:29]
|
|
|
|
|
reg _T_324 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_323 : @[Reg.scala 28:19]
|
|
|
|
|
_T_324 <= dcsr_single_step_running @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_321 <= _T_324 @[lib.scala 451:16]
|
|
|
|
|
dcsr_single_step_running_f <= _T_321 @[dec_tlu_ctl.scala 483:49]
|
|
|
|
|
wire _T_325 : UInt
|
|
|
|
|
_T_325 <= UInt<1>("h00")
|
|
|
|
|
node _T_326 = xor(io.dec_tlu_flush_pause_r, _T_325) @[lib.scala 448:21]
|
|
|
|
|
node _T_327 = orr(_T_326) @[lib.scala 448:29]
|
|
|
|
|
reg _T_328 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_327 : @[Reg.scala 28:19]
|
|
|
|
|
_T_328 <= io.dec_tlu_flush_pause_r @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_325 <= _T_328 @[lib.scala 451:16]
|
|
|
|
|
dec_tlu_flush_pause_r_d1 <= _T_325 @[dec_tlu_ctl.scala 484:49]
|
|
|
|
|
wire _T_329 : UInt
|
|
|
|
|
_T_329 <= UInt<1>("h00")
|
|
|
|
|
node _T_330 = xor(dbg_halt_req_held_ns, _T_329) @[lib.scala 448:21]
|
|
|
|
|
node _T_331 = orr(_T_330) @[lib.scala 448:29]
|
|
|
|
|
reg _T_332 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_331 : @[Reg.scala 28:19]
|
|
|
|
|
_T_332 <= dbg_halt_req_held_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_329 <= _T_332 @[lib.scala 451:16]
|
|
|
|
|
dbg_halt_req_held <= _T_329 @[dec_tlu_ctl.scala 485:57]
|
|
|
|
|
node _T_333 = not(io.dbg_halt_req) @[dec_tlu_ctl.scala 489:56]
|
|
|
|
|
node _T_334 = and(debug_resume_req_f_raw, _T_333) @[dec_tlu_ctl.scala 489:54]
|
|
|
|
|
debug_resume_req_f <= _T_334 @[dec_tlu_ctl.scala 489:28]
|
|
|
|
|
io.dec_tlu_debug_stall <= debug_halt_req_f @[dec_tlu_ctl.scala 491:41]
|
|
|
|
|
io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 492:41]
|
|
|
|
|
io.dec_tlu_debug_mode <= debug_mode_status @[dec_tlu_ctl.scala 493:41]
|
|
|
|
|
dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 494:41]
|
|
|
|
|
node _T_335 = and(fence_i_r, internal_dbg_halt_mode) @[dec_tlu_ctl.scala 497:71]
|
|
|
|
|
node _T_336 = or(take_halt, _T_335) @[dec_tlu_ctl.scala 497:58]
|
|
|
|
|
node _T_337 = or(_T_336, io.dec_tlu_flush_pause_r) @[dec_tlu_ctl.scala 497:97]
|
|
|
|
|
node _T_338 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[dec_tlu_ctl.scala 497:144]
|
|
|
|
|
node _T_339 = or(_T_337, _T_338) @[dec_tlu_ctl.scala 497:124]
|
|
|
|
|
node _T_340 = or(_T_339, take_ext_int_start) @[dec_tlu_ctl.scala 497:167]
|
|
|
|
|
io.tlu_ifc.dec_tlu_flush_noredir_wb <= _T_340 @[dec_tlu_ctl.scala 497:45]
|
|
|
|
|
io.dec_tlu_flush_extint <= take_ext_int_start @[dec_tlu_ctl.scala 499:33]
|
|
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|
|
node _T_341 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 502:61]
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|
node _T_342 = and(dec_tlu_wr_pause_r_d1, _T_341) @[dec_tlu_ctl.scala 502:59]
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|
node _T_343 = not(take_ext_int_start) @[dec_tlu_ctl.scala 502:82]
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|
node _T_344 = and(_T_342, _T_343) @[dec_tlu_ctl.scala 502:80]
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|
|
io.dec_tlu_flush_pause_r <= _T_344 @[dec_tlu_ctl.scala 502:34]
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|
node _T_345 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 504:28]
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|
node _T_346 = and(_T_345, dec_pause_state_f) @[dec_tlu_ctl.scala 504:48]
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|
node _T_347 = or(ext_int_ready, ce_int_ready) @[dec_tlu_ctl.scala 504:86]
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|
node _T_348 = or(_T_347, timer_int_ready) @[dec_tlu_ctl.scala 504:101]
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|
node _T_349 = or(_T_348, soft_int_ready) @[dec_tlu_ctl.scala 504:119]
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|
node _T_350 = or(_T_349, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 504:136]
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|
node _T_351 = or(_T_350, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 504:160]
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|
node _T_352 = or(_T_351, nmi_int_detected) @[dec_tlu_ctl.scala 504:184]
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|
node _T_353 = or(_T_352, csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 504:203]
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node _T_354 = not(_T_353) @[dec_tlu_ctl.scala 504:70]
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node _T_355 = and(_T_346, _T_354) @[dec_tlu_ctl.scala 504:68]
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node _T_356 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 504:233]
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|
node _T_357 = and(_T_355, _T_356) @[dec_tlu_ctl.scala 504:231]
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node _T_358 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 504:257]
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|
node _T_359 = and(_T_357, _T_358) @[dec_tlu_ctl.scala 504:255]
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node _T_360 = not(pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 504:277]
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|
node _T_361 = and(_T_359, _T_360) @[dec_tlu_ctl.scala 504:275]
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node _T_362 = not(halt_taken_f) @[dec_tlu_ctl.scala 504:298]
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|
node _T_363 = and(_T_361, _T_362) @[dec_tlu_ctl.scala 504:296]
|
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|
|
pause_expired_r <= _T_363 @[dec_tlu_ctl.scala 504:25]
|
|
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|
|
node _T_364 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 506:88]
|
|
|
|
|
node _T_365 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_364) @[dec_tlu_ctl.scala 506:82]
|
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|
|
node _T_366 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[dec_tlu_ctl.scala 506:125]
|
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|
|
node _T_367 = and(_T_365, _T_366) @[dec_tlu_ctl.scala 506:100]
|
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|
node _T_368 = not(io.tlu_ifc.dec_tlu_flush_noredir_wb) @[dec_tlu_ctl.scala 506:155]
|
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|
|
node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 506:153]
|
|
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|
|
io.tlu_bp.dec_tlu_flush_leak_one_wb <= _T_369 @[dec_tlu_ctl.scala 506:45]
|
|
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|
|
node _T_370 = or(ic_perr_r, iccm_sbecc_r) @[dec_tlu_ctl.scala 507:90]
|
|
|
|
|
node _T_371 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_370) @[dec_tlu_ctl.scala 507:77]
|
|
|
|
|
io.tlu_mem.dec_tlu_flush_err_wb <= _T_371 @[dec_tlu_ctl.scala 507:41]
|
|
|
|
|
io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[dec_tlu_ctl.scala 510:29]
|
|
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|
|
node _T_372 = and(illegal_r, io.dec_dbg_cmd_done) @[dec_tlu_ctl.scala 511:42]
|
|
|
|
|
io.dec_dbg_cmd_fail <= _T_372 @[dec_tlu_ctl.scala 511:29]
|
|
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|
|
node _T_373 = bits(mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 524:48]
|
|
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|
|
node _T_374 = bits(mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 524:75]
|
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|
|
node _T_375 = bits(mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 524:102]
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|
|
node _T_376 = bits(mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 524:129]
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|
|
node _T_377 = cat(_T_375, _T_376) @[Cat.scala 29:58]
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|
node _T_378 = cat(_T_373, _T_374) @[Cat.scala 29:58]
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|
|
node trigger_execute = cat(_T_378, _T_377) @[Cat.scala 29:58]
|
|
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|
|
node _T_379 = bits(mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 525:52]
|
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|
|
node _T_380 = bits(mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 525:79]
|
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|
node _T_381 = bits(mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 525:106]
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|
|
node _T_382 = bits(mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 525:133]
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|
node _T_383 = cat(_T_381, _T_382) @[Cat.scala 29:58]
|
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|
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node _T_384 = cat(_T_379, _T_380) @[Cat.scala 29:58]
|
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|
|
node trigger_data = cat(_T_384, _T_383) @[Cat.scala 29:58]
|
|
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|
node _T_385 = bits(mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 526:52]
|
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|
node _T_386 = bits(mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 526:79]
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|
node _T_387 = bits(mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 526:106]
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|
|
node _T_388 = bits(mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 526:133]
|
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|
|
node _T_389 = cat(_T_387, _T_388) @[Cat.scala 29:58]
|
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|
node _T_390 = cat(_T_385, _T_386) @[Cat.scala 29:58]
|
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|
|
node trigger_store = cat(_T_390, _T_389) @[Cat.scala 29:58]
|
|
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|
|
node _T_391 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 529:53]
|
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|
|
node _T_392 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 529:79]
|
|
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|
|
node _T_393 = or(_T_391, _T_392) @[dec_tlu_ctl.scala 529:70]
|
|
|
|
|
node _T_394 = bits(mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 529:108]
|
|
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|
|
node _T_395 = and(_T_393, _T_394) @[dec_tlu_ctl.scala 529:94]
|
|
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|
|
node _T_396 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 530:30]
|
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|
|
node _T_397 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 530:56]
|
|
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|
|
node _T_398 = or(_T_396, _T_397) @[dec_tlu_ctl.scala 530:47]
|
|
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|
|
node _T_399 = bits(mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 530:85]
|
|
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|
|
node _T_400 = and(_T_398, _T_399) @[dec_tlu_ctl.scala 530:71]
|
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|
|
node _T_401 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 531:30]
|
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|
|
node _T_402 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 531:56]
|
|
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|
|
node _T_403 = or(_T_401, _T_402) @[dec_tlu_ctl.scala 531:47]
|
|
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|
|
node _T_404 = bits(mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 531:85]
|
|
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|
|
node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 531:71]
|
|
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|
|
node _T_406 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 532:30]
|
|
|
|
|
node _T_407 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 532:56]
|
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|
|
node _T_408 = or(_T_406, _T_407) @[dec_tlu_ctl.scala 532:47]
|
|
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|
|
node _T_409 = bits(mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 532:85]
|
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|
|
node _T_410 = and(_T_408, _T_409) @[dec_tlu_ctl.scala 532:71]
|
|
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|
|
node _T_411 = cat(_T_405, _T_410) @[Cat.scala 29:58]
|
|
|
|
|
node _T_412 = cat(_T_395, _T_400) @[Cat.scala 29:58]
|
|
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|
|
node trigger_enabled = cat(_T_412, _T_411) @[Cat.scala 29:58]
|
|
|
|
|
node _T_413 = and(trigger_execute, trigger_data) @[dec_tlu_ctl.scala 535:62]
|
|
|
|
|
node _T_414 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15]
|
|
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|
|
node _T_415 = mux(_T_414, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_416 = and(_T_413, _T_415) @[dec_tlu_ctl.scala 535:77]
|
|
|
|
|
node _T_417 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 535:142]
|
|
|
|
|
node _T_418 = bits(_T_417, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_419 = mux(_T_418, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_420 = or(_T_416, _T_419) @[dec_tlu_ctl.scala 535:103]
|
|
|
|
|
node i0_iside_trigger_has_pri_r = not(_T_420) @[dec_tlu_ctl.scala 535:43]
|
|
|
|
|
node _T_421 = and(trigger_store, trigger_data) @[dec_tlu_ctl.scala 538:56]
|
|
|
|
|
node _T_422 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_423 = mux(_T_422, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 538:71]
|
|
|
|
|
node i0_lsu_trigger_has_pri_r = not(_T_424) @[dec_tlu_ctl.scala 538:40]
|
|
|
|
|
node _T_425 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_426 = mux(_T_425, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_427 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[dec_tlu_ctl.scala 543:89]
|
|
|
|
|
node _T_428 = and(_T_426, _T_427) @[dec_tlu_ctl.scala 543:58]
|
|
|
|
|
node _T_429 = and(_T_428, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 543:95]
|
|
|
|
|
node _T_430 = and(_T_429, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 543:124]
|
|
|
|
|
node i0trigger_qual_r = and(_T_430, trigger_enabled) @[dec_tlu_ctl.scala 543:151]
|
|
|
|
|
node _T_431 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 545:64]
|
|
|
|
|
node _T_432 = bits(_T_431, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_433 = mux(_T_432, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_434 = not(_T_433) @[dec_tlu_ctl.scala 545:29]
|
|
|
|
|
node i0_trigger_r = and(_T_434, i0trigger_qual_r) @[dec_tlu_ctl.scala 545:90]
|
|
|
|
|
node _T_435 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 548:58]
|
|
|
|
|
node _T_436 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 548:78]
|
|
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|
|
node _T_437 = not(_T_436) @[dec_tlu_ctl.scala 548:65]
|
|
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|
|
node _T_438 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 548:108]
|
|
|
|
|
node _T_439 = or(_T_437, _T_438) @[dec_tlu_ctl.scala 548:94]
|
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|
|
|
node _T_440 = and(_T_435, _T_439) @[dec_tlu_ctl.scala 548:62]
|
|
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|
|
node _T_441 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 549:29]
|
|
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|
|
node _T_442 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 549:49]
|
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|
|
node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 549:36]
|
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|
|
node _T_444 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 549:79]
|
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|
|
node _T_445 = or(_T_443, _T_444) @[dec_tlu_ctl.scala 549:65]
|
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|
|
node _T_446 = and(_T_441, _T_445) @[dec_tlu_ctl.scala 549:33]
|
|
|
|
|
node _T_447 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 550:29]
|
|
|
|
|
node _T_448 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 550:49]
|
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|
|
node _T_449 = not(_T_448) @[dec_tlu_ctl.scala 550:36]
|
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|
|
node _T_450 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 550:79]
|
|
|
|
|
node _T_451 = or(_T_449, _T_450) @[dec_tlu_ctl.scala 550:65]
|
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|
|
node _T_452 = and(_T_447, _T_451) @[dec_tlu_ctl.scala 550:33]
|
|
|
|
|
node _T_453 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 551:29]
|
|
|
|
|
node _T_454 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 551:49]
|
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|
|
node _T_455 = not(_T_454) @[dec_tlu_ctl.scala 551:36]
|
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|
|
node _T_456 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 551:79]
|
|
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|
|
node _T_457 = or(_T_455, _T_456) @[dec_tlu_ctl.scala 551:65]
|
|
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|
|
node _T_458 = and(_T_453, _T_457) @[dec_tlu_ctl.scala 551:33]
|
|
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|
|
node _T_459 = cat(_T_452, _T_458) @[Cat.scala 29:58]
|
|
|
|
|
node _T_460 = cat(_T_440, _T_446) @[Cat.scala 29:58]
|
|
|
|
|
node i0_trigger_chain_masked_r = cat(_T_460, _T_459) @[Cat.scala 29:58]
|
|
|
|
|
node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 555:62]
|
|
|
|
|
i0_trigger_hit_r <= i0_trigger_hit_raw_r @[dec_tlu_ctl.scala 557:33]
|
|
|
|
|
node _T_461 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 561:52]
|
|
|
|
|
node _T_462 = bits(mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 561:83]
|
|
|
|
|
node _T_463 = and(_T_461, _T_462) @[dec_tlu_ctl.scala 561:69]
|
|
|
|
|
node _T_464 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 562:29]
|
|
|
|
|
node _T_465 = bits(mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 562:60]
|
|
|
|
|
node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 562:46]
|
|
|
|
|
node _T_467 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 562:91]
|
|
|
|
|
node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 562:78]
|
|
|
|
|
node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 562:76]
|
|
|
|
|
node _T_470 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 563:29]
|
|
|
|
|
node _T_471 = bits(mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 563:60]
|
|
|
|
|
node _T_472 = and(_T_470, _T_471) @[dec_tlu_ctl.scala 563:46]
|
|
|
|
|
node _T_473 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 564:29]
|
|
|
|
|
node _T_474 = bits(mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 564:60]
|
|
|
|
|
node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 564:46]
|
|
|
|
|
node _T_476 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 564:91]
|
|
|
|
|
node _T_477 = not(_T_476) @[dec_tlu_ctl.scala 564:78]
|
|
|
|
|
node _T_478 = and(_T_475, _T_477) @[dec_tlu_ctl.scala 564:76]
|
|
|
|
|
node _T_479 = cat(_T_472, _T_478) @[Cat.scala 29:58]
|
|
|
|
|
node _T_480 = cat(_T_463, _T_469) @[Cat.scala 29:58]
|
|
|
|
|
node trigger_action = cat(_T_480, _T_479) @[Cat.scala 29:58]
|
|
|
|
|
node _T_481 = orr(i0_trigger_r) @[dec_tlu_ctl.scala 567:59]
|
|
|
|
|
node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 567:65]
|
|
|
|
|
node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 567:63]
|
|
|
|
|
node _T_484 = bits(_T_483, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_485 = mux(_T_484, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_486 = bits(i0_trigger_chain_masked_r, 3, 3) @[dec_tlu_ctl.scala 567:108]
|
|
|
|
|
node _T_487 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 567:125]
|
|
|
|
|
node _T_488 = bits(i0_trigger_chain_masked_r, 1, 1) @[dec_tlu_ctl.scala 567:155]
|
|
|
|
|
node _T_489 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 567:172]
|
|
|
|
|
node _T_490 = cat(_T_488, _T_489) @[Cat.scala 29:58]
|
|
|
|
|
node _T_491 = cat(_T_486, _T_487) @[Cat.scala 29:58]
|
|
|
|
|
node _T_492 = cat(_T_491, _T_490) @[Cat.scala 29:58]
|
|
|
|
|
node update_hit_bit_r = and(_T_485, _T_492) @[dec_tlu_ctl.scala 567:77]
|
|
|
|
|
node _T_493 = and(i0_trigger_chain_masked_r, trigger_action) @[dec_tlu_ctl.scala 570:62]
|
|
|
|
|
node i0_trigger_action_r = orr(_T_493) @[dec_tlu_ctl.scala 570:80]
|
|
|
|
|
node _T_494 = and(i0_trigger_hit_r, i0_trigger_action_r) @[dec_tlu_ctl.scala 572:50]
|
|
|
|
|
trigger_hit_dmode_r <= _T_494 @[dec_tlu_ctl.scala 572:29]
|
|
|
|
|
node _T_495 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 574:60]
|
|
|
|
|
node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_495) @[dec_tlu_ctl.scala 574:58]
|
|
|
|
|
node _T_496 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 601:62]
|
|
|
|
|
node _T_497 = and(i_cpu_halt_req_sync, _T_496) @[dec_tlu_ctl.scala 601:60]
|
|
|
|
|
node _T_498 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 601:87]
|
|
|
|
|
node i_cpu_halt_req_sync_qual = and(_T_497, _T_498) @[dec_tlu_ctl.scala 601:85]
|
|
|
|
|
node _T_499 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 602:60]
|
|
|
|
|
node _T_500 = and(i_cpu_run_req_sync, _T_499) @[dec_tlu_ctl.scala 602:58]
|
|
|
|
|
node _T_501 = and(_T_500, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 602:83]
|
|
|
|
|
node _T_502 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 602:107]
|
|
|
|
|
node i_cpu_run_req_sync_qual = and(_T_501, _T_502) @[dec_tlu_ctl.scala 602:105]
|
|
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|
|
wire i_cpu_halt_req_d1 : UInt
|
|
|
|
|
i_cpu_halt_req_d1 <= UInt<1>("h00")
|
|
|
|
|
node _T_503 = xor(i_cpu_halt_req_sync_qual, i_cpu_halt_req_d1) @[lib.scala 448:21]
|
|
|
|
|
node _T_504 = orr(_T_503) @[lib.scala 448:29]
|
|
|
|
|
reg _T_505 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_504 : @[Reg.scala 28:19]
|
|
|
|
|
_T_505 <= i_cpu_halt_req_sync_qual @[Reg.scala 28:23]
|
|
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|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
i_cpu_halt_req_d1 <= _T_505 @[lib.scala 451:16]
|
|
|
|
|
wire i_cpu_run_req_d1_raw : UInt
|
|
|
|
|
i_cpu_run_req_d1_raw <= UInt<1>("h00")
|
|
|
|
|
node _T_506 = xor(i_cpu_run_req_sync_qual, i_cpu_run_req_d1_raw) @[lib.scala 448:21]
|
|
|
|
|
node _T_507 = orr(_T_506) @[lib.scala 448:29]
|
|
|
|
|
reg _T_508 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_507 : @[Reg.scala 28:19]
|
|
|
|
|
_T_508 <= i_cpu_run_req_sync_qual @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
i_cpu_run_req_d1_raw <= _T_508 @[lib.scala 451:16]
|
|
|
|
|
wire _T_509 : UInt
|
|
|
|
|
_T_509 <= UInt<1>("h00")
|
|
|
|
|
node _T_510 = xor(cpu_halt_status, _T_509) @[lib.scala 448:21]
|
|
|
|
|
node _T_511 = orr(_T_510) @[lib.scala 448:29]
|
|
|
|
|
reg _T_512 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_511 : @[Reg.scala 28:19]
|
|
|
|
|
_T_512 <= cpu_halt_status @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_509 <= _T_512 @[lib.scala 451:16]
|
|
|
|
|
io.o_cpu_halt_status <= _T_509 @[dec_tlu_ctl.scala 606:60]
|
|
|
|
|
wire _T_513 : UInt
|
|
|
|
|
_T_513 <= UInt<1>("h00")
|
|
|
|
|
node _T_514 = xor(cpu_halt_ack, _T_513) @[lib.scala 448:21]
|
|
|
|
|
node _T_515 = orr(_T_514) @[lib.scala 448:29]
|
|
|
|
|
reg _T_516 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_515 : @[Reg.scala 28:19]
|
|
|
|
|
_T_516 <= cpu_halt_ack @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_513 <= _T_516 @[lib.scala 451:16]
|
|
|
|
|
io.o_cpu_halt_ack <= _T_513 @[dec_tlu_ctl.scala 607:68]
|
|
|
|
|
wire _T_517 : UInt
|
|
|
|
|
_T_517 <= UInt<1>("h00")
|
|
|
|
|
node _T_518 = xor(cpu_run_ack, _T_517) @[lib.scala 448:21]
|
|
|
|
|
node _T_519 = orr(_T_518) @[lib.scala 448:29]
|
|
|
|
|
reg _T_520 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_519 : @[Reg.scala 28:19]
|
|
|
|
|
_T_520 <= cpu_run_ack @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_517 <= _T_520 @[lib.scala 451:16]
|
|
|
|
|
io.o_cpu_run_ack <= _T_517 @[dec_tlu_ctl.scala 608:68]
|
|
|
|
|
wire internal_pmu_fw_halt_mode_f : UInt
|
|
|
|
|
internal_pmu_fw_halt_mode_f <= UInt<1>("h00")
|
|
|
|
|
node _T_521 = xor(internal_pmu_fw_halt_mode, internal_pmu_fw_halt_mode_f) @[lib.scala 448:21]
|
|
|
|
|
node _T_522 = orr(_T_521) @[lib.scala 448:29]
|
|
|
|
|
reg _T_523 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_522 : @[Reg.scala 28:19]
|
|
|
|
|
_T_523 <= internal_pmu_fw_halt_mode @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
internal_pmu_fw_halt_mode_f <= _T_523 @[lib.scala 451:16]
|
|
|
|
|
wire _T_524 : UInt
|
|
|
|
|
_T_524 <= UInt<1>("h00")
|
|
|
|
|
node _T_525 = xor(pmu_fw_halt_req_ns, _T_524) @[lib.scala 448:21]
|
|
|
|
|
node _T_526 = orr(_T_525) @[lib.scala 448:29]
|
|
|
|
|
reg _T_527 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_526 : @[Reg.scala 28:19]
|
|
|
|
|
_T_527 <= pmu_fw_halt_req_ns @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_524 <= _T_527 @[lib.scala 451:16]
|
|
|
|
|
pmu_fw_halt_req_f <= _T_524 @[dec_tlu_ctl.scala 610:62]
|
|
|
|
|
wire _T_528 : UInt
|
|
|
|
|
_T_528 <= UInt<1>("h00")
|
|
|
|
|
node _T_529 = xor(pmu_fw_tlu_halted, _T_528) @[lib.scala 448:21]
|
|
|
|
|
node _T_530 = orr(_T_529) @[lib.scala 448:29]
|
|
|
|
|
reg _T_531 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_530 : @[Reg.scala 28:19]
|
|
|
|
|
_T_531 <= pmu_fw_tlu_halted @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_528 <= _T_531 @[lib.scala 451:16]
|
|
|
|
|
pmu_fw_tlu_halted_f <= _T_528 @[dec_tlu_ctl.scala 611:60]
|
|
|
|
|
wire _T_532 : UInt
|
|
|
|
|
_T_532 <= UInt<1>("h00")
|
|
|
|
|
node _T_533 = xor(int_timer0_int_hold, _T_532) @[lib.scala 448:21]
|
|
|
|
|
node _T_534 = orr(_T_533) @[lib.scala 448:29]
|
|
|
|
|
reg _T_535 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_534 : @[Reg.scala 28:19]
|
|
|
|
|
_T_535 <= int_timer0_int_hold @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_532 <= _T_535 @[lib.scala 451:16]
|
|
|
|
|
int_timer0_int_hold_f <= _T_532 @[dec_tlu_ctl.scala 612:52]
|
|
|
|
|
wire _T_536 : UInt
|
|
|
|
|
_T_536 <= UInt<1>("h00")
|
|
|
|
|
node _T_537 = xor(int_timer1_int_hold, _T_536) @[lib.scala 448:21]
|
|
|
|
|
node _T_538 = orr(_T_537) @[lib.scala 448:29]
|
|
|
|
|
reg _T_539 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_538 : @[Reg.scala 28:19]
|
|
|
|
|
_T_539 <= int_timer1_int_hold @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
_T_536 <= _T_539 @[lib.scala 451:16]
|
|
|
|
|
int_timer1_int_hold_f <= _T_536 @[dec_tlu_ctl.scala 613:52]
|
|
|
|
|
node _T_540 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 617:57]
|
|
|
|
|
node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_540) @[dec_tlu_ctl.scala 617:55]
|
|
|
|
|
node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 618:53]
|
|
|
|
|
node _T_541 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 619:77]
|
|
|
|
|
node _T_542 = and(pmu_fw_halt_req_f, _T_541) @[dec_tlu_ctl.scala 619:75]
|
|
|
|
|
node _T_543 = or(enter_pmu_fw_halt_req, _T_542) @[dec_tlu_ctl.scala 619:54]
|
|
|
|
|
node _T_544 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 619:100]
|
|
|
|
|
node _T_545 = and(_T_543, _T_544) @[dec_tlu_ctl.scala 619:98]
|
|
|
|
|
pmu_fw_halt_req_ns <= _T_545 @[dec_tlu_ctl.scala 619:28]
|
|
|
|
|
node _T_546 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 620:90]
|
|
|
|
|
node _T_547 = and(internal_pmu_fw_halt_mode_f, _T_546) @[dec_tlu_ctl.scala 620:88]
|
|
|
|
|
node _T_548 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 620:110]
|
|
|
|
|
node _T_549 = and(_T_547, _T_548) @[dec_tlu_ctl.scala 620:108]
|
|
|
|
|
node _T_550 = or(pmu_fw_halt_req_ns, _T_549) @[dec_tlu_ctl.scala 620:57]
|
|
|
|
|
internal_pmu_fw_halt_mode <= _T_550 @[dec_tlu_ctl.scala 620:35]
|
|
|
|
|
node _T_551 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 623:50]
|
|
|
|
|
node _T_552 = and(_T_551, halt_taken) @[dec_tlu_ctl.scala 623:63]
|
|
|
|
|
node _T_553 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 623:78]
|
|
|
|
|
node _T_554 = and(_T_552, _T_553) @[dec_tlu_ctl.scala 623:76]
|
|
|
|
|
node _T_555 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 623:126]
|
|
|
|
|
node _T_556 = and(pmu_fw_tlu_halted_f, _T_555) @[dec_tlu_ctl.scala 623:124]
|
|
|
|
|
node _T_557 = or(_T_554, _T_556) @[dec_tlu_ctl.scala 623:101]
|
|
|
|
|
node _T_558 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 623:148]
|
|
|
|
|
node _T_559 = and(_T_557, _T_558) @[dec_tlu_ctl.scala 623:146]
|
|
|
|
|
pmu_fw_tlu_halted <= _T_559 @[dec_tlu_ctl.scala 623:27]
|
|
|
|
|
node _T_560 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 625:44]
|
|
|
|
|
node _T_561 = and(io.o_cpu_halt_ack, i_cpu_halt_req_sync) @[dec_tlu_ctl.scala 625:88]
|
|
|
|
|
node _T_562 = or(_T_560, _T_561) @[dec_tlu_ctl.scala 625:67]
|
|
|
|
|
cpu_halt_ack <= _T_562 @[dec_tlu_ctl.scala 625:22]
|
|
|
|
|
node _T_563 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 626:51]
|
|
|
|
|
node _T_564 = and(pmu_fw_tlu_halted_f, _T_563) @[dec_tlu_ctl.scala 626:49]
|
|
|
|
|
node _T_565 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 626:96]
|
|
|
|
|
node _T_566 = and(io.o_cpu_halt_status, _T_565) @[dec_tlu_ctl.scala 626:94]
|
|
|
|
|
node _T_567 = not(debug_mode_status) @[dec_tlu_ctl.scala 626:116]
|
|
|
|
|
node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 626:114]
|
|
|
|
|
node _T_569 = or(_T_564, _T_568) @[dec_tlu_ctl.scala 626:70]
|
|
|
|
|
cpu_halt_status <= _T_569 @[dec_tlu_ctl.scala 626:25]
|
|
|
|
|
node _T_570 = not(pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 627:25]
|
|
|
|
|
node _T_571 = and(_T_570, i_cpu_run_req_sync) @[dec_tlu_ctl.scala 627:46]
|
|
|
|
|
node _T_572 = and(io.o_cpu_halt_status, i_cpu_run_req_d1_raw) @[dec_tlu_ctl.scala 627:92]
|
|
|
|
|
node _T_573 = or(_T_571, _T_572) @[dec_tlu_ctl.scala 627:68]
|
|
|
|
|
node _T_574 = and(io.o_cpu_run_ack, i_cpu_run_req_sync) @[dec_tlu_ctl.scala 627:136]
|
|
|
|
|
node _T_575 = or(_T_573, _T_574) @[dec_tlu_ctl.scala 627:116]
|
|
|
|
|
cpu_run_ack <= _T_575 @[dec_tlu_ctl.scala 627:21]
|
|
|
|
|
io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 630:32]
|
|
|
|
|
node _T_576 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 633:71]
|
|
|
|
|
node _T_577 = or(_T_576, soft_int_ready) @[dec_tlu_ctl.scala 633:89]
|
|
|
|
|
node _T_578 = or(_T_577, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 633:106]
|
|
|
|
|
node _T_579 = or(_T_578, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 633:130]
|
|
|
|
|
node _T_580 = and(io.dec_pic.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 633:177]
|
|
|
|
|
node _T_581 = or(_T_579, _T_580) @[dec_tlu_ctl.scala 633:154]
|
|
|
|
|
node _T_582 = and(_T_581, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 633:196]
|
|
|
|
|
node _T_583 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 633:221]
|
|
|
|
|
node _T_584 = and(_T_582, _T_583) @[dec_tlu_ctl.scala 633:219]
|
|
|
|
|
node _T_585 = or(i_cpu_run_req_d1_raw, _T_584) @[dec_tlu_ctl.scala 633:50]
|
|
|
|
|
i_cpu_run_req_d1 <= _T_585 @[dec_tlu_ctl.scala 633:26]
|
|
|
|
|
node _T_586 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 642:62]
|
|
|
|
|
node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_586) @[dec_tlu_ctl.scala 642:60]
|
|
|
|
|
lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 643:26]
|
|
|
|
|
node _T_587 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 644:45]
|
|
|
|
|
node _T_588 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 644:69]
|
|
|
|
|
node _T_589 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 644:67]
|
|
|
|
|
node _T_590 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 644:89]
|
|
|
|
|
node lsu_exc_valid_r = and(_T_589, _T_590) @[dec_tlu_ctl.scala 644:87]
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|
|
|
|
node _T_591 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 651:54]
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|
|
|
|
node _T_592 = and(io.dec_tlu_i0_valid_r, _T_591) @[dec_tlu_ctl.scala 651:52]
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|
|
|
|
node _T_593 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 651:75]
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|
|
|
|
node _T_594 = and(_T_593, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 651:110]
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|
|
|
|
node lsu_i0_rfnpc_r = and(_T_592, _T_594) @[dec_tlu_ctl.scala 651:72]
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|
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|
|
node _T_595 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 654:57]
|
|
|
|
|
node _T_596 = and(io.dec_tlu_i0_valid_r, _T_595) @[dec_tlu_ctl.scala 654:55]
|
|
|
|
|
node _T_597 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 654:70]
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|
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|
|
node _T_598 = and(_T_596, _T_597) @[dec_tlu_ctl.scala 654:68]
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|
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|
|
node _T_599 = not(inst_acc_r) @[dec_tlu_ctl.scala 654:87]
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|
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|
|
node _T_600 = and(_T_598, _T_599) @[dec_tlu_ctl.scala 654:84]
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|
|
node _T_601 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 654:101]
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|
|
node _T_602 = and(_T_600, _T_601) @[dec_tlu_ctl.scala 654:99]
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|
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|
|
node _T_603 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 654:126]
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|
|
node _T_604 = and(_T_602, _T_603) @[dec_tlu_ctl.scala 654:124]
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|
node _T_605 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 654:153]
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|
|
node tlu_i0_commit_cmt = and(_T_604, _T_605) @[dec_tlu_ctl.scala 654:151]
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|
|
node _T_606 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 657:43]
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|
|
node _T_607 = or(_T_606, inst_acc_r) @[dec_tlu_ctl.scala 657:58]
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|
|
node _T_608 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 657:84]
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|
|
node _T_609 = or(_T_607, _T_608) @[dec_tlu_ctl.scala 657:71]
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|
|
node _T_610 = or(_T_609, i0_trigger_hit_r) @[dec_tlu_ctl.scala 657:109]
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|
|
tlu_i0_kill_writeb_r <= _T_610 @[dec_tlu_ctl.scala 657:30]
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|
|
|
|
io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 658:42]
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|
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|
|
node _T_611 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 663:49]
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|
|
node _T_612 = and(io.dec_tlu_i0_valid_r, _T_611) @[dec_tlu_ctl.scala 663:47]
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|
|
node _T_613 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 663:103]
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|
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|
|
node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 663:71]
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|
node _T_615 = or(ic_perr_r, iccm_sbecc_r) @[dec_tlu_ctl.scala 663:156]
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|
|
node _T_616 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 663:174]
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|
|
node _T_617 = and(_T_615, _T_616) @[dec_tlu_ctl.scala 663:172]
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|
|
node _T_618 = or(_T_614, _T_617) @[dec_tlu_ctl.scala 663:142]
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|
|
node _T_619 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 663:205]
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|
|
node _T_620 = and(_T_618, _T_619) @[dec_tlu_ctl.scala 663:202]
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|
|
node _T_621 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 663:226]
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|
|
node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 663:223]
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|
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|
|
rfpc_i0_r <= _T_622 @[dec_tlu_ctl.scala 663:19]
|
|
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|
|
node _T_623 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 666:72]
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|
|
node _T_624 = and(iccm_repair_state_d1, _T_623) @[dec_tlu_ctl.scala 666:70]
|
|
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|
|
node _T_625 = or(iccm_sbecc_r, _T_624) @[dec_tlu_ctl.scala 666:46]
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|
|
|
|
iccm_repair_state_ns <= _T_625 @[dec_tlu_ctl.scala 666:30]
|
|
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|
|
node _T_626 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 672:57]
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|
|
|
|
node _T_627 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 672:93]
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|
|
node _T_628 = or(_T_627, mret_r) @[dec_tlu_ctl.scala 672:103]
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|
|
node _T_629 = or(_T_628, take_reset) @[dec_tlu_ctl.scala 672:112]
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|
|
node _T_630 = or(_T_629, illegal_r) @[dec_tlu_ctl.scala 672:125]
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|
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|
|
node _T_631 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 672:181]
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|
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|
|
node _T_632 = and(dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 672:158]
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|
|
node _T_633 = or(_T_630, _T_632) @[dec_tlu_ctl.scala 672:137]
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|
|
node _T_634 = not(_T_633) @[dec_tlu_ctl.scala 672:82]
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|
|
node iccm_repair_state_rfnpc = and(_T_626, _T_634) @[dec_tlu_ctl.scala 672:80]
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|
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|
|
wire dec_tlu_br0_error_r : UInt<1>
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|
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|
|
dec_tlu_br0_error_r <= UInt<1>("h00")
|
|
|
|
|
wire dec_tlu_br0_start_error_r : UInt<1>
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|
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|
|
dec_tlu_br0_start_error_r <= UInt<1>("h00")
|
|
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|
|
wire dec_tlu_br0_v_r : UInt<1>
|
|
|
|
|
dec_tlu_br0_v_r <= UInt<1>("h00")
|
|
|
|
|
node _T_635 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 679:69]
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|
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|
|
node _T_636 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 679:95]
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|
|
node _T_637 = and(_T_635, _T_636) @[dec_tlu_ctl.scala 679:93]
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|
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|
|
dec_tlu_br0_error_r <= _T_637 @[dec_tlu_ctl.scala 679:37]
|
|
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|
|
node _T_638 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 680:81]
|
|
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|
|
node _T_639 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 680:107]
|
|
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|
|
node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 680:105]
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|
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|
|
dec_tlu_br0_start_error_r <= _T_640 @[dec_tlu_ctl.scala 680:43]
|
|
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|
|
node _T_641 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 681:65]
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|
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|
|
node _T_642 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 681:91]
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|
|
|
|
node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 681:89]
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|
|
node _T_644 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 681:116]
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|
|
node _T_645 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 681:145]
|
|
|
|
|
node _T_646 = or(_T_644, _T_645) @[dec_tlu_ctl.scala 681:143]
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|
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|
|
node _T_647 = and(_T_643, _T_646) @[dec_tlu_ctl.scala 681:113]
|
|
|
|
|
dec_tlu_br0_v_r <= _T_647 @[dec_tlu_ctl.scala 681:33]
|
|
|
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 684:73]
|
|
|
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 685:73]
|
|
|
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 686:73]
|
|
|
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 687:73]
|
|
|
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 688:73]
|
|
|
|
|
io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 689:81]
|
|
|
|
|
node _T_648 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 703:57]
|
|
|
|
|
node _T_649 = and(_T_648, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 703:70]
|
|
|
|
|
node _T_650 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 703:96]
|
|
|
|
|
node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 703:94]
|
|
|
|
|
node _T_652 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 703:121]
|
|
|
|
|
node _T_653 = not(_T_652) @[dec_tlu_ctl.scala 703:116]
|
|
|
|
|
node _T_654 = and(_T_651, _T_653) @[dec_tlu_ctl.scala 703:114]
|
|
|
|
|
node _T_655 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 703:138]
|
|
|
|
|
node _T_656 = and(_T_654, _T_655) @[dec_tlu_ctl.scala 703:136]
|
|
|
|
|
ebreak_r <= _T_656 @[dec_tlu_ctl.scala 703:19]
|
|
|
|
|
node _T_657 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 704:57]
|
|
|
|
|
node _T_658 = and(_T_657, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 704:70]
|
|
|
|
|
node _T_659 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 704:96]
|
|
|
|
|
node _T_660 = and(_T_658, _T_659) @[dec_tlu_ctl.scala 704:94]
|
|
|
|
|
node _T_661 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 704:116]
|
|
|
|
|
node _T_662 = and(_T_660, _T_661) @[dec_tlu_ctl.scala 704:114]
|
|
|
|
|
ecall_r <= _T_662 @[dec_tlu_ctl.scala 704:19]
|
|
|
|
|
node _T_663 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 705:23]
|
|
|
|
|
node _T_664 = and(_T_663, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 705:52]
|
|
|
|
|
node _T_665 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 705:78]
|
|
|
|
|
node _T_666 = and(_T_664, _T_665) @[dec_tlu_ctl.scala 705:76]
|
|
|
|
|
node _T_667 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 705:98]
|
|
|
|
|
node _T_668 = and(_T_666, _T_667) @[dec_tlu_ctl.scala 705:96]
|
|
|
|
|
illegal_r <= _T_668 @[dec_tlu_ctl.scala 705:19]
|
|
|
|
|
node _T_669 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 706:57]
|
|
|
|
|
node _T_670 = and(_T_669, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 706:70]
|
|
|
|
|
node _T_671 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 706:96]
|
|
|
|
|
node _T_672 = and(_T_670, _T_671) @[dec_tlu_ctl.scala 706:94]
|
|
|
|
|
node _T_673 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 706:116]
|
|
|
|
|
node _T_674 = and(_T_672, _T_673) @[dec_tlu_ctl.scala 706:114]
|
|
|
|
|
mret_r <= _T_674 @[dec_tlu_ctl.scala 706:19]
|
|
|
|
|
node _T_675 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 708:55]
|
|
|
|
|
node _T_676 = eq(i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 708:81]
|
|
|
|
|
node _T_677 = and(_T_675, _T_676) @[dec_tlu_ctl.scala 708:79]
|
|
|
|
|
node _T_678 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 708:102]
|
|
|
|
|
node _T_679 = and(_T_677, _T_678) @[dec_tlu_ctl.scala 708:100]
|
|
|
|
|
fence_i_r <= _T_679 @[dec_tlu_ctl.scala 708:22]
|
|
|
|
|
node _T_680 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 709:49]
|
|
|
|
|
node _T_681 = and(ifu_ic_error_start_f, _T_680) @[dec_tlu_ctl.scala 709:47]
|
|
|
|
|
node _T_682 = eq(debug_mode_status, UInt<1>("h00")) @[dec_tlu_ctl.scala 709:78]
|
|
|
|
|
node _T_683 = or(_T_682, dcsr_single_step_running) @[dec_tlu_ctl.scala 709:104]
|
|
|
|
|
node _T_684 = and(_T_681, _T_683) @[dec_tlu_ctl.scala 709:75]
|
|
|
|
|
node _T_685 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 709:134]
|
|
|
|
|
node _T_686 = and(_T_684, _T_685) @[dec_tlu_ctl.scala 709:132]
|
|
|
|
|
ic_perr_r <= _T_686 @[dec_tlu_ctl.scala 709:22]
|
|
|
|
|
node _T_687 = not(csr.io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 710:57]
|
|
|
|
|
node _T_688 = and(ifu_iccm_rd_ecc_single_err_f, _T_687) @[dec_tlu_ctl.scala 710:55]
|
|
|
|
|
node _T_689 = eq(debug_mode_status, UInt<1>("h00")) @[dec_tlu_ctl.scala 710:86]
|
|
|
|
|
node _T_690 = or(_T_689, dcsr_single_step_running) @[dec_tlu_ctl.scala 710:112]
|
|
|
|
|
node _T_691 = and(_T_688, _T_690) @[dec_tlu_ctl.scala 710:83]
|
|
|
|
|
node _T_692 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 710:142]
|
|
|
|
|
node _T_693 = and(_T_691, _T_692) @[dec_tlu_ctl.scala 710:140]
|
|
|
|
|
iccm_sbecc_r <= _T_693 @[dec_tlu_ctl.scala 710:22]
|
|
|
|
|
node _T_694 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 712:54]
|
|
|
|
|
inst_acc_r_raw <= _T_694 @[dec_tlu_ctl.scala 712:25]
|
|
|
|
|
node _T_695 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 713:40]
|
|
|
|
|
node _T_696 = and(inst_acc_r_raw, _T_695) @[dec_tlu_ctl.scala 713:38]
|
|
|
|
|
node _T_697 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 713:53]
|
|
|
|
|
node _T_698 = and(_T_696, _T_697) @[dec_tlu_ctl.scala 713:51]
|
|
|
|
|
inst_acc_r <= _T_698 @[dec_tlu_ctl.scala 713:20]
|
|
|
|
|
node _T_699 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 716:69]
|
|
|
|
|
node _T_700 = and(_T_699, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 716:82]
|
|
|
|
|
node _T_701 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 716:108]
|
|
|
|
|
node _T_702 = and(_T_700, _T_701) @[dec_tlu_ctl.scala 716:106]
|
|
|
|
|
node _T_703 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 716:132]
|
|
|
|
|
node _T_704 = and(_T_702, _T_703) @[dec_tlu_ctl.scala 716:126]
|
|
|
|
|
node _T_705 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 716:149]
|
|
|
|
|
node _T_706 = and(_T_704, _T_705) @[dec_tlu_ctl.scala 716:147]
|
|
|
|
|
ebreak_to_debug_mode_r <= _T_706 @[dec_tlu_ctl.scala 716:32]
|
|
|
|
|
reg _T_707 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 718:64]
|
|
|
|
|
_T_707 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 718:64]
|
|
|
|
|
ebreak_to_debug_mode_r_d1 <= _T_707 @[dec_tlu_ctl.scala 718:34]
|
|
|
|
|
io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 719:39]
|
|
|
|
|
int_exc.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 722:49]
|
|
|
|
|
int_exc.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 723:49]
|
|
|
|
|
int_exc.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 724:49]
|
|
|
|
|
int_exc.io.mstatus_mie_ns <= mstatus_mie_ns @[dec_tlu_ctl.scala 725:49]
|
|
|
|
|
int_exc.io.mip <= mip @[dec_tlu_ctl.scala 726:49]
|
|
|
|
|
int_exc.io.mie_ns <= mie_ns @[dec_tlu_ctl.scala 727:49]
|
|
|
|
|
int_exc.io.mret_r <= mret_r @[dec_tlu_ctl.scala 728:49]
|
|
|
|
|
int_exc.io.pmu_fw_tlu_halted_f <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 729:49]
|
|
|
|
|
int_exc.io.int_timer0_int_hold_f <= int_timer0_int_hold_f @[dec_tlu_ctl.scala 730:49]
|
|
|
|
|
int_exc.io.int_timer1_int_hold_f <= int_timer1_int_hold_f @[dec_tlu_ctl.scala 731:49]
|
|
|
|
|
int_exc.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 732:49]
|
|
|
|
|
int_exc.io.dcsr_single_step_running <= dcsr_single_step_running @[dec_tlu_ctl.scala 733:49]
|
|
|
|
|
int_exc.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 734:49]
|
|
|
|
|
int_exc.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 735:49]
|
|
|
|
|
int_exc.io.internal_pmu_fw_halt_mode <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 736:49]
|
|
|
|
|
int_exc.io.i_cpu_halt_req_d1 <= i_cpu_halt_req_d1 @[dec_tlu_ctl.scala 737:49]
|
|
|
|
|
int_exc.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 738:49]
|
|
|
|
|
int_exc.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 739:49]
|
|
|
|
|
int_exc.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 740:49]
|
|
|
|
|
int_exc.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 741:49]
|
|
|
|
|
int_exc.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 742:49]
|
|
|
|
|
int_exc.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 743:49]
|
|
|
|
|
int_exc.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 744:49]
|
|
|
|
|
int_exc.io.nmi_int_detected <= nmi_int_detected @[dec_tlu_ctl.scala 745:49]
|
|
|
|
|
int_exc.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 746:49]
|
|
|
|
|
int_exc.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 747:49]
|
|
|
|
|
int_exc.io.dcsr <= dcsr @[dec_tlu_ctl.scala 748:49]
|
|
|
|
|
int_exc.io.mtvec <= mtvec @[dec_tlu_ctl.scala 749:49]
|
|
|
|
|
int_exc.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 750:49]
|
|
|
|
|
int_exc.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 751:49]
|
|
|
|
|
int_exc.io.pause_expired_r <= pause_expired_r @[dec_tlu_ctl.scala 752:49]
|
|
|
|
|
int_exc.io.nmi_vec <= io.nmi_vec @[dec_tlu_ctl.scala 753:49]
|
|
|
|
|
int_exc.io.lsu_i0_rfnpc_r <= lsu_i0_rfnpc_r @[dec_tlu_ctl.scala 754:49]
|
|
|
|
|
int_exc.io.fence_i_r <= fence_i_r @[dec_tlu_ctl.scala 755:49]
|
|
|
|
|
int_exc.io.iccm_repair_state_rfnpc <= iccm_repair_state_rfnpc @[dec_tlu_ctl.scala 756:49]
|
|
|
|
|
int_exc.io.i_cpu_run_req_d1 <= i_cpu_run_req_d1 @[dec_tlu_ctl.scala 757:49]
|
|
|
|
|
int_exc.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 758:49]
|
|
|
|
|
int_exc.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 759:49]
|
|
|
|
|
int_exc.io.trigger_hit_dmode_r <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 760:49]
|
|
|
|
|
int_exc.io.take_halt <= take_halt @[dec_tlu_ctl.scala 761:49]
|
|
|
|
|
int_exc.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 762:49]
|
|
|
|
|
int_exc.io.lsu_fir_addr <= io.lsu_fir_addr @[dec_tlu_ctl.scala 763:49]
|
|
|
|
|
int_exc.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 764:49]
|
|
|
|
|
int_exc.io.npc_r <= npc_r @[dec_tlu_ctl.scala 765:49]
|
|
|
|
|
int_exc.io.mepc <= mepc @[dec_tlu_ctl.scala 766:49]
|
|
|
|
|
int_exc.io.debug_resume_req_f <= debug_resume_req_f @[dec_tlu_ctl.scala 767:49]
|
|
|
|
|
int_exc.io.dpc <= dpc @[dec_tlu_ctl.scala 768:49]
|
|
|
|
|
int_exc.io.npc_r_d1 <= npc_r_d1 @[dec_tlu_ctl.scala 769:49]
|
|
|
|
|
int_exc.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 770:49]
|
|
|
|
|
int_exc.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 771:49]
|
|
|
|
|
int_exc.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 772:49]
|
|
|
|
|
int_exc.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 773:49]
|
|
|
|
|
int_exc.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 774:49]
|
|
|
|
|
int_exc.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 775:49]
|
|
|
|
|
int_exc.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 776:49]
|
|
|
|
|
int_exc.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 777:49]
|
|
|
|
|
int_exc.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 777:49]
|
|
|
|
|
int_exc.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 777:49]
|
|
|
|
|
int_exc.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 777:49]
|
|
|
|
|
int_exc.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 777:49]
|
|
|
|
|
int_exc.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 777:49]
|
|
|
|
|
int_exc.io.dec_tlu_wr_pause_r_d1 <= dec_tlu_wr_pause_r_d1 @[dec_tlu_ctl.scala 778:42]
|
|
|
|
|
mhwakeup_ready <= int_exc.io.mhwakeup_ready @[dec_tlu_ctl.scala 780:43]
|
|
|
|
|
ext_int_ready <= int_exc.io.ext_int_ready @[dec_tlu_ctl.scala 781:43]
|
|
|
|
|
ce_int_ready <= int_exc.io.ce_int_ready @[dec_tlu_ctl.scala 782:43]
|
|
|
|
|
soft_int_ready <= int_exc.io.soft_int_ready @[dec_tlu_ctl.scala 783:43]
|
|
|
|
|
timer_int_ready <= int_exc.io.timer_int_ready @[dec_tlu_ctl.scala 784:43]
|
|
|
|
|
int_timer0_int_hold <= int_exc.io.int_timer0_int_hold @[dec_tlu_ctl.scala 785:43]
|
|
|
|
|
int_timer1_int_hold <= int_exc.io.int_timer1_int_hold @[dec_tlu_ctl.scala 786:43]
|
|
|
|
|
internal_dbg_halt_timers <= int_exc.io.internal_dbg_halt_timers @[dec_tlu_ctl.scala 787:43]
|
|
|
|
|
take_ext_int_start <= int_exc.io.take_ext_int_start @[dec_tlu_ctl.scala 788:43]
|
|
|
|
|
int_exc.io.ext_int_freeze_d1 <= csr.io.ext_int_freeze_d1 @[dec_tlu_ctl.scala 789:42]
|
|
|
|
|
int_exc.io.take_ext_int_start_d1 <= csr.io.take_ext_int_start_d1 @[dec_tlu_ctl.scala 790:44]
|
|
|
|
|
int_exc.io.take_ext_int_start_d2 <= csr.io.take_ext_int_start_d2 @[dec_tlu_ctl.scala 791:44]
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int_exc.io.take_ext_int_start_d3 <= csr.io.take_ext_int_start_d3 @[dec_tlu_ctl.scala 792:44]
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ext_int_freeze <= int_exc.io.ext_int_freeze @[dec_tlu_ctl.scala 796:43]
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take_ext_int <= int_exc.io.take_ext_int @[dec_tlu_ctl.scala 797:43]
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fast_int_meicpct <= int_exc.io.fast_int_meicpct @[dec_tlu_ctl.scala 798:43]
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ignore_ext_int_due_to_lsu_stall <= int_exc.io.ignore_ext_int_due_to_lsu_stall @[dec_tlu_ctl.scala 799:43]
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take_ce_int <= int_exc.io.take_ce_int @[dec_tlu_ctl.scala 800:43]
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take_soft_int <= int_exc.io.take_soft_int @[dec_tlu_ctl.scala 801:43]
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take_timer_int <= int_exc.io.take_timer_int @[dec_tlu_ctl.scala 802:43]
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take_int_timer0_int <= int_exc.io.take_int_timer0_int @[dec_tlu_ctl.scala 803:43]
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take_int_timer1_int <= int_exc.io.take_int_timer1_int @[dec_tlu_ctl.scala 804:43]
|
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|
take_reset <= int_exc.io.take_reset @[dec_tlu_ctl.scala 805:43]
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take_nmi <= int_exc.io.take_nmi @[dec_tlu_ctl.scala 806:43]
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synchronous_flush_r <= int_exc.io.synchronous_flush_r @[dec_tlu_ctl.scala 807:43]
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tlu_flush_lower_r <= int_exc.io.tlu_flush_lower_r @[dec_tlu_ctl.scala 808:43]
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io.dec_tlu_flush_lower_wb <= int_exc.io.dec_tlu_flush_lower_wb @[dec_tlu_ctl.scala 809:46]
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io.tlu_exu.dec_tlu_flush_lower_r <= int_exc.io.dec_tlu_flush_lower_r @[dec_tlu_ctl.scala 810:54]
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io.tlu_exu.dec_tlu_flush_path_r <= int_exc.io.dec_tlu_flush_path_r @[dec_tlu_ctl.scala 811:54]
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|
|
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|
interrupt_valid_r_d1 <= int_exc.io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 812:43]
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|
|
|
exc_or_int_valid_r_d1 <= int_exc.io.exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 813:43]
|
|
|
|
|
take_nmi_r_d1 <= int_exc.io.take_nmi_r_d1 @[dec_tlu_ctl.scala 814:43]
|
|
|
|
|
pause_expired_wb <= int_exc.io.pause_expired_wb @[dec_tlu_ctl.scala 815:43]
|
|
|
|
|
interrupt_valid_r <= int_exc.io.interrupt_valid_r @[dec_tlu_ctl.scala 816:43]
|
|
|
|
|
csr.io.ext_int_freeze <= int_exc.io.ext_int_freeze @[dec_tlu_ctl.scala 820:32]
|
|
|
|
|
csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 821:50]
|
|
|
|
|
csr.io.free_l2clk <= io.free_l2clk @[dec_tlu_ctl.scala 822:50]
|
|
|
|
|
csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 823:50]
|
|
|
|
|
csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 824:50]
|
|
|
|
|
csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 825:50]
|
|
|
|
|
csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 826:50]
|
|
|
|
|
csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 827:50]
|
|
|
|
|
csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 828:50]
|
|
|
|
|
csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 829:50]
|
|
|
|
|
csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 830:50]
|
|
|
|
|
csr.io.dma_iccm_stall_any <= io.tlu_dma.dma_iccm_stall_any @[dec_tlu_ctl.scala 831:50]
|
|
|
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|
csr.io.dma_dccm_stall_any <= io.tlu_dma.dma_dccm_stall_any @[dec_tlu_ctl.scala 832:50]
|
|
|
|
|
csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 833:50]
|
|
|
|
|
csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 834:50]
|
|
|
|
|
csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 835:50]
|
|
|
|
|
csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 836:50]
|
|
|
|
|
csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 837:50]
|
|
|
|
|
csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 838:50]
|
|
|
|
|
csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 838:50]
|
|
|
|
|
csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 838:50]
|
|
|
|
|
csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 838:50]
|
|
|
|
|
csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 838:50]
|
|
|
|
|
csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 838:50]
|
|
|
|
|
csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 838:50]
|
|
|
|
|
csr.io.dec_tlu_packet_r.icaf_second <= io.dec_tlu_packet_r.icaf_second @[dec_tlu_ctl.scala 838:50]
|
|
|
|
|
csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 838:50]
|
|
|
|
|
csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 838:50]
|
|
|
|
|
csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 839:50]
|
|
|
|
|
csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 840:50]
|
|
|
|
|
csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 841:50]
|
|
|
|
|
csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 842:50]
|
|
|
|
|
csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 843:50]
|
|
|
|
|
csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 844:50]
|
|
|
|
|
csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 845:50]
|
|
|
|
|
csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 846:50]
|
|
|
|
|
csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 847:50]
|
|
|
|
|
csr.io.dma_pmu_dccm_write <= io.tlu_dma.dma_pmu_dccm_write @[dec_tlu_ctl.scala 848:50]
|
|
|
|
|
csr.io.dma_pmu_dccm_read <= io.tlu_dma.dma_pmu_dccm_read @[dec_tlu_ctl.scala 849:50]
|
|
|
|
|
csr.io.dma_pmu_any_write <= io.tlu_dma.dma_pmu_any_write @[dec_tlu_ctl.scala 850:50]
|
|
|
|
|
csr.io.dma_pmu_any_read <= io.tlu_dma.dma_pmu_any_read @[dec_tlu_ctl.scala 851:50]
|
|
|
|
|
csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 852:50]
|
|
|
|
|
csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 853:50]
|
|
|
|
|
csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 854:50]
|
|
|
|
|
csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 855:50]
|
|
|
|
|
csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 856:50]
|
|
|
|
|
csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 857:50]
|
|
|
|
|
csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 858:50]
|
|
|
|
|
csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 859:50]
|
|
|
|
|
csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 860:50]
|
|
|
|
|
csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 861:50]
|
|
|
|
|
csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 862:50]
|
|
|
|
|
csr.io.pic_pl <= io.dec_pic.pic_pl @[dec_tlu_ctl.scala 863:50]
|
|
|
|
|
csr.io.pic_claimid <= io.dec_pic.pic_claimid @[dec_tlu_ctl.scala 864:50]
|
|
|
|
|
csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 865:50]
|
|
|
|
|
csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 866:50]
|
|
|
|
|
csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 867:50]
|
|
|
|
|
csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 868:50]
|
|
|
|
|
csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 869:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 870:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 870:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 870:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 870:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 870:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 870:50]
|
|
|
|
|
csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 871:50]
|
|
|
|
|
csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 872:50]
|
|
|
|
|
csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 873:50]
|
|
|
|
|
csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 874:50]
|
|
|
|
|
csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 875:50]
|
|
|
|
|
csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 876:50]
|
|
|
|
|
csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 877:50]
|
|
|
|
|
io.dec_pic.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 878:58]
|
|
|
|
|
io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 879:58]
|
|
|
|
|
io.dec_pic.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 880:58]
|
|
|
|
|
io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 881:50]
|
|
|
|
|
io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 882:50]
|
|
|
|
|
io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 883:50]
|
|
|
|
|
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 884:58]
|
|
|
|
|
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 884:58]
|
|
|
|
|
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 884:58]
|
|
|
|
|
io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 884:58]
|
|
|
|
|
io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 885:46]
|
|
|
|
|
io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 886:46]
|
|
|
|
|
io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 887:46]
|
|
|
|
|
io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 888:46]
|
|
|
|
|
io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 889:46]
|
|
|
|
|
io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 890:46]
|
|
|
|
|
io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 891:46]
|
|
|
|
|
io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 892:46]
|
|
|
|
|
io.dec_tlu_picio_clk_override <= csr.io.dec_tlu_picio_clk_override @[dec_tlu_ctl.scala 893:46]
|
|
|
|
|
io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 894:46]
|
|
|
|
|
io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 895:46]
|
|
|
|
|
io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 896:46]
|
|
|
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|
io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 897:46]
|
|
|
|
|
io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 898:46]
|
|
|
|
|
io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 899:46]
|
|
|
|
|
io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 900:46]
|
|
|
|
|
io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 901:46]
|
|
|
|
|
io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 902:46]
|
|
|
|
|
io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 903:46]
|
|
|
|
|
io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 904:54]
|
|
|
|
|
io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 905:58]
|
|
|
|
|
io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 906:53]
|
|
|
|
|
io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 907:58]
|
|
|
|
|
io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 908:54]
|
|
|
|
|
io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 909:58]
|
|
|
|
|
io.tlu_dma.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 910:54]
|
|
|
|
|
io.dec_tlu_trace_disable <= csr.io.dec_tlu_trace_disable @[dec_tlu_ctl.scala 911:49]
|
|
|
|
|
csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 912:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 913:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 913:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 913:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 913:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 913:50]
|
|
|
|
|
csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 913:50]
|
|
|
|
|
csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 914:50]
|
|
|
|
|
csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 915:50]
|
|
|
|
|
csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 916:50]
|
|
|
|
|
csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 917:50]
|
|
|
|
|
csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 918:50]
|
|
|
|
|
csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 919:50]
|
|
|
|
|
csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 920:50]
|
|
|
|
|
csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 923:45]
|
|
|
|
|
csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 924:45]
|
|
|
|
|
csr.io.exc_or_int_valid_r <= int_exc.io.exc_or_int_valid_r @[dec_tlu_ctl.scala 925:45]
|
|
|
|
|
csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 926:45]
|
|
|
|
|
csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 927:45]
|
|
|
|
|
csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 928:45]
|
|
|
|
|
csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 929:45]
|
|
|
|
|
csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 930:45]
|
|
|
|
|
csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 931:45]
|
|
|
|
|
csr.io.csr_wr_clk <= clock @[dec_tlu_ctl.scala 932:45]
|
|
|
|
|
csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 933:45]
|
|
|
|
|
csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 934:45]
|
|
|
|
|
csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 935:45]
|
|
|
|
|
csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 936:45]
|
|
|
|
|
csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 937:45]
|
|
|
|
|
csr.io.tlu_flush_path_r_d1 <= int_exc.io.tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 938:45]
|
|
|
|
|
csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 939:45]
|
|
|
|
|
csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 940:45]
|
|
|
|
|
csr.io.i0_exception_valid_r <= int_exc.io.i0_exception_valid_r @[dec_tlu_ctl.scala 941:45]
|
|
|
|
|
csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 942:45]
|
|
|
|
|
csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 943:45]
|
|
|
|
|
csr.io.lsu_single_ecc_error_r <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 944:45]
|
|
|
|
|
csr.io.e4e5_int_clk <= clock @[dec_tlu_ctl.scala 945:45]
|
|
|
|
|
csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 946:45]
|
|
|
|
|
csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 947:45]
|
|
|
|
|
csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_second @[dec_tlu_ctl.scala 948:45]
|
|
|
|
|
csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 949:45]
|
|
|
|
|
csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 950:45]
|
|
|
|
|
csr.io.exc_cause_r <= int_exc.io.exc_cause_r @[dec_tlu_ctl.scala 951:45]
|
|
|
|
|
csr.io.i0_valid_wb <= int_exc.io.i0_valid_wb @[dec_tlu_ctl.scala 952:45]
|
|
|
|
|
csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 953:45]
|
|
|
|
|
csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 954:45]
|
|
|
|
|
csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 955:45]
|
|
|
|
|
csr.io.i0_exception_valid_r_d1 <= int_exc.io.i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 956:45]
|
|
|
|
|
csr.io.exc_cause_wb <= int_exc.io.exc_cause_wb @[dec_tlu_ctl.scala 958:45]
|
|
|
|
|
csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 959:45]
|
|
|
|
|
csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 960:45]
|
|
|
|
|
csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 961:45]
|
|
|
|
|
csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 962:45]
|
|
|
|
|
csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 963:45]
|
|
|
|
|
csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 964:45]
|
|
|
|
|
mdseac_locked_f <= csr.io.mdseac_locked_f @[dec_tlu_ctl.scala 965:27]
|
|
|
|
|
csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 966:45]
|
|
|
|
|
csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 967:45]
|
|
|
|
|
csr.io.ic_perr_r <= ic_perr_r @[dec_tlu_ctl.scala 969:45]
|
|
|
|
|
csr.io.iccm_sbecc_r <= iccm_sbecc_r @[dec_tlu_ctl.scala 970:45]
|
|
|
|
|
csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 972:45]
|
|
|
|
|
csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 973:45]
|
|
|
|
|
csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 974:45]
|
|
|
|
|
csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 975:45]
|
|
|
|
|
csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 976:59]
|
|
|
|
|
csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 977:55]
|
|
|
|
|
csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 978:43]
|
|
|
|
|
csr.io.trigger_hit_r_d1 <= int_exc.io.trigger_hit_r_d1 @[dec_tlu_ctl.scala 979:43]
|
|
|
|
|
csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 980:43]
|
|
|
|
|
csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 981:45]
|
|
|
|
|
csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 982:51]
|
|
|
|
|
csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 983:45]
|
|
|
|
|
csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 984:45]
|
|
|
|
|
csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 985:45]
|
|
|
|
|
csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 986:45]
|
|
|
|
|
csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 987:45]
|
|
|
|
|
csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 988:45]
|
|
|
|
|
csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 989:45]
|
|
|
|
|
csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 990:45]
|
|
|
|
|
csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 991:45]
|
|
|
|
|
csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 992:45]
|
|
|
|
|
csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 993:45]
|
|
|
|
|
csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 994:45]
|
|
|
|
|
csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 995:45]
|
|
|
|
|
csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 996:45]
|
|
|
|
|
csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 997:45]
|
|
|
|
|
csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 998:45]
|
|
|
|
|
csr.io.trigger_enabled <= trigger_enabled @[dec_tlu_ctl.scala 999:45]
|
|
|
|
|
csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 1000:45]
|
|
|
|
|
npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 1002:37]
|
|
|
|
|
npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 1003:37]
|
|
|
|
|
mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 1004:37]
|
|
|
|
|
mepc <= csr.io.mepc @[dec_tlu_ctl.scala 1005:37]
|
|
|
|
|
mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 1006:37]
|
|
|
|
|
force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 1007:37]
|
|
|
|
|
dpc <= csr.io.dpc @[dec_tlu_ctl.scala 1008:37]
|
|
|
|
|
mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 1009:37]
|
|
|
|
|
dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 1010:37]
|
|
|
|
|
fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 1011:37]
|
|
|
|
|
mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 1012:37]
|
|
|
|
|
dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 1013:37]
|
|
|
|
|
mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 1014:37]
|
|
|
|
|
mip <= csr.io.mip @[dec_tlu_ctl.scala 1015:37]
|
|
|
|
|
mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 1016:39]
|
|
|
|
|
mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 1016:39]
|
|
|
|
|
mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 1016:39]
|
|
|
|
|
mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 1016:39]
|
|
|
|
|
inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1017:28]
|
|
|
|
|
csr_read.clock <= clock
|
|
|
|
|
csr_read.reset <= reset
|
|
|
|
|
csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1018:37]
|
|
|
|
|
csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1019:16]
|
|
|
|
|
node _T_708 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1021:50]
|
|
|
|
|
node _T_709 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1021:75]
|
|
|
|
|
node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 1021:73]
|
|
|
|
|
io.dec_tlu_presync_d <= _T_710 @[dec_tlu_ctl.scala 1021:31]
|
|
|
|
|
node _T_711 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1022:51]
|
|
|
|
|
io.dec_tlu_postsync_d <= _T_711 @[dec_tlu_ctl.scala 1022:31]
|
|
|
|
|
node _T_712 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1025:58]
|
|
|
|
|
node _T_713 = or(_T_712, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1025:80]
|
|
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|
|
node _T_714 = or(_T_713, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1025:100]
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|
node _T_715 = or(_T_714, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1025:120]
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|
node _T_716 = or(_T_715, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1025:142]
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|
node _T_717 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1025:167]
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|
node conditionally_illegal = and(_T_716, _T_717) @[dec_tlu_ctl.scala 1025:165]
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|
node _T_718 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1026:63]
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node _T_719 = or(_T_718, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1026:81]
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|
node _T_720 = or(_T_719, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1026:100]
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|
node _T_721 = or(_T_720, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1026:123]
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|
node _T_722 = or(_T_721, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1026:144]
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|
node _T_723 = or(_T_722, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1026:166]
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|
node _T_724 = or(_T_723, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1026:187]
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|
node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 1026:44]
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|
node _T_726 = or(_T_725, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1026:209]
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|
node _T_727 = and(csr_pkt.legal, _T_726) @[dec_tlu_ctl.scala 1026:41]
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|
node _T_728 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1026:231]
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|
node _T_729 = and(_T_727, _T_728) @[dec_tlu_ctl.scala 1026:229]
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node _T_730 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1026:251]
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|
node valid_csr = and(_T_729, _T_730) @[dec_tlu_ctl.scala 1026:249]
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|
node _T_731 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1028:54]
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node _T_732 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1028:115]
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|
node _T_733 = or(_T_732, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1028:137]
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|
node _T_734 = or(_T_733, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1028:158]
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|
node _T_735 = or(_T_734, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1028:180]
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|
node _T_736 = or(_T_735, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1028:201]
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|
node _T_737 = and(io.dec_csr_wen_unq_d, _T_736) @[dec_tlu_ctl.scala 1028:90]
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|
node _T_738 = not(_T_737) @[dec_tlu_ctl.scala 1028:67]
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|
node _T_739 = and(_T_731, _T_738) @[dec_tlu_ctl.scala 1028:65]
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|
io.dec_csr_legal_d <= _T_739 @[dec_tlu_ctl.scala 1028:28]
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module dec_trigger :
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|
input clock : Clock
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|
input reset : Reset
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|
output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>}
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node _T = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[dec_trigger.scala 14:63]
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node _T_1 = and(_T, io.trigger_pkt_any[0].execute) @[dec_trigger.scala 14:93]
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wire _T_2 : UInt<1>[32] @[lib.scala 12:48]
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_T_2[0] <= _T_1 @[lib.scala 12:48]
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|
_T_2[1] <= _T_1 @[lib.scala 12:48]
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|
_T_2[2] <= _T_1 @[lib.scala 12:48]
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|
_T_2[3] <= _T_1 @[lib.scala 12:48]
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|
_T_2[4] <= _T_1 @[lib.scala 12:48]
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|
_T_2[5] <= _T_1 @[lib.scala 12:48]
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|
_T_2[6] <= _T_1 @[lib.scala 12:48]
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|
_T_2[7] <= _T_1 @[lib.scala 12:48]
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|
_T_2[8] <= _T_1 @[lib.scala 12:48]
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|
_T_2[9] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[10] <= _T_1 @[lib.scala 12:48]
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|
_T_2[11] <= _T_1 @[lib.scala 12:48]
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|
_T_2[12] <= _T_1 @[lib.scala 12:48]
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|
_T_2[13] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[14] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[15] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[16] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[17] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[18] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[19] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[20] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[21] <= _T_1 @[lib.scala 12:48]
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|
_T_2[22] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[23] <= _T_1 @[lib.scala 12:48]
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|
|
|
_T_2[24] <= _T_1 @[lib.scala 12:48]
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|
|
|
_T_2[25] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[26] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[27] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[28] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[29] <= _T_1 @[lib.scala 12:48]
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|
|
|
_T_2[30] <= _T_1 @[lib.scala 12:48]
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|
|
_T_2[31] <= _T_1 @[lib.scala 12:48]
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|
node _T_3 = cat(_T_2[0], _T_2[1]) @[Cat.scala 29:58]
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|
node _T_4 = cat(_T_3, _T_2[2]) @[Cat.scala 29:58]
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|
node _T_5 = cat(_T_4, _T_2[3]) @[Cat.scala 29:58]
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|
node _T_6 = cat(_T_5, _T_2[4]) @[Cat.scala 29:58]
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|
node _T_7 = cat(_T_6, _T_2[5]) @[Cat.scala 29:58]
|
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|
node _T_8 = cat(_T_7, _T_2[6]) @[Cat.scala 29:58]
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|
node _T_9 = cat(_T_8, _T_2[7]) @[Cat.scala 29:58]
|
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|
node _T_10 = cat(_T_9, _T_2[8]) @[Cat.scala 29:58]
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|
node _T_11 = cat(_T_10, _T_2[9]) @[Cat.scala 29:58]
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|
node _T_12 = cat(_T_11, _T_2[10]) @[Cat.scala 29:58]
|
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|
node _T_13 = cat(_T_12, _T_2[11]) @[Cat.scala 29:58]
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|
node _T_14 = cat(_T_13, _T_2[12]) @[Cat.scala 29:58]
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|
node _T_15 = cat(_T_14, _T_2[13]) @[Cat.scala 29:58]
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|
node _T_16 = cat(_T_15, _T_2[14]) @[Cat.scala 29:58]
|
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|
node _T_17 = cat(_T_16, _T_2[15]) @[Cat.scala 29:58]
|
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|
node _T_18 = cat(_T_17, _T_2[16]) @[Cat.scala 29:58]
|
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|
|
node _T_19 = cat(_T_18, _T_2[17]) @[Cat.scala 29:58]
|
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|
node _T_20 = cat(_T_19, _T_2[18]) @[Cat.scala 29:58]
|
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|
|
node _T_21 = cat(_T_20, _T_2[19]) @[Cat.scala 29:58]
|
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|
node _T_22 = cat(_T_21, _T_2[20]) @[Cat.scala 29:58]
|
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|
node _T_23 = cat(_T_22, _T_2[21]) @[Cat.scala 29:58]
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|
node _T_24 = cat(_T_23, _T_2[22]) @[Cat.scala 29:58]
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|
node _T_25 = cat(_T_24, _T_2[23]) @[Cat.scala 29:58]
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|
node _T_26 = cat(_T_25, _T_2[24]) @[Cat.scala 29:58]
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|
node _T_27 = cat(_T_26, _T_2[25]) @[Cat.scala 29:58]
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|
node _T_28 = cat(_T_27, _T_2[26]) @[Cat.scala 29:58]
|
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|
node _T_29 = cat(_T_28, _T_2[27]) @[Cat.scala 29:58]
|
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|
node _T_30 = cat(_T_29, _T_2[28]) @[Cat.scala 29:58]
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|
node _T_31 = cat(_T_30, _T_2[29]) @[Cat.scala 29:58]
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|
|
node _T_32 = cat(_T_31, _T_2[30]) @[Cat.scala 29:58]
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|
|
node _T_33 = cat(_T_32, _T_2[31]) @[Cat.scala 29:58]
|
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|
|
node _T_34 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[dec_trigger.scala 14:177]
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|
|
node _T_35 = cat(io.dec_i0_pc_d, _T_34) @[Cat.scala 29:58]
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|
|
node _T_36 = and(_T_33, _T_35) @[dec_trigger.scala 14:127]
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|
|
node _T_37 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[dec_trigger.scala 14:63]
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|
|
node _T_38 = and(_T_37, io.trigger_pkt_any[1].execute) @[dec_trigger.scala 14:93]
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|
|
wire _T_39 : UInt<1>[32] @[lib.scala 12:48]
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|
|
|
_T_39[0] <= _T_38 @[lib.scala 12:48]
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|
|
|
|
_T_39[1] <= _T_38 @[lib.scala 12:48]
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|
|
|
|
_T_39[2] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[3] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[4] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[5] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[6] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[7] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[8] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[9] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[10] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[11] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[12] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[13] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[14] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[15] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[16] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[17] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[18] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[19] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[20] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[21] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[22] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[23] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[24] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[25] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[26] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[27] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[28] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[29] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[30] <= _T_38 @[lib.scala 12:48]
|
|
|
|
|
_T_39[31] <= _T_38 @[lib.scala 12:48]
|
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|
|
node _T_40 = cat(_T_39[0], _T_39[1]) @[Cat.scala 29:58]
|
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|
node _T_41 = cat(_T_40, _T_39[2]) @[Cat.scala 29:58]
|
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|
|
node _T_42 = cat(_T_41, _T_39[3]) @[Cat.scala 29:58]
|
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|
|
node _T_43 = cat(_T_42, _T_39[4]) @[Cat.scala 29:58]
|
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|
node _T_44 = cat(_T_43, _T_39[5]) @[Cat.scala 29:58]
|
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|
|
node _T_45 = cat(_T_44, _T_39[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_46 = cat(_T_45, _T_39[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_47 = cat(_T_46, _T_39[8]) @[Cat.scala 29:58]
|
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|
|
node _T_48 = cat(_T_47, _T_39[9]) @[Cat.scala 29:58]
|
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|
|
node _T_49 = cat(_T_48, _T_39[10]) @[Cat.scala 29:58]
|
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|
|
node _T_50 = cat(_T_49, _T_39[11]) @[Cat.scala 29:58]
|
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|
|
|
node _T_51 = cat(_T_50, _T_39[12]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_52 = cat(_T_51, _T_39[13]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_53 = cat(_T_52, _T_39[14]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_54 = cat(_T_53, _T_39[15]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_55 = cat(_T_54, _T_39[16]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_56 = cat(_T_55, _T_39[17]) @[Cat.scala 29:58]
|
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|
|
|
node _T_57 = cat(_T_56, _T_39[18]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_58 = cat(_T_57, _T_39[19]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_59 = cat(_T_58, _T_39[20]) @[Cat.scala 29:58]
|
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|
|
|
node _T_60 = cat(_T_59, _T_39[21]) @[Cat.scala 29:58]
|
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|
|
|
node _T_61 = cat(_T_60, _T_39[22]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_62 = cat(_T_61, _T_39[23]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_63 = cat(_T_62, _T_39[24]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_64 = cat(_T_63, _T_39[25]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_65 = cat(_T_64, _T_39[26]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_66 = cat(_T_65, _T_39[27]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_67 = cat(_T_66, _T_39[28]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_68 = cat(_T_67, _T_39[29]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_69 = cat(_T_68, _T_39[30]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_70 = cat(_T_69, _T_39[31]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_71 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[dec_trigger.scala 14:177]
|
|
|
|
|
node _T_72 = cat(io.dec_i0_pc_d, _T_71) @[Cat.scala 29:58]
|
|
|
|
|
node _T_73 = and(_T_70, _T_72) @[dec_trigger.scala 14:127]
|
|
|
|
|
node _T_74 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[dec_trigger.scala 14:63]
|
|
|
|
|
node _T_75 = and(_T_74, io.trigger_pkt_any[2].execute) @[dec_trigger.scala 14:93]
|
|
|
|
|
wire _T_76 : UInt<1>[32] @[lib.scala 12:48]
|
|
|
|
|
_T_76[0] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[1] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[2] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[3] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[4] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[5] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[6] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[7] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[8] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[9] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[10] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[11] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[12] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[13] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[14] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[15] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[16] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[17] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[18] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[19] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[20] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[21] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[22] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[23] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[24] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[25] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[26] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[27] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[28] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[29] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[30] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
_T_76[31] <= _T_75 @[lib.scala 12:48]
|
|
|
|
|
node _T_77 = cat(_T_76[0], _T_76[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_78 = cat(_T_77, _T_76[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_79 = cat(_T_78, _T_76[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_80 = cat(_T_79, _T_76[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_81 = cat(_T_80, _T_76[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_82 = cat(_T_81, _T_76[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_83 = cat(_T_82, _T_76[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_84 = cat(_T_83, _T_76[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_85 = cat(_T_84, _T_76[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_86 = cat(_T_85, _T_76[10]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_87 = cat(_T_86, _T_76[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_88 = cat(_T_87, _T_76[12]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_89 = cat(_T_88, _T_76[13]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_90 = cat(_T_89, _T_76[14]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_91 = cat(_T_90, _T_76[15]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_92 = cat(_T_91, _T_76[16]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_93 = cat(_T_92, _T_76[17]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_94 = cat(_T_93, _T_76[18]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_95 = cat(_T_94, _T_76[19]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_96 = cat(_T_95, _T_76[20]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_97 = cat(_T_96, _T_76[21]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_98 = cat(_T_97, _T_76[22]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_99 = cat(_T_98, _T_76[23]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_100 = cat(_T_99, _T_76[24]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_101 = cat(_T_100, _T_76[25]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_102 = cat(_T_101, _T_76[26]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_103 = cat(_T_102, _T_76[27]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_104 = cat(_T_103, _T_76[28]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_105 = cat(_T_104, _T_76[29]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_106 = cat(_T_105, _T_76[30]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_107 = cat(_T_106, _T_76[31]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_108 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[dec_trigger.scala 14:177]
|
|
|
|
|
node _T_109 = cat(io.dec_i0_pc_d, _T_108) @[Cat.scala 29:58]
|
|
|
|
|
node _T_110 = and(_T_107, _T_109) @[dec_trigger.scala 14:127]
|
|
|
|
|
node _T_111 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[dec_trigger.scala 14:63]
|
|
|
|
|
node _T_112 = and(_T_111, io.trigger_pkt_any[3].execute) @[dec_trigger.scala 14:93]
|
|
|
|
|
wire _T_113 : UInt<1>[32] @[lib.scala 12:48]
|
|
|
|
|
_T_113[0] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[1] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[2] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[3] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[4] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[5] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[6] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[7] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[8] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[9] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[10] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[11] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[12] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[13] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[14] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[15] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[16] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[17] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[18] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[19] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[20] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[21] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[22] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[23] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[24] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[25] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[26] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[27] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[28] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[29] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[30] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
_T_113[31] <= _T_112 @[lib.scala 12:48]
|
|
|
|
|
node _T_114 = cat(_T_113[0], _T_113[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_115 = cat(_T_114, _T_113[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_116 = cat(_T_115, _T_113[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_117 = cat(_T_116, _T_113[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_118 = cat(_T_117, _T_113[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_119 = cat(_T_118, _T_113[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_120 = cat(_T_119, _T_113[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_121 = cat(_T_120, _T_113[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_122 = cat(_T_121, _T_113[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_123 = cat(_T_122, _T_113[10]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_124 = cat(_T_123, _T_113[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_125 = cat(_T_124, _T_113[12]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_126 = cat(_T_125, _T_113[13]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_127 = cat(_T_126, _T_113[14]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_128 = cat(_T_127, _T_113[15]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_129 = cat(_T_128, _T_113[16]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_130 = cat(_T_129, _T_113[17]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_131 = cat(_T_130, _T_113[18]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_132 = cat(_T_131, _T_113[19]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_133 = cat(_T_132, _T_113[20]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_134 = cat(_T_133, _T_113[21]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_135 = cat(_T_134, _T_113[22]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_136 = cat(_T_135, _T_113[23]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_137 = cat(_T_136, _T_113[24]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_138 = cat(_T_137, _T_113[25]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_139 = cat(_T_138, _T_113[26]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_140 = cat(_T_139, _T_113[27]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_141 = cat(_T_140, _T_113[28]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_142 = cat(_T_141, _T_113[29]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_143 = cat(_T_142, _T_113[30]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_144 = cat(_T_143, _T_113[31]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_145 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[dec_trigger.scala 14:177]
|
|
|
|
|
node _T_146 = cat(io.dec_i0_pc_d, _T_145) @[Cat.scala 29:58]
|
|
|
|
|
node _T_147 = and(_T_144, _T_146) @[dec_trigger.scala 14:127]
|
|
|
|
|
wire dec_i0_match_data : UInt<32>[4] @[dec_trigger.scala 14:46]
|
|
|
|
|
dec_i0_match_data[0] <= _T_36 @[dec_trigger.scala 14:46]
|
|
|
|
|
dec_i0_match_data[1] <= _T_73 @[dec_trigger.scala 14:46]
|
|
|
|
|
dec_i0_match_data[2] <= _T_110 @[dec_trigger.scala 14:46]
|
|
|
|
|
dec_i0_match_data[3] <= _T_147 @[dec_trigger.scala 14:46]
|
|
|
|
|
node _T_148 = and(io.trigger_pkt_any[0].execute, io.trigger_pkt_any[0].m) @[dec_trigger.scala 15:83]
|
|
|
|
|
node _T_149 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[dec_trigger.scala 15:216]
|
|
|
|
|
wire _T_150 : UInt<1>[32] @[lib.scala 100:24]
|
|
|
|
|
node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[lib.scala 101:45]
|
|
|
|
|
node _T_152 = not(_T_151) @[lib.scala 101:39]
|
|
|
|
|
node _T_153 = and(_T_149, _T_152) @[lib.scala 101:37]
|
|
|
|
|
node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 102:48]
|
|
|
|
|
node _T_155 = bits(dec_i0_match_data[0], 0, 0) @[lib.scala 102:60]
|
|
|
|
|
node _T_156 = eq(_T_154, _T_155) @[lib.scala 102:52]
|
|
|
|
|
node _T_157 = or(_T_153, _T_156) @[lib.scala 102:41]
|
|
|
|
|
_T_150[0] <= _T_157 @[lib.scala 102:18]
|
|
|
|
|
node _T_158 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_159 = andr(_T_158) @[lib.scala 104:36]
|
|
|
|
|
node _T_160 = and(_T_159, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[lib.scala 104:74]
|
|
|
|
|
node _T_162 = bits(dec_i0_match_data[0], 1, 1) @[lib.scala 104:86]
|
|
|
|
|
node _T_163 = eq(_T_161, _T_162) @[lib.scala 104:78]
|
|
|
|
|
node _T_164 = mux(_T_160, UInt<1>("h01"), _T_163) @[lib.scala 104:23]
|
|
|
|
|
_T_150[1] <= _T_164 @[lib.scala 104:17]
|
|
|
|
|
node _T_165 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_166 = andr(_T_165) @[lib.scala 104:36]
|
|
|
|
|
node _T_167 = and(_T_166, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[lib.scala 104:74]
|
|
|
|
|
node _T_169 = bits(dec_i0_match_data[0], 2, 2) @[lib.scala 104:86]
|
|
|
|
|
node _T_170 = eq(_T_168, _T_169) @[lib.scala 104:78]
|
|
|
|
|
node _T_171 = mux(_T_167, UInt<1>("h01"), _T_170) @[lib.scala 104:23]
|
|
|
|
|
_T_150[2] <= _T_171 @[lib.scala 104:17]
|
|
|
|
|
node _T_172 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_173 = andr(_T_172) @[lib.scala 104:36]
|
|
|
|
|
node _T_174 = and(_T_173, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[lib.scala 104:74]
|
|
|
|
|
node _T_176 = bits(dec_i0_match_data[0], 3, 3) @[lib.scala 104:86]
|
|
|
|
|
node _T_177 = eq(_T_175, _T_176) @[lib.scala 104:78]
|
|
|
|
|
node _T_178 = mux(_T_174, UInt<1>("h01"), _T_177) @[lib.scala 104:23]
|
|
|
|
|
_T_150[3] <= _T_178 @[lib.scala 104:17]
|
|
|
|
|
node _T_179 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_180 = andr(_T_179) @[lib.scala 104:36]
|
|
|
|
|
node _T_181 = and(_T_180, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[lib.scala 104:74]
|
|
|
|
|
node _T_183 = bits(dec_i0_match_data[0], 4, 4) @[lib.scala 104:86]
|
|
|
|
|
node _T_184 = eq(_T_182, _T_183) @[lib.scala 104:78]
|
|
|
|
|
node _T_185 = mux(_T_181, UInt<1>("h01"), _T_184) @[lib.scala 104:23]
|
|
|
|
|
_T_150[4] <= _T_185 @[lib.scala 104:17]
|
|
|
|
|
node _T_186 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_187 = andr(_T_186) @[lib.scala 104:36]
|
|
|
|
|
node _T_188 = and(_T_187, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[lib.scala 104:74]
|
|
|
|
|
node _T_190 = bits(dec_i0_match_data[0], 5, 5) @[lib.scala 104:86]
|
|
|
|
|
node _T_191 = eq(_T_189, _T_190) @[lib.scala 104:78]
|
|
|
|
|
node _T_192 = mux(_T_188, UInt<1>("h01"), _T_191) @[lib.scala 104:23]
|
|
|
|
|
_T_150[5] <= _T_192 @[lib.scala 104:17]
|
|
|
|
|
node _T_193 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_194 = andr(_T_193) @[lib.scala 104:36]
|
|
|
|
|
node _T_195 = and(_T_194, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[lib.scala 104:74]
|
|
|
|
|
node _T_197 = bits(dec_i0_match_data[0], 6, 6) @[lib.scala 104:86]
|
|
|
|
|
node _T_198 = eq(_T_196, _T_197) @[lib.scala 104:78]
|
|
|
|
|
node _T_199 = mux(_T_195, UInt<1>("h01"), _T_198) @[lib.scala 104:23]
|
|
|
|
|
_T_150[6] <= _T_199 @[lib.scala 104:17]
|
|
|
|
|
node _T_200 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_201 = andr(_T_200) @[lib.scala 104:36]
|
|
|
|
|
node _T_202 = and(_T_201, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[lib.scala 104:74]
|
|
|
|
|
node _T_204 = bits(dec_i0_match_data[0], 7, 7) @[lib.scala 104:86]
|
|
|
|
|
node _T_205 = eq(_T_203, _T_204) @[lib.scala 104:78]
|
|
|
|
|
node _T_206 = mux(_T_202, UInt<1>("h01"), _T_205) @[lib.scala 104:23]
|
|
|
|
|
_T_150[7] <= _T_206 @[lib.scala 104:17]
|
|
|
|
|
node _T_207 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_208 = andr(_T_207) @[lib.scala 104:36]
|
|
|
|
|
node _T_209 = and(_T_208, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[lib.scala 104:74]
|
|
|
|
|
node _T_211 = bits(dec_i0_match_data[0], 8, 8) @[lib.scala 104:86]
|
|
|
|
|
node _T_212 = eq(_T_210, _T_211) @[lib.scala 104:78]
|
|
|
|
|
node _T_213 = mux(_T_209, UInt<1>("h01"), _T_212) @[lib.scala 104:23]
|
|
|
|
|
_T_150[8] <= _T_213 @[lib.scala 104:17]
|
|
|
|
|
node _T_214 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_215 = andr(_T_214) @[lib.scala 104:36]
|
|
|
|
|
node _T_216 = and(_T_215, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[lib.scala 104:74]
|
|
|
|
|
node _T_218 = bits(dec_i0_match_data[0], 9, 9) @[lib.scala 104:86]
|
|
|
|
|
node _T_219 = eq(_T_217, _T_218) @[lib.scala 104:78]
|
|
|
|
|
node _T_220 = mux(_T_216, UInt<1>("h01"), _T_219) @[lib.scala 104:23]
|
|
|
|
|
_T_150[9] <= _T_220 @[lib.scala 104:17]
|
|
|
|
|
node _T_221 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_222 = andr(_T_221) @[lib.scala 104:36]
|
|
|
|
|
node _T_223 = and(_T_222, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[lib.scala 104:74]
|
|
|
|
|
node _T_225 = bits(dec_i0_match_data[0], 10, 10) @[lib.scala 104:86]
|
|
|
|
|
node _T_226 = eq(_T_224, _T_225) @[lib.scala 104:78]
|
|
|
|
|
node _T_227 = mux(_T_223, UInt<1>("h01"), _T_226) @[lib.scala 104:23]
|
|
|
|
|
_T_150[10] <= _T_227 @[lib.scala 104:17]
|
|
|
|
|
node _T_228 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_229 = andr(_T_228) @[lib.scala 104:36]
|
|
|
|
|
node _T_230 = and(_T_229, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[lib.scala 104:74]
|
|
|
|
|
node _T_232 = bits(dec_i0_match_data[0], 11, 11) @[lib.scala 104:86]
|
|
|
|
|
node _T_233 = eq(_T_231, _T_232) @[lib.scala 104:78]
|
|
|
|
|
node _T_234 = mux(_T_230, UInt<1>("h01"), _T_233) @[lib.scala 104:23]
|
|
|
|
|
_T_150[11] <= _T_234 @[lib.scala 104:17]
|
|
|
|
|
node _T_235 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_236 = andr(_T_235) @[lib.scala 104:36]
|
|
|
|
|
node _T_237 = and(_T_236, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[lib.scala 104:74]
|
|
|
|
|
node _T_239 = bits(dec_i0_match_data[0], 12, 12) @[lib.scala 104:86]
|
|
|
|
|
node _T_240 = eq(_T_238, _T_239) @[lib.scala 104:78]
|
|
|
|
|
node _T_241 = mux(_T_237, UInt<1>("h01"), _T_240) @[lib.scala 104:23]
|
|
|
|
|
_T_150[12] <= _T_241 @[lib.scala 104:17]
|
|
|
|
|
node _T_242 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_243 = andr(_T_242) @[lib.scala 104:36]
|
|
|
|
|
node _T_244 = and(_T_243, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[lib.scala 104:74]
|
|
|
|
|
node _T_246 = bits(dec_i0_match_data[0], 13, 13) @[lib.scala 104:86]
|
|
|
|
|
node _T_247 = eq(_T_245, _T_246) @[lib.scala 104:78]
|
|
|
|
|
node _T_248 = mux(_T_244, UInt<1>("h01"), _T_247) @[lib.scala 104:23]
|
|
|
|
|
_T_150[13] <= _T_248 @[lib.scala 104:17]
|
|
|
|
|
node _T_249 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_250 = andr(_T_249) @[lib.scala 104:36]
|
|
|
|
|
node _T_251 = and(_T_250, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[lib.scala 104:74]
|
|
|
|
|
node _T_253 = bits(dec_i0_match_data[0], 14, 14) @[lib.scala 104:86]
|
|
|
|
|
node _T_254 = eq(_T_252, _T_253) @[lib.scala 104:78]
|
|
|
|
|
node _T_255 = mux(_T_251, UInt<1>("h01"), _T_254) @[lib.scala 104:23]
|
|
|
|
|
_T_150[14] <= _T_255 @[lib.scala 104:17]
|
|
|
|
|
node _T_256 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_257 = andr(_T_256) @[lib.scala 104:36]
|
|
|
|
|
node _T_258 = and(_T_257, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[lib.scala 104:74]
|
|
|
|
|
node _T_260 = bits(dec_i0_match_data[0], 15, 15) @[lib.scala 104:86]
|
|
|
|
|
node _T_261 = eq(_T_259, _T_260) @[lib.scala 104:78]
|
|
|
|
|
node _T_262 = mux(_T_258, UInt<1>("h01"), _T_261) @[lib.scala 104:23]
|
|
|
|
|
_T_150[15] <= _T_262 @[lib.scala 104:17]
|
|
|
|
|
node _T_263 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_264 = andr(_T_263) @[lib.scala 104:36]
|
|
|
|
|
node _T_265 = and(_T_264, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[lib.scala 104:74]
|
|
|
|
|
node _T_267 = bits(dec_i0_match_data[0], 16, 16) @[lib.scala 104:86]
|
|
|
|
|
node _T_268 = eq(_T_266, _T_267) @[lib.scala 104:78]
|
|
|
|
|
node _T_269 = mux(_T_265, UInt<1>("h01"), _T_268) @[lib.scala 104:23]
|
|
|
|
|
_T_150[16] <= _T_269 @[lib.scala 104:17]
|
|
|
|
|
node _T_270 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_271 = andr(_T_270) @[lib.scala 104:36]
|
|
|
|
|
node _T_272 = and(_T_271, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_273 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[lib.scala 104:74]
|
|
|
|
|
node _T_274 = bits(dec_i0_match_data[0], 17, 17) @[lib.scala 104:86]
|
|
|
|
|
node _T_275 = eq(_T_273, _T_274) @[lib.scala 104:78]
|
|
|
|
|
node _T_276 = mux(_T_272, UInt<1>("h01"), _T_275) @[lib.scala 104:23]
|
|
|
|
|
_T_150[17] <= _T_276 @[lib.scala 104:17]
|
|
|
|
|
node _T_277 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_278 = andr(_T_277) @[lib.scala 104:36]
|
|
|
|
|
node _T_279 = and(_T_278, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_280 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[lib.scala 104:74]
|
|
|
|
|
node _T_281 = bits(dec_i0_match_data[0], 18, 18) @[lib.scala 104:86]
|
|
|
|
|
node _T_282 = eq(_T_280, _T_281) @[lib.scala 104:78]
|
|
|
|
|
node _T_283 = mux(_T_279, UInt<1>("h01"), _T_282) @[lib.scala 104:23]
|
|
|
|
|
_T_150[18] <= _T_283 @[lib.scala 104:17]
|
|
|
|
|
node _T_284 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_285 = andr(_T_284) @[lib.scala 104:36]
|
|
|
|
|
node _T_286 = and(_T_285, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_287 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[lib.scala 104:74]
|
|
|
|
|
node _T_288 = bits(dec_i0_match_data[0], 19, 19) @[lib.scala 104:86]
|
|
|
|
|
node _T_289 = eq(_T_287, _T_288) @[lib.scala 104:78]
|
|
|
|
|
node _T_290 = mux(_T_286, UInt<1>("h01"), _T_289) @[lib.scala 104:23]
|
|
|
|
|
_T_150[19] <= _T_290 @[lib.scala 104:17]
|
|
|
|
|
node _T_291 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_292 = andr(_T_291) @[lib.scala 104:36]
|
|
|
|
|
node _T_293 = and(_T_292, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_294 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[lib.scala 104:74]
|
|
|
|
|
node _T_295 = bits(dec_i0_match_data[0], 20, 20) @[lib.scala 104:86]
|
|
|
|
|
node _T_296 = eq(_T_294, _T_295) @[lib.scala 104:78]
|
|
|
|
|
node _T_297 = mux(_T_293, UInt<1>("h01"), _T_296) @[lib.scala 104:23]
|
|
|
|
|
_T_150[20] <= _T_297 @[lib.scala 104:17]
|
|
|
|
|
node _T_298 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_299 = andr(_T_298) @[lib.scala 104:36]
|
|
|
|
|
node _T_300 = and(_T_299, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_301 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[lib.scala 104:74]
|
|
|
|
|
node _T_302 = bits(dec_i0_match_data[0], 21, 21) @[lib.scala 104:86]
|
|
|
|
|
node _T_303 = eq(_T_301, _T_302) @[lib.scala 104:78]
|
|
|
|
|
node _T_304 = mux(_T_300, UInt<1>("h01"), _T_303) @[lib.scala 104:23]
|
|
|
|
|
_T_150[21] <= _T_304 @[lib.scala 104:17]
|
|
|
|
|
node _T_305 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_306 = andr(_T_305) @[lib.scala 104:36]
|
|
|
|
|
node _T_307 = and(_T_306, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_308 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[lib.scala 104:74]
|
|
|
|
|
node _T_309 = bits(dec_i0_match_data[0], 22, 22) @[lib.scala 104:86]
|
|
|
|
|
node _T_310 = eq(_T_308, _T_309) @[lib.scala 104:78]
|
|
|
|
|
node _T_311 = mux(_T_307, UInt<1>("h01"), _T_310) @[lib.scala 104:23]
|
|
|
|
|
_T_150[22] <= _T_311 @[lib.scala 104:17]
|
|
|
|
|
node _T_312 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_313 = andr(_T_312) @[lib.scala 104:36]
|
|
|
|
|
node _T_314 = and(_T_313, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_315 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[lib.scala 104:74]
|
|
|
|
|
node _T_316 = bits(dec_i0_match_data[0], 23, 23) @[lib.scala 104:86]
|
|
|
|
|
node _T_317 = eq(_T_315, _T_316) @[lib.scala 104:78]
|
|
|
|
|
node _T_318 = mux(_T_314, UInt<1>("h01"), _T_317) @[lib.scala 104:23]
|
|
|
|
|
_T_150[23] <= _T_318 @[lib.scala 104:17]
|
|
|
|
|
node _T_319 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_320 = andr(_T_319) @[lib.scala 104:36]
|
|
|
|
|
node _T_321 = and(_T_320, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_322 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[lib.scala 104:74]
|
|
|
|
|
node _T_323 = bits(dec_i0_match_data[0], 24, 24) @[lib.scala 104:86]
|
|
|
|
|
node _T_324 = eq(_T_322, _T_323) @[lib.scala 104:78]
|
|
|
|
|
node _T_325 = mux(_T_321, UInt<1>("h01"), _T_324) @[lib.scala 104:23]
|
|
|
|
|
_T_150[24] <= _T_325 @[lib.scala 104:17]
|
|
|
|
|
node _T_326 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_327 = andr(_T_326) @[lib.scala 104:36]
|
|
|
|
|
node _T_328 = and(_T_327, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_329 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[lib.scala 104:74]
|
|
|
|
|
node _T_330 = bits(dec_i0_match_data[0], 25, 25) @[lib.scala 104:86]
|
|
|
|
|
node _T_331 = eq(_T_329, _T_330) @[lib.scala 104:78]
|
|
|
|
|
node _T_332 = mux(_T_328, UInt<1>("h01"), _T_331) @[lib.scala 104:23]
|
|
|
|
|
_T_150[25] <= _T_332 @[lib.scala 104:17]
|
|
|
|
|
node _T_333 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_334 = andr(_T_333) @[lib.scala 104:36]
|
|
|
|
|
node _T_335 = and(_T_334, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_336 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[lib.scala 104:74]
|
|
|
|
|
node _T_337 = bits(dec_i0_match_data[0], 26, 26) @[lib.scala 104:86]
|
|
|
|
|
node _T_338 = eq(_T_336, _T_337) @[lib.scala 104:78]
|
|
|
|
|
node _T_339 = mux(_T_335, UInt<1>("h01"), _T_338) @[lib.scala 104:23]
|
|
|
|
|
_T_150[26] <= _T_339 @[lib.scala 104:17]
|
|
|
|
|
node _T_340 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_341 = andr(_T_340) @[lib.scala 104:36]
|
|
|
|
|
node _T_342 = and(_T_341, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_343 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[lib.scala 104:74]
|
|
|
|
|
node _T_344 = bits(dec_i0_match_data[0], 27, 27) @[lib.scala 104:86]
|
|
|
|
|
node _T_345 = eq(_T_343, _T_344) @[lib.scala 104:78]
|
|
|
|
|
node _T_346 = mux(_T_342, UInt<1>("h01"), _T_345) @[lib.scala 104:23]
|
|
|
|
|
_T_150[27] <= _T_346 @[lib.scala 104:17]
|
|
|
|
|
node _T_347 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_348 = andr(_T_347) @[lib.scala 104:36]
|
|
|
|
|
node _T_349 = and(_T_348, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_350 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[lib.scala 104:74]
|
|
|
|
|
node _T_351 = bits(dec_i0_match_data[0], 28, 28) @[lib.scala 104:86]
|
|
|
|
|
node _T_352 = eq(_T_350, _T_351) @[lib.scala 104:78]
|
|
|
|
|
node _T_353 = mux(_T_349, UInt<1>("h01"), _T_352) @[lib.scala 104:23]
|
|
|
|
|
_T_150[28] <= _T_353 @[lib.scala 104:17]
|
|
|
|
|
node _T_354 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_355 = andr(_T_354) @[lib.scala 104:36]
|
|
|
|
|
node _T_356 = and(_T_355, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_357 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[lib.scala 104:74]
|
|
|
|
|
node _T_358 = bits(dec_i0_match_data[0], 29, 29) @[lib.scala 104:86]
|
|
|
|
|
node _T_359 = eq(_T_357, _T_358) @[lib.scala 104:78]
|
|
|
|
|
node _T_360 = mux(_T_356, UInt<1>("h01"), _T_359) @[lib.scala 104:23]
|
|
|
|
|
_T_150[29] <= _T_360 @[lib.scala 104:17]
|
|
|
|
|
node _T_361 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_362 = andr(_T_361) @[lib.scala 104:36]
|
|
|
|
|
node _T_363 = and(_T_362, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_364 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[lib.scala 104:74]
|
|
|
|
|
node _T_365 = bits(dec_i0_match_data[0], 30, 30) @[lib.scala 104:86]
|
|
|
|
|
node _T_366 = eq(_T_364, _T_365) @[lib.scala 104:78]
|
|
|
|
|
node _T_367 = mux(_T_363, UInt<1>("h01"), _T_366) @[lib.scala 104:23]
|
|
|
|
|
_T_150[30] <= _T_367 @[lib.scala 104:17]
|
|
|
|
|
node _T_368 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_369 = andr(_T_368) @[lib.scala 104:36]
|
|
|
|
|
node _T_370 = and(_T_369, _T_153) @[lib.scala 104:41]
|
|
|
|
|
node _T_371 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[lib.scala 104:74]
|
|
|
|
|
node _T_372 = bits(dec_i0_match_data[0], 31, 31) @[lib.scala 104:86]
|
|
|
|
|
node _T_373 = eq(_T_371, _T_372) @[lib.scala 104:78]
|
|
|
|
|
node _T_374 = mux(_T_370, UInt<1>("h01"), _T_373) @[lib.scala 104:23]
|
|
|
|
|
_T_150[31] <= _T_374 @[lib.scala 104:17]
|
|
|
|
|
node _T_375 = cat(_T_150[1], _T_150[0]) @[lib.scala 105:14]
|
|
|
|
|
node _T_376 = cat(_T_150[3], _T_150[2]) @[lib.scala 105:14]
|
|
|
|
|
node _T_377 = cat(_T_376, _T_375) @[lib.scala 105:14]
|
|
|
|
|
node _T_378 = cat(_T_150[5], _T_150[4]) @[lib.scala 105:14]
|
|
|
|
|
node _T_379 = cat(_T_150[7], _T_150[6]) @[lib.scala 105:14]
|
|
|
|
|
node _T_380 = cat(_T_379, _T_378) @[lib.scala 105:14]
|
|
|
|
|
node _T_381 = cat(_T_380, _T_377) @[lib.scala 105:14]
|
|
|
|
|
node _T_382 = cat(_T_150[9], _T_150[8]) @[lib.scala 105:14]
|
|
|
|
|
node _T_383 = cat(_T_150[11], _T_150[10]) @[lib.scala 105:14]
|
|
|
|
|
node _T_384 = cat(_T_383, _T_382) @[lib.scala 105:14]
|
|
|
|
|
node _T_385 = cat(_T_150[13], _T_150[12]) @[lib.scala 105:14]
|
|
|
|
|
node _T_386 = cat(_T_150[15], _T_150[14]) @[lib.scala 105:14]
|
|
|
|
|
node _T_387 = cat(_T_386, _T_385) @[lib.scala 105:14]
|
|
|
|
|
node _T_388 = cat(_T_387, _T_384) @[lib.scala 105:14]
|
|
|
|
|
node _T_389 = cat(_T_388, _T_381) @[lib.scala 105:14]
|
|
|
|
|
node _T_390 = cat(_T_150[17], _T_150[16]) @[lib.scala 105:14]
|
|
|
|
|
node _T_391 = cat(_T_150[19], _T_150[18]) @[lib.scala 105:14]
|
|
|
|
|
node _T_392 = cat(_T_391, _T_390) @[lib.scala 105:14]
|
|
|
|
|
node _T_393 = cat(_T_150[21], _T_150[20]) @[lib.scala 105:14]
|
|
|
|
|
node _T_394 = cat(_T_150[23], _T_150[22]) @[lib.scala 105:14]
|
|
|
|
|
node _T_395 = cat(_T_394, _T_393) @[lib.scala 105:14]
|
|
|
|
|
node _T_396 = cat(_T_395, _T_392) @[lib.scala 105:14]
|
|
|
|
|
node _T_397 = cat(_T_150[25], _T_150[24]) @[lib.scala 105:14]
|
|
|
|
|
node _T_398 = cat(_T_150[27], _T_150[26]) @[lib.scala 105:14]
|
|
|
|
|
node _T_399 = cat(_T_398, _T_397) @[lib.scala 105:14]
|
|
|
|
|
node _T_400 = cat(_T_150[29], _T_150[28]) @[lib.scala 105:14]
|
|
|
|
|
node _T_401 = cat(_T_150[31], _T_150[30]) @[lib.scala 105:14]
|
|
|
|
|
node _T_402 = cat(_T_401, _T_400) @[lib.scala 105:14]
|
|
|
|
|
node _T_403 = cat(_T_402, _T_399) @[lib.scala 105:14]
|
|
|
|
|
node _T_404 = cat(_T_403, _T_396) @[lib.scala 105:14]
|
|
|
|
|
node _T_405 = cat(_T_404, _T_389) @[lib.scala 105:14]
|
|
|
|
|
node _T_406 = andr(_T_405) @[lib.scala 105:25]
|
|
|
|
|
node _T_407 = and(_T_148, _T_406) @[dec_trigger.scala 15:109]
|
|
|
|
|
node _T_408 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[dec_trigger.scala 15:83]
|
|
|
|
|
node _T_409 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[dec_trigger.scala 15:216]
|
|
|
|
|
wire _T_410 : UInt<1>[32] @[lib.scala 100:24]
|
|
|
|
|
node _T_411 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 101:45]
|
|
|
|
|
node _T_412 = not(_T_411) @[lib.scala 101:39]
|
|
|
|
|
node _T_413 = and(_T_409, _T_412) @[lib.scala 101:37]
|
|
|
|
|
node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 102:48]
|
|
|
|
|
node _T_415 = bits(dec_i0_match_data[1], 0, 0) @[lib.scala 102:60]
|
|
|
|
|
node _T_416 = eq(_T_414, _T_415) @[lib.scala 102:52]
|
|
|
|
|
node _T_417 = or(_T_413, _T_416) @[lib.scala 102:41]
|
|
|
|
|
_T_410[0] <= _T_417 @[lib.scala 102:18]
|
|
|
|
|
node _T_418 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_419 = andr(_T_418) @[lib.scala 104:36]
|
|
|
|
|
node _T_420 = and(_T_419, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 104:74]
|
|
|
|
|
node _T_422 = bits(dec_i0_match_data[1], 1, 1) @[lib.scala 104:86]
|
|
|
|
|
node _T_423 = eq(_T_421, _T_422) @[lib.scala 104:78]
|
|
|
|
|
node _T_424 = mux(_T_420, UInt<1>("h01"), _T_423) @[lib.scala 104:23]
|
|
|
|
|
_T_410[1] <= _T_424 @[lib.scala 104:17]
|
|
|
|
|
node _T_425 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_426 = andr(_T_425) @[lib.scala 104:36]
|
|
|
|
|
node _T_427 = and(_T_426, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 104:74]
|
|
|
|
|
node _T_429 = bits(dec_i0_match_data[1], 2, 2) @[lib.scala 104:86]
|
|
|
|
|
node _T_430 = eq(_T_428, _T_429) @[lib.scala 104:78]
|
|
|
|
|
node _T_431 = mux(_T_427, UInt<1>("h01"), _T_430) @[lib.scala 104:23]
|
|
|
|
|
_T_410[2] <= _T_431 @[lib.scala 104:17]
|
|
|
|
|
node _T_432 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_433 = andr(_T_432) @[lib.scala 104:36]
|
|
|
|
|
node _T_434 = and(_T_433, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 104:74]
|
|
|
|
|
node _T_436 = bits(dec_i0_match_data[1], 3, 3) @[lib.scala 104:86]
|
|
|
|
|
node _T_437 = eq(_T_435, _T_436) @[lib.scala 104:78]
|
|
|
|
|
node _T_438 = mux(_T_434, UInt<1>("h01"), _T_437) @[lib.scala 104:23]
|
|
|
|
|
_T_410[3] <= _T_438 @[lib.scala 104:17]
|
|
|
|
|
node _T_439 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_440 = andr(_T_439) @[lib.scala 104:36]
|
|
|
|
|
node _T_441 = and(_T_440, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 104:74]
|
|
|
|
|
node _T_443 = bits(dec_i0_match_data[1], 4, 4) @[lib.scala 104:86]
|
|
|
|
|
node _T_444 = eq(_T_442, _T_443) @[lib.scala 104:78]
|
|
|
|
|
node _T_445 = mux(_T_441, UInt<1>("h01"), _T_444) @[lib.scala 104:23]
|
|
|
|
|
_T_410[4] <= _T_445 @[lib.scala 104:17]
|
|
|
|
|
node _T_446 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_447 = andr(_T_446) @[lib.scala 104:36]
|
|
|
|
|
node _T_448 = and(_T_447, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 104:74]
|
|
|
|
|
node _T_450 = bits(dec_i0_match_data[1], 5, 5) @[lib.scala 104:86]
|
|
|
|
|
node _T_451 = eq(_T_449, _T_450) @[lib.scala 104:78]
|
|
|
|
|
node _T_452 = mux(_T_448, UInt<1>("h01"), _T_451) @[lib.scala 104:23]
|
|
|
|
|
_T_410[5] <= _T_452 @[lib.scala 104:17]
|
|
|
|
|
node _T_453 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_454 = andr(_T_453) @[lib.scala 104:36]
|
|
|
|
|
node _T_455 = and(_T_454, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 104:74]
|
|
|
|
|
node _T_457 = bits(dec_i0_match_data[1], 6, 6) @[lib.scala 104:86]
|
|
|
|
|
node _T_458 = eq(_T_456, _T_457) @[lib.scala 104:78]
|
|
|
|
|
node _T_459 = mux(_T_455, UInt<1>("h01"), _T_458) @[lib.scala 104:23]
|
|
|
|
|
_T_410[6] <= _T_459 @[lib.scala 104:17]
|
|
|
|
|
node _T_460 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_461 = andr(_T_460) @[lib.scala 104:36]
|
|
|
|
|
node _T_462 = and(_T_461, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 104:74]
|
|
|
|
|
node _T_464 = bits(dec_i0_match_data[1], 7, 7) @[lib.scala 104:86]
|
|
|
|
|
node _T_465 = eq(_T_463, _T_464) @[lib.scala 104:78]
|
|
|
|
|
node _T_466 = mux(_T_462, UInt<1>("h01"), _T_465) @[lib.scala 104:23]
|
|
|
|
|
_T_410[7] <= _T_466 @[lib.scala 104:17]
|
|
|
|
|
node _T_467 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_468 = andr(_T_467) @[lib.scala 104:36]
|
|
|
|
|
node _T_469 = and(_T_468, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 104:74]
|
|
|
|
|
node _T_471 = bits(dec_i0_match_data[1], 8, 8) @[lib.scala 104:86]
|
|
|
|
|
node _T_472 = eq(_T_470, _T_471) @[lib.scala 104:78]
|
|
|
|
|
node _T_473 = mux(_T_469, UInt<1>("h01"), _T_472) @[lib.scala 104:23]
|
|
|
|
|
_T_410[8] <= _T_473 @[lib.scala 104:17]
|
|
|
|
|
node _T_474 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_475 = andr(_T_474) @[lib.scala 104:36]
|
|
|
|
|
node _T_476 = and(_T_475, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 104:74]
|
|
|
|
|
node _T_478 = bits(dec_i0_match_data[1], 9, 9) @[lib.scala 104:86]
|
|
|
|
|
node _T_479 = eq(_T_477, _T_478) @[lib.scala 104:78]
|
|
|
|
|
node _T_480 = mux(_T_476, UInt<1>("h01"), _T_479) @[lib.scala 104:23]
|
|
|
|
|
_T_410[9] <= _T_480 @[lib.scala 104:17]
|
|
|
|
|
node _T_481 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_482 = andr(_T_481) @[lib.scala 104:36]
|
|
|
|
|
node _T_483 = and(_T_482, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 104:74]
|
|
|
|
|
node _T_485 = bits(dec_i0_match_data[1], 10, 10) @[lib.scala 104:86]
|
|
|
|
|
node _T_486 = eq(_T_484, _T_485) @[lib.scala 104:78]
|
|
|
|
|
node _T_487 = mux(_T_483, UInt<1>("h01"), _T_486) @[lib.scala 104:23]
|
|
|
|
|
_T_410[10] <= _T_487 @[lib.scala 104:17]
|
|
|
|
|
node _T_488 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_489 = andr(_T_488) @[lib.scala 104:36]
|
|
|
|
|
node _T_490 = and(_T_489, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 104:74]
|
|
|
|
|
node _T_492 = bits(dec_i0_match_data[1], 11, 11) @[lib.scala 104:86]
|
|
|
|
|
node _T_493 = eq(_T_491, _T_492) @[lib.scala 104:78]
|
|
|
|
|
node _T_494 = mux(_T_490, UInt<1>("h01"), _T_493) @[lib.scala 104:23]
|
|
|
|
|
_T_410[11] <= _T_494 @[lib.scala 104:17]
|
|
|
|
|
node _T_495 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_496 = andr(_T_495) @[lib.scala 104:36]
|
|
|
|
|
node _T_497 = and(_T_496, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 104:74]
|
|
|
|
|
node _T_499 = bits(dec_i0_match_data[1], 12, 12) @[lib.scala 104:86]
|
|
|
|
|
node _T_500 = eq(_T_498, _T_499) @[lib.scala 104:78]
|
|
|
|
|
node _T_501 = mux(_T_497, UInt<1>("h01"), _T_500) @[lib.scala 104:23]
|
|
|
|
|
_T_410[12] <= _T_501 @[lib.scala 104:17]
|
|
|
|
|
node _T_502 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_503 = andr(_T_502) @[lib.scala 104:36]
|
|
|
|
|
node _T_504 = and(_T_503, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 104:74]
|
|
|
|
|
node _T_506 = bits(dec_i0_match_data[1], 13, 13) @[lib.scala 104:86]
|
|
|
|
|
node _T_507 = eq(_T_505, _T_506) @[lib.scala 104:78]
|
|
|
|
|
node _T_508 = mux(_T_504, UInt<1>("h01"), _T_507) @[lib.scala 104:23]
|
|
|
|
|
_T_410[13] <= _T_508 @[lib.scala 104:17]
|
|
|
|
|
node _T_509 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_510 = andr(_T_509) @[lib.scala 104:36]
|
|
|
|
|
node _T_511 = and(_T_510, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 104:74]
|
|
|
|
|
node _T_513 = bits(dec_i0_match_data[1], 14, 14) @[lib.scala 104:86]
|
|
|
|
|
node _T_514 = eq(_T_512, _T_513) @[lib.scala 104:78]
|
|
|
|
|
node _T_515 = mux(_T_511, UInt<1>("h01"), _T_514) @[lib.scala 104:23]
|
|
|
|
|
_T_410[14] <= _T_515 @[lib.scala 104:17]
|
|
|
|
|
node _T_516 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_517 = andr(_T_516) @[lib.scala 104:36]
|
|
|
|
|
node _T_518 = and(_T_517, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 104:74]
|
|
|
|
|
node _T_520 = bits(dec_i0_match_data[1], 15, 15) @[lib.scala 104:86]
|
|
|
|
|
node _T_521 = eq(_T_519, _T_520) @[lib.scala 104:78]
|
|
|
|
|
node _T_522 = mux(_T_518, UInt<1>("h01"), _T_521) @[lib.scala 104:23]
|
|
|
|
|
_T_410[15] <= _T_522 @[lib.scala 104:17]
|
|
|
|
|
node _T_523 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_524 = andr(_T_523) @[lib.scala 104:36]
|
|
|
|
|
node _T_525 = and(_T_524, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 104:74]
|
|
|
|
|
node _T_527 = bits(dec_i0_match_data[1], 16, 16) @[lib.scala 104:86]
|
|
|
|
|
node _T_528 = eq(_T_526, _T_527) @[lib.scala 104:78]
|
|
|
|
|
node _T_529 = mux(_T_525, UInt<1>("h01"), _T_528) @[lib.scala 104:23]
|
|
|
|
|
_T_410[16] <= _T_529 @[lib.scala 104:17]
|
|
|
|
|
node _T_530 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_531 = andr(_T_530) @[lib.scala 104:36]
|
|
|
|
|
node _T_532 = and(_T_531, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 104:74]
|
|
|
|
|
node _T_534 = bits(dec_i0_match_data[1], 17, 17) @[lib.scala 104:86]
|
|
|
|
|
node _T_535 = eq(_T_533, _T_534) @[lib.scala 104:78]
|
|
|
|
|
node _T_536 = mux(_T_532, UInt<1>("h01"), _T_535) @[lib.scala 104:23]
|
|
|
|
|
_T_410[17] <= _T_536 @[lib.scala 104:17]
|
|
|
|
|
node _T_537 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_538 = andr(_T_537) @[lib.scala 104:36]
|
|
|
|
|
node _T_539 = and(_T_538, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_540 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 104:74]
|
|
|
|
|
node _T_541 = bits(dec_i0_match_data[1], 18, 18) @[lib.scala 104:86]
|
|
|
|
|
node _T_542 = eq(_T_540, _T_541) @[lib.scala 104:78]
|
|
|
|
|
node _T_543 = mux(_T_539, UInt<1>("h01"), _T_542) @[lib.scala 104:23]
|
|
|
|
|
_T_410[18] <= _T_543 @[lib.scala 104:17]
|
|
|
|
|
node _T_544 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_545 = andr(_T_544) @[lib.scala 104:36]
|
|
|
|
|
node _T_546 = and(_T_545, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_547 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 104:74]
|
|
|
|
|
node _T_548 = bits(dec_i0_match_data[1], 19, 19) @[lib.scala 104:86]
|
|
|
|
|
node _T_549 = eq(_T_547, _T_548) @[lib.scala 104:78]
|
|
|
|
|
node _T_550 = mux(_T_546, UInt<1>("h01"), _T_549) @[lib.scala 104:23]
|
|
|
|
|
_T_410[19] <= _T_550 @[lib.scala 104:17]
|
|
|
|
|
node _T_551 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_552 = andr(_T_551) @[lib.scala 104:36]
|
|
|
|
|
node _T_553 = and(_T_552, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_554 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 104:74]
|
|
|
|
|
node _T_555 = bits(dec_i0_match_data[1], 20, 20) @[lib.scala 104:86]
|
|
|
|
|
node _T_556 = eq(_T_554, _T_555) @[lib.scala 104:78]
|
|
|
|
|
node _T_557 = mux(_T_553, UInt<1>("h01"), _T_556) @[lib.scala 104:23]
|
|
|
|
|
_T_410[20] <= _T_557 @[lib.scala 104:17]
|
|
|
|
|
node _T_558 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_559 = andr(_T_558) @[lib.scala 104:36]
|
|
|
|
|
node _T_560 = and(_T_559, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_561 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 104:74]
|
|
|
|
|
node _T_562 = bits(dec_i0_match_data[1], 21, 21) @[lib.scala 104:86]
|
|
|
|
|
node _T_563 = eq(_T_561, _T_562) @[lib.scala 104:78]
|
|
|
|
|
node _T_564 = mux(_T_560, UInt<1>("h01"), _T_563) @[lib.scala 104:23]
|
|
|
|
|
_T_410[21] <= _T_564 @[lib.scala 104:17]
|
|
|
|
|
node _T_565 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_566 = andr(_T_565) @[lib.scala 104:36]
|
|
|
|
|
node _T_567 = and(_T_566, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_568 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 104:74]
|
|
|
|
|
node _T_569 = bits(dec_i0_match_data[1], 22, 22) @[lib.scala 104:86]
|
|
|
|
|
node _T_570 = eq(_T_568, _T_569) @[lib.scala 104:78]
|
|
|
|
|
node _T_571 = mux(_T_567, UInt<1>("h01"), _T_570) @[lib.scala 104:23]
|
|
|
|
|
_T_410[22] <= _T_571 @[lib.scala 104:17]
|
|
|
|
|
node _T_572 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_573 = andr(_T_572) @[lib.scala 104:36]
|
|
|
|
|
node _T_574 = and(_T_573, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_575 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 104:74]
|
|
|
|
|
node _T_576 = bits(dec_i0_match_data[1], 23, 23) @[lib.scala 104:86]
|
|
|
|
|
node _T_577 = eq(_T_575, _T_576) @[lib.scala 104:78]
|
|
|
|
|
node _T_578 = mux(_T_574, UInt<1>("h01"), _T_577) @[lib.scala 104:23]
|
|
|
|
|
_T_410[23] <= _T_578 @[lib.scala 104:17]
|
|
|
|
|
node _T_579 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_580 = andr(_T_579) @[lib.scala 104:36]
|
|
|
|
|
node _T_581 = and(_T_580, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_582 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 104:74]
|
|
|
|
|
node _T_583 = bits(dec_i0_match_data[1], 24, 24) @[lib.scala 104:86]
|
|
|
|
|
node _T_584 = eq(_T_582, _T_583) @[lib.scala 104:78]
|
|
|
|
|
node _T_585 = mux(_T_581, UInt<1>("h01"), _T_584) @[lib.scala 104:23]
|
|
|
|
|
_T_410[24] <= _T_585 @[lib.scala 104:17]
|
|
|
|
|
node _T_586 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_587 = andr(_T_586) @[lib.scala 104:36]
|
|
|
|
|
node _T_588 = and(_T_587, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_589 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 104:74]
|
|
|
|
|
node _T_590 = bits(dec_i0_match_data[1], 25, 25) @[lib.scala 104:86]
|
|
|
|
|
node _T_591 = eq(_T_589, _T_590) @[lib.scala 104:78]
|
|
|
|
|
node _T_592 = mux(_T_588, UInt<1>("h01"), _T_591) @[lib.scala 104:23]
|
|
|
|
|
_T_410[25] <= _T_592 @[lib.scala 104:17]
|
|
|
|
|
node _T_593 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_594 = andr(_T_593) @[lib.scala 104:36]
|
|
|
|
|
node _T_595 = and(_T_594, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_596 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 104:74]
|
|
|
|
|
node _T_597 = bits(dec_i0_match_data[1], 26, 26) @[lib.scala 104:86]
|
|
|
|
|
node _T_598 = eq(_T_596, _T_597) @[lib.scala 104:78]
|
|
|
|
|
node _T_599 = mux(_T_595, UInt<1>("h01"), _T_598) @[lib.scala 104:23]
|
|
|
|
|
_T_410[26] <= _T_599 @[lib.scala 104:17]
|
|
|
|
|
node _T_600 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_601 = andr(_T_600) @[lib.scala 104:36]
|
|
|
|
|
node _T_602 = and(_T_601, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_603 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 104:74]
|
|
|
|
|
node _T_604 = bits(dec_i0_match_data[1], 27, 27) @[lib.scala 104:86]
|
|
|
|
|
node _T_605 = eq(_T_603, _T_604) @[lib.scala 104:78]
|
|
|
|
|
node _T_606 = mux(_T_602, UInt<1>("h01"), _T_605) @[lib.scala 104:23]
|
|
|
|
|
_T_410[27] <= _T_606 @[lib.scala 104:17]
|
|
|
|
|
node _T_607 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_608 = andr(_T_607) @[lib.scala 104:36]
|
|
|
|
|
node _T_609 = and(_T_608, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_610 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 104:74]
|
|
|
|
|
node _T_611 = bits(dec_i0_match_data[1], 28, 28) @[lib.scala 104:86]
|
|
|
|
|
node _T_612 = eq(_T_610, _T_611) @[lib.scala 104:78]
|
|
|
|
|
node _T_613 = mux(_T_609, UInt<1>("h01"), _T_612) @[lib.scala 104:23]
|
|
|
|
|
_T_410[28] <= _T_613 @[lib.scala 104:17]
|
|
|
|
|
node _T_614 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_615 = andr(_T_614) @[lib.scala 104:36]
|
|
|
|
|
node _T_616 = and(_T_615, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_617 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 104:74]
|
|
|
|
|
node _T_618 = bits(dec_i0_match_data[1], 29, 29) @[lib.scala 104:86]
|
|
|
|
|
node _T_619 = eq(_T_617, _T_618) @[lib.scala 104:78]
|
|
|
|
|
node _T_620 = mux(_T_616, UInt<1>("h01"), _T_619) @[lib.scala 104:23]
|
|
|
|
|
_T_410[29] <= _T_620 @[lib.scala 104:17]
|
|
|
|
|
node _T_621 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_622 = andr(_T_621) @[lib.scala 104:36]
|
|
|
|
|
node _T_623 = and(_T_622, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_624 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 104:74]
|
|
|
|
|
node _T_625 = bits(dec_i0_match_data[1], 30, 30) @[lib.scala 104:86]
|
|
|
|
|
node _T_626 = eq(_T_624, _T_625) @[lib.scala 104:78]
|
|
|
|
|
node _T_627 = mux(_T_623, UInt<1>("h01"), _T_626) @[lib.scala 104:23]
|
|
|
|
|
_T_410[30] <= _T_627 @[lib.scala 104:17]
|
|
|
|
|
node _T_628 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_629 = andr(_T_628) @[lib.scala 104:36]
|
|
|
|
|
node _T_630 = and(_T_629, _T_413) @[lib.scala 104:41]
|
|
|
|
|
node _T_631 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 104:74]
|
|
|
|
|
node _T_632 = bits(dec_i0_match_data[1], 31, 31) @[lib.scala 104:86]
|
|
|
|
|
node _T_633 = eq(_T_631, _T_632) @[lib.scala 104:78]
|
|
|
|
|
node _T_634 = mux(_T_630, UInt<1>("h01"), _T_633) @[lib.scala 104:23]
|
|
|
|
|
_T_410[31] <= _T_634 @[lib.scala 104:17]
|
|
|
|
|
node _T_635 = cat(_T_410[1], _T_410[0]) @[lib.scala 105:14]
|
|
|
|
|
node _T_636 = cat(_T_410[3], _T_410[2]) @[lib.scala 105:14]
|
|
|
|
|
node _T_637 = cat(_T_636, _T_635) @[lib.scala 105:14]
|
|
|
|
|
node _T_638 = cat(_T_410[5], _T_410[4]) @[lib.scala 105:14]
|
|
|
|
|
node _T_639 = cat(_T_410[7], _T_410[6]) @[lib.scala 105:14]
|
|
|
|
|
node _T_640 = cat(_T_639, _T_638) @[lib.scala 105:14]
|
|
|
|
|
node _T_641 = cat(_T_640, _T_637) @[lib.scala 105:14]
|
|
|
|
|
node _T_642 = cat(_T_410[9], _T_410[8]) @[lib.scala 105:14]
|
|
|
|
|
node _T_643 = cat(_T_410[11], _T_410[10]) @[lib.scala 105:14]
|
|
|
|
|
node _T_644 = cat(_T_643, _T_642) @[lib.scala 105:14]
|
|
|
|
|
node _T_645 = cat(_T_410[13], _T_410[12]) @[lib.scala 105:14]
|
|
|
|
|
node _T_646 = cat(_T_410[15], _T_410[14]) @[lib.scala 105:14]
|
|
|
|
|
node _T_647 = cat(_T_646, _T_645) @[lib.scala 105:14]
|
|
|
|
|
node _T_648 = cat(_T_647, _T_644) @[lib.scala 105:14]
|
|
|
|
|
node _T_649 = cat(_T_648, _T_641) @[lib.scala 105:14]
|
|
|
|
|
node _T_650 = cat(_T_410[17], _T_410[16]) @[lib.scala 105:14]
|
|
|
|
|
node _T_651 = cat(_T_410[19], _T_410[18]) @[lib.scala 105:14]
|
|
|
|
|
node _T_652 = cat(_T_651, _T_650) @[lib.scala 105:14]
|
|
|
|
|
node _T_653 = cat(_T_410[21], _T_410[20]) @[lib.scala 105:14]
|
|
|
|
|
node _T_654 = cat(_T_410[23], _T_410[22]) @[lib.scala 105:14]
|
|
|
|
|
node _T_655 = cat(_T_654, _T_653) @[lib.scala 105:14]
|
|
|
|
|
node _T_656 = cat(_T_655, _T_652) @[lib.scala 105:14]
|
|
|
|
|
node _T_657 = cat(_T_410[25], _T_410[24]) @[lib.scala 105:14]
|
|
|
|
|
node _T_658 = cat(_T_410[27], _T_410[26]) @[lib.scala 105:14]
|
|
|
|
|
node _T_659 = cat(_T_658, _T_657) @[lib.scala 105:14]
|
|
|
|
|
node _T_660 = cat(_T_410[29], _T_410[28]) @[lib.scala 105:14]
|
|
|
|
|
node _T_661 = cat(_T_410[31], _T_410[30]) @[lib.scala 105:14]
|
|
|
|
|
node _T_662 = cat(_T_661, _T_660) @[lib.scala 105:14]
|
|
|
|
|
node _T_663 = cat(_T_662, _T_659) @[lib.scala 105:14]
|
|
|
|
|
node _T_664 = cat(_T_663, _T_656) @[lib.scala 105:14]
|
|
|
|
|
node _T_665 = cat(_T_664, _T_649) @[lib.scala 105:14]
|
|
|
|
|
node _T_666 = andr(_T_665) @[lib.scala 105:25]
|
|
|
|
|
node _T_667 = and(_T_408, _T_666) @[dec_trigger.scala 15:109]
|
|
|
|
|
node _T_668 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[dec_trigger.scala 15:83]
|
|
|
|
|
node _T_669 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[dec_trigger.scala 15:216]
|
|
|
|
|
wire _T_670 : UInt<1>[32] @[lib.scala 100:24]
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node _T_671 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 101:45]
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node _T_672 = not(_T_671) @[lib.scala 101:39]
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node _T_673 = and(_T_669, _T_672) @[lib.scala 101:37]
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node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 102:48]
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node _T_675 = bits(dec_i0_match_data[2], 0, 0) @[lib.scala 102:60]
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node _T_676 = eq(_T_674, _T_675) @[lib.scala 102:52]
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node _T_677 = or(_T_673, _T_676) @[lib.scala 102:41]
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_T_670[0] <= _T_677 @[lib.scala 102:18]
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node _T_678 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 104:28]
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node _T_679 = andr(_T_678) @[lib.scala 104:36]
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node _T_680 = and(_T_679, _T_673) @[lib.scala 104:41]
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node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 104:74]
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node _T_682 = bits(dec_i0_match_data[2], 1, 1) @[lib.scala 104:86]
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node _T_683 = eq(_T_681, _T_682) @[lib.scala 104:78]
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node _T_684 = mux(_T_680, UInt<1>("h01"), _T_683) @[lib.scala 104:23]
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_T_670[1] <= _T_684 @[lib.scala 104:17]
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node _T_685 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 104:28]
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node _T_686 = andr(_T_685) @[lib.scala 104:36]
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node _T_687 = and(_T_686, _T_673) @[lib.scala 104:41]
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node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 104:74]
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node _T_689 = bits(dec_i0_match_data[2], 2, 2) @[lib.scala 104:86]
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node _T_690 = eq(_T_688, _T_689) @[lib.scala 104:78]
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node _T_691 = mux(_T_687, UInt<1>("h01"), _T_690) @[lib.scala 104:23]
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_T_670[2] <= _T_691 @[lib.scala 104:17]
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node _T_692 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 104:28]
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node _T_693 = andr(_T_692) @[lib.scala 104:36]
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node _T_694 = and(_T_693, _T_673) @[lib.scala 104:41]
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node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 104:74]
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node _T_696 = bits(dec_i0_match_data[2], 3, 3) @[lib.scala 104:86]
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node _T_697 = eq(_T_695, _T_696) @[lib.scala 104:78]
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node _T_698 = mux(_T_694, UInt<1>("h01"), _T_697) @[lib.scala 104:23]
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_T_670[3] <= _T_698 @[lib.scala 104:17]
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node _T_699 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 104:28]
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node _T_700 = andr(_T_699) @[lib.scala 104:36]
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node _T_701 = and(_T_700, _T_673) @[lib.scala 104:41]
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node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 104:74]
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node _T_703 = bits(dec_i0_match_data[2], 4, 4) @[lib.scala 104:86]
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node _T_704 = eq(_T_702, _T_703) @[lib.scala 104:78]
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node _T_705 = mux(_T_701, UInt<1>("h01"), _T_704) @[lib.scala 104:23]
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_T_670[4] <= _T_705 @[lib.scala 104:17]
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node _T_706 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 104:28]
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node _T_707 = andr(_T_706) @[lib.scala 104:36]
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node _T_708 = and(_T_707, _T_673) @[lib.scala 104:41]
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node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 104:74]
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node _T_710 = bits(dec_i0_match_data[2], 5, 5) @[lib.scala 104:86]
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node _T_711 = eq(_T_709, _T_710) @[lib.scala 104:78]
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node _T_712 = mux(_T_708, UInt<1>("h01"), _T_711) @[lib.scala 104:23]
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_T_670[5] <= _T_712 @[lib.scala 104:17]
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node _T_713 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 104:28]
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node _T_714 = andr(_T_713) @[lib.scala 104:36]
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node _T_715 = and(_T_714, _T_673) @[lib.scala 104:41]
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node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 104:74]
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node _T_717 = bits(dec_i0_match_data[2], 6, 6) @[lib.scala 104:86]
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node _T_718 = eq(_T_716, _T_717) @[lib.scala 104:78]
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node _T_719 = mux(_T_715, UInt<1>("h01"), _T_718) @[lib.scala 104:23]
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_T_670[6] <= _T_719 @[lib.scala 104:17]
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node _T_720 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 104:28]
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node _T_721 = andr(_T_720) @[lib.scala 104:36]
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node _T_722 = and(_T_721, _T_673) @[lib.scala 104:41]
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node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 104:74]
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node _T_724 = bits(dec_i0_match_data[2], 7, 7) @[lib.scala 104:86]
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node _T_725 = eq(_T_723, _T_724) @[lib.scala 104:78]
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node _T_726 = mux(_T_722, UInt<1>("h01"), _T_725) @[lib.scala 104:23]
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_T_670[7] <= _T_726 @[lib.scala 104:17]
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node _T_727 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 104:28]
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node _T_728 = andr(_T_727) @[lib.scala 104:36]
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node _T_729 = and(_T_728, _T_673) @[lib.scala 104:41]
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node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 104:74]
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node _T_731 = bits(dec_i0_match_data[2], 8, 8) @[lib.scala 104:86]
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node _T_732 = eq(_T_730, _T_731) @[lib.scala 104:78]
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node _T_733 = mux(_T_729, UInt<1>("h01"), _T_732) @[lib.scala 104:23]
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_T_670[8] <= _T_733 @[lib.scala 104:17]
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node _T_734 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 104:28]
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node _T_735 = andr(_T_734) @[lib.scala 104:36]
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node _T_736 = and(_T_735, _T_673) @[lib.scala 104:41]
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node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 104:74]
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node _T_738 = bits(dec_i0_match_data[2], 9, 9) @[lib.scala 104:86]
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node _T_739 = eq(_T_737, _T_738) @[lib.scala 104:78]
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node _T_740 = mux(_T_736, UInt<1>("h01"), _T_739) @[lib.scala 104:23]
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_T_670[9] <= _T_740 @[lib.scala 104:17]
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node _T_741 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 104:28]
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node _T_742 = andr(_T_741) @[lib.scala 104:36]
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node _T_743 = and(_T_742, _T_673) @[lib.scala 104:41]
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node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 104:74]
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node _T_745 = bits(dec_i0_match_data[2], 10, 10) @[lib.scala 104:86]
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node _T_746 = eq(_T_744, _T_745) @[lib.scala 104:78]
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node _T_747 = mux(_T_743, UInt<1>("h01"), _T_746) @[lib.scala 104:23]
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_T_670[10] <= _T_747 @[lib.scala 104:17]
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node _T_748 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 104:28]
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node _T_749 = andr(_T_748) @[lib.scala 104:36]
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node _T_750 = and(_T_749, _T_673) @[lib.scala 104:41]
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node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 104:74]
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node _T_752 = bits(dec_i0_match_data[2], 11, 11) @[lib.scala 104:86]
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node _T_753 = eq(_T_751, _T_752) @[lib.scala 104:78]
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|
node _T_754 = mux(_T_750, UInt<1>("h01"), _T_753) @[lib.scala 104:23]
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_T_670[11] <= _T_754 @[lib.scala 104:17]
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node _T_755 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 104:28]
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node _T_756 = andr(_T_755) @[lib.scala 104:36]
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node _T_757 = and(_T_756, _T_673) @[lib.scala 104:41]
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node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 104:74]
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node _T_759 = bits(dec_i0_match_data[2], 12, 12) @[lib.scala 104:86]
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node _T_760 = eq(_T_758, _T_759) @[lib.scala 104:78]
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node _T_761 = mux(_T_757, UInt<1>("h01"), _T_760) @[lib.scala 104:23]
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_T_670[12] <= _T_761 @[lib.scala 104:17]
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node _T_762 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 104:28]
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node _T_763 = andr(_T_762) @[lib.scala 104:36]
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node _T_764 = and(_T_763, _T_673) @[lib.scala 104:41]
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|
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node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 104:74]
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node _T_766 = bits(dec_i0_match_data[2], 13, 13) @[lib.scala 104:86]
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|
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node _T_767 = eq(_T_765, _T_766) @[lib.scala 104:78]
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node _T_768 = mux(_T_764, UInt<1>("h01"), _T_767) @[lib.scala 104:23]
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|
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_T_670[13] <= _T_768 @[lib.scala 104:17]
|
|
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node _T_769 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 104:28]
|
|
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node _T_770 = andr(_T_769) @[lib.scala 104:36]
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node _T_771 = and(_T_770, _T_673) @[lib.scala 104:41]
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node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 104:74]
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node _T_773 = bits(dec_i0_match_data[2], 14, 14) @[lib.scala 104:86]
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node _T_774 = eq(_T_772, _T_773) @[lib.scala 104:78]
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|
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|
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node _T_775 = mux(_T_771, UInt<1>("h01"), _T_774) @[lib.scala 104:23]
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_T_670[14] <= _T_775 @[lib.scala 104:17]
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node _T_776 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 104:28]
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node _T_777 = andr(_T_776) @[lib.scala 104:36]
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node _T_778 = and(_T_777, _T_673) @[lib.scala 104:41]
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node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 104:74]
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node _T_780 = bits(dec_i0_match_data[2], 15, 15) @[lib.scala 104:86]
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node _T_781 = eq(_T_779, _T_780) @[lib.scala 104:78]
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node _T_782 = mux(_T_778, UInt<1>("h01"), _T_781) @[lib.scala 104:23]
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_T_670[15] <= _T_782 @[lib.scala 104:17]
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node _T_783 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 104:28]
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node _T_784 = andr(_T_783) @[lib.scala 104:36]
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node _T_785 = and(_T_784, _T_673) @[lib.scala 104:41]
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node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 104:74]
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node _T_787 = bits(dec_i0_match_data[2], 16, 16) @[lib.scala 104:86]
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node _T_788 = eq(_T_786, _T_787) @[lib.scala 104:78]
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node _T_789 = mux(_T_785, UInt<1>("h01"), _T_788) @[lib.scala 104:23]
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_T_670[16] <= _T_789 @[lib.scala 104:17]
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|
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node _T_790 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 104:28]
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node _T_791 = andr(_T_790) @[lib.scala 104:36]
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node _T_792 = and(_T_791, _T_673) @[lib.scala 104:41]
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node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 104:74]
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node _T_794 = bits(dec_i0_match_data[2], 17, 17) @[lib.scala 104:86]
|
|
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|
|
node _T_795 = eq(_T_793, _T_794) @[lib.scala 104:78]
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node _T_796 = mux(_T_792, UInt<1>("h01"), _T_795) @[lib.scala 104:23]
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|
_T_670[17] <= _T_796 @[lib.scala 104:17]
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|
node _T_797 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 104:28]
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node _T_798 = andr(_T_797) @[lib.scala 104:36]
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|
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|
|
node _T_799 = and(_T_798, _T_673) @[lib.scala 104:41]
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node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 104:74]
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node _T_801 = bits(dec_i0_match_data[2], 18, 18) @[lib.scala 104:86]
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|
node _T_802 = eq(_T_800, _T_801) @[lib.scala 104:78]
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|
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node _T_803 = mux(_T_799, UInt<1>("h01"), _T_802) @[lib.scala 104:23]
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|
|
_T_670[18] <= _T_803 @[lib.scala 104:17]
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|
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|
|
node _T_804 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 104:28]
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|
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|
|
node _T_805 = andr(_T_804) @[lib.scala 104:36]
|
|
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|
|
node _T_806 = and(_T_805, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_807 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 104:74]
|
|
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|
|
node _T_808 = bits(dec_i0_match_data[2], 19, 19) @[lib.scala 104:86]
|
|
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|
|
node _T_809 = eq(_T_807, _T_808) @[lib.scala 104:78]
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|
|
node _T_810 = mux(_T_806, UInt<1>("h01"), _T_809) @[lib.scala 104:23]
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|
|
_T_670[19] <= _T_810 @[lib.scala 104:17]
|
|
|
|
|
node _T_811 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_812 = andr(_T_811) @[lib.scala 104:36]
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|
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|
|
node _T_813 = and(_T_812, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_814 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 104:74]
|
|
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|
|
node _T_815 = bits(dec_i0_match_data[2], 20, 20) @[lib.scala 104:86]
|
|
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|
|
node _T_816 = eq(_T_814, _T_815) @[lib.scala 104:78]
|
|
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|
|
node _T_817 = mux(_T_813, UInt<1>("h01"), _T_816) @[lib.scala 104:23]
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|
|
|
|
_T_670[20] <= _T_817 @[lib.scala 104:17]
|
|
|
|
|
node _T_818 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_819 = andr(_T_818) @[lib.scala 104:36]
|
|
|
|
|
node _T_820 = and(_T_819, _T_673) @[lib.scala 104:41]
|
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|
|
node _T_821 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 104:74]
|
|
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|
|
node _T_822 = bits(dec_i0_match_data[2], 21, 21) @[lib.scala 104:86]
|
|
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|
|
node _T_823 = eq(_T_821, _T_822) @[lib.scala 104:78]
|
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|
|
node _T_824 = mux(_T_820, UInt<1>("h01"), _T_823) @[lib.scala 104:23]
|
|
|
|
|
_T_670[21] <= _T_824 @[lib.scala 104:17]
|
|
|
|
|
node _T_825 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_826 = andr(_T_825) @[lib.scala 104:36]
|
|
|
|
|
node _T_827 = and(_T_826, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_828 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 104:74]
|
|
|
|
|
node _T_829 = bits(dec_i0_match_data[2], 22, 22) @[lib.scala 104:86]
|
|
|
|
|
node _T_830 = eq(_T_828, _T_829) @[lib.scala 104:78]
|
|
|
|
|
node _T_831 = mux(_T_827, UInt<1>("h01"), _T_830) @[lib.scala 104:23]
|
|
|
|
|
_T_670[22] <= _T_831 @[lib.scala 104:17]
|
|
|
|
|
node _T_832 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_833 = andr(_T_832) @[lib.scala 104:36]
|
|
|
|
|
node _T_834 = and(_T_833, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_835 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 104:74]
|
|
|
|
|
node _T_836 = bits(dec_i0_match_data[2], 23, 23) @[lib.scala 104:86]
|
|
|
|
|
node _T_837 = eq(_T_835, _T_836) @[lib.scala 104:78]
|
|
|
|
|
node _T_838 = mux(_T_834, UInt<1>("h01"), _T_837) @[lib.scala 104:23]
|
|
|
|
|
_T_670[23] <= _T_838 @[lib.scala 104:17]
|
|
|
|
|
node _T_839 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_840 = andr(_T_839) @[lib.scala 104:36]
|
|
|
|
|
node _T_841 = and(_T_840, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_842 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 104:74]
|
|
|
|
|
node _T_843 = bits(dec_i0_match_data[2], 24, 24) @[lib.scala 104:86]
|
|
|
|
|
node _T_844 = eq(_T_842, _T_843) @[lib.scala 104:78]
|
|
|
|
|
node _T_845 = mux(_T_841, UInt<1>("h01"), _T_844) @[lib.scala 104:23]
|
|
|
|
|
_T_670[24] <= _T_845 @[lib.scala 104:17]
|
|
|
|
|
node _T_846 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_847 = andr(_T_846) @[lib.scala 104:36]
|
|
|
|
|
node _T_848 = and(_T_847, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_849 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 104:74]
|
|
|
|
|
node _T_850 = bits(dec_i0_match_data[2], 25, 25) @[lib.scala 104:86]
|
|
|
|
|
node _T_851 = eq(_T_849, _T_850) @[lib.scala 104:78]
|
|
|
|
|
node _T_852 = mux(_T_848, UInt<1>("h01"), _T_851) @[lib.scala 104:23]
|
|
|
|
|
_T_670[25] <= _T_852 @[lib.scala 104:17]
|
|
|
|
|
node _T_853 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_854 = andr(_T_853) @[lib.scala 104:36]
|
|
|
|
|
node _T_855 = and(_T_854, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_856 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 104:74]
|
|
|
|
|
node _T_857 = bits(dec_i0_match_data[2], 26, 26) @[lib.scala 104:86]
|
|
|
|
|
node _T_858 = eq(_T_856, _T_857) @[lib.scala 104:78]
|
|
|
|
|
node _T_859 = mux(_T_855, UInt<1>("h01"), _T_858) @[lib.scala 104:23]
|
|
|
|
|
_T_670[26] <= _T_859 @[lib.scala 104:17]
|
|
|
|
|
node _T_860 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_861 = andr(_T_860) @[lib.scala 104:36]
|
|
|
|
|
node _T_862 = and(_T_861, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_863 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 104:74]
|
|
|
|
|
node _T_864 = bits(dec_i0_match_data[2], 27, 27) @[lib.scala 104:86]
|
|
|
|
|
node _T_865 = eq(_T_863, _T_864) @[lib.scala 104:78]
|
|
|
|
|
node _T_866 = mux(_T_862, UInt<1>("h01"), _T_865) @[lib.scala 104:23]
|
|
|
|
|
_T_670[27] <= _T_866 @[lib.scala 104:17]
|
|
|
|
|
node _T_867 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_868 = andr(_T_867) @[lib.scala 104:36]
|
|
|
|
|
node _T_869 = and(_T_868, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_870 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 104:74]
|
|
|
|
|
node _T_871 = bits(dec_i0_match_data[2], 28, 28) @[lib.scala 104:86]
|
|
|
|
|
node _T_872 = eq(_T_870, _T_871) @[lib.scala 104:78]
|
|
|
|
|
node _T_873 = mux(_T_869, UInt<1>("h01"), _T_872) @[lib.scala 104:23]
|
|
|
|
|
_T_670[28] <= _T_873 @[lib.scala 104:17]
|
|
|
|
|
node _T_874 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_875 = andr(_T_874) @[lib.scala 104:36]
|
|
|
|
|
node _T_876 = and(_T_875, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_877 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 104:74]
|
|
|
|
|
node _T_878 = bits(dec_i0_match_data[2], 29, 29) @[lib.scala 104:86]
|
|
|
|
|
node _T_879 = eq(_T_877, _T_878) @[lib.scala 104:78]
|
|
|
|
|
node _T_880 = mux(_T_876, UInt<1>("h01"), _T_879) @[lib.scala 104:23]
|
|
|
|
|
_T_670[29] <= _T_880 @[lib.scala 104:17]
|
|
|
|
|
node _T_881 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_882 = andr(_T_881) @[lib.scala 104:36]
|
|
|
|
|
node _T_883 = and(_T_882, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_884 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 104:74]
|
|
|
|
|
node _T_885 = bits(dec_i0_match_data[2], 30, 30) @[lib.scala 104:86]
|
|
|
|
|
node _T_886 = eq(_T_884, _T_885) @[lib.scala 104:78]
|
|
|
|
|
node _T_887 = mux(_T_883, UInt<1>("h01"), _T_886) @[lib.scala 104:23]
|
|
|
|
|
_T_670[30] <= _T_887 @[lib.scala 104:17]
|
|
|
|
|
node _T_888 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_889 = andr(_T_888) @[lib.scala 104:36]
|
|
|
|
|
node _T_890 = and(_T_889, _T_673) @[lib.scala 104:41]
|
|
|
|
|
node _T_891 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 104:74]
|
|
|
|
|
node _T_892 = bits(dec_i0_match_data[2], 31, 31) @[lib.scala 104:86]
|
|
|
|
|
node _T_893 = eq(_T_891, _T_892) @[lib.scala 104:78]
|
|
|
|
|
node _T_894 = mux(_T_890, UInt<1>("h01"), _T_893) @[lib.scala 104:23]
|
|
|
|
|
_T_670[31] <= _T_894 @[lib.scala 104:17]
|
|
|
|
|
node _T_895 = cat(_T_670[1], _T_670[0]) @[lib.scala 105:14]
|
|
|
|
|
node _T_896 = cat(_T_670[3], _T_670[2]) @[lib.scala 105:14]
|
|
|
|
|
node _T_897 = cat(_T_896, _T_895) @[lib.scala 105:14]
|
|
|
|
|
node _T_898 = cat(_T_670[5], _T_670[4]) @[lib.scala 105:14]
|
|
|
|
|
node _T_899 = cat(_T_670[7], _T_670[6]) @[lib.scala 105:14]
|
|
|
|
|
node _T_900 = cat(_T_899, _T_898) @[lib.scala 105:14]
|
|
|
|
|
node _T_901 = cat(_T_900, _T_897) @[lib.scala 105:14]
|
|
|
|
|
node _T_902 = cat(_T_670[9], _T_670[8]) @[lib.scala 105:14]
|
|
|
|
|
node _T_903 = cat(_T_670[11], _T_670[10]) @[lib.scala 105:14]
|
|
|
|
|
node _T_904 = cat(_T_903, _T_902) @[lib.scala 105:14]
|
|
|
|
|
node _T_905 = cat(_T_670[13], _T_670[12]) @[lib.scala 105:14]
|
|
|
|
|
node _T_906 = cat(_T_670[15], _T_670[14]) @[lib.scala 105:14]
|
|
|
|
|
node _T_907 = cat(_T_906, _T_905) @[lib.scala 105:14]
|
|
|
|
|
node _T_908 = cat(_T_907, _T_904) @[lib.scala 105:14]
|
|
|
|
|
node _T_909 = cat(_T_908, _T_901) @[lib.scala 105:14]
|
|
|
|
|
node _T_910 = cat(_T_670[17], _T_670[16]) @[lib.scala 105:14]
|
|
|
|
|
node _T_911 = cat(_T_670[19], _T_670[18]) @[lib.scala 105:14]
|
|
|
|
|
node _T_912 = cat(_T_911, _T_910) @[lib.scala 105:14]
|
|
|
|
|
node _T_913 = cat(_T_670[21], _T_670[20]) @[lib.scala 105:14]
|
|
|
|
|
node _T_914 = cat(_T_670[23], _T_670[22]) @[lib.scala 105:14]
|
|
|
|
|
node _T_915 = cat(_T_914, _T_913) @[lib.scala 105:14]
|
|
|
|
|
node _T_916 = cat(_T_915, _T_912) @[lib.scala 105:14]
|
|
|
|
|
node _T_917 = cat(_T_670[25], _T_670[24]) @[lib.scala 105:14]
|
|
|
|
|
node _T_918 = cat(_T_670[27], _T_670[26]) @[lib.scala 105:14]
|
|
|
|
|
node _T_919 = cat(_T_918, _T_917) @[lib.scala 105:14]
|
|
|
|
|
node _T_920 = cat(_T_670[29], _T_670[28]) @[lib.scala 105:14]
|
|
|
|
|
node _T_921 = cat(_T_670[31], _T_670[30]) @[lib.scala 105:14]
|
|
|
|
|
node _T_922 = cat(_T_921, _T_920) @[lib.scala 105:14]
|
|
|
|
|
node _T_923 = cat(_T_922, _T_919) @[lib.scala 105:14]
|
|
|
|
|
node _T_924 = cat(_T_923, _T_916) @[lib.scala 105:14]
|
|
|
|
|
node _T_925 = cat(_T_924, _T_909) @[lib.scala 105:14]
|
|
|
|
|
node _T_926 = andr(_T_925) @[lib.scala 105:25]
|
|
|
|
|
node _T_927 = and(_T_668, _T_926) @[dec_trigger.scala 15:109]
|
|
|
|
|
node _T_928 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[dec_trigger.scala 15:83]
|
|
|
|
|
node _T_929 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[dec_trigger.scala 15:216]
|
|
|
|
|
wire _T_930 : UInt<1>[32] @[lib.scala 100:24]
|
|
|
|
|
node _T_931 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 101:45]
|
|
|
|
|
node _T_932 = not(_T_931) @[lib.scala 101:39]
|
|
|
|
|
node _T_933 = and(_T_929, _T_932) @[lib.scala 101:37]
|
|
|
|
|
node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 102:48]
|
|
|
|
|
node _T_935 = bits(dec_i0_match_data[3], 0, 0) @[lib.scala 102:60]
|
|
|
|
|
node _T_936 = eq(_T_934, _T_935) @[lib.scala 102:52]
|
|
|
|
|
node _T_937 = or(_T_933, _T_936) @[lib.scala 102:41]
|
|
|
|
|
_T_930[0] <= _T_937 @[lib.scala 102:18]
|
|
|
|
|
node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_939 = andr(_T_938) @[lib.scala 104:36]
|
|
|
|
|
node _T_940 = and(_T_939, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 104:74]
|
|
|
|
|
node _T_942 = bits(dec_i0_match_data[3], 1, 1) @[lib.scala 104:86]
|
|
|
|
|
node _T_943 = eq(_T_941, _T_942) @[lib.scala 104:78]
|
|
|
|
|
node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[lib.scala 104:23]
|
|
|
|
|
_T_930[1] <= _T_944 @[lib.scala 104:17]
|
|
|
|
|
node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_946 = andr(_T_945) @[lib.scala 104:36]
|
|
|
|
|
node _T_947 = and(_T_946, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 104:74]
|
|
|
|
|
node _T_949 = bits(dec_i0_match_data[3], 2, 2) @[lib.scala 104:86]
|
|
|
|
|
node _T_950 = eq(_T_948, _T_949) @[lib.scala 104:78]
|
|
|
|
|
node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[lib.scala 104:23]
|
|
|
|
|
_T_930[2] <= _T_951 @[lib.scala 104:17]
|
|
|
|
|
node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_953 = andr(_T_952) @[lib.scala 104:36]
|
|
|
|
|
node _T_954 = and(_T_953, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 104:74]
|
|
|
|
|
node _T_956 = bits(dec_i0_match_data[3], 3, 3) @[lib.scala 104:86]
|
|
|
|
|
node _T_957 = eq(_T_955, _T_956) @[lib.scala 104:78]
|
|
|
|
|
node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[lib.scala 104:23]
|
|
|
|
|
_T_930[3] <= _T_958 @[lib.scala 104:17]
|
|
|
|
|
node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_960 = andr(_T_959) @[lib.scala 104:36]
|
|
|
|
|
node _T_961 = and(_T_960, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 104:74]
|
|
|
|
|
node _T_963 = bits(dec_i0_match_data[3], 4, 4) @[lib.scala 104:86]
|
|
|
|
|
node _T_964 = eq(_T_962, _T_963) @[lib.scala 104:78]
|
|
|
|
|
node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[lib.scala 104:23]
|
|
|
|
|
_T_930[4] <= _T_965 @[lib.scala 104:17]
|
|
|
|
|
node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_967 = andr(_T_966) @[lib.scala 104:36]
|
|
|
|
|
node _T_968 = and(_T_967, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 104:74]
|
|
|
|
|
node _T_970 = bits(dec_i0_match_data[3], 5, 5) @[lib.scala 104:86]
|
|
|
|
|
node _T_971 = eq(_T_969, _T_970) @[lib.scala 104:78]
|
|
|
|
|
node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[lib.scala 104:23]
|
|
|
|
|
_T_930[5] <= _T_972 @[lib.scala 104:17]
|
|
|
|
|
node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_974 = andr(_T_973) @[lib.scala 104:36]
|
|
|
|
|
node _T_975 = and(_T_974, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 104:74]
|
|
|
|
|
node _T_977 = bits(dec_i0_match_data[3], 6, 6) @[lib.scala 104:86]
|
|
|
|
|
node _T_978 = eq(_T_976, _T_977) @[lib.scala 104:78]
|
|
|
|
|
node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[lib.scala 104:23]
|
|
|
|
|
_T_930[6] <= _T_979 @[lib.scala 104:17]
|
|
|
|
|
node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_981 = andr(_T_980) @[lib.scala 104:36]
|
|
|
|
|
node _T_982 = and(_T_981, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 104:74]
|
|
|
|
|
node _T_984 = bits(dec_i0_match_data[3], 7, 7) @[lib.scala 104:86]
|
|
|
|
|
node _T_985 = eq(_T_983, _T_984) @[lib.scala 104:78]
|
|
|
|
|
node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[lib.scala 104:23]
|
|
|
|
|
_T_930[7] <= _T_986 @[lib.scala 104:17]
|
|
|
|
|
node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_988 = andr(_T_987) @[lib.scala 104:36]
|
|
|
|
|
node _T_989 = and(_T_988, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 104:74]
|
|
|
|
|
node _T_991 = bits(dec_i0_match_data[3], 8, 8) @[lib.scala 104:86]
|
|
|
|
|
node _T_992 = eq(_T_990, _T_991) @[lib.scala 104:78]
|
|
|
|
|
node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[lib.scala 104:23]
|
|
|
|
|
_T_930[8] <= _T_993 @[lib.scala 104:17]
|
|
|
|
|
node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_995 = andr(_T_994) @[lib.scala 104:36]
|
|
|
|
|
node _T_996 = and(_T_995, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 104:74]
|
|
|
|
|
node _T_998 = bits(dec_i0_match_data[3], 9, 9) @[lib.scala 104:86]
|
|
|
|
|
node _T_999 = eq(_T_997, _T_998) @[lib.scala 104:78]
|
|
|
|
|
node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[lib.scala 104:23]
|
|
|
|
|
_T_930[9] <= _T_1000 @[lib.scala 104:17]
|
|
|
|
|
node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1002 = andr(_T_1001) @[lib.scala 104:36]
|
|
|
|
|
node _T_1003 = and(_T_1002, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 104:74]
|
|
|
|
|
node _T_1005 = bits(dec_i0_match_data[3], 10, 10) @[lib.scala 104:86]
|
|
|
|
|
node _T_1006 = eq(_T_1004, _T_1005) @[lib.scala 104:78]
|
|
|
|
|
node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[lib.scala 104:23]
|
|
|
|
|
_T_930[10] <= _T_1007 @[lib.scala 104:17]
|
|
|
|
|
node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1009 = andr(_T_1008) @[lib.scala 104:36]
|
|
|
|
|
node _T_1010 = and(_T_1009, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 104:74]
|
|
|
|
|
node _T_1012 = bits(dec_i0_match_data[3], 11, 11) @[lib.scala 104:86]
|
|
|
|
|
node _T_1013 = eq(_T_1011, _T_1012) @[lib.scala 104:78]
|
|
|
|
|
node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[lib.scala 104:23]
|
|
|
|
|
_T_930[11] <= _T_1014 @[lib.scala 104:17]
|
|
|
|
|
node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1016 = andr(_T_1015) @[lib.scala 104:36]
|
|
|
|
|
node _T_1017 = and(_T_1016, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 104:74]
|
|
|
|
|
node _T_1019 = bits(dec_i0_match_data[3], 12, 12) @[lib.scala 104:86]
|
|
|
|
|
node _T_1020 = eq(_T_1018, _T_1019) @[lib.scala 104:78]
|
|
|
|
|
node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[lib.scala 104:23]
|
|
|
|
|
_T_930[12] <= _T_1021 @[lib.scala 104:17]
|
|
|
|
|
node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1023 = andr(_T_1022) @[lib.scala 104:36]
|
|
|
|
|
node _T_1024 = and(_T_1023, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 104:74]
|
|
|
|
|
node _T_1026 = bits(dec_i0_match_data[3], 13, 13) @[lib.scala 104:86]
|
|
|
|
|
node _T_1027 = eq(_T_1025, _T_1026) @[lib.scala 104:78]
|
|
|
|
|
node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[lib.scala 104:23]
|
|
|
|
|
_T_930[13] <= _T_1028 @[lib.scala 104:17]
|
|
|
|
|
node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1030 = andr(_T_1029) @[lib.scala 104:36]
|
|
|
|
|
node _T_1031 = and(_T_1030, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 104:74]
|
|
|
|
|
node _T_1033 = bits(dec_i0_match_data[3], 14, 14) @[lib.scala 104:86]
|
|
|
|
|
node _T_1034 = eq(_T_1032, _T_1033) @[lib.scala 104:78]
|
|
|
|
|
node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[lib.scala 104:23]
|
|
|
|
|
_T_930[14] <= _T_1035 @[lib.scala 104:17]
|
|
|
|
|
node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1037 = andr(_T_1036) @[lib.scala 104:36]
|
|
|
|
|
node _T_1038 = and(_T_1037, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 104:74]
|
|
|
|
|
node _T_1040 = bits(dec_i0_match_data[3], 15, 15) @[lib.scala 104:86]
|
|
|
|
|
node _T_1041 = eq(_T_1039, _T_1040) @[lib.scala 104:78]
|
|
|
|
|
node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[lib.scala 104:23]
|
|
|
|
|
_T_930[15] <= _T_1042 @[lib.scala 104:17]
|
|
|
|
|
node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1044 = andr(_T_1043) @[lib.scala 104:36]
|
|
|
|
|
node _T_1045 = and(_T_1044, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 104:74]
|
|
|
|
|
node _T_1047 = bits(dec_i0_match_data[3], 16, 16) @[lib.scala 104:86]
|
|
|
|
|
node _T_1048 = eq(_T_1046, _T_1047) @[lib.scala 104:78]
|
|
|
|
|
node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[lib.scala 104:23]
|
|
|
|
|
_T_930[16] <= _T_1049 @[lib.scala 104:17]
|
|
|
|
|
node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1051 = andr(_T_1050) @[lib.scala 104:36]
|
|
|
|
|
node _T_1052 = and(_T_1051, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 104:74]
|
|
|
|
|
node _T_1054 = bits(dec_i0_match_data[3], 17, 17) @[lib.scala 104:86]
|
|
|
|
|
node _T_1055 = eq(_T_1053, _T_1054) @[lib.scala 104:78]
|
|
|
|
|
node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[lib.scala 104:23]
|
|
|
|
|
_T_930[17] <= _T_1056 @[lib.scala 104:17]
|
|
|
|
|
node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1058 = andr(_T_1057) @[lib.scala 104:36]
|
|
|
|
|
node _T_1059 = and(_T_1058, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 104:74]
|
|
|
|
|
node _T_1061 = bits(dec_i0_match_data[3], 18, 18) @[lib.scala 104:86]
|
|
|
|
|
node _T_1062 = eq(_T_1060, _T_1061) @[lib.scala 104:78]
|
|
|
|
|
node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[lib.scala 104:23]
|
|
|
|
|
_T_930[18] <= _T_1063 @[lib.scala 104:17]
|
|
|
|
|
node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1065 = andr(_T_1064) @[lib.scala 104:36]
|
|
|
|
|
node _T_1066 = and(_T_1065, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 104:74]
|
|
|
|
|
node _T_1068 = bits(dec_i0_match_data[3], 19, 19) @[lib.scala 104:86]
|
|
|
|
|
node _T_1069 = eq(_T_1067, _T_1068) @[lib.scala 104:78]
|
|
|
|
|
node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[lib.scala 104:23]
|
|
|
|
|
_T_930[19] <= _T_1070 @[lib.scala 104:17]
|
|
|
|
|
node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1072 = andr(_T_1071) @[lib.scala 104:36]
|
|
|
|
|
node _T_1073 = and(_T_1072, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1074 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 104:74]
|
|
|
|
|
node _T_1075 = bits(dec_i0_match_data[3], 20, 20) @[lib.scala 104:86]
|
|
|
|
|
node _T_1076 = eq(_T_1074, _T_1075) @[lib.scala 104:78]
|
|
|
|
|
node _T_1077 = mux(_T_1073, UInt<1>("h01"), _T_1076) @[lib.scala 104:23]
|
|
|
|
|
_T_930[20] <= _T_1077 @[lib.scala 104:17]
|
|
|
|
|
node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1079 = andr(_T_1078) @[lib.scala 104:36]
|
|
|
|
|
node _T_1080 = and(_T_1079, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1081 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 104:74]
|
|
|
|
|
node _T_1082 = bits(dec_i0_match_data[3], 21, 21) @[lib.scala 104:86]
|
|
|
|
|
node _T_1083 = eq(_T_1081, _T_1082) @[lib.scala 104:78]
|
|
|
|
|
node _T_1084 = mux(_T_1080, UInt<1>("h01"), _T_1083) @[lib.scala 104:23]
|
|
|
|
|
_T_930[21] <= _T_1084 @[lib.scala 104:17]
|
|
|
|
|
node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1086 = andr(_T_1085) @[lib.scala 104:36]
|
|
|
|
|
node _T_1087 = and(_T_1086, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1088 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 104:74]
|
|
|
|
|
node _T_1089 = bits(dec_i0_match_data[3], 22, 22) @[lib.scala 104:86]
|
|
|
|
|
node _T_1090 = eq(_T_1088, _T_1089) @[lib.scala 104:78]
|
|
|
|
|
node _T_1091 = mux(_T_1087, UInt<1>("h01"), _T_1090) @[lib.scala 104:23]
|
|
|
|
|
_T_930[22] <= _T_1091 @[lib.scala 104:17]
|
|
|
|
|
node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1093 = andr(_T_1092) @[lib.scala 104:36]
|
|
|
|
|
node _T_1094 = and(_T_1093, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1095 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 104:74]
|
|
|
|
|
node _T_1096 = bits(dec_i0_match_data[3], 23, 23) @[lib.scala 104:86]
|
|
|
|
|
node _T_1097 = eq(_T_1095, _T_1096) @[lib.scala 104:78]
|
|
|
|
|
node _T_1098 = mux(_T_1094, UInt<1>("h01"), _T_1097) @[lib.scala 104:23]
|
|
|
|
|
_T_930[23] <= _T_1098 @[lib.scala 104:17]
|
|
|
|
|
node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1100 = andr(_T_1099) @[lib.scala 104:36]
|
|
|
|
|
node _T_1101 = and(_T_1100, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1102 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 104:74]
|
|
|
|
|
node _T_1103 = bits(dec_i0_match_data[3], 24, 24) @[lib.scala 104:86]
|
|
|
|
|
node _T_1104 = eq(_T_1102, _T_1103) @[lib.scala 104:78]
|
|
|
|
|
node _T_1105 = mux(_T_1101, UInt<1>("h01"), _T_1104) @[lib.scala 104:23]
|
|
|
|
|
_T_930[24] <= _T_1105 @[lib.scala 104:17]
|
|
|
|
|
node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1107 = andr(_T_1106) @[lib.scala 104:36]
|
|
|
|
|
node _T_1108 = and(_T_1107, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1109 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 104:74]
|
|
|
|
|
node _T_1110 = bits(dec_i0_match_data[3], 25, 25) @[lib.scala 104:86]
|
|
|
|
|
node _T_1111 = eq(_T_1109, _T_1110) @[lib.scala 104:78]
|
|
|
|
|
node _T_1112 = mux(_T_1108, UInt<1>("h01"), _T_1111) @[lib.scala 104:23]
|
|
|
|
|
_T_930[25] <= _T_1112 @[lib.scala 104:17]
|
|
|
|
|
node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1114 = andr(_T_1113) @[lib.scala 104:36]
|
|
|
|
|
node _T_1115 = and(_T_1114, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1116 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 104:74]
|
|
|
|
|
node _T_1117 = bits(dec_i0_match_data[3], 26, 26) @[lib.scala 104:86]
|
|
|
|
|
node _T_1118 = eq(_T_1116, _T_1117) @[lib.scala 104:78]
|
|
|
|
|
node _T_1119 = mux(_T_1115, UInt<1>("h01"), _T_1118) @[lib.scala 104:23]
|
|
|
|
|
_T_930[26] <= _T_1119 @[lib.scala 104:17]
|
|
|
|
|
node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1121 = andr(_T_1120) @[lib.scala 104:36]
|
|
|
|
|
node _T_1122 = and(_T_1121, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1123 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 104:74]
|
|
|
|
|
node _T_1124 = bits(dec_i0_match_data[3], 27, 27) @[lib.scala 104:86]
|
|
|
|
|
node _T_1125 = eq(_T_1123, _T_1124) @[lib.scala 104:78]
|
|
|
|
|
node _T_1126 = mux(_T_1122, UInt<1>("h01"), _T_1125) @[lib.scala 104:23]
|
|
|
|
|
_T_930[27] <= _T_1126 @[lib.scala 104:17]
|
|
|
|
|
node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1128 = andr(_T_1127) @[lib.scala 104:36]
|
|
|
|
|
node _T_1129 = and(_T_1128, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1130 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 104:74]
|
|
|
|
|
node _T_1131 = bits(dec_i0_match_data[3], 28, 28) @[lib.scala 104:86]
|
|
|
|
|
node _T_1132 = eq(_T_1130, _T_1131) @[lib.scala 104:78]
|
|
|
|
|
node _T_1133 = mux(_T_1129, UInt<1>("h01"), _T_1132) @[lib.scala 104:23]
|
|
|
|
|
_T_930[28] <= _T_1133 @[lib.scala 104:17]
|
|
|
|
|
node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1135 = andr(_T_1134) @[lib.scala 104:36]
|
|
|
|
|
node _T_1136 = and(_T_1135, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1137 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 104:74]
|
|
|
|
|
node _T_1138 = bits(dec_i0_match_data[3], 29, 29) @[lib.scala 104:86]
|
|
|
|
|
node _T_1139 = eq(_T_1137, _T_1138) @[lib.scala 104:78]
|
|
|
|
|
node _T_1140 = mux(_T_1136, UInt<1>("h01"), _T_1139) @[lib.scala 104:23]
|
|
|
|
|
_T_930[29] <= _T_1140 @[lib.scala 104:17]
|
|
|
|
|
node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1142 = andr(_T_1141) @[lib.scala 104:36]
|
|
|
|
|
node _T_1143 = and(_T_1142, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1144 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 104:74]
|
|
|
|
|
node _T_1145 = bits(dec_i0_match_data[3], 30, 30) @[lib.scala 104:86]
|
|
|
|
|
node _T_1146 = eq(_T_1144, _T_1145) @[lib.scala 104:78]
|
|
|
|
|
node _T_1147 = mux(_T_1143, UInt<1>("h01"), _T_1146) @[lib.scala 104:23]
|
|
|
|
|
_T_930[30] <= _T_1147 @[lib.scala 104:17]
|
|
|
|
|
node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 104:28]
|
|
|
|
|
node _T_1149 = andr(_T_1148) @[lib.scala 104:36]
|
|
|
|
|
node _T_1150 = and(_T_1149, _T_933) @[lib.scala 104:41]
|
|
|
|
|
node _T_1151 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 104:74]
|
|
|
|
|
node _T_1152 = bits(dec_i0_match_data[3], 31, 31) @[lib.scala 104:86]
|
|
|
|
|
node _T_1153 = eq(_T_1151, _T_1152) @[lib.scala 104:78]
|
|
|
|
|
node _T_1154 = mux(_T_1150, UInt<1>("h01"), _T_1153) @[lib.scala 104:23]
|
|
|
|
|
_T_930[31] <= _T_1154 @[lib.scala 104:17]
|
|
|
|
|
node _T_1155 = cat(_T_930[1], _T_930[0]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1156 = cat(_T_930[3], _T_930[2]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1157 = cat(_T_1156, _T_1155) @[lib.scala 105:14]
|
|
|
|
|
node _T_1158 = cat(_T_930[5], _T_930[4]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1159 = cat(_T_930[7], _T_930[6]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1160 = cat(_T_1159, _T_1158) @[lib.scala 105:14]
|
|
|
|
|
node _T_1161 = cat(_T_1160, _T_1157) @[lib.scala 105:14]
|
|
|
|
|
node _T_1162 = cat(_T_930[9], _T_930[8]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1163 = cat(_T_930[11], _T_930[10]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1164 = cat(_T_1163, _T_1162) @[lib.scala 105:14]
|
|
|
|
|
node _T_1165 = cat(_T_930[13], _T_930[12]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1166 = cat(_T_930[15], _T_930[14]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1167 = cat(_T_1166, _T_1165) @[lib.scala 105:14]
|
|
|
|
|
node _T_1168 = cat(_T_1167, _T_1164) @[lib.scala 105:14]
|
|
|
|
|
node _T_1169 = cat(_T_1168, _T_1161) @[lib.scala 105:14]
|
|
|
|
|
node _T_1170 = cat(_T_930[17], _T_930[16]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1171 = cat(_T_930[19], _T_930[18]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1172 = cat(_T_1171, _T_1170) @[lib.scala 105:14]
|
|
|
|
|
node _T_1173 = cat(_T_930[21], _T_930[20]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1174 = cat(_T_930[23], _T_930[22]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1175 = cat(_T_1174, _T_1173) @[lib.scala 105:14]
|
|
|
|
|
node _T_1176 = cat(_T_1175, _T_1172) @[lib.scala 105:14]
|
|
|
|
|
node _T_1177 = cat(_T_930[25], _T_930[24]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1178 = cat(_T_930[27], _T_930[26]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1179 = cat(_T_1178, _T_1177) @[lib.scala 105:14]
|
|
|
|
|
node _T_1180 = cat(_T_930[29], _T_930[28]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1181 = cat(_T_930[31], _T_930[30]) @[lib.scala 105:14]
|
|
|
|
|
node _T_1182 = cat(_T_1181, _T_1180) @[lib.scala 105:14]
|
|
|
|
|
node _T_1183 = cat(_T_1182, _T_1179) @[lib.scala 105:14]
|
|
|
|
|
node _T_1184 = cat(_T_1183, _T_1176) @[lib.scala 105:14]
|
|
|
|
|
node _T_1185 = cat(_T_1184, _T_1169) @[lib.scala 105:14]
|
|
|
|
|
node _T_1186 = andr(_T_1185) @[lib.scala 105:25]
|
|
|
|
|
node _T_1187 = and(_T_928, _T_1186) @[dec_trigger.scala 15:109]
|
|
|
|
|
node _T_1188 = cat(_T_1187, _T_927) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1189 = cat(_T_1188, _T_667) @[Cat.scala 29:58]
|
|
|
|
|
node _T_1190 = cat(_T_1189, _T_407) @[Cat.scala 29:58]
|
|
|
|
|
io.dec_i0_trigger_match_d <= _T_1190 @[dec_trigger.scala 15:29]
|
|
|
|
|
|
|
|
|
|
module dec :
|
|
|
|
|
input clock : Clock
|
|
|
|
|
input reset : AsyncReset
|
2021-01-27 21:01:24 +08:00
|
|
|
output io : {flip free_clk : Clock, flip active_clk : Clock, flip free_l2clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_pause_state_cg : UInt<1>, dec_tlu_core_empty : UInt<1>, flip rst_vec : UInt<31>, flip ifu_i0_fa_index : UInt<9>, dec_fa_error_index : UInt<9>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip lsu_nonblock_load_data : UInt<32>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip lsu_trigger_match_m : UInt<4>, flip lsu_idle_any : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_dbg_rddata : UInt<32>, dec_csr_rddata_d : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip exu_i0_br_way_r : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, dec_lsu_offset_d : UInt<12>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, trace_rv_trace_pkt : {rv_i_valid_ip : UInt<1>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<1>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<1>, rv_i_tval_ip : UInt<32>}, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_picio_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_i0_decode_d : UInt<1>, flip scan_mode : UInt<1>, flip ifu_dec : {dec_aln : {aln_dec : {ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_second : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err
|
2021-01-27 14:46:11 +08:00
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|
|
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|
|
wire dec_i0_inst_wb1 : UInt<32>
|
|
|
|
|
dec_i0_inst_wb1 <= UInt<1>("h00")
|
|
|
|
|
wire dec_i0_pc_wb1 : UInt<32>
|
|
|
|
|
dec_i0_pc_wb1 <= UInt<1>("h00")
|
|
|
|
|
wire dec_tlu_i0_valid_wb1 : UInt<1>
|
|
|
|
|
dec_tlu_i0_valid_wb1 <= UInt<1>("h00")
|
|
|
|
|
wire dec_tlu_int_valid_wb1 : UInt<1>
|
|
|
|
|
dec_tlu_int_valid_wb1 <= UInt<1>("h00")
|
|
|
|
|
wire dec_tlu_exc_cause_wb1 : UInt<5>
|
|
|
|
|
dec_tlu_exc_cause_wb1 <= UInt<1>("h00")
|
|
|
|
|
wire dec_tlu_mtval_wb1 : UInt<32>
|
|
|
|
|
dec_tlu_mtval_wb1 <= UInt<1>("h00")
|
|
|
|
|
wire dec_tlu_i0_exc_valid_wb1 : UInt<1>
|
|
|
|
|
dec_tlu_i0_exc_valid_wb1 <= UInt<1>("h00")
|
|
|
|
|
wire dec_tlu_trace_disable : UInt<1>
|
|
|
|
|
dec_tlu_trace_disable <= UInt<1>("h00")
|
2021-01-27 21:01:24 +08:00
|
|
|
inst instbuff of dec_ib_ctl @[dec.scala 130:24]
|
2021-01-27 14:46:11 +08:00
|
|
|
instbuff.clock <= clock
|
|
|
|
|
instbuff.reset <= reset
|
2021-01-27 21:01:24 +08:00
|
|
|
inst decode of dec_decode_ctl @[dec.scala 131:22]
|
2021-01-27 14:46:11 +08:00
|
|
|
decode.clock <= clock
|
|
|
|
|
decode.reset <= reset
|
2021-01-27 21:01:24 +08:00
|
|
|
inst gpr of dec_gpr_ctl @[dec.scala 132:19]
|
2021-01-27 14:46:11 +08:00
|
|
|
gpr.clock <= clock
|
|
|
|
|
gpr.reset <= reset
|
2021-01-27 21:01:24 +08:00
|
|
|
inst tlu of dec_tlu_ctl @[dec.scala 133:19]
|
2021-01-27 14:46:11 +08:00
|
|
|
tlu.clock <= clock
|
|
|
|
|
tlu.reset <= reset
|
2021-01-27 21:01:24 +08:00
|
|
|
inst dec_trigger of dec_trigger @[dec.scala 134:27]
|
2021-01-27 14:46:11 +08:00
|
|
|
dec_trigger.clock <= clock
|
|
|
|
|
dec_trigger.reset <= reset
|
2021-01-27 21:01:24 +08:00
|
|
|
instbuff.io.ifu_ib.i0_brp.bits.ret <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[dec.scala 138:22]
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|
|
|
|
instbuff.io.ifu_ib.i0_brp.bits.way <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.i0_brp.bits.prett <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.i0_brp.bits.bank <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.i0_brp.bits.br_start_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.i0_brp.bits.br_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.i0_brp.bits.hist <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.i0_brp.bits.toffset <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[dec.scala 138:22]
|
|
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|
instbuff.io.ifu_ib.i0_brp.valid <= io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[dec.scala 138:22]
|
|
|
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|
instbuff.io.ifu_ib.ifu_i0_pc4 <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[dec.scala 138:22]
|
|
|
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|
instbuff.io.ifu_ib.ifu_i0_pc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.ifu_i0_instr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.ifu_i0_valid <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.ifu_i0_bp_btag <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.ifu_i0_bp_fghr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.ifu_i0_bp_index <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.ifu_i0_dbecc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.ifu_i0_icaf_second <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_second @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.ifu_i0_icaf_type <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[dec.scala 138:22]
|
|
|
|
|
instbuff.io.ifu_ib.ifu_i0_icaf <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[dec.scala 138:22]
|
|
|
|
|
io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= instbuff.io.ib_exu.dec_debug_wdata_rs1_d @[dec.scala 139:22]
|
|
|
|
|
io.dec_exu.ib_exu.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 139:22]
|
|
|
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|
instbuff.io.dbg_ib.dbg_cmd_addr <= io.dec_dbg.dbg_ib.dbg_cmd_addr @[dec.scala 140:22]
|
|
|
|
|
instbuff.io.dbg_ib.dbg_cmd_type <= io.dec_dbg.dbg_ib.dbg_cmd_type @[dec.scala 140:22]
|
|
|
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|
instbuff.io.dbg_ib.dbg_cmd_write <= io.dec_dbg.dbg_ib.dbg_cmd_write @[dec.scala 140:22]
|
|
|
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|
instbuff.io.dbg_ib.dbg_cmd_valid <= io.dec_dbg.dbg_ib.dbg_cmd_valid @[dec.scala 140:22]
|
|
|
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|
instbuff.io.ifu_i0_fa_index <= io.ifu_i0_fa_index @[dec.scala 141:31]
|
|
|
|
|
dec_trigger.io.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 142:30]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 143:34]
|
|
|
|
|
dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 143:34]
|
|
|
|
|
decode.io.dec_aln.ifu_i0_cinst <= io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[dec.scala 147:21]
|
|
|
|
|
io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[dec.scala 148:22]
|
|
|
|
|
decode.io.decode_exu.exu_csr_rs1_x <= io.dec_exu.decode_exu.exu_csr_rs1_x @[dec.scala 149:23]
|
|
|
|
|
decode.io.decode_exu.exu_i0_result_x <= io.dec_exu.decode_exu.exu_i0_result_x @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_extint_stall <= decode.io.decode_exu.dec_extint_stall @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.pred_correct_npc_x <= decode.io.decode_exu.pred_correct_npc_x @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.bfp <= decode.io.decode_exu.mul_p.bits.bfp @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= decode.io.decode_exu.mul_p.bits.crc32c_w @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= decode.io.decode_exu.mul_p.bits.crc32c_h @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= decode.io.decode_exu.mul_p.bits.crc32c_b @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32_w <= decode.io.decode_exu.mul_p.bits.crc32_w @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32_h <= decode.io.decode_exu.mul_p.bits.crc32_h @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.crc32_b <= decode.io.decode_exu.mul_p.bits.crc32_b @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.unshfl <= decode.io.decode_exu.mul_p.bits.unshfl @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.shfl <= decode.io.decode_exu.mul_p.bits.shfl @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.gorc <= decode.io.decode_exu.mul_p.bits.gorc @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.grev <= decode.io.decode_exu.mul_p.bits.grev @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.clmulr <= decode.io.decode_exu.mul_p.bits.clmulr @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.clmulh <= decode.io.decode_exu.mul_p.bits.clmulh @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.clmul <= decode.io.decode_exu.mul_p.bits.clmul @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.bdep <= decode.io.decode_exu.mul_p.bits.bdep @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.bext <= decode.io.decode_exu.mul_p.bits.bext @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.low <= decode.io.decode_exu.mul_p.bits.low @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= decode.io.decode_exu.mul_p.bits.rs2_sign @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= decode.io.decode_exu.mul_p.bits.rs1_sign @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.mul_p.valid <= decode.io.decode_exu.mul_p.valid @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= decode.io.decode_exu.dec_i0_rs2_bypass_en_d @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= decode.io.decode_exu.dec_i0_rs1_bypass_en_d @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_select_pc_d <= decode.io.decode_exu.dec_i0_select_pc_d @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_qual_lsu_d <= decode.io.decode_exu.dec_qual_lsu_d @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_result_r <= decode.io.decode_exu.dec_i0_result_r @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_immed_d <= decode.io.decode_exu.dec_i0_immed_d @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_rs2_en_d <= decode.io.decode_exu.dec_i0_rs2_en_d @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_branch_d <= decode.io.decode_exu.dec_i0_branch_d @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_rs1_en_d <= decode.io.decode_exu.dec_i0_rs1_en_d @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_predict_btag_d <= decode.io.decode_exu.i0_predict_btag_d @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_predict_index_d <= decode.io.decode_exu.i0_predict_index_d @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_predict_fghr_d <= decode.io.decode_exu.i0_predict_fghr_d @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= decode.io.decode_exu.dec_i0_predict_p_d.bits.prett @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pret @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= decode.io.decode_exu.dec_i0_predict_p_d.bits.way @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pja @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pcall @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_error @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.toffset @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= decode.io.decode_exu.dec_i0_predict_p_d.bits.hist @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pc4 @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.boffset @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= decode.io.decode_exu.dec_i0_predict_p_d.bits.ataken @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= decode.io.decode_exu.dec_i0_predict_p_d.bits.misp @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= decode.io.decode_exu.dec_i0_predict_p_d.valid @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.csr_imm <= decode.io.decode_exu.i0_ap.csr_imm @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.csr_write <= decode.io.decode_exu.i0_ap.csr_write @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.predict_nt <= decode.io.decode_exu.i0_ap.predict_nt @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.predict_t <= decode.io.decode_exu.i0_ap.predict_t @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.jal <= decode.io.decode_exu.i0_ap.jal @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.unsign <= decode.io.decode_exu.i0_ap.unsign @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.slt <= decode.io.decode_exu.i0_ap.slt @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sub <= decode.io.decode_exu.i0_ap.sub @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.add <= decode.io.decode_exu.i0_ap.add @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.bge <= decode.io.decode_exu.i0_ap.bge @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.blt <= decode.io.decode_exu.i0_ap.blt @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.bne <= decode.io.decode_exu.i0_ap.bne @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.beq <= decode.io.decode_exu.i0_ap.beq @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sra <= decode.io.decode_exu.i0_ap.sra @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.srl <= decode.io.decode_exu.i0_ap.srl @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sll <= decode.io.decode_exu.i0_ap.sll @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.lxor <= decode.io.decode_exu.i0_ap.lxor @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.lor <= decode.io.decode_exu.i0_ap.lor @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.land <= decode.io.decode_exu.i0_ap.land @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.zba <= decode.io.decode_exu.i0_ap.zba @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sh3add <= decode.io.decode_exu.i0_ap.sh3add @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sh2add <= decode.io.decode_exu.i0_ap.sh2add @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sh1add <= decode.io.decode_exu.i0_ap.sh1add @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sbext <= decode.io.decode_exu.i0_ap.sbext @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sbinv <= decode.io.decode_exu.i0_ap.sbinv @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sbclr <= decode.io.decode_exu.i0_ap.sbclr @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sbset <= decode.io.decode_exu.i0_ap.sbset @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.zbb <= decode.io.decode_exu.i0_ap.zbb @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.gorc <= decode.io.decode_exu.i0_ap.gorc @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.grev <= decode.io.decode_exu.i0_ap.grev @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.ror <= decode.io.decode_exu.i0_ap.ror @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.rol <= decode.io.decode_exu.i0_ap.rol @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.packh <= decode.io.decode_exu.i0_ap.packh @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.packu <= decode.io.decode_exu.i0_ap.packu @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.pack <= decode.io.decode_exu.i0_ap.pack @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.max <= decode.io.decode_exu.i0_ap.max @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.min <= decode.io.decode_exu.i0_ap.min @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sro <= decode.io.decode_exu.i0_ap.sro @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.slo <= decode.io.decode_exu.i0_ap.slo @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sext_h <= decode.io.decode_exu.i0_ap.sext_h @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.sext_b <= decode.io.decode_exu.i0_ap.sext_b @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.pcnt <= decode.io.decode_exu.i0_ap.pcnt @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.ctz <= decode.io.decode_exu.i0_ap.ctz @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.i0_ap.clz <= decode.io.decode_exu.i0_ap.clz @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_ctl_en <= decode.io.decode_exu.dec_ctl_en @[dec.scala 149:23]
|
|
|
|
|
io.dec_exu.decode_exu.dec_data_en <= decode.io.decode_exu.dec_data_en @[dec.scala 149:23]
|
|
|
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|
decode.io.dec_alu.exu_i0_pc_x <= io.dec_exu.dec_alu.exu_i0_pc_x @[dec.scala 150:20]
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|
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io.dec_exu.dec_alu.dec_i0_br_immed_d <= decode.io.dec_alu.dec_i0_br_immed_d @[dec.scala 150:20]
|
|
|
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|
io.dec_exu.dec_alu.dec_csr_ren_d <= decode.io.dec_alu.dec_csr_ren_d @[dec.scala 150:20]
|
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|
io.dec_exu.dec_alu.dec_i0_alu_decode_d <= decode.io.dec_alu.dec_i0_alu_decode_d @[dec.scala 150:20]
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|
|
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|
io.dec_exu.dec_div.dec_div_cancel <= decode.io.dec_div.dec_div_cancel @[dec.scala 151:20]
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|
io.dec_exu.dec_div.div_p.bits.rem <= decode.io.dec_div.div_p.bits.rem @[dec.scala 151:20]
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|
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|
io.dec_exu.dec_div.div_p.bits.unsign <= decode.io.dec_div.div_p.bits.unsign @[dec.scala 151:20]
|
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|
io.dec_exu.dec_div.div_p.valid <= decode.io.dec_div.div_p.valid @[dec.scala 151:20]
|
|
|
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decode.io.dctl_dma.dma_dccm_stall_any <= io.dec_dma.dctl_dma.dma_dccm_stall_any @[dec.scala 152:22]
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|
|
decode.io.dec_tlu_trace_disable <= tlu.io.dec_tlu_trace_disable @[dec.scala 153:48]
|
2021-01-28 15:40:20 +08:00
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|
|
decode.io.dec_debug_valid_d <= instbuff.io.dec_debug_valid_d @[dec.scala 154:48]
|
2021-01-27 21:01:24 +08:00
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|
|
decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[dec.scala 155:48]
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|
decode.io.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 156:48]
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decode.io.dctl_busbuff.lsu_nonblock_load_data_tag <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[dec.scala 157:26]
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decode.io.dctl_busbuff.lsu_nonblock_load_data_error <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[dec.scala 157:26]
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decode.io.dctl_busbuff.lsu_nonblock_load_data_valid <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[dec.scala 157:26]
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decode.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[dec.scala 157:26]
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decode.io.dctl_busbuff.lsu_nonblock_load_inv_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[dec.scala 157:26]
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decode.io.dctl_busbuff.lsu_nonblock_load_tag_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[dec.scala 157:26]
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decode.io.dctl_busbuff.lsu_nonblock_load_valid_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[dec.scala 157:26]
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|
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|
decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[dec.scala 158:48]
|
|
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|
|
decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[dec.scala 159:48]
|
|
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|
|
decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[dec.scala 160:48]
|
|
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|
|
decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[dec.scala 161:48]
|
|
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|
|
decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_misaligned_m @[dec.scala 162:48]
|
|
|
|
|
decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[dec.scala 163:48]
|
|
|
|
|
decode.io.dec_i0_bp_fa_index <= instbuff.io.dec_i0_bp_fa_index @[dec.scala 164:48]
|
|
|
|
|
decode.io.dec_tlu_flush_leak_one_r <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 165:48]
|
|
|
|
|
decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[dec.scala 166:48]
|
|
|
|
|
decode.io.dbg_dctl.dbg_cmd_wrdata <= io.dec_dbg.dbg_dctl.dbg_cmd_wrdata @[dec.scala 167:22]
|
|
|
|
|
decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[dec.scala 168:48]
|
|
|
|
|
decode.io.dec_i0_icaf_second_d <= instbuff.io.dec_i0_icaf_second_d @[dec.scala 169:48]
|
|
|
|
|
decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[dec.scala 170:48]
|
|
|
|
|
decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[dec.scala 171:48]
|
|
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|
decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[dec.scala 172:48]
|
|
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|
|
decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[dec.scala 172:48]
|
|
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|
decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[dec.scala 172:48]
|
|
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|
decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[dec.scala 172:48]
|
|
|
|
|
decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[dec.scala 172:48]
|
|
|
|
|
decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[dec.scala 172:48]
|
|
|
|
|
decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[dec.scala 172:48]
|
|
|
|
|
decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[dec.scala 172:48]
|
|
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|
|
decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[dec.scala 172:48]
|
|
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|
|
decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[dec.scala 173:48]
|
|
|
|
|
decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[dec.scala 174:48]
|
|
|
|
|
decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[dec.scala 175:48]
|
|
|
|
|
decode.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 176:48]
|
|
|
|
|
decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[dec.scala 177:48]
|
|
|
|
|
decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 178:48]
|
|
|
|
|
decode.io.exu_div_wren <= io.exu_div_wren @[dec.scala 179:48]
|
|
|
|
|
decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[dec.scala 180:48]
|
|
|
|
|
decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 181:48]
|
|
|
|
|
decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 182:48]
|
|
|
|
|
decode.io.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 183:48]
|
|
|
|
|
decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[dec.scala 184:48]
|
|
|
|
|
decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[dec.scala 185:48]
|
|
|
|
|
decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[dec.scala 186:48]
|
|
|
|
|
decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[dec.scala 187:48]
|
|
|
|
|
decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[dec.scala 188:48]
|
|
|
|
|
decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[dec.scala 189:48]
|
|
|
|
|
decode.io.lsu_result_m <= io.lsu_result_m @[dec.scala 190:48]
|
|
|
|
|
decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[dec.scala 191:48]
|
|
|
|
|
decode.io.exu_flush_final <= io.exu_flush_final @[dec.scala 192:48]
|
|
|
|
|
decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[dec.scala 193:48]
|
|
|
|
|
decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[dec.scala 194:48]
|
|
|
|
|
decode.io.free_l2clk <= io.free_l2clk @[dec.scala 195:48]
|
|
|
|
|
decode.io.active_clk <= io.active_clk @[dec.scala 196:48]
|
|
|
|
|
decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[dec.scala 197:48]
|
|
|
|
|
decode.io.scan_mode <= io.scan_mode @[dec.scala 198:48]
|
|
|
|
|
dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb @[dec.scala 199:48]
|
|
|
|
|
dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb @[dec.scala 200:48]
|
|
|
|
|
io.lsu_p.bits.store_data_bypass_m <= decode.io.lsu_p.bits.store_data_bypass_m @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.load_ldst_bypass_d <= decode.io.lsu_p.bits.load_ldst_bypass_d @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.store_data_bypass_d <= decode.io.lsu_p.bits.store_data_bypass_d @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.dma <= decode.io.lsu_p.bits.dma @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.unsign <= decode.io.lsu_p.bits.unsign @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.store <= decode.io.lsu_p.bits.store @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.load <= decode.io.lsu_p.bits.load @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.dword <= decode.io.lsu_p.bits.dword @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.word <= decode.io.lsu_p.bits.word @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.half <= decode.io.lsu_p.bits.half @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.by <= decode.io.lsu_p.bits.by @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.stack <= decode.io.lsu_p.bits.stack @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.bits.fast_int <= decode.io.lsu_p.bits.fast_int @[dec.scala 201:48]
|
|
|
|
|
io.lsu_p.valid <= decode.io.lsu_p.valid @[dec.scala 201:48]
|
|
|
|
|
io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[dec.scala 202:48]
|
|
|
|
|
io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[dec.scala 203:48]
|
|
|
|
|
io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[dec.scala 204:48]
|
|
|
|
|
io.dec_exu.decode_exu.dec_qual_lsu_d <= decode.io.decode_exu.dec_qual_lsu_d @[dec.scala 205:48]
|
|
|
|
|
io.dec_fa_error_index <= decode.io.dec_fa_error_index @[dec.scala 206:48]
|
|
|
|
|
gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[dec.scala 208:23]
|
|
|
|
|
gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[dec.scala 209:23]
|
|
|
|
|
gpr.io.wen0 <= decode.io.dec_i0_wen_r @[dec.scala 210:23]
|
|
|
|
|
gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[dec.scala 211:23]
|
|
|
|
|
gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[dec.scala 212:23]
|
|
|
|
|
gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[dec.scala 213:23]
|
|
|
|
|
gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[dec.scala 214:23]
|
|
|
|
|
gpr.io.wd1 <= io.lsu_nonblock_load_data @[dec.scala 215:23]
|
|
|
|
|
gpr.io.wen2 <= io.exu_div_wren @[dec.scala 216:23]
|
|
|
|
|
gpr.io.waddr2 <= decode.io.div_waddr_wb @[dec.scala 217:23]
|
|
|
|
|
gpr.io.wd2 <= io.exu_div_result @[dec.scala 218:23]
|
|
|
|
|
gpr.io.scan_mode <= io.scan_mode @[dec.scala 219:23]
|
|
|
|
|
io.dec_exu.gpr_exu.gpr_i0_rs2_d <= gpr.io.gpr_exu.gpr_i0_rs2_d @[dec.scala 220:22]
|
|
|
|
|
io.dec_exu.gpr_exu.gpr_i0_rs1_d <= gpr.io.gpr_exu.gpr_i0_rs1_d @[dec.scala 220:22]
|
|
|
|
|
tlu.io.tlu_mem.ifu_miss_state_idle <= io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[dec.scala 222:18]
|
|
|
|
|
tlu.io.tlu_mem.ifu_ic_debug_rd_data_valid <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[dec.scala 222:18]
|
|
|
|
|
tlu.io.tlu_mem.ifu_ic_debug_rd_data <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[dec.scala 222:18]
|
|
|
|
|
tlu.io.tlu_mem.ifu_iccm_rd_ecc_single_err <= io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[dec.scala 222:18]
|
|
|
|
|
tlu.io.tlu_mem.ifu_ic_error_start <= io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[dec.scala 222:18]
|
|
|
|
|
tlu.io.tlu_mem.ifu_pmu_bus_trxn <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[dec.scala 222:18]
|
|
|
|
|
tlu.io.tlu_mem.ifu_pmu_bus_busy <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[dec.scala 222:18]
|
|
|
|
|
tlu.io.tlu_mem.ifu_pmu_bus_error <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[dec.scala 222:18]
|
|
|
|
|
tlu.io.tlu_mem.ifu_pmu_ic_hit <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[dec.scala 222:18]
|
|
|
|
|
tlu.io.tlu_mem.ifu_pmu_ic_miss <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[dec.scala 222:18]
|
|
|
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= tlu.io.tlu_mem.dec_tlu_core_ecc_disable @[dec.scala 222:18]
|
|
|
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec.scala 222:18]
|
|
|
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec.scala 222:18]
|
|
|
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics @[dec.scala 222:18]
|
|
|
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata @[dec.scala 222:18]
|
|
|
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= tlu.io.tlu_mem.dec_tlu_fence_i_wb @[dec.scala 222:18]
|
|
|
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 222:18]
|
|
|
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= tlu.io.tlu_mem.dec_tlu_i0_commit_cmt @[dec.scala 222:18]
|
|
|
|
|
io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= tlu.io.tlu_mem.dec_tlu_flush_err_wb @[dec.scala 222:18]
|
|
|
|
|
tlu.io.tlu_ifc.ifu_pmu_fetch_stall <= io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[dec.scala 223:18]
|
|
|
|
|
io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= tlu.io.tlu_ifc.dec_tlu_mrac_ff @[dec.scala 223:18]
|
|
|
|
|
io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= tlu.io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec.scala 223:18]
|
|
|
|
|
io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= tlu.io.tlu_bp.dec_tlu_bpred_disable @[dec.scala 224:18]
|
|
|
|
|
io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 224:18]
|
|
|
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle @[dec.scala 224:18]
|
|
|
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.way @[dec.scala 224:18]
|
|
|
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[dec.scala 224:18]
|
|
|
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error @[dec.scala 224:18]
|
|
|
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist @[dec.scala 224:18]
|
|
|
|
|
io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.valid @[dec.scala 224:18]
|
|
|
|
|
tlu.io.tlu_exu.exu_npc_r <= io.dec_exu.tlu_exu.exu_npc_r @[dec.scala 225:18]
|
|
|
|
|
tlu.io.tlu_exu.exu_pmu_i0_pc4 <= io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[dec.scala 225:18]
|
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tlu.io.tlu_exu.exu_pmu_i0_br_ataken <= io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[dec.scala 225:18]
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tlu.io.tlu_exu.exu_pmu_i0_br_misp <= io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[dec.scala 225:18]
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tlu.io.tlu_exu.exu_i0_br_middle_r <= io.dec_exu.tlu_exu.exu_i0_br_middle_r @[dec.scala 225:18]
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tlu.io.tlu_exu.exu_i0_br_mp_r <= io.dec_exu.tlu_exu.exu_i0_br_mp_r @[dec.scala 225:18]
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tlu.io.tlu_exu.exu_i0_br_valid_r <= io.dec_exu.tlu_exu.exu_i0_br_valid_r @[dec.scala 225:18]
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tlu.io.tlu_exu.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[dec.scala 225:18]
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tlu.io.tlu_exu.exu_i0_br_start_error_r <= io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[dec.scala 225:18]
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tlu.io.tlu_exu.exu_i0_br_error_r <= io.dec_exu.tlu_exu.exu_i0_br_error_r @[dec.scala 225:18]
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tlu.io.tlu_exu.exu_i0_br_hist_r <= io.dec_exu.tlu_exu.exu_i0_br_hist_r @[dec.scala 225:18]
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io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= tlu.io.tlu_exu.dec_tlu_flush_path_r @[dec.scala 225:18]
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io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 225:18]
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io.dec_exu.tlu_exu.dec_tlu_meihap <= tlu.io.tlu_exu.dec_tlu_meihap @[dec.scala 225:18]
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tlu.io.tlu_dma.dma_iccm_stall_any <= io.dec_dma.tlu_dma.dma_iccm_stall_any @[dec.scala 226:18]
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tlu.io.tlu_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dec.scala 226:18]
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io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= tlu.io.tlu_dma.dec_tlu_dma_qos_prty @[dec.scala 226:18]
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tlu.io.tlu_dma.dma_pmu_any_write <= io.dec_dma.tlu_dma.dma_pmu_any_write @[dec.scala 226:18]
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tlu.io.tlu_dma.dma_pmu_any_read <= io.dec_dma.tlu_dma.dma_pmu_any_read @[dec.scala 226:18]
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tlu.io.tlu_dma.dma_pmu_dccm_write <= io.dec_dma.tlu_dma.dma_pmu_dccm_write @[dec.scala 226:18]
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tlu.io.tlu_dma.dma_pmu_dccm_read <= io.dec_dma.tlu_dma.dma_pmu_dccm_read @[dec.scala 226:18]
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tlu.io.free_l2clk <= io.free_l2clk @[dec.scala 227:45]
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tlu.io.free_clk <= io.free_clk @[dec.scala 228:45]
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tlu.io.scan_mode <= io.scan_mode @[dec.scala 229:45]
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tlu.io.rst_vec <= io.rst_vec @[dec.scala 230:45]
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tlu.io.nmi_int <= io.nmi_int @[dec.scala 231:45]
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tlu.io.nmi_vec <= io.nmi_vec @[dec.scala 232:45]
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tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[dec.scala 233:45]
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tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[dec.scala 234:45]
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tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[dec.scala 235:45]
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tlu.io.ifu_pmu_instr_aligned <= io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[dec.scala 236:45]
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tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[dec.scala 237:45]
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tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[dec.scala 238:45]
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tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[dec.scala 239:45]
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tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[dec.scala 240:45]
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tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 241:45]
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tlu.io.tlu_busbuff.lsu_imprecise_error_addr_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[dec.scala 242:26]
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tlu.io.tlu_busbuff.lsu_imprecise_error_store_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[dec.scala 242:26]
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tlu.io.tlu_busbuff.lsu_imprecise_error_load_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[dec.scala 242:26]
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io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= tlu.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[dec.scala 242:26]
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io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= tlu.io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[dec.scala 242:26]
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io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= tlu.io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[dec.scala 242:26]
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tlu.io.tlu_busbuff.lsu_pmu_bus_busy <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[dec.scala 242:26]
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tlu.io.tlu_busbuff.lsu_pmu_bus_error <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[dec.scala 242:26]
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tlu.io.tlu_busbuff.lsu_pmu_bus_misaligned <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[dec.scala 242:26]
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tlu.io.tlu_busbuff.lsu_pmu_bus_trxn <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[dec.scala 242:26]
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tlu.io.lsu_tlu.lsu_pmu_store_external_m <= io.lsu_tlu.lsu_pmu_store_external_m @[dec.scala 243:14]
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tlu.io.lsu_tlu.lsu_pmu_load_external_m <= io.lsu_tlu.lsu_pmu_load_external_m @[dec.scala 243:14]
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tlu.io.dec_pic.mexintpend <= io.dec_pic.mexintpend @[dec.scala 244:14]
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io.dec_pic.dec_tlu_meipt <= tlu.io.dec_pic.dec_tlu_meipt @[dec.scala 244:14]
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|
io.dec_pic.dec_tlu_meicurpl <= tlu.io.dec_pic.dec_tlu_meicurpl @[dec.scala 244:14]
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|
tlu.io.dec_pic.mhwakeup <= io.dec_pic.mhwakeup @[dec.scala 244:14]
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tlu.io.dec_pic.pic_pl <= io.dec_pic.pic_pl @[dec.scala 244:14]
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|
tlu.io.dec_pic.pic_claimid <= io.dec_pic.pic_claimid @[dec.scala 244:14]
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tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[dec.scala 245:45]
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|
tlu.io.lsu_fir_error <= io.lsu_fir_error @[dec.scala 246:45]
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|
tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec.scala 247:45]
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tlu.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec.scala 248:45]
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|
tlu.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec.scala 248:45]
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tlu.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec.scala 248:45]
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|
tlu.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec.scala 248:45]
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|
tlu.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec.scala 248:45]
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|
tlu.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec.scala 248:45]
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|
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|
tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[dec.scala 249:45]
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|
|
tlu.io.dec_pause_state <= decode.io.dec_pause_state @[dec.scala 250:45]
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|
tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[dec.scala 251:45]
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|
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|
tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[dec.scala 252:45]
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|
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|
tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[dec.scala 253:45]
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|
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|
tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[dec.scala 254:45]
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|
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|
tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[dec.scala 255:45]
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|
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|
tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[dec.scala 256:45]
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|
|
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|
tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[dec.scala 257:45]
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|
|
|
|
tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[dec.scala 258:45]
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|
|
|
|
tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[dec.scala 259:45]
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|
|
|
|
tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec.scala 260:45]
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|
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|
tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[dec.scala 260:45]
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|
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|
|
tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec.scala 260:45]
|
|
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|
tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[dec.scala 260:45]
|
|
|
|
|
tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[dec.scala 260:45]
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|
|
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|
tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[dec.scala 260:45]
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|
|
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|
tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[dec.scala 260:45]
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|
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|
tlu.io.dec_tlu_packet_r.icaf_second <= decode.io.dec_tlu_packet_r.icaf_second @[dec.scala 260:45]
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|
|
|
|
tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[dec.scala 260:45]
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|
|
|
|
tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[dec.scala 260:45]
|
|
|
|
|
tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[dec.scala 261:45]
|
|
|
|
|
tlu.io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[dec.scala 262:45]
|
|
|
|
|
tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[dec.scala 263:45]
|
|
|
|
|
tlu.io.dbg_halt_req <= io.dbg_halt_req @[dec.scala 264:45]
|
|
|
|
|
tlu.io.dbg_resume_req <= io.dbg_resume_req @[dec.scala 265:45]
|
|
|
|
|
tlu.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 266:45]
|
|
|
|
|
tlu.io.dec_div_active <= decode.io.dec_div_active @[dec.scala 267:45]
|
|
|
|
|
tlu.io.timer_int <= io.timer_int @[dec.scala 268:45]
|
|
|
|
|
tlu.io.soft_int <= io.soft_int @[dec.scala 269:45]
|
|
|
|
|
tlu.io.core_id <= io.core_id @[dec.scala 270:45]
|
|
|
|
|
tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[dec.scala 271:45]
|
|
|
|
|
tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[dec.scala 272:45]
|
|
|
|
|
tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec.scala 273:45]
|
|
|
|
|
io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[dec.scala 274:28]
|
|
|
|
|
io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[dec.scala 275:28]
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|
|
|
|
io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[dec.scala 276:28]
|
|
|
|
|
io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[dec.scala 277:28]
|
|
|
|
|
io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[dec.scala 278:28]
|
|
|
|
|
io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[dec.scala 279:51]
|
|
|
|
|
io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 280:29]
|
|
|
|
|
io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 280:29]
|
|
|
|
|
io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[dec.scala 281:29]
|
|
|
|
|
io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[dec.scala 282:29]
|
|
|
|
|
io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[dec.scala 283:29]
|
|
|
|
|
io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[dec.scala 284:29]
|
|
|
|
|
io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[dec.scala 285:29]
|
|
|
|
|
io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[dec.scala 286:29]
|
|
|
|
|
io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[dec.scala 287:29]
|
|
|
|
|
io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 288:34]
|
|
|
|
|
io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[dec.scala 289:29]
|
|
|
|
|
io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[dec.scala 290:29]
|
|
|
|
|
io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[dec.scala 291:29]
|
|
|
|
|
io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[dec.scala 292:29]
|
|
|
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dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[dec.scala 293:32]
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dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[dec.scala 294:32]
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dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 295:32]
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dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[dec.scala 296:32]
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dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 297:32]
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io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[dec.scala 298:35]
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io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[dec.scala 299:36]
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io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[dec.scala 300:36]
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io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[dec.scala 301:36]
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io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[dec.scala 302:36]
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io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[dec.scala 303:36]
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io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[dec.scala 304:36]
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io.dec_tlu_picio_clk_override <= tlu.io.dec_tlu_picio_clk_override @[dec.scala 305:36]
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io.dec_tlu_core_empty <= tlu.io.dec_tlu_core_empty @[dec.scala 306:36]
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io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[dec.scala 307:36]
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io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 308:36]
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io.trace_rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb @[dec.scala 312:38]
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2021-01-27 14:46:11 +08:00
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node _T = cat(decode.io.dec_i0_pc_wb, UInt<1>("h00")) @[Cat.scala 29:58]
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2021-01-27 21:01:24 +08:00
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io.trace_rv_trace_pkt.rv_i_address_ip <= _T @[dec.scala 313:41]
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node _T_1 = or(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1) @[dec.scala 314:71]
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node _T_2 = or(_T_1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 314:101]
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io.trace_rv_trace_pkt.rv_i_valid_ip <= _T_2 @[dec.scala 314:39]
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node _T_3 = or(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 315:75]
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io.trace_rv_trace_pkt.rv_i_exception_ip <= _T_3 @[dec.scala 315:43]
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node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[dec.scala 316:71]
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io.trace_rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[dec.scala 316:40]
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io.trace_rv_trace_pkt.rv_i_interrupt_ip <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 317:43]
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io.trace_rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 318:38]
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io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[dec.scala 322:21]
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2021-01-27 14:46:11 +08:00
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