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2 bit divider
2021-01-06 12:32:46 +08:00
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit exu_div_new_2bit_fullshortq :
module exu_div_cls :
input clock : Clock
input reset : Reset
output io : {flip operand : UInt<33>, cls : UInt<5>}
wire cls_zeros : UInt<5>
cls_zeros <= UInt<5>("h00")
wire cls_ones : UInt<5>
cls_ones <= UInt<5>("h00")
node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 655:54]
node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 655:54]
node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 655:54]
node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 655:54]
node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 655:54]
node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 655:54]
node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 655:54]
node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 655:54]
node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 655:54]
node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 655:54]
node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 655:54]
node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 655:54]
node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 655:54]
node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 655:54]
node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 655:54]
node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 655:54]
node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 655:54]
node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 655:54]
node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 655:54]
node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 655:54]
node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 655:54]
node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 655:54]
node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 655:54]
node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 655:54]
node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 655:54]
node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 655:54]
node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 655:54]
node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 655:54]
node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 655:54]
node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 655:54]
node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 655:54]
node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 655:54]
node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_67 = mux(_T_7, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_68 = mux(_T_9, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_69 = mux(_T_11, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_70 = mux(_T_13, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_71 = mux(_T_15, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_72 = mux(_T_17, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_73 = mux(_T_19, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_74 = mux(_T_21, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_75 = mux(_T_23, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_76 = mux(_T_25, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_77 = mux(_T_27, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_78 = mux(_T_29, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_79 = mux(_T_31, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_80 = mux(_T_33, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_81 = mux(_T_35, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_82 = mux(_T_37, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_83 = mux(_T_39, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_84 = mux(_T_41, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_85 = mux(_T_43, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_86 = mux(_T_45, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_87 = mux(_T_47, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_88 = mux(_T_49, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_89 = mux(_T_51, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_90 = mux(_T_53, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_91 = mux(_T_55, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_92 = mux(_T_57, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_93 = mux(_T_59, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_94 = mux(_T_61, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_95 = mux(_T_63, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_96 = or(_T_64, _T_65) @[Mux.scala 27:72]
node _T_97 = or(_T_96, _T_66) @[Mux.scala 27:72]
node _T_98 = or(_T_97, _T_67) @[Mux.scala 27:72]
node _T_99 = or(_T_98, _T_68) @[Mux.scala 27:72]
node _T_100 = or(_T_99, _T_69) @[Mux.scala 27:72]
node _T_101 = or(_T_100, _T_70) @[Mux.scala 27:72]
node _T_102 = or(_T_101, _T_71) @[Mux.scala 27:72]
node _T_103 = or(_T_102, _T_72) @[Mux.scala 27:72]
node _T_104 = or(_T_103, _T_73) @[Mux.scala 27:72]
node _T_105 = or(_T_104, _T_74) @[Mux.scala 27:72]
node _T_106 = or(_T_105, _T_75) @[Mux.scala 27:72]
node _T_107 = or(_T_106, _T_76) @[Mux.scala 27:72]
node _T_108 = or(_T_107, _T_77) @[Mux.scala 27:72]
node _T_109 = or(_T_108, _T_78) @[Mux.scala 27:72]
node _T_110 = or(_T_109, _T_79) @[Mux.scala 27:72]
node _T_111 = or(_T_110, _T_80) @[Mux.scala 27:72]
node _T_112 = or(_T_111, _T_81) @[Mux.scala 27:72]
node _T_113 = or(_T_112, _T_82) @[Mux.scala 27:72]
node _T_114 = or(_T_113, _T_83) @[Mux.scala 27:72]
node _T_115 = or(_T_114, _T_84) @[Mux.scala 27:72]
node _T_116 = or(_T_115, _T_85) @[Mux.scala 27:72]
node _T_117 = or(_T_116, _T_86) @[Mux.scala 27:72]
node _T_118 = or(_T_117, _T_87) @[Mux.scala 27:72]
node _T_119 = or(_T_118, _T_88) @[Mux.scala 27:72]
node _T_120 = or(_T_119, _T_89) @[Mux.scala 27:72]
node _T_121 = or(_T_120, _T_90) @[Mux.scala 27:72]
node _T_122 = or(_T_121, _T_91) @[Mux.scala 27:72]
node _T_123 = or(_T_122, _T_92) @[Mux.scala 27:72]
node _T_124 = or(_T_123, _T_93) @[Mux.scala 27:72]
node _T_125 = or(_T_124, _T_94) @[Mux.scala 27:72]
node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72]
wire _T_127 : UInt<5> @[Mux.scala 27:72]
_T_127 <= _T_126 @[Mux.scala 27:72]
cls_zeros <= _T_127 @[exu_div_ctl.scala 655:13]
node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 657:18]
node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 657:25]
when _T_129 : @[exu_div_ctl.scala 657:44]
cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 657:55]
skip @[exu_div_ctl.scala 657:44]
else : @[exu_div_ctl.scala 658:15]
node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 658:66]
node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 658:76]
node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 658:66]
node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 658:76]
node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 658:66]
node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 658:76]
node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 658:66]
node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 658:76]
node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 658:66]
node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 658:76]
node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 658:66]
node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 658:76]
node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 658:66]
node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 658:76]
node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 658:66]
node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 658:76]
node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 658:66]
node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 658:76]
node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 658:66]
node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12]
node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 658:76]
node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 658:66]
node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12]
node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 658:76]
node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 658:66]
node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 658:76]
node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 658:66]
node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 658:76]
node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 658:66]
node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12]
node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 658:76]
node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 658:66]
node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12]
node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 658:76]
node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 658:66]
node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 658:76]
node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 658:66]
node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 658:76]
node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 658:66]
node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12]
node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 658:76]
node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 658:66]
node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 658:76]
node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 658:66]
node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 658:76]
node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 658:66]
node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12]
node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 658:76]
node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 658:66]
node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12]
node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 658:76]
node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 658:66]
node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12]
node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 658:76]
node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 658:66]
node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 658:76]
node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 658:66]
node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12]
node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 658:76]
node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 658:66]
node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 658:76]
node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 658:66]
node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12]
node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 658:76]
node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 658:66]
node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 658:76]
node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 658:66]
node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 658:76]
node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 658:66]
node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 658:76]
node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 658:66]
node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 658:76]
node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_287 = mux(_T_148, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_288 = mux(_T_153, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_289 = mux(_T_158, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_290 = mux(_T_163, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_291 = mux(_T_168, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_292 = mux(_T_173, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_293 = mux(_T_178, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_294 = mux(_T_183, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_295 = mux(_T_188, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_296 = mux(_T_193, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_297 = mux(_T_198, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_298 = mux(_T_203, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_299 = mux(_T_208, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_300 = mux(_T_213, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_301 = mux(_T_218, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_302 = mux(_T_223, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_303 = mux(_T_228, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_304 = mux(_T_233, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_305 = mux(_T_238, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_306 = mux(_T_243, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_307 = mux(_T_248, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_308 = mux(_T_253, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_309 = mux(_T_258, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_310 = mux(_T_263, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_311 = mux(_T_268, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_312 = mux(_T_273, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_313 = mux(_T_278, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_314 = mux(_T_283, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_315 = or(_T_284, _T_285) @[Mux.scala 27:72]
node _T_316 = or(_T_315, _T_286) @[Mux.scala 27:72]
node _T_317 = or(_T_316, _T_287) @[Mux.scala 27:72]
node _T_318 = or(_T_317, _T_288) @[Mux.scala 27:72]
node _T_319 = or(_T_318, _T_289) @[Mux.scala 27:72]
node _T_320 = or(_T_319, _T_290) @[Mux.scala 27:72]
node _T_321 = or(_T_320, _T_291) @[Mux.scala 27:72]
node _T_322 = or(_T_321, _T_292) @[Mux.scala 27:72]
node _T_323 = or(_T_322, _T_293) @[Mux.scala 27:72]
node _T_324 = or(_T_323, _T_294) @[Mux.scala 27:72]
node _T_325 = or(_T_324, _T_295) @[Mux.scala 27:72]
node _T_326 = or(_T_325, _T_296) @[Mux.scala 27:72]
node _T_327 = or(_T_326, _T_297) @[Mux.scala 27:72]
node _T_328 = or(_T_327, _T_298) @[Mux.scala 27:72]
node _T_329 = or(_T_328, _T_299) @[Mux.scala 27:72]
node _T_330 = or(_T_329, _T_300) @[Mux.scala 27:72]
node _T_331 = or(_T_330, _T_301) @[Mux.scala 27:72]
node _T_332 = or(_T_331, _T_302) @[Mux.scala 27:72]
node _T_333 = or(_T_332, _T_303) @[Mux.scala 27:72]
node _T_334 = or(_T_333, _T_304) @[Mux.scala 27:72]
node _T_335 = or(_T_334, _T_305) @[Mux.scala 27:72]
node _T_336 = or(_T_335, _T_306) @[Mux.scala 27:72]
node _T_337 = or(_T_336, _T_307) @[Mux.scala 27:72]
node _T_338 = or(_T_337, _T_308) @[Mux.scala 27:72]
node _T_339 = or(_T_338, _T_309) @[Mux.scala 27:72]
node _T_340 = or(_T_339, _T_310) @[Mux.scala 27:72]
node _T_341 = or(_T_340, _T_311) @[Mux.scala 27:72]
node _T_342 = or(_T_341, _T_312) @[Mux.scala 27:72]
node _T_343 = or(_T_342, _T_313) @[Mux.scala 27:72]
node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72]
wire _T_345 : UInt<5> @[Mux.scala 27:72]
_T_345 <= _T_344 @[Mux.scala 27:72]
cls_ones <= _T_345 @[exu_div_ctl.scala 658:25]
skip @[exu_div_ctl.scala 658:15]
node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 659:27]
node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 659:16]
io.cls <= _T_347 @[exu_div_ctl.scala 659:10]
module exu_div_cls_1 :
input clock : Clock
input reset : Reset
output io : {flip operand : UInt<33>, cls : UInt<5>}
wire cls_zeros : UInt<5>
cls_zeros <= UInt<5>("h00")
wire cls_ones : UInt<5>
cls_ones <= UInt<5>("h00")
node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 655:54]
node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 655:54]
node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 655:54]
node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 655:54]
node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 655:54]
node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 655:54]
node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 655:54]
node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 655:54]
node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 655:54]
node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 655:54]
node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 655:54]
node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 655:54]
node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 655:54]
node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 655:54]
node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 655:54]
node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 655:54]
node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 655:54]
node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 655:54]
node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 655:54]
node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 655:54]
node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 655:54]
node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 655:54]
node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 655:54]
node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 655:54]
node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 655:54]
node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 655:54]
node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 655:54]
node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 655:54]
node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 655:54]
node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 655:54]
node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 655:54]
node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 655:54]
node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 655:63]
node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_67 = mux(_T_7, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_68 = mux(_T_9, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_69 = mux(_T_11, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_70 = mux(_T_13, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_71 = mux(_T_15, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_72 = mux(_T_17, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_73 = mux(_T_19, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_74 = mux(_T_21, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_75 = mux(_T_23, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_76 = mux(_T_25, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_77 = mux(_T_27, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_78 = mux(_T_29, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_79 = mux(_T_31, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_80 = mux(_T_33, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_81 = mux(_T_35, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_82 = mux(_T_37, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_83 = mux(_T_39, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_84 = mux(_T_41, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_85 = mux(_T_43, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_86 = mux(_T_45, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_87 = mux(_T_47, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_88 = mux(_T_49, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_89 = mux(_T_51, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_90 = mux(_T_53, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_91 = mux(_T_55, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_92 = mux(_T_57, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_93 = mux(_T_59, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_94 = mux(_T_61, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_95 = mux(_T_63, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_96 = or(_T_64, _T_65) @[Mux.scala 27:72]
node _T_97 = or(_T_96, _T_66) @[Mux.scala 27:72]
node _T_98 = or(_T_97, _T_67) @[Mux.scala 27:72]
node _T_99 = or(_T_98, _T_68) @[Mux.scala 27:72]
node _T_100 = or(_T_99, _T_69) @[Mux.scala 27:72]
node _T_101 = or(_T_100, _T_70) @[Mux.scala 27:72]
node _T_102 = or(_T_101, _T_71) @[Mux.scala 27:72]
node _T_103 = or(_T_102, _T_72) @[Mux.scala 27:72]
node _T_104 = or(_T_103, _T_73) @[Mux.scala 27:72]
node _T_105 = or(_T_104, _T_74) @[Mux.scala 27:72]
node _T_106 = or(_T_105, _T_75) @[Mux.scala 27:72]
node _T_107 = or(_T_106, _T_76) @[Mux.scala 27:72]
node _T_108 = or(_T_107, _T_77) @[Mux.scala 27:72]
node _T_109 = or(_T_108, _T_78) @[Mux.scala 27:72]
node _T_110 = or(_T_109, _T_79) @[Mux.scala 27:72]
node _T_111 = or(_T_110, _T_80) @[Mux.scala 27:72]
node _T_112 = or(_T_111, _T_81) @[Mux.scala 27:72]
node _T_113 = or(_T_112, _T_82) @[Mux.scala 27:72]
node _T_114 = or(_T_113, _T_83) @[Mux.scala 27:72]
node _T_115 = or(_T_114, _T_84) @[Mux.scala 27:72]
node _T_116 = or(_T_115, _T_85) @[Mux.scala 27:72]
node _T_117 = or(_T_116, _T_86) @[Mux.scala 27:72]
node _T_118 = or(_T_117, _T_87) @[Mux.scala 27:72]
node _T_119 = or(_T_118, _T_88) @[Mux.scala 27:72]
node _T_120 = or(_T_119, _T_89) @[Mux.scala 27:72]
node _T_121 = or(_T_120, _T_90) @[Mux.scala 27:72]
node _T_122 = or(_T_121, _T_91) @[Mux.scala 27:72]
node _T_123 = or(_T_122, _T_92) @[Mux.scala 27:72]
node _T_124 = or(_T_123, _T_93) @[Mux.scala 27:72]
node _T_125 = or(_T_124, _T_94) @[Mux.scala 27:72]
node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72]
wire _T_127 : UInt<5> @[Mux.scala 27:72]
_T_127 <= _T_126 @[Mux.scala 27:72]
cls_zeros <= _T_127 @[exu_div_ctl.scala 655:13]
node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 657:18]
node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 657:25]
when _T_129 : @[exu_div_ctl.scala 657:44]
cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 657:55]
skip @[exu_div_ctl.scala 657:44]
else : @[exu_div_ctl.scala 658:15]
node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 658:66]
node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 658:76]
node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 658:66]
node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 658:76]
node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 658:66]
node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 658:76]
node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 658:66]
node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 658:76]
node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 658:66]
node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 658:76]
node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 658:66]
node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 658:76]
node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 658:66]
node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 658:76]
node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 658:66]
node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 658:76]
node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 658:66]
node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 658:76]
node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 658:66]
node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12]
node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 658:76]
node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 658:66]
node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12]
node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 658:76]
node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 658:66]
node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 658:76]
node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 658:66]
node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 658:76]
node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 658:66]
node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12]
node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 658:76]
node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 658:66]
node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12]
node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 658:76]
node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 658:66]
node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 658:76]
node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 658:66]
node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 658:76]
node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 658:66]
node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12]
node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 658:76]
node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 658:66]
node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 658:76]
node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 658:66]
node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 658:76]
node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 658:66]
node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12]
node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 658:76]
node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 658:66]
node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12]
node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 658:76]
node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 658:66]
node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12]
node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 658:76]
node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 658:66]
node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 658:76]
node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 658:66]
node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12]
node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 658:76]
node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 658:66]
node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 658:76]
node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 658:66]
node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12]
node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 658:76]
node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 658:66]
node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 658:76]
node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 658:66]
node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 658:76]
node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 658:66]
node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 658:76]
node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 658:66]
node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 658:76]
node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 658:102]
node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_287 = mux(_T_148, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_288 = mux(_T_153, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_289 = mux(_T_158, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_290 = mux(_T_163, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_291 = mux(_T_168, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_292 = mux(_T_173, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_293 = mux(_T_178, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_294 = mux(_T_183, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_295 = mux(_T_188, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_296 = mux(_T_193, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_297 = mux(_T_198, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_298 = mux(_T_203, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_299 = mux(_T_208, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_300 = mux(_T_213, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_301 = mux(_T_218, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_302 = mux(_T_223, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_303 = mux(_T_228, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_304 = mux(_T_233, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_305 = mux(_T_238, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_306 = mux(_T_243, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_307 = mux(_T_248, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_308 = mux(_T_253, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_309 = mux(_T_258, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_310 = mux(_T_263, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_311 = mux(_T_268, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_312 = mux(_T_273, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_313 = mux(_T_278, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_314 = mux(_T_283, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_315 = or(_T_284, _T_285) @[Mux.scala 27:72]
node _T_316 = or(_T_315, _T_286) @[Mux.scala 27:72]
node _T_317 = or(_T_316, _T_287) @[Mux.scala 27:72]
node _T_318 = or(_T_317, _T_288) @[Mux.scala 27:72]
node _T_319 = or(_T_318, _T_289) @[Mux.scala 27:72]
node _T_320 = or(_T_319, _T_290) @[Mux.scala 27:72]
node _T_321 = or(_T_320, _T_291) @[Mux.scala 27:72]
node _T_322 = or(_T_321, _T_292) @[Mux.scala 27:72]
node _T_323 = or(_T_322, _T_293) @[Mux.scala 27:72]
node _T_324 = or(_T_323, _T_294) @[Mux.scala 27:72]
node _T_325 = or(_T_324, _T_295) @[Mux.scala 27:72]
node _T_326 = or(_T_325, _T_296) @[Mux.scala 27:72]
node _T_327 = or(_T_326, _T_297) @[Mux.scala 27:72]
node _T_328 = or(_T_327, _T_298) @[Mux.scala 27:72]
node _T_329 = or(_T_328, _T_299) @[Mux.scala 27:72]
node _T_330 = or(_T_329, _T_300) @[Mux.scala 27:72]
node _T_331 = or(_T_330, _T_301) @[Mux.scala 27:72]
node _T_332 = or(_T_331, _T_302) @[Mux.scala 27:72]
node _T_333 = or(_T_332, _T_303) @[Mux.scala 27:72]
node _T_334 = or(_T_333, _T_304) @[Mux.scala 27:72]
node _T_335 = or(_T_334, _T_305) @[Mux.scala 27:72]
node _T_336 = or(_T_335, _T_306) @[Mux.scala 27:72]
node _T_337 = or(_T_336, _T_307) @[Mux.scala 27:72]
node _T_338 = or(_T_337, _T_308) @[Mux.scala 27:72]
node _T_339 = or(_T_338, _T_309) @[Mux.scala 27:72]
node _T_340 = or(_T_339, _T_310) @[Mux.scala 27:72]
node _T_341 = or(_T_340, _T_311) @[Mux.scala 27:72]
node _T_342 = or(_T_341, _T_312) @[Mux.scala 27:72]
node _T_343 = or(_T_342, _T_313) @[Mux.scala 27:72]
node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72]
wire _T_345 : UInt<5> @[Mux.scala 27:72]
_T_345 <= _T_344 @[Mux.scala 27:72]
cls_ones <= _T_345 @[exu_div_ctl.scala 658:25]
skip @[exu_div_ctl.scala 658:15]
node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 659:27]
node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 659:16]
io.cls <= _T_347 @[exu_div_ctl.scala 659:10]
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_4 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_5 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_5 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_6 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_7 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_8 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_8 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_9 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_9 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_10 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_10 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_10 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
module exu_div_new_2bit_fullshortq :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip cancel : UInt<1>, flip valid_in : UInt<1>, flip signed_in : UInt<1>, flip rem_in : UInt<1>, flip dividend_in : UInt<32>, flip divisor_in : UInt<32>, data_out : UInt<32>, valid_out : UInt<1>}
wire valid_ff : UInt<1>
valid_ff <= UInt<1>("h00")
wire finish_ff : UInt<1>
finish_ff <= UInt<1>("h00")
wire control_ff : UInt<3>
control_ff <= UInt<3>("h00")
wire count_ff : UInt<7>
count_ff <= UInt<7>("h00")
wire smallnum : UInt<4>
smallnum <= UInt<4>("h00")
wire a_ff : UInt<32>
a_ff <= UInt<32>("h00")
wire b_ff1 : UInt<33>
b_ff1 <= UInt<33>("h00")
wire b_ff : UInt<35>
b_ff <= UInt<35>("h00")
wire q_ff : UInt<32>
q_ff <= UInt<32>("h00")
wire r_ff : UInt<32>
r_ff <= UInt<32>("h00")
quotient new changed
2021-01-06 13:05:37 +08:00
wire quotient_raw : UInt<4>
quotient_raw <= UInt<4>("h00")
2 bit divider
2021-01-06 12:32:46 +08:00
wire quotient_new : UInt<2>
quotient_new <= UInt<2>("h00")
wire shortq_enable : UInt<1>
shortq_enable <= UInt<1>("h00")
wire shortq_enable_ff : UInt<1>
shortq_enable_ff <= UInt<1>("h00")
wire by_zero_case_ff : UInt<1>
by_zero_case_ff <= UInt<1>("h00")
wire ar_shifted : UInt<64>
ar_shifted <= UInt<64>("h00")
small numcase corrected
2021-01-06 13:22:58 +08:00
wire shortq_shift_ff : UInt<5>
shortq_shift_ff <= UInt<5>("h00")
2 bit divider
2021-01-06 12:32:46 +08:00
node _T = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 488:35]
node valid_ff_in = and(io.valid_in, _T) @[exu_div_ctl.scala 488:33]
node _T_1 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 489:35]
node _T_2 = bits(control_ff, 2, 2) @[exu_div_ctl.scala 489:60]
node _T_3 = and(_T_1, _T_2) @[exu_div_ctl.scala 489:48]
node _T_4 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 489:80]
node _T_5 = bits(io.dividend_in, 31, 31) @[exu_div_ctl.scala 489:112]
node _T_6 = and(_T_4, _T_5) @[exu_div_ctl.scala 489:96]
node _T_7 = or(_T_3, _T_6) @[exu_div_ctl.scala 489:65]
node _T_8 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 489:120]
node _T_9 = bits(control_ff, 1, 1) @[exu_div_ctl.scala 489:145]
node _T_10 = and(_T_8, _T_9) @[exu_div_ctl.scala 489:133]
node _T_11 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 489:165]
node _T_12 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 489:197]
node _T_13 = and(_T_11, _T_12) @[exu_div_ctl.scala 489:181]
node _T_14 = or(_T_10, _T_13) @[exu_div_ctl.scala 489:150]
node _T_15 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 489:205]
node _T_16 = bits(control_ff, 0, 0) @[exu_div_ctl.scala 489:230]
node _T_17 = and(_T_15, _T_16) @[exu_div_ctl.scala 489:218]
node _T_18 = and(io.valid_in, io.rem_in) @[exu_div_ctl.scala 489:250]
node _T_19 = or(_T_17, _T_18) @[exu_div_ctl.scala 489:235]
node _T_20 = cat(_T_7, _T_14) @[Cat.scala 29:58]
node control_in = cat(_T_20, _T_19) @[Cat.scala 29:58]
node dividend_sign_ff = bits(control_ff, 2, 2) @[exu_div_ctl.scala 490:40]
node divisor_sign_ff = bits(control_ff, 1, 1) @[exu_div_ctl.scala 491:40]
node rem_ff = bits(control_ff, 0, 0) @[exu_div_ctl.scala 492:40]
node _T_21 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 493:47]
node _T_22 = eq(_T_21, UInt<1>("h00")) @[exu_div_ctl.scala 493:54]
node by_zero_case = and(valid_ff, _T_22) @[exu_div_ctl.scala 493:40]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_23 = bits(a_ff, 31, 4) @[exu_div_ctl.scala 495:30]
node _T_24 = eq(_T_23, UInt<1>("h00")) @[exu_div_ctl.scala 495:37]
node _T_25 = bits(b_ff, 31, 4) @[exu_div_ctl.scala 495:53]
node _T_26 = eq(_T_25, UInt<1>("h00")) @[exu_div_ctl.scala 495:60]
node _T_27 = and(_T_24, _T_26) @[exu_div_ctl.scala 495:46]
node _T_28 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 495:71]
node _T_29 = and(_T_27, _T_28) @[exu_div_ctl.scala 495:69]
node _T_30 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 495:87]
node _T_31 = and(_T_29, _T_30) @[exu_div_ctl.scala 495:85]
node _T_32 = and(_T_31, valid_ff) @[exu_div_ctl.scala 495:95]
node _T_33 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 495:108]
node _T_34 = and(_T_32, _T_33) @[exu_div_ctl.scala 495:106]
node _T_35 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 496:11]
node _T_36 = eq(_T_35, UInt<1>("h00")) @[exu_div_ctl.scala 496:18]
node _T_37 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 496:29]
node _T_38 = and(_T_36, _T_37) @[exu_div_ctl.scala 496:27]
node _T_39 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 496:45]
node _T_40 = and(_T_38, _T_39) @[exu_div_ctl.scala 496:43]
node _T_41 = and(_T_40, valid_ff) @[exu_div_ctl.scala 496:53]
node _T_42 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 496:66]
node _T_43 = and(_T_41, _T_42) @[exu_div_ctl.scala 496:64]
node smallnum_case = or(_T_34, _T_43) @[exu_div_ctl.scala 495:120]
node _T_44 = orr(count_ff) @[exu_div_ctl.scala 497:42]
node running_state = or(_T_44, shortq_enable_ff) @[exu_div_ctl.scala 497:45]
node _T_45 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 498:43]
node _T_46 = or(_T_45, io.cancel) @[exu_div_ctl.scala 498:54]
node _T_47 = or(_T_46, running_state) @[exu_div_ctl.scala 498:66]
node misc_enable = or(_T_47, finish_ff) @[exu_div_ctl.scala 498:82]
node _T_48 = or(smallnum_case, by_zero_case) @[exu_div_ctl.scala 499:45]
node _T_49 = eq(count_ff, UInt<6>("h020")) @[exu_div_ctl.scala 499:72]
node finish_raw = or(_T_48, _T_49) @[exu_div_ctl.scala 499:60]
node _T_50 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 500:43]
node finish = and(finish_raw, _T_50) @[exu_div_ctl.scala 500:41]
node _T_51 = or(valid_ff, running_state) @[exu_div_ctl.scala 501:40]
node _T_52 = eq(finish, UInt<1>("h00")) @[exu_div_ctl.scala 501:59]
node _T_53 = and(_T_51, _T_52) @[exu_div_ctl.scala 501:57]
node _T_54 = eq(finish_ff, UInt<1>("h00")) @[exu_div_ctl.scala 501:69]
node _T_55 = and(_T_53, _T_54) @[exu_div_ctl.scala 501:67]
node _T_56 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 501:82]
node _T_57 = and(_T_55, _T_56) @[exu_div_ctl.scala 501:80]
node _T_58 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 501:95]
node count_enable = and(_T_57, _T_58) @[exu_div_ctl.scala 501:93]
node _T_59 = bits(count_enable, 0, 0) @[Bitwise.scala 72:15]
node _T_60 = mux(_T_59, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
node _T_61 = cat(UInt<5>("h00"), UInt<2>("h02")) @[Cat.scala 29:58]
node _T_62 = add(count_ff, _T_61) @[exu_div_ctl.scala 502:63]
node _T_63 = tail(_T_62, 1) @[exu_div_ctl.scala 502:63]
node _T_64 = bits(shortq_shift_ff, 4, 1) @[exu_div_ctl.scala 502:113]
node _T_65 = cat(UInt<2>("h00"), _T_64) @[Cat.scala 29:58]
node _T_66 = cat(_T_65, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_67 = add(_T_63, _T_66) @[exu_div_ctl.scala 502:83]
node _T_68 = tail(_T_67, 1) @[exu_div_ctl.scala 502:83]
node count_in = and(_T_60, _T_68) @[exu_div_ctl.scala 502:51]
2 bit divider
2021-01-06 12:32:46 +08:00
node a_enable = or(io.valid_in, running_state) @[exu_div_ctl.scala 503:43]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_69 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 504:47]
node a_shift = and(running_state, _T_69) @[exu_div_ctl.scala 504:45]
node _T_70 = bits(dividend_sign_ff, 0, 0) @[Bitwise.scala 72:15]
node _T_71 = mux(_T_70, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_72 = cat(_T_71, a_ff) @[Cat.scala 29:58]
node _T_73 = bits(shortq_shift_ff, 4, 1) @[exu_div_ctl.scala 505:90]
node _T_74 = cat(_T_73, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_75 = dshl(_T_72, _T_74) @[exu_div_ctl.scala 505:68]
ar_shifted <= _T_75 @[exu_div_ctl.scala 505:28]
node _T_76 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 506:61]
node _T_77 = eq(_T_76, UInt<1>("h00")) @[exu_div_ctl.scala 506:42]
node b_twos_comp = and(valid_ff, _T_77) @[exu_div_ctl.scala 506:40]
node _T_78 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 507:62]
node _T_79 = eq(_T_78, UInt<1>("h00")) @[exu_div_ctl.scala 507:43]
node twos_comp_b_sel = and(valid_ff, _T_79) @[exu_div_ctl.scala 507:41]
node _T_80 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 508:30]
node _T_81 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 508:42]
node _T_82 = and(_T_80, _T_81) @[exu_div_ctl.scala 508:40]
node _T_83 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 508:71]
node _T_84 = and(_T_82, _T_83) @[exu_div_ctl.scala 508:50]
node _T_85 = eq(by_zero_case_ff, UInt<1>("h00")) @[exu_div_ctl.scala 508:92]
node twos_comp_q_sel = and(_T_84, _T_85) @[exu_div_ctl.scala 508:90]
2 bit divider
2021-01-06 12:32:46 +08:00
node b_enable = or(io.valid_in, b_twos_comp) @[exu_div_ctl.scala 509:43]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_86 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 510:43]
node rq_enable = or(_T_86, running_state) @[exu_div_ctl.scala 510:54]
node _T_87 = and(valid_ff, dividend_sign_ff) @[exu_div_ctl.scala 511:40]
node _T_88 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 511:61]
node r_sign_sel = and(_T_87, _T_88) @[exu_div_ctl.scala 511:59]
node _T_89 = eq(quotient_new, UInt<1>("h00")) @[exu_div_ctl.scala 512:61]
node _T_90 = and(running_state, _T_89) @[exu_div_ctl.scala 512:45]
node _T_91 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 512:72]
node r_restore_sel = and(_T_90, _T_91) @[exu_div_ctl.scala 512:70]
node _T_92 = eq(quotient_new, UInt<1>("h01")) @[exu_div_ctl.scala 513:61]
node _T_93 = and(running_state, _T_92) @[exu_div_ctl.scala 513:45]
node _T_94 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 513:72]
node r_adder1_sel = and(_T_93, _T_94) @[exu_div_ctl.scala 513:70]
node _T_95 = eq(quotient_new, UInt<2>("h02")) @[exu_div_ctl.scala 514:61]
node _T_96 = and(running_state, _T_95) @[exu_div_ctl.scala 514:45]
node _T_97 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 514:72]
node r_adder2_sel = and(_T_96, _T_97) @[exu_div_ctl.scala 514:70]
node _T_98 = eq(quotient_new, UInt<2>("h03")) @[exu_div_ctl.scala 515:61]
node _T_99 = and(running_state, _T_98) @[exu_div_ctl.scala 515:45]
node _T_100 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 515:72]
node r_adder3_sel = and(_T_99, _T_100) @[exu_div_ctl.scala 515:70]
node _T_101 = bits(r_ff, 30, 0) @[exu_div_ctl.scala 516:28]
node _T_102 = bits(a_ff, 31, 30) @[exu_div_ctl.scala 516:39]
node _T_103 = cat(_T_101, _T_102) @[Cat.scala 29:58]
node _T_104 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 516:54]
node _T_105 = add(_T_103, _T_104) @[exu_div_ctl.scala 516:48]
node adder1_out = tail(_T_105, 1) @[exu_div_ctl.scala 516:48]
node _T_106 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 517:28]
node _T_107 = bits(a_ff, 31, 30) @[exu_div_ctl.scala 517:39]
node _T_108 = cat(_T_106, _T_107) @[Cat.scala 29:58]
node _T_109 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 517:58]
node _T_110 = cat(_T_109, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_111 = add(_T_108, _T_110) @[exu_div_ctl.scala 517:48]
node adder2_out = tail(_T_111, 1) @[exu_div_ctl.scala 517:48]
node _T_112 = bits(r_ff, 31, 31) @[exu_div_ctl.scala 518:28]
node _T_113 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 518:37]
node _T_114 = bits(a_ff, 31, 30) @[exu_div_ctl.scala 518:48]
node _T_115 = cat(_T_112, _T_113) @[Cat.scala 29:58]
node _T_116 = cat(_T_115, _T_114) @[Cat.scala 29:58]
node _T_117 = bits(b_ff, 33, 0) @[exu_div_ctl.scala 518:67]
node _T_118 = cat(_T_117, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_119 = add(_T_116, _T_118) @[exu_div_ctl.scala 518:57]
node _T_120 = tail(_T_119, 1) @[exu_div_ctl.scala 518:57]
node _T_121 = add(_T_120, b_ff) @[exu_div_ctl.scala 518:79]
node adder3_out = tail(_T_121, 1) @[exu_div_ctl.scala 518:79]
node _T_122 = bits(adder3_out, 34, 34) @[exu_div_ctl.scala 519:35]
node _T_123 = eq(_T_122, UInt<1>("h00")) @[exu_div_ctl.scala 519:24]
node _T_124 = xor(_T_123, dividend_sign_ff) @[exu_div_ctl.scala 519:40]
node _T_125 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 519:68]
node _T_126 = eq(_T_125, UInt<1>("h00")) @[exu_div_ctl.scala 519:75]
node _T_127 = eq(adder3_out, UInt<1>("h00")) @[exu_div_ctl.scala 519:98]
node _T_128 = and(_T_126, _T_127) @[exu_div_ctl.scala 519:84]
node _T_129 = or(_T_124, _T_128) @[exu_div_ctl.scala 519:60]
node _T_130 = bits(adder2_out, 33, 33) @[exu_div_ctl.scala 520:17]
node _T_131 = eq(_T_130, UInt<1>("h00")) @[exu_div_ctl.scala 520:6]
node _T_132 = xor(_T_131, dividend_sign_ff) @[exu_div_ctl.scala 520:22]
node _T_133 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 520:50]
node _T_134 = eq(_T_133, UInt<1>("h00")) @[exu_div_ctl.scala 520:57]
node _T_135 = eq(adder2_out, UInt<1>("h00")) @[exu_div_ctl.scala 520:80]
node _T_136 = and(_T_134, _T_135) @[exu_div_ctl.scala 520:66]
node _T_137 = or(_T_132, _T_136) @[exu_div_ctl.scala 520:42]
node _T_138 = bits(adder1_out, 32, 32) @[exu_div_ctl.scala 521:17]
node _T_139 = eq(_T_138, UInt<1>("h00")) @[exu_div_ctl.scala 521:6]
node _T_140 = xor(_T_139, dividend_sign_ff) @[exu_div_ctl.scala 521:22]
node _T_141 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 521:50]
node _T_142 = eq(_T_141, UInt<1>("h00")) @[exu_div_ctl.scala 521:57]
node _T_143 = eq(adder1_out, UInt<1>("h00")) @[exu_div_ctl.scala 521:80]
node _T_144 = and(_T_142, _T_143) @[exu_div_ctl.scala 521:66]
node _T_145 = or(_T_140, _T_144) @[exu_div_ctl.scala 521:42]
node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_147 = cat(_T_129, _T_137) @[Cat.scala 29:58]
node _T_148 = cat(_T_147, _T_146) @[Cat.scala 29:58]
quotient_raw <= _T_148 @[exu_div_ctl.scala 519:16]
node _T_149 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 522:37]
node _T_150 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 522:56]
node _T_151 = or(_T_149, _T_150) @[exu_div_ctl.scala 522:41]
node _T_152 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 522:76]
node _T_153 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 522:95]
node _T_154 = eq(_T_153, UInt<1>("h00")) @[exu_div_ctl.scala 522:82]
node _T_155 = bits(quotient_raw, 1, 1) @[exu_div_ctl.scala 522:113]
node _T_156 = and(_T_154, _T_155) @[exu_div_ctl.scala 522:99]
node _T_157 = or(_T_152, _T_156) @[exu_div_ctl.scala 522:80]
node _T_158 = cat(_T_151, _T_157) @[Cat.scala 29:58]
quotient_new <= _T_158 @[exu_div_ctl.scala 522:16]
node _T_159 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 525:48]
node _T_160 = mux(twos_comp_q_sel, q_ff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_161 = mux(twos_comp_b_sel, _T_159, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_162 = or(_T_160, _T_161) @[Mux.scala 27:72]
2 bit divider
2021-01-06 12:32:46 +08:00
wire twos_comp_in : UInt<32> @[Mux.scala 27:72]
small numcase corrected
2021-01-06 13:22:58 +08:00
twos_comp_in <= _T_162 @[Mux.scala 27:72]
wire _T_163 : UInt<1>[31] @[lib.scala 426:20]
node _T_164 = bits(twos_comp_in, 0, 0) @[lib.scala 428:27]
node _T_165 = orr(_T_164) @[lib.scala 428:35]
node _T_166 = bits(twos_comp_in, 1, 1) @[lib.scala 428:44]
node _T_167 = not(_T_166) @[lib.scala 428:40]
node _T_168 = bits(twos_comp_in, 1, 1) @[lib.scala 428:51]
node _T_169 = mux(_T_165, _T_167, _T_168) @[lib.scala 428:23]
_T_163[0] <= _T_169 @[lib.scala 428:17]
node _T_170 = bits(twos_comp_in, 1, 0) @[lib.scala 428:27]
node _T_171 = orr(_T_170) @[lib.scala 428:35]
node _T_172 = bits(twos_comp_in, 2, 2) @[lib.scala 428:44]
node _T_173 = not(_T_172) @[lib.scala 428:40]
node _T_174 = bits(twos_comp_in, 2, 2) @[lib.scala 428:51]
node _T_175 = mux(_T_171, _T_173, _T_174) @[lib.scala 428:23]
_T_163[1] <= _T_175 @[lib.scala 428:17]
node _T_176 = bits(twos_comp_in, 2, 0) @[lib.scala 428:27]
node _T_177 = orr(_T_176) @[lib.scala 428:35]
node _T_178 = bits(twos_comp_in, 3, 3) @[lib.scala 428:44]
node _T_179 = not(_T_178) @[lib.scala 428:40]
node _T_180 = bits(twos_comp_in, 3, 3) @[lib.scala 428:51]
node _T_181 = mux(_T_177, _T_179, _T_180) @[lib.scala 428:23]
_T_163[2] <= _T_181 @[lib.scala 428:17]
node _T_182 = bits(twos_comp_in, 3, 0) @[lib.scala 428:27]
node _T_183 = orr(_T_182) @[lib.scala 428:35]
node _T_184 = bits(twos_comp_in, 4, 4) @[lib.scala 428:44]
node _T_185 = not(_T_184) @[lib.scala 428:40]
node _T_186 = bits(twos_comp_in, 4, 4) @[lib.scala 428:51]
node _T_187 = mux(_T_183, _T_185, _T_186) @[lib.scala 428:23]
_T_163[3] <= _T_187 @[lib.scala 428:17]
node _T_188 = bits(twos_comp_in, 4, 0) @[lib.scala 428:27]
node _T_189 = orr(_T_188) @[lib.scala 428:35]
node _T_190 = bits(twos_comp_in, 5, 5) @[lib.scala 428:44]
node _T_191 = not(_T_190) @[lib.scala 428:40]
node _T_192 = bits(twos_comp_in, 5, 5) @[lib.scala 428:51]
node _T_193 = mux(_T_189, _T_191, _T_192) @[lib.scala 428:23]
_T_163[4] <= _T_193 @[lib.scala 428:17]
node _T_194 = bits(twos_comp_in, 5, 0) @[lib.scala 428:27]
node _T_195 = orr(_T_194) @[lib.scala 428:35]
node _T_196 = bits(twos_comp_in, 6, 6) @[lib.scala 428:44]
node _T_197 = not(_T_196) @[lib.scala 428:40]
node _T_198 = bits(twos_comp_in, 6, 6) @[lib.scala 428:51]
node _T_199 = mux(_T_195, _T_197, _T_198) @[lib.scala 428:23]
_T_163[5] <= _T_199 @[lib.scala 428:17]
node _T_200 = bits(twos_comp_in, 6, 0) @[lib.scala 428:27]
node _T_201 = orr(_T_200) @[lib.scala 428:35]
node _T_202 = bits(twos_comp_in, 7, 7) @[lib.scala 428:44]
node _T_203 = not(_T_202) @[lib.scala 428:40]
node _T_204 = bits(twos_comp_in, 7, 7) @[lib.scala 428:51]
node _T_205 = mux(_T_201, _T_203, _T_204) @[lib.scala 428:23]
_T_163[6] <= _T_205 @[lib.scala 428:17]
node _T_206 = bits(twos_comp_in, 7, 0) @[lib.scala 428:27]
node _T_207 = orr(_T_206) @[lib.scala 428:35]
node _T_208 = bits(twos_comp_in, 8, 8) @[lib.scala 428:44]
node _T_209 = not(_T_208) @[lib.scala 428:40]
node _T_210 = bits(twos_comp_in, 8, 8) @[lib.scala 428:51]
node _T_211 = mux(_T_207, _T_209, _T_210) @[lib.scala 428:23]
_T_163[7] <= _T_211 @[lib.scala 428:17]
node _T_212 = bits(twos_comp_in, 8, 0) @[lib.scala 428:27]
node _T_213 = orr(_T_212) @[lib.scala 428:35]
node _T_214 = bits(twos_comp_in, 9, 9) @[lib.scala 428:44]
node _T_215 = not(_T_214) @[lib.scala 428:40]
node _T_216 = bits(twos_comp_in, 9, 9) @[lib.scala 428:51]
node _T_217 = mux(_T_213, _T_215, _T_216) @[lib.scala 428:23]
_T_163[8] <= _T_217 @[lib.scala 428:17]
node _T_218 = bits(twos_comp_in, 9, 0) @[lib.scala 428:27]
node _T_219 = orr(_T_218) @[lib.scala 428:35]
node _T_220 = bits(twos_comp_in, 10, 10) @[lib.scala 428:44]
node _T_221 = not(_T_220) @[lib.scala 428:40]
node _T_222 = bits(twos_comp_in, 10, 10) @[lib.scala 428:51]
node _T_223 = mux(_T_219, _T_221, _T_222) @[lib.scala 428:23]
_T_163[9] <= _T_223 @[lib.scala 428:17]
node _T_224 = bits(twos_comp_in, 10, 0) @[lib.scala 428:27]
node _T_225 = orr(_T_224) @[lib.scala 428:35]
node _T_226 = bits(twos_comp_in, 11, 11) @[lib.scala 428:44]
node _T_227 = not(_T_226) @[lib.scala 428:40]
node _T_228 = bits(twos_comp_in, 11, 11) @[lib.scala 428:51]
node _T_229 = mux(_T_225, _T_227, _T_228) @[lib.scala 428:23]
_T_163[10] <= _T_229 @[lib.scala 428:17]
node _T_230 = bits(twos_comp_in, 11, 0) @[lib.scala 428:27]
node _T_231 = orr(_T_230) @[lib.scala 428:35]
node _T_232 = bits(twos_comp_in, 12, 12) @[lib.scala 428:44]
node _T_233 = not(_T_232) @[lib.scala 428:40]
node _T_234 = bits(twos_comp_in, 12, 12) @[lib.scala 428:51]
node _T_235 = mux(_T_231, _T_233, _T_234) @[lib.scala 428:23]
_T_163[11] <= _T_235 @[lib.scala 428:17]
node _T_236 = bits(twos_comp_in, 12, 0) @[lib.scala 428:27]
node _T_237 = orr(_T_236) @[lib.scala 428:35]
node _T_238 = bits(twos_comp_in, 13, 13) @[lib.scala 428:44]
node _T_239 = not(_T_238) @[lib.scala 428:40]
node _T_240 = bits(twos_comp_in, 13, 13) @[lib.scala 428:51]
node _T_241 = mux(_T_237, _T_239, _T_240) @[lib.scala 428:23]
_T_163[12] <= _T_241 @[lib.scala 428:17]
node _T_242 = bits(twos_comp_in, 13, 0) @[lib.scala 428:27]
node _T_243 = orr(_T_242) @[lib.scala 428:35]
node _T_244 = bits(twos_comp_in, 14, 14) @[lib.scala 428:44]
node _T_245 = not(_T_244) @[lib.scala 428:40]
node _T_246 = bits(twos_comp_in, 14, 14) @[lib.scala 428:51]
node _T_247 = mux(_T_243, _T_245, _T_246) @[lib.scala 428:23]
_T_163[13] <= _T_247 @[lib.scala 428:17]
node _T_248 = bits(twos_comp_in, 14, 0) @[lib.scala 428:27]
node _T_249 = orr(_T_248) @[lib.scala 428:35]
node _T_250 = bits(twos_comp_in, 15, 15) @[lib.scala 428:44]
node _T_251 = not(_T_250) @[lib.scala 428:40]
node _T_252 = bits(twos_comp_in, 15, 15) @[lib.scala 428:51]
node _T_253 = mux(_T_249, _T_251, _T_252) @[lib.scala 428:23]
_T_163[14] <= _T_253 @[lib.scala 428:17]
node _T_254 = bits(twos_comp_in, 15, 0) @[lib.scala 428:27]
node _T_255 = orr(_T_254) @[lib.scala 428:35]
node _T_256 = bits(twos_comp_in, 16, 16) @[lib.scala 428:44]
node _T_257 = not(_T_256) @[lib.scala 428:40]
node _T_258 = bits(twos_comp_in, 16, 16) @[lib.scala 428:51]
node _T_259 = mux(_T_255, _T_257, _T_258) @[lib.scala 428:23]
_T_163[15] <= _T_259 @[lib.scala 428:17]
node _T_260 = bits(twos_comp_in, 16, 0) @[lib.scala 428:27]
node _T_261 = orr(_T_260) @[lib.scala 428:35]
node _T_262 = bits(twos_comp_in, 17, 17) @[lib.scala 428:44]
node _T_263 = not(_T_262) @[lib.scala 428:40]
node _T_264 = bits(twos_comp_in, 17, 17) @[lib.scala 428:51]
node _T_265 = mux(_T_261, _T_263, _T_264) @[lib.scala 428:23]
_T_163[16] <= _T_265 @[lib.scala 428:17]
node _T_266 = bits(twos_comp_in, 17, 0) @[lib.scala 428:27]
node _T_267 = orr(_T_266) @[lib.scala 428:35]
node _T_268 = bits(twos_comp_in, 18, 18) @[lib.scala 428:44]
node _T_269 = not(_T_268) @[lib.scala 428:40]
node _T_270 = bits(twos_comp_in, 18, 18) @[lib.scala 428:51]
node _T_271 = mux(_T_267, _T_269, _T_270) @[lib.scala 428:23]
_T_163[17] <= _T_271 @[lib.scala 428:17]
node _T_272 = bits(twos_comp_in, 18, 0) @[lib.scala 428:27]
node _T_273 = orr(_T_272) @[lib.scala 428:35]
node _T_274 = bits(twos_comp_in, 19, 19) @[lib.scala 428:44]
node _T_275 = not(_T_274) @[lib.scala 428:40]
node _T_276 = bits(twos_comp_in, 19, 19) @[lib.scala 428:51]
node _T_277 = mux(_T_273, _T_275, _T_276) @[lib.scala 428:23]
_T_163[18] <= _T_277 @[lib.scala 428:17]
node _T_278 = bits(twos_comp_in, 19, 0) @[lib.scala 428:27]
node _T_279 = orr(_T_278) @[lib.scala 428:35]
node _T_280 = bits(twos_comp_in, 20, 20) @[lib.scala 428:44]
node _T_281 = not(_T_280) @[lib.scala 428:40]
node _T_282 = bits(twos_comp_in, 20, 20) @[lib.scala 428:51]
node _T_283 = mux(_T_279, _T_281, _T_282) @[lib.scala 428:23]
_T_163[19] <= _T_283 @[lib.scala 428:17]
node _T_284 = bits(twos_comp_in, 20, 0) @[lib.scala 428:27]
node _T_285 = orr(_T_284) @[lib.scala 428:35]
node _T_286 = bits(twos_comp_in, 21, 21) @[lib.scala 428:44]
node _T_287 = not(_T_286) @[lib.scala 428:40]
node _T_288 = bits(twos_comp_in, 21, 21) @[lib.scala 428:51]
node _T_289 = mux(_T_285, _T_287, _T_288) @[lib.scala 428:23]
_T_163[20] <= _T_289 @[lib.scala 428:17]
node _T_290 = bits(twos_comp_in, 21, 0) @[lib.scala 428:27]
node _T_291 = orr(_T_290) @[lib.scala 428:35]
node _T_292 = bits(twos_comp_in, 22, 22) @[lib.scala 428:44]
node _T_293 = not(_T_292) @[lib.scala 428:40]
node _T_294 = bits(twos_comp_in, 22, 22) @[lib.scala 428:51]
node _T_295 = mux(_T_291, _T_293, _T_294) @[lib.scala 428:23]
_T_163[21] <= _T_295 @[lib.scala 428:17]
node _T_296 = bits(twos_comp_in, 22, 0) @[lib.scala 428:27]
node _T_297 = orr(_T_296) @[lib.scala 428:35]
node _T_298 = bits(twos_comp_in, 23, 23) @[lib.scala 428:44]
node _T_299 = not(_T_298) @[lib.scala 428:40]
node _T_300 = bits(twos_comp_in, 23, 23) @[lib.scala 428:51]
node _T_301 = mux(_T_297, _T_299, _T_300) @[lib.scala 428:23]
_T_163[22] <= _T_301 @[lib.scala 428:17]
node _T_302 = bits(twos_comp_in, 23, 0) @[lib.scala 428:27]
node _T_303 = orr(_T_302) @[lib.scala 428:35]
node _T_304 = bits(twos_comp_in, 24, 24) @[lib.scala 428:44]
node _T_305 = not(_T_304) @[lib.scala 428:40]
node _T_306 = bits(twos_comp_in, 24, 24) @[lib.scala 428:51]
node _T_307 = mux(_T_303, _T_305, _T_306) @[lib.scala 428:23]
_T_163[23] <= _T_307 @[lib.scala 428:17]
node _T_308 = bits(twos_comp_in, 24, 0) @[lib.scala 428:27]
node _T_309 = orr(_T_308) @[lib.scala 428:35]
node _T_310 = bits(twos_comp_in, 25, 25) @[lib.scala 428:44]
node _T_311 = not(_T_310) @[lib.scala 428:40]
node _T_312 = bits(twos_comp_in, 25, 25) @[lib.scala 428:51]
node _T_313 = mux(_T_309, _T_311, _T_312) @[lib.scala 428:23]
_T_163[24] <= _T_313 @[lib.scala 428:17]
node _T_314 = bits(twos_comp_in, 25, 0) @[lib.scala 428:27]
node _T_315 = orr(_T_314) @[lib.scala 428:35]
node _T_316 = bits(twos_comp_in, 26, 26) @[lib.scala 428:44]
node _T_317 = not(_T_316) @[lib.scala 428:40]
node _T_318 = bits(twos_comp_in, 26, 26) @[lib.scala 428:51]
node _T_319 = mux(_T_315, _T_317, _T_318) @[lib.scala 428:23]
_T_163[25] <= _T_319 @[lib.scala 428:17]
node _T_320 = bits(twos_comp_in, 26, 0) @[lib.scala 428:27]
node _T_321 = orr(_T_320) @[lib.scala 428:35]
node _T_322 = bits(twos_comp_in, 27, 27) @[lib.scala 428:44]
node _T_323 = not(_T_322) @[lib.scala 428:40]
node _T_324 = bits(twos_comp_in, 27, 27) @[lib.scala 428:51]
node _T_325 = mux(_T_321, _T_323, _T_324) @[lib.scala 428:23]
_T_163[26] <= _T_325 @[lib.scala 428:17]
node _T_326 = bits(twos_comp_in, 27, 0) @[lib.scala 428:27]
node _T_327 = orr(_T_326) @[lib.scala 428:35]
node _T_328 = bits(twos_comp_in, 28, 28) @[lib.scala 428:44]
node _T_329 = not(_T_328) @[lib.scala 428:40]
node _T_330 = bits(twos_comp_in, 28, 28) @[lib.scala 428:51]
node _T_331 = mux(_T_327, _T_329, _T_330) @[lib.scala 428:23]
_T_163[27] <= _T_331 @[lib.scala 428:17]
node _T_332 = bits(twos_comp_in, 28, 0) @[lib.scala 428:27]
node _T_333 = orr(_T_332) @[lib.scala 428:35]
node _T_334 = bits(twos_comp_in, 29, 29) @[lib.scala 428:44]
node _T_335 = not(_T_334) @[lib.scala 428:40]
node _T_336 = bits(twos_comp_in, 29, 29) @[lib.scala 428:51]
node _T_337 = mux(_T_333, _T_335, _T_336) @[lib.scala 428:23]
_T_163[28] <= _T_337 @[lib.scala 428:17]
node _T_338 = bits(twos_comp_in, 29, 0) @[lib.scala 428:27]
node _T_339 = orr(_T_338) @[lib.scala 428:35]
node _T_340 = bits(twos_comp_in, 30, 30) @[lib.scala 428:44]
node _T_341 = not(_T_340) @[lib.scala 428:40]
node _T_342 = bits(twos_comp_in, 30, 30) @[lib.scala 428:51]
node _T_343 = mux(_T_339, _T_341, _T_342) @[lib.scala 428:23]
_T_163[29] <= _T_343 @[lib.scala 428:17]
node _T_344 = bits(twos_comp_in, 30, 0) @[lib.scala 428:27]
node _T_345 = orr(_T_344) @[lib.scala 428:35]
node _T_346 = bits(twos_comp_in, 31, 31) @[lib.scala 428:44]
node _T_347 = not(_T_346) @[lib.scala 428:40]
node _T_348 = bits(twos_comp_in, 31, 31) @[lib.scala 428:51]
node _T_349 = mux(_T_345, _T_347, _T_348) @[lib.scala 428:23]
_T_163[30] <= _T_349 @[lib.scala 428:17]
node _T_350 = cat(_T_163[2], _T_163[1]) @[lib.scala 430:14]
node _T_351 = cat(_T_350, _T_163[0]) @[lib.scala 430:14]
node _T_352 = cat(_T_163[4], _T_163[3]) @[lib.scala 430:14]
node _T_353 = cat(_T_163[6], _T_163[5]) @[lib.scala 430:14]
node _T_354 = cat(_T_353, _T_352) @[lib.scala 430:14]
node _T_355 = cat(_T_354, _T_351) @[lib.scala 430:14]
node _T_356 = cat(_T_163[8], _T_163[7]) @[lib.scala 430:14]
node _T_357 = cat(_T_163[10], _T_163[9]) @[lib.scala 430:14]
node _T_358 = cat(_T_357, _T_356) @[lib.scala 430:14]
node _T_359 = cat(_T_163[12], _T_163[11]) @[lib.scala 430:14]
node _T_360 = cat(_T_163[14], _T_163[13]) @[lib.scala 430:14]
node _T_361 = cat(_T_360, _T_359) @[lib.scala 430:14]
node _T_362 = cat(_T_361, _T_358) @[lib.scala 430:14]
node _T_363 = cat(_T_362, _T_355) @[lib.scala 430:14]
node _T_364 = cat(_T_163[16], _T_163[15]) @[lib.scala 430:14]
node _T_365 = cat(_T_163[18], _T_163[17]) @[lib.scala 430:14]
node _T_366 = cat(_T_365, _T_364) @[lib.scala 430:14]
node _T_367 = cat(_T_163[20], _T_163[19]) @[lib.scala 430:14]
node _T_368 = cat(_T_163[22], _T_163[21]) @[lib.scala 430:14]
node _T_369 = cat(_T_368, _T_367) @[lib.scala 430:14]
node _T_370 = cat(_T_369, _T_366) @[lib.scala 430:14]
node _T_371 = cat(_T_163[24], _T_163[23]) @[lib.scala 430:14]
node _T_372 = cat(_T_163[26], _T_163[25]) @[lib.scala 430:14]
node _T_373 = cat(_T_372, _T_371) @[lib.scala 430:14]
node _T_374 = cat(_T_163[28], _T_163[27]) @[lib.scala 430:14]
node _T_375 = cat(_T_163[30], _T_163[29]) @[lib.scala 430:14]
node _T_376 = cat(_T_375, _T_374) @[lib.scala 430:14]
node _T_377 = cat(_T_376, _T_373) @[lib.scala 430:14]
node _T_378 = cat(_T_377, _T_370) @[lib.scala 430:14]
node _T_379 = cat(_T_378, _T_363) @[lib.scala 430:14]
node _T_380 = bits(twos_comp_in, 0, 0) @[lib.scala 430:24]
node twos_comp_out = cat(_T_379, _T_380) @[Cat.scala 29:58]
node _T_381 = eq(a_shift, UInt<1>("h00")) @[exu_div_ctl.scala 530:6]
node _T_382 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 530:17]
node _T_383 = and(_T_381, _T_382) @[exu_div_ctl.scala 530:15]
node _T_384 = bits(_T_383, 0, 0) @[exu_div_ctl.scala 530:36]
node _T_385 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 531:52]
node _T_386 = cat(_T_385, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_387 = bits(ar_shifted, 31, 0) @[exu_div_ctl.scala 532:54]
node _T_388 = mux(_T_384, io.dividend_in, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_389 = mux(a_shift, _T_386, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_390 = mux(shortq_enable_ff, _T_387, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_391 = or(_T_388, _T_389) @[Mux.scala 27:72]
node _T_392 = or(_T_391, _T_390) @[Mux.scala 27:72]
2 bit divider
2021-01-06 12:32:46 +08:00
wire a_in : UInt<32> @[Mux.scala 27:72]
small numcase corrected
2021-01-06 13:22:58 +08:00
a_in <= _T_392 @[Mux.scala 27:72]
node _T_393 = eq(b_twos_comp, UInt<1>("h00")) @[exu_div_ctl.scala 536:5]
node _T_394 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 536:78]
node _T_395 = and(io.signed_in, _T_394) @[exu_div_ctl.scala 536:63]
node _T_396 = bits(io.divisor_in, 31, 0) @[exu_div_ctl.scala 536:96]
node _T_397 = cat(_T_395, _T_396) @[Cat.scala 29:58]
node _T_398 = eq(divisor_sign_ff, UInt<1>("h00")) @[exu_div_ctl.scala 537:49]
node _T_399 = bits(twos_comp_out, 31, 0) @[exu_div_ctl.scala 537:79]
node _T_400 = cat(_T_398, _T_399) @[Cat.scala 29:58]
node _T_401 = mux(_T_393, _T_397, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_402 = mux(b_twos_comp, _T_400, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_403 = or(_T_401, _T_402) @[Mux.scala 27:72]
2 bit divider
2021-01-06 12:32:46 +08:00
wire b_in : UInt<33> @[Mux.scala 27:72]
small numcase corrected
2021-01-06 13:22:58 +08:00
b_in <= _T_403 @[Mux.scala 27:72]
node _T_404 = bits(r_ff, 29, 0) @[exu_div_ctl.scala 541:54]
node _T_405 = bits(a_ff, 31, 30) @[exu_div_ctl.scala 541:65]
node _T_406 = cat(_T_404, _T_405) @[Cat.scala 29:58]
node _T_407 = bits(adder1_out, 31, 0) @[exu_div_ctl.scala 542:57]
node _T_408 = bits(adder2_out, 31, 0) @[exu_div_ctl.scala 543:57]
node _T_409 = bits(adder3_out, 31, 0) @[exu_div_ctl.scala 544:57]
node _T_410 = bits(ar_shifted, 63, 32) @[exu_div_ctl.scala 545:56]
node _T_411 = mux(r_sign_sel, UInt<32>("h0ffffffff"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_412 = mux(r_restore_sel, _T_406, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_413 = mux(r_adder1_sel, _T_407, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_414 = mux(r_adder2_sel, _T_408, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_415 = mux(r_adder3_sel, _T_409, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_416 = mux(shortq_enable_ff, _T_410, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_417 = mux(by_zero_case, a_ff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_418 = or(_T_411, _T_412) @[Mux.scala 27:72]
node _T_419 = or(_T_418, _T_413) @[Mux.scala 27:72]
node _T_420 = or(_T_419, _T_414) @[Mux.scala 27:72]
node _T_421 = or(_T_420, _T_415) @[Mux.scala 27:72]
node _T_422 = or(_T_421, _T_416) @[Mux.scala 27:72]
node _T_423 = or(_T_422, _T_417) @[Mux.scala 27:72]
2 bit divider
2021-01-06 12:32:46 +08:00
wire r_in : UInt<32> @[Mux.scala 27:72]
small numcase corrected
2021-01-06 13:22:58 +08:00
r_in <= _T_423 @[Mux.scala 27:72]
node _T_424 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 549:5]
node _T_425 = bits(q_ff, 29, 0) @[exu_div_ctl.scala 549:55]
node _T_426 = cat(_T_425, quotient_new) @[Cat.scala 29:58]
node _T_427 = cat(UInt<28>("h00"), smallnum) @[Cat.scala 29:58]
node _T_428 = mux(UInt<1>("h01"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_429 = mux(_T_424, _T_426, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_430 = mux(smallnum_case, _T_427, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_431 = mux(by_zero_case, _T_428, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_432 = or(_T_429, _T_430) @[Mux.scala 27:72]
node _T_433 = or(_T_432, _T_431) @[Mux.scala 27:72]
2 bit divider
2021-01-06 12:32:46 +08:00
wire q_in : UInt<32> @[Mux.scala 27:72]
small numcase corrected
2021-01-06 13:22:58 +08:00
q_in <= _T_433 @[Mux.scala 27:72]
node _T_434 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 553:31]
node _T_435 = and(finish_ff, _T_434) @[exu_div_ctl.scala 553:29]
io.valid_out <= _T_435 @[exu_div_ctl.scala 553:16]
node _T_436 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 555:6]
node _T_437 = eq(twos_comp_q_sel, UInt<1>("h00")) @[exu_div_ctl.scala 555:16]
node _T_438 = and(_T_436, _T_437) @[exu_div_ctl.scala 555:14]
node _T_439 = bits(_T_438, 0, 0) @[exu_div_ctl.scala 555:40]
node _T_440 = mux(_T_439, q_ff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_441 = mux(rem_ff, r_ff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_442 = mux(twos_comp_q_sel, twos_comp_out, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_443 = or(_T_440, _T_441) @[Mux.scala 27:72]
node _T_444 = or(_T_443, _T_442) @[Mux.scala 27:72]
wire _T_445 : UInt<32> @[Mux.scala 27:72]
_T_445 <= _T_444 @[Mux.scala 27:72]
io.data_out <= _T_445 @[exu_div_ctl.scala 554:15]
node _T_446 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_447 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_448 = eq(_T_447, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_449 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_450 = eq(_T_449, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_451 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_452 = eq(_T_451, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_453 = and(_T_448, _T_450) @[exu_div_ctl.scala 561:95]
node _T_454 = and(_T_453, _T_452) @[exu_div_ctl.scala 561:95]
node _T_455 = and(_T_446, _T_454) @[exu_div_ctl.scala 562:11]
node _T_456 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_457 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_458 = eq(_T_457, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_459 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_460 = eq(_T_459, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_461 = and(_T_458, _T_460) @[exu_div_ctl.scala 561:95]
node _T_462 = and(_T_456, _T_461) @[exu_div_ctl.scala 562:11]
node _T_463 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 567:38]
node _T_464 = eq(_T_463, UInt<1>("h00")) @[exu_div_ctl.scala 567:33]
node _T_465 = and(_T_462, _T_464) @[exu_div_ctl.scala 567:31]
node _T_466 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_467 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_468 = eq(_T_467, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_469 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_470 = eq(_T_469, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_471 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_472 = eq(_T_471, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_473 = and(_T_468, _T_470) @[exu_div_ctl.scala 561:95]
node _T_474 = and(_T_473, _T_472) @[exu_div_ctl.scala 561:95]
node _T_475 = and(_T_466, _T_474) @[exu_div_ctl.scala 562:11]
node _T_476 = or(_T_465, _T_475) @[exu_div_ctl.scala 567:42]
node _T_477 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_478 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_479 = and(_T_477, _T_478) @[exu_div_ctl.scala 560:95]
node _T_480 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_481 = eq(_T_480, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_482 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_483 = eq(_T_482, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_484 = and(_T_481, _T_483) @[exu_div_ctl.scala 561:95]
node _T_485 = and(_T_479, _T_484) @[exu_div_ctl.scala 562:11]
node _T_486 = or(_T_476, _T_485) @[exu_div_ctl.scala 567:75]
node _T_487 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_488 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_489 = eq(_T_488, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_490 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_491 = eq(_T_490, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_492 = and(_T_489, _T_491) @[exu_div_ctl.scala 561:95]
node _T_493 = and(_T_487, _T_492) @[exu_div_ctl.scala 562:11]
node _T_494 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 569:38]
node _T_495 = eq(_T_494, UInt<1>("h00")) @[exu_div_ctl.scala 569:33]
node _T_496 = and(_T_493, _T_495) @[exu_div_ctl.scala 569:31]
node _T_497 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_498 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_499 = eq(_T_498, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_500 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_501 = eq(_T_500, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_502 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_503 = eq(_T_502, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_504 = and(_T_499, _T_501) @[exu_div_ctl.scala 561:95]
node _T_505 = and(_T_504, _T_503) @[exu_div_ctl.scala 561:95]
node _T_506 = and(_T_497, _T_505) @[exu_div_ctl.scala 562:11]
node _T_507 = or(_T_496, _T_506) @[exu_div_ctl.scala 569:42]
node _T_508 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_509 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_510 = eq(_T_509, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_511 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_512 = eq(_T_511, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_513 = and(_T_510, _T_512) @[exu_div_ctl.scala 561:95]
node _T_514 = and(_T_508, _T_513) @[exu_div_ctl.scala 562:11]
node _T_515 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 569:113]
node _T_516 = eq(_T_515, UInt<1>("h00")) @[exu_div_ctl.scala 569:108]
node _T_517 = and(_T_514, _T_516) @[exu_div_ctl.scala 569:106]
node _T_518 = or(_T_507, _T_517) @[exu_div_ctl.scala 569:78]
node _T_519 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_520 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_521 = eq(_T_520, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_522 = and(_T_519, _T_521) @[exu_div_ctl.scala 560:95]
node _T_523 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_524 = eq(_T_523, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_525 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_526 = eq(_T_525, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_527 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_528 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 561:58]
node _T_529 = and(_T_524, _T_526) @[exu_div_ctl.scala 561:95]
node _T_530 = and(_T_529, _T_527) @[exu_div_ctl.scala 561:95]
node _T_531 = and(_T_530, _T_528) @[exu_div_ctl.scala 561:95]
node _T_532 = and(_T_522, _T_531) @[exu_div_ctl.scala 562:11]
node _T_533 = or(_T_518, _T_532) @[exu_div_ctl.scala 569:117]
node _T_534 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
node _T_535 = eq(_T_534, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_536 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_537 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_538 = and(_T_535, _T_536) @[exu_div_ctl.scala 560:95]
node _T_539 = and(_T_538, _T_537) @[exu_div_ctl.scala 560:95]
node _T_540 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_541 = eq(_T_540, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_542 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_543 = eq(_T_542, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_544 = and(_T_541, _T_543) @[exu_div_ctl.scala 561:95]
node _T_545 = and(_T_539, _T_544) @[exu_div_ctl.scala 562:11]
node _T_546 = or(_T_533, _T_545) @[exu_div_ctl.scala 570:44]
node _T_547 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_548 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_549 = and(_T_547, _T_548) @[exu_div_ctl.scala 560:95]
node _T_550 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_551 = eq(_T_550, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_552 = and(_T_549, _T_551) @[exu_div_ctl.scala 562:11]
node _T_553 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 570:114]
node _T_554 = eq(_T_553, UInt<1>("h00")) @[exu_div_ctl.scala 570:109]
node _T_555 = and(_T_552, _T_554) @[exu_div_ctl.scala 570:107]
node _T_556 = or(_T_546, _T_555) @[exu_div_ctl.scala 570:80]
node _T_557 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_558 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_559 = and(_T_557, _T_558) @[exu_div_ctl.scala 560:95]
node _T_560 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_561 = eq(_T_560, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_562 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_563 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_564 = eq(_T_563, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_565 = and(_T_561, _T_562) @[exu_div_ctl.scala 561:95]
node _T_566 = and(_T_565, _T_564) @[exu_div_ctl.scala 561:95]
node _T_567 = and(_T_559, _T_566) @[exu_div_ctl.scala 562:11]
node _T_568 = or(_T_556, _T_567) @[exu_div_ctl.scala 570:119]
node _T_569 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_570 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_571 = and(_T_569, _T_570) @[exu_div_ctl.scala 560:95]
node _T_572 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_573 = eq(_T_572, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_574 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_575 = eq(_T_574, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_576 = and(_T_573, _T_575) @[exu_div_ctl.scala 561:95]
node _T_577 = and(_T_571, _T_576) @[exu_div_ctl.scala 562:11]
node _T_578 = or(_T_568, _T_577) @[exu_div_ctl.scala 571:44]
node _T_579 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_580 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_581 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_582 = and(_T_579, _T_580) @[exu_div_ctl.scala 560:95]
node _T_583 = and(_T_582, _T_581) @[exu_div_ctl.scala 560:95]
node _T_584 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_585 = eq(_T_584, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_586 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_587 = and(_T_585, _T_586) @[exu_div_ctl.scala 561:95]
node _T_588 = and(_T_583, _T_587) @[exu_div_ctl.scala 562:11]
node _T_589 = or(_T_578, _T_588) @[exu_div_ctl.scala 571:79]
node _T_590 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_591 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_592 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_593 = and(_T_590, _T_591) @[exu_div_ctl.scala 560:95]
node _T_594 = and(_T_593, _T_592) @[exu_div_ctl.scala 560:95]
node _T_595 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_596 = eq(_T_595, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_597 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_598 = eq(_T_597, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_599 = and(_T_596, _T_598) @[exu_div_ctl.scala 561:95]
node _T_600 = and(_T_594, _T_599) @[exu_div_ctl.scala 562:11]
node _T_601 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_602 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
node _T_603 = eq(_T_602, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_604 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_605 = and(_T_601, _T_603) @[exu_div_ctl.scala 560:95]
node _T_606 = and(_T_605, _T_604) @[exu_div_ctl.scala 560:95]
node _T_607 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_608 = eq(_T_607, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_609 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_610 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 561:58]
node _T_611 = and(_T_608, _T_609) @[exu_div_ctl.scala 561:95]
node _T_612 = and(_T_611, _T_610) @[exu_div_ctl.scala 561:95]
node _T_613 = and(_T_606, _T_612) @[exu_div_ctl.scala 562:11]
node _T_614 = or(_T_600, _T_613) @[exu_div_ctl.scala 573:45]
node _T_615 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_616 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_617 = eq(_T_616, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_618 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_619 = eq(_T_618, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_620 = and(_T_617, _T_619) @[exu_div_ctl.scala 561:95]
node _T_621 = and(_T_615, _T_620) @[exu_div_ctl.scala 562:11]
node _T_622 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 573:121]
node _T_623 = eq(_T_622, UInt<1>("h00")) @[exu_div_ctl.scala 573:116]
node _T_624 = and(_T_621, _T_623) @[exu_div_ctl.scala 573:114]
node _T_625 = or(_T_614, _T_624) @[exu_div_ctl.scala 573:86]
node _T_626 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_627 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_628 = eq(_T_627, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_629 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_630 = eq(_T_629, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_631 = and(_T_628, _T_630) @[exu_div_ctl.scala 561:95]
node _T_632 = and(_T_626, _T_631) @[exu_div_ctl.scala 562:11]
node _T_633 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 574:40]
node _T_634 = eq(_T_633, UInt<1>("h00")) @[exu_div_ctl.scala 574:35]
node _T_635 = and(_T_632, _T_634) @[exu_div_ctl.scala 574:33]
node _T_636 = or(_T_625, _T_635) @[exu_div_ctl.scala 573:129]
node _T_637 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_638 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_639 = eq(_T_638, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_640 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_641 = eq(_T_640, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_642 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_643 = eq(_T_642, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_644 = and(_T_639, _T_641) @[exu_div_ctl.scala 561:95]
node _T_645 = and(_T_644, _T_643) @[exu_div_ctl.scala 561:95]
node _T_646 = and(_T_637, _T_645) @[exu_div_ctl.scala 562:11]
node _T_647 = or(_T_636, _T_646) @[exu_div_ctl.scala 574:47]
node _T_648 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
node _T_649 = eq(_T_648, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_650 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_651 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:75]
node _T_652 = eq(_T_651, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_653 = and(_T_649, _T_650) @[exu_div_ctl.scala 560:95]
node _T_654 = and(_T_653, _T_652) @[exu_div_ctl.scala 560:95]
node _T_655 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_656 = eq(_T_655, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_657 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_658 = eq(_T_657, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_659 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_660 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 561:58]
node _T_661 = and(_T_656, _T_658) @[exu_div_ctl.scala 561:95]
node _T_662 = and(_T_661, _T_659) @[exu_div_ctl.scala 561:95]
node _T_663 = and(_T_662, _T_660) @[exu_div_ctl.scala 561:95]
node _T_664 = and(_T_654, _T_663) @[exu_div_ctl.scala 562:11]
node _T_665 = or(_T_647, _T_664) @[exu_div_ctl.scala 574:88]
node _T_666 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
node _T_667 = eq(_T_666, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_668 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_669 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_670 = and(_T_667, _T_668) @[exu_div_ctl.scala 560:95]
node _T_671 = and(_T_670, _T_669) @[exu_div_ctl.scala 560:95]
node _T_672 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_673 = eq(_T_672, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_674 = and(_T_671, _T_673) @[exu_div_ctl.scala 562:11]
node _T_675 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 575:43]
node _T_676 = eq(_T_675, UInt<1>("h00")) @[exu_div_ctl.scala 575:38]
node _T_677 = and(_T_674, _T_676) @[exu_div_ctl.scala 575:36]
node _T_678 = or(_T_665, _T_677) @[exu_div_ctl.scala 574:131]
node _T_679 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_680 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_681 = eq(_T_680, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_682 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_683 = eq(_T_682, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_684 = and(_T_681, _T_683) @[exu_div_ctl.scala 561:95]
node _T_685 = and(_T_679, _T_684) @[exu_div_ctl.scala 562:11]
node _T_686 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 575:83]
node _T_687 = eq(_T_686, UInt<1>("h00")) @[exu_div_ctl.scala 575:78]
node _T_688 = and(_T_685, _T_687) @[exu_div_ctl.scala 575:76]
node _T_689 = or(_T_678, _T_688) @[exu_div_ctl.scala 575:47]
node _T_690 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_691 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
node _T_692 = eq(_T_691, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_693 = and(_T_690, _T_692) @[exu_div_ctl.scala 560:95]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_694 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_695 = eq(_T_694, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_696 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_697 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_698 = and(_T_695, _T_696) @[exu_div_ctl.scala 561:95]
node _T_699 = and(_T_698, _T_697) @[exu_div_ctl.scala 561:95]
node _T_700 = and(_T_693, _T_699) @[exu_div_ctl.scala 562:11]
node _T_701 = or(_T_689, _T_700) @[exu_div_ctl.scala 575:88]
node _T_702 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
node _T_703 = eq(_T_702, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_704 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_705 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_706 = and(_T_703, _T_704) @[exu_div_ctl.scala 560:95]
node _T_707 = and(_T_706, _T_705) @[exu_div_ctl.scala 560:95]
node _T_708 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_709 = eq(_T_708, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_710 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_711 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_712 = eq(_T_711, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_713 = and(_T_709, _T_710) @[exu_div_ctl.scala 561:95]
node _T_714 = and(_T_713, _T_712) @[exu_div_ctl.scala 561:95]
node _T_715 = and(_T_707, _T_714) @[exu_div_ctl.scala 562:11]
node _T_716 = or(_T_701, _T_715) @[exu_div_ctl.scala 575:131]
node _T_717 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_718 = eq(_T_717, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_719 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_720 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_721 = and(_T_718, _T_719) @[exu_div_ctl.scala 560:95]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_722 = and(_T_721, _T_720) @[exu_div_ctl.scala 560:95]
node _T_723 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_724 = eq(_T_723, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_725 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_726 = eq(_T_725, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_727 = and(_T_724, _T_726) @[exu_div_ctl.scala 561:95]
node _T_728 = and(_T_722, _T_727) @[exu_div_ctl.scala 562:11]
node _T_729 = or(_T_716, _T_728) @[exu_div_ctl.scala 576:47]
node _T_730 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_731 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
node _T_732 = eq(_T_731, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_733 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:75]
node _T_734 = eq(_T_733, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_735 = and(_T_730, _T_732) @[exu_div_ctl.scala 560:95]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_736 = and(_T_735, _T_734) @[exu_div_ctl.scala 560:95]
node _T_737 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_738 = eq(_T_737, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_739 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_740 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 561:58]
node _T_741 = and(_T_738, _T_739) @[exu_div_ctl.scala 561:95]
node _T_742 = and(_T_741, _T_740) @[exu_div_ctl.scala 561:95]
node _T_743 = and(_T_736, _T_742) @[exu_div_ctl.scala 562:11]
node _T_744 = or(_T_729, _T_743) @[exu_div_ctl.scala 576:88]
node _T_745 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
node _T_746 = eq(_T_745, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_747 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_748 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_749 = and(_T_746, _T_747) @[exu_div_ctl.scala 560:95]
node _T_750 = and(_T_749, _T_748) @[exu_div_ctl.scala 560:95]
node _T_751 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_752 = eq(_T_751, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_753 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_754 = eq(_T_753, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_755 = and(_T_752, _T_754) @[exu_div_ctl.scala 561:95]
node _T_756 = and(_T_750, _T_755) @[exu_div_ctl.scala 562:11]
node _T_757 = or(_T_744, _T_756) @[exu_div_ctl.scala 576:131]
node _T_758 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_759 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_760 = and(_T_758, _T_759) @[exu_div_ctl.scala 560:95]
node _T_761 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_762 = eq(_T_761, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_763 = and(_T_760, _T_762) @[exu_div_ctl.scala 562:11]
node _T_764 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 577:82]
node _T_765 = eq(_T_764, UInt<1>("h00")) @[exu_div_ctl.scala 577:77]
node _T_766 = and(_T_763, _T_765) @[exu_div_ctl.scala 577:75]
node _T_767 = or(_T_757, _T_766) @[exu_div_ctl.scala 577:47]
node _T_768 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:75]
node _T_769 = eq(_T_768, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_770 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_771 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_772 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_773 = and(_T_769, _T_770) @[exu_div_ctl.scala 560:95]
node _T_774 = and(_T_773, _T_771) @[exu_div_ctl.scala 560:95]
node _T_775 = and(_T_774, _T_772) @[exu_div_ctl.scala 560:95]
node _T_776 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_777 = eq(_T_776, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_778 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_779 = and(_T_777, _T_778) @[exu_div_ctl.scala 561:95]
node _T_780 = and(_T_775, _T_779) @[exu_div_ctl.scala 562:11]
node _T_781 = or(_T_767, _T_780) @[exu_div_ctl.scala 577:88]
node _T_782 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_783 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_784 = and(_T_782, _T_783) @[exu_div_ctl.scala 560:95]
node _T_785 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_786 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_787 = eq(_T_786, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_788 = and(_T_785, _T_787) @[exu_div_ctl.scala 561:95]
node _T_789 = and(_T_784, _T_788) @[exu_div_ctl.scala 562:11]
node _T_790 = or(_T_781, _T_789) @[exu_div_ctl.scala 577:131]
node _T_791 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_792 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_793 = and(_T_791, _T_792) @[exu_div_ctl.scala 560:95]
node _T_794 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_795 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_796 = eq(_T_795, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_797 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_798 = eq(_T_797, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_799 = and(_T_794, _T_796) @[exu_div_ctl.scala 561:95]
node _T_800 = and(_T_799, _T_798) @[exu_div_ctl.scala 561:95]
node _T_801 = and(_T_793, _T_800) @[exu_div_ctl.scala 562:11]
node _T_802 = or(_T_790, _T_801) @[exu_div_ctl.scala 578:47]
node _T_803 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_804 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_805 = and(_T_803, _T_804) @[exu_div_ctl.scala 560:95]
node _T_806 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_807 = eq(_T_806, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_808 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_809 = eq(_T_808, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_810 = and(_T_807, _T_809) @[exu_div_ctl.scala 561:95]
node _T_811 = and(_T_805, _T_810) @[exu_div_ctl.scala 562:11]
node _T_812 = or(_T_802, _T_811) @[exu_div_ctl.scala 578:88]
quotient new changed
2021-01-06 13:05:37 +08:00
node _T_813 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_814 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:75]
node _T_815 = eq(_T_814, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_816 = and(_T_813, _T_815) @[exu_div_ctl.scala 560:95]
node _T_817 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_818 = eq(_T_817, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_819 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:58]
node _T_820 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_821 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 561:58]
node _T_822 = and(_T_818, _T_819) @[exu_div_ctl.scala 561:95]
node _T_823 = and(_T_822, _T_820) @[exu_div_ctl.scala 561:95]
node _T_824 = and(_T_823, _T_821) @[exu_div_ctl.scala 561:95]
node _T_825 = and(_T_816, _T_824) @[exu_div_ctl.scala 562:11]
node _T_826 = or(_T_812, _T_825) @[exu_div_ctl.scala 578:131]
node _T_827 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_828 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_829 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_830 = and(_T_827, _T_828) @[exu_div_ctl.scala 560:95]
node _T_831 = and(_T_830, _T_829) @[exu_div_ctl.scala 560:95]
node _T_832 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_833 = and(_T_831, _T_832) @[exu_div_ctl.scala 562:11]
node _T_834 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 579:84]
node _T_835 = eq(_T_834, UInt<1>("h00")) @[exu_div_ctl.scala 579:79]
node _T_836 = and(_T_833, _T_835) @[exu_div_ctl.scala 579:77]
node _T_837 = or(_T_826, _T_836) @[exu_div_ctl.scala 579:47]
node _T_838 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_839 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_840 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_841 = and(_T_838, _T_839) @[exu_div_ctl.scala 560:95]
node _T_842 = and(_T_841, _T_840) @[exu_div_ctl.scala 560:95]
node _T_843 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_844 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_845 = eq(_T_844, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_846 = and(_T_843, _T_845) @[exu_div_ctl.scala 561:95]
node _T_847 = and(_T_842, _T_846) @[exu_div_ctl.scala 562:11]
node _T_848 = or(_T_837, _T_847) @[exu_div_ctl.scala 579:88]
node _T_849 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_850 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_851 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_852 = and(_T_849, _T_850) @[exu_div_ctl.scala 560:95]
node _T_853 = and(_T_852, _T_851) @[exu_div_ctl.scala 560:95]
node _T_854 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_855 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:75]
node _T_856 = eq(_T_855, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_857 = and(_T_854, _T_856) @[exu_div_ctl.scala 561:95]
node _T_858 = and(_T_853, _T_857) @[exu_div_ctl.scala 562:11]
node _T_859 = or(_T_848, _T_858) @[exu_div_ctl.scala 579:131]
node _T_860 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_861 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:75]
node _T_862 = eq(_T_861, UInt<1>("h00")) @[exu_div_ctl.scala 560:70]
node _T_863 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_864 = and(_T_860, _T_862) @[exu_div_ctl.scala 560:95]
node _T_865 = and(_T_864, _T_863) @[exu_div_ctl.scala 560:95]
node _T_866 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:75]
node _T_867 = eq(_T_866, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_868 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 561:58]
node _T_869 = and(_T_867, _T_868) @[exu_div_ctl.scala 561:95]
node _T_870 = and(_T_865, _T_869) @[exu_div_ctl.scala 562:11]
node _T_871 = or(_T_859, _T_870) @[exu_div_ctl.scala 580:47]
node _T_872 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_873 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_874 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_875 = and(_T_872, _T_873) @[exu_div_ctl.scala 560:95]
node _T_876 = and(_T_875, _T_874) @[exu_div_ctl.scala 560:95]
node _T_877 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_878 = eq(_T_877, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_879 = and(_T_876, _T_878) @[exu_div_ctl.scala 562:11]
node _T_880 = or(_T_871, _T_879) @[exu_div_ctl.scala 580:88]
node _T_881 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_882 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 560:58]
node _T_883 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_884 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 560:58]
node _T_885 = and(_T_881, _T_882) @[exu_div_ctl.scala 560:95]
node _T_886 = and(_T_885, _T_883) @[exu_div_ctl.scala 560:95]
node _T_887 = and(_T_886, _T_884) @[exu_div_ctl.scala 560:95]
node _T_888 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 561:58]
node _T_889 = and(_T_887, _T_888) @[exu_div_ctl.scala 562:11]
node _T_890 = or(_T_880, _T_889) @[exu_div_ctl.scala 580:131]
node _T_891 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 560:58]
node _T_892 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 560:58]
node _T_893 = and(_T_891, _T_892) @[exu_div_ctl.scala 560:95]
node _T_894 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 561:75]
node _T_895 = eq(_T_894, UInt<1>("h00")) @[exu_div_ctl.scala 561:70]
node _T_896 = and(_T_893, _T_895) @[exu_div_ctl.scala 562:11]
node _T_897 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 581:81]
node _T_898 = eq(_T_897, UInt<1>("h00")) @[exu_div_ctl.scala 581:76]
node _T_899 = and(_T_896, _T_898) @[exu_div_ctl.scala 581:74]
node _T_900 = or(_T_890, _T_899) @[exu_div_ctl.scala 581:47]
node _T_901 = cat(_T_589, _T_900) @[Cat.scala 29:58]
node _T_902 = cat(_T_455, _T_486) @[Cat.scala 29:58]
node _T_903 = cat(_T_902, _T_901) @[Cat.scala 29:58]
smallnum <= _T_903 @[exu_div_ctl.scala 564:12]
2 bit divider
2021-01-06 12:32:46 +08:00
node shortq_dividend = cat(dividend_sign_ff, a_ff) @[Cat.scala 29:58]
inst a_enc of exu_div_cls @[exu_div_ctl.scala 584:21]
a_enc.clock <= clock
a_enc.reset <= reset
a_enc.io.operand <= shortq_dividend @[exu_div_ctl.scala 585:20]
inst b_enc of exu_div_cls_1 @[exu_div_ctl.scala 587:21]
b_enc.clock <= clock
b_enc.reset <= reset
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_904 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 588:27]
b_enc.io.operand <= _T_904 @[exu_div_ctl.scala 588:20]
2 bit divider
2021-01-06 12:32:46 +08:00
node dw_a_enc = cat(UInt<1>("h00"), a_enc.io.cls) @[Cat.scala 29:58]
node dw_b_enc = cat(UInt<1>("h00"), b_enc.io.cls) @[Cat.scala 29:58]
small numcase corrected
2021-01-06 13:22:58 +08:00
node _T_905 = cat(UInt<1>("h00"), dw_b_enc) @[Cat.scala 29:58]
node _T_906 = cat(UInt<1>("h00"), dw_a_enc) @[Cat.scala 29:58]
node _T_907 = sub(_T_905, _T_906) @[exu_div_ctl.scala 592:41]
node _T_908 = tail(_T_907, 1) @[exu_div_ctl.scala 592:41]
node _T_909 = add(_T_908, UInt<7>("h01")) @[exu_div_ctl.scala 592:61]
node dw_shortq_raw = tail(_T_909, 1) @[exu_div_ctl.scala 592:61]
node _T_910 = bits(dw_shortq_raw, 6, 6) @[exu_div_ctl.scala 593:33]
node _T_911 = bits(_T_910, 0, 0) @[exu_div_ctl.scala 593:43]
node _T_912 = bits(dw_shortq_raw, 5, 0) @[exu_div_ctl.scala 593:63]
node shortq = mux(_T_911, UInt<1>("h00"), _T_912) @[exu_div_ctl.scala 593:19]
node _T_913 = bits(shortq, 5, 5) @[exu_div_ctl.scala 594:38]
node _T_914 = eq(_T_913, UInt<1>("h00")) @[exu_div_ctl.scala 594:31]
node _T_915 = and(valid_ff, _T_914) @[exu_div_ctl.scala 594:29]
node _T_916 = bits(shortq, 4, 1) @[exu_div_ctl.scala 594:52]
node _T_917 = eq(_T_916, UInt<4>("h0f")) @[exu_div_ctl.scala 594:58]
node _T_918 = eq(_T_917, UInt<1>("h00")) @[exu_div_ctl.scala 594:44]
node _T_919 = and(_T_915, _T_918) @[exu_div_ctl.scala 594:42]
node _T_920 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 594:76]
node _T_921 = and(_T_919, _T_920) @[exu_div_ctl.scala 594:74]
shortq_enable <= _T_921 @[exu_div_ctl.scala 594:17]
node _T_922 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 595:26]
node _T_923 = bits(shortq, 4, 0) @[exu_div_ctl.scala 595:65]
node _T_924 = sub(UInt<5>("h01f"), _T_923) @[exu_div_ctl.scala 595:57]
node _T_925 = tail(_T_924, 1) @[exu_div_ctl.scala 595:57]
node shortq_shift = mux(_T_922, UInt<1>("h00"), _T_925) @[exu_div_ctl.scala 595:25]
node _T_926 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 596:20]
node _T_927 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 596:30]
node _T_928 = cat(_T_926, _T_927) @[Cat.scala 29:58]
node _T_929 = cat(_T_928, b_ff1) @[Cat.scala 29:58]
b_ff <= _T_929 @[exu_div_ctl.scala 596:8]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 392:18]
rvclkhdr.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
small numcase corrected
2021-01-06 13:22:58 +08:00
reg _T_930 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when misc_enable : @[Reg.scala 28:19]
small numcase corrected
2021-01-06 13:22:58 +08:00
_T_930 <= valid_ff_in @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
small numcase corrected
2021-01-06 13:22:58 +08:00
valid_ff <= _T_930 @[exu_div_ctl.scala 597:12]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_1.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
small numcase corrected
2021-01-06 13:22:58 +08:00
reg _T_931 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when misc_enable : @[Reg.scala 28:19]
small numcase corrected
2021-01-06 13:22:58 +08:00
_T_931 <= control_in @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
small numcase corrected
2021-01-06 13:22:58 +08:00
control_ff <= _T_931 @[exu_div_ctl.scala 598:16]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_2.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
small numcase corrected
2021-01-06 13:22:58 +08:00
reg _T_932 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when misc_enable : @[Reg.scala 28:19]
small numcase corrected
2021-01-06 13:22:58 +08:00
_T_932 <= by_zero_case @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
small numcase corrected
2021-01-06 13:22:58 +08:00
by_zero_case_ff <= _T_932 @[exu_div_ctl.scala 599:19]
2 bit divider
2021-01-06 12:32:46 +08:00
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 390:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_3.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
small numcase corrected
2021-01-06 13:22:58 +08:00
reg _T_933 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
2021-01-06 12:32:46 +08:00
when misc_enable : @[Reg.scala 28:19]
small numcase corrected
2021-01-06 13:22:58 +08:00
_T_933 <= shortq_enable @[Reg.scala 28:23]
2 bit divider
2021-01-06 12:32:46 +08:00
skip @[Reg.scala 28:19]
small numcase corrected
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shortq_enable_ff <= _T_933 @[exu_div_ctl.scala 600:20]
node _T_934 = bits(shortq_shift, 4, 1) @[exu_div_ctl.scala 601:45]
2 bit divider
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inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 390:23]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_4.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
small numcase corrected
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reg _T_935 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
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when misc_enable : @[Reg.scala 28:19]
small numcase corrected
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_T_935 <= _T_934 @[Reg.scala 28:23]
2 bit divider
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skip @[Reg.scala 28:19]
small numcase corrected
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node _T_936 = cat(_T_935, UInt<1>("h00")) @[Cat.scala 29:58]
shortq_shift_ff <= _T_936 @[exu_div_ctl.scala 601:19]
2 bit divider
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inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 390:23]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_5.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
small numcase corrected
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reg _T_937 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
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when misc_enable : @[Reg.scala 28:19]
small numcase corrected
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_T_937 <= finish @[Reg.scala 28:23]
2 bit divider
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skip @[Reg.scala 28:19]
small numcase corrected
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finish_ff <= _T_937 @[exu_div_ctl.scala 602:13]
2 bit divider
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inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 390:23]
rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_6.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
small numcase corrected
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reg _T_938 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
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when misc_enable : @[Reg.scala 28:19]
small numcase corrected
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_T_938 <= count_in @[Reg.scala 28:23]
2 bit divider
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skip @[Reg.scala 28:19]
small numcase corrected
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count_ff <= _T_938 @[exu_div_ctl.scala 603:12]
2 bit divider
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inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 390:23]
rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_7.io.en <= a_enable @[lib.scala 393:17]
rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
small numcase corrected
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reg _T_939 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
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when a_enable : @[Reg.scala 28:19]
small numcase corrected
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_T_939 <= a_in @[Reg.scala 28:23]
2 bit divider
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skip @[Reg.scala 28:19]
small numcase corrected
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a_ff <= _T_939 @[exu_div_ctl.scala 605:8]
node _T_940 = bits(b_in, 32, 0) @[exu_div_ctl.scala 606:23]
2 bit divider
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inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 390:23]
rvclkhdr_8.clock <= clock
rvclkhdr_8.reset <= reset
rvclkhdr_8.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_8.io.en <= b_enable @[lib.scala 393:17]
rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
small numcase corrected
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reg _T_941 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
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when b_enable : @[Reg.scala 28:19]
small numcase corrected
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_T_941 <= _T_940 @[Reg.scala 28:23]
2 bit divider
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skip @[Reg.scala 28:19]
small numcase corrected
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b_ff1 <= _T_941 @[exu_div_ctl.scala 606:9]
2 bit divider
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inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 390:23]
rvclkhdr_9.clock <= clock
rvclkhdr_9.reset <= reset
rvclkhdr_9.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_9.io.en <= rq_enable @[lib.scala 393:17]
rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
small numcase corrected
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reg _T_942 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
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when rq_enable : @[Reg.scala 28:19]
small numcase corrected
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_T_942 <= r_in @[Reg.scala 28:23]
2 bit divider
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skip @[Reg.scala 28:19]
small numcase corrected
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r_ff <= _T_942 @[exu_div_ctl.scala 607:8]
2 bit divider
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inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 390:23]
rvclkhdr_10.clock <= clock
rvclkhdr_10.reset <= reset
rvclkhdr_10.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_10.io.en <= rq_enable @[lib.scala 393:17]
rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
small numcase corrected
2021-01-06 13:22:58 +08:00
reg _T_943 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
2 bit divider
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when rq_enable : @[Reg.scala 28:19]
small numcase corrected
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_T_943 <= q_in @[Reg.scala 28:23]
2 bit divider
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skip @[Reg.scala 28:19]
small numcase corrected
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q_ff <= _T_943 @[exu_div_ctl.scala 608:8]
2 bit divider
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