quasar/axi4_to_ahb.anno.json

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2020-12-14 21:22:02 +08:00
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_w_ready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hprot",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_prot"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_aw_ready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_haddr",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_addr",
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_b_valid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hsize",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_size",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hwrite",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_htrans",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_r_valid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_ready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"axi4_to_ahb.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"axi4_to_ahb"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]