2020-10-06 22:30:06 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_iccm_mem :
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module el2_ifu_iccm_mem :
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input clock : Clock
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input reset : UInt<1>
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2020-10-08 14:08:49 +08:00
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output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>, iccm_bank_wr_data : UInt<39>[4]}
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2020-10-06 22:30:06 +08:00
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io.iccm_rd_data <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 22:19]
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io.iccm_rd_data_ecc <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 23:23]
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node _T = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 24:38]
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node _T_1 = eq(_T, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 24:43]
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node _T_2 = bits(_T_1, 0, 0) @[el2_ifu_iccm_mem.scala 24:51]
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node addr_inc = mux(_T_2, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_iccm_mem.scala 24:21]
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node _T_3 = bits(io.iccm_rw_addr, 14, 0) @[el2_ifu_iccm_mem.scala 25:38]
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node _T_4 = add(_T_3, addr_inc) @[el2_ifu_iccm_mem.scala 25:54]
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node addr_bank_inc = tail(_T_4, 1) @[el2_ifu_iccm_mem.scala 25:54]
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wire iccm_bank_wr_data : UInt<39>[4] @[el2_ifu_iccm_mem.scala 27:35]
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node _T_5 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50]
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iccm_bank_wr_data[0] <= _T_5 @[el2_ifu_iccm_mem.scala 29:32]
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node _T_6 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54]
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iccm_bank_wr_data[1] <= _T_6 @[el2_ifu_iccm_mem.scala 30:36]
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node _T_7 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50]
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iccm_bank_wr_data[2] <= _T_7 @[el2_ifu_iccm_mem.scala 29:32]
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node _T_8 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54]
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iccm_bank_wr_data[3] <= _T_8 @[el2_ifu_iccm_mem.scala 30:36]
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node _T_9 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81]
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node _T_10 = eq(_T_9, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:99]
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node _T_11 = and(io.iccm_wren, _T_10) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_12 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121]
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node _T_13 = eq(_T_12, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:139]
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node wren_bank_0 = or(_T_11, _T_13) @[el2_ifu_iccm_mem.scala 33:106]
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node _T_14 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81]
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node _T_15 = eq(_T_14, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:99]
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node _T_16 = and(io.iccm_wren, _T_15) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_17 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121]
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node _T_18 = eq(_T_17, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:139]
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node wren_bank_1 = or(_T_16, _T_18) @[el2_ifu_iccm_mem.scala 33:106]
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node _T_19 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81]
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node _T_20 = eq(_T_19, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:99]
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node _T_21 = and(io.iccm_wren, _T_20) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_22 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121]
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node _T_23 = eq(_T_22, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:139]
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node wren_bank_2 = or(_T_21, _T_23) @[el2_ifu_iccm_mem.scala 33:106]
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node _T_24 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:81]
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node _T_25 = eq(_T_24, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:99]
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node _T_26 = and(io.iccm_wren, _T_25) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_27 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121]
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node _T_28 = eq(_T_27, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:139]
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node wren_bank_3 = or(_T_26, _T_28) @[el2_ifu_iccm_mem.scala 33:106]
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2020-10-08 14:08:49 +08:00
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io.iccm_bank_wr_data[0] <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 35:24]
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io.iccm_bank_wr_data[1] <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 35:24]
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io.iccm_bank_wr_data[2] <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 35:24]
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io.iccm_bank_wr_data[3] <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 35:24]
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node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81]
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node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 36:99]
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node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 36:64]
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node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121]
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node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 36:139]
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node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 36:106]
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node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81]
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node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 36:99]
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node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 36:64]
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node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121]
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node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 36:139]
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node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 36:106]
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node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81]
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node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 36:99]
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node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 36:64]
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node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121]
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node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 36:139]
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node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 36:106]
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node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81]
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node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 36:99]
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node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 36:64]
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node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121]
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node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 36:139]
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node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 36:106]
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node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 37:72]
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node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87]
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node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 37:72]
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node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87]
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node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 37:72]
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node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87]
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node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 37:72]
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node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87]
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node _T_53 = bits(wren_bank_0, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
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node _T_54 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
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node _T_55 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
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node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 39:41]
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node _T_57 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
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node _T_58 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
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node _T_59 = mux(_T_56, _T_57, _T_58) @[el2_ifu_iccm_mem.scala 39:8]
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node addr_bank_0 = mux(_T_53, _T_54, _T_59) @[el2_ifu_iccm_mem.scala 38:55]
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node _T_60 = bits(wren_bank_1, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
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node _T_61 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
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node _T_62 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
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node _T_63 = eq(_T_62, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 39:41]
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node _T_64 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
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node _T_65 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
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node _T_66 = mux(_T_63, _T_64, _T_65) @[el2_ifu_iccm_mem.scala 39:8]
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node addr_bank_1 = mux(_T_60, _T_61, _T_66) @[el2_ifu_iccm_mem.scala 38:55]
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node _T_67 = bits(wren_bank_2, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
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node _T_68 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
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node _T_69 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
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node _T_70 = eq(_T_69, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 39:41]
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node _T_71 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
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node _T_72 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
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node _T_73 = mux(_T_70, _T_71, _T_72) @[el2_ifu_iccm_mem.scala 39:8]
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node addr_bank_2 = mux(_T_67, _T_68, _T_73) @[el2_ifu_iccm_mem.scala 38:55]
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node _T_74 = bits(wren_bank_3, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
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node _T_75 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
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node _T_76 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
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node _T_77 = eq(_T_76, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 39:41]
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node _T_78 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
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node _T_79 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
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node _T_80 = mux(_T_77, _T_78, _T_79) @[el2_ifu_iccm_mem.scala 39:8]
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node addr_bank_3 = mux(_T_74, _T_75, _T_80) @[el2_ifu_iccm_mem.scala 38:55]
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cmem iccm_mem : UInt<39>[4][4096] @[el2_ifu_iccm_mem.scala 41:21]
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node _T_81 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 43:68]
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node _T_82 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 43:68]
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node _T_83 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 43:68]
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node _T_84 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 43:68]
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wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[0] <= _T_81 @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[1] <= _T_82 @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[2] <= _T_83 @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[3] <= _T_84 @[el2_ifu_iccm_mem.scala 43:51]
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node _T_85 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_86 = and(iccm_clken_0, _T_85) @[el2_ifu_iccm_mem.scala 44:70]
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node _T_87 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_88 = and(iccm_clken_1, _T_87) @[el2_ifu_iccm_mem.scala 44:70]
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node _T_89 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_90 = and(iccm_clken_2, _T_89) @[el2_ifu_iccm_mem.scala 44:70]
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node _T_91 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_92 = and(iccm_clken_3, _T_91) @[el2_ifu_iccm_mem.scala 44:70]
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wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[0] <= _T_86 @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[1] <= _T_88 @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[2] <= _T_90 @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[3] <= _T_92 @[el2_ifu_iccm_mem.scala 44:53]
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wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 46:28]
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wire inter : UInt<39>[4] @[el2_ifu_iccm_mem.scala 47:19]
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2020-10-06 22:30:06 +08:00
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write mport _T_93 = iccm_mem[addr_bank_0], clock
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when write_vec[0] :
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_T_93[0] <= iccm_bank_wr_data[0]
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skip
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when write_vec[1] :
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_T_93[1] <= iccm_bank_wr_data[1]
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skip
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when write_vec[2] :
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_T_93[2] <= iccm_bank_wr_data[2]
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skip
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when write_vec[3] :
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_T_93[3] <= iccm_bank_wr_data[3]
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skip
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write mport _T_94 = iccm_mem[addr_bank_1], clock
|
|
|
|
|
when write_vec[0] :
|
|
|
|
|
_T_94[0] <= iccm_bank_wr_data[0]
|
|
|
|
|
skip
|
|
|
|
|
when write_vec[1] :
|
|
|
|
|
_T_94[1] <= iccm_bank_wr_data[1]
|
|
|
|
|
skip
|
|
|
|
|
when write_vec[2] :
|
|
|
|
|
_T_94[2] <= iccm_bank_wr_data[2]
|
|
|
|
|
skip
|
|
|
|
|
when write_vec[3] :
|
|
|
|
|
_T_94[3] <= iccm_bank_wr_data[3]
|
|
|
|
|
skip
|
|
|
|
|
write mport _T_95 = iccm_mem[addr_bank_2], clock
|
|
|
|
|
when write_vec[0] :
|
|
|
|
|
_T_95[0] <= iccm_bank_wr_data[0]
|
|
|
|
|
skip
|
|
|
|
|
when write_vec[1] :
|
|
|
|
|
_T_95[1] <= iccm_bank_wr_data[1]
|
|
|
|
|
skip
|
|
|
|
|
when write_vec[2] :
|
|
|
|
|
_T_95[2] <= iccm_bank_wr_data[2]
|
|
|
|
|
skip
|
|
|
|
|
when write_vec[3] :
|
|
|
|
|
_T_95[3] <= iccm_bank_wr_data[3]
|
|
|
|
|
skip
|
|
|
|
|
write mport _T_96 = iccm_mem[addr_bank_3], clock
|
|
|
|
|
when write_vec[0] :
|
|
|
|
|
_T_96[0] <= iccm_bank_wr_data[0]
|
|
|
|
|
skip
|
|
|
|
|
when write_vec[1] :
|
|
|
|
|
_T_96[1] <= iccm_bank_wr_data[1]
|
|
|
|
|
skip
|
|
|
|
|
when write_vec[2] :
|
|
|
|
|
_T_96[2] <= iccm_bank_wr_data[2]
|
|
|
|
|
skip
|
|
|
|
|
when write_vec[3] :
|
|
|
|
|
_T_96[3] <= iccm_bank_wr_data[3]
|
|
|
|
|
skip
|
2020-10-08 14:08:49 +08:00
|
|
|
read mport _T_97 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 49:25]
|
|
|
|
|
inter[0] <= _T_97[0] @[el2_ifu_iccm_mem.scala 49:9]
|
|
|
|
|
inter[1] <= _T_97[1] @[el2_ifu_iccm_mem.scala 49:9]
|
|
|
|
|
inter[2] <= _T_97[2] @[el2_ifu_iccm_mem.scala 49:9]
|
|
|
|
|
inter[3] <= _T_97[3] @[el2_ifu_iccm_mem.scala 49:9]
|
|
|
|
|
reg _T_98 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
|
|
|
|
|
_T_98 <= inter[0] @[el2_ifu_iccm_mem.scala 50:62]
|
|
|
|
|
iccm_bank_dout[0] <= _T_98 @[el2_ifu_iccm_mem.scala 50:52]
|
|
|
|
|
reg _T_99 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
|
|
|
|
|
_T_99 <= inter[1] @[el2_ifu_iccm_mem.scala 50:62]
|
|
|
|
|
iccm_bank_dout[1] <= _T_99 @[el2_ifu_iccm_mem.scala 50:52]
|
|
|
|
|
reg _T_100 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
|
|
|
|
|
_T_100 <= inter[2] @[el2_ifu_iccm_mem.scala 50:62]
|
|
|
|
|
iccm_bank_dout[2] <= _T_100 @[el2_ifu_iccm_mem.scala 50:52]
|
|
|
|
|
reg _T_101 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
|
|
|
|
|
_T_101 <= inter[3] @[el2_ifu_iccm_mem.scala 50:62]
|
|
|
|
|
iccm_bank_dout[3] <= _T_101 @[el2_ifu_iccm_mem.scala 50:52]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire redundant_valid : UInt<2>
|
|
|
|
|
redundant_valid <= UInt<1>("h00")
|
2020-10-08 14:08:49 +08:00
|
|
|
wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 53:31]
|
|
|
|
|
redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 54:21]
|
|
|
|
|
redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 54:21]
|
|
|
|
|
node _T_102 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
|
|
|
|
|
node _T_103 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
|
|
|
|
|
node _T_104 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
|
|
|
|
|
node _T_105 = eq(_T_103, _T_104) @[el2_ifu_iccm_mem.scala 56:105]
|
|
|
|
|
node _T_106 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
|
|
|
|
|
node _T_107 = eq(_T_106, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 56:169]
|
|
|
|
|
node _T_108 = and(_T_105, _T_107) @[el2_ifu_iccm_mem.scala 56:145]
|
|
|
|
|
node _T_109 = and(_T_102, _T_108) @[el2_ifu_iccm_mem.scala 56:71]
|
|
|
|
|
node _T_110 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
|
|
|
|
|
node _T_111 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
|
|
|
|
|
node _T_112 = eq(_T_110, _T_111) @[el2_ifu_iccm_mem.scala 57:37]
|
|
|
|
|
node _T_113 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
|
|
|
|
|
node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 57:99]
|
|
|
|
|
node _T_115 = and(_T_112, _T_114) @[el2_ifu_iccm_mem.scala 57:77]
|
|
|
|
|
node _T_116 = or(_T_109, _T_115) @[el2_ifu_iccm_mem.scala 56:179]
|
|
|
|
|
node _T_117 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
|
|
|
|
|
node _T_118 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
|
|
|
|
|
node _T_119 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
|
|
|
|
|
node _T_120 = eq(_T_118, _T_119) @[el2_ifu_iccm_mem.scala 56:105]
|
|
|
|
|
node _T_121 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
|
|
|
|
|
node _T_122 = eq(_T_121, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 56:169]
|
|
|
|
|
node _T_123 = and(_T_120, _T_122) @[el2_ifu_iccm_mem.scala 56:145]
|
|
|
|
|
node _T_124 = and(_T_117, _T_123) @[el2_ifu_iccm_mem.scala 56:71]
|
|
|
|
|
node _T_125 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
|
|
|
|
|
node _T_126 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
|
|
|
|
|
node _T_127 = eq(_T_125, _T_126) @[el2_ifu_iccm_mem.scala 57:37]
|
|
|
|
|
node _T_128 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
|
|
|
|
|
node _T_129 = eq(_T_128, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 57:99]
|
|
|
|
|
node _T_130 = and(_T_127, _T_129) @[el2_ifu_iccm_mem.scala 57:77]
|
|
|
|
|
node _T_131 = or(_T_124, _T_130) @[el2_ifu_iccm_mem.scala 56:179]
|
|
|
|
|
node _T_132 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
|
|
|
|
|
node _T_133 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
|
|
|
|
|
node _T_134 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
|
|
|
|
|
node _T_135 = eq(_T_133, _T_134) @[el2_ifu_iccm_mem.scala 56:105]
|
|
|
|
|
node _T_136 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
|
|
|
|
|
node _T_137 = eq(_T_136, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 56:169]
|
|
|
|
|
node _T_138 = and(_T_135, _T_137) @[el2_ifu_iccm_mem.scala 56:145]
|
|
|
|
|
node _T_139 = and(_T_132, _T_138) @[el2_ifu_iccm_mem.scala 56:71]
|
|
|
|
|
node _T_140 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
|
|
|
|
|
node _T_141 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
|
|
|
|
|
node _T_142 = eq(_T_140, _T_141) @[el2_ifu_iccm_mem.scala 57:37]
|
|
|
|
|
node _T_143 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
|
|
|
|
|
node _T_144 = eq(_T_143, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 57:99]
|
|
|
|
|
node _T_145 = and(_T_142, _T_144) @[el2_ifu_iccm_mem.scala 57:77]
|
|
|
|
|
node _T_146 = or(_T_139, _T_145) @[el2_ifu_iccm_mem.scala 56:179]
|
|
|
|
|
node _T_147 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
|
|
|
|
|
node _T_148 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
|
|
|
|
|
node _T_149 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
|
|
|
|
|
node _T_150 = eq(_T_148, _T_149) @[el2_ifu_iccm_mem.scala 56:105]
|
|
|
|
|
node _T_151 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
|
|
|
|
|
node _T_152 = eq(_T_151, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 56:169]
|
|
|
|
|
node _T_153 = and(_T_150, _T_152) @[el2_ifu_iccm_mem.scala 56:145]
|
|
|
|
|
node _T_154 = and(_T_147, _T_153) @[el2_ifu_iccm_mem.scala 56:71]
|
|
|
|
|
node _T_155 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
|
|
|
|
|
node _T_156 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
|
|
|
|
|
node _T_157 = eq(_T_155, _T_156) @[el2_ifu_iccm_mem.scala 57:37]
|
|
|
|
|
node _T_158 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
|
|
|
|
|
node _T_159 = eq(_T_158, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 57:99]
|
|
|
|
|
node _T_160 = and(_T_157, _T_159) @[el2_ifu_iccm_mem.scala 57:77]
|
|
|
|
|
node _T_161 = or(_T_154, _T_160) @[el2_ifu_iccm_mem.scala 56:179]
|
|
|
|
|
node _T_162 = cat(_T_161, _T_146) @[Cat.scala 29:58]
|
|
|
|
|
node _T_163 = cat(_T_162, _T_131) @[Cat.scala 29:58]
|
|
|
|
|
node sel_red1 = cat(_T_163, _T_116) @[Cat.scala 29:58]
|
|
|
|
|
node _T_164 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
|
|
|
|
|
node _T_165 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
|
|
|
|
|
node _T_166 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
|
|
|
|
|
node _T_167 = eq(_T_165, _T_166) @[el2_ifu_iccm_mem.scala 58:105]
|
|
|
|
|
node _T_168 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
|
|
|
|
|
node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 58:169]
|
|
|
|
|
node _T_170 = and(_T_167, _T_169) @[el2_ifu_iccm_mem.scala 58:145]
|
|
|
|
|
node _T_171 = and(_T_164, _T_170) @[el2_ifu_iccm_mem.scala 58:71]
|
|
|
|
|
node _T_172 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
|
|
|
|
|
node _T_173 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
|
|
|
|
|
node _T_174 = eq(_T_172, _T_173) @[el2_ifu_iccm_mem.scala 59:37]
|
|
|
|
|
node _T_175 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
|
|
|
|
|
node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 59:99]
|
|
|
|
|
node _T_177 = and(_T_174, _T_176) @[el2_ifu_iccm_mem.scala 59:77]
|
|
|
|
|
node _T_178 = or(_T_171, _T_177) @[el2_ifu_iccm_mem.scala 58:179]
|
|
|
|
|
node _T_179 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
|
|
|
|
|
node _T_180 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
|
|
|
|
|
node _T_181 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
|
|
|
|
|
node _T_182 = eq(_T_180, _T_181) @[el2_ifu_iccm_mem.scala 58:105]
|
|
|
|
|
node _T_183 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
|
|
|
|
|
node _T_184 = eq(_T_183, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 58:169]
|
|
|
|
|
node _T_185 = and(_T_182, _T_184) @[el2_ifu_iccm_mem.scala 58:145]
|
|
|
|
|
node _T_186 = and(_T_179, _T_185) @[el2_ifu_iccm_mem.scala 58:71]
|
|
|
|
|
node _T_187 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
|
|
|
|
|
node _T_188 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
|
|
|
|
|
node _T_189 = eq(_T_187, _T_188) @[el2_ifu_iccm_mem.scala 59:37]
|
|
|
|
|
node _T_190 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
|
|
|
|
|
node _T_191 = eq(_T_190, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 59:99]
|
|
|
|
|
node _T_192 = and(_T_189, _T_191) @[el2_ifu_iccm_mem.scala 59:77]
|
|
|
|
|
node _T_193 = or(_T_186, _T_192) @[el2_ifu_iccm_mem.scala 58:179]
|
|
|
|
|
node _T_194 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
|
|
|
|
|
node _T_195 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
|
|
|
|
|
node _T_196 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
|
|
|
|
|
node _T_197 = eq(_T_195, _T_196) @[el2_ifu_iccm_mem.scala 58:105]
|
|
|
|
|
node _T_198 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
|
|
|
|
|
node _T_199 = eq(_T_198, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 58:169]
|
|
|
|
|
node _T_200 = and(_T_197, _T_199) @[el2_ifu_iccm_mem.scala 58:145]
|
|
|
|
|
node _T_201 = and(_T_194, _T_200) @[el2_ifu_iccm_mem.scala 58:71]
|
|
|
|
|
node _T_202 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
|
|
|
|
|
node _T_203 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
|
|
|
|
|
node _T_204 = eq(_T_202, _T_203) @[el2_ifu_iccm_mem.scala 59:37]
|
|
|
|
|
node _T_205 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
|
|
|
|
|
node _T_206 = eq(_T_205, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 59:99]
|
|
|
|
|
node _T_207 = and(_T_204, _T_206) @[el2_ifu_iccm_mem.scala 59:77]
|
|
|
|
|
node _T_208 = or(_T_201, _T_207) @[el2_ifu_iccm_mem.scala 58:179]
|
|
|
|
|
node _T_209 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
|
|
|
|
|
node _T_210 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
|
|
|
|
|
node _T_211 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
|
|
|
|
|
node _T_212 = eq(_T_210, _T_211) @[el2_ifu_iccm_mem.scala 58:105]
|
|
|
|
|
node _T_213 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
|
|
|
|
|
node _T_214 = eq(_T_213, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 58:169]
|
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|
node _T_215 = and(_T_212, _T_214) @[el2_ifu_iccm_mem.scala 58:145]
|
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|
node _T_216 = and(_T_209, _T_215) @[el2_ifu_iccm_mem.scala 58:71]
|
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|
node _T_217 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
|
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|
node _T_218 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
|
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|
node _T_219 = eq(_T_217, _T_218) @[el2_ifu_iccm_mem.scala 59:37]
|
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node _T_220 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
|
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|
node _T_221 = eq(_T_220, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 59:99]
|
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|
node _T_222 = and(_T_219, _T_221) @[el2_ifu_iccm_mem.scala 59:77]
|
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|
node _T_223 = or(_T_216, _T_222) @[el2_ifu_iccm_mem.scala 58:179]
|
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|
|
node _T_224 = cat(_T_223, _T_208) @[Cat.scala 29:58]
|
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|
|
node _T_225 = cat(_T_224, _T_193) @[Cat.scala 29:58]
|
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|
|
node sel_red0 = cat(_T_225, _T_178) @[Cat.scala 29:58]
|
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|
|
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 61:27]
|
|
|
|
|
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 61:27]
|
|
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|
|
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 62:27]
|
|
|
|
|
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 62:27]
|
|
|
|
|
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 63:28]
|
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|
|
|
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 64:18]
|
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|
|
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 64:18]
|
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|
|
|
node _T_226 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 66:47]
|
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|
node _T_227 = bits(_T_226, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
|
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node _T_228 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 67:47]
|
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node _T_229 = bits(_T_228, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
|
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node _T_230 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 68:47]
|
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node _T_231 = not(_T_230) @[el2_ifu_iccm_mem.scala 68:36]
|
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|
node _T_232 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 68:64]
|
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node _T_233 = not(_T_232) @[el2_ifu_iccm_mem.scala 68:53]
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node _T_234 = and(_T_231, _T_233) @[el2_ifu_iccm_mem.scala 68:51]
|
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node _T_235 = bits(_T_234, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
|
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node _T_236 = mux(_T_227, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
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node _T_237 = mux(_T_229, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_238 = mux(_T_235, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
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node _T_239 = or(_T_236, _T_237) @[Mux.scala 27:72]
|
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|
|
node _T_240 = or(_T_239, _T_238) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 14:08:49 +08:00
|
|
|
iccm_bank_dout_fn_0 <= _T_240 @[Mux.scala 27:72]
|
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|
|
node _T_241 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 66:47]
|
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node _T_242 = bits(_T_241, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
|
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node _T_243 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 67:47]
|
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node _T_244 = bits(_T_243, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
|
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node _T_245 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 68:47]
|
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node _T_246 = not(_T_245) @[el2_ifu_iccm_mem.scala 68:36]
|
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|
node _T_247 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 68:64]
|
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node _T_248 = not(_T_247) @[el2_ifu_iccm_mem.scala 68:53]
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|
node _T_249 = and(_T_246, _T_248) @[el2_ifu_iccm_mem.scala 68:51]
|
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node _T_250 = bits(_T_249, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
|
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|
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node _T_251 = mux(_T_242, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_252 = mux(_T_244, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_253 = mux(_T_250, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_254 = or(_T_251, _T_252) @[Mux.scala 27:72]
|
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|
|
node _T_255 = or(_T_254, _T_253) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 14:08:49 +08:00
|
|
|
iccm_bank_dout_fn_1 <= _T_255 @[Mux.scala 27:72]
|
|
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|
|
node _T_256 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 66:47]
|
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|
|
node _T_257 = bits(_T_256, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
|
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|
|
node _T_258 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 67:47]
|
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|
|
node _T_259 = bits(_T_258, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
|
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|
|
node _T_260 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 68:47]
|
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|
|
|
node _T_261 = not(_T_260) @[el2_ifu_iccm_mem.scala 68:36]
|
|
|
|
|
node _T_262 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 68:64]
|
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|
|
|
node _T_263 = not(_T_262) @[el2_ifu_iccm_mem.scala 68:53]
|
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|
|
node _T_264 = and(_T_261, _T_263) @[el2_ifu_iccm_mem.scala 68:51]
|
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|
|
node _T_265 = bits(_T_264, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
|
|
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|
|
node _T_266 = mux(_T_257, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_267 = mux(_T_259, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_268 = mux(_T_265, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_269 = or(_T_266, _T_267) @[Mux.scala 27:72]
|
|
|
|
|
node _T_270 = or(_T_269, _T_268) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 14:08:49 +08:00
|
|
|
iccm_bank_dout_fn_2 <= _T_270 @[Mux.scala 27:72]
|
|
|
|
|
node _T_271 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 66:47]
|
|
|
|
|
node _T_272 = bits(_T_271, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
|
|
|
|
|
node _T_273 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 67:47]
|
|
|
|
|
node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
|
|
|
|
|
node _T_275 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 68:47]
|
|
|
|
|
node _T_276 = not(_T_275) @[el2_ifu_iccm_mem.scala 68:36]
|
|
|
|
|
node _T_277 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 68:64]
|
|
|
|
|
node _T_278 = not(_T_277) @[el2_ifu_iccm_mem.scala 68:53]
|
|
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|
|
node _T_279 = and(_T_276, _T_278) @[el2_ifu_iccm_mem.scala 68:51]
|
|
|
|
|
node _T_280 = bits(_T_279, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
|
|
|
|
|
node _T_281 = mux(_T_272, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_282 = mux(_T_274, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_283 = mux(_T_280, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_284 = or(_T_281, _T_282) @[Mux.scala 27:72]
|
|
|
|
|
node _T_285 = or(_T_284, _T_283) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 14:08:49 +08:00
|
|
|
iccm_bank_dout_fn_3 <= _T_285 @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire redundant_lru : UInt<1>
|
|
|
|
|
redundant_lru <= UInt<1>("h00")
|
2020-10-08 14:08:49 +08:00
|
|
|
node _T_286 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:20]
|
|
|
|
|
node r0_addr_en = and(_T_286, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 70:35]
|
|
|
|
|
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 71:35]
|
|
|
|
|
node _T_287 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 72:63]
|
|
|
|
|
node _T_288 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 72:78]
|
|
|
|
|
node _T_289 = or(_T_287, _T_288) @[el2_ifu_iccm_mem.scala 72:67]
|
|
|
|
|
node _T_290 = and(_T_289, io.iccm_rden) @[el2_ifu_iccm_mem.scala 72:83]
|
|
|
|
|
node _T_291 = and(_T_290, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 72:98]
|
|
|
|
|
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_291) @[el2_ifu_iccm_mem.scala 72:50]
|
|
|
|
|
node _T_292 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:55]
|
|
|
|
|
node _T_293 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 73:84]
|
|
|
|
|
node _T_294 = mux(_T_293, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:74]
|
|
|
|
|
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_292, _T_294) @[el2_ifu_iccm_mem.scala 73:29]
|
|
|
|
|
reg _T_295 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2020-10-06 22:30:06 +08:00
|
|
|
when redundant_lru_en : @[Reg.scala 28:19]
|
2020-10-08 14:08:49 +08:00
|
|
|
_T_295 <= redundant_lru_in @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 14:08:49 +08:00
|
|
|
redundant_lru <= _T_295 @[el2_ifu_iccm_mem.scala 74:17]
|
|
|
|
|
node _T_296 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 75:52]
|
|
|
|
|
reg _T_297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2020-10-06 22:30:06 +08:00
|
|
|
when r0_addr_en : @[Reg.scala 28:19]
|
2020-10-08 14:08:49 +08:00
|
|
|
_T_297 <= _T_296 @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 14:08:49 +08:00
|
|
|
redundant_address[0] <= _T_297 @[el2_ifu_iccm_mem.scala 75:24]
|
|
|
|
|
node _T_298 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 76:52]
|
|
|
|
|
node _T_299 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 76:85]
|
|
|
|
|
reg _T_300 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_299 : @[Reg.scala 28:19]
|
|
|
|
|
_T_300 <= _T_298 @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 14:08:49 +08:00
|
|
|
redundant_address[1] <= _T_300 @[el2_ifu_iccm_mem.scala 76:24]
|
|
|
|
|
node _T_301 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 77:57]
|
|
|
|
|
reg _T_302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_301 : @[Reg.scala 28:19]
|
|
|
|
|
_T_302 <= UInt<1>("h01") @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 14:08:49 +08:00
|
|
|
reg _T_303 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2020-10-06 22:30:06 +08:00
|
|
|
when r0_addr_en : @[Reg.scala 28:19]
|
2020-10-08 14:08:49 +08:00
|
|
|
_T_303 <= UInt<1>("h01") @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 14:08:49 +08:00
|
|
|
node _T_304 = cat(_T_302, _T_303) @[Cat.scala 29:58]
|
|
|
|
|
redundant_valid <= _T_304 @[el2_ifu_iccm_mem.scala 77:19]
|
|
|
|
|
node _T_305 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 79:45]
|
|
|
|
|
node _T_306 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 79:85]
|
|
|
|
|
node _T_307 = eq(_T_305, _T_306) @[el2_ifu_iccm_mem.scala 79:61]
|
|
|
|
|
node _T_308 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 80:22]
|
|
|
|
|
node _T_309 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 80:48]
|
|
|
|
|
node _T_310 = and(_T_308, _T_309) @[el2_ifu_iccm_mem.scala 80:26]
|
|
|
|
|
node _T_311 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 80:70]
|
|
|
|
|
node _T_312 = eq(_T_311, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 80:75]
|
|
|
|
|
node _T_313 = or(_T_310, _T_312) @[el2_ifu_iccm_mem.scala 80:52]
|
|
|
|
|
node _T_314 = and(_T_307, _T_313) @[el2_ifu_iccm_mem.scala 79:102]
|
|
|
|
|
node _T_315 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 80:101]
|
|
|
|
|
node _T_316 = and(_T_314, _T_315) @[el2_ifu_iccm_mem.scala 80:84]
|
|
|
|
|
node _T_317 = and(_T_316, io.iccm_wren) @[el2_ifu_iccm_mem.scala 80:105]
|
|
|
|
|
node _T_318 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 81:6]
|
|
|
|
|
node _T_319 = and(_T_318, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 81:21]
|
|
|
|
|
node redundant_data0_en = or(_T_317, _T_319) @[el2_ifu_iccm_mem.scala 80:121]
|
|
|
|
|
node _T_320 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 82:49]
|
|
|
|
|
node _T_321 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 82:73]
|
|
|
|
|
node _T_322 = and(_T_320, _T_321) @[el2_ifu_iccm_mem.scala 82:52]
|
|
|
|
|
node _T_323 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 82:100]
|
|
|
|
|
node _T_324 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 82:122]
|
|
|
|
|
node _T_325 = eq(_T_324, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 82:127]
|
|
|
|
|
node _T_326 = and(_T_323, _T_325) @[el2_ifu_iccm_mem.scala 82:104]
|
|
|
|
|
node _T_327 = or(_T_322, _T_326) @[el2_ifu_iccm_mem.scala 82:78]
|
|
|
|
|
node _T_328 = bits(_T_327, 0, 0) @[el2_ifu_iccm_mem.scala 82:137]
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node _T_329 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 83:20]
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node _T_330 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 83:44]
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node redundant_data0_in = mux(_T_328, _T_329, _T_330) @[el2_ifu_iccm_mem.scala 82:31]
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node _T_331 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 84:78]
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reg _T_332 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_331 : @[Reg.scala 28:19]
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_T_332 <= redundant_data0_in @[Reg.scala 28:23]
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2020-10-06 22:30:06 +08:00
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skip @[Reg.scala 28:19]
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2020-10-08 14:08:49 +08:00
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redundant_data[0] <= _T_332 @[el2_ifu_iccm_mem.scala 84:21]
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node _T_333 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 86:45]
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node _T_334 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 86:85]
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node _T_335 = eq(_T_333, _T_334) @[el2_ifu_iccm_mem.scala 86:61]
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node _T_336 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 87:22]
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node _T_337 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 87:48]
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node _T_338 = and(_T_336, _T_337) @[el2_ifu_iccm_mem.scala 87:26]
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node _T_339 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 87:70]
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node _T_340 = eq(_T_339, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 87:75]
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node _T_341 = or(_T_338, _T_340) @[el2_ifu_iccm_mem.scala 87:52]
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node _T_342 = and(_T_335, _T_341) @[el2_ifu_iccm_mem.scala 86:102]
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node _T_343 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 87:101]
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node _T_344 = and(_T_342, _T_343) @[el2_ifu_iccm_mem.scala 87:84]
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node _T_345 = and(_T_344, io.iccm_wren) @[el2_ifu_iccm_mem.scala 87:105]
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node _T_346 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 88:6]
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node _T_347 = and(_T_346, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 88:21]
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node redundant_data1_en = or(_T_345, _T_347) @[el2_ifu_iccm_mem.scala 87:121]
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node _T_348 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:49]
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node _T_349 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 89:73]
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node _T_350 = and(_T_348, _T_349) @[el2_ifu_iccm_mem.scala 89:52]
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node _T_351 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 89:100]
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node _T_352 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:122]
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node _T_353 = eq(_T_352, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:127]
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node _T_354 = and(_T_351, _T_353) @[el2_ifu_iccm_mem.scala 89:104]
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node _T_355 = or(_T_350, _T_354) @[el2_ifu_iccm_mem.scala 89:78]
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node _T_356 = bits(_T_355, 0, 0) @[el2_ifu_iccm_mem.scala 89:137]
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node _T_357 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 90:20]
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node _T_358 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 90:44]
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node redundant_data1_in = mux(_T_356, _T_357, _T_358) @[el2_ifu_iccm_mem.scala 89:31]
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node _T_359 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:78]
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reg _T_360 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_359 : @[Reg.scala 28:19]
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_T_360 <= redundant_data1_in @[Reg.scala 28:23]
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2020-10-06 22:30:06 +08:00
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skip @[Reg.scala 28:19]
|
2020-10-08 14:08:49 +08:00
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redundant_data[1] <= _T_360 @[el2_ifu_iccm_mem.scala 91:21]
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node _T_361 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 93:50]
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reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 93:34]
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iccm_rd_addr_lo_q <= _T_361 @[el2_ifu_iccm_mem.scala 93:34]
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node _T_362 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 94:48]
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reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 94:34]
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iccm_rd_addr_hi_q <= _T_362 @[el2_ifu_iccm_mem.scala 94:34]
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node _T_363 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 96:86]
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node _T_364 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
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node _T_365 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 96:86]
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node _T_366 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
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node _T_367 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 96:86]
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node _T_368 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
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node _T_369 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:86]
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node _T_370 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
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node _T_371 = mux(_T_363, _T_364, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_372 = mux(_T_365, _T_366, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_373 = mux(_T_367, _T_368, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_374 = mux(_T_369, _T_370, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_375 = or(_T_371, _T_372) @[Mux.scala 27:72]
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node _T_376 = or(_T_375, _T_373) @[Mux.scala 27:72]
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node _T_377 = or(_T_376, _T_374) @[Mux.scala 27:72]
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wire _T_378 : UInt<32> @[Mux.scala 27:72]
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_T_378 <= _T_377 @[Mux.scala 27:72]
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node _T_379 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
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node _T_380 = eq(_T_379, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:77]
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node _T_381 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
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node _T_382 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
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node _T_383 = eq(_T_382, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 97:77]
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node _T_384 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
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node _T_385 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
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node _T_386 = eq(_T_385, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 97:77]
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node _T_387 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
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node _T_388 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
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node _T_389 = eq(_T_388, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 97:77]
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node _T_390 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
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node _T_391 = mux(_T_380, _T_381, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_392 = mux(_T_383, _T_384, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_393 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_394 = mux(_T_389, _T_390, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_395 = or(_T_391, _T_392) @[Mux.scala 27:72]
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node _T_396 = or(_T_395, _T_393) @[Mux.scala 27:72]
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node _T_397 = or(_T_396, _T_394) @[Mux.scala 27:72]
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wire _T_398 : UInt<32> @[Mux.scala 27:72]
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_T_398 <= _T_397 @[Mux.scala 27:72]
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node iccm_rd_data_pre = cat(_T_378, _T_398) @[Cat.scala 29:58]
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node _T_399 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 98:43]
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node _T_400 = bits(_T_399, 0, 0) @[el2_ifu_iccm_mem.scala 98:53]
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node _T_401 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
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node _T_402 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 98:89]
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node _T_403 = cat(_T_401, _T_402) @[Cat.scala 29:58]
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node _T_404 = mux(_T_400, _T_403, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 98:25]
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io.iccm_rd_data <= _T_404 @[el2_ifu_iccm_mem.scala 98:19]
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node _T_405 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 99:85]
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node _T_406 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 99:85]
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node _T_407 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 99:85]
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node _T_408 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 99:85]
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node _T_409 = mux(_T_405, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_410 = mux(_T_406, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_411 = mux(_T_407, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_412 = mux(_T_408, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_413 = or(_T_409, _T_410) @[Mux.scala 27:72]
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node _T_414 = or(_T_413, _T_411) @[Mux.scala 27:72]
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node _T_415 = or(_T_414, _T_412) @[Mux.scala 27:72]
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wire _T_416 : UInt<39> @[Mux.scala 27:72]
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_T_416 <= _T_415 @[Mux.scala 27:72]
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node _T_417 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
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node _T_418 = eq(_T_417, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 100:79]
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node _T_419 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
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node _T_420 = eq(_T_419, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 100:79]
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node _T_421 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
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node _T_422 = eq(_T_421, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 100:79]
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node _T_423 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
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node _T_424 = eq(_T_423, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 100:79]
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node _T_425 = mux(_T_418, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_426 = mux(_T_420, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_427 = mux(_T_422, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_428 = mux(_T_424, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_429 = or(_T_425, _T_426) @[Mux.scala 27:72]
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node _T_430 = or(_T_429, _T_427) @[Mux.scala 27:72]
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node _T_431 = or(_T_430, _T_428) @[Mux.scala 27:72]
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wire _T_432 : UInt<39> @[Mux.scala 27:72]
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_T_432 <= _T_431 @[Mux.scala 27:72]
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node _T_433 = cat(_T_416, _T_432) @[Cat.scala 29:58]
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io.iccm_rd_data_ecc <= _T_433 @[el2_ifu_iccm_mem.scala 99:23]
|
2020-10-06 22:30:06 +08:00
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