2020-09-07 17:44:14 +08:00
|
|
|
|
# EL2 SweRV RISC-V Core Chiselified Version from <> LAMPRO MELLON
|
2020-09-04 14:17:16 +08:00
|
|
|
|
|
2020-09-07 17:44:14 +08:00
|
|
|
|
This repository contains the SweRV EL2 Core design in CHISEL
|
2020-09-04 14:17:16 +08:00
|
|
|
|
|
2020-09-07 17:44:14 +08:00
|
|
|
|
## Back ground
|
2020-09-04 14:17:16 +08:00
|
|
|
|
|
2020-09-07 17:44:14 +08:00
|
|
|
|
The project is being made for learning purpose. Copy rights to the SweRV-EL2 belongs to Wrestern Digital
|
2020-09-04 14:17:16 +08:00
|
|
|
|
|
2020-09-07 17:44:14 +08:00
|
|
|
|
## Directory Structure
|
2020-09-04 14:17:16 +08:00
|
|
|
|
|
2020-09-07 17:44:14 +08:00
|
|
|
|
├── configs # Configurations Dir
|
|
|
|
|
│ └── snapshots # Where generated configuration files are created
|
|
|
|
|
├── design # Design root dir
|
|
|
|
|
│ ├── dbg # Debugger
|
|
|
|
|
│ ├── dec # Decode, Registers and Exceptions
|
|
|
|
|
│ ├── dmi # DMI block
|
|
|
|
|
│ ├── exu # EXU (ALU/MUL/DIV)
|
|
|
|
|
│ ├── ifu # Fetch & Branch Prediction
|
|
|
|
|
│ ├── include
|
|
|
|
|
│ ├── lib
|
|
|
|
|
│ └── lsu # Load/Store
|
|
|
|
|
├── docs
|
|
|
|
|
├── tools # Scripts/Makefiles
|
|
|
|
|
└── testbench # (Very) simple testbench
|
|
|
|
|
├── asm # Example assembly files
|
|
|
|
|
└── hex # Canned demo hex files
|
2020-09-04 14:17:16 +08:00
|
|
|
|
|