2020-09-07 16:27:29 +08:00
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_out",
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"sources":[
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2020-09-08 13:00:45 +08:00
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_in",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_in2"
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2020-09-07 16:27:29 +08:00
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"el2_ifu_bp_ctl"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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