2020-09-10 15:04:38 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit EL2_IC_DATA :
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module EL2_IC_DATA :
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input clock : Clock
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input reset : UInt<1>
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2020-09-30 14:57:37 +08:00
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output io : {flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>}
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2020-09-10 15:04:38 +08:00
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2020-09-30 14:57:37 +08:00
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io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 194:17]
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io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 195:23]
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io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 196:16]
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io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 197:16]
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node _T = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 198:70]
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node _T_1 = and(io.ic_debug_rd_en, _T) @[el2_ifu_ic_mem.scala 198:68]
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node _T_2 = bits(_T_1, 0, 0) @[Bitwise.scala 72:15]
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node _T_3 = mux(_T_2, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node ic_debug_rd_way_en = and(_T_3, io.ic_debug_way) @[el2_ifu_ic_mem.scala 198:94]
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node _T_4 = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 199:70]
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node _T_5 = and(io.ic_debug_wr_en, _T_4) @[el2_ifu_ic_mem.scala 199:68]
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wire _T_6 : UInt<1>[2] @[el2_lib.scala 185:48]
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_T_6[0] <= _T_5 @[el2_lib.scala 185:48]
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_T_6[1] <= _T_5 @[el2_lib.scala 185:48]
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2020-09-12 23:12:43 +08:00
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node _T_7 = cat(_T_6[0], _T_6[1]) @[Cat.scala 29:58]
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2020-09-30 14:57:37 +08:00
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node ic_debug_wr_way_en = and(_T_7, io.ic_debug_way) @[el2_ifu_ic_mem.scala 199:94]
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node _T_8 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 202:78]
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node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 202:113]
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node _T_10 = bits(_T_9, 0, 0) @[Bitwise.scala 72:15]
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node _T_11 = mux(_T_10, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_12 = and(ic_debug_wr_way_en, _T_11) @[el2_ifu_ic_mem.scala 202:38]
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node _T_13 = or(io.ic_wr_en, _T_12) @[el2_ifu_ic_mem.scala 202:17]
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node _T_14 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 203:21]
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node _T_15 = eq(_T_14, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 203:56]
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node _T_16 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 202:78]
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node _T_17 = eq(_T_16, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 202:113]
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node _T_18 = bits(_T_17, 0, 0) @[Bitwise.scala 72:15]
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node _T_19 = mux(_T_18, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_20 = and(ic_debug_wr_way_en, _T_19) @[el2_ifu_ic_mem.scala 202:38]
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node _T_21 = or(io.ic_wr_en, _T_20) @[el2_ifu_ic_mem.scala 202:17]
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node _T_22 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 203:21]
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node _T_23 = eq(_T_22, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 203:56]
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node _T_24 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 202:78]
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node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 202:113]
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node _T_26 = bits(_T_25, 0, 0) @[Bitwise.scala 72:15]
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node _T_27 = mux(_T_26, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_28 = and(ic_debug_wr_way_en, _T_27) @[el2_ifu_ic_mem.scala 202:38]
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node _T_29 = or(io.ic_wr_en, _T_28) @[el2_ifu_ic_mem.scala 202:17]
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node _T_30 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 203:21]
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node _T_31 = eq(_T_30, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 203:56]
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node _T_32 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 202:78]
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node _T_33 = eq(_T_32, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 202:113]
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node _T_34 = bits(_T_33, 0, 0) @[Bitwise.scala 72:15]
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node _T_35 = mux(_T_34, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_36 = and(ic_debug_wr_way_en, _T_35) @[el2_ifu_ic_mem.scala 202:38]
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node _T_37 = or(io.ic_wr_en, _T_36) @[el2_ifu_ic_mem.scala 202:17]
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node _T_38 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 203:21]
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node _T_39 = eq(_T_38, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 203:56]
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2020-09-10 15:04:38 +08:00
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