43 lines
1.2 KiB
JSON
43 lines
1.2 KiB
JSON
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_clkdomain|lsu_clkdomain>io_lsu_busm_clken",
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"sources":[
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"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_clk_en",
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"~lsu_clkdomain|lsu_clkdomain>io_clk_override",
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"~lsu_clkdomain|lsu_clkdomain>io_lsu_busreq_r",
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"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_buffer_empty_any"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_obuf_c1_clken",
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"sources":[
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"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_clk_en",
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"~lsu_clkdomain|lsu_clkdomain>io_clk_override",
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"~lsu_clkdomain|lsu_clkdomain>io_lsu_bus_buffer_pend_any",
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"~lsu_clkdomain|lsu_clkdomain>io_lsu_busreq_r"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"lsu_clkdomain.gated_latch",
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"resourceId":"/vsrc/gated_latch.sv"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"lsu_clkdomain"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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