quasar/dma_ctrl.anno.json

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2020-12-16 19:02:33 +08:00
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_ifu_dma_dma_mem_ctl_dma_mem_tag",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_mem_tag"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_ifu_dma_dma_mem_ctl_dma_mem_addr",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_dec_dma_tlu_dma_dma_dccm_stall_any",
"sources":[
"~dma_ctrl|dma_ctrl>io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_dec_dma_tlu_dma_dma_pmu_any_write",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~dma_ctrl|dma_ctrl>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dccm_ready",
"~dma_ctrl|dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_dec_dma_tlu_dma_dma_iccm_stall_any",
"sources":[
"~dma_ctrl|dma_ctrl>io_ifu_dma_dma_ifc_dma_iccm_stall_any",
"~dma_ctrl|dma_ctrl>io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
"sources":[
"~dma_ctrl|dma_ctrl>io_iccm_ready",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_dec_dma_tlu_dma_dma_pmu_any_read",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~dma_ctrl|dma_ctrl>io_ifu_dma_dma_mem_ctl_dma_iccm_req",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dccm_ready",
"~dma_ctrl|dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_dec_dma_dctl_dma_dma_dccm_stall_any",
"sources":[
"~dma_ctrl|dma_ctrl>io_dec_dma_tlu_dma_dma_dccm_stall_any",
"~dma_ctrl|dma_ctrl>io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_dec_dma_tlu_dma_dma_pmu_dccm_read",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_ifu_dma_dma_mem_ctl_dma_mem_wdata",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_ifu_dma_dma_mem_ctl_dma_mem_sz",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_ifu_dma_dma_ifc_dma_iccm_stall_any",
"sources":[
"~dma_ctrl|dma_ctrl>io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_dec_dma_tlu_dma_dma_pmu_dccm_write",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_ifu_dma_dma_mem_ctl_dma_mem_write",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"sources":[
"~dma_ctrl|dma_ctrl>io_lsu_dma_dccm_ready",
"~dma_ctrl|dma_ctrl>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"dma_ctrl.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"dma_ctrl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]