quasar/el2_lsu_trigger.anno.json

[
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~el2_lsu_trigger|el2_lsu_trigger>io_lsu_trigger_match_m",
    "sources":[
      "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_valid",
      "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_dma",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_store",
      "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_store",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_store",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_load",
      "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_load",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_select",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_store",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_store",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_load",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_select",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_load",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_select",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_load",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_select",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_tdata2",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_0_match_pkt",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_tdata2",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_1_match_pkt",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_tdata2",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_3_match_pkt",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_tdata2",
      "~el2_lsu_trigger|el2_lsu_trigger>io_trigger_pkt_any_2_match_pkt",
      "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_addr_m",
      "~el2_lsu_trigger|el2_lsu_trigger>io_store_data_m",
      "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_word",
      "~el2_lsu_trigger|el2_lsu_trigger>io_lsu_pkt_m_bits_half"
    ]
  },
  {
    "class":"firrtl.EmitCircuitAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.options.TargetDirAnnotation",
    "directory":"."
  },
  {
    "class":"firrtl.options.OutputAnnotationFileAnnotation",
    "file":"el2_lsu_trigger"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"."
  }
]