quasar/axi4_to_ahb.anno.json

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2020-11-27 19:33:17 +08:00
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_bvalid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_htrans",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hwrite",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_araddr",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hsize",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arsize",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hprot",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arprot"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"axi4_to_ahb.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"axi4_to_ahb"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]