quasar/lsu.anno.json

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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn",
"sources":[
"~lsu|lsu>io_axi_ar_ready",
"~lsu|lsu>io_axi_aw_ready",
"~lsu|lsu>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
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"sources":[
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"~lsu|lsu>io_dec_tlu_core_ecc_disable",
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"~lsu|lsu>io_dccm_rd_data_hi",
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"~lsu|lsu>io_dccm_rd_data_lo"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_single_ecc_error_incr",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
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{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rd_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
]
},
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{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dccm_ready",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_dccm_wr_data_hi",
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"sources":[
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wren",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
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"~lsu|lsu>io_lsu_p_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy",
"sources":[
"~lsu|lsu>io_axi_ar_ready",
"~lsu|lsu>io_axi_aw_ready",
"~lsu|lsu>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_pic_picm_rden",
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"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
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"~lsu|lsu>io_dec_tlu_flush_lower_r",
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"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_dccm_rd_addr_lo",
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"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
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"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_dccm_wr_addr_lo",
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"sources":[
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
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"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
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"~lsu|lsu>io_dec_lsu_valid_raw_d",
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"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
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"~lsu|lsu>io_lsu_p_bits_word"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_fir_addr",
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"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
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"~lsu|lsu>io_dccm_rd_data_lo"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr",
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"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
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"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_pic_picm_wr_data",
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"sources":[
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"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
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"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
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"~lsu|lsu>io_lsu_p_valid",
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"~lsu|lsu>io_dec_tlu_flush_lower_r",
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"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_dccm_rd_data_lo"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_trigger_match_m",
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"sources":[
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"~lsu|lsu>io_trigger_pkt_any_0_store",
"~lsu|lsu>io_trigger_pkt_any_1_store",
"~lsu|lsu>io_trigger_pkt_any_3_m",
"~lsu|lsu>io_trigger_pkt_any_0_load",
"~lsu|lsu>io_trigger_pkt_any_0_select",
"~lsu|lsu>io_trigger_pkt_any_3_store",
"~lsu|lsu>io_trigger_pkt_any_2_store",
"~lsu|lsu>io_trigger_pkt_any_1_load",
"~lsu|lsu>io_trigger_pkt_any_1_select",
"~lsu|lsu>io_trigger_pkt_any_2_m",
"~lsu|lsu>io_trigger_pkt_any_3_load",
"~lsu|lsu>io_trigger_pkt_any_3_select",
"~lsu|lsu>io_trigger_pkt_any_2_load",
"~lsu|lsu>io_trigger_pkt_any_2_select",
"~lsu|lsu>io_trigger_pkt_any_0_m",
"~lsu|lsu>io_trigger_pkt_any_1_m",
"~lsu|lsu>io_trigger_pkt_any_0_tdata2",
"~lsu|lsu>io_trigger_pkt_any_0_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_1_tdata2",
"~lsu|lsu>io_trigger_pkt_any_1_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_3_tdata2",
"~lsu|lsu>io_trigger_pkt_any_3_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_2_tdata2",
"~lsu|lsu>io_trigger_pkt_any_2_match_pkt",
"~lsu|lsu>io_lsu_pic_picm_rd_data"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_pic_picm_wren",
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"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
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"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
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"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_result_corr_r",
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"sources":[
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"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_store_stall_any",
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"sources":[
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"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
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"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_offset_d",
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"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_fastint_stall_any",
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"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_pic_picm_wraddr",
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"sources":[
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"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
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"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_fir_error",
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"sources":[
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"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_dccm_rden",
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"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
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"~lsu|lsu>io_dec_lsu_valid_raw_d",
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"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
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"~lsu|lsu>io_dec_lsu_offset_d",
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"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
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"~lsu|lsu>io_dec_tlu_flush_lower_r",
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"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_store"
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu|lsu>io_lsu_pic_picm_mken",
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"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_store",
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"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
2020-12-22 18:24:39 +08:00
"~lsu|lsu>io_dccm_rd_data_hi",
2021-01-08 19:13:00 +08:00
"~lsu|lsu>io_dccm_rd_data_lo"
2020-12-22 18:24:39 +08:00
]
},
{
"class":"firrtl.transforms.CombinationalPath",
2021-01-08 19:13:00 +08:00
"sink":"~lsu|lsu>io_lsu_error_pkt_r_bits_single_ecc_error",
2020-12-22 18:24:39 +08:00
"sources":[
2021-01-08 19:13:00 +08:00
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
2020-12-22 18:24:39 +08:00
"~lsu|lsu>io_dccm_rd_data_hi",
2021-01-08 19:13:00 +08:00
"~lsu|lsu>io_dccm_rd_data_lo"
2020-12-22 18:24:39 +08:00
]
},
{
"class":"firrtl.transforms.CombinationalPath",
2021-01-08 19:13:00 +08:00
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r",
2020-12-22 18:24:39 +08:00
"sources":[
2021-01-08 19:13:00 +08:00
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_error_pkt_r_valid",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_load_stall_any",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
2020-12-22 18:24:39 +08:00
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_offset_d",
2021-01-08 19:13:00 +08:00
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
2020-12-22 18:24:39 +08:00
]
},
{
"class":"firrtl.transforms.CombinationalPath",
2021-01-08 19:13:00 +08:00
"sink":"~lsu|lsu>io_dccm_wr_data_lo",
2020-12-22 18:24:39 +08:00
"sources":[
2021-01-08 19:13:00 +08:00
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
2020-12-22 18:24:39 +08:00
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
2021-01-08 19:13:00 +08:00
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
2020-12-22 18:24:39 +08:00
]
},
{
"class":"firrtl.transforms.CombinationalPath",
2021-01-08 19:13:00 +08:00
"sink":"~lsu|lsu>io_lsu_error_pkt_r_bits_mscause",
2020-12-22 18:24:39 +08:00
"sources":[
2021-01-08 19:13:00 +08:00
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
2020-12-22 18:24:39 +08:00
"~lsu|lsu>io_dccm_rd_data_hi",
2021-01-08 19:13:00 +08:00
"~lsu|lsu>io_dccm_rd_data_lo"
2020-12-22 18:24:39 +08:00
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m",
"sources":[
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]