36 lines
1.6 KiB
Markdown
36 lines
1.6 KiB
Markdown
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# Quasar RISC-V Core 2.0 from Lampro Mellon
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## Release Notes
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* Multiple debug module compliance deviations and bugs reported by Codasip
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* Updates to debug module to level compliance to version 0.13.2 of debug spec
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* Trigger chaining compliance fixes
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* Power optimization improvements and clock gating improvements
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* Significantly lower power in sleep as well as normal operation.
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* Enhanced debug memory abstract command to access internal as well as external memories
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* Added bit-manipulation support for Zba, Zbb, Zbc, Zbe, Zbf, Zbp, Zbr, Zbs (Jan 29, 2020 Draft spec).
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* Zbs and Zbb are enabled by default. Use -set=bitmanip+zb*=1 to enable other sub-extensions.
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* Enhancements and additional configurations options for a faster divider
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* JTAG controller intial state issue fixed
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* Branch predictor fully-associative mode for 8,16,32 entries.
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* Corner case bugs fixes related to
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* Bus protocol corner cases (ahb)
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* Fetch bus error recording improved accuracy
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* Branch predictor pathological timing cases fixes
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* Fast interrupt with DCCM ECC errors priority bug
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* MPC & PMU protocol cleanup
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* Performance counter bug fixes (counting branch prediction events)
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* Triggers and ECC correctable error overflows bug fixes
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* Demo test-bench updates
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* Handling bigger test sizes using associative arrays in external memory slaves,
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* simplified test building process and CCM loading functions (only program.hex is generated, no data.hex)
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* Improved Makefile and example tests (see README)
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* Generating crt0 and link.ld from quasar.config
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# Quasar RISC-V Core 1.0 from Lampro Mellon
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## Release Notes
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Initial release
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