65 lines
2.4 KiB
Systemverilog
65 lines
2.4 KiB
Systemverilog
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module el2_btb_tag_hash
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`include "parameter.sv"
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(
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input logic [BTB_ADDR_HI+BTB_BTAG_SIZE+BTB_BTAG_SIZE+BTB_BTAG_SIZE:BTB_ADDR_HI+1] pc,
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output logic [BTB_BTAG_SIZE-1:0] hash
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);
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assign hash = {(pc[BTB_ADDR_HI+BTB_BTAG_SIZE+BTB_BTAG_SIZE+BTB_BTAG_SIZE:BTB_ADDR_HI+BTB_BTAG_SIZE+BTB_BTAG_SIZE+1] ^
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pc[BTB_ADDR_HI+BTB_BTAG_SIZE+BTB_BTAG_SIZE:BTB_ADDR_HI+BTB_BTAG_SIZE+1] ^
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pc[BTB_ADDR_HI+BTB_BTAG_SIZE:BTB_ADDR_HI+1])};
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endmodule
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module el2_btb_tag_hash_fold
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`include "parameter.sv"
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(
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input logic [BTB_ADDR_HI+BTB_BTAG_SIZE+BTB_BTAG_SIZE:BTB_ADDR_HI+1] pc,
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output logic [BTB_BTAG_SIZE-1:0] hash
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);
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assign hash = {(
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pc[BTB_ADDR_HI+BTB_BTAG_SIZE+BTB_BTAG_SIZE:BTB_ADDR_HI+BTB_BTAG_SIZE+1] ^
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pc[BTB_ADDR_HI+BTB_BTAG_SIZE:BTB_ADDR_HI+1])};
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endmodule
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module el2_btb_addr_hash
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`include "parameter.sv"
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(
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input logic [BTB_INDEX3_HI:BTB_INDEX1_LO] pc,
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output logic [BTB_ADDR_HI:BTB_ADDR_LO] hash
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);
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if(BTB_FOLD2_INDEX_HASH) begin : fold2
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assign hash[BTB_ADDR_HI:BTB_ADDR_LO] = pc[BTB_INDEX1_HI:BTB_INDEX1_LO] ^
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pc[BTB_INDEX3_HI:BTB_INDEX3_LO];
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end
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else begin
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assign hash[BTB_ADDR_HI:BTB_ADDR_LO] = pc[BTB_INDEX1_HI:BTB_INDEX1_LO] ^
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pc[BTB_INDEX2_HI:BTB_INDEX2_LO] ^
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pc[BTB_INDEX3_HI:BTB_INDEX3_LO];
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end
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endmodule
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module el2_btb_ghr_hash
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`include "parameter.sv"
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(
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input logic [BTB_ADDR_HI:BTB_ADDR_LO] hashin,
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input logic [BHT_GHR_SIZE-1:0] ghr,
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output logic [BHT_ADDR_HI:BHT_ADDR_LO] hash
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);
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// The hash function is too complex to write in verilog for all cases.
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// The config script generates the logic string based on the bp config.
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if(BHT_GHR_HASH_1) begin : ghrhash_cfg1
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assign hash[BHT_ADDR_HI:BHT_ADDR_LO] = { ghr[BHT_GHR_SIZE-1:BTB_INDEX1_HI-1], hashin[BTB_INDEX1_HI:2]^ghr[BTB_INDEX1_HI-2:0]};
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end
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else begin : ghrhash_cfg2
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assign hash[BHT_ADDR_HI:BHT_ADDR_LO] = { hashin[BHT_GHR_SIZE+1:2]^ghr[BHT_GHR_SIZE-1:0]};
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end
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endmodule
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