2020-09-07 16:27:29 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_bp_ctl :
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module el2_ifu_bp_ctl :
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input clock : Clock
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input reset : UInt<1>
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2020-09-24 13:58:56 +08:00
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output io : {flip clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<32>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<7>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<32>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<7>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>}
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2020-09-07 16:27:29 +08:00
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2020-09-24 13:58:56 +08:00
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io.ifu_bp_hit_taken_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 42:25]
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io.ifu_bp_btb_target_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 43:26]
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io.ifu_bp_inst_mask_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 44:25]
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io.ifu_bp_fghr_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 45:20]
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io.ifu_bp_way_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 46:19]
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io.ifu_bp_ret_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 47:19]
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io.ifu_bp_hist1_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 48:21]
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io.ifu_bp_hist0_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 49:21]
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io.ifu_bp_pc4_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 50:19]
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io.ifu_bp_valid_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 51:21]
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io.ifu_bp_poffset_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 52:23]
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wire leak_one_f : UInt<1>
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leak_one_f <= UInt<1>("h00")
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node _T = not(leak_one_f) @[el2_ifu_bp_ctl.scala 67:43]
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node exu_mp_valid = and(io.exu_mp_pkt.misp, _T) @[el2_ifu_bp_ctl.scala 67:41]
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wire fetch_rd_tag_p1_f : UInt<5>
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fetch_rd_tag_p1_f <= UInt<1>("h00")
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wire fetch_rd_tag_f : UInt<5>
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fetch_rd_tag_f <= UInt<1>("h00")
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wire bht_dir_f : UInt<2>
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bht_dir_f <= UInt<1>("h00")
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wire dec_tlu_error_wb : UInt<1>
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dec_tlu_error_wb <= UInt<1>("h00")
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wire btb_error_addr_wb : UInt<7>
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btb_error_addr_wb <= UInt<1>("h00")
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wire btb_bank0_rd_data_way0_f : UInt<22>
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btb_bank0_rd_data_way0_f <= UInt<1>("h00")
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wire btb_bank0_rd_data_way1_f : UInt<22>
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btb_bank0_rd_data_way1_f <= UInt<1>("h00")
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wire btb_bank0_rd_data_way0_p1_f : UInt<22>
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btb_bank0_rd_data_way0_p1_f <= UInt<1>("h00")
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wire btb_bank0_rd_data_way1_p1_f : UInt<22>
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btb_bank0_rd_data_way1_p1_f <= UInt<1>("h00")
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2020-09-25 15:15:14 +08:00
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wire eoc_mask : UInt<1>
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eoc_mask <= UInt<1>("h00")
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wire btb_lru_b0_f : UInt<256>
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btb_lru_b0_f <= UInt<1>("h00")
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2020-09-24 13:58:56 +08:00
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wire dec_tlu_way_wb : UInt<1>
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dec_tlu_way_wb <= UInt<1>("h00")
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node _T_1 = bits(io.ifc_fetch_addr_f, 9, 2) @[el2_lib.scala 182:12]
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node _T_2 = bits(io.ifc_fetch_addr_f, 17, 10) @[el2_lib.scala 182:46]
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node _T_3 = xor(_T_1, _T_2) @[el2_lib.scala 182:42]
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node _T_4 = bits(io.ifc_fetch_addr_f, 25, 18) @[el2_lib.scala 182:80]
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node btb_rd_addr_f = xor(_T_3, _T_4) @[el2_lib.scala 182:76]
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2020-09-25 15:15:14 +08:00
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node _T_5 = add(io.ifc_fetch_addr_f, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 106:45]
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node fetch_addr_p1_f = tail(_T_5, 1) @[el2_ifu_bp_ctl.scala 106:45]
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2020-09-24 13:58:56 +08:00
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node _T_6 = bits(fetch_addr_p1_f, 9, 2) @[el2_lib.scala 182:12]
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node _T_7 = bits(fetch_addr_p1_f, 17, 10) @[el2_lib.scala 182:46]
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node _T_8 = xor(_T_6, _T_7) @[el2_lib.scala 182:42]
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node _T_9 = bits(fetch_addr_p1_f, 25, 18) @[el2_lib.scala 182:80]
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node btb_rd_addr_p1_f = xor(_T_8, _T_9) @[el2_lib.scala 182:76]
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2020-09-25 15:15:14 +08:00
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node _T_10 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 111:33]
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node _T_11 = not(_T_10) @[el2_ifu_bp_ctl.scala 111:23]
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node _T_12 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 111:46]
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2020-09-24 13:58:56 +08:00
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node btb_sel_f = cat(_T_11, _T_12) @[Cat.scala 29:58]
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2020-09-25 15:15:14 +08:00
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node _T_13 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 114:46]
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node _T_14 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 114:70]
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node _T_15 = not(_T_14) @[el2_ifu_bp_ctl.scala 114:50]
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2020-09-24 13:58:56 +08:00
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node fetch_start_f = cat(_T_13, _T_15) @[Cat.scala 29:58]
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2020-09-25 15:15:14 +08:00
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node _T_16 = eq(btb_error_addr_wb, btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 117:72]
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node branch_error_collision_f = and(dec_tlu_error_wb, _T_16) @[el2_ifu_bp_ctl.scala 117:51]
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node _T_17 = eq(btb_error_addr_wb, btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 118:75]
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node branch_error_collision_p1_f = and(dec_tlu_error_wb, _T_17) @[el2_ifu_bp_ctl.scala 118:54]
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node branch_error_bank_conflict_f = and(branch_error_collision_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 121:63]
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node branch_error_bank_conflict_p1_f = and(branch_error_collision_p1_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 122:69]
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node _T_18 = eq(io.exu_mp_btag, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 125:46]
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node _T_19 = and(_T_18, exu_mp_valid) @[el2_ifu_bp_ctl.scala 125:66]
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node _T_20 = and(_T_19, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 125:81]
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node _T_21 = eq(io.exu_mp_index, btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 125:117]
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node fetch_mp_collision_f = and(_T_20, _T_21) @[el2_ifu_bp_ctl.scala 125:102]
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node _T_22 = eq(io.exu_mp_btag, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 126:49]
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node _T_23 = and(_T_22, exu_mp_valid) @[el2_ifu_bp_ctl.scala 126:72]
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node _T_24 = and(_T_23, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 126:87]
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node _T_25 = eq(io.exu_mp_index, btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 126:123]
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node fetch_mp_collision_p1_f = and(_T_24, _T_25) @[el2_ifu_bp_ctl.scala 126:108]
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reg leak_one_f_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 128:30]
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leak_one_f_d1 <= leak_one_f @[el2_ifu_bp_ctl.scala 128:30]
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reg dec_tlu_way_wb_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 129:33]
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dec_tlu_way_wb_f <= dec_tlu_way_wb @[el2_ifu_bp_ctl.scala 129:33]
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reg exu_mp_way_f : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 130:29]
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exu_mp_way_f <= io.exu_mp_pkt.way @[el2_ifu_bp_ctl.scala 130:29]
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reg exu_flush_final_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 131:35]
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exu_flush_final_d1 <= io.exu_flush_final @[el2_ifu_bp_ctl.scala 131:35]
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node _T_26 = and(io.dec_tlu_flush_leak_one_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 133:47]
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node _T_27 = and(leak_one_f_d1, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 133:93]
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node _T_28 = or(_T_26, _T_27) @[el2_ifu_bp_ctl.scala 133:76]
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leak_one_f <= _T_28 @[el2_ifu_bp_ctl.scala 133:14]
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node _T_29 = bits(btb_bank0_rd_data_way0_f, 0, 0) @[el2_ifu_bp_ctl.scala 136:50]
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node _T_30 = bits(btb_bank0_rd_data_way0_f, 21, 17) @[el2_ifu_bp_ctl.scala 136:82]
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node _T_31 = eq(_T_30, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 136:97]
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node _T_32 = and(_T_29, _T_31) @[el2_ifu_bp_ctl.scala 136:55]
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node _T_33 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 137:22]
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node _T_34 = not(_T_33) @[el2_ifu_bp_ctl.scala 137:3]
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node _T_35 = and(_T_32, _T_34) @[el2_ifu_bp_ctl.scala 136:117]
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node _T_36 = and(_T_35, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 137:54]
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node _T_37 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 137:77]
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node tag_match_way0_f = and(_T_36, _T_37) @[el2_ifu_bp_ctl.scala 137:75]
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node _T_38 = bits(btb_bank0_rd_data_way1_f, 0, 0) @[el2_ifu_bp_ctl.scala 139:50]
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node _T_39 = bits(btb_bank0_rd_data_way1_f, 21, 17) @[el2_ifu_bp_ctl.scala 139:82]
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node _T_40 = eq(_T_39, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 139:97]
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node _T_41 = and(_T_38, _T_40) @[el2_ifu_bp_ctl.scala 139:55]
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node _T_42 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 140:22]
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node _T_43 = not(_T_42) @[el2_ifu_bp_ctl.scala 140:3]
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node _T_44 = and(_T_41, _T_43) @[el2_ifu_bp_ctl.scala 139:117]
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node _T_45 = and(_T_44, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 140:54]
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node _T_46 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 140:77]
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node tag_match_way1_f = and(_T_45, _T_46) @[el2_ifu_bp_ctl.scala 140:75]
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node _T_47 = bits(btb_bank0_rd_data_way0_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 142:56]
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node _T_48 = bits(btb_bank0_rd_data_way0_p1_f, 21, 17) @[el2_ifu_bp_ctl.scala 142:91]
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node _T_49 = eq(_T_48, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 142:106]
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node _T_50 = and(_T_47, _T_49) @[el2_ifu_bp_ctl.scala 142:61]
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node _T_51 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 143:24]
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node _T_52 = not(_T_51) @[el2_ifu_bp_ctl.scala 143:5]
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node _T_53 = and(_T_50, _T_52) @[el2_ifu_bp_ctl.scala 142:129]
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node _T_54 = and(_T_53, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 143:56]
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node _T_55 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 143:79]
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node tag_match_way0_p1_f = and(_T_54, _T_55) @[el2_ifu_bp_ctl.scala 143:77]
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node _T_56 = bits(btb_bank0_rd_data_way1_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 145:56]
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node _T_57 = bits(btb_bank0_rd_data_way1_p1_f, 21, 17) @[el2_ifu_bp_ctl.scala 145:91]
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node _T_58 = eq(_T_57, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 145:106]
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node _T_59 = and(_T_56, _T_58) @[el2_ifu_bp_ctl.scala 145:61]
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node _T_60 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 146:24]
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node _T_61 = not(_T_60) @[el2_ifu_bp_ctl.scala 146:5]
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node _T_62 = and(_T_59, _T_61) @[el2_ifu_bp_ctl.scala 145:129]
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node _T_63 = and(_T_62, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 146:56]
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node _T_64 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 146:79]
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node tag_match_way1_p1_f = and(_T_63, _T_64) @[el2_ifu_bp_ctl.scala 146:77]
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node _T_65 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[el2_ifu_bp_ctl.scala 149:84]
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node _T_66 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[el2_ifu_bp_ctl.scala 149:117]
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node _T_67 = xor(_T_65, _T_66) @[el2_ifu_bp_ctl.scala 149:91]
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node _T_68 = and(tag_match_way0_f, _T_67) @[el2_ifu_bp_ctl.scala 149:56]
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node _T_69 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[el2_ifu_bp_ctl.scala 150:50]
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node _T_70 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[el2_ifu_bp_ctl.scala 150:83]
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node _T_71 = xor(_T_69, _T_70) @[el2_ifu_bp_ctl.scala 150:57]
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node _T_72 = not(_T_71) @[el2_ifu_bp_ctl.scala 150:24]
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node _T_73 = and(tag_match_way0_f, _T_72) @[el2_ifu_bp_ctl.scala 150:22]
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node tag_match_way0_expanded_f = cat(_T_68, _T_73) @[Cat.scala 29:58]
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node _T_74 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[el2_ifu_bp_ctl.scala 152:84]
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node _T_75 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[el2_ifu_bp_ctl.scala 152:117]
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node _T_76 = xor(_T_74, _T_75) @[el2_ifu_bp_ctl.scala 152:91]
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node _T_77 = and(tag_match_way1_f, _T_76) @[el2_ifu_bp_ctl.scala 152:56]
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node _T_78 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[el2_ifu_bp_ctl.scala 153:50]
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node _T_79 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[el2_ifu_bp_ctl.scala 153:83]
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node _T_80 = xor(_T_78, _T_79) @[el2_ifu_bp_ctl.scala 153:57]
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node _T_81 = not(_T_80) @[el2_ifu_bp_ctl.scala 153:24]
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node _T_82 = and(tag_match_way1_f, _T_81) @[el2_ifu_bp_ctl.scala 153:22]
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node tag_match_way1_expanded_f = cat(_T_77, _T_82) @[Cat.scala 29:58]
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node _T_83 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 156:93]
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node _T_84 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 156:129]
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node _T_85 = xor(_T_83, _T_84) @[el2_ifu_bp_ctl.scala 156:100]
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node _T_86 = and(tag_match_way0_p1_f, _T_85) @[el2_ifu_bp_ctl.scala 156:62]
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node _T_87 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 157:56]
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node _T_88 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 157:92]
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node _T_89 = xor(_T_87, _T_88) @[el2_ifu_bp_ctl.scala 157:63]
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node _T_90 = not(_T_89) @[el2_ifu_bp_ctl.scala 157:27]
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node _T_91 = and(tag_match_way0_p1_f, _T_90) @[el2_ifu_bp_ctl.scala 157:25]
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node tag_match_way0_expanded_p1_f = cat(_T_86, _T_91) @[Cat.scala 29:58]
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node _T_92 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 159:93]
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node _T_93 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 159:129]
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node _T_94 = xor(_T_92, _T_93) @[el2_ifu_bp_ctl.scala 159:100]
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node _T_95 = and(tag_match_way1_p1_f, _T_94) @[el2_ifu_bp_ctl.scala 159:62]
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node _T_96 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 160:56]
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node _T_97 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 160:92]
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node _T_98 = xor(_T_96, _T_97) @[el2_ifu_bp_ctl.scala 160:63]
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node _T_99 = not(_T_98) @[el2_ifu_bp_ctl.scala 160:27]
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node _T_100 = and(tag_match_way1_p1_f, _T_99) @[el2_ifu_bp_ctl.scala 160:25]
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node tag_match_way1_expanded_p1_f = cat(_T_95, _T_100) @[Cat.scala 29:58]
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node wayhit_f = or(tag_match_way0_expanded_f, tag_match_way1_expanded_f) @[el2_ifu_bp_ctl.scala 162:44]
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node wayhit_p1_f = or(tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f) @[el2_ifu_bp_ctl.scala 164:50]
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node _T_101 = bits(tag_match_way0_expanded_f, 0, 0) @[el2_ifu_bp_ctl.scala 167:65]
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node _T_102 = bits(_T_101, 0, 0) @[el2_ifu_bp_ctl.scala 167:69]
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node _T_103 = bits(tag_match_way1_expanded_f, 0, 0) @[el2_ifu_bp_ctl.scala 168:30]
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node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_bp_ctl.scala 168:34]
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node _T_105 = mux(_T_102, btb_bank0_rd_data_way0_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_106 = mux(_T_104, btb_bank0_rd_data_way1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_107 = or(_T_105, _T_106) @[Mux.scala 27:72]
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wire btb_bank0e_rd_data_f : UInt<22> @[Mux.scala 27:72]
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btb_bank0e_rd_data_f <= _T_107 @[Mux.scala 27:72]
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node _T_108 = bits(tag_match_way0_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 170:65]
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node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_bp_ctl.scala 170:69]
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node _T_110 = bits(tag_match_way1_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 171:30]
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node _T_111 = bits(_T_110, 0, 0) @[el2_ifu_bp_ctl.scala 171:34]
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node _T_112 = mux(_T_109, btb_bank0_rd_data_way0_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_113 = mux(_T_111, btb_bank0_rd_data_way1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_114 = or(_T_112, _T_113) @[Mux.scala 27:72]
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wire btb_bank0o_rd_data_f : UInt<22> @[Mux.scala 27:72]
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btb_bank0o_rd_data_f <= _T_114 @[Mux.scala 27:72]
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node _T_115 = bits(tag_match_way0_expanded_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 173:71]
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node _T_116 = bits(_T_115, 0, 0) @[el2_ifu_bp_ctl.scala 173:75]
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node _T_117 = bits(tag_match_way1_expanded_p1_f, 1, 1) @[el2_ifu_bp_ctl.scala 174:33]
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node _T_118 = bits(_T_117, 0, 0) @[el2_ifu_bp_ctl.scala 174:37]
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node _T_119 = mux(_T_116, btb_bank0_rd_data_way0_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_120 = mux(_T_118, btb_bank0_rd_data_way1_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_121 = or(_T_119, _T_120) @[Mux.scala 27:72]
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wire btb_bank0e_rd_data_p1_f : UInt<22> @[Mux.scala 27:72]
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btb_bank0e_rd_data_p1_f <= _T_121 @[Mux.scala 27:72]
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node _T_122 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 177:60]
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node _T_123 = not(_T_122) @[el2_ifu_bp_ctl.scala 177:40]
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node _T_124 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 178:24]
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node _T_125 = mux(_T_123, btb_bank0e_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_126 = mux(_T_124, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_127 = or(_T_125, _T_126) @[Mux.scala 27:72]
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wire btb_vbank0_rd_data_f : UInt<22> @[Mux.scala 27:72]
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btb_vbank0_rd_data_f <= _T_127 @[Mux.scala 27:72]
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node _T_128 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_bp_ctl.scala 180:60]
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node _T_129 = not(_T_128) @[el2_ifu_bp_ctl.scala 180:40]
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node _T_130 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_bp_ctl.scala 181:24]
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node _T_131 = mux(_T_129, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_132 = mux(_T_130, btb_bank0e_rd_data_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_133 = or(_T_131, _T_132) @[Mux.scala 27:72]
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wire btb_vbank1_rd_data_f : UInt<22> @[Mux.scala 27:72]
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btb_vbank1_rd_data_f <= _T_133 @[Mux.scala 27:72]
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node mp_wrindex_dec = dshl(UInt<1>("h00"), io.exu_mp_index) @[el2_ifu_bp_ctl.scala 184:38]
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node fetch_wrindex_dec = dshl(UInt<1>("h00"), btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 185:41]
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node fetch_wrindex_p1_dec = dshl(UInt<1>("h00"), btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 186:44]
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node _T_134 = bits(exu_mp_valid, 0, 0) @[Bitwise.scala 72:15]
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node _T_135 = mux(_T_134, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
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node mp_wrlru_b0 = and(mp_wrindex_dec, _T_135) @[el2_ifu_bp_ctl.scala 187:36]
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node _T_136 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 189:49]
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node _T_137 = bits(_T_136, 0, 0) @[el2_ifu_bp_ctl.scala 189:53]
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node _T_138 = not(_T_137) @[el2_ifu_bp_ctl.scala 189:29]
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node _T_139 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 190:24]
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node _T_140 = bits(_T_139, 0, 0) @[el2_ifu_bp_ctl.scala 190:28]
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node _T_141 = bits(wayhit_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 190:51]
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node _T_142 = bits(wayhit_f, 1, 1) @[el2_ifu_bp_ctl.scala 190:64]
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node _T_143 = cat(_T_141, _T_142) @[Cat.scala 29:58]
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node _T_144 = mux(_T_138, wayhit_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_145 = mux(_T_140, _T_143, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_146 = or(_T_144, _T_145) @[Mux.scala 27:72]
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wire _T_147 : UInt<2> @[Mux.scala 27:72]
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_T_147 <= _T_146 @[Mux.scala 27:72]
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node _T_148 = cat(eoc_mask, UInt<1>("h01")) @[Cat.scala 29:58]
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node vwayhit_f = and(_T_147, _T_148) @[el2_ifu_bp_ctl.scala 190:71]
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node _T_149 = bits(vwayhit_f, 0, 0) @[el2_ifu_bp_ctl.scala 191:38]
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node _T_150 = bits(vwayhit_f, 1, 1) @[el2_ifu_bp_ctl.scala 191:53]
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node _T_151 = or(_T_149, _T_150) @[el2_ifu_bp_ctl.scala 191:42]
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node _T_152 = and(_T_151, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 191:58]
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node _T_153 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 191:81]
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node lru_update_valid_f = and(_T_152, _T_153) @[el2_ifu_bp_ctl.scala 191:79]
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node _T_154 = bits(lru_update_valid_f, 0, 0) @[Bitwise.scala 72:15]
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node _T_155 = mux(_T_154, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
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node fetch_wrlru_b0 = and(fetch_wrindex_dec, _T_155) @[el2_ifu_bp_ctl.scala 193:42]
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node _T_156 = bits(lru_update_valid_f, 0, 0) @[Bitwise.scala 72:15]
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node _T_157 = mux(_T_156, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
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node fetch_wrlru_p1_b0 = and(fetch_wrindex_p1_dec, _T_157) @[el2_ifu_bp_ctl.scala 194:48]
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node _T_158 = not(mp_wrlru_b0) @[el2_ifu_bp_ctl.scala 196:25]
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node _T_159 = not(fetch_wrlru_b0) @[el2_ifu_bp_ctl.scala 196:40]
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node btb_lru_b0_hold = and(_T_158, _T_159) @[el2_ifu_bp_ctl.scala 196:38]
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node _T_160 = bits(io.exu_mp_pkt.way, 0, 0) @[el2_ifu_bp_ctl.scala 200:45]
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node _T_161 = not(_T_160) @[el2_ifu_bp_ctl.scala 200:33]
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node _T_162 = bits(tag_match_way0_f, 0, 0) @[el2_ifu_bp_ctl.scala 201:22]
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node _T_163 = bits(tag_match_way0_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 201:65]
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node _T_164 = mux(_T_161, mp_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_165 = mux(_T_162, fetch_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_166 = mux(_T_163, fetch_wrlru_p1_b0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_167 = or(_T_164, _T_165) @[Mux.scala 27:72]
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node _T_168 = or(_T_167, _T_166) @[Mux.scala 27:72]
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wire _T_169 : UInt<256> @[Mux.scala 27:72]
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_T_169 <= _T_168 @[Mux.scala 27:72]
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node _T_170 = and(btb_lru_b0_hold, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 201:111]
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node btb_lru_b0_ns = or(_T_169, _T_170) @[el2_ifu_bp_ctl.scala 201:93]
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node _T_171 = bits(fetch_mp_collision_f, 0, 0) @[el2_ifu_bp_ctl.scala 203:37]
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node _T_172 = and(fetch_wrindex_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 203:78]
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node _T_173 = orr(_T_172) @[el2_ifu_bp_ctl.scala 203:94]
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node btb_lru_rd_f = mux(_T_171, exu_mp_way_f, _T_173) @[el2_ifu_bp_ctl.scala 203:25]
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node _T_174 = bits(fetch_mp_collision_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 204:43]
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node _T_175 = and(fetch_wrindex_p1_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 204:87]
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node _T_176 = orr(_T_175) @[el2_ifu_bp_ctl.scala 204:103]
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node btb_lru_rd_p1_f = mux(_T_174, exu_mp_way_f, _T_176) @[el2_ifu_bp_ctl.scala 204:28]
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node _T_177 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 206:53]
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node _T_178 = bits(_T_177, 0, 0) @[el2_ifu_bp_ctl.scala 206:57]
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node _T_179 = not(_T_178) @[el2_ifu_bp_ctl.scala 206:33]
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node _T_180 = cat(btb_lru_rd_f, btb_lru_rd_f) @[Cat.scala 29:58]
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node _T_181 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 207:24]
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node _T_182 = bits(_T_181, 0, 0) @[el2_ifu_bp_ctl.scala 207:28]
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node _T_183 = cat(btb_lru_rd_p1_f, btb_lru_rd_f) @[Cat.scala 29:58]
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node _T_184 = mux(_T_179, _T_180, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_185 = mux(_T_182, _T_183, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_186 = or(_T_184, _T_185) @[Mux.scala 27:72]
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wire btb_vlru_rd_f : UInt @[Mux.scala 27:72]
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btb_vlru_rd_f <= _T_186 @[Mux.scala 27:72]
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2020-09-07 16:27:29 +08:00
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