quasar/el2_ifu_mem_ctl.fir

;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_mem_ctl : 
  module el2_ifu_mem_ctl : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, ifu_miss_state_idle : UInt<1>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, flip ifu_fetch_val : UInt<2>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, iccm_rd_ecc_single_err : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, ic_error_start : UInt<1>, ifu_async_error_start : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>}
    
    io.ic_debug_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 126:20]
    io.ic_debug_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 127:20]
    io.ic_debug_tag_array <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 128:24]
    io.ifu_miss_state_idle <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 129:25]
    io.ifu_ic_mb_empty <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 130:21]
    io.ic_dma_active <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 131:19]
    io.ic_write_stall <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 132:20]
    io.ifu_pmu_ic_miss <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 133:21]
    io.ifu_pmu_ic_hit <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 134:20]
    io.ifu_pmu_bus_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 135:23]
    io.ifu_pmu_bus_busy <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 136:22]
    io.ifu_pmu_bus_trxn <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 137:22]
    io.ifu_axi_awvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 138:21]
    io.ifu_axi_awid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 139:18]
    io.ifu_axi_awaddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 140:20]
    io.ifu_axi_awlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 141:19]
    io.ifu_axi_awsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 142:20]
    io.ifu_axi_awburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 143:21]
    io.ifu_axi_awlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 144:20]
    io.ifu_axi_awcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 145:21]
    io.ifu_axi_awprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 146:20]
    io.ifu_axi_awqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 147:19]
    io.ifu_axi_wvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 148:20]
    io.ifu_axi_wdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 149:19]
    io.ifu_axi_wstrb <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 150:19]
    io.ifu_axi_wlast <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 151:19]
    io.ifu_axi_bready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 152:20]
    io.ifu_axi_arvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 153:21]
    io.ic_debug_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 154:19]
    io.ifu_axi_arid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 155:18]
    io.ifu_axi_araddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 156:20]
    io.ifu_axi_arregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 157:22]
    io.ifu_axi_arlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 158:19]
    io.ifu_axi_arsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 159:20]
    io.ifu_axi_arburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 160:21]
    io.ifu_axi_arlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 161:20]
    io.ifu_axi_arcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 162:21]
    io.ifu_axi_arprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 163:20]
    io.ifu_axi_arqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 164:19]
    io.ifu_axi_rready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 165:20]
    io.iccm_dma_ecc_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 166:24]
    io.iccm_dma_rvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 167:21]
    io.iccm_dma_rdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 168:20]
    io.iccm_dma_rtag <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 169:19]
    io.iccm_ready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 170:16]
    io.ic_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 171:16]
    io.ic_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 172:14]
    io.ic_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 173:14]
    io.ic_wr_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 174:16]
    io.ic_wr_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 174:16]
    io.ic_debug_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 175:22]
    io.ifu_ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 176:26]
    io.ic_tag_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 177:18]
    io.iccm_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 178:18]
    io.iccm_wren <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 179:15]
    io.iccm_rden <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 180:15]
    io.iccm_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 181:18]
    io.iccm_wr_size <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 182:18]
    io.ic_hit_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 183:14]
    io.ic_access_fault_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 184:23]
    io.ic_access_fault_type_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 185:28]
    io.iccm_rd_ecc_single_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 186:28]
    io.iccm_rd_ecc_double_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 187:28]
    io.ic_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 188:20]
    io.ifu_async_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 189:27]
    io.iccm_dma_sb_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 190:23]
    io.ic_fetch_val_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 191:20]
    io.ic_data_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 192:15]
    io.ic_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 193:20]
    io.ic_sel_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 194:24]
    io.ifu_ic_debug_rd_data_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 195:32]
    io.iccm_buf_correct_ecc <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 196:26]
    io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 197:27]
    io.ic_debug_way <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 198:18]
    io.ifu_axi_awregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 199:22]