quasar/target/scala-2.12/classes/vsrc/gated_latch.v

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2020-12-10 15:52:23 +08:00
module gated_latch
(
input wire SE, EN, CK,
output Q
);
reg en_ff;
wire enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule