2020-09-30 18:29:09 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_ifc_ctl :
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module el2_ifu_ifc_ctl :
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input clock : Clock
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input reset : AsyncReset
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2020-10-01 14:41:24 +08:00
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output io : {flip free_clk : Clock, flip active_clk : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
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2020-09-30 18:29:09 +08:00
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2020-10-01 01:28:23 +08:00
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wire fetch_addr_bf : UInt<31>
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2020-09-30 18:29:09 +08:00
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fetch_addr_bf <= UInt<1>("h00")
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2020-10-01 01:28:23 +08:00
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wire fetch_addr_next_0 : UInt<1>
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fetch_addr_next_0 <= UInt<1>("h00")
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wire fetch_addr_next : UInt<31>
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2020-09-30 18:29:09 +08:00
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fetch_addr_next <= UInt<1>("h00")
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wire fb_write_ns : UInt<4>
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fb_write_ns <= UInt<1>("h00")
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wire fb_write_f : UInt<4>
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fb_write_f <= UInt<1>("h00")
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wire fb_full_f_ns : UInt<1>
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fb_full_f_ns <= UInt<1>("h00")
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wire fb_right : UInt<1>
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fb_right <= UInt<1>("h00")
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wire fb_right2 : UInt<1>
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fb_right2 <= UInt<1>("h00")
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wire fb_left : UInt<1>
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fb_left <= UInt<1>("h00")
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wire wfm : UInt<1>
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wfm <= UInt<1>("h00")
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wire idle : UInt<1>
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idle <= UInt<1>("h00")
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wire miss_f : UInt<1>
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miss_f <= UInt<1>("h00")
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wire miss_a : UInt<1>
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miss_a <= UInt<1>("h00")
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wire flush_fb : UInt<1>
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flush_fb <= UInt<1>("h00")
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wire mb_empty_mod : UInt<1>
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mb_empty_mod <= UInt<1>("h00")
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wire goto_idle : UInt<1>
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goto_idle <= UInt<1>("h00")
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wire leave_idle : UInt<1>
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leave_idle <= UInt<1>("h00")
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wire fetch_bf_en : UInt<1>
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fetch_bf_en <= UInt<1>("h00")
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wire line_wrap : UInt<1>
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line_wrap <= UInt<1>("h00")
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wire state : UInt<2>
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state <= UInt<1>("h00")
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wire dma_iccm_stall_any_f : UInt<1>
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dma_iccm_stall_any_f <= UInt<1>("h00")
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2020-10-01 14:41:24 +08:00
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node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 62:36]
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reg _T : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 63:58]
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_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctl.scala 63:58]
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dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctl.scala 63:24]
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reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 65:44]
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_T_1 <= miss_f @[el2_ifu_ifc_ctl.scala 65:44]
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miss_a <= _T_1 @[el2_ifu_ifc_ctl.scala 65:10]
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node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:26]
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node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:49]
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node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 67:71]
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node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctl.scala 67:69]
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node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctl.scala 67:46]
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node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 68:26]
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node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 68:46]
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node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctl.scala 68:67]
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node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 68:92]
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node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:26]
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node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 69:46]
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node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 69:69]
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node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctl.scala 69:67]
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node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctl.scala 69:92]
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node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctl.scala 72:56]
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node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 73:22]
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node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 74:21]
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node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctl.scala 75:22]
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2020-09-30 18:29:09 +08:00
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node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_20 = mux(_T_16, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
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node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
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node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
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2020-10-01 01:28:23 +08:00
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wire _T_24 : UInt<31> @[Mux.scala 27:72]
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2020-09-30 18:29:09 +08:00
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_T_24 <= _T_23 @[Mux.scala 27:72]
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2020-10-01 14:41:24 +08:00
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io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctl.scala 72:24]
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node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42]
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node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48]
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node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48]
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2020-10-01 21:31:31 +08:00
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node _T_27 = bits(address_upper, 5, 5) @[el2_ifu_ifc_ctl.scala 78:38]
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node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:83]
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node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:62]
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node _T_30 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:129]
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node _T_31 = and(_T_29, _T_30) @[el2_ifu_ifc_ctl.scala 78:108]
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fetch_addr_next_0 <= _T_31 @[el2_ifu_ifc_ctl.scala 78:21]
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node _T_32 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
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fetch_addr_next <= _T_32 @[el2_ifu_ifc_ctl.scala 80:19]
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node _T_33 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
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io.ifc_fetch_req_bf_raw <= _T_33 @[el2_ifu_ifc_ctl.scala 82:27]
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node _T_34 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
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node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
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node _T_36 = and(fb_full_f_ns, _T_35) @[el2_ifu_ifc_ctl.scala 84:68]
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node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
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node _T_38 = and(io.ifc_fetch_req_bf_raw, _T_37) @[el2_ifu_ifc_ctl.scala 84:51]
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node _T_39 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
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node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctl.scala 84:114]
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node _T_41 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
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node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctl.scala 85:16]
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node _T_43 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
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node _T_44 = and(_T_42, _T_43) @[el2_ifu_ifc_ctl.scala 85:37]
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io.ifc_fetch_req_bf <= _T_44 @[el2_ifu_ifc_ctl.scala 84:23]
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node _T_45 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
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fetch_bf_en <= _T_45 @[el2_ifu_ifc_ctl.scala 87:15]
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node _T_46 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
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node _T_47 = and(io.ifc_fetch_req_f, _T_46) @[el2_ifu_ifc_ctl.scala 89:32]
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node _T_48 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
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node _T_49 = and(_T_47, _T_48) @[el2_ifu_ifc_ctl.scala 89:47]
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miss_f <= _T_49 @[el2_ifu_ifc_ctl.scala 89:10]
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node _T_50 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
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node _T_51 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
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node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctl.scala 91:61]
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node _T_53 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
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node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctl.scala 91:74]
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node _T_55 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
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node _T_56 = and(_T_54, _T_55) @[el2_ifu_ifc_ctl.scala 91:84]
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mb_empty_mod <= _T_56 @[el2_ifu_ifc_ctl.scala 91:16]
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node _T_57 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
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goto_idle <= _T_57 @[el2_ifu_ifc_ctl.scala 93:13]
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node _T_58 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
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node _T_59 = and(io.exu_flush_final, _T_58) @[el2_ifu_ifc_ctl.scala 95:36]
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node _T_60 = and(_T_59, idle) @[el2_ifu_ifc_ctl.scala 95:67]
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leave_idle <= _T_60 @[el2_ifu_ifc_ctl.scala 95:14]
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node _T_61 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
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node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
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node _T_63 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
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node _T_64 = and(_T_62, _T_63) @[el2_ifu_ifc_ctl.scala 97:33]
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node _T_65 = and(_T_64, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
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node _T_66 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
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node _T_67 = and(_T_65, _T_66) @[el2_ifu_ifc_ctl.scala 97:53]
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node _T_68 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
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node _T_69 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
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node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctl.scala 98:15]
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node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
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node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctl.scala 98:31]
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node next_state_1 = or(_T_67, _T_72) @[el2_ifu_ifc_ctl.scala 97:67]
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node _T_73 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
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node _T_74 = and(_T_73, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
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node _T_75 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
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node _T_76 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
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node _T_77 = and(_T_75, _T_76) @[el2_ifu_ifc_ctl.scala 100:60]
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node next_state_0 = or(_T_74, _T_77) @[el2_ifu_ifc_ctl.scala 100:48]
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node _T_78 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
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reg _T_79 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:19]
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_T_79 <= _T_78 @[el2_ifu_ifc_ctl.scala 102:19]
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state <= _T_79 @[el2_ifu_ifc_ctl.scala 102:9]
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2020-10-01 14:41:24 +08:00
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flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 104:12]
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2020-10-01 21:31:31 +08:00
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node _T_80 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
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node _T_81 = and(io.ifu_fb_consume1, _T_80) @[el2_ifu_ifc_ctl.scala 106:36]
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node _T_82 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
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node _T_83 = or(_T_82, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
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node _T_84 = and(_T_81, _T_83) @[el2_ifu_ifc_ctl.scala 106:58]
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node _T_85 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
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node _T_86 = or(_T_84, _T_85) @[el2_ifu_ifc_ctl.scala 106:92]
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fb_right <= _T_86 @[el2_ifu_ifc_ctl.scala 106:12]
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node _T_87 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
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node _T_88 = or(_T_87, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
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node _T_89 = and(io.ifu_fb_consume2, _T_88) @[el2_ifu_ifc_ctl.scala 109:36]
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fb_right2 <= _T_89 @[el2_ifu_ifc_ctl.scala 109:13]
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node _T_90 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
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node _T_91 = eq(_T_90, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
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node _T_92 = and(io.ifc_fetch_req_f, _T_91) @[el2_ifu_ifc_ctl.scala 110:33]
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node _T_93 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
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node _T_94 = and(_T_92, _T_93) @[el2_ifu_ifc_ctl.scala 110:78]
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fb_left <= _T_94 @[el2_ifu_ifc_ctl.scala 110:11]
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node _T_95 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
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node _T_96 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
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node _T_97 = and(_T_96, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
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node _T_98 = bits(_T_97, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
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node _T_99 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
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node _T_100 = cat(UInt<1>("h00"), _T_99) @[Cat.scala 29:58]
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node _T_101 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
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node _T_102 = and(_T_101, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
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node _T_103 = bits(_T_102, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
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node _T_104 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
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node _T_105 = cat(UInt<2>("h00"), _T_104) @[Cat.scala 29:58]
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node _T_106 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
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node _T_107 = and(_T_106, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
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node _T_108 = bits(_T_107, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
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node _T_109 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
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node _T_110 = cat(_T_109, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_111 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
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node _T_112 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
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node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctl.scala 116:16]
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node _T_114 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
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node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctl.scala 116:28]
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node _T_116 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
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node _T_117 = and(_T_115, _T_116) @[el2_ifu_ifc_ctl.scala 116:41]
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node _T_118 = bits(_T_117, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
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node _T_119 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
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node _T_120 = mux(_T_95, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_121 = mux(_T_98, _T_100, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_122 = mux(_T_103, _T_105, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_123 = mux(_T_108, _T_110, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_124 = mux(_T_118, _T_119, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_125 = or(_T_120, _T_121) @[Mux.scala 27:72]
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node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
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2020-10-01 01:28:23 +08:00
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node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
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node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
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2020-10-01 21:31:31 +08:00
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wire _T_129 : UInt<4> @[Mux.scala 27:72]
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_T_129 <= _T_128 @[Mux.scala 27:72]
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fb_write_ns <= _T_129 @[el2_ifu_ifc_ctl.scala 112:15]
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node _T_130 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 119:38]
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reg _T_131 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 119:26]
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_T_131 <= _T_130 @[el2_ifu_ifc_ctl.scala 119:26]
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fb_full_f_ns <= _T_131 @[el2_ifu_ifc_ctl.scala 119:16]
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node _T_132 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 121:17]
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idle <= _T_132 @[el2_ifu_ifc_ctl.scala 121:8]
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node _T_133 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 122:16]
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wfm <= _T_133 @[el2_ifu_ifc_ctl.scala 122:7]
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node _T_134 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 124:30]
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fb_full_f_ns <= _T_134 @[el2_ifu_ifc_ctl.scala 124:16]
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2020-10-01 14:41:24 +08:00
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reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 125:26]
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fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 125:26]
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2020-10-01 21:31:31 +08:00
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reg _T_135 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:24]
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_T_135 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 126:24]
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fb_write_f <= _T_135 @[el2_ifu_ifc_ctl.scala 126:14]
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node _T_136 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 129:40]
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node _T_137 = or(_T_136, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 129:61]
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node _T_138 = eq(_T_137, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 129:19]
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node _T_139 = and(fb_full_f, _T_138) @[el2_ifu_ifc_ctl.scala 129:17]
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node _T_140 = or(_T_139, dma_stall) @[el2_ifu_ifc_ctl.scala 129:84]
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node _T_141 = and(io.ifc_fetch_req_bf_raw, _T_140) @[el2_ifu_ifc_ctl.scala 128:60]
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node _T_142 = or(wfm, _T_141) @[el2_ifu_ifc_ctl.scala 128:33]
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io.ifu_pmu_fetch_stall <= _T_142 @[el2_ifu_ifc_ctl.scala 128:26]
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node _T_143 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_144 = bits(_T_143, 31, 28) @[el2_lib.scala 211:25]
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node iccm_acc_in_region_bf = eq(_T_144, UInt<4>("h0e")) @[el2_lib.scala 211:47]
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node _T_145 = bits(_T_143, 31, 16) @[el2_lib.scala 214:14]
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node iccm_acc_in_range_bf = eq(_T_145, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
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2020-10-01 14:41:24 +08:00
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io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 134:25]
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2020-10-01 21:31:31 +08:00
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node _T_146 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:30]
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node _T_147 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 136:39]
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node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:18]
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node _T_149 = and(fb_full_f, _T_148) @[el2_ifu_ifc_ctl.scala 136:16]
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node _T_150 = or(_T_146, _T_149) @[el2_ifu_ifc_ctl.scala 135:53]
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node _T_151 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:13]
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node _T_152 = and(wfm, _T_151) @[el2_ifu_ifc_ctl.scala 137:11]
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node _T_153 = or(_T_150, _T_152) @[el2_ifu_ifc_ctl.scala 136:62]
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node _T_154 = or(_T_153, idle) @[el2_ifu_ifc_ctl.scala 137:35]
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node _T_155 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:46]
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node _T_156 = and(_T_154, _T_155) @[el2_ifu_ifc_ctl.scala 137:44]
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node _T_157 = or(_T_156, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 137:67]
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io.ifc_dma_access_ok <= _T_157 @[el2_ifu_ifc_ctl.scala 135:24]
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node _T_158 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 139:33]
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node _T_159 = and(_T_158, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 139:55]
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io.ifc_region_acc_fault_bf <= _T_159 @[el2_ifu_ifc_ctl.scala 139:30]
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node _T_160 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 140:78]
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node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_162 = dshr(io.dec_tlu_mrac_ff, _T_161) @[el2_ifu_ifc_ctl.scala 140:53]
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node _T_163 = bits(_T_162, 0, 0) @[el2_ifu_ifc_ctl.scala 140:53]
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node _T_164 = not(_T_163) @[el2_ifu_ifc_ctl.scala 140:34]
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io.ifc_fetch_uncacheable_bf <= _T_164 @[el2_ifu_ifc_ctl.scala 140:31]
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reg _T_165 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 142:32]
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_T_165 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 142:32]
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io.ifc_fetch_req_f <= _T_165 @[el2_ifu_ifc_ctl.scala 142:22]
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node _T_166 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 144:88]
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reg _T_167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_166 : @[Reg.scala 28:19]
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_T_167 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
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2020-09-30 18:29:09 +08:00
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skip @[Reg.scala 28:19]
|
2020-10-01 21:31:31 +08:00
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io.ifc_fetch_addr_f <= _T_167 @[el2_ifu_ifc_ctl.scala 144:23]
|
2020-09-30 18:29:09 +08:00
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