2020-12-10 18:52:32 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit dbg :
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch @[lib.scala 318:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 319:14]
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clkhdr.CK <= io.clk @[lib.scala 320:18]
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clkhdr.EN <= io.en @[lib.scala 321:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
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extmodule gated_latch_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_1 @[lib.scala 318:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 319:14]
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clkhdr.CK <= io.clk @[lib.scala 320:18]
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clkhdr.EN <= io.en @[lib.scala 321:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
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extmodule gated_latch_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_2 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_2 @[lib.scala 318:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 319:14]
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clkhdr.CK <= io.clk @[lib.scala 320:18]
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clkhdr.EN <= io.en @[lib.scala 321:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
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extmodule gated_latch_3 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_3 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_3 @[lib.scala 318:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 319:14]
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clkhdr.CK <= io.clk @[lib.scala 320:18]
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clkhdr.EN <= io.en @[lib.scala 321:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
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extmodule gated_latch_4 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_4 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_4 @[lib.scala 318:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 319:14]
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clkhdr.CK <= io.clk @[lib.scala 320:18]
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clkhdr.EN <= io.en @[lib.scala 321:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
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extmodule gated_latch_5 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_5 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_5 @[lib.scala 318:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[lib.scala 319:14]
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clkhdr.CK <= io.clk @[lib.scala 320:18]
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clkhdr.EN <= io.en @[lib.scala 321:18]
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clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
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module dbg :
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input clock : Clock
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input reset : AsyncReset
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2020-12-10 19:59:28 +08:00
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output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<32>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>}
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2020-12-10 18:52:32 +08:00
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wire dbg_state : UInt<3>
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dbg_state <= UInt<3>("h00")
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wire dbg_state_en : UInt<1>
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dbg_state_en <= UInt<1>("h00")
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wire sb_state : UInt<4>
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sb_state <= UInt<4>("h00")
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wire sb_state_en : UInt<1>
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sb_state_en <= UInt<1>("h00")
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wire dmcontrol_reg : UInt<32>
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dmcontrol_reg <= UInt<32>("h00")
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wire sbaddress0_reg : UInt<32>
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sbaddress0_reg <= UInt<32>("h00")
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wire sbcs_sbbusy_wren : UInt<1>
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sbcs_sbbusy_wren <= UInt<1>("h00")
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wire sbcs_sberror_wren : UInt<1>
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sbcs_sberror_wren <= UInt<1>("h00")
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wire sb_bus_rdata : UInt<64>
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sb_bus_rdata <= UInt<64>("h00")
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wire sbaddress0_reg_wren1 : UInt<1>
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sbaddress0_reg_wren1 <= UInt<1>("h00")
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wire dmstatus_reg : UInt<32>
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dmstatus_reg <= UInt<32>("h00")
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wire dmstatus_havereset : UInt<1>
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dmstatus_havereset <= UInt<1>("h00")
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wire dmstatus_resumeack : UInt<1>
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dmstatus_resumeack <= UInt<1>("h00")
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wire dmstatus_unavail : UInt<1>
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dmstatus_unavail <= UInt<1>("h00")
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wire dmstatus_running : UInt<1>
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dmstatus_running <= UInt<1>("h00")
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wire dmstatus_halted : UInt<1>
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dmstatus_halted <= UInt<1>("h00")
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wire abstractcs_busy_wren : UInt<1>
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abstractcs_busy_wren <= UInt<1>("h00")
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wire abstractcs_busy_din : UInt<1>
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abstractcs_busy_din <= UInt<1>("h00")
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wire sb_bus_cmd_read : UInt<1>
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sb_bus_cmd_read <= UInt<1>("h00")
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wire sb_bus_cmd_write_addr : UInt<1>
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sb_bus_cmd_write_addr <= UInt<1>("h00")
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wire sb_bus_cmd_write_data : UInt<1>
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sb_bus_cmd_write_data <= UInt<1>("h00")
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wire sb_bus_rsp_read : UInt<1>
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sb_bus_rsp_read <= UInt<1>("h00")
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wire sb_bus_rsp_error : UInt<1>
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sb_bus_rsp_error <= UInt<1>("h00")
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wire sb_bus_rsp_write : UInt<1>
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sb_bus_rsp_write <= UInt<1>("h00")
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wire sbcs_sbbusy_din : UInt<1>
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sbcs_sbbusy_din <= UInt<1>("h00")
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wire sbcs_sberror_din : UInt<3>
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sbcs_sberror_din <= UInt<3>("h00")
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wire data1_reg : UInt<32>
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data1_reg <= UInt<32>("h00")
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wire sbcs_reg : UInt<32>
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sbcs_reg <= UInt<32>("h00")
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node _T = neq(dbg_state, UInt<3>("h00")) @[dbg.scala 95:51]
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node _T_1 = or(io.dmi_reg_en, _T) @[dbg.scala 95:38]
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node _T_2 = or(_T_1, dbg_state_en) @[dbg.scala 95:69]
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node _T_3 = or(_T_2, io.dec_tlu_dbg_halted) @[dbg.scala 95:84]
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node dbg_free_clken = or(_T_3, io.clk_override) @[dbg.scala 95:108]
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node _T_4 = or(io.dmi_reg_en, sb_state_en) @[dbg.scala 96:37]
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node _T_5 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 96:63]
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node _T_6 = or(_T_4, _T_5) @[dbg.scala 96:51]
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node sb_free_clken = or(_T_6, io.clk_override) @[dbg.scala 96:86]
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inst rvclkhdr of rvclkhdr @[lib.scala 327:22]
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rvclkhdr.clock <= clock
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rvclkhdr.reset <= reset
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rvclkhdr.io.clk <= clock @[lib.scala 328:17]
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rvclkhdr.io.en <= dbg_free_clken @[lib.scala 329:16]
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rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
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inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 327:22]
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rvclkhdr_1.clock <= clock
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rvclkhdr_1.reset <= reset
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rvclkhdr_1.io.clk <= clock @[lib.scala 328:17]
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rvclkhdr_1.io.en <= sb_free_clken @[lib.scala 329:16]
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rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
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node _T_7 = bits(io.dbg_rst_l, 0, 0) @[dbg.scala 99:41]
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node _T_8 = bits(dmcontrol_reg, 0, 0) @[dbg.scala 99:60]
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node _T_9 = or(_T_8, io.scan_mode) @[dbg.scala 99:64]
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node dbg_dm_rst_l = and(_T_7, _T_9) @[dbg.scala 99:44]
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node _T_10 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 100:39]
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node _T_11 = eq(_T_10, UInt<1>("h00")) @[dbg.scala 100:25]
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node _T_12 = bits(_T_11, 0, 0) @[dbg.scala 100:50]
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io.dbg_core_rst_l <= _T_12 @[dbg.scala 100:21]
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node _T_13 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 101:36]
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node _T_14 = and(_T_13, io.dmi_reg_en) @[dbg.scala 101:49]
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node _T_15 = and(_T_14, io.dmi_reg_wr_en) @[dbg.scala 101:65]
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node _T_16 = eq(sb_state, UInt<4>("h00")) @[dbg.scala 101:96]
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node sbcs_wren = and(_T_15, _T_16) @[dbg.scala 101:84]
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node _T_17 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 102:60]
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node _T_18 = and(sbcs_wren, _T_17) @[dbg.scala 102:42]
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node _T_19 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 102:79]
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node _T_20 = and(_T_19, io.dmi_reg_en) @[dbg.scala 102:102]
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node _T_21 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 103:23]
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node _T_22 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 103:55]
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node _T_23 = or(_T_21, _T_22) @[dbg.scala 103:36]
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node _T_24 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 103:87]
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node _T_25 = or(_T_23, _T_24) @[dbg.scala 103:68]
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node _T_26 = and(_T_20, _T_25) @[dbg.scala 102:118]
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node sbcs_sbbusyerror_wren = or(_T_18, _T_26) @[dbg.scala 102:66]
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node _T_27 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 105:61]
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node _T_28 = and(sbcs_wren, _T_27) @[dbg.scala 105:43]
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node sbcs_sbbusyerror_din = not(_T_28) @[dbg.scala 105:31]
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node _T_29 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 106:54]
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node _T_30 = asAsyncReset(_T_29) @[dbg.scala 106:81]
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reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_30, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_sbbusyerror_wren : @[Reg.scala 28:19]
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temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_31 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 110:54]
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node _T_32 = asAsyncReset(_T_31) @[dbg.scala 110:81]
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reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_32, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_sbbusy_wren : @[Reg.scala 28:19]
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temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_33 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 114:54]
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node _T_34 = asAsyncReset(_T_33) @[dbg.scala 114:81]
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node _T_35 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 115:31]
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reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_34, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_wren : @[Reg.scala 28:19]
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temp_sbcs_20 <= _T_35 @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_36 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 118:57]
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node _T_37 = asAsyncReset(_T_36) @[dbg.scala 118:84]
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node _T_38 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 119:31]
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reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_37, UInt<1>("h00"))) @[Reg.scala 27:20]
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when sbcs_wren : @[Reg.scala 28:19]
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temp_sbcs_19_15 <= _T_38 @[Reg.scala 28:23]
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|
skip @[Reg.scala 28:19]
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|
node _T_39 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 122:57]
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node _T_40 = asAsyncReset(_T_39) @[dbg.scala 122:84]
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node _T_41 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 123:31]
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|
reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_40, UInt<1>("h00"))) @[Reg.scala 27:20]
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|
when sbcs_sberror_wren : @[Reg.scala 28:19]
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temp_sbcs_14_12 <= _T_41 @[Reg.scala 28:23]
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|
|
skip @[Reg.scala 28:19]
|
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|
node _T_42 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58]
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node _T_43 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58]
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node _T_44 = cat(_T_43, _T_42) @[Cat.scala 29:58]
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node _T_45 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58]
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node _T_46 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58]
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node _T_47 = cat(_T_46, temp_sbcs_22) @[Cat.scala 29:58]
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node _T_48 = cat(_T_47, _T_45) @[Cat.scala 29:58]
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node _T_49 = cat(_T_48, _T_44) @[Cat.scala 29:58]
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|
sbcs_reg <= _T_49 @[dbg.scala 125:12]
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node _T_50 = bits(sbcs_reg, 19, 17) @[dbg.scala 127:33]
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node _T_51 = eq(_T_50, UInt<1>("h01")) @[dbg.scala 127:42]
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node _T_52 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 127:72]
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node _T_53 = and(_T_51, _T_52) @[dbg.scala 127:56]
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node _T_54 = bits(sbcs_reg, 19, 17) @[dbg.scala 128:14]
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node _T_55 = eq(_T_54, UInt<2>("h02")) @[dbg.scala 128:23]
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|
node _T_56 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 128:53]
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|
|
node _T_57 = orr(_T_56) @[dbg.scala 128:60]
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node _T_58 = and(_T_55, _T_57) @[dbg.scala 128:37]
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|
|
node _T_59 = or(_T_53, _T_58) @[dbg.scala 127:76]
|
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|
|
node _T_60 = bits(sbcs_reg, 19, 17) @[dbg.scala 129:14]
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|
|
node _T_61 = eq(_T_60, UInt<2>("h03")) @[dbg.scala 129:23]
|
|
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|
|
node _T_62 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 129:53]
|
|
|
|
|
node _T_63 = orr(_T_62) @[dbg.scala 129:60]
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|
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|
|
node _T_64 = and(_T_61, _T_63) @[dbg.scala 129:37]
|
|
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|
|
node sbcs_unaligned = or(_T_59, _T_64) @[dbg.scala 128:64]
|
|
|
|
|
node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[dbg.scala 131:35]
|
|
|
|
|
node _T_65 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:42]
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|
|
node _T_66 = eq(_T_65, UInt<1>("h00")) @[dbg.scala 132:51]
|
|
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|
|
node _T_67 = bits(_T_66, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_68 = mux(_T_67, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_69 = and(_T_68, UInt<1>("h01")) @[dbg.scala 132:64]
|
|
|
|
|
node _T_70 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:95]
|
|
|
|
|
node _T_71 = eq(_T_70, UInt<1>("h01")) @[dbg.scala 132:104]
|
|
|
|
|
node _T_72 = bits(_T_71, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_73 = mux(_T_72, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_74 = and(_T_73, UInt<2>("h02")) @[dbg.scala 132:117]
|
|
|
|
|
node _T_75 = or(_T_69, _T_74) @[dbg.scala 132:76]
|
|
|
|
|
node _T_76 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:22]
|
|
|
|
|
node _T_77 = eq(_T_76, UInt<2>("h02")) @[dbg.scala 133:31]
|
|
|
|
|
node _T_78 = bits(_T_77, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_79 = mux(_T_78, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_80 = and(_T_79, UInt<3>("h04")) @[dbg.scala 133:44]
|
|
|
|
|
node _T_81 = or(_T_75, _T_80) @[dbg.scala 132:129]
|
|
|
|
|
node _T_82 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:75]
|
|
|
|
|
node _T_83 = eq(_T_82, UInt<2>("h03")) @[dbg.scala 133:84]
|
|
|
|
|
node _T_84 = bits(_T_83, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_85 = mux(_T_84, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_86 = and(_T_85, UInt<4>("h08")) @[dbg.scala 133:97]
|
|
|
|
|
node sbaddress0_incr = or(_T_81, _T_86) @[dbg.scala 133:56]
|
|
|
|
|
node _T_87 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 135:41]
|
|
|
|
|
node _T_88 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 135:79]
|
|
|
|
|
node sbdata0_reg_wren0 = and(_T_87, _T_88) @[dbg.scala 135:60]
|
|
|
|
|
node _T_89 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 136:37]
|
|
|
|
|
node _T_90 = and(_T_89, sb_state_en) @[dbg.scala 136:60]
|
|
|
|
|
node _T_91 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 136:76]
|
|
|
|
|
node sbdata0_reg_wren1 = and(_T_90, _T_91) @[dbg.scala 136:74]
|
|
|
|
|
node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[dbg.scala 137:44]
|
|
|
|
|
node _T_92 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 138:41]
|
|
|
|
|
node _T_93 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 138:79]
|
|
|
|
|
node sbdata1_reg_wren0 = and(_T_92, _T_93) @[dbg.scala 138:60]
|
|
|
|
|
node _T_94 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 139:37]
|
|
|
|
|
node _T_95 = and(_T_94, sb_state_en) @[dbg.scala 139:60]
|
|
|
|
|
node _T_96 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 139:76]
|
|
|
|
|
node sbdata1_reg_wren1 = and(_T_95, _T_96) @[dbg.scala 139:74]
|
|
|
|
|
node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[dbg.scala 140:44]
|
|
|
|
|
node _T_97 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_98 = mux(_T_97, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_99 = and(_T_98, io.dmi_reg_wdata) @[dbg.scala 141:49]
|
|
|
|
|
node _T_100 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_101 = mux(_T_100, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_102 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 142:47]
|
|
|
|
|
node _T_103 = and(_T_101, _T_102) @[dbg.scala 142:33]
|
|
|
|
|
node sbdata0_din = or(_T_99, _T_103) @[dbg.scala 141:68]
|
|
|
|
|
node _T_104 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_105 = mux(_T_104, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_106 = and(_T_105, io.dmi_reg_wdata) @[dbg.scala 144:49]
|
|
|
|
|
node _T_107 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_108 = mux(_T_107, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_109 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 145:47]
|
|
|
|
|
node _T_110 = and(_T_108, _T_109) @[dbg.scala 145:33]
|
|
|
|
|
node sbdata1_din = or(_T_106, _T_110) @[dbg.scala 144:68]
|
|
|
|
|
node _T_111 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 147:32]
|
|
|
|
|
node _T_112 = asAsyncReset(_T_111) @[dbg.scala 147:59]
|
|
|
|
|
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 352:23]
|
|
|
|
|
rvclkhdr_2.clock <= clock
|
|
|
|
|
rvclkhdr_2.reset <= _T_112
|
|
|
|
|
rvclkhdr_2.io.clk <= clock @[lib.scala 354:18]
|
|
|
|
|
rvclkhdr_2.io.en <= sbdata0_reg_wren @[lib.scala 355:17]
|
|
|
|
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
|
|
|
|
|
reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (_T_112, UInt<1>("h00"))) @[lib.scala 358:16]
|
|
|
|
|
sbdata0_reg <= sbdata0_din @[lib.scala 358:16]
|
|
|
|
|
node _T_113 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 151:32]
|
|
|
|
|
node _T_114 = asAsyncReset(_T_113) @[dbg.scala 151:59]
|
|
|
|
|
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 352:23]
|
|
|
|
|
rvclkhdr_3.clock <= clock
|
|
|
|
|
rvclkhdr_3.reset <= _T_114
|
|
|
|
|
rvclkhdr_3.io.clk <= clock @[lib.scala 354:18]
|
|
|
|
|
rvclkhdr_3.io.en <= sbdata1_reg_wren @[lib.scala 355:17]
|
|
|
|
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
|
|
|
|
|
reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (_T_114, UInt<1>("h00"))) @[lib.scala 358:16]
|
|
|
|
|
sbdata1_reg <= sbdata1_din @[lib.scala 358:16]
|
|
|
|
|
node _T_115 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 155:44]
|
|
|
|
|
node _T_116 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 155:82]
|
|
|
|
|
node sbaddress0_reg_wren0 = and(_T_115, _T_116) @[dbg.scala 155:63]
|
|
|
|
|
node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[dbg.scala 156:50]
|
|
|
|
|
node _T_117 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_118 = mux(_T_117, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_119 = and(_T_118, io.dmi_reg_wdata) @[dbg.scala 157:59]
|
|
|
|
|
node _T_120 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_121 = mux(_T_120, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_122 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58]
|
|
|
|
|
node _T_123 = add(sbaddress0_reg, _T_122) @[dbg.scala 158:54]
|
|
|
|
|
node _T_124 = tail(_T_123, 1) @[dbg.scala 158:54]
|
|
|
|
|
node _T_125 = and(_T_121, _T_124) @[dbg.scala 158:36]
|
|
|
|
|
node sbaddress0_reg_din = or(_T_119, _T_125) @[dbg.scala 157:78]
|
|
|
|
|
node _T_126 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 159:32]
|
|
|
|
|
node _T_127 = asAsyncReset(_T_126) @[dbg.scala 159:59]
|
|
|
|
|
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 352:23]
|
|
|
|
|
rvclkhdr_4.clock <= clock
|
|
|
|
|
rvclkhdr_4.reset <= _T_127
|
|
|
|
|
rvclkhdr_4.io.clk <= clock @[lib.scala 354:18]
|
|
|
|
|
rvclkhdr_4.io.en <= sbaddress0_reg_wren @[lib.scala 355:17]
|
|
|
|
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
|
|
|
|
|
reg _T_128 : UInt, rvclkhdr_4.io.l1clk with : (reset => (_T_127, UInt<1>("h00"))) @[lib.scala 358:16]
|
|
|
|
|
_T_128 <= sbaddress0_reg_din @[lib.scala 358:16]
|
|
|
|
|
sbaddress0_reg <= _T_128 @[dbg.scala 159:18]
|
|
|
|
|
node _T_129 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 163:43]
|
|
|
|
|
node _T_130 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 163:81]
|
|
|
|
|
node _T_131 = and(_T_129, _T_130) @[dbg.scala 163:62]
|
|
|
|
|
node _T_132 = bits(sbcs_reg, 20, 20) @[dbg.scala 163:104]
|
|
|
|
|
node sbreadonaddr_access = and(_T_131, _T_132) @[dbg.scala 163:94]
|
|
|
|
|
node _T_133 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 164:45]
|
|
|
|
|
node _T_134 = and(io.dmi_reg_en, _T_133) @[dbg.scala 164:43]
|
|
|
|
|
node _T_135 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 164:82]
|
|
|
|
|
node _T_136 = and(_T_134, _T_135) @[dbg.scala 164:63]
|
|
|
|
|
node _T_137 = bits(sbcs_reg, 15, 15) @[dbg.scala 164:105]
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node sbreadondata_access = and(_T_136, _T_137) @[dbg.scala 164:95]
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node _T_138 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 165:40]
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node _T_139 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 165:78]
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node sbdata0wr_access = and(_T_138, _T_139) @[dbg.scala 165:59]
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node _T_140 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 166:41]
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node _T_141 = and(_T_140, io.dmi_reg_en) @[dbg.scala 166:54]
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node dmcontrol_wren = and(_T_141, io.dmi_reg_wr_en) @[dbg.scala 166:70]
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node _T_142 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 167:50]
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node _T_143 = asAsyncReset(_T_142) @[dbg.scala 167:77]
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node _T_144 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 169:27]
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node _T_145 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 169:53]
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node _T_146 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 169:75]
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node _T_147 = cat(_T_144, _T_145) @[Cat.scala 29:58]
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node _T_148 = cat(_T_147, _T_146) @[Cat.scala 29:58]
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reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (_T_143, UInt<1>("h00"))) @[Reg.scala 27:20]
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when dmcontrol_wren : @[Reg.scala 28:19]
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dm_temp <= _T_148 @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_149 = asAsyncReset(io.dbg_rst_l) @[dbg.scala 173:76]
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node _T_150 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 174:31]
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reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_149, UInt<1>("h00"))) @[Reg.scala 27:20]
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when dmcontrol_wren : @[Reg.scala 28:19]
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dm_temp_0 <= _T_150 @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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node _T_151 = bits(dm_temp, 3, 2) @[dbg.scala 177:25]
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node _T_152 = bits(dm_temp, 1, 1) @[dbg.scala 177:45]
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node _T_153 = bits(dm_temp, 0, 0) @[dbg.scala 177:68]
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node _T_154 = cat(UInt<26>("h00"), _T_153) @[Cat.scala 29:58]
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node _T_155 = cat(_T_154, dm_temp_0) @[Cat.scala 29:58]
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node _T_156 = cat(_T_151, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_157 = cat(_T_156, _T_152) @[Cat.scala 29:58]
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node temp = cat(_T_157, _T_155) @[Cat.scala 29:58]
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dmcontrol_reg <= temp @[dbg.scala 178:17]
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node _T_158 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 180:59]
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node _T_159 = asAsyncReset(_T_158) @[dbg.scala 180:86]
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reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_159, UInt<1>("h00"))) @[dbg.scala 181:12]
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dmcontrol_wren_Q <= dmcontrol_wren @[dbg.scala 181:12]
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node _T_160 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15]
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node _T_161 = mux(_T_160, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_162 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15]
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node _T_163 = mux(_T_162, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_164 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15]
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node _T_165 = mux(_T_164, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_166 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15]
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node _T_167 = mux(_T_166, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_168 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15]
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node _T_169 = mux(_T_168, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_170 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58]
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node _T_171 = cat(_T_167, _T_169) @[Cat.scala 29:58]
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node _T_172 = cat(_T_171, UInt<1>("h01")) @[Cat.scala 29:58]
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node _T_173 = cat(_T_172, _T_170) @[Cat.scala 29:58]
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node _T_174 = cat(UInt<2>("h00"), _T_165) @[Cat.scala 29:58]
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node _T_175 = cat(UInt<12>("h00"), _T_161) @[Cat.scala 29:58]
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node _T_176 = cat(_T_175, _T_163) @[Cat.scala 29:58]
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node _T_177 = cat(_T_176, _T_174) @[Cat.scala 29:58]
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node _T_178 = cat(_T_177, _T_173) @[Cat.scala 29:58]
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dmstatus_reg <= _T_178 @[dbg.scala 184:16]
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node _T_179 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 186:44]
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node _T_180 = and(_T_179, io.dec_tlu_resume_ack) @[dbg.scala 186:66]
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|
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node _T_181 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 186:127]
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node _T_182 = eq(_T_181, UInt<1>("h00")) @[dbg.scala 186:113]
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|
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node _T_183 = and(dmstatus_resumeack, _T_182) @[dbg.scala 186:111]
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|
|
node dmstatus_resumeack_wren = or(_T_180, _T_183) @[dbg.scala 186:90]
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|
|
node _T_184 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 187:43]
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|
|
node dmstatus_resumeack_din = and(_T_184, io.dec_tlu_resume_ack) @[dbg.scala 187:65]
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|
|
node _T_185 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 188:50]
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|
|
node _T_186 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 188:81]
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|
|
node _T_187 = and(_T_185, _T_186) @[dbg.scala 188:63]
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|
node _T_188 = and(_T_187, io.dmi_reg_en) @[dbg.scala 188:85]
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|
|
node dmstatus_havereset_wren = and(_T_188, io.dmi_reg_wr_en) @[dbg.scala 188:101]
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|
|
node _T_189 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 189:49]
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|
|
node _T_190 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 189:80]
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|
|
node _T_191 = and(_T_189, _T_190) @[dbg.scala 189:62]
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|
|
node _T_192 = and(_T_191, io.dmi_reg_en) @[dbg.scala 189:85]
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|
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|
|
node dmstatus_havereset_rst = and(_T_192, io.dmi_reg_wr_en) @[dbg.scala 189:101]
|
|
|
|
|
node temp_rst = asUInt(reset) @[dbg.scala 190:30]
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|
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|
|
node _T_193 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 191:37]
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|
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|
|
node _T_194 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 191:43]
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|
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|
|
node _T_195 = or(_T_193, _T_194) @[dbg.scala 191:41]
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|
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|
|
node _T_196 = bits(_T_195, 0, 0) @[dbg.scala 191:62]
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|
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|
|
dmstatus_unavail <= _T_196 @[dbg.scala 191:20]
|
|
|
|
|
node _T_197 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 192:42]
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|
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|
|
node _T_198 = not(_T_197) @[dbg.scala 192:23]
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|
|
|
|
dmstatus_running <= _T_198 @[dbg.scala 192:20]
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|
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|
|
node _T_199 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 193:58]
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|
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|
|
node _T_200 = asAsyncReset(_T_199) @[dbg.scala 193:85]
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|
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|
|
reg _T_201 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_200, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when dmstatus_resumeack_wren : @[Reg.scala 28:19]
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|
|
|
|
_T_201 <= dmstatus_resumeack_din @[Reg.scala 28:23]
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|
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|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
dmstatus_resumeack <= _T_201 @[dbg.scala 193:22]
|
|
|
|
|
node _T_202 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 197:55]
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|
|
node _T_203 = asAsyncReset(_T_202) @[dbg.scala 197:82]
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|
|
node _T_204 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 198:37]
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|
|
node _T_205 = and(io.dec_tlu_dbg_halted, _T_204) @[dbg.scala 198:35]
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|
|
reg _T_206 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_203, UInt<1>("h00"))) @[dbg.scala 198:12]
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|
|
|
|
_T_206 <= _T_205 @[dbg.scala 198:12]
|
|
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|
|
dmstatus_halted <= _T_206 @[dbg.scala 197:19]
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|
|
|
|
node _T_207 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 201:58]
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|
|
|
|
node _T_208 = asAsyncReset(_T_207) @[dbg.scala 201:85]
|
|
|
|
|
node _T_209 = not(dmstatus_havereset_rst) @[dbg.scala 202:15]
|
|
|
|
|
reg _T_210 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_208, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when dmstatus_havereset_wren : @[Reg.scala 28:19]
|
|
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|
|
_T_210 <= _T_209 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
dmstatus_havereset <= _T_210 @[dbg.scala 201:22]
|
|
|
|
|
node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58]
|
|
|
|
|
wire abstractcs_reg : UInt<32>
|
|
|
|
|
abstractcs_reg <= UInt<32>("h02")
|
|
|
|
|
node _T_211 = bits(abstractcs_reg, 12, 12) @[dbg.scala 208:45]
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|
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|
|
node _T_212 = and(_T_211, io.dmi_reg_en) @[dbg.scala 208:50]
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|
|
node _T_213 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 208:106]
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|
|
node _T_214 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 208:138]
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|
|
|
node _T_215 = or(_T_213, _T_214) @[dbg.scala 208:119]
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|
|
node _T_216 = and(io.dmi_reg_wr_en, _T_215) @[dbg.scala 208:86]
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|
|
|
node _T_217 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 208:171]
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|
|
|
|
node _T_218 = or(_T_216, _T_217) @[dbg.scala 208:152]
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|
|
|
node abstractcs_error_sel0 = and(_T_212, _T_218) @[dbg.scala 208:66]
|
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|
|
|
node _T_219 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 209:45]
|
|
|
|
|
node _T_220 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 209:83]
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|
|
|
|
node _T_221 = and(_T_219, _T_220) @[dbg.scala 209:64]
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|
|
|
|
node _T_222 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:117]
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|
|
|
|
node _T_223 = eq(_T_222, UInt<1>("h00")) @[dbg.scala 209:126]
|
|
|
|
|
node _T_224 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:154]
|
|
|
|
|
node _T_225 = eq(_T_224, UInt<2>("h02")) @[dbg.scala 209:163]
|
|
|
|
|
node _T_226 = or(_T_223, _T_225) @[dbg.scala 209:135]
|
|
|
|
|
node _T_227 = eq(_T_226, UInt<1>("h00")) @[dbg.scala 209:98]
|
|
|
|
|
node abstractcs_error_sel1 = and(_T_221, _T_227) @[dbg.scala 209:96]
|
|
|
|
|
node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[dbg.scala 210:52]
|
|
|
|
|
node _T_228 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 211:45]
|
|
|
|
|
node _T_229 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 211:83]
|
|
|
|
|
node _T_230 = and(_T_228, _T_229) @[dbg.scala 211:64]
|
|
|
|
|
node _T_231 = bits(dmstatus_reg, 9, 9) @[dbg.scala 211:111]
|
|
|
|
|
node _T_232 = eq(_T_231, UInt<1>("h00")) @[dbg.scala 211:98]
|
|
|
|
|
node abstractcs_error_sel3 = and(_T_230, _T_232) @[dbg.scala 211:96]
|
|
|
|
|
node _T_233 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 212:48]
|
|
|
|
|
node _T_234 = and(_T_233, io.dmi_reg_en) @[dbg.scala 212:61]
|
|
|
|
|
node _T_235 = and(_T_234, io.dmi_reg_wr_en) @[dbg.scala 212:77]
|
|
|
|
|
node _T_236 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 213:23]
|
|
|
|
|
node _T_237 = neq(_T_236, UInt<2>("h02")) @[dbg.scala 213:32]
|
|
|
|
|
node _T_238 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 213:66]
|
|
|
|
|
node _T_239 = eq(_T_238, UInt<2>("h02")) @[dbg.scala 213:75]
|
|
|
|
|
node _T_240 = bits(data1_reg, 1, 0) @[dbg.scala 213:99]
|
|
|
|
|
node _T_241 = orr(_T_240) @[dbg.scala 213:106]
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|
|
|
|
node _T_242 = and(_T_239, _T_241) @[dbg.scala 213:87]
|
|
|
|
|
node _T_243 = or(_T_237, _T_242) @[dbg.scala 213:46]
|
|
|
|
|
node abstractcs_error_sel4 = and(_T_235, _T_243) @[dbg.scala 212:96]
|
|
|
|
|
node _T_244 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 215:48]
|
|
|
|
|
node _T_245 = and(_T_244, io.dmi_reg_en) @[dbg.scala 215:61]
|
|
|
|
|
node abstractcs_error_sel5 = and(_T_245, io.dmi_reg_wr_en) @[dbg.scala 215:77]
|
|
|
|
|
node _T_246 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 216:54]
|
|
|
|
|
node _T_247 = or(_T_246, abstractcs_error_sel2) @[dbg.scala 216:78]
|
|
|
|
|
node _T_248 = or(_T_247, abstractcs_error_sel3) @[dbg.scala 216:102]
|
|
|
|
|
node _T_249 = or(_T_248, abstractcs_error_sel4) @[dbg.scala 216:126]
|
|
|
|
|
node abstractcs_error_selor = or(_T_249, abstractcs_error_sel5) @[dbg.scala 216:150]
|
|
|
|
|
node _T_250 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_251 = mux(_T_250, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_252 = and(_T_251, UInt<1>("h01")) @[dbg.scala 217:62]
|
|
|
|
|
node _T_253 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_254 = mux(_T_253, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_255 = and(_T_254, UInt<2>("h02")) @[dbg.scala 218:37]
|
|
|
|
|
node _T_256 = or(_T_252, _T_255) @[dbg.scala 217:74]
|
|
|
|
|
node _T_257 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_258 = mux(_T_257, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_259 = and(_T_258, UInt<2>("h03")) @[dbg.scala 219:37]
|
|
|
|
|
node _T_260 = or(_T_256, _T_259) @[dbg.scala 218:49]
|
|
|
|
|
node _T_261 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_262 = mux(_T_261, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_263 = and(_T_262, UInt<3>("h04")) @[dbg.scala 220:37]
|
|
|
|
|
node _T_264 = or(_T_260, _T_263) @[dbg.scala 219:49]
|
|
|
|
|
node _T_265 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_266 = mux(_T_265, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_267 = and(_T_266, UInt<3>("h07")) @[dbg.scala 221:37]
|
|
|
|
|
node _T_268 = or(_T_264, _T_267) @[dbg.scala 220:49]
|
|
|
|
|
node _T_269 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_270 = mux(_T_269, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_271 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 222:57]
|
|
|
|
|
node _T_272 = not(_T_271) @[dbg.scala 222:40]
|
|
|
|
|
node _T_273 = and(_T_270, _T_272) @[dbg.scala 222:37]
|
|
|
|
|
node _T_274 = bits(abstractcs_reg, 10, 8) @[dbg.scala 222:91]
|
|
|
|
|
node _T_275 = and(_T_273, _T_274) @[dbg.scala 222:75]
|
|
|
|
|
node _T_276 = or(_T_268, _T_275) @[dbg.scala 221:49]
|
|
|
|
|
node _T_277 = not(abstractcs_error_selor) @[dbg.scala 223:15]
|
|
|
|
|
node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_279 = mux(_T_278, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_280 = bits(abstractcs_reg, 10, 8) @[dbg.scala 223:66]
|
|
|
|
|
node _T_281 = and(_T_279, _T_280) @[dbg.scala 223:50]
|
|
|
|
|
node abstractcs_error_din = or(_T_276, _T_281) @[dbg.scala 222:100]
|
|
|
|
|
node _T_282 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 225:54]
|
|
|
|
|
node _T_283 = asAsyncReset(_T_282) @[dbg.scala 225:81]
|
|
|
|
|
reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_283, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when abstractcs_busy_wren : @[Reg.scala 28:19]
|
|
|
|
|
abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_284 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 229:56]
|
|
|
|
|
node _T_285 = asAsyncReset(_T_284) @[dbg.scala 229:83]
|
|
|
|
|
node _T_286 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 230:33]
|
|
|
|
|
reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_285, UInt<1>("h00"))) @[dbg.scala 230:12]
|
|
|
|
|
abs_temp_10_8 <= _T_286 @[dbg.scala 230:12]
|
|
|
|
|
node _T_287 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_288 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58]
|
|
|
|
|
node _T_289 = cat(_T_288, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_290 = cat(_T_289, _T_287) @[Cat.scala 29:58]
|
|
|
|
|
abstractcs_reg <= _T_290 @[dbg.scala 233:18]
|
|
|
|
|
node _T_291 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 235:39]
|
|
|
|
|
node _T_292 = and(_T_291, io.dmi_reg_en) @[dbg.scala 235:52]
|
|
|
|
|
node _T_293 = and(_T_292, io.dmi_reg_wr_en) @[dbg.scala 235:68]
|
|
|
|
|
node _T_294 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 235:100]
|
|
|
|
|
node command_wren = and(_T_293, _T_294) @[dbg.scala 235:87]
|
|
|
|
|
node _T_295 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 236:41]
|
|
|
|
|
node _T_296 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 236:77]
|
|
|
|
|
node _T_297 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 236:113]
|
|
|
|
|
node _T_298 = cat(UInt<3>("h00"), _T_297) @[Cat.scala 29:58]
|
|
|
|
|
node _T_299 = cat(_T_295, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_300 = cat(_T_299, _T_296) @[Cat.scala 29:58]
|
|
|
|
|
node command_din = cat(_T_300, _T_298) @[Cat.scala 29:58]
|
|
|
|
|
node _T_301 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 237:32]
|
|
|
|
|
node _T_302 = asAsyncReset(_T_301) @[dbg.scala 237:59]
|
|
|
|
|
reg command_reg : UInt, clock with : (reset => (_T_302, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when command_wren : @[Reg.scala 28:19]
|
|
|
|
|
command_reg <= command_din @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_303 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 241:39]
|
|
|
|
|
node _T_304 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 241:77]
|
|
|
|
|
node _T_305 = and(_T_303, _T_304) @[dbg.scala 241:58]
|
|
|
|
|
node _T_306 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 241:102]
|
|
|
|
|
node data0_reg_wren0 = and(_T_305, _T_306) @[dbg.scala 241:89]
|
|
|
|
|
node _T_307 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 242:59]
|
|
|
|
|
node _T_308 = and(io.core_dbg_cmd_done, _T_307) @[dbg.scala 242:46]
|
|
|
|
|
node _T_309 = bits(command_reg, 16, 16) @[dbg.scala 242:95]
|
|
|
|
|
node _T_310 = eq(_T_309, UInt<1>("h00")) @[dbg.scala 242:83]
|
|
|
|
|
node data0_reg_wren1 = and(_T_308, _T_310) @[dbg.scala 242:81]
|
|
|
|
|
node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[dbg.scala 244:40]
|
|
|
|
|
node _T_311 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_312 = mux(_T_311, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_313 = and(_T_312, io.dmi_reg_wdata) @[dbg.scala 245:45]
|
|
|
|
|
node _T_314 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_315 = mux(_T_314, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_316 = and(_T_315, io.core_dbg_rddata) @[dbg.scala 245:92]
|
|
|
|
|
node data0_din = or(_T_313, _T_316) @[dbg.scala 245:64]
|
|
|
|
|
node _T_317 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 246:30]
|
|
|
|
|
node _T_318 = asAsyncReset(_T_317) @[dbg.scala 246:57]
|
|
|
|
|
reg data0_reg : UInt, clock with : (reset => (_T_318, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when data0_reg_wren : @[Reg.scala 28:19]
|
|
|
|
|
data0_reg <= data0_din @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_319 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 250:39]
|
|
|
|
|
node _T_320 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 250:77]
|
|
|
|
|
node _T_321 = and(_T_319, _T_320) @[dbg.scala 250:58]
|
|
|
|
|
node _T_322 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 250:102]
|
|
|
|
|
node data1_reg_wren = and(_T_321, _T_322) @[dbg.scala 250:89]
|
|
|
|
|
node _T_323 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_324 = mux(_T_323, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node data1_din = and(_T_324, io.dmi_reg_wdata) @[dbg.scala 251:44]
|
|
|
|
|
node _T_325 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 252:27]
|
|
|
|
|
node _T_326 = asAsyncReset(_T_325) @[dbg.scala 252:54]
|
|
|
|
|
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 352:23]
|
|
|
|
|
rvclkhdr_5.clock <= clock
|
|
|
|
|
rvclkhdr_5.reset <= _T_326
|
|
|
|
|
rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
|
|
|
|
|
rvclkhdr_5.io.en <= data1_reg_wren @[lib.scala 355:17]
|
|
|
|
|
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
|
|
|
|
|
reg _T_327 : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_326, UInt<1>("h00"))) @[lib.scala 358:16]
|
|
|
|
|
_T_327 <= data1_din @[lib.scala 358:16]
|
|
|
|
|
data1_reg <= _T_327 @[dbg.scala 252:13]
|
|
|
|
|
wire dbg_nxtstate : UInt<3>
|
|
|
|
|
dbg_nxtstate <= UInt<3>("h00")
|
|
|
|
|
dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 257:16]
|
|
|
|
|
dbg_state_en <= UInt<1>("h00") @[dbg.scala 258:16]
|
|
|
|
|
abstractcs_busy_wren <= UInt<1>("h00") @[dbg.scala 259:24]
|
|
|
|
|
abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 260:23]
|
|
|
|
|
io.dbg_halt_req <= UInt<1>("h00") @[dbg.scala 261:19]
|
|
|
|
|
io.dbg_resume_req <= UInt<1>("h00") @[dbg.scala 262:21]
|
|
|
|
|
node _T_328 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_328 : @[Conditional.scala 40:58]
|
|
|
|
|
node _T_329 = bits(dmstatus_reg, 9, 9) @[dbg.scala 265:39]
|
|
|
|
|
node _T_330 = or(_T_329, io.dec_tlu_mpc_halted_only) @[dbg.scala 265:43]
|
|
|
|
|
node _T_331 = mux(_T_330, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 265:26]
|
|
|
|
|
dbg_nxtstate <= _T_331 @[dbg.scala 265:20]
|
|
|
|
|
node _T_332 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 266:38]
|
|
|
|
|
node _T_333 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 266:45]
|
|
|
|
|
node _T_334 = and(_T_332, _T_333) @[dbg.scala 266:43]
|
|
|
|
|
node _T_335 = bits(dmstatus_reg, 9, 9) @[dbg.scala 266:83]
|
|
|
|
|
node _T_336 = or(_T_334, _T_335) @[dbg.scala 266:69]
|
|
|
|
|
node _T_337 = or(_T_336, io.dec_tlu_mpc_halted_only) @[dbg.scala 266:87]
|
|
|
|
|
node _T_338 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 266:133]
|
|
|
|
|
node _T_339 = eq(_T_338, UInt<1>("h00")) @[dbg.scala 266:119]
|
|
|
|
|
node _T_340 = and(_T_337, _T_339) @[dbg.scala 266:117]
|
|
|
|
|
dbg_state_en <= _T_340 @[dbg.scala 266:20]
|
|
|
|
|
node _T_341 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 267:40]
|
|
|
|
|
node _T_342 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 267:61]
|
|
|
|
|
node _T_343 = eq(_T_342, UInt<1>("h00")) @[dbg.scala 267:47]
|
|
|
|
|
node _T_344 = and(_T_341, _T_343) @[dbg.scala 267:45]
|
|
|
|
|
node _T_345 = bits(_T_344, 0, 0) @[dbg.scala 267:72]
|
|
|
|
|
io.dbg_halt_req <= _T_345 @[dbg.scala 267:23]
|
|
|
|
|
skip @[Conditional.scala 40:58]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_346 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_346 : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_347 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 270:40]
|
|
|
|
|
node _T_348 = mux(_T_347, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 270:26]
|
|
|
|
|
dbg_nxtstate <= _T_348 @[dbg.scala 270:20]
|
|
|
|
|
node _T_349 = bits(dmstatus_reg, 9, 9) @[dbg.scala 271:35]
|
|
|
|
|
node _T_350 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 271:54]
|
|
|
|
|
node _T_351 = or(_T_349, _T_350) @[dbg.scala 271:39]
|
|
|
|
|
dbg_state_en <= _T_351 @[dbg.scala 271:20]
|
|
|
|
|
node _T_352 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 272:59]
|
|
|
|
|
node _T_353 = and(dmcontrol_wren_Q, _T_352) @[dbg.scala 272:44]
|
|
|
|
|
node _T_354 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 272:81]
|
|
|
|
|
node _T_355 = not(_T_354) @[dbg.scala 272:67]
|
|
|
|
|
node _T_356 = and(_T_353, _T_355) @[dbg.scala 272:64]
|
|
|
|
|
node _T_357 = bits(_T_356, 0, 0) @[dbg.scala 272:102]
|
|
|
|
|
io.dbg_halt_req <= _T_357 @[dbg.scala 272:23]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_358 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_358 : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_359 = bits(dmstatus_reg, 9, 9) @[dbg.scala 275:39]
|
|
|
|
|
node _T_360 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 275:59]
|
|
|
|
|
node _T_361 = eq(_T_360, UInt<1>("h00")) @[dbg.scala 275:45]
|
|
|
|
|
node _T_362 = and(_T_359, _T_361) @[dbg.scala 275:43]
|
|
|
|
|
node _T_363 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 276:26]
|
|
|
|
|
node _T_364 = bits(dmcontrol_reg, 3, 3) @[dbg.scala 276:47]
|
|
|
|
|
node _T_365 = eq(_T_364, UInt<1>("h00")) @[dbg.scala 276:33]
|
|
|
|
|
node _T_366 = and(_T_363, _T_365) @[dbg.scala 276:31]
|
|
|
|
|
node _T_367 = mux(_T_366, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 276:12]
|
|
|
|
|
node _T_368 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 277:26]
|
|
|
|
|
node _T_369 = mux(_T_368, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 277:12]
|
|
|
|
|
node _T_370 = mux(_T_362, _T_367, _T_369) @[dbg.scala 275:26]
|
|
|
|
|
dbg_nxtstate <= _T_370 @[dbg.scala 275:20]
|
|
|
|
|
node _T_371 = bits(dmstatus_reg, 9, 9) @[dbg.scala 278:35]
|
|
|
|
|
node _T_372 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 278:54]
|
|
|
|
|
node _T_373 = and(_T_371, _T_372) @[dbg.scala 278:39]
|
|
|
|
|
node _T_374 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 278:75]
|
|
|
|
|
node _T_375 = eq(_T_374, UInt<1>("h00")) @[dbg.scala 278:61]
|
|
|
|
|
node _T_376 = and(_T_373, _T_375) @[dbg.scala 278:59]
|
|
|
|
|
node _T_377 = and(_T_376, dmcontrol_wren_Q) @[dbg.scala 278:80]
|
|
|
|
|
node _T_378 = or(_T_377, command_wren) @[dbg.scala 278:99]
|
|
|
|
|
node _T_379 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 279:22]
|
|
|
|
|
node _T_380 = or(_T_378, _T_379) @[dbg.scala 278:114]
|
|
|
|
|
node _T_381 = bits(dmstatus_reg, 9, 9) @[dbg.scala 279:42]
|
|
|
|
|
node _T_382 = or(_T_381, io.dec_tlu_mpc_halted_only) @[dbg.scala 279:46]
|
|
|
|
|
node _T_383 = eq(_T_382, UInt<1>("h00")) @[dbg.scala 279:28]
|
|
|
|
|
node _T_384 = or(_T_380, _T_383) @[dbg.scala 279:26]
|
|
|
|
|
dbg_state_en <= _T_384 @[dbg.scala 278:20]
|
|
|
|
|
node _T_385 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 280:60]
|
|
|
|
|
node _T_386 = and(dbg_state_en, _T_385) @[dbg.scala 280:44]
|
|
|
|
|
abstractcs_busy_wren <= _T_386 @[dbg.scala 280:28]
|
|
|
|
|
abstractcs_busy_din <= UInt<1>("h01") @[dbg.scala 281:27]
|
|
|
|
|
node _T_387 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 282:58]
|
|
|
|
|
node _T_388 = and(dbg_state_en, _T_387) @[dbg.scala 282:42]
|
|
|
|
|
node _T_389 = bits(_T_388, 0, 0) @[dbg.scala 282:87]
|
|
|
|
|
io.dbg_resume_req <= _T_389 @[dbg.scala 282:25]
|
|
|
|
|
node _T_390 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:59]
|
|
|
|
|
node _T_391 = and(dmcontrol_wren_Q, _T_390) @[dbg.scala 283:44]
|
|
|
|
|
node _T_392 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 283:81]
|
|
|
|
|
node _T_393 = not(_T_392) @[dbg.scala 283:67]
|
|
|
|
|
node _T_394 = and(_T_391, _T_393) @[dbg.scala 283:64]
|
|
|
|
|
node _T_395 = bits(_T_394, 0, 0) @[dbg.scala 283:102]
|
|
|
|
|
io.dbg_halt_req <= _T_395 @[dbg.scala 283:23]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_396 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_396 : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_397 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 286:40]
|
|
|
|
|
node _T_398 = bits(abstractcs_reg, 10, 8) @[dbg.scala 286:77]
|
|
|
|
|
node _T_399 = orr(_T_398) @[dbg.scala 286:85]
|
|
|
|
|
node _T_400 = mux(_T_399, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 286:62]
|
|
|
|
|
node _T_401 = mux(_T_397, UInt<3>("h00"), _T_400) @[dbg.scala 286:26]
|
|
|
|
|
dbg_nxtstate <= _T_401 @[dbg.scala 286:20]
|
|
|
|
|
node _T_402 = bits(abstractcs_reg, 10, 8) @[dbg.scala 287:71]
|
|
|
|
|
node _T_403 = orr(_T_402) @[dbg.scala 287:79]
|
|
|
|
|
node _T_404 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_403) @[dbg.scala 287:55]
|
|
|
|
|
node _T_405 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 287:98]
|
|
|
|
|
node _T_406 = or(_T_404, _T_405) @[dbg.scala 287:83]
|
|
|
|
|
dbg_state_en <= _T_406 @[dbg.scala 287:20]
|
|
|
|
|
node _T_407 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 288:59]
|
|
|
|
|
node _T_408 = and(dmcontrol_wren_Q, _T_407) @[dbg.scala 288:44]
|
|
|
|
|
node _T_409 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 288:81]
|
|
|
|
|
node _T_410 = not(_T_409) @[dbg.scala 288:67]
|
|
|
|
|
node _T_411 = and(_T_408, _T_410) @[dbg.scala 288:64]
|
|
|
|
|
node _T_412 = bits(_T_411, 0, 0) @[dbg.scala 288:102]
|
|
|
|
|
io.dbg_halt_req <= _T_412 @[dbg.scala 288:23]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_413 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_413 : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_414 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 291:40]
|
|
|
|
|
node _T_415 = mux(_T_414, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 291:26]
|
|
|
|
|
dbg_nxtstate <= _T_415 @[dbg.scala 291:20]
|
|
|
|
|
node _T_416 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 292:59]
|
|
|
|
|
node _T_417 = or(io.core_dbg_cmd_done, _T_416) @[dbg.scala 292:44]
|
|
|
|
|
dbg_state_en <= _T_417 @[dbg.scala 292:20]
|
|
|
|
|
node _T_418 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 293:59]
|
|
|
|
|
node _T_419 = and(dmcontrol_wren_Q, _T_418) @[dbg.scala 293:44]
|
|
|
|
|
node _T_420 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:81]
|
|
|
|
|
node _T_421 = not(_T_420) @[dbg.scala 293:67]
|
|
|
|
|
node _T_422 = and(_T_419, _T_421) @[dbg.scala 293:64]
|
|
|
|
|
node _T_423 = bits(_T_422, 0, 0) @[dbg.scala 293:102]
|
|
|
|
|
io.dbg_halt_req <= _T_423 @[dbg.scala 293:23]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_424 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_424 : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_425 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 296:40]
|
|
|
|
|
node _T_426 = mux(_T_425, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 296:26]
|
|
|
|
|
dbg_nxtstate <= _T_426 @[dbg.scala 296:20]
|
|
|
|
|
dbg_state_en <= UInt<1>("h01") @[dbg.scala 297:20]
|
|
|
|
|
abstractcs_busy_wren <= dbg_state_en @[dbg.scala 298:28]
|
|
|
|
|
abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 299:27]
|
|
|
|
|
node _T_427 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 300:59]
|
|
|
|
|
node _T_428 = and(dmcontrol_wren_Q, _T_427) @[dbg.scala 300:44]
|
|
|
|
|
node _T_429 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 300:81]
|
|
|
|
|
node _T_430 = not(_T_429) @[dbg.scala 300:67]
|
|
|
|
|
node _T_431 = and(_T_428, _T_430) @[dbg.scala 300:64]
|
|
|
|
|
node _T_432 = bits(_T_431, 0, 0) @[dbg.scala 300:102]
|
|
|
|
|
io.dbg_halt_req <= _T_432 @[dbg.scala 300:23]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_433 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_433 : @[Conditional.scala 39:67]
|
|
|
|
|
dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 303:20]
|
|
|
|
|
node _T_434 = bits(dmstatus_reg, 17, 17) @[dbg.scala 304:35]
|
|
|
|
|
node _T_435 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 304:55]
|
|
|
|
|
node _T_436 = or(_T_434, _T_435) @[dbg.scala 304:40]
|
|
|
|
|
dbg_state_en <= _T_436 @[dbg.scala 304:20]
|
|
|
|
|
node _T_437 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:59]
|
|
|
|
|
node _T_438 = and(dmcontrol_wren_Q, _T_437) @[dbg.scala 305:44]
|
|
|
|
|
node _T_439 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 305:81]
|
|
|
|
|
node _T_440 = not(_T_439) @[dbg.scala 305:67]
|
|
|
|
|
node _T_441 = and(_T_438, _T_440) @[dbg.scala 305:64]
|
|
|
|
|
node _T_442 = bits(_T_441, 0, 0) @[dbg.scala 305:102]
|
|
|
|
|
io.dbg_halt_req <= _T_442 @[dbg.scala 305:23]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
node _T_443 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 308:52]
|
|
|
|
|
node _T_444 = bits(_T_443, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_445 = mux(_T_444, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_446 = and(_T_445, data0_reg) @[dbg.scala 308:71]
|
|
|
|
|
node _T_447 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 308:110]
|
|
|
|
|
node _T_448 = bits(_T_447, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_450 = and(_T_449, data1_reg) @[dbg.scala 308:122]
|
|
|
|
|
node _T_451 = or(_T_446, _T_450) @[dbg.scala 308:83]
|
|
|
|
|
node _T_452 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 309:30]
|
|
|
|
|
node _T_453 = bits(_T_452, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_454 = mux(_T_453, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_455 = and(_T_454, dmcontrol_reg) @[dbg.scala 309:43]
|
|
|
|
|
node _T_456 = or(_T_451, _T_455) @[dbg.scala 308:134]
|
|
|
|
|
node _T_457 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 309:86]
|
|
|
|
|
node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_460 = and(_T_459, dmstatus_reg) @[dbg.scala 309:99]
|
|
|
|
|
node _T_461 = or(_T_456, _T_460) @[dbg.scala 309:59]
|
|
|
|
|
node _T_462 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 310:30]
|
|
|
|
|
node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_464 = mux(_T_463, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_465 = and(_T_464, abstractcs_reg) @[dbg.scala 310:43]
|
|
|
|
|
node _T_466 = or(_T_461, _T_465) @[dbg.scala 309:114]
|
|
|
|
|
node _T_467 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 310:87]
|
|
|
|
|
node _T_468 = bits(_T_467, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_470 = and(_T_469, command_reg) @[dbg.scala 310:100]
|
|
|
|
|
node _T_471 = or(_T_466, _T_470) @[dbg.scala 310:60]
|
|
|
|
|
node _T_472 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 311:30]
|
|
|
|
|
node _T_473 = bits(_T_472, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_474 = mux(_T_473, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_475 = and(_T_474, haltsum0_reg) @[dbg.scala 311:43]
|
|
|
|
|
node _T_476 = or(_T_471, _T_475) @[dbg.scala 310:114]
|
|
|
|
|
node _T_477 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 311:85]
|
|
|
|
|
node _T_478 = bits(_T_477, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_479 = mux(_T_478, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_480 = and(_T_479, sbcs_reg) @[dbg.scala 311:98]
|
|
|
|
|
node _T_481 = or(_T_476, _T_480) @[dbg.scala 311:58]
|
|
|
|
|
node _T_482 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 312:30]
|
|
|
|
|
node _T_483 = bits(_T_482, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_484 = mux(_T_483, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_485 = and(_T_484, sbaddress0_reg) @[dbg.scala 312:43]
|
|
|
|
|
node _T_486 = or(_T_481, _T_485) @[dbg.scala 311:109]
|
|
|
|
|
node _T_487 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 312:87]
|
|
|
|
|
node _T_488 = bits(_T_487, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_489 = mux(_T_488, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_490 = and(_T_489, sbdata0_reg) @[dbg.scala 312:100]
|
|
|
|
|
node _T_491 = or(_T_486, _T_490) @[dbg.scala 312:60]
|
|
|
|
|
node _T_492 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 313:30]
|
|
|
|
|
node _T_493 = bits(_T_492, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_494 = mux(_T_493, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_495 = and(_T_494, sbdata1_reg) @[dbg.scala 313:43]
|
|
|
|
|
node dmi_reg_rdata_din = or(_T_491, _T_495) @[dbg.scala 312:114]
|
|
|
|
|
node _T_496 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 315:49]
|
|
|
|
|
node _T_497 = and(_T_496, temp_rst) @[dbg.scala 315:63]
|
|
|
|
|
node _T_498 = asAsyncReset(_T_497) @[dbg.scala 315:87]
|
|
|
|
|
reg _T_499 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_498, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when dbg_state_en : @[Reg.scala 28:19]
|
|
|
|
|
_T_499 <= dbg_nxtstate @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
dbg_state <= _T_499 @[dbg.scala 315:13]
|
|
|
|
|
node _T_500 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 320:56]
|
|
|
|
|
node _T_501 = asAsyncReset(_T_500) @[dbg.scala 320:83]
|
|
|
|
|
reg _T_502 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_501, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when io.dmi_reg_en : @[Reg.scala 28:19]
|
|
|
|
|
_T_502 <= dmi_reg_rdata_din @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
io.dmi_reg_rdata <= _T_502 @[dbg.scala 320:20]
|
|
|
|
|
node _T_503 = bits(command_reg, 31, 24) @[dbg.scala 324:53]
|
|
|
|
|
node _T_504 = eq(_T_503, UInt<2>("h02")) @[dbg.scala 324:62]
|
|
|
|
|
node _T_505 = bits(data1_reg, 31, 2) @[dbg.scala 324:88]
|
|
|
|
|
node _T_506 = cat(_T_505, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_507 = bits(command_reg, 11, 0) @[dbg.scala 324:133]
|
|
|
|
|
node _T_508 = cat(UInt<20>("h00"), _T_507) @[Cat.scala 29:58]
|
|
|
|
|
node _T_509 = mux(_T_504, _T_506, _T_508) @[dbg.scala 324:40]
|
|
|
|
|
io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_509 @[dbg.scala 324:34]
|
|
|
|
|
node _T_510 = bits(data0_reg, 31, 0) @[dbg.scala 325:50]
|
|
|
|
|
io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_510 @[dbg.scala 325:38]
|
|
|
|
|
node _T_511 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 326:50]
|
|
|
|
|
node _T_512 = bits(abstractcs_reg, 10, 8) @[dbg.scala 326:91]
|
|
|
|
|
node _T_513 = orr(_T_512) @[dbg.scala 326:99]
|
|
|
|
|
node _T_514 = eq(_T_513, UInt<1>("h00")) @[dbg.scala 326:75]
|
|
|
|
|
node _T_515 = and(_T_511, _T_514) @[dbg.scala 326:73]
|
|
|
|
|
node _T_516 = and(_T_515, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 326:104]
|
|
|
|
|
node _T_517 = bits(_T_516, 0, 0) @[dbg.scala 326:141]
|
|
|
|
|
io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_517 @[dbg.scala 326:35]
|
|
|
|
|
node _T_518 = bits(command_reg, 16, 16) @[dbg.scala 327:49]
|
|
|
|
|
node _T_519 = bits(_T_518, 0, 0) @[dbg.scala 327:60]
|
|
|
|
|
io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_519 @[dbg.scala 327:35]
|
|
|
|
|
node _T_520 = bits(command_reg, 31, 24) @[dbg.scala 328:53]
|
|
|
|
|
node _T_521 = eq(_T_520, UInt<2>("h02")) @[dbg.scala 328:62]
|
|
|
|
|
node _T_522 = bits(command_reg, 15, 12) @[dbg.scala 328:108]
|
|
|
|
|
node _T_523 = eq(_T_522, UInt<1>("h00")) @[dbg.scala 328:117]
|
|
|
|
|
node _T_524 = cat(UInt<1>("h00"), _T_523) @[Cat.scala 29:58]
|
|
|
|
|
node _T_525 = mux(_T_521, UInt<2>("h02"), _T_524) @[dbg.scala 328:40]
|
|
|
|
|
io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_525 @[dbg.scala 328:34]
|
|
|
|
|
node _T_526 = bits(command_reg, 21, 20) @[dbg.scala 329:33]
|
|
|
|
|
io.dbg_cmd_size <= _T_526 @[dbg.scala 329:19]
|
|
|
|
|
node _T_527 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 330:47]
|
|
|
|
|
node _T_528 = bits(abstractcs_reg, 10, 8) @[dbg.scala 330:88]
|
|
|
|
|
node _T_529 = orr(_T_528) @[dbg.scala 330:96]
|
|
|
|
|
node _T_530 = eq(_T_529, UInt<1>("h00")) @[dbg.scala 330:72]
|
|
|
|
|
node _T_531 = and(_T_527, _T_530) @[dbg.scala 330:70]
|
|
|
|
|
node _T_532 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 330:114]
|
|
|
|
|
node _T_533 = or(_T_531, _T_532) @[dbg.scala 330:101]
|
|
|
|
|
node _T_534 = bits(_T_533, 0, 0) @[dbg.scala 330:143]
|
|
|
|
|
io.dbg_dma_io.dbg_dma_bubble <= _T_534 @[dbg.scala 330:32]
|
|
|
|
|
wire sb_nxtstate : UInt<4>
|
|
|
|
|
sb_nxtstate <= UInt<4>("h00")
|
|
|
|
|
sb_nxtstate <= UInt<4>("h00") @[dbg.scala 333:15]
|
|
|
|
|
sbcs_sbbusy_wren <= UInt<1>("h00") @[dbg.scala 335:20]
|
|
|
|
|
sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 336:19]
|
|
|
|
|
sbcs_sberror_wren <= UInt<1>("h00") @[dbg.scala 337:21]
|
|
|
|
|
sbcs_sberror_din <= UInt<3>("h00") @[dbg.scala 338:20]
|
|
|
|
|
sbaddress0_reg_wren1 <= UInt<1>("h00") @[dbg.scala 339:24]
|
|
|
|
|
node _T_535 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_535 : @[Conditional.scala 40:58]
|
|
|
|
|
node _T_536 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 342:25]
|
|
|
|
|
sb_nxtstate <= _T_536 @[dbg.scala 342:19]
|
|
|
|
|
node _T_537 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 343:39]
|
|
|
|
|
node _T_538 = or(_T_537, sbreadonaddr_access) @[dbg.scala 343:61]
|
|
|
|
|
sb_state_en <= _T_538 @[dbg.scala 343:19]
|
|
|
|
|
sbcs_sbbusy_wren <= sb_state_en @[dbg.scala 344:24]
|
|
|
|
|
sbcs_sbbusy_din <= UInt<1>("h01") @[dbg.scala 345:23]
|
|
|
|
|
node _T_539 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 346:56]
|
|
|
|
|
node _T_540 = orr(_T_539) @[dbg.scala 346:65]
|
|
|
|
|
node _T_541 = and(sbcs_wren, _T_540) @[dbg.scala 346:38]
|
|
|
|
|
sbcs_sberror_wren <= _T_541 @[dbg.scala 346:25]
|
|
|
|
|
node _T_542 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 347:44]
|
|
|
|
|
node _T_543 = eq(_T_542, UInt<1>("h00")) @[dbg.scala 347:27]
|
|
|
|
|
node _T_544 = bits(sbcs_reg, 14, 12) @[dbg.scala 347:63]
|
|
|
|
|
node _T_545 = and(_T_543, _T_544) @[dbg.scala 347:53]
|
|
|
|
|
sbcs_sberror_din <= _T_545 @[dbg.scala 347:24]
|
|
|
|
|
skip @[Conditional.scala 40:58]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_546 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_546 : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_547 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 350:41]
|
|
|
|
|
node _T_548 = mux(_T_547, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 350:25]
|
|
|
|
|
sb_nxtstate <= _T_548 @[dbg.scala 350:19]
|
|
|
|
|
node _T_549 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 351:40]
|
|
|
|
|
node _T_550 = or(_T_549, sbcs_illegal_size) @[dbg.scala 351:57]
|
|
|
|
|
sb_state_en <= _T_550 @[dbg.scala 351:19]
|
|
|
|
|
node _T_551 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 352:43]
|
|
|
|
|
sbcs_sberror_wren <= _T_551 @[dbg.scala 352:25]
|
|
|
|
|
node _T_552 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[dbg.scala 353:30]
|
|
|
|
|
sbcs_sberror_din <= _T_552 @[dbg.scala 353:24]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_553 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_553 : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_554 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 356:41]
|
|
|
|
|
node _T_555 = mux(_T_554, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 356:25]
|
|
|
|
|
sb_nxtstate <= _T_555 @[dbg.scala 356:19]
|
|
|
|
|
node _T_556 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 357:40]
|
|
|
|
|
node _T_557 = or(_T_556, sbcs_illegal_size) @[dbg.scala 357:57]
|
|
|
|
|
sb_state_en <= _T_557 @[dbg.scala 357:19]
|
|
|
|
|
node _T_558 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 358:43]
|
|
|
|
|
sbcs_sberror_wren <= _T_558 @[dbg.scala 358:25]
|
|
|
|
|
node _T_559 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[dbg.scala 359:30]
|
|
|
|
|
sbcs_sberror_din <= _T_559 @[dbg.scala 359:24]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_560 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_560 : @[Conditional.scala 39:67]
|
|
|
|
|
sb_nxtstate <= UInt<4>("h07") @[dbg.scala 362:19]
|
|
|
|
|
node _T_561 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 363:38]
|
|
|
|
|
sb_state_en <= _T_561 @[dbg.scala 363:19]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_562 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_562 : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_563 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 366:48]
|
|
|
|
|
node _T_564 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 366:95]
|
|
|
|
|
node _T_565 = mux(_T_563, UInt<4>("h08"), _T_564) @[dbg.scala 366:25]
|
|
|
|
|
sb_nxtstate <= _T_565 @[dbg.scala 366:19]
|
|
|
|
|
node _T_566 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 367:45]
|
|
|
|
|
node _T_567 = and(_T_566, io.dbg_bus_clk_en) @[dbg.scala 367:70]
|
|
|
|
|
sb_state_en <= _T_567 @[dbg.scala 367:19]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_568 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_568 : @[Conditional.scala 39:67]
|
|
|
|
|
sb_nxtstate <= UInt<4>("h08") @[dbg.scala 370:19]
|
|
|
|
|
node _T_569 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 371:44]
|
|
|
|
|
sb_state_en <= _T_569 @[dbg.scala 371:19]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_570 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_570 : @[Conditional.scala 39:67]
|
|
|
|
|
sb_nxtstate <= UInt<4>("h08") @[dbg.scala 374:19]
|
|
|
|
|
node _T_571 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 375:44]
|
|
|
|
|
sb_state_en <= _T_571 @[dbg.scala 375:19]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_572 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_572 : @[Conditional.scala 39:67]
|
|
|
|
|
sb_nxtstate <= UInt<4>("h09") @[dbg.scala 378:19]
|
|
|
|
|
node _T_573 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 379:38]
|
|
|
|
|
sb_state_en <= _T_573 @[dbg.scala 379:19]
|
|
|
|
|
node _T_574 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 380:40]
|
|
|
|
|
sbcs_sberror_wren <= _T_574 @[dbg.scala 380:25]
|
|
|
|
|
sbcs_sberror_din <= UInt<2>("h02") @[dbg.scala 381:24]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_575 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_575 : @[Conditional.scala 39:67]
|
|
|
|
|
sb_nxtstate <= UInt<4>("h09") @[dbg.scala 384:19]
|
|
|
|
|
node _T_576 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 385:39]
|
|
|
|
|
sb_state_en <= _T_576 @[dbg.scala 385:19]
|
|
|
|
|
node _T_577 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 386:40]
|
|
|
|
|
sbcs_sberror_wren <= _T_577 @[dbg.scala 386:25]
|
|
|
|
|
sbcs_sberror_din <= UInt<2>("h02") @[dbg.scala 387:24]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
else : @[Conditional.scala 39:67]
|
|
|
|
|
node _T_578 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30]
|
|
|
|
|
when _T_578 : @[Conditional.scala 39:67]
|
|
|
|
|
sb_nxtstate <= UInt<4>("h00") @[dbg.scala 390:19]
|
|
|
|
|
sb_state_en <= UInt<1>("h01") @[dbg.scala 391:19]
|
|
|
|
|
sbcs_sbbusy_wren <= UInt<1>("h01") @[dbg.scala 392:24]
|
|
|
|
|
sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 393:23]
|
|
|
|
|
node _T_579 = bits(sbcs_reg, 16, 16) @[dbg.scala 394:39]
|
|
|
|
|
sbaddress0_reg_wren1 <= _T_579 @[dbg.scala 394:28]
|
|
|
|
|
skip @[Conditional.scala 39:67]
|
|
|
|
|
node _T_580 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 397:47]
|
|
|
|
|
node _T_581 = asAsyncReset(_T_580) @[dbg.scala 397:74]
|
|
|
|
|
reg _T_582 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_581, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when sb_state_en : @[Reg.scala 28:19]
|
|
|
|
|
_T_582 <= sb_nxtstate @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
sb_state <= _T_582 @[dbg.scala 397:12]
|
|
|
|
|
node _T_583 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 401:41]
|
|
|
|
|
sb_bus_cmd_read <= _T_583 @[dbg.scala 401:19]
|
|
|
|
|
node _T_584 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 402:47]
|
|
|
|
|
sb_bus_cmd_write_addr <= _T_584 @[dbg.scala 402:25]
|
|
|
|
|
node _T_585 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 403:46]
|
|
|
|
|
sb_bus_cmd_write_data <= _T_585 @[dbg.scala 403:25]
|
|
|
|
|
node _T_586 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 404:40]
|
|
|
|
|
sb_bus_rsp_read <= _T_586 @[dbg.scala 404:19]
|
|
|
|
|
node _T_587 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 405:41]
|
|
|
|
|
sb_bus_rsp_write <= _T_587 @[dbg.scala 405:20]
|
|
|
|
|
node _T_588 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 406:62]
|
|
|
|
|
node _T_589 = orr(_T_588) @[dbg.scala 406:69]
|
|
|
|
|
node _T_590 = and(sb_bus_rsp_read, _T_589) @[dbg.scala 406:39]
|
|
|
|
|
node _T_591 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 406:115]
|
|
|
|
|
node _T_592 = orr(_T_591) @[dbg.scala 406:122]
|
|
|
|
|
node _T_593 = and(sb_bus_rsp_write, _T_592) @[dbg.scala 406:92]
|
|
|
|
|
node _T_594 = or(_T_590, _T_593) @[dbg.scala 406:73]
|
|
|
|
|
sb_bus_rsp_error <= _T_594 @[dbg.scala 406:20]
|
|
|
|
|
node _T_595 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 407:36]
|
|
|
|
|
node _T_596 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 407:71]
|
|
|
|
|
node _T_597 = or(_T_595, _T_596) @[dbg.scala 407:59]
|
|
|
|
|
node _T_598 = bits(_T_597, 0, 0) @[dbg.scala 407:106]
|
|
|
|
|
io.sb_axi.aw.valid <= _T_598 @[dbg.scala 407:22]
|
|
|
|
|
io.sb_axi.aw.bits.addr <= sbaddress0_reg @[dbg.scala 408:26]
|
|
|
|
|
io.sb_axi.aw.bits.id <= UInt<1>("h00") @[dbg.scala 409:24]
|
|
|
|
|
node _T_599 = bits(sbcs_reg, 19, 17) @[dbg.scala 410:37]
|
|
|
|
|
io.sb_axi.aw.bits.size <= _T_599 @[dbg.scala 410:26]
|
|
|
|
|
io.sb_axi.aw.bits.prot <= UInt<1>("h00") @[dbg.scala 411:26]
|
|
|
|
|
io.sb_axi.aw.bits.cache <= UInt<4>("h0f") @[dbg.scala 412:27]
|
|
|
|
|
node _T_600 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 413:45]
|
|
|
|
|
io.sb_axi.aw.bits.region <= _T_600 @[dbg.scala 413:28]
|
|
|
|
|
io.sb_axi.aw.bits.len <= UInt<1>("h00") @[dbg.scala 414:25]
|
|
|
|
|
io.sb_axi.aw.bits.burst <= UInt<1>("h01") @[dbg.scala 415:27]
|
|
|
|
|
io.sb_axi.aw.bits.qos <= UInt<1>("h00") @[dbg.scala 416:25]
|
|
|
|
|
io.sb_axi.aw.bits.lock <= UInt<1>("h00") @[dbg.scala 417:26]
|
|
|
|
|
node _T_601 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 418:35]
|
|
|
|
|
node _T_602 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 418:70]
|
|
|
|
|
node _T_603 = or(_T_601, _T_602) @[dbg.scala 418:58]
|
|
|
|
|
node _T_604 = bits(_T_603, 0, 0) @[dbg.scala 418:105]
|
|
|
|
|
io.sb_axi.w.valid <= _T_604 @[dbg.scala 418:21]
|
|
|
|
|
node _T_605 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:46]
|
|
|
|
|
node _T_606 = eq(_T_605, UInt<1>("h00")) @[dbg.scala 419:55]
|
|
|
|
|
node _T_607 = bits(_T_606, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_608 = mux(_T_607, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_609 = bits(sbdata0_reg, 7, 0) @[dbg.scala 419:87]
|
|
|
|
|
node _T_610 = cat(_T_609, _T_609) @[Cat.scala 29:58]
|
|
|
|
|
node _T_611 = cat(_T_610, _T_610) @[Cat.scala 29:58]
|
|
|
|
|
node _T_612 = cat(_T_611, _T_611) @[Cat.scala 29:58]
|
|
|
|
|
node _T_613 = and(_T_608, _T_612) @[dbg.scala 419:65]
|
|
|
|
|
node _T_614 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:116]
|
|
|
|
|
node _T_615 = eq(_T_614, UInt<1>("h01")) @[dbg.scala 419:125]
|
|
|
|
|
node _T_616 = bits(_T_615, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_617 = mux(_T_616, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_618 = bits(sbdata0_reg, 15, 0) @[dbg.scala 419:159]
|
|
|
|
|
node _T_619 = cat(_T_618, _T_618) @[Cat.scala 29:58]
|
|
|
|
|
node _T_620 = cat(_T_619, _T_619) @[Cat.scala 29:58]
|
|
|
|
|
node _T_621 = and(_T_617, _T_620) @[dbg.scala 419:138]
|
|
|
|
|
node _T_622 = or(_T_613, _T_621) @[dbg.scala 419:96]
|
|
|
|
|
node _T_623 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:23]
|
|
|
|
|
node _T_624 = eq(_T_623, UInt<2>("h02")) @[dbg.scala 420:32]
|
|
|
|
|
node _T_625 = bits(_T_624, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_626 = mux(_T_625, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_627 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:67]
|
|
|
|
|
node _T_628 = cat(_T_627, _T_627) @[Cat.scala 29:58]
|
|
|
|
|
node _T_629 = and(_T_626, _T_628) @[dbg.scala 420:45]
|
|
|
|
|
node _T_630 = or(_T_622, _T_629) @[dbg.scala 419:168]
|
|
|
|
|
node _T_631 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:97]
|
|
|
|
|
node _T_632 = eq(_T_631, UInt<2>("h03")) @[dbg.scala 420:106]
|
|
|
|
|
node _T_633 = bits(_T_632, 0, 0) @[Bitwise.scala 72:15]
|
|
|
|
|
node _T_634 = mux(_T_633, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_635 = bits(sbdata1_reg, 31, 0) @[dbg.scala 420:136]
|
|
|
|
|
node _T_636 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:156]
|
|
|
|
|
node _T_637 = cat(_T_635, _T_636) @[Cat.scala 29:58]
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node _T_638 = and(_T_634, _T_637) @[dbg.scala 420:119]
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node _T_639 = or(_T_630, _T_638) @[dbg.scala 420:77]
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io.sb_axi.w.bits.data <= _T_639 @[dbg.scala 419:25]
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node _T_640 = bits(sbcs_reg, 19, 17) @[dbg.scala 422:45]
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node _T_641 = eq(_T_640, UInt<1>("h00")) @[dbg.scala 422:54]
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node _T_642 = bits(_T_641, 0, 0) @[Bitwise.scala 72:15]
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node _T_643 = mux(_T_642, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
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node _T_644 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 422:99]
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node _T_645 = dshl(UInt<8>("h01"), _T_644) @[dbg.scala 422:82]
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node _T_646 = and(_T_643, _T_645) @[dbg.scala 422:67]
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node _T_647 = bits(sbcs_reg, 19, 17) @[dbg.scala 423:22]
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node _T_648 = eq(_T_647, UInt<1>("h01")) @[dbg.scala 423:31]
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node _T_649 = bits(_T_648, 0, 0) @[Bitwise.scala 72:15]
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node _T_650 = mux(_T_649, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
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node _T_651 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 423:80]
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node _T_652 = cat(_T_651, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_653 = dshl(UInt<8>("h03"), _T_652) @[dbg.scala 423:59]
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node _T_654 = and(_T_650, _T_653) @[dbg.scala 423:44]
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node _T_655 = or(_T_646, _T_654) @[dbg.scala 422:107]
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node _T_656 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:22]
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node _T_657 = eq(_T_656, UInt<2>("h02")) @[dbg.scala 424:31]
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node _T_658 = bits(_T_657, 0, 0) @[Bitwise.scala 72:15]
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node _T_659 = mux(_T_658, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
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node _T_660 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 424:80]
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node _T_661 = cat(_T_660, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_662 = dshl(UInt<8>("h0f"), _T_661) @[dbg.scala 424:59]
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node _T_663 = and(_T_659, _T_662) @[dbg.scala 424:44]
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node _T_664 = or(_T_655, _T_663) @[dbg.scala 423:97]
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node _T_665 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:22]
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node _T_666 = eq(_T_665, UInt<2>("h03")) @[dbg.scala 425:31]
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node _T_667 = bits(_T_666, 0, 0) @[Bitwise.scala 72:15]
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node _T_668 = mux(_T_667, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
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node _T_669 = and(_T_668, UInt<8>("h0ff")) @[dbg.scala 425:44]
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node _T_670 = or(_T_664, _T_669) @[dbg.scala 424:95]
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io.sb_axi.w.bits.strb <= _T_670 @[dbg.scala 422:25]
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io.sb_axi.w.bits.last <= UInt<1>("h01") @[dbg.scala 427:25]
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node _T_671 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 428:35]
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node _T_672 = bits(_T_671, 0, 0) @[dbg.scala 428:64]
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io.sb_axi.ar.valid <= _T_672 @[dbg.scala 428:22]
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io.sb_axi.ar.bits.addr <= sbaddress0_reg @[dbg.scala 429:26]
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io.sb_axi.ar.bits.id <= UInt<1>("h00") @[dbg.scala 430:24]
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node _T_673 = bits(sbcs_reg, 19, 17) @[dbg.scala 431:37]
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io.sb_axi.ar.bits.size <= _T_673 @[dbg.scala 431:26]
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io.sb_axi.ar.bits.prot <= UInt<1>("h00") @[dbg.scala 432:26]
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io.sb_axi.ar.bits.cache <= UInt<1>("h00") @[dbg.scala 433:27]
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node _T_674 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 434:45]
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io.sb_axi.ar.bits.region <= _T_674 @[dbg.scala 434:28]
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io.sb_axi.ar.bits.len <= UInt<1>("h00") @[dbg.scala 435:25]
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io.sb_axi.ar.bits.burst <= UInt<1>("h01") @[dbg.scala 436:27]
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io.sb_axi.ar.bits.qos <= UInt<1>("h00") @[dbg.scala 437:25]
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io.sb_axi.ar.bits.lock <= UInt<1>("h00") @[dbg.scala 438:26]
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io.sb_axi.b.ready <= UInt<1>("h01") @[dbg.scala 439:21]
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io.sb_axi.r.ready <= UInt<1>("h01") @[dbg.scala 440:21]
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node _T_675 = bits(sbcs_reg, 19, 17) @[dbg.scala 441:37]
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node _T_676 = eq(_T_675, UInt<1>("h00")) @[dbg.scala 441:46]
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node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15]
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node _T_678 = mux(_T_677, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
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node _T_679 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 441:84]
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node _T_680 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 441:115]
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node _T_681 = mul(UInt<4>("h08"), _T_680) @[dbg.scala 441:99]
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node _T_682 = dshr(_T_679, _T_681) @[dbg.scala 441:92]
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node _T_683 = and(_T_682, UInt<64>("h0ff")) @[dbg.scala 441:123]
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node _T_684 = and(_T_678, _T_683) @[dbg.scala 441:59]
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node _T_685 = bits(sbcs_reg, 19, 17) @[dbg.scala 442:23]
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node _T_686 = eq(_T_685, UInt<1>("h01")) @[dbg.scala 442:32]
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node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15]
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node _T_688 = mux(_T_687, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
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node _T_689 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 442:70]
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node _T_690 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 442:102]
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node _T_691 = mul(UInt<5>("h010"), _T_690) @[dbg.scala 442:86]
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node _T_692 = dshr(_T_689, _T_691) @[dbg.scala 442:78]
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node _T_693 = and(_T_692, UInt<64>("h0ffff")) @[dbg.scala 442:110]
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node _T_694 = and(_T_688, _T_693) @[dbg.scala 442:45]
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node _T_695 = or(_T_684, _T_694) @[dbg.scala 441:140]
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node _T_696 = bits(sbcs_reg, 19, 17) @[dbg.scala 443:23]
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node _T_697 = eq(_T_696, UInt<2>("h02")) @[dbg.scala 443:32]
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node _T_698 = bits(_T_697, 0, 0) @[Bitwise.scala 72:15]
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node _T_699 = mux(_T_698, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
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node _T_700 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 443:70]
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node _T_701 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 443:102]
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node _T_702 = mul(UInt<6>("h020"), _T_701) @[dbg.scala 443:86]
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node _T_703 = dshr(_T_700, _T_702) @[dbg.scala 443:78]
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node _T_704 = and(_T_703, UInt<64>("h0ffffffff")) @[dbg.scala 443:107]
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node _T_705 = and(_T_699, _T_704) @[dbg.scala 443:45]
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node _T_706 = or(_T_695, _T_705) @[dbg.scala 442:129]
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node _T_707 = bits(sbcs_reg, 19, 17) @[dbg.scala 444:23]
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|
node _T_708 = eq(_T_707, UInt<2>("h03")) @[dbg.scala 444:32]
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|
node _T_709 = bits(_T_708, 0, 0) @[Bitwise.scala 72:15]
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|
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|
|
node _T_710 = mux(_T_709, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
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|
node _T_711 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 444:68]
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|
node _T_712 = and(_T_710, _T_711) @[dbg.scala 444:45]
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node _T_713 = or(_T_706, _T_712) @[dbg.scala 443:131]
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sb_bus_rdata <= _T_713 @[dbg.scala 441:16]
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|
io.dbg_dma.dbg_ib.dbg_cmd_addr <= io.dbg_dec.dbg_ib.dbg_cmd_addr @[dbg.scala 447:39]
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|
io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[dbg.scala 448:39]
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|
io.dbg_dma.dbg_ib.dbg_cmd_valid <= io.dbg_dec.dbg_ib.dbg_cmd_valid @[dbg.scala 449:39]
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io.dbg_dma.dbg_ib.dbg_cmd_write <= io.dbg_dec.dbg_ib.dbg_cmd_write @[dbg.scala 450:39]
|
|
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|
|
io.dbg_dma.dbg_ib.dbg_cmd_type <= io.dbg_dec.dbg_ib.dbg_cmd_type @[dbg.scala 451:39]
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