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divider 4 added
2021-01-06 18:04:21 +08:00
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit exu_div_new_3bit_fullshortq :
module exu_div_cls :
input clock : Clock
input reset : Reset
output io : {flip operand : UInt<33>, cls : UInt<5>}
wire cls_zeros : UInt<5>
cls_zeros <= UInt<5>("h00")
wire cls_ones : UInt<5>
cls_ones <= UInt<5>("h00")
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 775:54]
node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 775:54]
node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 775:54]
node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 775:54]
node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 775:54]
node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 775:54]
node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 775:54]
node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 775:54]
node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 775:54]
node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 775:54]
node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 775:54]
node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 775:54]
node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 775:54]
node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 775:54]
node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 775:54]
node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 775:54]
node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 775:54]
node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 775:54]
node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 775:54]
node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 775:54]
node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 775:54]
node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 775:54]
node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 775:54]
node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 775:54]
node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 775:54]
node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 775:54]
node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 775:54]
node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 775:54]
node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 775:54]
node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 775:54]
node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 775:54]
node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 775:54]
node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_67 = mux(_T_7, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_68 = mux(_T_9, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_69 = mux(_T_11, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_70 = mux(_T_13, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_71 = mux(_T_15, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_72 = mux(_T_17, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_73 = mux(_T_19, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_74 = mux(_T_21, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_75 = mux(_T_23, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_76 = mux(_T_25, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_77 = mux(_T_27, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_78 = mux(_T_29, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_79 = mux(_T_31, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_80 = mux(_T_33, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_81 = mux(_T_35, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_82 = mux(_T_37, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_83 = mux(_T_39, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_84 = mux(_T_41, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_85 = mux(_T_43, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_86 = mux(_T_45, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_87 = mux(_T_47, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_88 = mux(_T_49, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_89 = mux(_T_51, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_90 = mux(_T_53, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_91 = mux(_T_55, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_92 = mux(_T_57, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_93 = mux(_T_59, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_94 = mux(_T_61, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_95 = mux(_T_63, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_96 = or(_T_64, _T_65) @[Mux.scala 27:72]
node _T_97 = or(_T_96, _T_66) @[Mux.scala 27:72]
node _T_98 = or(_T_97, _T_67) @[Mux.scala 27:72]
node _T_99 = or(_T_98, _T_68) @[Mux.scala 27:72]
node _T_100 = or(_T_99, _T_69) @[Mux.scala 27:72]
node _T_101 = or(_T_100, _T_70) @[Mux.scala 27:72]
node _T_102 = or(_T_101, _T_71) @[Mux.scala 27:72]
node _T_103 = or(_T_102, _T_72) @[Mux.scala 27:72]
node _T_104 = or(_T_103, _T_73) @[Mux.scala 27:72]
node _T_105 = or(_T_104, _T_74) @[Mux.scala 27:72]
node _T_106 = or(_T_105, _T_75) @[Mux.scala 27:72]
node _T_107 = or(_T_106, _T_76) @[Mux.scala 27:72]
node _T_108 = or(_T_107, _T_77) @[Mux.scala 27:72]
node _T_109 = or(_T_108, _T_78) @[Mux.scala 27:72]
node _T_110 = or(_T_109, _T_79) @[Mux.scala 27:72]
node _T_111 = or(_T_110, _T_80) @[Mux.scala 27:72]
node _T_112 = or(_T_111, _T_81) @[Mux.scala 27:72]
node _T_113 = or(_T_112, _T_82) @[Mux.scala 27:72]
node _T_114 = or(_T_113, _T_83) @[Mux.scala 27:72]
node _T_115 = or(_T_114, _T_84) @[Mux.scala 27:72]
node _T_116 = or(_T_115, _T_85) @[Mux.scala 27:72]
node _T_117 = or(_T_116, _T_86) @[Mux.scala 27:72]
node _T_118 = or(_T_117, _T_87) @[Mux.scala 27:72]
node _T_119 = or(_T_118, _T_88) @[Mux.scala 27:72]
node _T_120 = or(_T_119, _T_89) @[Mux.scala 27:72]
node _T_121 = or(_T_120, _T_90) @[Mux.scala 27:72]
node _T_122 = or(_T_121, _T_91) @[Mux.scala 27:72]
node _T_123 = or(_T_122, _T_92) @[Mux.scala 27:72]
node _T_124 = or(_T_123, _T_93) @[Mux.scala 27:72]
node _T_125 = or(_T_124, _T_94) @[Mux.scala 27:72]
node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72]
wire _T_127 : UInt<5> @[Mux.scala 27:72]
_T_127 <= _T_126 @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
cls_zeros <= _T_127 @[exu_div_ctl.scala 775:13]
node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 777:18]
node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 777:25]
when _T_129 : @[exu_div_ctl.scala 777:44]
cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 777:55]
skip @[exu_div_ctl.scala 777:44]
else : @[exu_div_ctl.scala 778:15]
node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 778:76]
node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 778:76]
node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 778:76]
node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 778:76]
node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 778:76]
node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 778:76]
node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 778:76]
node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 778:76]
node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 778:76]
node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12]
node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 778:76]
node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12]
node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 778:76]
node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 778:76]
node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 778:76]
node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12]
node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 778:76]
node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12]
node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 778:76]
node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 778:76]
node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 778:76]
node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12]
node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 778:76]
node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 778:76]
node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 778:76]
node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12]
node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 778:76]
node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12]
node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 778:76]
node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12]
node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 778:76]
node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 778:76]
node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12]
node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 778:76]
node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 778:76]
node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12]
node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 778:76]
node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 778:76]
node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 778:76]
node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 778:76]
node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 778:76]
node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 778:102]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_287 = mux(_T_148, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_288 = mux(_T_153, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_289 = mux(_T_158, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_290 = mux(_T_163, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_291 = mux(_T_168, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_292 = mux(_T_173, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_293 = mux(_T_178, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_294 = mux(_T_183, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_295 = mux(_T_188, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_296 = mux(_T_193, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_297 = mux(_T_198, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_298 = mux(_T_203, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_299 = mux(_T_208, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_300 = mux(_T_213, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_301 = mux(_T_218, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_302 = mux(_T_223, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_303 = mux(_T_228, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_304 = mux(_T_233, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_305 = mux(_T_238, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_306 = mux(_T_243, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_307 = mux(_T_248, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_308 = mux(_T_253, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_309 = mux(_T_258, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_310 = mux(_T_263, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_311 = mux(_T_268, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_312 = mux(_T_273, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_313 = mux(_T_278, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_314 = mux(_T_283, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_315 = or(_T_284, _T_285) @[Mux.scala 27:72]
node _T_316 = or(_T_315, _T_286) @[Mux.scala 27:72]
node _T_317 = or(_T_316, _T_287) @[Mux.scala 27:72]
node _T_318 = or(_T_317, _T_288) @[Mux.scala 27:72]
node _T_319 = or(_T_318, _T_289) @[Mux.scala 27:72]
node _T_320 = or(_T_319, _T_290) @[Mux.scala 27:72]
node _T_321 = or(_T_320, _T_291) @[Mux.scala 27:72]
node _T_322 = or(_T_321, _T_292) @[Mux.scala 27:72]
node _T_323 = or(_T_322, _T_293) @[Mux.scala 27:72]
node _T_324 = or(_T_323, _T_294) @[Mux.scala 27:72]
node _T_325 = or(_T_324, _T_295) @[Mux.scala 27:72]
node _T_326 = or(_T_325, _T_296) @[Mux.scala 27:72]
node _T_327 = or(_T_326, _T_297) @[Mux.scala 27:72]
node _T_328 = or(_T_327, _T_298) @[Mux.scala 27:72]
node _T_329 = or(_T_328, _T_299) @[Mux.scala 27:72]
node _T_330 = or(_T_329, _T_300) @[Mux.scala 27:72]
node _T_331 = or(_T_330, _T_301) @[Mux.scala 27:72]
node _T_332 = or(_T_331, _T_302) @[Mux.scala 27:72]
node _T_333 = or(_T_332, _T_303) @[Mux.scala 27:72]
node _T_334 = or(_T_333, _T_304) @[Mux.scala 27:72]
node _T_335 = or(_T_334, _T_305) @[Mux.scala 27:72]
node _T_336 = or(_T_335, _T_306) @[Mux.scala 27:72]
node _T_337 = or(_T_336, _T_307) @[Mux.scala 27:72]
node _T_338 = or(_T_337, _T_308) @[Mux.scala 27:72]
node _T_339 = or(_T_338, _T_309) @[Mux.scala 27:72]
node _T_340 = or(_T_339, _T_310) @[Mux.scala 27:72]
node _T_341 = or(_T_340, _T_311) @[Mux.scala 27:72]
node _T_342 = or(_T_341, _T_312) @[Mux.scala 27:72]
node _T_343 = or(_T_342, _T_313) @[Mux.scala 27:72]
node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72]
wire _T_345 : UInt<5> @[Mux.scala 27:72]
_T_345 <= _T_344 @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
cls_ones <= _T_345 @[exu_div_ctl.scala 778:25]
skip @[exu_div_ctl.scala 778:15]
node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 779:27]
node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 779:16]
io.cls <= _T_347 @[exu_div_ctl.scala 779:10]
divider 4 added
2021-01-06 18:04:21 +08:00
module exu_div_cls_1 :
input clock : Clock
input reset : Reset
output io : {flip operand : UInt<33>, cls : UInt<5>}
wire cls_zeros : UInt<5>
cls_zeros <= UInt<5>("h00")
wire cls_ones : UInt<5>
cls_ones <= UInt<5>("h00")
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 775:54]
node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 775:54]
node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 775:54]
node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 775:54]
node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 775:54]
node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 775:54]
node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 775:54]
node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 775:54]
node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 775:54]
node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 775:54]
node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 775:54]
node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 775:54]
node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 775:54]
node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 775:54]
node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 775:54]
node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 775:54]
node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 775:54]
node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 775:54]
node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 775:54]
node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 775:54]
node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 775:54]
node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 775:54]
node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 775:54]
node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 775:54]
node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 775:54]
node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 775:54]
node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 775:54]
node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 775:54]
node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 775:54]
node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 775:54]
node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 775:54]
node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 775:54]
node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 775:63]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_67 = mux(_T_7, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_68 = mux(_T_9, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_69 = mux(_T_11, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_70 = mux(_T_13, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_71 = mux(_T_15, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_72 = mux(_T_17, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_73 = mux(_T_19, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_74 = mux(_T_21, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_75 = mux(_T_23, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_76 = mux(_T_25, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_77 = mux(_T_27, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_78 = mux(_T_29, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_79 = mux(_T_31, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_80 = mux(_T_33, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_81 = mux(_T_35, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_82 = mux(_T_37, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_83 = mux(_T_39, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_84 = mux(_T_41, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_85 = mux(_T_43, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_86 = mux(_T_45, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_87 = mux(_T_47, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_88 = mux(_T_49, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_89 = mux(_T_51, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_90 = mux(_T_53, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_91 = mux(_T_55, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_92 = mux(_T_57, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_93 = mux(_T_59, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_94 = mux(_T_61, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_95 = mux(_T_63, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_96 = or(_T_64, _T_65) @[Mux.scala 27:72]
node _T_97 = or(_T_96, _T_66) @[Mux.scala 27:72]
node _T_98 = or(_T_97, _T_67) @[Mux.scala 27:72]
node _T_99 = or(_T_98, _T_68) @[Mux.scala 27:72]
node _T_100 = or(_T_99, _T_69) @[Mux.scala 27:72]
node _T_101 = or(_T_100, _T_70) @[Mux.scala 27:72]
node _T_102 = or(_T_101, _T_71) @[Mux.scala 27:72]
node _T_103 = or(_T_102, _T_72) @[Mux.scala 27:72]
node _T_104 = or(_T_103, _T_73) @[Mux.scala 27:72]
node _T_105 = or(_T_104, _T_74) @[Mux.scala 27:72]
node _T_106 = or(_T_105, _T_75) @[Mux.scala 27:72]
node _T_107 = or(_T_106, _T_76) @[Mux.scala 27:72]
node _T_108 = or(_T_107, _T_77) @[Mux.scala 27:72]
node _T_109 = or(_T_108, _T_78) @[Mux.scala 27:72]
node _T_110 = or(_T_109, _T_79) @[Mux.scala 27:72]
node _T_111 = or(_T_110, _T_80) @[Mux.scala 27:72]
node _T_112 = or(_T_111, _T_81) @[Mux.scala 27:72]
node _T_113 = or(_T_112, _T_82) @[Mux.scala 27:72]
node _T_114 = or(_T_113, _T_83) @[Mux.scala 27:72]
node _T_115 = or(_T_114, _T_84) @[Mux.scala 27:72]
node _T_116 = or(_T_115, _T_85) @[Mux.scala 27:72]
node _T_117 = or(_T_116, _T_86) @[Mux.scala 27:72]
node _T_118 = or(_T_117, _T_87) @[Mux.scala 27:72]
node _T_119 = or(_T_118, _T_88) @[Mux.scala 27:72]
node _T_120 = or(_T_119, _T_89) @[Mux.scala 27:72]
node _T_121 = or(_T_120, _T_90) @[Mux.scala 27:72]
node _T_122 = or(_T_121, _T_91) @[Mux.scala 27:72]
node _T_123 = or(_T_122, _T_92) @[Mux.scala 27:72]
node _T_124 = or(_T_123, _T_93) @[Mux.scala 27:72]
node _T_125 = or(_T_124, _T_94) @[Mux.scala 27:72]
node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72]
wire _T_127 : UInt<5> @[Mux.scala 27:72]
_T_127 <= _T_126 @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
cls_zeros <= _T_127 @[exu_div_ctl.scala 775:13]
node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 777:18]
node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 777:25]
when _T_129 : @[exu_div_ctl.scala 777:44]
cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 777:55]
skip @[exu_div_ctl.scala 777:44]
else : @[exu_div_ctl.scala 778:15]
node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 778:76]
node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 778:76]
node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 778:76]
node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 778:76]
node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 778:76]
node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 778:76]
node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 778:76]
node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 778:76]
node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 778:76]
node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12]
node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 778:76]
node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12]
node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 778:76]
node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 778:76]
node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 778:76]
node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12]
node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 778:76]
node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12]
node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 778:76]
node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 778:76]
node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 778:76]
node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12]
node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 778:76]
node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 778:76]
node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 778:76]
node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12]
node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 778:76]
node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12]
node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 778:76]
node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12]
node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 778:76]
node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 778:76]
node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12]
node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 778:76]
node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 778:76]
node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12]
node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 778:76]
node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 778:76]
node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 778:76]
node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 778:76]
node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 778:102]
node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 778:66]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 778:76]
node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 778:102]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_287 = mux(_T_148, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_288 = mux(_T_153, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_289 = mux(_T_158, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_290 = mux(_T_163, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_291 = mux(_T_168, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_292 = mux(_T_173, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_293 = mux(_T_178, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_294 = mux(_T_183, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_295 = mux(_T_188, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_296 = mux(_T_193, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_297 = mux(_T_198, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_298 = mux(_T_203, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_299 = mux(_T_208, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_300 = mux(_T_213, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_301 = mux(_T_218, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_302 = mux(_T_223, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_303 = mux(_T_228, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_304 = mux(_T_233, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_305 = mux(_T_238, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_306 = mux(_T_243, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_307 = mux(_T_248, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_308 = mux(_T_253, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_309 = mux(_T_258, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_310 = mux(_T_263, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_311 = mux(_T_268, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_312 = mux(_T_273, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_313 = mux(_T_278, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_314 = mux(_T_283, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_315 = or(_T_284, _T_285) @[Mux.scala 27:72]
node _T_316 = or(_T_315, _T_286) @[Mux.scala 27:72]
node _T_317 = or(_T_316, _T_287) @[Mux.scala 27:72]
node _T_318 = or(_T_317, _T_288) @[Mux.scala 27:72]
node _T_319 = or(_T_318, _T_289) @[Mux.scala 27:72]
node _T_320 = or(_T_319, _T_290) @[Mux.scala 27:72]
node _T_321 = or(_T_320, _T_291) @[Mux.scala 27:72]
node _T_322 = or(_T_321, _T_292) @[Mux.scala 27:72]
node _T_323 = or(_T_322, _T_293) @[Mux.scala 27:72]
node _T_324 = or(_T_323, _T_294) @[Mux.scala 27:72]
node _T_325 = or(_T_324, _T_295) @[Mux.scala 27:72]
node _T_326 = or(_T_325, _T_296) @[Mux.scala 27:72]
node _T_327 = or(_T_326, _T_297) @[Mux.scala 27:72]
node _T_328 = or(_T_327, _T_298) @[Mux.scala 27:72]
node _T_329 = or(_T_328, _T_299) @[Mux.scala 27:72]
node _T_330 = or(_T_329, _T_300) @[Mux.scala 27:72]
node _T_331 = or(_T_330, _T_301) @[Mux.scala 27:72]
node _T_332 = or(_T_331, _T_302) @[Mux.scala 27:72]
node _T_333 = or(_T_332, _T_303) @[Mux.scala 27:72]
node _T_334 = or(_T_333, _T_304) @[Mux.scala 27:72]
node _T_335 = or(_T_334, _T_305) @[Mux.scala 27:72]
node _T_336 = or(_T_335, _T_306) @[Mux.scala 27:72]
node _T_337 = or(_T_336, _T_307) @[Mux.scala 27:72]
node _T_338 = or(_T_337, _T_308) @[Mux.scala 27:72]
node _T_339 = or(_T_338, _T_309) @[Mux.scala 27:72]
node _T_340 = or(_T_339, _T_310) @[Mux.scala 27:72]
node _T_341 = or(_T_340, _T_311) @[Mux.scala 27:72]
node _T_342 = or(_T_341, _T_312) @[Mux.scala 27:72]
node _T_343 = or(_T_342, _T_313) @[Mux.scala 27:72]
node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72]
wire _T_345 : UInt<5> @[Mux.scala 27:72]
_T_345 <= _T_344 @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
cls_ones <= _T_345 @[exu_div_ctl.scala 778:25]
skip @[exu_div_ctl.scala 778:15]
node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 779:27]
node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 779:16]
io.cls <= _T_347 @[exu_div_ctl.scala 779:10]
divider 4 added
2021-01-06 18:04:21 +08:00
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_4 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_5 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_5 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_6 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_7 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_8 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_8 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_9 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_9 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_10 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_10 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_10 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
module exu_div_new_3bit_fullshortq :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip cancel : UInt<1>, flip valid_in : UInt<1>, flip signed_in : UInt<1>, flip rem_in : UInt<1>, flip dividend_in : UInt<32>, flip divisor_in : UInt<32>, data_out : UInt<32>, valid_out : UInt<1>}
wire valid_ff : UInt<1>
valid_ff <= UInt<1>("h00")
wire finish_ff : UInt<1>
finish_ff <= UInt<1>("h00")
wire control_ff : UInt<3>
control_ff <= UInt<3>("h00")
wire count_ff : UInt<7>
count_ff <= UInt<7>("h00")
wire smallnum : UInt<4>
smallnum <= UInt<4>("h00")
wire a_ff : UInt<33>
a_ff <= UInt<33>("h00")
wire b_ff1 : UInt<33>
b_ff1 <= UInt<33>("h00")
wire b_ff : UInt<37>
b_ff <= UInt<37>("h00")
wire q_ff : UInt<32>
q_ff <= UInt<32>("h00")
wire r_ff : UInt<33>
r_ff <= UInt<33>("h00")
wire quotient_raw : UInt<8>
quotient_raw <= UInt<8>("h00")
wire quotient_new : UInt<3>
quotient_new <= UInt<3>("h00")
wire shortq_enable : UInt<1>
shortq_enable <= UInt<1>("h00")
wire shortq_enable_ff : UInt<1>
shortq_enable_ff <= UInt<1>("h00")
wire by_zero_case_ff : UInt<1>
by_zero_case_ff <= UInt<1>("h00")
wire ar_shifted : UInt<66>
ar_shifted <= UInt<66>("h00")
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
wire shortq_shift : UInt<5>
shortq_shift <= UInt<5>("h00")
divider 4 added
2021-01-06 18:04:21 +08:00
wire shortq_decode : UInt<5>
shortq_decode <= UInt<5>("h00")
wire shortq_shift_ff : UInt<5>
shortq_shift_ff <= UInt<5>("h00")
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 605:35]
node valid_ff_in = and(io.valid_in, _T) @[exu_div_ctl.scala 605:33]
node _T_1 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 606:35]
node _T_2 = bits(control_ff, 2, 2) @[exu_div_ctl.scala 606:60]
node _T_3 = and(_T_1, _T_2) @[exu_div_ctl.scala 606:48]
node _T_4 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 606:80]
node _T_5 = bits(io.dividend_in, 31, 31) @[exu_div_ctl.scala 606:112]
node _T_6 = and(_T_4, _T_5) @[exu_div_ctl.scala 606:96]
node _T_7 = or(_T_3, _T_6) @[exu_div_ctl.scala 606:65]
node _T_8 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 606:120]
node _T_9 = bits(control_ff, 1, 1) @[exu_div_ctl.scala 606:145]
node _T_10 = and(_T_8, _T_9) @[exu_div_ctl.scala 606:133]
node _T_11 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 606:165]
node _T_12 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 606:197]
node _T_13 = and(_T_11, _T_12) @[exu_div_ctl.scala 606:181]
node _T_14 = or(_T_10, _T_13) @[exu_div_ctl.scala 606:150]
node _T_15 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 606:205]
node _T_16 = bits(control_ff, 0, 0) @[exu_div_ctl.scala 606:230]
node _T_17 = and(_T_15, _T_16) @[exu_div_ctl.scala 606:218]
node _T_18 = and(io.valid_in, io.rem_in) @[exu_div_ctl.scala 606:250]
node _T_19 = or(_T_17, _T_18) @[exu_div_ctl.scala 606:235]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_20 = cat(_T_7, _T_14) @[Cat.scala 29:58]
node control_in = cat(_T_20, _T_19) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node dividend_sign_ff = bits(control_ff, 2, 2) @[exu_div_ctl.scala 607:40]
node divisor_sign_ff = bits(control_ff, 1, 1) @[exu_div_ctl.scala 608:40]
node rem_ff = bits(control_ff, 0, 0) @[exu_div_ctl.scala 609:40]
node _T_21 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 610:47]
node _T_22 = eq(_T_21, UInt<1>("h00")) @[exu_div_ctl.scala 610:54]
node by_zero_case = and(valid_ff, _T_22) @[exu_div_ctl.scala 610:40]
node _T_23 = bits(a_ff, 31, 4) @[exu_div_ctl.scala 612:30]
node _T_24 = eq(_T_23, UInt<1>("h00")) @[exu_div_ctl.scala 612:37]
node _T_25 = bits(b_ff, 31, 4) @[exu_div_ctl.scala 612:53]
node _T_26 = eq(_T_25, UInt<1>("h00")) @[exu_div_ctl.scala 612:60]
node _T_27 = and(_T_24, _T_26) @[exu_div_ctl.scala 612:46]
node _T_28 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 612:71]
node _T_29 = and(_T_27, _T_28) @[exu_div_ctl.scala 612:69]
node _T_30 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 612:87]
node _T_31 = and(_T_29, _T_30) @[exu_div_ctl.scala 612:85]
node _T_32 = and(_T_31, valid_ff) @[exu_div_ctl.scala 612:95]
node _T_33 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 612:108]
node _T_34 = and(_T_32, _T_33) @[exu_div_ctl.scala 612:106]
node _T_35 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 613:11]
node _T_36 = eq(_T_35, UInt<1>("h00")) @[exu_div_ctl.scala 613:18]
node _T_37 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 613:29]
node _T_38 = and(_T_36, _T_37) @[exu_div_ctl.scala 613:27]
node _T_39 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 613:45]
node _T_40 = and(_T_38, _T_39) @[exu_div_ctl.scala 613:43]
node _T_41 = and(_T_40, valid_ff) @[exu_div_ctl.scala 613:53]
node _T_42 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 613:66]
node _T_43 = and(_T_41, _T_42) @[exu_div_ctl.scala 613:64]
node smallnum_case = or(_T_34, _T_43) @[exu_div_ctl.scala 612:120]
node _T_44 = orr(count_ff) @[exu_div_ctl.scala 614:42]
node running_state = or(_T_44, shortq_enable_ff) @[exu_div_ctl.scala 614:45]
node _T_45 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 615:43]
node _T_46 = or(_T_45, io.cancel) @[exu_div_ctl.scala 615:54]
node _T_47 = or(_T_46, running_state) @[exu_div_ctl.scala 615:66]
node misc_enable = or(_T_47, finish_ff) @[exu_div_ctl.scala 615:82]
node _T_48 = or(smallnum_case, by_zero_case) @[exu_div_ctl.scala 616:45]
node _T_49 = eq(count_ff, UInt<6>("h021")) @[exu_div_ctl.scala 616:72]
node finish_raw = or(_T_48, _T_49) @[exu_div_ctl.scala 616:60]
node _T_50 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 617:43]
node finish = and(finish_raw, _T_50) @[exu_div_ctl.scala 617:41]
node _T_51 = or(valid_ff, running_state) @[exu_div_ctl.scala 618:40]
node _T_52 = eq(finish, UInt<1>("h00")) @[exu_div_ctl.scala 618:59]
node _T_53 = and(_T_51, _T_52) @[exu_div_ctl.scala 618:57]
node _T_54 = eq(finish_ff, UInt<1>("h00")) @[exu_div_ctl.scala 618:69]
node _T_55 = and(_T_53, _T_54) @[exu_div_ctl.scala 618:67]
node _T_56 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 618:82]
node _T_57 = and(_T_55, _T_56) @[exu_div_ctl.scala 618:80]
node _T_58 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 618:95]
node count_enable = and(_T_57, _T_58) @[exu_div_ctl.scala 618:93]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_59 = bits(count_enable, 0, 0) @[Bitwise.scala 72:15]
node _T_60 = mux(_T_59, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
node _T_61 = cat(UInt<5>("h00"), UInt<2>("h03")) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_62 = add(count_ff, _T_61) @[exu_div_ctl.scala 619:63]
node _T_63 = tail(_T_62, 1) @[exu_div_ctl.scala 619:63]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_64 = cat(UInt<2>("h00"), shortq_shift_ff) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_65 = add(_T_63, _T_64) @[exu_div_ctl.scala 619:88]
node _T_66 = tail(_T_65, 1) @[exu_div_ctl.scala 619:88]
node count_in = and(_T_60, _T_66) @[exu_div_ctl.scala 619:51]
node a_enable = or(io.valid_in, running_state) @[exu_div_ctl.scala 620:43]
node _T_67 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 621:47]
node a_shift = and(running_state, _T_67) @[exu_div_ctl.scala 621:45]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_68 = bits(dividend_sign_ff, 0, 0) @[Bitwise.scala 72:15]
node _T_69 = mux(_T_68, UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12]
node _T_70 = cat(_T_69, a_ff) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_71 = bits(shortq_shift_ff, 4, 0) @[exu_div_ctl.scala 622:86]
node _T_72 = dshl(_T_70, _T_71) @[exu_div_ctl.scala 622:68]
ar_shifted <= _T_72 @[exu_div_ctl.scala 622:28]
node _T_73 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 623:61]
node _T_74 = eq(_T_73, UInt<1>("h00")) @[exu_div_ctl.scala 623:42]
node b_twos_comp = and(valid_ff, _T_74) @[exu_div_ctl.scala 623:40]
node _T_75 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 624:62]
node _T_76 = eq(_T_75, UInt<1>("h00")) @[exu_div_ctl.scala 624:43]
node twos_comp_b_sel = and(valid_ff, _T_76) @[exu_div_ctl.scala 624:41]
node _T_77 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 625:30]
node _T_78 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 625:42]
node _T_79 = and(_T_77, _T_78) @[exu_div_ctl.scala 625:40]
node _T_80 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 625:71]
node _T_81 = and(_T_79, _T_80) @[exu_div_ctl.scala 625:50]
node _T_82 = eq(by_zero_case_ff, UInt<1>("h00")) @[exu_div_ctl.scala 625:92]
node twos_comp_q_sel = and(_T_81, _T_82) @[exu_div_ctl.scala 625:90]
node b_enable = or(io.valid_in, b_twos_comp) @[exu_div_ctl.scala 626:43]
node _T_83 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 627:43]
node rq_enable = or(_T_83, running_state) @[exu_div_ctl.scala 627:54]
node _T_84 = and(valid_ff, dividend_sign_ff) @[exu_div_ctl.scala 628:40]
node _T_85 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 628:61]
node r_sign_sel = and(_T_84, _T_85) @[exu_div_ctl.scala 628:59]
node _T_86 = eq(quotient_new, UInt<1>("h00")) @[exu_div_ctl.scala 629:61]
node _T_87 = and(running_state, _T_86) @[exu_div_ctl.scala 629:45]
node _T_88 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 629:72]
node r_restore_sel = and(_T_87, _T_88) @[exu_div_ctl.scala 629:70]
node _T_89 = eq(quotient_new, UInt<1>("h01")) @[exu_div_ctl.scala 630:61]
node _T_90 = and(running_state, _T_89) @[exu_div_ctl.scala 630:45]
node _T_91 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 630:72]
node r_adder1_sel = and(_T_90, _T_91) @[exu_div_ctl.scala 630:70]
node _T_92 = eq(quotient_new, UInt<2>("h02")) @[exu_div_ctl.scala 631:61]
node _T_93 = and(running_state, _T_92) @[exu_div_ctl.scala 631:45]
node _T_94 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 631:72]
node r_adder2_sel = and(_T_93, _T_94) @[exu_div_ctl.scala 631:70]
node _T_95 = eq(quotient_new, UInt<2>("h03")) @[exu_div_ctl.scala 632:61]
node _T_96 = and(running_state, _T_95) @[exu_div_ctl.scala 632:45]
node _T_97 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 632:72]
node r_adder3_sel = and(_T_96, _T_97) @[exu_div_ctl.scala 632:70]
node _T_98 = eq(quotient_new, UInt<3>("h04")) @[exu_div_ctl.scala 633:61]
node _T_99 = and(running_state, _T_98) @[exu_div_ctl.scala 633:45]
node _T_100 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 633:72]
node r_adder4_sel = and(_T_99, _T_100) @[exu_div_ctl.scala 633:70]
node _T_101 = eq(quotient_new, UInt<3>("h05")) @[exu_div_ctl.scala 634:61]
node _T_102 = and(running_state, _T_101) @[exu_div_ctl.scala 634:45]
node _T_103 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 634:72]
node r_adder5_sel = and(_T_102, _T_103) @[exu_div_ctl.scala 634:70]
node _T_104 = eq(quotient_new, UInt<3>("h06")) @[exu_div_ctl.scala 635:61]
node _T_105 = and(running_state, _T_104) @[exu_div_ctl.scala 635:45]
node _T_106 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 635:72]
node r_adder6_sel = and(_T_105, _T_106) @[exu_div_ctl.scala 635:70]
node _T_107 = eq(quotient_new, UInt<3>("h07")) @[exu_div_ctl.scala 636:61]
node _T_108 = and(running_state, _T_107) @[exu_div_ctl.scala 636:45]
node _T_109 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 636:72]
node r_adder7_sel = and(_T_108, _T_109) @[exu_div_ctl.scala 636:70]
node _T_110 = bits(r_ff, 30, 0) @[exu_div_ctl.scala 637:28]
node _T_111 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 637:39]
node _T_112 = cat(_T_110, _T_111) @[Cat.scala 29:58]
node _T_113 = bits(b_ff, 33, 0) @[exu_div_ctl.scala 637:54]
node _T_114 = add(_T_112, _T_113) @[exu_div_ctl.scala 637:48]
node adder1_out = tail(_T_114, 1) @[exu_div_ctl.scala 637:48]
node _T_115 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 638:28]
node _T_116 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 638:39]
node _T_117 = cat(_T_115, _T_116) @[Cat.scala 29:58]
node _T_118 = bits(b_ff, 33, 0) @[exu_div_ctl.scala 638:58]
node _T_119 = cat(_T_118, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_120 = add(_T_117, _T_119) @[exu_div_ctl.scala 638:48]
node adder2_out = tail(_T_120, 1) @[exu_div_ctl.scala 638:48]
node _T_121 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 639:28]
node _T_122 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 639:39]
node _T_123 = cat(_T_121, _T_122) @[Cat.scala 29:58]
node _T_124 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 639:58]
node _T_125 = cat(_T_124, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_126 = add(_T_123, _T_125) @[exu_div_ctl.scala 639:48]
node _T_127 = tail(_T_126, 1) @[exu_div_ctl.scala 639:48]
node _T_128 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 639:76]
node _T_129 = add(_T_127, _T_128) @[exu_div_ctl.scala 639:70]
node adder3_out = tail(_T_129, 1) @[exu_div_ctl.scala 639:70]
node _T_130 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 640:28]
node _T_131 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 640:37]
node _T_132 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 640:48]
node _T_133 = cat(_T_130, _T_131) @[Cat.scala 29:58]
node _T_134 = cat(_T_133, _T_132) @[Cat.scala 29:58]
node _T_135 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 640:67]
node _T_136 = cat(_T_135, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_137 = add(_T_134, _T_136) @[exu_div_ctl.scala 640:57]
node adder4_out = tail(_T_137, 1) @[exu_div_ctl.scala 640:57]
node _T_138 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 641:28]
node _T_139 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 641:37]
node _T_140 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 641:48]
node _T_141 = cat(_T_138, _T_139) @[Cat.scala 29:58]
node _T_142 = cat(_T_141, _T_140) @[Cat.scala 29:58]
node _T_143 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 641:67]
node _T_144 = cat(_T_143, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_145 = add(_T_142, _T_144) @[exu_div_ctl.scala 641:57]
node _T_146 = tail(_T_145, 1) @[exu_div_ctl.scala 641:57]
node _T_147 = add(_T_146, b_ff) @[exu_div_ctl.scala 641:84]
node adder5_out = tail(_T_147, 1) @[exu_div_ctl.scala 641:84]
node _T_148 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 642:28]
node _T_149 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 642:37]
node _T_150 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 642:48]
node _T_151 = cat(_T_148, _T_149) @[Cat.scala 29:58]
node _T_152 = cat(_T_151, _T_150) @[Cat.scala 29:58]
node _T_153 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 642:67]
node _T_154 = cat(_T_153, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_155 = add(_T_152, _T_154) @[exu_div_ctl.scala 642:57]
node _T_156 = tail(_T_155, 1) @[exu_div_ctl.scala 642:57]
node _T_157 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 642:94]
node _T_158 = cat(_T_157, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_159 = add(_T_156, _T_158) @[exu_div_ctl.scala 642:84]
node adder6_out = tail(_T_159, 1) @[exu_div_ctl.scala 642:84]
node _T_160 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 643:28]
node _T_161 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 643:37]
node _T_162 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 643:48]
node _T_163 = cat(_T_160, _T_161) @[Cat.scala 29:58]
node _T_164 = cat(_T_163, _T_162) @[Cat.scala 29:58]
node _T_165 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 643:67]
node _T_166 = cat(_T_165, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_167 = add(_T_164, _T_166) @[exu_div_ctl.scala 643:57]
node _T_168 = tail(_T_167, 1) @[exu_div_ctl.scala 643:57]
node _T_169 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 643:94]
node _T_170 = cat(_T_169, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_171 = add(_T_168, _T_170) @[exu_div_ctl.scala 643:84]
node _T_172 = tail(_T_171, 1) @[exu_div_ctl.scala 643:84]
node _T_173 = add(_T_172, b_ff) @[exu_div_ctl.scala 643:106]
node adder7_out = tail(_T_173, 1) @[exu_div_ctl.scala 643:106]
node _T_174 = bits(adder7_out, 36, 36) @[exu_div_ctl.scala 644:35]
node _T_175 = eq(_T_174, UInt<1>("h00")) @[exu_div_ctl.scala 644:24]
node _T_176 = xor(_T_175, dividend_sign_ff) @[exu_div_ctl.scala 644:40]
node _T_177 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 644:68]
node _T_178 = eq(_T_177, UInt<1>("h00")) @[exu_div_ctl.scala 644:75]
node _T_179 = eq(adder7_out, UInt<1>("h00")) @[exu_div_ctl.scala 644:98]
node _T_180 = and(_T_178, _T_179) @[exu_div_ctl.scala 644:84]
node _T_181 = or(_T_176, _T_180) @[exu_div_ctl.scala 644:60]
node _T_182 = bits(adder6_out, 36, 36) @[exu_div_ctl.scala 645:34]
node _T_183 = eq(_T_182, UInt<1>("h00")) @[exu_div_ctl.scala 645:23]
node _T_184 = xor(_T_183, dividend_sign_ff) @[exu_div_ctl.scala 645:39]
node _T_185 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 645:67]
node _T_186 = eq(_T_185, UInt<1>("h00")) @[exu_div_ctl.scala 645:74]
node _T_187 = eq(adder6_out, UInt<1>("h00")) @[exu_div_ctl.scala 645:97]
node _T_188 = and(_T_186, _T_187) @[exu_div_ctl.scala 645:83]
node _T_189 = or(_T_184, _T_188) @[exu_div_ctl.scala 645:59]
node _T_190 = bits(adder5_out, 36, 36) @[exu_div_ctl.scala 646:34]
node _T_191 = eq(_T_190, UInt<1>("h00")) @[exu_div_ctl.scala 646:23]
node _T_192 = xor(_T_191, dividend_sign_ff) @[exu_div_ctl.scala 646:39]
node _T_193 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 646:67]
node _T_194 = eq(_T_193, UInt<1>("h00")) @[exu_div_ctl.scala 646:74]
node _T_195 = eq(adder5_out, UInt<1>("h00")) @[exu_div_ctl.scala 646:97]
node _T_196 = and(_T_194, _T_195) @[exu_div_ctl.scala 646:83]
node _T_197 = or(_T_192, _T_196) @[exu_div_ctl.scala 646:59]
node _T_198 = bits(adder4_out, 36, 36) @[exu_div_ctl.scala 647:34]
node _T_199 = eq(_T_198, UInt<1>("h00")) @[exu_div_ctl.scala 647:23]
node _T_200 = xor(_T_199, dividend_sign_ff) @[exu_div_ctl.scala 647:39]
node _T_201 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 647:67]
node _T_202 = eq(_T_201, UInt<1>("h00")) @[exu_div_ctl.scala 647:74]
node _T_203 = eq(adder4_out, UInt<1>("h00")) @[exu_div_ctl.scala 647:97]
node _T_204 = and(_T_202, _T_203) @[exu_div_ctl.scala 647:83]
node _T_205 = or(_T_200, _T_204) @[exu_div_ctl.scala 647:59]
node _T_206 = bits(adder3_out, 35, 35) @[exu_div_ctl.scala 648:34]
node _T_207 = eq(_T_206, UInt<1>("h00")) @[exu_div_ctl.scala 648:23]
node _T_208 = xor(_T_207, dividend_sign_ff) @[exu_div_ctl.scala 648:39]
node _T_209 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 648:67]
node _T_210 = eq(_T_209, UInt<1>("h00")) @[exu_div_ctl.scala 648:74]
node _T_211 = eq(adder3_out, UInt<1>("h00")) @[exu_div_ctl.scala 648:97]
node _T_212 = and(_T_210, _T_211) @[exu_div_ctl.scala 648:83]
node _T_213 = or(_T_208, _T_212) @[exu_div_ctl.scala 648:59]
node _T_214 = bits(adder2_out, 34, 34) @[exu_div_ctl.scala 649:34]
node _T_215 = eq(_T_214, UInt<1>("h00")) @[exu_div_ctl.scala 649:23]
node _T_216 = xor(_T_215, dividend_sign_ff) @[exu_div_ctl.scala 649:39]
node _T_217 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 649:67]
node _T_218 = eq(_T_217, UInt<1>("h00")) @[exu_div_ctl.scala 649:74]
node _T_219 = eq(adder2_out, UInt<1>("h00")) @[exu_div_ctl.scala 649:97]
node _T_220 = and(_T_218, _T_219) @[exu_div_ctl.scala 649:83]
node _T_221 = or(_T_216, _T_220) @[exu_div_ctl.scala 649:59]
node _T_222 = bits(adder1_out, 33, 33) @[exu_div_ctl.scala 650:34]
node _T_223 = eq(_T_222, UInt<1>("h00")) @[exu_div_ctl.scala 650:23]
node _T_224 = xor(_T_223, dividend_sign_ff) @[exu_div_ctl.scala 650:39]
node _T_225 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 650:67]
node _T_226 = eq(_T_225, UInt<1>("h00")) @[exu_div_ctl.scala 650:74]
node _T_227 = eq(adder1_out, UInt<1>("h00")) @[exu_div_ctl.scala 650:97]
node _T_228 = and(_T_226, _T_227) @[exu_div_ctl.scala 650:83]
node _T_229 = or(_T_224, _T_228) @[exu_div_ctl.scala 650:59]
node _T_230 = cat(_T_229, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_231 = cat(_T_213, _T_221) @[Cat.scala 29:58]
node _T_232 = cat(_T_231, _T_230) @[Cat.scala 29:58]
node _T_233 = cat(_T_197, _T_205) @[Cat.scala 29:58]
node _T_234 = cat(_T_181, _T_189) @[Cat.scala 29:58]
node _T_235 = cat(_T_234, _T_233) @[Cat.scala 29:58]
node _T_236 = cat(_T_235, _T_232) @[Cat.scala 29:58]
quotient_raw <= _T_236 @[exu_div_ctl.scala 644:16]
node _T_237 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 651:37]
node _T_238 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 651:56]
node _T_239 = or(_T_237, _T_238) @[exu_div_ctl.scala 651:41]
node _T_240 = bits(quotient_raw, 5, 5) @[exu_div_ctl.scala 651:74]
node _T_241 = or(_T_239, _T_240) @[exu_div_ctl.scala 651:60]
node _T_242 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 651:93]
node _T_243 = or(_T_241, _T_242) @[exu_div_ctl.scala 651:78]
node _T_244 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 652:38]
node _T_245 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 652:57]
node _T_246 = or(_T_244, _T_245) @[exu_div_ctl.scala 652:42]
node _T_247 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 652:76]
node _T_248 = eq(_T_247, UInt<1>("h00")) @[exu_div_ctl.scala 652:63]
node _T_249 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 652:94]
node _T_250 = and(_T_248, _T_249) @[exu_div_ctl.scala 652:80]
node _T_251 = or(_T_246, _T_250) @[exu_div_ctl.scala 652:61]
node _T_252 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 652:114]
node _T_253 = eq(_T_252, UInt<1>("h00")) @[exu_div_ctl.scala 652:101]
node _T_254 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 652:132]
node _T_255 = and(_T_253, _T_254) @[exu_div_ctl.scala 652:118]
node _T_256 = or(_T_251, _T_255) @[exu_div_ctl.scala 652:99]
node _T_257 = bits(quotient_raw, 7, 7) @[exu_div_ctl.scala 653:38]
node _T_258 = bits(quotient_raw, 6, 6) @[exu_div_ctl.scala 653:57]
node _T_259 = bits(quotient_raw, 5, 5) @[exu_div_ctl.scala 653:75]
node _T_260 = and(_T_258, _T_259) @[exu_div_ctl.scala 653:61]
node _T_261 = or(_T_257, _T_260) @[exu_div_ctl.scala 653:42]
node _T_262 = bits(quotient_raw, 4, 4) @[exu_div_ctl.scala 653:94]
node _T_263 = eq(_T_262, UInt<1>("h00")) @[exu_div_ctl.scala 653:81]
node _T_264 = bits(quotient_raw, 3, 3) @[exu_div_ctl.scala 653:112]
node _T_265 = and(_T_263, _T_264) @[exu_div_ctl.scala 653:98]
node _T_266 = or(_T_261, _T_265) @[exu_div_ctl.scala 653:79]
node _T_267 = bits(quotient_raw, 2, 2) @[exu_div_ctl.scala 653:132]
node _T_268 = eq(_T_267, UInt<1>("h00")) @[exu_div_ctl.scala 653:119]
node _T_269 = bits(quotient_raw, 1, 1) @[exu_div_ctl.scala 653:150]
node _T_270 = and(_T_268, _T_269) @[exu_div_ctl.scala 653:136]
node _T_271 = or(_T_266, _T_270) @[exu_div_ctl.scala 653:117]
node _T_272 = cat(_T_243, _T_256) @[Cat.scala 29:58]
node _T_273 = cat(_T_272, _T_271) @[Cat.scala 29:58]
quotient_new <= _T_273 @[exu_div_ctl.scala 651:16]
node _T_274 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 656:48]
node _T_275 = mux(twos_comp_q_sel, q_ff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_276 = mux(twos_comp_b_sel, _T_274, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_277 = or(_T_275, _T_276) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
wire twos_comp_in : UInt<32> @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
twos_comp_in <= _T_277 @[Mux.scala 27:72]
wire _T_278 : UInt<1>[31] @[lib.scala 426:20]
node _T_279 = bits(twos_comp_in, 0, 0) @[lib.scala 428:27]
node _T_280 = orr(_T_279) @[lib.scala 428:35]
node _T_281 = bits(twos_comp_in, 1, 1) @[lib.scala 428:44]
node _T_282 = not(_T_281) @[lib.scala 428:40]
node _T_283 = bits(twos_comp_in, 1, 1) @[lib.scala 428:51]
node _T_284 = mux(_T_280, _T_282, _T_283) @[lib.scala 428:23]
_T_278[0] <= _T_284 @[lib.scala 428:17]
node _T_285 = bits(twos_comp_in, 1, 0) @[lib.scala 428:27]
node _T_286 = orr(_T_285) @[lib.scala 428:35]
node _T_287 = bits(twos_comp_in, 2, 2) @[lib.scala 428:44]
node _T_288 = not(_T_287) @[lib.scala 428:40]
node _T_289 = bits(twos_comp_in, 2, 2) @[lib.scala 428:51]
node _T_290 = mux(_T_286, _T_288, _T_289) @[lib.scala 428:23]
_T_278[1] <= _T_290 @[lib.scala 428:17]
node _T_291 = bits(twos_comp_in, 2, 0) @[lib.scala 428:27]
node _T_292 = orr(_T_291) @[lib.scala 428:35]
node _T_293 = bits(twos_comp_in, 3, 3) @[lib.scala 428:44]
node _T_294 = not(_T_293) @[lib.scala 428:40]
node _T_295 = bits(twos_comp_in, 3, 3) @[lib.scala 428:51]
node _T_296 = mux(_T_292, _T_294, _T_295) @[lib.scala 428:23]
_T_278[2] <= _T_296 @[lib.scala 428:17]
node _T_297 = bits(twos_comp_in, 3, 0) @[lib.scala 428:27]
node _T_298 = orr(_T_297) @[lib.scala 428:35]
node _T_299 = bits(twos_comp_in, 4, 4) @[lib.scala 428:44]
node _T_300 = not(_T_299) @[lib.scala 428:40]
node _T_301 = bits(twos_comp_in, 4, 4) @[lib.scala 428:51]
node _T_302 = mux(_T_298, _T_300, _T_301) @[lib.scala 428:23]
_T_278[3] <= _T_302 @[lib.scala 428:17]
node _T_303 = bits(twos_comp_in, 4, 0) @[lib.scala 428:27]
node _T_304 = orr(_T_303) @[lib.scala 428:35]
node _T_305 = bits(twos_comp_in, 5, 5) @[lib.scala 428:44]
node _T_306 = not(_T_305) @[lib.scala 428:40]
node _T_307 = bits(twos_comp_in, 5, 5) @[lib.scala 428:51]
node _T_308 = mux(_T_304, _T_306, _T_307) @[lib.scala 428:23]
_T_278[4] <= _T_308 @[lib.scala 428:17]
node _T_309 = bits(twos_comp_in, 5, 0) @[lib.scala 428:27]
node _T_310 = orr(_T_309) @[lib.scala 428:35]
node _T_311 = bits(twos_comp_in, 6, 6) @[lib.scala 428:44]
node _T_312 = not(_T_311) @[lib.scala 428:40]
node _T_313 = bits(twos_comp_in, 6, 6) @[lib.scala 428:51]
node _T_314 = mux(_T_310, _T_312, _T_313) @[lib.scala 428:23]
_T_278[5] <= _T_314 @[lib.scala 428:17]
node _T_315 = bits(twos_comp_in, 6, 0) @[lib.scala 428:27]
node _T_316 = orr(_T_315) @[lib.scala 428:35]
node _T_317 = bits(twos_comp_in, 7, 7) @[lib.scala 428:44]
node _T_318 = not(_T_317) @[lib.scala 428:40]
node _T_319 = bits(twos_comp_in, 7, 7) @[lib.scala 428:51]
node _T_320 = mux(_T_316, _T_318, _T_319) @[lib.scala 428:23]
_T_278[6] <= _T_320 @[lib.scala 428:17]
node _T_321 = bits(twos_comp_in, 7, 0) @[lib.scala 428:27]
node _T_322 = orr(_T_321) @[lib.scala 428:35]
node _T_323 = bits(twos_comp_in, 8, 8) @[lib.scala 428:44]
node _T_324 = not(_T_323) @[lib.scala 428:40]
node _T_325 = bits(twos_comp_in, 8, 8) @[lib.scala 428:51]
node _T_326 = mux(_T_322, _T_324, _T_325) @[lib.scala 428:23]
_T_278[7] <= _T_326 @[lib.scala 428:17]
node _T_327 = bits(twos_comp_in, 8, 0) @[lib.scala 428:27]
node _T_328 = orr(_T_327) @[lib.scala 428:35]
node _T_329 = bits(twos_comp_in, 9, 9) @[lib.scala 428:44]
node _T_330 = not(_T_329) @[lib.scala 428:40]
node _T_331 = bits(twos_comp_in, 9, 9) @[lib.scala 428:51]
node _T_332 = mux(_T_328, _T_330, _T_331) @[lib.scala 428:23]
_T_278[8] <= _T_332 @[lib.scala 428:17]
node _T_333 = bits(twos_comp_in, 9, 0) @[lib.scala 428:27]
node _T_334 = orr(_T_333) @[lib.scala 428:35]
node _T_335 = bits(twos_comp_in, 10, 10) @[lib.scala 428:44]
node _T_336 = not(_T_335) @[lib.scala 428:40]
node _T_337 = bits(twos_comp_in, 10, 10) @[lib.scala 428:51]
node _T_338 = mux(_T_334, _T_336, _T_337) @[lib.scala 428:23]
_T_278[9] <= _T_338 @[lib.scala 428:17]
node _T_339 = bits(twos_comp_in, 10, 0) @[lib.scala 428:27]
node _T_340 = orr(_T_339) @[lib.scala 428:35]
node _T_341 = bits(twos_comp_in, 11, 11) @[lib.scala 428:44]
node _T_342 = not(_T_341) @[lib.scala 428:40]
node _T_343 = bits(twos_comp_in, 11, 11) @[lib.scala 428:51]
node _T_344 = mux(_T_340, _T_342, _T_343) @[lib.scala 428:23]
_T_278[10] <= _T_344 @[lib.scala 428:17]
node _T_345 = bits(twos_comp_in, 11, 0) @[lib.scala 428:27]
node _T_346 = orr(_T_345) @[lib.scala 428:35]
node _T_347 = bits(twos_comp_in, 12, 12) @[lib.scala 428:44]
node _T_348 = not(_T_347) @[lib.scala 428:40]
node _T_349 = bits(twos_comp_in, 12, 12) @[lib.scala 428:51]
node _T_350 = mux(_T_346, _T_348, _T_349) @[lib.scala 428:23]
_T_278[11] <= _T_350 @[lib.scala 428:17]
node _T_351 = bits(twos_comp_in, 12, 0) @[lib.scala 428:27]
node _T_352 = orr(_T_351) @[lib.scala 428:35]
node _T_353 = bits(twos_comp_in, 13, 13) @[lib.scala 428:44]
node _T_354 = not(_T_353) @[lib.scala 428:40]
node _T_355 = bits(twos_comp_in, 13, 13) @[lib.scala 428:51]
node _T_356 = mux(_T_352, _T_354, _T_355) @[lib.scala 428:23]
_T_278[12] <= _T_356 @[lib.scala 428:17]
node _T_357 = bits(twos_comp_in, 13, 0) @[lib.scala 428:27]
node _T_358 = orr(_T_357) @[lib.scala 428:35]
node _T_359 = bits(twos_comp_in, 14, 14) @[lib.scala 428:44]
node _T_360 = not(_T_359) @[lib.scala 428:40]
node _T_361 = bits(twos_comp_in, 14, 14) @[lib.scala 428:51]
node _T_362 = mux(_T_358, _T_360, _T_361) @[lib.scala 428:23]
_T_278[13] <= _T_362 @[lib.scala 428:17]
node _T_363 = bits(twos_comp_in, 14, 0) @[lib.scala 428:27]
node _T_364 = orr(_T_363) @[lib.scala 428:35]
node _T_365 = bits(twos_comp_in, 15, 15) @[lib.scala 428:44]
node _T_366 = not(_T_365) @[lib.scala 428:40]
node _T_367 = bits(twos_comp_in, 15, 15) @[lib.scala 428:51]
node _T_368 = mux(_T_364, _T_366, _T_367) @[lib.scala 428:23]
_T_278[14] <= _T_368 @[lib.scala 428:17]
node _T_369 = bits(twos_comp_in, 15, 0) @[lib.scala 428:27]
node _T_370 = orr(_T_369) @[lib.scala 428:35]
node _T_371 = bits(twos_comp_in, 16, 16) @[lib.scala 428:44]
node _T_372 = not(_T_371) @[lib.scala 428:40]
node _T_373 = bits(twos_comp_in, 16, 16) @[lib.scala 428:51]
node _T_374 = mux(_T_370, _T_372, _T_373) @[lib.scala 428:23]
_T_278[15] <= _T_374 @[lib.scala 428:17]
node _T_375 = bits(twos_comp_in, 16, 0) @[lib.scala 428:27]
node _T_376 = orr(_T_375) @[lib.scala 428:35]
node _T_377 = bits(twos_comp_in, 17, 17) @[lib.scala 428:44]
node _T_378 = not(_T_377) @[lib.scala 428:40]
node _T_379 = bits(twos_comp_in, 17, 17) @[lib.scala 428:51]
node _T_380 = mux(_T_376, _T_378, _T_379) @[lib.scala 428:23]
_T_278[16] <= _T_380 @[lib.scala 428:17]
node _T_381 = bits(twos_comp_in, 17, 0) @[lib.scala 428:27]
node _T_382 = orr(_T_381) @[lib.scala 428:35]
node _T_383 = bits(twos_comp_in, 18, 18) @[lib.scala 428:44]
node _T_384 = not(_T_383) @[lib.scala 428:40]
node _T_385 = bits(twos_comp_in, 18, 18) @[lib.scala 428:51]
node _T_386 = mux(_T_382, _T_384, _T_385) @[lib.scala 428:23]
_T_278[17] <= _T_386 @[lib.scala 428:17]
node _T_387 = bits(twos_comp_in, 18, 0) @[lib.scala 428:27]
node _T_388 = orr(_T_387) @[lib.scala 428:35]
node _T_389 = bits(twos_comp_in, 19, 19) @[lib.scala 428:44]
node _T_390 = not(_T_389) @[lib.scala 428:40]
node _T_391 = bits(twos_comp_in, 19, 19) @[lib.scala 428:51]
node _T_392 = mux(_T_388, _T_390, _T_391) @[lib.scala 428:23]
_T_278[18] <= _T_392 @[lib.scala 428:17]
node _T_393 = bits(twos_comp_in, 19, 0) @[lib.scala 428:27]
node _T_394 = orr(_T_393) @[lib.scala 428:35]
node _T_395 = bits(twos_comp_in, 20, 20) @[lib.scala 428:44]
node _T_396 = not(_T_395) @[lib.scala 428:40]
node _T_397 = bits(twos_comp_in, 20, 20) @[lib.scala 428:51]
node _T_398 = mux(_T_394, _T_396, _T_397) @[lib.scala 428:23]
_T_278[19] <= _T_398 @[lib.scala 428:17]
node _T_399 = bits(twos_comp_in, 20, 0) @[lib.scala 428:27]
node _T_400 = orr(_T_399) @[lib.scala 428:35]
node _T_401 = bits(twos_comp_in, 21, 21) @[lib.scala 428:44]
node _T_402 = not(_T_401) @[lib.scala 428:40]
node _T_403 = bits(twos_comp_in, 21, 21) @[lib.scala 428:51]
node _T_404 = mux(_T_400, _T_402, _T_403) @[lib.scala 428:23]
_T_278[20] <= _T_404 @[lib.scala 428:17]
node _T_405 = bits(twos_comp_in, 21, 0) @[lib.scala 428:27]
node _T_406 = orr(_T_405) @[lib.scala 428:35]
node _T_407 = bits(twos_comp_in, 22, 22) @[lib.scala 428:44]
node _T_408 = not(_T_407) @[lib.scala 428:40]
node _T_409 = bits(twos_comp_in, 22, 22) @[lib.scala 428:51]
node _T_410 = mux(_T_406, _T_408, _T_409) @[lib.scala 428:23]
_T_278[21] <= _T_410 @[lib.scala 428:17]
node _T_411 = bits(twos_comp_in, 22, 0) @[lib.scala 428:27]
node _T_412 = orr(_T_411) @[lib.scala 428:35]
node _T_413 = bits(twos_comp_in, 23, 23) @[lib.scala 428:44]
node _T_414 = not(_T_413) @[lib.scala 428:40]
node _T_415 = bits(twos_comp_in, 23, 23) @[lib.scala 428:51]
node _T_416 = mux(_T_412, _T_414, _T_415) @[lib.scala 428:23]
_T_278[22] <= _T_416 @[lib.scala 428:17]
node _T_417 = bits(twos_comp_in, 23, 0) @[lib.scala 428:27]
node _T_418 = orr(_T_417) @[lib.scala 428:35]
node _T_419 = bits(twos_comp_in, 24, 24) @[lib.scala 428:44]
node _T_420 = not(_T_419) @[lib.scala 428:40]
node _T_421 = bits(twos_comp_in, 24, 24) @[lib.scala 428:51]
node _T_422 = mux(_T_418, _T_420, _T_421) @[lib.scala 428:23]
_T_278[23] <= _T_422 @[lib.scala 428:17]
node _T_423 = bits(twos_comp_in, 24, 0) @[lib.scala 428:27]
node _T_424 = orr(_T_423) @[lib.scala 428:35]
node _T_425 = bits(twos_comp_in, 25, 25) @[lib.scala 428:44]
node _T_426 = not(_T_425) @[lib.scala 428:40]
node _T_427 = bits(twos_comp_in, 25, 25) @[lib.scala 428:51]
node _T_428 = mux(_T_424, _T_426, _T_427) @[lib.scala 428:23]
_T_278[24] <= _T_428 @[lib.scala 428:17]
node _T_429 = bits(twos_comp_in, 25, 0) @[lib.scala 428:27]
node _T_430 = orr(_T_429) @[lib.scala 428:35]
node _T_431 = bits(twos_comp_in, 26, 26) @[lib.scala 428:44]
node _T_432 = not(_T_431) @[lib.scala 428:40]
node _T_433 = bits(twos_comp_in, 26, 26) @[lib.scala 428:51]
node _T_434 = mux(_T_430, _T_432, _T_433) @[lib.scala 428:23]
_T_278[25] <= _T_434 @[lib.scala 428:17]
node _T_435 = bits(twos_comp_in, 26, 0) @[lib.scala 428:27]
node _T_436 = orr(_T_435) @[lib.scala 428:35]
node _T_437 = bits(twos_comp_in, 27, 27) @[lib.scala 428:44]
node _T_438 = not(_T_437) @[lib.scala 428:40]
node _T_439 = bits(twos_comp_in, 27, 27) @[lib.scala 428:51]
node _T_440 = mux(_T_436, _T_438, _T_439) @[lib.scala 428:23]
_T_278[26] <= _T_440 @[lib.scala 428:17]
node _T_441 = bits(twos_comp_in, 27, 0) @[lib.scala 428:27]
node _T_442 = orr(_T_441) @[lib.scala 428:35]
node _T_443 = bits(twos_comp_in, 28, 28) @[lib.scala 428:44]
node _T_444 = not(_T_443) @[lib.scala 428:40]
node _T_445 = bits(twos_comp_in, 28, 28) @[lib.scala 428:51]
node _T_446 = mux(_T_442, _T_444, _T_445) @[lib.scala 428:23]
_T_278[27] <= _T_446 @[lib.scala 428:17]
node _T_447 = bits(twos_comp_in, 28, 0) @[lib.scala 428:27]
node _T_448 = orr(_T_447) @[lib.scala 428:35]
node _T_449 = bits(twos_comp_in, 29, 29) @[lib.scala 428:44]
node _T_450 = not(_T_449) @[lib.scala 428:40]
node _T_451 = bits(twos_comp_in, 29, 29) @[lib.scala 428:51]
node _T_452 = mux(_T_448, _T_450, _T_451) @[lib.scala 428:23]
_T_278[28] <= _T_452 @[lib.scala 428:17]
node _T_453 = bits(twos_comp_in, 29, 0) @[lib.scala 428:27]
node _T_454 = orr(_T_453) @[lib.scala 428:35]
node _T_455 = bits(twos_comp_in, 30, 30) @[lib.scala 428:44]
node _T_456 = not(_T_455) @[lib.scala 428:40]
node _T_457 = bits(twos_comp_in, 30, 30) @[lib.scala 428:51]
node _T_458 = mux(_T_454, _T_456, _T_457) @[lib.scala 428:23]
_T_278[29] <= _T_458 @[lib.scala 428:17]
node _T_459 = bits(twos_comp_in, 30, 0) @[lib.scala 428:27]
node _T_460 = orr(_T_459) @[lib.scala 428:35]
node _T_461 = bits(twos_comp_in, 31, 31) @[lib.scala 428:44]
node _T_462 = not(_T_461) @[lib.scala 428:40]
node _T_463 = bits(twos_comp_in, 31, 31) @[lib.scala 428:51]
node _T_464 = mux(_T_460, _T_462, _T_463) @[lib.scala 428:23]
_T_278[30] <= _T_464 @[lib.scala 428:17]
node _T_465 = cat(_T_278[2], _T_278[1]) @[lib.scala 430:14]
node _T_466 = cat(_T_465, _T_278[0]) @[lib.scala 430:14]
node _T_467 = cat(_T_278[4], _T_278[3]) @[lib.scala 430:14]
node _T_468 = cat(_T_278[6], _T_278[5]) @[lib.scala 430:14]
node _T_469 = cat(_T_468, _T_467) @[lib.scala 430:14]
node _T_470 = cat(_T_469, _T_466) @[lib.scala 430:14]
node _T_471 = cat(_T_278[8], _T_278[7]) @[lib.scala 430:14]
node _T_472 = cat(_T_278[10], _T_278[9]) @[lib.scala 430:14]
node _T_473 = cat(_T_472, _T_471) @[lib.scala 430:14]
node _T_474 = cat(_T_278[12], _T_278[11]) @[lib.scala 430:14]
node _T_475 = cat(_T_278[14], _T_278[13]) @[lib.scala 430:14]
node _T_476 = cat(_T_475, _T_474) @[lib.scala 430:14]
node _T_477 = cat(_T_476, _T_473) @[lib.scala 430:14]
node _T_478 = cat(_T_477, _T_470) @[lib.scala 430:14]
node _T_479 = cat(_T_278[16], _T_278[15]) @[lib.scala 430:14]
node _T_480 = cat(_T_278[18], _T_278[17]) @[lib.scala 430:14]
node _T_481 = cat(_T_480, _T_479) @[lib.scala 430:14]
node _T_482 = cat(_T_278[20], _T_278[19]) @[lib.scala 430:14]
node _T_483 = cat(_T_278[22], _T_278[21]) @[lib.scala 430:14]
node _T_484 = cat(_T_483, _T_482) @[lib.scala 430:14]
node _T_485 = cat(_T_484, _T_481) @[lib.scala 430:14]
node _T_486 = cat(_T_278[24], _T_278[23]) @[lib.scala 430:14]
node _T_487 = cat(_T_278[26], _T_278[25]) @[lib.scala 430:14]
node _T_488 = cat(_T_487, _T_486) @[lib.scala 430:14]
node _T_489 = cat(_T_278[28], _T_278[27]) @[lib.scala 430:14]
node _T_490 = cat(_T_278[30], _T_278[29]) @[lib.scala 430:14]
node _T_491 = cat(_T_490, _T_489) @[lib.scala 430:14]
node _T_492 = cat(_T_491, _T_488) @[lib.scala 430:14]
node _T_493 = cat(_T_492, _T_485) @[lib.scala 430:14]
node _T_494 = cat(_T_493, _T_478) @[lib.scala 430:14]
node _T_495 = bits(twos_comp_in, 0, 0) @[lib.scala 430:24]
node twos_comp_out = cat(_T_494, _T_495) @[Cat.scala 29:58]
node _T_496 = eq(a_shift, UInt<1>("h00")) @[exu_div_ctl.scala 661:6]
node _T_497 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 661:17]
node _T_498 = and(_T_496, _T_497) @[exu_div_ctl.scala 661:15]
node _T_499 = bits(_T_498, 0, 0) @[exu_div_ctl.scala 661:36]
node _T_500 = bits(io.dividend_in, 31, 31) @[exu_div_ctl.scala 661:79]
node _T_501 = and(io.signed_in, _T_500) @[exu_div_ctl.scala 661:63]
node _T_502 = bits(io.dividend_in, 31, 0) @[exu_div_ctl.scala 661:98]
node _T_503 = cat(_T_501, _T_502) @[Cat.scala 29:58]
node _T_504 = bits(a_ff, 29, 0) @[exu_div_ctl.scala 662:52]
node _T_505 = cat(_T_504, UInt<3>("h00")) @[Cat.scala 29:58]
node _T_506 = bits(ar_shifted, 32, 0) @[exu_div_ctl.scala 663:54]
node _T_507 = mux(_T_499, _T_503, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_508 = mux(a_shift, _T_505, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_509 = mux(shortq_enable_ff, _T_506, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_510 = or(_T_507, _T_508) @[Mux.scala 27:72]
node _T_511 = or(_T_510, _T_509) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
wire a_in : UInt<33> @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
a_in <= _T_511 @[Mux.scala 27:72]
node _T_512 = eq(b_twos_comp, UInt<1>("h00")) @[exu_div_ctl.scala 666:5]
node _T_513 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 666:78]
node _T_514 = and(io.signed_in, _T_513) @[exu_div_ctl.scala 666:63]
node _T_515 = bits(io.divisor_in, 31, 0) @[exu_div_ctl.scala 666:96]
node _T_516 = cat(_T_514, _T_515) @[Cat.scala 29:58]
node _T_517 = eq(divisor_sign_ff, UInt<1>("h00")) @[exu_div_ctl.scala 667:49]
node _T_518 = bits(twos_comp_out, 31, 0) @[exu_div_ctl.scala 667:79]
node _T_519 = cat(_T_517, _T_518) @[Cat.scala 29:58]
node _T_520 = mux(_T_512, _T_516, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_521 = mux(b_twos_comp, _T_519, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_522 = or(_T_520, _T_521) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
wire b_in : UInt<33> @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
b_in <= _T_522 @[Mux.scala 27:72]
node _T_523 = bits(r_ff, 29, 0) @[exu_div_ctl.scala 672:54]
node _T_524 = bits(a_ff, 32, 30) @[exu_div_ctl.scala 672:65]
node _T_525 = cat(_T_523, _T_524) @[Cat.scala 29:58]
node _T_526 = bits(adder1_out, 32, 0) @[exu_div_ctl.scala 673:57]
node _T_527 = bits(adder2_out, 32, 0) @[exu_div_ctl.scala 674:57]
node _T_528 = bits(adder3_out, 32, 0) @[exu_div_ctl.scala 675:57]
node _T_529 = bits(adder4_out, 32, 0) @[exu_div_ctl.scala 676:57]
node _T_530 = bits(adder5_out, 32, 0) @[exu_div_ctl.scala 677:57]
node _T_531 = bits(adder6_out, 32, 0) @[exu_div_ctl.scala 678:57]
node _T_532 = bits(adder7_out, 32, 0) @[exu_div_ctl.scala 679:57]
node _T_533 = bits(ar_shifted, 65, 33) @[exu_div_ctl.scala 680:57]
node _T_534 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 681:59]
node _T_535 = cat(UInt<1>("h00"), _T_534) @[Cat.scala 29:58]
node _T_536 = mux(r_sign_sel, UInt<33>("h01ffffffff"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_537 = mux(r_restore_sel, _T_525, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_538 = mux(r_adder1_sel, _T_526, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_539 = mux(r_adder2_sel, _T_527, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_540 = mux(r_adder3_sel, _T_528, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_541 = mux(r_adder4_sel, _T_529, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_542 = mux(r_adder5_sel, _T_530, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_543 = mux(r_adder6_sel, _T_531, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_544 = mux(r_adder7_sel, _T_532, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_545 = mux(shortq_enable_ff, _T_533, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_546 = mux(by_zero_case, _T_535, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_547 = or(_T_536, _T_537) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_548 = or(_T_547, _T_538) @[Mux.scala 27:72]
node _T_549 = or(_T_548, _T_539) @[Mux.scala 27:72]
node _T_550 = or(_T_549, _T_540) @[Mux.scala 27:72]
node _T_551 = or(_T_550, _T_541) @[Mux.scala 27:72]
node _T_552 = or(_T_551, _T_542) @[Mux.scala 27:72]
node _T_553 = or(_T_552, _T_543) @[Mux.scala 27:72]
node _T_554 = or(_T_553, _T_544) @[Mux.scala 27:72]
node _T_555 = or(_T_554, _T_545) @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_556 = or(_T_555, _T_546) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
wire r_in : UInt<33> @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
r_in <= _T_556 @[Mux.scala 27:72]
node _T_557 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 684:4]
node _T_558 = bits(q_ff, 28, 0) @[exu_div_ctl.scala 684:54]
node _T_559 = cat(_T_558, quotient_new) @[Cat.scala 29:58]
node _T_560 = cat(UInt<28>("h00"), smallnum) @[Cat.scala 29:58]
node _T_561 = mux(UInt<1>("h01"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_562 = mux(_T_557, _T_559, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_563 = mux(smallnum_case, _T_560, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_564 = mux(by_zero_case, _T_561, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_565 = or(_T_562, _T_563) @[Mux.scala 27:72]
node _T_566 = or(_T_565, _T_564) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
wire q_in : UInt<32> @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
q_in <= _T_566 @[Mux.scala 27:72]
node _T_567 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 688:31]
node _T_568 = and(finish_ff, _T_567) @[exu_div_ctl.scala 688:29]
io.valid_out <= _T_568 @[exu_div_ctl.scala 688:16]
node _T_569 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 690:6]
node _T_570 = eq(twos_comp_q_sel, UInt<1>("h00")) @[exu_div_ctl.scala 690:16]
node _T_571 = and(_T_569, _T_570) @[exu_div_ctl.scala 690:14]
node _T_572 = bits(_T_571, 0, 0) @[exu_div_ctl.scala 690:40]
node _T_573 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 691:48]
node _T_574 = mux(_T_572, q_ff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_575 = mux(rem_ff, _T_573, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_576 = mux(twos_comp_q_sel, twos_comp_out, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_577 = or(_T_574, _T_575) @[Mux.scala 27:72]
node _T_578 = or(_T_577, _T_576) @[Mux.scala 27:72]
wire _T_579 : UInt<32> @[Mux.scala 27:72]
_T_579 <= _T_578 @[Mux.scala 27:72]
io.data_out <= _T_579 @[exu_div_ctl.scala 689:15]
node _T_580 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_581 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_582 = eq(_T_581, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_583 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_584 = eq(_T_583, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_585 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_586 = eq(_T_585, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_587 = and(_T_582, _T_584) @[exu_div_ctl.scala 696:95]
node _T_588 = and(_T_587, _T_586) @[exu_div_ctl.scala 696:95]
node _T_589 = and(_T_580, _T_588) @[exu_div_ctl.scala 697:11]
node _T_590 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_591 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_592 = eq(_T_591, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_593 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_594 = eq(_T_593, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_595 = and(_T_592, _T_594) @[exu_div_ctl.scala 696:95]
node _T_596 = and(_T_590, _T_595) @[exu_div_ctl.scala 697:11]
node _T_597 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 702:38]
node _T_598 = eq(_T_597, UInt<1>("h00")) @[exu_div_ctl.scala 702:33]
node _T_599 = and(_T_596, _T_598) @[exu_div_ctl.scala 702:31]
node _T_600 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_601 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_602 = eq(_T_601, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_603 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_604 = eq(_T_603, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_605 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_606 = eq(_T_605, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_607 = and(_T_602, _T_604) @[exu_div_ctl.scala 696:95]
node _T_608 = and(_T_607, _T_606) @[exu_div_ctl.scala 696:95]
node _T_609 = and(_T_600, _T_608) @[exu_div_ctl.scala 697:11]
node _T_610 = or(_T_599, _T_609) @[exu_div_ctl.scala 702:42]
node _T_611 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_612 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_613 = and(_T_611, _T_612) @[exu_div_ctl.scala 695:95]
node _T_614 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_615 = eq(_T_614, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_616 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_617 = eq(_T_616, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_618 = and(_T_615, _T_617) @[exu_div_ctl.scala 696:95]
node _T_619 = and(_T_613, _T_618) @[exu_div_ctl.scala 697:11]
node _T_620 = or(_T_610, _T_619) @[exu_div_ctl.scala 702:75]
node _T_621 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_622 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_623 = eq(_T_622, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_624 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_625 = eq(_T_624, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_626 = and(_T_623, _T_625) @[exu_div_ctl.scala 696:95]
node _T_627 = and(_T_621, _T_626) @[exu_div_ctl.scala 697:11]
node _T_628 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 704:38]
node _T_629 = eq(_T_628, UInt<1>("h00")) @[exu_div_ctl.scala 704:33]
node _T_630 = and(_T_627, _T_629) @[exu_div_ctl.scala 704:31]
node _T_631 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_632 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_633 = eq(_T_632, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_634 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_635 = eq(_T_634, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_636 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_637 = eq(_T_636, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_638 = and(_T_633, _T_635) @[exu_div_ctl.scala 696:95]
node _T_639 = and(_T_638, _T_637) @[exu_div_ctl.scala 696:95]
node _T_640 = and(_T_631, _T_639) @[exu_div_ctl.scala 697:11]
node _T_641 = or(_T_630, _T_640) @[exu_div_ctl.scala 704:42]
node _T_642 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_643 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_644 = eq(_T_643, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_645 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_646 = eq(_T_645, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_647 = and(_T_644, _T_646) @[exu_div_ctl.scala 696:95]
node _T_648 = and(_T_642, _T_647) @[exu_div_ctl.scala 697:11]
node _T_649 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 704:113]
node _T_650 = eq(_T_649, UInt<1>("h00")) @[exu_div_ctl.scala 704:108]
node _T_651 = and(_T_648, _T_650) @[exu_div_ctl.scala 704:106]
node _T_652 = or(_T_641, _T_651) @[exu_div_ctl.scala 704:78]
node _T_653 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_654 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:75]
node _T_655 = eq(_T_654, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_656 = and(_T_653, _T_655) @[exu_div_ctl.scala 695:95]
node _T_657 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_658 = eq(_T_657, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_659 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_660 = eq(_T_659, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_661 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:58]
node _T_662 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 696:58]
node _T_663 = and(_T_658, _T_660) @[exu_div_ctl.scala 696:95]
node _T_664 = and(_T_663, _T_661) @[exu_div_ctl.scala 696:95]
node _T_665 = and(_T_664, _T_662) @[exu_div_ctl.scala 696:95]
node _T_666 = and(_T_656, _T_665) @[exu_div_ctl.scala 697:11]
node _T_667 = or(_T_652, _T_666) @[exu_div_ctl.scala 704:117]
node _T_668 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:75]
node _T_669 = eq(_T_668, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_670 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_671 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_672 = and(_T_669, _T_670) @[exu_div_ctl.scala 695:95]
node _T_673 = and(_T_672, _T_671) @[exu_div_ctl.scala 695:95]
node _T_674 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_675 = eq(_T_674, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_676 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_677 = eq(_T_676, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_678 = and(_T_675, _T_677) @[exu_div_ctl.scala 696:95]
node _T_679 = and(_T_673, _T_678) @[exu_div_ctl.scala 697:11]
node _T_680 = or(_T_667, _T_679) @[exu_div_ctl.scala 705:44]
node _T_681 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_682 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_683 = and(_T_681, _T_682) @[exu_div_ctl.scala 695:95]
node _T_684 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_685 = eq(_T_684, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_686 = and(_T_683, _T_685) @[exu_div_ctl.scala 697:11]
node _T_687 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 705:114]
node _T_688 = eq(_T_687, UInt<1>("h00")) @[exu_div_ctl.scala 705:109]
node _T_689 = and(_T_686, _T_688) @[exu_div_ctl.scala 705:107]
node _T_690 = or(_T_680, _T_689) @[exu_div_ctl.scala 705:80]
node _T_691 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_692 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_693 = and(_T_691, _T_692) @[exu_div_ctl.scala 695:95]
node _T_694 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_695 = eq(_T_694, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_696 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:58]
node _T_697 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_698 = eq(_T_697, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_699 = and(_T_695, _T_696) @[exu_div_ctl.scala 696:95]
node _T_700 = and(_T_699, _T_698) @[exu_div_ctl.scala 696:95]
node _T_701 = and(_T_693, _T_700) @[exu_div_ctl.scala 697:11]
node _T_702 = or(_T_690, _T_701) @[exu_div_ctl.scala 705:119]
node _T_703 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_704 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_705 = and(_T_703, _T_704) @[exu_div_ctl.scala 695:95]
node _T_706 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_707 = eq(_T_706, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_708 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_709 = eq(_T_708, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_710 = and(_T_707, _T_709) @[exu_div_ctl.scala 696:95]
node _T_711 = and(_T_705, _T_710) @[exu_div_ctl.scala 697:11]
node _T_712 = or(_T_702, _T_711) @[exu_div_ctl.scala 706:44]
node _T_713 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_714 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_715 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_716 = and(_T_713, _T_714) @[exu_div_ctl.scala 695:95]
node _T_717 = and(_T_716, _T_715) @[exu_div_ctl.scala 695:95]
node _T_718 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_719 = eq(_T_718, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_720 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:58]
node _T_721 = and(_T_719, _T_720) @[exu_div_ctl.scala 696:95]
node _T_722 = and(_T_717, _T_721) @[exu_div_ctl.scala 697:11]
node _T_723 = or(_T_712, _T_722) @[exu_div_ctl.scala 706:79]
node _T_724 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_725 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_726 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 695:58]
node _T_727 = and(_T_724, _T_725) @[exu_div_ctl.scala 695:95]
node _T_728 = and(_T_727, _T_726) @[exu_div_ctl.scala 695:95]
node _T_729 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_730 = eq(_T_729, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_731 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_732 = eq(_T_731, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_733 = and(_T_730, _T_732) @[exu_div_ctl.scala 696:95]
node _T_734 = and(_T_728, _T_733) @[exu_div_ctl.scala 697:11]
node _T_735 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_736 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:75]
node _T_737 = eq(_T_736, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_738 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 695:58]
node _T_739 = and(_T_735, _T_737) @[exu_div_ctl.scala 695:95]
node _T_740 = and(_T_739, _T_738) @[exu_div_ctl.scala 695:95]
node _T_741 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_742 = eq(_T_741, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_743 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:58]
node _T_744 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 696:58]
node _T_745 = and(_T_742, _T_743) @[exu_div_ctl.scala 696:95]
node _T_746 = and(_T_745, _T_744) @[exu_div_ctl.scala 696:95]
node _T_747 = and(_T_740, _T_746) @[exu_div_ctl.scala 697:11]
node _T_748 = or(_T_734, _T_747) @[exu_div_ctl.scala 708:45]
node _T_749 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_750 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_751 = eq(_T_750, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_752 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_753 = eq(_T_752, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_754 = and(_T_751, _T_753) @[exu_div_ctl.scala 696:95]
node _T_755 = and(_T_749, _T_754) @[exu_div_ctl.scala 697:11]
node _T_756 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 708:121]
node _T_757 = eq(_T_756, UInt<1>("h00")) @[exu_div_ctl.scala 708:116]
node _T_758 = and(_T_755, _T_757) @[exu_div_ctl.scala 708:114]
node _T_759 = or(_T_748, _T_758) @[exu_div_ctl.scala 708:86]
node _T_760 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_761 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_762 = eq(_T_761, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_763 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_764 = eq(_T_763, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_765 = and(_T_762, _T_764) @[exu_div_ctl.scala 696:95]
node _T_766 = and(_T_760, _T_765) @[exu_div_ctl.scala 697:11]
node _T_767 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 709:40]
node _T_768 = eq(_T_767, UInt<1>("h00")) @[exu_div_ctl.scala 709:35]
node _T_769 = and(_T_766, _T_768) @[exu_div_ctl.scala 709:33]
node _T_770 = or(_T_759, _T_769) @[exu_div_ctl.scala 708:129]
node _T_771 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 695:58]
node _T_772 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_773 = eq(_T_772, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_774 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_775 = eq(_T_774, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_776 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_777 = eq(_T_776, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_778 = and(_T_773, _T_775) @[exu_div_ctl.scala 696:95]
node _T_779 = and(_T_778, _T_777) @[exu_div_ctl.scala 696:95]
node _T_780 = and(_T_771, _T_779) @[exu_div_ctl.scala 697:11]
node _T_781 = or(_T_770, _T_780) @[exu_div_ctl.scala 709:47]
node _T_782 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:75]
node _T_783 = eq(_T_782, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_784 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_785 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:75]
node _T_786 = eq(_T_785, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_787 = and(_T_783, _T_784) @[exu_div_ctl.scala 695:95]
node _T_788 = and(_T_787, _T_786) @[exu_div_ctl.scala 695:95]
node _T_789 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_790 = eq(_T_789, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_791 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_792 = eq(_T_791, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_793 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:58]
node _T_794 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 696:58]
node _T_795 = and(_T_790, _T_792) @[exu_div_ctl.scala 696:95]
node _T_796 = and(_T_795, _T_793) @[exu_div_ctl.scala 696:95]
node _T_797 = and(_T_796, _T_794) @[exu_div_ctl.scala 696:95]
node _T_798 = and(_T_788, _T_797) @[exu_div_ctl.scala 697:11]
node _T_799 = or(_T_781, _T_798) @[exu_div_ctl.scala 709:88]
node _T_800 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:75]
node _T_801 = eq(_T_800, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_802 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_803 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_804 = and(_T_801, _T_802) @[exu_div_ctl.scala 695:95]
node _T_805 = and(_T_804, _T_803) @[exu_div_ctl.scala 695:95]
node _T_806 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_807 = eq(_T_806, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_808 = and(_T_805, _T_807) @[exu_div_ctl.scala 697:11]
node _T_809 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 710:43]
node _T_810 = eq(_T_809, UInt<1>("h00")) @[exu_div_ctl.scala 710:38]
node _T_811 = and(_T_808, _T_810) @[exu_div_ctl.scala 710:36]
node _T_812 = or(_T_799, _T_811) @[exu_div_ctl.scala 709:131]
node _T_813 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_814 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_815 = eq(_T_814, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_816 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_817 = eq(_T_816, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_818 = and(_T_815, _T_817) @[exu_div_ctl.scala 696:95]
node _T_819 = and(_T_813, _T_818) @[exu_div_ctl.scala 697:11]
node _T_820 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 710:83]
node _T_821 = eq(_T_820, UInt<1>("h00")) @[exu_div_ctl.scala 710:78]
node _T_822 = and(_T_819, _T_821) @[exu_div_ctl.scala 710:76]
node _T_823 = or(_T_812, _T_822) @[exu_div_ctl.scala 710:47]
node _T_824 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_825 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:75]
node _T_826 = eq(_T_825, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_827 = and(_T_824, _T_826) @[exu_div_ctl.scala 695:95]
node _T_828 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_829 = eq(_T_828, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_830 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:58]
node _T_831 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:58]
node _T_832 = and(_T_829, _T_830) @[exu_div_ctl.scala 696:95]
node _T_833 = and(_T_832, _T_831) @[exu_div_ctl.scala 696:95]
node _T_834 = and(_T_827, _T_833) @[exu_div_ctl.scala 697:11]
node _T_835 = or(_T_823, _T_834) @[exu_div_ctl.scala 710:88]
node _T_836 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:75]
node _T_837 = eq(_T_836, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_838 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_839 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_840 = and(_T_837, _T_838) @[exu_div_ctl.scala 695:95]
node _T_841 = and(_T_840, _T_839) @[exu_div_ctl.scala 695:95]
node _T_842 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_843 = eq(_T_842, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_844 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:58]
node _T_845 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_846 = eq(_T_845, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_847 = and(_T_843, _T_844) @[exu_div_ctl.scala 696:95]
node _T_848 = and(_T_847, _T_846) @[exu_div_ctl.scala 696:95]
node _T_849 = and(_T_841, _T_848) @[exu_div_ctl.scala 697:11]
node _T_850 = or(_T_835, _T_849) @[exu_div_ctl.scala 710:131]
node _T_851 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:75]
node _T_852 = eq(_T_851, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_853 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_854 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 695:58]
node _T_855 = and(_T_852, _T_853) @[exu_div_ctl.scala 695:95]
node _T_856 = and(_T_855, _T_854) @[exu_div_ctl.scala 695:95]
node _T_857 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_858 = eq(_T_857, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_859 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_860 = eq(_T_859, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_861 = and(_T_858, _T_860) @[exu_div_ctl.scala 696:95]
node _T_862 = and(_T_856, _T_861) @[exu_div_ctl.scala 697:11]
node _T_863 = or(_T_850, _T_862) @[exu_div_ctl.scala 711:47]
node _T_864 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_865 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:75]
node _T_866 = eq(_T_865, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_867 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:75]
node _T_868 = eq(_T_867, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_869 = and(_T_864, _T_866) @[exu_div_ctl.scala 695:95]
node _T_870 = and(_T_869, _T_868) @[exu_div_ctl.scala 695:95]
node _T_871 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_872 = eq(_T_871, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_873 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:58]
node _T_874 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 696:58]
node _T_875 = and(_T_872, _T_873) @[exu_div_ctl.scala 696:95]
node _T_876 = and(_T_875, _T_874) @[exu_div_ctl.scala 696:95]
node _T_877 = and(_T_870, _T_876) @[exu_div_ctl.scala 697:11]
node _T_878 = or(_T_863, _T_877) @[exu_div_ctl.scala 711:88]
node _T_879 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:75]
node _T_880 = eq(_T_879, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_881 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_882 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 695:58]
node _T_883 = and(_T_880, _T_881) @[exu_div_ctl.scala 695:95]
node _T_884 = and(_T_883, _T_882) @[exu_div_ctl.scala 695:95]
node _T_885 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_886 = eq(_T_885, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_887 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_888 = eq(_T_887, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_889 = and(_T_886, _T_888) @[exu_div_ctl.scala 696:95]
node _T_890 = and(_T_884, _T_889) @[exu_div_ctl.scala 697:11]
node _T_891 = or(_T_878, _T_890) @[exu_div_ctl.scala 711:131]
node _T_892 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_893 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_894 = and(_T_892, _T_893) @[exu_div_ctl.scala 695:95]
node _T_895 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_896 = eq(_T_895, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_897 = and(_T_894, _T_896) @[exu_div_ctl.scala 697:11]
node _T_898 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 712:82]
node _T_899 = eq(_T_898, UInt<1>("h00")) @[exu_div_ctl.scala 712:77]
node _T_900 = and(_T_897, _T_899) @[exu_div_ctl.scala 712:75]
node _T_901 = or(_T_891, _T_900) @[exu_div_ctl.scala 712:47]
node _T_902 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:75]
node _T_903 = eq(_T_902, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_904 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_905 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_906 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 695:58]
node _T_907 = and(_T_903, _T_904) @[exu_div_ctl.scala 695:95]
node _T_908 = and(_T_907, _T_905) @[exu_div_ctl.scala 695:95]
node _T_909 = and(_T_908, _T_906) @[exu_div_ctl.scala 695:95]
node _T_910 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_911 = eq(_T_910, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_912 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:58]
node _T_913 = and(_T_911, _T_912) @[exu_div_ctl.scala 696:95]
node _T_914 = and(_T_909, _T_913) @[exu_div_ctl.scala 697:11]
node _T_915 = or(_T_901, _T_914) @[exu_div_ctl.scala 712:88]
node _T_916 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_917 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_918 = and(_T_916, _T_917) @[exu_div_ctl.scala 695:95]
node _T_919 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:58]
node _T_920 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_921 = eq(_T_920, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_922 = and(_T_919, _T_921) @[exu_div_ctl.scala 696:95]
node _T_923 = and(_T_918, _T_922) @[exu_div_ctl.scala 697:11]
node _T_924 = or(_T_915, _T_923) @[exu_div_ctl.scala 712:131]
node _T_925 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_926 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_927 = and(_T_925, _T_926) @[exu_div_ctl.scala 695:95]
node _T_928 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:58]
node _T_929 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_930 = eq(_T_929, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_931 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_932 = eq(_T_931, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_933 = and(_T_928, _T_930) @[exu_div_ctl.scala 696:95]
node _T_934 = and(_T_933, _T_932) @[exu_div_ctl.scala 696:95]
node _T_935 = and(_T_927, _T_934) @[exu_div_ctl.scala 697:11]
node _T_936 = or(_T_924, _T_935) @[exu_div_ctl.scala 713:47]
node _T_937 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_938 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 695:58]
node _T_939 = and(_T_937, _T_938) @[exu_div_ctl.scala 695:95]
node _T_940 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_941 = eq(_T_940, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_942 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_943 = eq(_T_942, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_944 = and(_T_941, _T_943) @[exu_div_ctl.scala 696:95]
node _T_945 = and(_T_939, _T_944) @[exu_div_ctl.scala 697:11]
node _T_946 = or(_T_936, _T_945) @[exu_div_ctl.scala 713:88]
node _T_947 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_948 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:75]
node _T_949 = eq(_T_948, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_950 = and(_T_947, _T_949) @[exu_div_ctl.scala 695:95]
node _T_951 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_952 = eq(_T_951, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_953 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:58]
node _T_954 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:58]
node _T_955 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 696:58]
node _T_956 = and(_T_952, _T_953) @[exu_div_ctl.scala 696:95]
node _T_957 = and(_T_956, _T_954) @[exu_div_ctl.scala 696:95]
node _T_958 = and(_T_957, _T_955) @[exu_div_ctl.scala 696:95]
node _T_959 = and(_T_950, _T_958) @[exu_div_ctl.scala 697:11]
node _T_960 = or(_T_946, _T_959) @[exu_div_ctl.scala 713:131]
node _T_961 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_962 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_963 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_964 = and(_T_961, _T_962) @[exu_div_ctl.scala 695:95]
node _T_965 = and(_T_964, _T_963) @[exu_div_ctl.scala 695:95]
node _T_966 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:58]
node _T_967 = and(_T_965, _T_966) @[exu_div_ctl.scala 697:11]
node _T_968 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 714:84]
node _T_969 = eq(_T_968, UInt<1>("h00")) @[exu_div_ctl.scala 714:79]
node _T_970 = and(_T_967, _T_969) @[exu_div_ctl.scala 714:77]
node _T_971 = or(_T_960, _T_970) @[exu_div_ctl.scala 714:47]
node _T_972 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_973 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_974 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_975 = and(_T_972, _T_973) @[exu_div_ctl.scala 695:95]
node _T_976 = and(_T_975, _T_974) @[exu_div_ctl.scala 695:95]
node _T_977 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:58]
node _T_978 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_979 = eq(_T_978, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_980 = and(_T_977, _T_979) @[exu_div_ctl.scala 696:95]
node _T_981 = and(_T_976, _T_980) @[exu_div_ctl.scala 697:11]
node _T_982 = or(_T_971, _T_981) @[exu_div_ctl.scala 714:88]
node _T_983 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_984 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_985 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 695:58]
node _T_986 = and(_T_983, _T_984) @[exu_div_ctl.scala 695:95]
node _T_987 = and(_T_986, _T_985) @[exu_div_ctl.scala 695:95]
node _T_988 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:58]
node _T_989 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:75]
node _T_990 = eq(_T_989, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_991 = and(_T_988, _T_990) @[exu_div_ctl.scala 696:95]
node _T_992 = and(_T_987, _T_991) @[exu_div_ctl.scala 697:11]
node _T_993 = or(_T_982, _T_992) @[exu_div_ctl.scala 714:131]
node _T_994 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_995 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:75]
node _T_996 = eq(_T_995, UInt<1>("h00")) @[exu_div_ctl.scala 695:70]
node _T_997 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_998 = and(_T_994, _T_996) @[exu_div_ctl.scala 695:95]
node _T_999 = and(_T_998, _T_997) @[exu_div_ctl.scala 695:95]
node _T_1000 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:75]
node _T_1001 = eq(_T_1000, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_1002 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 696:58]
node _T_1003 = and(_T_1001, _T_1002) @[exu_div_ctl.scala 696:95]
node _T_1004 = and(_T_999, _T_1003) @[exu_div_ctl.scala 697:11]
node _T_1005 = or(_T_993, _T_1004) @[exu_div_ctl.scala 715:47]
node _T_1006 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_1007 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_1008 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 695:58]
node _T_1009 = and(_T_1006, _T_1007) @[exu_div_ctl.scala 695:95]
node _T_1010 = and(_T_1009, _T_1008) @[exu_div_ctl.scala 695:95]
node _T_1011 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_1012 = eq(_T_1011, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_1013 = and(_T_1010, _T_1012) @[exu_div_ctl.scala 697:11]
node _T_1014 = or(_T_1005, _T_1013) @[exu_div_ctl.scala 715:88]
node _T_1015 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_1016 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 695:58]
node _T_1017 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_1018 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 695:58]
node _T_1019 = and(_T_1015, _T_1016) @[exu_div_ctl.scala 695:95]
node _T_1020 = and(_T_1019, _T_1017) @[exu_div_ctl.scala 695:95]
node _T_1021 = and(_T_1020, _T_1018) @[exu_div_ctl.scala 695:95]
node _T_1022 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 696:58]
node _T_1023 = and(_T_1021, _T_1022) @[exu_div_ctl.scala 697:11]
node _T_1024 = or(_T_1014, _T_1023) @[exu_div_ctl.scala 715:131]
node _T_1025 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 695:58]
node _T_1026 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 695:58]
node _T_1027 = and(_T_1025, _T_1026) @[exu_div_ctl.scala 695:95]
node _T_1028 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 696:75]
node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[exu_div_ctl.scala 696:70]
node _T_1030 = and(_T_1027, _T_1029) @[exu_div_ctl.scala 697:11]
node _T_1031 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 716:81]
node _T_1032 = eq(_T_1031, UInt<1>("h00")) @[exu_div_ctl.scala 716:76]
node _T_1033 = and(_T_1030, _T_1032) @[exu_div_ctl.scala 716:74]
node _T_1034 = or(_T_1024, _T_1033) @[exu_div_ctl.scala 716:47]
node _T_1035 = cat(_T_723, _T_1034) @[Cat.scala 29:58]
node _T_1036 = cat(_T_589, _T_620) @[Cat.scala 29:58]
node _T_1037 = cat(_T_1036, _T_1035) @[Cat.scala 29:58]
smallnum <= _T_1037 @[exu_div_ctl.scala 699:12]
node _T_1038 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 718:50]
node shortq_dividend = cat(dividend_sign_ff, _T_1038) @[Cat.scala 29:58]
inst a_enc of exu_div_cls @[exu_div_ctl.scala 719:21]
divider 4 added
2021-01-06 18:04:21 +08:00
a_enc.clock <= clock
a_enc.reset <= reset
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
a_enc.io.operand <= shortq_dividend @[exu_div_ctl.scala 720:20]
inst b_enc of exu_div_cls_1 @[exu_div_ctl.scala 722:20]
divider 4 added
2021-01-06 18:04:21 +08:00
b_enc.clock <= clock
b_enc.reset <= reset
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1039 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 723:27]
b_enc.io.operand <= _T_1039 @[exu_div_ctl.scala 723:20]
divider 4 added
2021-01-06 18:04:21 +08:00
node dw_a_enc = cat(UInt<1>("h00"), a_enc.io.cls) @[Cat.scala 29:58]
node dw_b_enc = cat(UInt<1>("h00"), b_enc.io.cls) @[Cat.scala 29:58]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1040 = cat(UInt<1>("h00"), dw_b_enc) @[Cat.scala 29:58]
node _T_1041 = cat(UInt<1>("h00"), dw_a_enc) @[Cat.scala 29:58]
node _T_1042 = sub(_T_1040, _T_1041) @[exu_div_ctl.scala 727:41]
node _T_1043 = tail(_T_1042, 1) @[exu_div_ctl.scala 727:41]
node _T_1044 = add(_T_1043, UInt<7>("h01")) @[exu_div_ctl.scala 727:61]
node dw_shortq_raw = tail(_T_1044, 1) @[exu_div_ctl.scala 727:61]
node _T_1045 = bits(dw_shortq_raw, 6, 6) @[exu_div_ctl.scala 728:33]
node _T_1046 = bits(_T_1045, 0, 0) @[exu_div_ctl.scala 728:43]
node _T_1047 = bits(dw_shortq_raw, 5, 0) @[exu_div_ctl.scala 728:63]
node shortq = mux(_T_1046, UInt<1>("h00"), _T_1047) @[exu_div_ctl.scala 728:19]
node _T_1048 = bits(shortq, 5, 5) @[exu_div_ctl.scala 729:38]
node _T_1049 = eq(_T_1048, UInt<1>("h00")) @[exu_div_ctl.scala 729:31]
node _T_1050 = and(valid_ff, _T_1049) @[exu_div_ctl.scala 729:29]
node _T_1051 = bits(shortq, 4, 2) @[exu_div_ctl.scala 729:52]
node _T_1052 = eq(_T_1051, UInt<3>("h07")) @[exu_div_ctl.scala 729:58]
node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[exu_div_ctl.scala 729:44]
node _T_1054 = and(_T_1050, _T_1053) @[exu_div_ctl.scala 729:42]
node _T_1055 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 729:75]
node _T_1056 = and(_T_1054, _T_1055) @[exu_div_ctl.scala 729:73]
shortq_enable <= _T_1056 @[exu_div_ctl.scala 729:17]
node _T_1057 = eq(shortq, UInt<5>("h01f")) @[exu_div_ctl.scala 731:58]
node _T_1058 = eq(shortq, UInt<5>("h01e")) @[exu_div_ctl.scala 731:58]
node _T_1059 = eq(shortq, UInt<5>("h01d")) @[exu_div_ctl.scala 731:58]
node _T_1060 = eq(shortq, UInt<5>("h01c")) @[exu_div_ctl.scala 731:58]
node _T_1061 = eq(shortq, UInt<5>("h01b")) @[exu_div_ctl.scala 731:58]
node _T_1062 = eq(shortq, UInt<5>("h01a")) @[exu_div_ctl.scala 731:58]
node _T_1063 = eq(shortq, UInt<5>("h019")) @[exu_div_ctl.scala 731:58]
node _T_1064 = eq(shortq, UInt<5>("h018")) @[exu_div_ctl.scala 731:58]
node _T_1065 = eq(shortq, UInt<5>("h017")) @[exu_div_ctl.scala 731:58]
node _T_1066 = eq(shortq, UInt<5>("h016")) @[exu_div_ctl.scala 731:58]
node _T_1067 = eq(shortq, UInt<5>("h015")) @[exu_div_ctl.scala 731:58]
node _T_1068 = eq(shortq, UInt<5>("h014")) @[exu_div_ctl.scala 731:58]
node _T_1069 = eq(shortq, UInt<5>("h013")) @[exu_div_ctl.scala 731:58]
node _T_1070 = eq(shortq, UInt<5>("h012")) @[exu_div_ctl.scala 731:58]
node _T_1071 = eq(shortq, UInt<5>("h011")) @[exu_div_ctl.scala 731:58]
node _T_1072 = eq(shortq, UInt<5>("h010")) @[exu_div_ctl.scala 731:58]
node _T_1073 = eq(shortq, UInt<4>("h0f")) @[exu_div_ctl.scala 731:58]
node _T_1074 = eq(shortq, UInt<4>("h0e")) @[exu_div_ctl.scala 731:58]
node _T_1075 = eq(shortq, UInt<4>("h0d")) @[exu_div_ctl.scala 731:58]
node _T_1076 = eq(shortq, UInt<4>("h0c")) @[exu_div_ctl.scala 731:58]
node _T_1077 = eq(shortq, UInt<4>("h0b")) @[exu_div_ctl.scala 731:58]
node _T_1078 = eq(shortq, UInt<4>("h0a")) @[exu_div_ctl.scala 731:58]
node _T_1079 = eq(shortq, UInt<4>("h09")) @[exu_div_ctl.scala 731:58]
node _T_1080 = eq(shortq, UInt<4>("h08")) @[exu_div_ctl.scala 731:58]
node _T_1081 = eq(shortq, UInt<3>("h07")) @[exu_div_ctl.scala 731:58]
node _T_1082 = eq(shortq, UInt<3>("h06")) @[exu_div_ctl.scala 731:58]
node _T_1083 = eq(shortq, UInt<3>("h05")) @[exu_div_ctl.scala 731:58]
node _T_1084 = eq(shortq, UInt<3>("h04")) @[exu_div_ctl.scala 731:58]
node _T_1085 = eq(shortq, UInt<2>("h03")) @[exu_div_ctl.scala 731:58]
node _T_1086 = eq(shortq, UInt<2>("h02")) @[exu_div_ctl.scala 731:58]
node _T_1087 = eq(shortq, UInt<1>("h01")) @[exu_div_ctl.scala 731:58]
node _T_1088 = eq(shortq, UInt<1>("h00")) @[exu_div_ctl.scala 731:58]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_1089 = mux(_T_1057, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1090 = mux(_T_1058, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:43:04 +08:00
node _T_1091 = mux(_T_1059, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1092 = mux(_T_1060, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1093 = mux(_T_1061, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_1094 = mux(_T_1062, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:43:04 +08:00
node _T_1095 = mux(_T_1063, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1096 = mux(_T_1064, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_1097 = mux(_T_1065, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:43:04 +08:00
node _T_1098 = mux(_T_1066, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1099 = mux(_T_1067, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_1100 = mux(_T_1068, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:43:04 +08:00
node _T_1101 = mux(_T_1069, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1102 = mux(_T_1070, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_1103 = mux(_T_1071, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:43:04 +08:00
node _T_1104 = mux(_T_1072, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1105 = mux(_T_1073, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_1106 = mux(_T_1074, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:43:04 +08:00
node _T_1107 = mux(_T_1075, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1108 = mux(_T_1076, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_1109 = mux(_T_1077, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:43:04 +08:00
node _T_1110 = mux(_T_1078, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1111 = mux(_T_1079, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_1112 = mux(_T_1080, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:43:04 +08:00
node _T_1113 = mux(_T_1081, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1114 = mux(_T_1082, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_1115 = mux(_T_1083, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1116 = mux(_T_1084, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1117 = mux(_T_1085, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1118 = mux(_T_1086, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:43:04 +08:00
node _T_1119 = mux(_T_1087, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1120 = mux(_T_1088, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1121 = or(_T_1089, _T_1090) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:04:21 +08:00
node _T_1122 = or(_T_1121, _T_1091) @[Mux.scala 27:72]
node _T_1123 = or(_T_1122, _T_1092) @[Mux.scala 27:72]
node _T_1124 = or(_T_1123, _T_1093) @[Mux.scala 27:72]
node _T_1125 = or(_T_1124, _T_1094) @[Mux.scala 27:72]
node _T_1126 = or(_T_1125, _T_1095) @[Mux.scala 27:72]
node _T_1127 = or(_T_1126, _T_1096) @[Mux.scala 27:72]
node _T_1128 = or(_T_1127, _T_1097) @[Mux.scala 27:72]
node _T_1129 = or(_T_1128, _T_1098) @[Mux.scala 27:72]
node _T_1130 = or(_T_1129, _T_1099) @[Mux.scala 27:72]
node _T_1131 = or(_T_1130, _T_1100) @[Mux.scala 27:72]
node _T_1132 = or(_T_1131, _T_1101) @[Mux.scala 27:72]
node _T_1133 = or(_T_1132, _T_1102) @[Mux.scala 27:72]
node _T_1134 = or(_T_1133, _T_1103) @[Mux.scala 27:72]
node _T_1135 = or(_T_1134, _T_1104) @[Mux.scala 27:72]
node _T_1136 = or(_T_1135, _T_1105) @[Mux.scala 27:72]
node _T_1137 = or(_T_1136, _T_1106) @[Mux.scala 27:72]
node _T_1138 = or(_T_1137, _T_1107) @[Mux.scala 27:72]
node _T_1139 = or(_T_1138, _T_1108) @[Mux.scala 27:72]
node _T_1140 = or(_T_1139, _T_1109) @[Mux.scala 27:72]
node _T_1141 = or(_T_1140, _T_1110) @[Mux.scala 27:72]
node _T_1142 = or(_T_1141, _T_1111) @[Mux.scala 27:72]
node _T_1143 = or(_T_1142, _T_1112) @[Mux.scala 27:72]
node _T_1144 = or(_T_1143, _T_1113) @[Mux.scala 27:72]
node _T_1145 = or(_T_1144, _T_1114) @[Mux.scala 27:72]
node _T_1146 = or(_T_1145, _T_1115) @[Mux.scala 27:72]
node _T_1147 = or(_T_1146, _T_1116) @[Mux.scala 27:72]
node _T_1148 = or(_T_1147, _T_1117) @[Mux.scala 27:72]
node _T_1149 = or(_T_1148, _T_1118) @[Mux.scala 27:72]
divider 4 added
2021-01-06 18:43:04 +08:00
node _T_1150 = or(_T_1149, _T_1119) @[Mux.scala 27:72]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
node _T_1151 = or(_T_1150, _T_1120) @[Mux.scala 27:72]
wire _T_1152 : UInt<5> @[Mux.scala 27:72]
_T_1152 <= _T_1151 @[Mux.scala 27:72]
shortq_decode <= _T_1152 @[exu_div_ctl.scala 731:17]
node _T_1153 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 732:23]
node _T_1154 = mux(_T_1153, UInt<1>("h00"), shortq_decode) @[exu_div_ctl.scala 732:22]
shortq_shift <= _T_1154 @[exu_div_ctl.scala 732:16]
node _T_1155 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 733:20]
node _T_1156 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 733:30]
node _T_1157 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 733:40]
node _T_1158 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 733:50]
node _T_1159 = cat(_T_1158, b_ff1) @[Cat.scala 29:58]
node _T_1160 = cat(_T_1155, _T_1156) @[Cat.scala 29:58]
node _T_1161 = cat(_T_1160, _T_1157) @[Cat.scala 29:58]
node _T_1162 = cat(_T_1161, _T_1159) @[Cat.scala 29:58]
b_ff <= _T_1162 @[exu_div_ctl.scala 733:8]
divider 4 added
2021-01-06 18:04:21 +08:00
inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 392:18]
rvclkhdr.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
reg _T_1163 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
divider 4 added
2021-01-06 18:04:21 +08:00
when misc_enable : @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
_T_1163 <= valid_ff_in @[Reg.scala 28:23]
divider 4 added
2021-01-06 18:04:21 +08:00
skip @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
valid_ff <= _T_1163 @[exu_div_ctl.scala 734:12]
divider 4 added
2021-01-06 18:04:21 +08:00
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_1.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
reg _T_1164 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
divider 4 added
2021-01-06 18:04:21 +08:00
when misc_enable : @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
_T_1164 <= control_in @[Reg.scala 28:23]
divider 4 added
2021-01-06 18:04:21 +08:00
skip @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
control_ff <= _T_1164 @[exu_div_ctl.scala 735:16]
divider 4 added
2021-01-06 18:04:21 +08:00
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_2.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
reg _T_1165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
divider 4 added
2021-01-06 18:04:21 +08:00
when misc_enable : @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
_T_1165 <= by_zero_case @[Reg.scala 28:23]
divider 4 added
2021-01-06 18:04:21 +08:00
skip @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
by_zero_case_ff <= _T_1165 @[exu_div_ctl.scala 736:19]
divider 4 added
2021-01-06 18:04:21 +08:00
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 390:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_3.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
reg _T_1166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
divider 4 added
2021-01-06 18:04:21 +08:00
when misc_enable : @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
_T_1166 <= shortq_enable @[Reg.scala 28:23]
divider 4 added
2021-01-06 18:04:21 +08:00
skip @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
shortq_enable_ff <= _T_1166 @[exu_div_ctl.scala 737:20]
divider 4 added
2021-01-06 18:04:21 +08:00
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 390:23]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_4.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
reg _T_1167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
divider 4 added
2021-01-06 18:04:21 +08:00
when misc_enable : @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
_T_1167 <= shortq_shift @[Reg.scala 28:23]
divider 4 added
2021-01-06 18:04:21 +08:00
skip @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
shortq_shift_ff <= _T_1167 @[exu_div_ctl.scala 738:19]
divider 4 added
2021-01-06 18:04:21 +08:00
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 390:23]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_5.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
reg _T_1168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
divider 4 added
2021-01-06 18:04:21 +08:00
when misc_enable : @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
_T_1168 <= finish @[Reg.scala 28:23]
divider 4 added
2021-01-06 18:04:21 +08:00
skip @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
finish_ff <= _T_1168 @[exu_div_ctl.scala 739:13]
divider 4 added
2021-01-06 18:04:21 +08:00
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 390:23]
rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_6.io.en <= misc_enable @[lib.scala 393:17]
rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
reg _T_1169 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
divider 4 added
2021-01-06 18:04:21 +08:00
when misc_enable : @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
_T_1169 <= count_in @[Reg.scala 28:23]
divider 4 added
2021-01-06 18:04:21 +08:00
skip @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
count_ff <= _T_1169 @[exu_div_ctl.scala 740:12]
divider 4 added
2021-01-06 18:04:21 +08:00
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 390:23]
rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_7.io.en <= a_enable @[lib.scala 393:17]
rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
reg _T_1170 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
divider 4 added
2021-01-06 18:04:21 +08:00
when a_enable : @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
_T_1170 <= a_in @[Reg.scala 28:23]
divider 4 added
2021-01-06 18:04:21 +08:00
skip @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
a_ff <= _T_1170 @[exu_div_ctl.scala 742:8]
node _T_1171 = bits(b_in, 32, 0) @[exu_div_ctl.scala 743:23]
divider 4 added
2021-01-06 18:04:21 +08:00
inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 390:23]
rvclkhdr_8.clock <= clock
rvclkhdr_8.reset <= reset
rvclkhdr_8.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_8.io.en <= b_enable @[lib.scala 393:17]
rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
reg _T_1172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
divider 4 added
2021-01-06 18:04:21 +08:00
when b_enable : @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
_T_1172 <= _T_1171 @[Reg.scala 28:23]
divider 4 added
2021-01-06 18:04:21 +08:00
skip @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
b_ff1 <= _T_1172 @[exu_div_ctl.scala 743:9]
divider 4 added
2021-01-06 18:04:21 +08:00
inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 390:23]
rvclkhdr_9.clock <= clock
rvclkhdr_9.reset <= reset
rvclkhdr_9.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_9.io.en <= rq_enable @[lib.scala 393:17]
rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
reg _T_1173 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
divider 4 added
2021-01-06 18:04:21 +08:00
when rq_enable : @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
_T_1173 <= r_in @[Reg.scala 28:23]
divider 4 added
2021-01-06 18:04:21 +08:00
skip @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
r_ff <= _T_1173 @[exu_div_ctl.scala 744:8]
divider 4 added
2021-01-06 18:04:21 +08:00
inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 390:23]
rvclkhdr_10.clock <= clock
rvclkhdr_10.reset <= reset
rvclkhdr_10.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_10.io.en <= rq_enable @[lib.scala 393:17]
rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
reg _T_1174 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
divider 4 added
2021-01-06 18:04:21 +08:00
when rq_enable : @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
_T_1174 <= q_in @[Reg.scala 28:23]
divider 4 added
2021-01-06 18:04:21 +08:00
skip @[Reg.scala 28:19]
shiftq_ff corrected
2021-01-06 19:43:25 +08:00
q_ff <= _T_1174 @[exu_div_ctl.scala 745:8]
divider 4 added
2021-01-06 18:04:21 +08:00