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Bridge comp

This commit is contained in:
waleed-lm 2020-12-10 12:52:23 +05:00
parent 0bd697a1d2
commit 01c9c9e296
51 changed files with 204331 additions and 403 deletions
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90
dmi_wrapper.sv Normal file
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// SPDX-License-Identifier: Apache-2.0
// Copyright 2018 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//------------------------------------------------------------------------------------
//
// Copyright Western Digital, 2018
// Owner : Anusha Narayanamoorthy
// Description:
// Wrapper module for JTAG_TAP and DMI synchronizer
//
//-------------------------------------------------------------------------------------
module dmi_wrapper(
// JTAG signals
input trst_n, // JTAG reset
input tck, // JTAG clock
input tms, // Test mode select
input tdi, // Test Data Input
output tdo, // Test Data Output
output tdoEnable, // Test Data Output enable
// Processor Signals
input core_rst_n, // Core reset
input core_clk, // Core clock
input [31:1] jtag_id, // JTAG ID
input [31:0] rd_data, // 32 bit Read data from Processor
output [31:0] reg_wr_data, // 32 bit Write data to Processor
output [6:0] reg_wr_addr, // 7 bit reg address to Processor
output reg_en, // 1 bit Read enable to Processor
output reg_wr_en, // 1 bit Write enable to Processor
output dmi_hard_reset
);
//Wire Declaration
wire rd_en;
wire wr_en;
wire dmireset;
//jtag_tap instantiation
rvjtag_tap i_jtag_tap(
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
.tck(tck), // dedicated JTAG TCK pad signal
.tms(tms), // dedicated JTAG TMS pad signal
.tdi(tdi), // dedicated JTAG TDI pad signal
.tdo(tdo), // dedicated JTAG TDO pad signal
.tdoEnable(tdoEnable), // enable for TDO pad
.wr_data(reg_wr_data), // 32 bit Write data
.wr_addr(reg_wr_addr), // 7 bit Write address
.rd_en(rd_en), // 1 bit read enable
.wr_en(wr_en), // 1 bit Write enable
.rd_data(rd_data), // 32 bit Read data
.rd_status(2'b0),
.idle(3'h0), // no need to wait to sample data
.dmi_stat(2'b0), // no need to wait or error possible
.version(4'h1), // debug spec 0.13 compliant
.jtag_id(jtag_id),
.dmi_hard_reset(dmi_hard_reset),
.dmi_reset(dmireset)
);
// dmi_jtag_to_core_sync instantiation
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
.wr_en(wr_en), // 1 bit Write enable
.rd_en(rd_en), // 1 bit Read enable
.rst_n(core_rst_n),
.clk(core_clk),
.reg_en(reg_en), // 1 bit Write interface bit
.reg_wr_en(reg_wr_en) // 1 bit Write enable
);
endmodule

3
firrtl_black_box_resource_files.f Normal file
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/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
/home/waleedbinehsan/Desktop/Quasar/mem.sv

14
gated_latch.v Normal file
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module gated_latch
(
input wire SE, EN, CK,
output Q
);
reg en_ff;
wire enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule

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mem.sv Normal file
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module mem #(
parameter ICACHE_BEAT_BITS,
parameter ICCM_BITS,
parameter ICACHE_NUM_WAYS,
parameter DCCM_BYTE_WIDTH,
parameter ICCM_BANK_INDEX_LO,
parameter ICACHE_BANK_BITS,
parameter DCCM_BITS,
parameter ICACHE_BEAT_ADDR_HI,
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICACHE_BANKS_WAY,
parameter ICACHE_INDEX_HI,
parameter DCCM_NUM_BANKS,
parameter ICACHE_BANK_HI,
parameter ICACHE_BANK_LO,
parameter DCCM_ENABLE= 'b1,
parameter ICACHE_TAG_LO,
parameter ICACHE_DATA_INDEX_LO,
parameter ICCM_NUM_BANKS,
parameter ICACHE_ECC,
parameter ICACHE_ENABLE= 'b1,
parameter DCCM_BANK_BITS,
parameter ICCM_ENABLE= 'b1,
parameter ICCM_BANK_BITS,
parameter ICACHE_TAG_DEPTH,
parameter ICACHE_WAYPACK,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter ICACHE_TAG_INDEX_LO,
parameter ICACHE_DATA_DEPTH)
(
input logic clk,
input logic rst_l,
input logic dccm_clk_override,
input logic icm_clk_override,
input logic dec_tlu_core_ecc_disable,
//DCCM ports
input logic dccm_wren,
input logic dccm_rden,
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE
//`endif
//ICCM ports
input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
input logic iccm_wren,
input logic iccm_rden,
input logic [2:0] iccm_wr_size,
input logic [77:0] iccm_wr_data,
output logic [63:0] iccm_rd_data,
output logic [77:0] iccm_rd_data_ecc,
// Icache and Itag Ports
input logic [31:1] ic_rw_addr,
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1,
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
input logic ic_debug_rd_en, // Icache debug rd
input logic ic_debug_wr_en, // Icache debug wr
input logic ic_debug_tag_array, // Debug tag array
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic ic_tag_perr, // Icache Tag parity error
input logic scan_mode
);
logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
assign ic_wr_data [0] = ic_wr_data_0;
assign ic_wr_data [1] = ic_wr_data_1;
// DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
.clk_override(dccm_clk_override),
.*
);
end else begin: Gen_dccm_disable
assign dccm_rd_data_lo = '0;
assign dccm_rd_data_hi = '0;
end
if ( ICACHE_ENABLE ) begin: icache
ifu_ic_mem #(
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
.ICACHE_BANK_HI(ICACHE_BANK_HI),
.ICACHE_BANK_LO(ICACHE_BANK_LO),
.ICACHE_TAG_LO(ICACHE_TAG_LO),
.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
.ICACHE_ECC(ICACHE_ECC),
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
.ICACHE_WAYPACK(ICACHE_WAYPACK),
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
.clk_override(icm_clk_override),
.*
);
end
else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ic_tag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE )
if (ICCM_ENABLE) begin : iccm
ifu_iccm_mem #(
.ICCM_BITS(ICCM_BITS),
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
.ICCM_BANK_HI(ICCM_BANK_HI),
.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
.clk_override(icm_clk_override),
.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
.iccm_rd_data(iccm_rd_data[63:0])
);
end
else begin
assign iccm_rd_data = '0 ;
assign iccm_rd_data_ecc = '0 ;
end
endmodule

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sbt.internal.DslEntry

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project/target/config-classes/$1e1278e7407262c7fcf4.class
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[debug] Full compilation, no sources in previous analysis. [debug] Full compilation, no sources in previous analysis.

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[debug] Copy resource mappings: [debug] Copy resource mappings: 
[debug] [debug]  

997
quasar_wrapper.anno.json Normal file
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[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"quasar_wrapper.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>selected_int_priority"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|exu>i0_rs2_d"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|dec_trigger>io_dec_i0_trigger_match_d"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"quasar_wrapper.dmi_wrapper",
"resourceId":"/vsrc/dmi_wrapper.sv"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"quasar_wrapper.mem",
"resourceId":"/vsrc/mem.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"quasar_wrapper"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

114990
quasar_wrapper.fir Normal file
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84490
quasar_wrapper.v Normal file
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4
src/main/scala/dec/dec_tlu_ctl.scala
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@ -740,7 +740,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val block_interrupts = ((internal_dbg_halt_mode & (~dcsr_single_step_running | io.dec_tlu_i0_valid_r)) | internal_pmu_fw_halt_mode | i_cpu_halt_req_d1 | take_nmi | ebreak_to_debug_mode_r | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r | ext_int_freeze_d1) val block_interrupts = ((internal_dbg_halt_mode & (~dcsr_single_step_running | io.dec_tlu_i0_valid_r)) | internal_pmu_fw_halt_mode | i_cpu_halt_req_d1 | take_nmi | ebreak_to_debug_mode_r | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r | ext_int_freeze_d1)
if(FAST_INTERRUPT_REDIRECT==1) { if(FAST_INTERRUPT_REDIRECT) {
take_ext_int_start_d1:=withClock(io.free_clk){RegNext(take_ext_int_start,0.U)} take_ext_int_start_d1:=withClock(io.free_clk){RegNext(take_ext_int_start,0.U)}
take_ext_int_start_d2:=withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)} take_ext_int_start_d2:=withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)}
take_ext_int_start_d3:=withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)} take_ext_int_start_d3:=withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)}
@ -1748,7 +1748,7 @@ val wr_mcycleh_r = WireInit(UInt(1.W), 0.U)
mfdc_int := rvdffe(mfdc_ns,wr_mfdc_r.asBool,clock,io.scan_mode) mfdc_int := rvdffe(mfdc_ns,wr_mfdc_r.asBool,clock,io.scan_mode)
// rvdffe #(15) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[14:0]}), .dout(mfdc_int[14:0])); // rvdffe #(15) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[14:0]}), .dout(mfdc_int[14:0]));
if(BUILD_AXI4 == true){ if(BUILD_AXI4){
// flip poweron value of bit 6 for AXI build // flip poweron value of bit 6 for AXI build
mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,7), ~io.dec_csr_wrdata_r(6), io.dec_csr_wrdata_r(5,0)) mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,7), ~io.dec_csr_wrdata_r(6), io.dec_csr_wrdata_r(5,0))
mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,7), ~mfdc_int(6), mfdc_int(5,0)) mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,7), ~mfdc_int(6), mfdc_int(5,0))

2
src/main/scala/lib/lib.scala
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@ -86,7 +86,7 @@ trait lib extends param{
matchvec(0) := masken_or_fullmask | (mask(0) === data(0)).asUInt matchvec(0) := masken_or_fullmask | (mask(0) === data(0)).asUInt
for(i <- 1 to data.getWidth-1) for(i <- 1 to data.getWidth-1)
matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt) matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt)
matchvec.asUInt matchvec.asUInt.andR()
} }
/////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////

2
src/main/scala/pic_ctrl.scala
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@ -165,7 +165,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
if (PIC_2CYCLE == 1) { if (PIC_2CYCLE) {
val level_intpend_w_prior_en = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(INTPRIORITY_BITS.W)))) //PIC_TOTAL_INT_PLUS1+3 should be there val level_intpend_w_prior_en = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(INTPRIORITY_BITS.W)))) //PIC_TOTAL_INT_PLUS1+3 should be there
val level_intpend_id = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(ID_BITS.W)))) //PIC_TOTAL_INT_PLUS1+3 should be there val level_intpend_id = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(ID_BITS.W)))) //PIC_TOTAL_INT_PLUS1+3 should be there
for(i<-0 until (NUM_LEVELS/2)+1; j<-0 until PIC_TOTAL_INT_PLUS1+3){ //PIC_TOTAL_INT_PLUS1+3 should be there for(i<-0 until (NUM_LEVELS/2)+1; j<-0 until PIC_TOTAL_INT_PLUS1+3){ //PIC_TOTAL_INT_PLUS1+3 should be there

121
src/main/scala/quasar.scala
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@ -289,50 +289,6 @@ class quasar extends Module with RequireAsyncReset with lib {
io.ifu_axi <> ifu.io.ifu io.ifu_axi <> ifu.io.ifu
io.dma_axi <> dma_ctrl.io.dma_axi io.dma_axi <> dma_ctrl.io.dma_axi
// lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready)
// lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready)
// lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid)
// lsu.io.axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp)
// lsu.io.axi.b.bits.id := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id)
// lsu.io.axi.ar.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready)
// lsu.io.axi.r.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid)
// lsu.io.axi.r.bits.id := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id)
// lsu.io.axi.r.bits.data := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data)
// lsu.io.axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp)
// lsu.io.axi.r.bits.last := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last)
//
// ifu.io.ifu.aw.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_awready, io.ifu_axi.aw.ready)
// ifu.io.ifu.w.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_wready, io.ifu_axi.w.ready)
// ifu.io.ifu.ar.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_arready, io.ifu_axi.ar.ready)
// ifu.io.ifu.r.valid := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rvalid, io.ifu_axi.r.valid)
// ifu.io.ifu.r.bits.id := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rid, io.ifu_axi.r.bits.id)
// ifu.io.ifu.r.bits.data := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rdata, io.ifu_axi.r.bits.data)
// ifu.io.ifu.r.bits.resp := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rresp, io.ifu_axi.r.bits.resp)
// ifu.io.ifu.r.bits.last := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rlast, io.ifu_axi.r.bits.last)
//
// dbg.io.sb_axi.aw.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_awready, io.sb_axi.aw.ready)
// dbg.io.sb_axi.w.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_wready, io.sb_axi.w.ready)
// dbg.io.sb_axi.b.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bvalid, io.sb_axi.b.valid)
// dbg.io.sb_axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bresp, io.sb_axi.b.bits.resp)
// dbg.io.sb_axi.ar.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_arready, io.sb_axi.ar.ready)
// dbg.io.sb_axi.r.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rvalid, io.sb_axi.r.valid)
// dbg.io.sb_axi.r.bits.id := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rid, io.sb_axi.r.bits.id)
// dbg.io.sb_axi.r.bits.data := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rdata, io.sb_axi.r.bits.data)
// dbg.io.sb_axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rresp, io.sb_axi.r.bits.resp)
//
// dma_ctrl.io.dma_axi.aw.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid)
// dma_ctrl.io.dma_axi.aw.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id)
// dma_ctrl.io.dma_axi.aw.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr)
// dma_ctrl.io.dma_axi.aw.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size)
// dma_ctrl.io.dma_axi.w.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid)
// dma_ctrl.io.dma_axi.w.bits.data := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data)
// dma_ctrl.io.dma_axi.w.bits.strb := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb)
// dma_ctrl.io.dma_axi.b.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready)
// dma_ctrl.io.dma_axi.ar.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid)
// dma_ctrl.io.dma_axi.ar.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id)
// dma_ctrl.io.dma_axi.ar.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr)
// dma_ctrl.io.dma_axi.ar.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size)
// dma_ctrl.io.dma_axi.r.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready)
@ -449,6 +405,53 @@ class quasar extends Module with RequireAsyncReset with lib {
dma_ahb_to_axi4.io.ahb_hsel := io.dma_hsel dma_ahb_to_axi4.io.ahb_hsel := io.dma_hsel
dma_ahb_to_axi4.io.ahb_hreadyin := io.dma_hreadyin dma_ahb_to_axi4.io.ahb_hreadyin := io.dma_hreadyin
// Mux for the axi-bridge
lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready)
lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready)
lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid)
lsu.io.axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp)
lsu.io.axi.b.bits.id := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id)
lsu.io.axi.ar.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready)
lsu.io.axi.r.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid)
lsu.io.axi.r.bits.id := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id)
lsu.io.axi.r.bits.data := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data)
lsu.io.axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp)
lsu.io.axi.r.bits.last := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last)
ifu.io.ifu.aw.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_awready, io.ifu_axi.aw.ready)
ifu.io.ifu.w.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_wready, io.ifu_axi.w.ready)
ifu.io.ifu.ar.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_arready, io.ifu_axi.ar.ready)
ifu.io.ifu.r.valid := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rvalid, io.ifu_axi.r.valid)
ifu.io.ifu.r.bits.id := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rid, io.ifu_axi.r.bits.id)
ifu.io.ifu.r.bits.data := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rdata, io.ifu_axi.r.bits.data)
ifu.io.ifu.r.bits.resp := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rresp, io.ifu_axi.r.bits.resp)
ifu.io.ifu.r.bits.last := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rlast, io.ifu_axi.r.bits.last)
dbg.io.sb_axi.aw.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_awready, io.sb_axi.aw.ready)
dbg.io.sb_axi.w.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_wready, io.sb_axi.w.ready)
dbg.io.sb_axi.b.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bvalid, io.sb_axi.b.valid)
dbg.io.sb_axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bresp, io.sb_axi.b.bits.resp)
dbg.io.sb_axi.ar.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_arready, io.sb_axi.ar.ready)
dbg.io.sb_axi.r.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rvalid, io.sb_axi.r.valid)
dbg.io.sb_axi.r.bits.id := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rid, io.sb_axi.r.bits.id)
dbg.io.sb_axi.r.bits.data := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rdata, io.sb_axi.r.bits.data)
dbg.io.sb_axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rresp, io.sb_axi.r.bits.resp)
dma_ctrl.io.dma_axi.aw.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid)
dma_ctrl.io.dma_axi.aw.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id)
dma_ctrl.io.dma_axi.aw.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr)
dma_ctrl.io.dma_axi.aw.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size)
dma_ctrl.io.dma_axi.w.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid)
dma_ctrl.io.dma_axi.w.bits.data := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data)
dma_ctrl.io.dma_axi.w.bits.strb := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb)
dma_ctrl.io.dma_axi.b.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready)
dma_ctrl.io.dma_axi.ar.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid)
dma_ctrl.io.dma_axi.ar.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id)
dma_ctrl.io.dma_axi.ar.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr)
dma_ctrl.io.dma_axi.ar.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size)
dma_ctrl.io.dma_axi.r.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready)
// AHB Signals // AHB Signals
io.haddr := ifu_axi4_to_ahb.io.ahb_haddr io.haddr := ifu_axi4_to_ahb.io.ahb_haddr
io.hburst := ifu_axi4_to_ahb.io.ahb_hburst io.hburst := ifu_axi4_to_ahb.io.ahb_hburst
@ -515,36 +518,6 @@ class quasar extends Module with RequireAsyncReset with lib {
io.dma_hresp := 0.U io.dma_hresp := 0.U
} }
io.haddr := 0.U
io.hburst := 0.U
io.hmastlock := 0.U
io.hprot := 0.U
io.hsize := 0.U
io.htrans := 0.U
io.hwrite := 0.U
io.lsu_haddr := 0.U
io.lsu_hburst := 0.U
io.lsu_hmastlock := 0.U
io.lsu_hprot := 0.U
io.lsu_hsize := 0.U
io.lsu_htrans := 0.U
io.lsu_hwrite := 0.U
io.lsu_hwdata := 0.U
io.sb_haddr := 0.U
io.sb_hburst := 0.U
io.sb_hmastlock := 0.U
io.sb_hprot := 0.U
io.sb_hsize := 0.U
io.sb_htrans := 0.U
io.sb_hwrite := 0.U
io.sb_hwdata := 0.U
io.dma_hrdata := 0.U
io.dma_hreadyout := 0.U
io.dma_hresp := 0.U
io.dmi_reg_rdata := 0.U io.dmi_reg_rdata := 0.U
} }

4
src/main/scala/quasar_wrapper.scala
View File

@ -197,3 +197,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
io.dma_hresp := core.io.dma_hresp io.dma_hresp := core.io.dma_hresp
} }
object QUASAR_Wrp extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()))
}

158
src/main/scala/snapshot/el2_param.scala
View File

@ -1,158 +0,0 @@
package snapshot
import chisel3._
object pt{
val BHT_ADDR_HI = "h9".U(4.W)
val BHT_ADDR_LO = "h2".U(2.W)
val BHT_ARRAY_DEPTH = "h100".U(11.W)
val BHT_GHR_HASH_1 = "h0".U(1.W)
val BHT_GHR_SIZE = "8h".U(4.W)
val BHT_SIZE = "h200".U(12.W)
val BTB_ADDR_HI = "h09".U(5.W)
val BTB_ADDR_LO = "h2".U(2.W)
val BTB_ARRAY_DEPTH = "h100".U(9.W)
val BTB_BTAG_FOLD = "h0".U(1.W)
val BTB_BTAG_SIZE = "h5".U(4.W)
val BTB_FOLD2_INDEX_HASH = "h0".U(1.W)
val BTB_INDEX1_HI = "h09".U(5.W)
val BTB_INDEX1_LO = "h02".U(5.W)
val BTB_INDEX2_HI = "h11".U(5.W)
val BTB_INDEX2_LO = "h0A".U(5.W)
val BTB_INDEX3_HI = "h19".U(5.W)
val BTB_INDEX3_LO = "h12".U(5.W)
val BTB_SIZE = "h200".U(10.W)
val BUILD_AHB_LITE = "h0".U(1.W)
val BUILD_AXI4 = "h1".U(1.W)
val BUILD_AXI_NATIVE = "h1".U(1.W)
val BUS_PRTY_DEFAULT = "h3".U(2.W)
val DATA_ACCESS_ADDR0 = "h00000000".U(32.W)
val DATA_ACCESS_ADDR1 = "hC0000000".U(32.W)
val DATA_ACCESS_ADDR2 = "hA0000000".U(32.W)
val DATA_ACCESS_ADDR3 = "h80000000".U(32.W)
val DATA_ACCESS_ADDR4 = "h00000000".U(32.W)
val DATA_ACCESS_ADDR5 = "h00000000".U(32.W)
val DATA_ACCESS_ADDR6 = "h00000000".U(32.W)
val DATA_ACCESS_ADDR7 = "h00000000".U(32.W)
val DATA_ACCESS_ENABLE0 = "h1".U(1.W)
val DATA_ACCESS_ENABLE1 = "h1".U(1.W)
val DATA_ACCESS_ENABLE2 = "h1".U(1.W)
val DATA_ACCESS_ENABLE3 = "h1".U(1.W)
val DATA_ACCESS_ENABLE4 = "h0".U(1.W)
val DATA_ACCESS_ENABLE5 = "h0".U(1.W)
val DATA_ACCESS_ENABLE6 = "h0".U(1.W)
val DATA_ACCESS_ENABLE7 = "h0".U(1.W)
val DATA_ACCESS_MASK0 = "h7FFFFFFF".U(32.W)
val DATA_ACCESS_MASK1 = "h3FFFFFFF".U(32.W)
val DATA_ACCESS_MASK2 = "h1FFFFFFF".U(32.W)
val DATA_ACCESS_MASK3 = "h0FFFFFFF".U(32.W)
val DATA_ACCESS_MASK4 = "hFFFFFFFF".U(32.W)
val DATA_ACCESS_MASK5 = "hFFFFFFFF".U(32.W)
val DATA_ACCESS_MASK6 = "hFFFFFFFF".U(32.W)
val DATA_ACCESS_MASK7 = "hFFFFFFFF".U(32.W)
val DCCM_BANK_BITS = "h2".U(3.W)
val DCCM_BITS = "h10".U(5.W)
val DCCM_BYTE_WIDTH = "h4".U(3.W)
val DCCM_DATA_WIDTH = "h20".U(6.W)
val DCCM_ECC_WIDTH = "h7".U(3.W)
val DCCM_ENABLE = "h1".U(1.W)
val DCCM_FDATA_WIDTH = "h27".U(6.W)
val DCCM_INDEX_BITS = "hC".U(4.W)
val DCCM_NUM_BANKS = "h04".U(5.W)
val DCCM_REGION = "hF".U(4.W)
val DCCM_SADR = "hF0040000".U(32.W)
val DCCM_SIZE = "h040".U(10.W)
val DCCM_WIDTH_BITS = "h2".U(2.W)
val DMA_BUF_DEPTH = "h5".U(3.W)
val DMA_BUS_ID = "h1".U(1.W)
val DMA_BUS_PRTY = "h2".U(2.W)
val DMA_BUS_TAG = "h1".U(4.W)
val FAST_INTERRUPT_REDIRECT= "h1".U(1.W)
val ICACHE_2BANKS = "h1".U(1.W)
val ICACHE_BANK_BITS = "h1".U(3.W)
val ICACHE_BANK_HI = "h3".U(3.W)
val ICACHE_BANK_LO = "h3".U(2.W)
val ICACHE_BANK_WIDTH = "h8".U(4.W)
val ICACHE_BANKS_WAY = "h2".U(3.W)
val ICACHE_BEAT_ADDR_HI = "h5".U(4.W)
val ICACHE_BEAT_BITS = "h3".U(4.W)
val ICACHE_DATA_DEPTH = "h0200".U(14.W)
val ICACHE_DATA_INDEX_LO = "h4".U(3.W)
val ICACHE_DATA_WIDTH = "h40".U(7.W)
val ICACHE_ECC = "h1".U(1.W)
val ICACHE_ENABLE = "h1".U(1.W)
val ICACHE_FDATA_WIDTH = "h47".U(7.W)
val ICACHE_INDEX_HI = "h0C".U(5.W)
val ICACHE_LN_SZ = "h40".U(7.W)
val ICACHE_NUM_BEATS = "h8".U(4.W)
val ICACHE_NUM_WAYS = "h2".U(3.W)
val ICACHE_ONLY = "h0".U(1.W)
val ICACHE_SCND_LAST = "h6".U(4.W)
val ICACHE_SIZE = "h010".U(9.W)
val ICACHE_STATUS_BITS = "h1".U(3.W)
val ICACHE_TAG_DEPTH = "h0080".U(13.W)
val ICACHE_TAG_INDEX_LO = "h6".U(3.W)
val ICACHE_TAG_LO = "h0D".U(5.W)
val ICACHE_WAYPACK = "h0".U(1.W)
val ICCM_BANK_BITS = "h2".U(3.W)
val ICCM_BANK_HI = "h03".U(5.W)
val ICCM_BANK_INDEX_LO = "h04".U(5.W)
val ICCM_BITS = "h10".U(5.W)
val ICCM_ENABLE = "h1".U(1.W)
val ICCM_ICACHE = "h1".U(1.W)
val ICCM_INDEX_BITS = "hC".U(4.W)
val ICCM_NUM_BANKS = "h04".U(5.W)
val ICCM_ONLY = "h0".U(1.W)
val ICCM_REGION = "hE".U(4.W)
val ICCM_SADR = "hEE000000".U(32.W)
val ICCM_SIZE = "h040".U(10.W)
val IFU_BUS_ID = "h1".U(1.W)
val IFU_BUS_PRTY = "h2".U(2.W)
val IFU_BUS_TAG = "h3".U(4.W)
val INST_ACCESS_ADDR0 = "h00000000".U(32.W)
val INST_ACCESS_ADDR1 = "hC0000000".U(32.W)
val INST_ACCESS_ADDR2 = "hA0000000".U(32.W)
val INST_ACCESS_ADDR3 = "h80000000".U(32.W)
val INST_ACCESS_ADDR4 = "h00000000".U(32.W)
val INST_ACCESS_ADDR5 = "h00000000".U(32.W)
val INST_ACCESS_ADDR6 = "h00000000".U(32.W)
val INST_ACCESS_ADDR7 = "h00000000".U(32.W)
val INST_ACCESS_ENABLE0 = "h1".U(1.W)
val INST_ACCESS_ENABLE1 = "h1".U(1.W)
val INST_ACCESS_ENABLE2 = "h1".U(1.W)
val INST_ACCESS_ENABLE3 = "h1".U(1.W)
val INST_ACCESS_ENABLE4 = "h0".U(1.W)
val INST_ACCESS_ENABLE5 = "h0".U(1.W)
val INST_ACCESS_ENABLE6 = "h0".U(1.W)
val INST_ACCESS_ENABLE7 = "h0".U(1.W)
val INST_ACCESS_MASK0 = "h7FFFFFFF".U(32.W)
val INST_ACCESS_MASK1 = "h3FFFFFFF".U(32.W)
val INST_ACCESS_MASK2 = "h1FFFFFFF".U(32.W)
val INST_ACCESS_MASK3 = "h0FFFFFFF".U(32.W)
val INST_ACCESS_MASK4 = "hFFFFFFFF".U(32.W)
val INST_ACCESS_MASK5 = "hFFFFFFFF".U(32.W)
val INST_ACCESS_MASK6 = "hFFFFFFFF".U(32.W)
val INST_ACCESS_MASK7 = "hFFFFFFFF".U(32.W)
val LOAD_TO_USE_PLUS1 = "h0".U(1.W)
val LSU2DMA = "h0".U(1.W)
val LSU_BUS_ID = "h1".U(1.W)
val LSU_BUS_PRTY = "h2".U(2.W)
val LSU_BUS_TAG = "h3".U(4.W)
val LSU_NUM_NBLOAD = "h04".U(5.W)
val LSU_NUM_NBLOAD_WIDTH = "h2".U(3.W)
val LSU_SB_BITS = "h10".U(5.W)
val LSU_STBUF_DEPTH = "h4".U(4.W)
val NO_ICCM_NO_ICACHE = "h0".U(1.W)
val PIC_2CYCLE = "h0".U(1.W)
val PIC_BASE_ADDR = "hF00C0000".U(32.W)
val PIC_BITS = "h0F".U(5.W)
val PIC_INT_WORDS = "h1".U(4.W)
val PIC_REGION = "hF".U(4.W)
val PIC_SIZE = "h020".U(9.W)
val PIC_TOTAL_INT = "h1F".U(8.W)
val PIC_TOTAL_INT_PLUS1 = "h020".U(9.W)
val RET_STACK_SIZE = "h8".U(4.W)
val SB_BUS_ID = "h1".U(1.W)
val SB_BUS_PRTY = "h2".U(2.W)
val SB_BUS_TAG = "h1".U(4.W)
val TIMER_LEGAL_EN = "h1".U(1.W)
}

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["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/el2_pic_ctrl.scala","6013727ad8913e69c2a7aa92386ef3d007222a52"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/exu/el2_exu.scala","3f9225ed252ed66244ffaadc30181214d49eae29"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/exu/el2_exu_alu_ctl.scala","53427614c56168767f6626fef1ae9edcaa98c2ff"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/include/el2_bundle.scala","e31d147291a415bbfb4846b78695a7385203e2c5"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lsu/el2_lsu.scala","1ef8375e06a926acc2800ce9f66b230a1a778a47"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dbg/el2_dbg.scala","a9288ad33e4be923745906ebdbedfc6940f5938b"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/ifu/el2_ifu.scala","90ccc65ac7488b8494521c865b772c52b8366feb"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_ib_ctl.scala","3f80243a4e22c30eedccccab540dc6c2e31dc399"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec.scala","94145e2a312952a3c6791d6eeb7f89c414f76b8a"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_gpr_ctl.scala","8cee95c67d7be69104cb66c7c313573d6b0bd1d7"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_dec_ctl.scala","564654df5ce8bc82515485b9e2fb2137a8b42a5c"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_tlu_ctl.scala","782b0d3a3699abda569dccdff2c48b1ade643dcf"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/test.scala","4ff4c6d27ac98fd9a89894d7fa467d531da7dcfe"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_decode_ctl.scala","12d275492ff0b62d3c9331bc254d503e4697648d"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dec/el2_dec_trigger.scala","06ff42965223482189db017d6c3edcd895c55229"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/dmi_wrapper.scala","e57d82ef2ee034749d59900097403d64f5d99c7f"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/rvjtag_tap.scala","725d115902c1948b83040e3ae82f26ae3d44ee4b"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/dmi/dmi_jtag_to_core_sync.scala","973d8d71d39c2efb8a9869b538f76cb3f12fbd98"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lib/beh_lib.scala","e7e638a7534f3091918cfb4eccb9737010d0504e"],["/home/abdulhameedakram/Documents/SweRV-Chislified/src/main/scala/lib/el2_lib.scala","8665016d9dfa28edf72a1e8b6e164174a0bc9c03"]],"lastModifiedTimes":[]}}] ["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala","e9418660ac1519eea2058bbd87d585d5d47343f0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala","503f063a2675efdbfb57a502a4fa60dea15b9331"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala","f24faa32ddf3bf63a73061d9d24e5c00058f3d2b"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala","f3dd5c2431ee23c1b5b158754bdad765cc909ba9"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala","6e8e5a15a1d60123a4f55018ef9caede35deeeb1"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala","a2fdfc7178e808f4bbb358784e7aa677d7fde3b6"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala","a66e9f0672f75f5a3288a7362ed7976e9d4048d0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala","474eec82140152f20417b6c1e4404d409f7f4a9b"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala","aa8a428318dab2b44f123bfe674710f400b73ff9"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala","3e2056149b7e8a89ba0809ff0082c71e3601820a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala","343974417ab69591d12c7d15a8bee798ad82be20"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala","9d4cedee7eee5415275809ba6f02d693324110fd"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala","a5028b217bfd6cc6fad3c8388d151e7f8fbcbe77"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala","9923de9bfd2f504ae2bb2b15c42a32ceaa2d5846"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala","0f9289fbd8cba0253e85afd8439b7fad7f368274"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala","d9c545afed0cc63a9ab0b880ec36abca3e7fb61a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala","d9284179851f33d9cd92a94f31bd327c1fdef9ac"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala","5168463f9c0e776c36750656998fc360fd269ab2"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala","191bf9cc863939ecf0cab24cdceca1b9b64223d4"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala","415669c1df1dfb3db6b4d92e4010e4ccf4870d7e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala","3c84af93ccb882d99b74852439d20c3b189dd518"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala","8d8d0e8ed37d5810d2b47b5762ccdb75afc7fce3"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala","013b036929ed7c9f917ba73eba950f188939743c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala","fd528764c26575f995645a109d8b55799591874c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala","dc91c0c780fed1ff374122dea516b6252fca923f"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala","d343e32edc9108a662b206313eaf1da425813eec"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala","ef5be7fa3e120fc7104f10ab2b519cca0905a566"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala","6c672ea7f0e7f4522288b3fe7f476dad6908ff30"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala","532968a2606c8c841ea8464c48293c06a0e069df"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala","ee1c243afb72958e00597a078bfb318805b9e8bc"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala","99a4c8d332a0802d19c3c31f621b978afaf986ff"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala","619171c0b49373f3aaf18f92aa659d8c05acbdfa"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala","03281ac6989dfaf67a9693a253a4aca96e04e5a1"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala","cb83a19d8b65a41e5dc8a61e2b4198c362c2d912"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala","6980af1cdf70a73b9d9dc1b6bdd14d50395cc8e0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala","7c91d79f3efef190e30f1ad2346f5113c7a5598a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala","76e2bf13097343ace8beed76c0d1bf730db133ed"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala","e1f606df5c404d0d829d3a680836da2d31e9197e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala","95624005291940cd8a95dba6bc01a44a0fd312f7"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala","ef85566d41d8ca0d3781ab005c86097221e11c28"]],"lastModifiedTimes":[]}}]

2
target/streams/compile/_global/_global/dependencyClasspathFiles/previous
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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar","/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar","/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar"]] ["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar","/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar"]]

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["dec.dec_dec_ctl","dec.dec_decode","dec.dec_main","dec.dec_trig","dec.gpr_gen","dec.ib_gen","dec.test","dec.tlu_gen","exu.alu","pic_main"] ["QUASAR_Wrp"]

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[debug] Acquiring lock on file /home/abdulhameed.akram/Documents/SweRV-Chislified/project/target/.sbt-compilation-infos/swerv-chislified-compile/.sbt-idea-lock ... [warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala:502:3: a pure expression does nothing in statement position; multiline expressions may require enclosing parentheses
[debug] Releasing lock on file /home/abdulhameed.akram/Documents/SweRV-Chislified/project/target/.sbt-compilation-infos/swerv-chislified-compile/.sbt-idea-lock. [warn]  bus_ifu_bus_clk_en
[warn]  ^
[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala:8:5: match may not be exhaustive.
[warn] It would fail on the following inputs: (0, _), (1, _), (??, _), (_, 0), (_, 1), (_, ??), (_, _)
[warn]  (ICACHE_WAYPACK, ICACHE_ECC) match{
[warn]  ^
[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala:1751:16: comparing values of types Int and Boolean using `==' will always yield false
[warn]  if(BUILD_AXI4 == true){
[warn]  ^
[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala:2122:17: comparing values of types Int and Boolean using `==' will always yield false
[warn]  if (ICACHE_ECC == true) {
[warn]  ^
[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala:2155:17: comparing values of types Int and Boolean using `==' will always yield false
[warn]  if (ICACHE_ECC == true) io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0))
[warn]  ^
[warn] there were 3738 feature warnings; re-run with -feature for details
[warn] 6 warnings found

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target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip
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[debug] Copy resource mappings:  [debug] Copy resource mappings: 
[debug]  (/home/abdulhameed.akram/Documents/SweRV-Chislified/src/main/resources/vsrc/gated_latch.v,/home/abdulhameed.akram/Documents/SweRV-Chislified/target/scala-2.12/classes/vsrc/gated_latch.v) [debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv)
[debug]  (/home/abdulhameed.akram/Documents/SweRV-Chislified/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv,/home/abdulhameed.akram/Documents/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv) [debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_wrapper.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_wrapper.sv)
[debug]  (/home/abdulhameed.akram/Documents/SweRV-Chislified/src/main/resources/vsrc/el2_mem.sv,/home/abdulhameed.akram/Documents/SweRV-Chislified/target/scala-2.12/classes/vsrc/el2_mem.sv) [debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv)
[debug]  (/home/abdulhameed.akram/Documents/SweRV-Chislified/src/main/resources/vsrc/el2_ifu_ic_mem.sv,/home/abdulhameed.akram/Documents/SweRV-Chislified/target/scala-2.12/classes/vsrc/el2_ifu_ic_mem.sv) [debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.v,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.v)
[debug]  (/home/abdulhameed.akram/Documents/SweRV-Chislified/src/main/resources/vsrc/el2_ifu_iccm_mem.sv,/home/abdulhameed.akram/Documents/SweRV-Chislified/target/scala-2.12/classes/vsrc/el2_ifu_iccm_mem.sv) [debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/beh_lib.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/beh_lib.sv)
[debug]  (/home/abdulhameed.akram/Documents/SweRV-Chislified/src/main/resources/vsrc/dmi_wrapper.sv,/home/abdulhameed.akram/Documents/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_wrapper.sv) [debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv)
[debug]  (/home/abdulhameed.akram/Documents/SweRV-Chislified/src/main/resources/vsrc/el2_lsu_dccm_mem.sv,/home/abdulhameed.akram/Documents/SweRV-Chislified/target/scala-2.12/classes/vsrc/el2_lsu_dccm_mem.sv) [debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvtaj_tap.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvtaj_tap.sv)
[debug]  (/home/abdulhameed.akram/Documents/SweRV-Chislified/src/main/resources/vsrc/rvtaj_tap.sv,/home/abdulhameed.akram/Documents/SweRV-Chislified/target/scala-2.12/classes/vsrc/rvtaj_tap.sv) [debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/gated_latch.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.sv)
[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/rvjtag_tap.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvjtag_tap.sv)
[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem.sv)
[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_lib.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_lib.sv)
[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/mem_mod.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_mod.sv)
[debug]  (/home/waleedbinehsan/Desktop/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv,/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv)

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/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar

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[debug] Jar uptodate: /home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar [debug] Packaging /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar ...
[debug] Input file mappings:
[debug]  pic_ctrl$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/pic_ctrl$$anon$1.class
[debug]  QUASAR_Wrp$delayedInit$body.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class
[debug]  ifu
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu
[debug]  ifu/ifu_aln_ctl$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_aln_ctl$$anon$1.class
[debug]  ifu/ifu_aln_ctl.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_aln_ctl.class
[debug]  ifu/ifu_compress_ctl$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_compress_ctl$$anon$1.class
[debug]  ifu/ifu_ifc_ctl$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_ifc_ctl$$anon$1.class
[debug]  ifu/mem_ctl_io.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/mem_ctl_io.class
[debug]  ifu/ifu_mem_ctl.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_mem_ctl.class
[debug]  ifu/ifu$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu$$anon$1.class
[debug]  ifu/ifu_ifc_ctl.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_ifc_ctl.class
[debug]  ifu/ifu.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu.class
[debug]  ifu/ifu_bp_ctl$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_bp_ctl$$anon$1.class
[debug]  ifu/ifu_compress_ctl.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_compress_ctl.class
[debug]  ifu/ifu_bp_ctl.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_bp_ctl.class
[debug]  QUASAR_Wrp$.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/QUASAR_Wrp$.class
[debug]  snapshot
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot
[debug]  snapshot/pt$.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot/pt$.class
[debug]  snapshot/pt.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot/pt.class
[debug]  quasar_wrapper.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar_wrapper.class
[debug]  vsrc
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc
[debug]  vsrc/ifu_iccm_mem.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv
[debug]  vsrc/dmi_wrapper.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_wrapper.sv
[debug]  vsrc/dmi_jtag_to_core_sync.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv
[debug]  vsrc/gated_latch.v
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.v
[debug]  vsrc/beh_lib.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/beh_lib.sv
[debug]  vsrc/lsu_dccm_mem.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv
[debug]  vsrc/rvtaj_tap.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvtaj_tap.sv
[debug]  vsrc/gated_latch.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/gated_latch.sv
[debug]  vsrc/rvjtag_tap.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/rvjtag_tap.sv
[debug]  vsrc/mem.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem.sv
[debug]  vsrc/mem_lib.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_lib.sv
[debug]  vsrc/mem_mod.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/mem_mod.sv
[debug]  vsrc/ifu_ic_mem.sv
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv
[debug]  lsu
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu
[debug]  lsu/lsu.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu.class
[debug]  lsu/lsu_dccm_ctl.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class
[debug]  lsu/lsu_trigger.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_trigger.class
[debug]  lsu/lsu_lsc_ctl.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class
[debug]  lsu/lsu_ecc.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_ecc.class
[debug]  lsu/lsu_bus_buffer.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_bus_buffer.class
[debug]  lsu/lsu_stbuf$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_stbuf$$anon$1.class
[debug]  lsu/lsu_clkdomain$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class
[debug]  lsu/lsu_lsc_ctl$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class
[debug]  lsu/lsu_bus_buffer$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class
[debug]  lsu/lsu_clkdomain.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_clkdomain.class
[debug]  lsu/lsu_stbuf.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_stbuf.class
[debug]  lsu/lsu_ecc$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class
[debug]  lsu/lsu_trigger$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_trigger$$anon$1.class
[debug]  lsu/lsu_addrcheck.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_addrcheck.class
[debug]  lsu/lsu_dccm_ctl$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class
[debug]  lsu/lsu_addrcheck$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class
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[debug]  dbg/state_t.class
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[debug]  lib/ahb_to_axi4.class
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[debug]  lib/axi4_to_ahb.class
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[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dma_ctrl.class
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[debug]  mem/Mem_bundle.class
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[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_mem_ctrl.class
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[debug]  include/lsu_exu.class
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[debug]  include/predict_pkt_t.class
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[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/exu_bp.class
[debug]  include/dec_tlu_csr_pkt.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class
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[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_alu.class
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[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_dec.class
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[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_data.class
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[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_data.class
[debug]  include/alu_pkt_t.class
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[debug]  include/read_addr$.class
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[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec
[debug]  dec/dec_trigger$$anon$1.class
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[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_timer_ctl.class
[debug]  dec/dec_dec_ctl$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_dec_ctl$$anon$1.class
[debug]  dec/dec_gpr_ctl_IO.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_gpr_ctl_IO.class
[debug]  dec/dec_ib_ctl.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_ib_ctl.class
[debug]  dec/CSR_IO.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/CSR_IO.class
[debug]  dec/dec_decode_ctl$$anon$1.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class
[debug]  dec/dec_decode_csr_read.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_csr_read.class
[debug]  dec/dec.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec.class
[debug]  dec/dec_decode_ctl.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_ctl.class
[debug]  dec/dec_trigger.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_trigger.class
[debug]  dec/csr_tlu.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/csr_tlu.class
[debug]  dec/dec_dec_ctl.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_dec_ctl.class
[debug]  dec/dec_gpr_ctl.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_gpr_ctl.class
[debug]  dec/CSRs.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/CSRs.class
[debug]  dec/dec_decode_csr_read_IO.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class
[debug]  dec/dec_tlu_ctl_IO.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class
[debug]  dec/dec_timer_ctl_IO.class
[debug]  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class
[debug] Done packaging.

2
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1893358648 -1025085726

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/home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar:/home/abdulhameedakram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameedakram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar

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/home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar

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/home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar:/home/abdulhameedakram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameedakram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameedakram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar

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/home/abdulhameedakram/Documents/SweRV-Chislified/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar