colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

stbuf with rvdffe

This commit is contained in:
​Laraib Khan 2020-12-22 18:10:15 +05:00
parent b1a6c0bf30
commit 01d018f555
7 changed files with 123 additions and 120 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

96
lsu_stbuf.fir
View File

@ -1019,91 +1019,91 @@ circuit lsu_stbuf :
stbuf_byteen[3] <= _T_661 @[lsu_stbuf.scala 165:18]
node _T_662 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 169:59]
node _T_663 = bits(_T_662, 0, 0) @[lsu_stbuf.scala 169:69]
inst rvclkhdr of rvclkhdr @[lib.scala 368:23]
inst rvclkhdr of rvclkhdr @[lib.scala 377:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 370:18]
rvclkhdr.io.en <= _T_663 @[lib.scala 371:17]
rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
reg _T_664 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_664 <= stbuf_addrin[0] @[lib.scala 374:16]
rvclkhdr.io.clk <= clock @[lib.scala 379:18]
rvclkhdr.io.en <= _T_663 @[lib.scala 380:17]
rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 381:24]
reg _T_664 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_664 <= stbuf_addrin[0] @[lib.scala 383:16]
stbuf_addr[0] <= _T_664 @[lsu_stbuf.scala 169:21]
node _T_665 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 170:59]
node _T_666 = bits(_T_665, 0, 0) @[lsu_stbuf.scala 170:69]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 368:23]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 377:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_1.io.en <= _T_666 @[lib.scala 371:17]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
reg _T_667 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_667 <= stbuf_datain[0] @[lib.scala 374:16]
rvclkhdr_1.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_1.io.en <= _T_666 @[lib.scala 380:17]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 381:24]
reg _T_667 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_667 <= stbuf_datain[0] @[lib.scala 383:16]
stbuf_data[0] <= _T_667 @[lsu_stbuf.scala 170:21]
node _T_668 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 169:59]
node _T_669 = bits(_T_668, 0, 0) @[lsu_stbuf.scala 169:69]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 377:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_2.io.en <= _T_669 @[lib.scala 371:17]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
reg _T_670 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_670 <= stbuf_addrin[1] @[lib.scala 374:16]
rvclkhdr_2.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_2.io.en <= _T_669 @[lib.scala 380:17]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 381:24]
reg _T_670 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_670 <= stbuf_addrin[1] @[lib.scala 383:16]
stbuf_addr[1] <= _T_670 @[lsu_stbuf.scala 169:21]
node _T_671 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 170:59]
node _T_672 = bits(_T_671, 0, 0) @[lsu_stbuf.scala 170:69]
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23]
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 377:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_3.io.en <= _T_672 @[lib.scala 371:17]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
reg _T_673 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_673 <= stbuf_datain[1] @[lib.scala 374:16]
rvclkhdr_3.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_3.io.en <= _T_672 @[lib.scala 380:17]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 381:24]
reg _T_673 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_673 <= stbuf_datain[1] @[lib.scala 383:16]
stbuf_data[1] <= _T_673 @[lsu_stbuf.scala 170:21]
node _T_674 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 169:59]
node _T_675 = bits(_T_674, 0, 0) @[lsu_stbuf.scala 169:69]
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23]
inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 377:23]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_4.io.en <= _T_675 @[lib.scala 371:17]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
reg _T_676 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_676 <= stbuf_addrin[2] @[lib.scala 374:16]
rvclkhdr_4.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_4.io.en <= _T_675 @[lib.scala 380:17]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 381:24]
reg _T_676 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_676 <= stbuf_addrin[2] @[lib.scala 383:16]
stbuf_addr[2] <= _T_676 @[lsu_stbuf.scala 169:21]
node _T_677 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 170:59]
node _T_678 = bits(_T_677, 0, 0) @[lsu_stbuf.scala 170:69]
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 368:23]
inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 377:23]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_5.io.en <= _T_678 @[lib.scala 371:17]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
reg _T_679 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_679 <= stbuf_datain[2] @[lib.scala 374:16]
rvclkhdr_5.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_5.io.en <= _T_678 @[lib.scala 380:17]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 381:24]
reg _T_679 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_679 <= stbuf_datain[2] @[lib.scala 383:16]
stbuf_data[2] <= _T_679 @[lsu_stbuf.scala 170:21]
node _T_680 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 169:59]
node _T_681 = bits(_T_680, 0, 0) @[lsu_stbuf.scala 169:69]
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 368:23]
inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 377:23]
rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_6.io.en <= _T_681 @[lib.scala 371:17]
rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
reg _T_682 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_682 <= stbuf_addrin[3] @[lib.scala 374:16]
rvclkhdr_6.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_6.io.en <= _T_681 @[lib.scala 380:17]
rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 381:24]
reg _T_682 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_682 <= stbuf_addrin[3] @[lib.scala 383:16]
stbuf_addr[3] <= _T_682 @[lsu_stbuf.scala 169:21]
node _T_683 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 170:59]
node _T_684 = bits(_T_683, 0, 0) @[lsu_stbuf.scala 170:69]
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 368:23]
inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 377:23]
rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_7.io.en <= _T_684 @[lib.scala 371:17]
rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
reg _T_685 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_685 <= stbuf_datain[3] @[lib.scala 374:16]
rvclkhdr_7.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_7.io.en <= _T_684 @[lib.scala 380:17]
rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 381:24]
reg _T_685 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_685 <= stbuf_datain[3] @[lib.scala 383:16]
stbuf_data[3] <= _T_685 @[lsu_stbuf.scala 170:21]
node _T_686 = dshr(stbuf_vld, RdPtr) @[lsu_stbuf.scala 183:43]
node _T_687 = bits(_T_686, 0, 0) @[lsu_stbuf.scala 183:43]

144
lsu_stbuf.v
View File

@ -107,38 +107,38 @@ module lsu_stbuf(
reg [31:0] _RAND_20;
reg [31:0] _RAND_21;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_io_en; // @[lib.scala 368:23]
wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_1_io_en; // @[lib.scala 368:23]
wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_2_io_en; // @[lib.scala 368:23]
wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_3_io_en; // @[lib.scala 368:23]
wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_4_io_en; // @[lib.scala 368:23]
wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_5_io_en; // @[lib.scala 368:23]
wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_6_io_en; // @[lib.scala 368:23]
wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_7_io_en; // @[lib.scala 368:23]
wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_io_en; // @[lib.scala 377:23]
wire rvclkhdr_io_scan_mode; // @[lib.scala 377:23]
wire rvclkhdr_1_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_1_io_en; // @[lib.scala 377:23]
wire rvclkhdr_1_io_scan_mode; // @[lib.scala 377:23]
wire rvclkhdr_2_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_2_io_en; // @[lib.scala 377:23]
wire rvclkhdr_2_io_scan_mode; // @[lib.scala 377:23]
wire rvclkhdr_3_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_3_io_en; // @[lib.scala 377:23]
wire rvclkhdr_3_io_scan_mode; // @[lib.scala 377:23]
wire rvclkhdr_4_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_4_io_en; // @[lib.scala 377:23]
wire rvclkhdr_4_io_scan_mode; // @[lib.scala 377:23]
wire rvclkhdr_5_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_5_io_en; // @[lib.scala 377:23]
wire rvclkhdr_5_io_scan_mode; // @[lib.scala 377:23]
wire rvclkhdr_6_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_6_io_en; // @[lib.scala 377:23]
wire rvclkhdr_6_io_scan_mode; // @[lib.scala 377:23]
wire rvclkhdr_7_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_7_io_en; // @[lib.scala 377:23]
wire rvclkhdr_7_io_scan_mode; // @[lib.scala 377:23]
wire [1:0] _T_5 = io_lsu_pkt_r_bits_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [3:0] _T_6 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [7:0] _T_7 = io_lsu_pkt_r_bits_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72]
@ -161,7 +161,7 @@ module lsu_stbuf(
wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[lsu_stbuf.scala 122:26]
wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[lsu_stbuf.scala 123:26]
wire _T_22 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_stbuf.scala 125:46]
reg [15:0] stbuf_addr_0; // @[lib.scala 374:16]
reg [15:0] stbuf_addr_0; // @[lib.scala 383:16]
wire _T_26 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
reg _T_587; // @[lsu_stbuf.scala 160:14]
reg _T_579; // @[lsu_stbuf.scala 160:14]
@ -188,21 +188,21 @@ module lsu_stbuf(
wire [3:0] stbuf_reset = {_T_214,_T_210,_T_206,_T_202}; // @[Cat.scala 29:58]
wire _T_33 = ~stbuf_reset[0]; // @[lsu_stbuf.scala 127:218]
wire _T_34 = _T_31 & _T_33; // @[lsu_stbuf.scala 127:216]
reg [15:0] stbuf_addr_1; // @[lib.scala 374:16]
reg [15:0] stbuf_addr_1; // @[lib.scala 383:16]
wire _T_37 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
wire _T_39 = _T_37 & stbuf_vld[1]; // @[lsu_stbuf.scala 127:179]
wire _T_41 = ~stbuf_dma_kill[1]; // @[lsu_stbuf.scala 127:197]
wire _T_42 = _T_39 & _T_41; // @[lsu_stbuf.scala 127:195]
wire _T_44 = ~stbuf_reset[1]; // @[lsu_stbuf.scala 127:218]
wire _T_45 = _T_42 & _T_44; // @[lsu_stbuf.scala 127:216]
reg [15:0] stbuf_addr_2; // @[lib.scala 374:16]
reg [15:0] stbuf_addr_2; // @[lib.scala 383:16]
wire _T_48 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
wire _T_50 = _T_48 & stbuf_vld[2]; // @[lsu_stbuf.scala 127:179]
wire _T_52 = ~stbuf_dma_kill[2]; // @[lsu_stbuf.scala 127:197]
wire _T_53 = _T_50 & _T_52; // @[lsu_stbuf.scala 127:195]
wire _T_55 = ~stbuf_reset[2]; // @[lsu_stbuf.scala 127:218]
wire _T_56 = _T_53 & _T_55; // @[lsu_stbuf.scala 127:216]
reg [15:0] stbuf_addr_3; // @[lib.scala 374:16]
reg [15:0] stbuf_addr_3; // @[lib.scala 383:16]
wire _T_59 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
wire _T_61 = _T_59 & stbuf_vld[3]; // @[lsu_stbuf.scala 127:179]
wire _T_63 = ~stbuf_dma_kill[3]; // @[lsu_stbuf.scala 127:197]
@ -319,28 +319,28 @@ module lsu_stbuf(
wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_285 : _T_286; // @[lsu_stbuf.scala 142:61]
wire _T_290 = ~stbuf_byteen_0[0]; // @[lsu_stbuf.scala 144:70]
wire _T_292 = _T_290 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
reg [31:0] stbuf_data_0; // @[lib.scala 374:16]
reg [31:0] stbuf_data_0; // @[lib.scala 383:16]
wire [7:0] _T_295 = _T_292 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 144:69]
wire _T_299 = _T_290 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
wire [7:0] _T_302 = _T_299 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 145:10]
wire [7:0] datain1_0 = sel_lo[0] ? _T_295 : _T_302; // @[lsu_stbuf.scala 144:54]
wire _T_306 = ~stbuf_byteen_1[0]; // @[lsu_stbuf.scala 144:70]
wire _T_308 = _T_306 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
reg [31:0] stbuf_data_1; // @[lib.scala 374:16]
reg [31:0] stbuf_data_1; // @[lib.scala 383:16]
wire [7:0] _T_311 = _T_308 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 144:69]
wire _T_315 = _T_306 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
wire [7:0] _T_318 = _T_315 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 145:10]
wire [7:0] datain1_1 = sel_lo[1] ? _T_311 : _T_318; // @[lsu_stbuf.scala 144:54]
wire _T_322 = ~stbuf_byteen_2[0]; // @[lsu_stbuf.scala 144:70]
wire _T_324 = _T_322 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
reg [31:0] stbuf_data_2; // @[lib.scala 374:16]
reg [31:0] stbuf_data_2; // @[lib.scala 383:16]
wire [7:0] _T_327 = _T_324 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 144:69]
wire _T_331 = _T_322 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
wire [7:0] _T_334 = _T_331 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 145:10]
wire [7:0] datain1_2 = sel_lo[2] ? _T_327 : _T_334; // @[lsu_stbuf.scala 144:54]
wire _T_338 = ~stbuf_byteen_3[0]; // @[lsu_stbuf.scala 144:70]
wire _T_340 = _T_338 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
reg [31:0] stbuf_data_3; // @[lib.scala 374:16]
reg [31:0] stbuf_data_3; // @[lib.scala 383:16]
wire [7:0] _T_343 = _T_340 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 144:69]
wire _T_347 = _T_338 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
wire [7:0] _T_350 = _T_347 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 145:10]
@ -770,49 +770,49 @@ module lsu_stbuf(
wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[lsu_stbuf.scala 271:30]
wire [15:0] _T_1309 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58]
wire [15:0] _T_1310 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58]
rvclkhdr rvclkhdr ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr_1 ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr_2 ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr_3 ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr_4 ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_4_io_l1clk),
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en),
.io_scan_mode(rvclkhdr_4_io_scan_mode)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr_5 ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_5_io_l1clk),
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr_6 ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_6_io_l1clk),
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en),
.io_scan_mode(rvclkhdr_6_io_scan_mode)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr_7 ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_7_io_l1clk),
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en),
@ -829,30 +829,30 @@ module lsu_stbuf(
assign io_stbuf_fwddata_lo_m = {_T_1295,_T_1294}; // @[lsu_stbuf.scala 59:43 lsu_stbuf.scala 266:25]
assign io_stbuf_fwdbyteen_hi_m = {_T_1269,_T_1261}; // @[lsu_stbuf.scala 60:37 lsu_stbuf.scala 258:27]
assign io_stbuf_fwdbyteen_lo_m = {_T_1280,_T_1272}; // @[lsu_stbuf.scala 61:37 lsu_stbuf.scala 259:27]
assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[lib.scala 371:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[lib.scala 371:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[lib.scala 371:17]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[lib.scala 371:17]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[lib.scala 371:17]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[lib.scala 371:17]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[lib.scala 371:17]
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[lib.scala 371:17]
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[lib.scala 380:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 381:24]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[lib.scala 380:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 381:24]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[lib.scala 380:17]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 381:24]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[lib.scala 380:17]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 381:24]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[lib.scala 380:17]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 381:24]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[lib.scala 380:17]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 381:24]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[lib.scala 380:17]
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 381:24]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[lib.scala 380:17]
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 381:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif

3
src/main/scala/lsu/lsu_stbuf.scala
View File

@ -270,4 +270,7 @@ class lsu_stbuf extends Module with lib with RequireAsyncReset {
val stbuf_fwdpipe3_hi = Mux(ld_byte_rhit_hi(2),ld_fwddata_rpipe_hi(23,16),stbuf_fwddata_hi_pre_m(23,16))
val stbuf_fwdpipe4_hi = Mux(ld_byte_rhit_hi(3),ld_fwddata_rpipe_hi(31,24),stbuf_fwddata_hi_pre_m(31,24))
io.stbuf_fwddata_hi_m := Cat(stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi,stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi)
}
object stbuf extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_stbuf()))
}

BIN
target/scala-2.12/classes/lsu/lsu_stbuf.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lsu/stbuf$.class Normal file
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lsu/stbuf$delayedInit$body.class Normal file
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lsu/stbuf.class Normal file
View File

Binary file not shown.