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IFC

This commit is contained in:
waleed-lm 2020-09-25 12:15:14 +05:00
parent ab68ee287d
commit 0228097e51
29 changed files with 1761 additions and 1508 deletions
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310
el2_ifu_bp_ctl.fir
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@ -38,6 +38,10 @@ circuit el2_ifu_bp_ctl :
btb_bank0_rd_data_way0_p1_f <= UInt<1>("h00") btb_bank0_rd_data_way0_p1_f <= UInt<1>("h00")
wire btb_bank0_rd_data_way1_p1_f : UInt<22> wire btb_bank0_rd_data_way1_p1_f : UInt<22>
btb_bank0_rd_data_way1_p1_f <= UInt<1>("h00") btb_bank0_rd_data_way1_p1_f <= UInt<1>("h00")
wire eoc_mask : UInt<1>
eoc_mask <= UInt<1>("h00")
wire btb_lru_b0_f : UInt<256>
btb_lru_b0_f <= UInt<1>("h00")
wire dec_tlu_way_wb : UInt<1> wire dec_tlu_way_wb : UInt<1>
dec_tlu_way_wb <= UInt<1>("h00") dec_tlu_way_wb <= UInt<1>("h00")
node _T_1 = bits(io.ifc_fetch_addr_f, 9, 2) @[el2_lib.scala 182:12] node _T_1 = bits(io.ifc_fetch_addr_f, 9, 2) @[el2_lib.scala 182:12]
@ -45,87 +49,241 @@ circuit el2_ifu_bp_ctl :
node _T_3 = xor(_T_1, _T_2) @[el2_lib.scala 182:42] node _T_3 = xor(_T_1, _T_2) @[el2_lib.scala 182:42]
node _T_4 = bits(io.ifc_fetch_addr_f, 25, 18) @[el2_lib.scala 182:80] node _T_4 = bits(io.ifc_fetch_addr_f, 25, 18) @[el2_lib.scala 182:80]
node btb_rd_addr_f = xor(_T_3, _T_4) @[el2_lib.scala 182:76] node btb_rd_addr_f = xor(_T_3, _T_4) @[el2_lib.scala 182:76]
node _T_5 = add(io.ifc_fetch_addr_f, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 103:45] node _T_5 = add(io.ifc_fetch_addr_f, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 106:45]
node fetch_addr_p1_f = tail(_T_5, 1) @[el2_ifu_bp_ctl.scala 103:45] node fetch_addr_p1_f = tail(_T_5, 1) @[el2_ifu_bp_ctl.scala 106:45]
node _T_6 = bits(fetch_addr_p1_f, 9, 2) @[el2_lib.scala 182:12] node _T_6 = bits(fetch_addr_p1_f, 9, 2) @[el2_lib.scala 182:12]
node _T_7 = bits(fetch_addr_p1_f, 17, 10) @[el2_lib.scala 182:46] node _T_7 = bits(fetch_addr_p1_f, 17, 10) @[el2_lib.scala 182:46]
node _T_8 = xor(_T_6, _T_7) @[el2_lib.scala 182:42] node _T_8 = xor(_T_6, _T_7) @[el2_lib.scala 182:42]
node _T_9 = bits(fetch_addr_p1_f, 25, 18) @[el2_lib.scala 182:80] node _T_9 = bits(fetch_addr_p1_f, 25, 18) @[el2_lib.scala 182:80]
node btb_rd_addr_p1_f = xor(_T_8, _T_9) @[el2_lib.scala 182:76] node btb_rd_addr_p1_f = xor(_T_8, _T_9) @[el2_lib.scala 182:76]
node _T_10 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 108:33] node _T_10 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 111:33]
node _T_11 = not(_T_10) @[el2_ifu_bp_ctl.scala 108:23] node _T_11 = not(_T_10) @[el2_ifu_bp_ctl.scala 111:23]
node _T_12 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 108:46] node _T_12 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 111:46]
node btb_sel_f = cat(_T_11, _T_12) @[Cat.scala 29:58] node btb_sel_f = cat(_T_11, _T_12) @[Cat.scala 29:58]
node _T_13 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 111:46] node _T_13 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 114:46]
node _T_14 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 111:70] node _T_14 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 114:70]
node _T_15 = not(_T_14) @[el2_ifu_bp_ctl.scala 111:50] node _T_15 = not(_T_14) @[el2_ifu_bp_ctl.scala 114:50]
node fetch_start_f = cat(_T_13, _T_15) @[Cat.scala 29:58] node fetch_start_f = cat(_T_13, _T_15) @[Cat.scala 29:58]
node _T_16 = eq(btb_error_addr_wb, btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 114:72] node _T_16 = eq(btb_error_addr_wb, btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 117:72]
node branch_error_collision_f = and(dec_tlu_error_wb, _T_16) @[el2_ifu_bp_ctl.scala 114:51] node branch_error_collision_f = and(dec_tlu_error_wb, _T_16) @[el2_ifu_bp_ctl.scala 117:51]
node _T_17 = eq(btb_error_addr_wb, btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 115:75] node _T_17 = eq(btb_error_addr_wb, btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 118:75]
node branch_error_collision_p1_f = and(dec_tlu_error_wb, _T_17) @[el2_ifu_bp_ctl.scala 115:54] node branch_error_collision_p1_f = and(dec_tlu_error_wb, _T_17) @[el2_ifu_bp_ctl.scala 118:54]
node branch_error_bank_conflict_f = and(branch_error_collision_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 118:63] node branch_error_bank_conflict_f = and(branch_error_collision_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 121:63]
node branch_error_bank_conflict_p1_f = and(branch_error_collision_p1_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 119:69] node branch_error_bank_conflict_p1_f = and(branch_error_collision_p1_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 122:69]
node _T_18 = eq(io.exu_mp_btag, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 122:46] node _T_18 = eq(io.exu_mp_btag, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 125:46]
node _T_19 = and(_T_18, exu_mp_valid) @[el2_ifu_bp_ctl.scala 122:66] node _T_19 = and(_T_18, exu_mp_valid) @[el2_ifu_bp_ctl.scala 125:66]
node _T_20 = and(_T_19, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 122:81] node _T_20 = and(_T_19, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 125:81]
node _T_21 = eq(io.exu_mp_index, btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 122:117] node _T_21 = eq(io.exu_mp_index, btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 125:117]
node fetch_mp_collision_f = and(_T_20, _T_21) @[el2_ifu_bp_ctl.scala 122:102] node fetch_mp_collision_f = and(_T_20, _T_21) @[el2_ifu_bp_ctl.scala 125:102]
node _T_22 = eq(io.exu_mp_btag, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 123:49] node _T_22 = eq(io.exu_mp_btag, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 126:49]
node _T_23 = and(_T_22, exu_mp_valid) @[el2_ifu_bp_ctl.scala 123:72] node _T_23 = and(_T_22, exu_mp_valid) @[el2_ifu_bp_ctl.scala 126:72]
node _T_24 = and(_T_23, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 123:87] node _T_24 = and(_T_23, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 126:87]
node _T_25 = eq(io.exu_mp_index, btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 123:123] node _T_25 = eq(io.exu_mp_index, btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 126:123]
node fetch_mp_collision_p1_f = and(_T_24, _T_25) @[el2_ifu_bp_ctl.scala 123:108] node fetch_mp_collision_p1_f = and(_T_24, _T_25) @[el2_ifu_bp_ctl.scala 126:108]
reg leak_one_f_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 125:30] reg leak_one_f_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 128:30]
leak_one_f_d1 <= leak_one_f @[el2_ifu_bp_ctl.scala 125:30] leak_one_f_d1 <= leak_one_f @[el2_ifu_bp_ctl.scala 128:30]
reg dec_tlu_way_wb_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 126:33] reg dec_tlu_way_wb_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 129:33]
dec_tlu_way_wb_f <= dec_tlu_way_wb @[el2_ifu_bp_ctl.scala 126:33] dec_tlu_way_wb_f <= dec_tlu_way_wb @[el2_ifu_bp_ctl.scala 129:33]
reg exu_mp_way_f : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 127:29] reg exu_mp_way_f : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 130:29]
exu_mp_way_f <= io.exu_mp_pkt.way @[el2_ifu_bp_ctl.scala 127:29] exu_mp_way_f <= io.exu_mp_pkt.way @[el2_ifu_bp_ctl.scala 130:29]
reg exu_flush_final_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 128:35] reg exu_flush_final_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 131:35]
exu_flush_final_d1 <= io.exu_flush_final @[el2_ifu_bp_ctl.scala 128:35] exu_flush_final_d1 <= io.exu_flush_final @[el2_ifu_bp_ctl.scala 131:35]
node _T_26 = and(io.dec_tlu_flush_leak_one_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 130:47] node _T_26 = and(io.dec_tlu_flush_leak_one_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 133:47]
node _T_27 = and(leak_one_f_d1, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 130:93] node _T_27 = and(leak_one_f_d1, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 133:93]
node _T_28 = or(_T_26, _T_27) @[el2_ifu_bp_ctl.scala 130:76] node _T_28 = or(_T_26, _T_27) @[el2_ifu_bp_ctl.scala 133:76]
leak_one_f <= _T_28 @[el2_ifu_bp_ctl.scala 130:14] leak_one_f <= _T_28 @[el2_ifu_bp_ctl.scala 133:14]
node _T_29 = bits(btb_bank0_rd_data_way0_f, 0, 0) @[el2_ifu_bp_ctl.scala 133:50] node _T_29 = bits(btb_bank0_rd_data_way0_f, 0, 0) @[el2_ifu_bp_ctl.scala 136:50]
node _T_30 = bits(btb_bank0_rd_data_way0_f, 21, 17) @[el2_ifu_bp_ctl.scala 133:82] node _T_30 = bits(btb_bank0_rd_data_way0_f, 21, 17) @[el2_ifu_bp_ctl.scala 136:82]
node _T_31 = eq(_T_30, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 133:97] node _T_31 = eq(_T_30, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 136:97]
node _T_32 = and(_T_29, _T_31) @[el2_ifu_bp_ctl.scala 133:55] node _T_32 = and(_T_29, _T_31) @[el2_ifu_bp_ctl.scala 136:55]
node _T_33 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 134:22] node _T_33 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 137:22]
node _T_34 = not(_T_33) @[el2_ifu_bp_ctl.scala 134:3] node _T_34 = not(_T_33) @[el2_ifu_bp_ctl.scala 137:3]
node _T_35 = and(_T_32, _T_34) @[el2_ifu_bp_ctl.scala 133:117] node _T_35 = and(_T_32, _T_34) @[el2_ifu_bp_ctl.scala 136:117]
node _T_36 = and(_T_35, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 134:54] node _T_36 = and(_T_35, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 137:54]
node _T_37 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 134:77] node _T_37 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 137:77]
node tag_match_way0_f = and(_T_36, _T_37) @[el2_ifu_bp_ctl.scala 134:75] node tag_match_way0_f = and(_T_36, _T_37) @[el2_ifu_bp_ctl.scala 137:75]
node _T_38 = bits(btb_bank0_rd_data_way1_f, 0, 0) @[el2_ifu_bp_ctl.scala 136:50] node _T_38 = bits(btb_bank0_rd_data_way1_f, 0, 0) @[el2_ifu_bp_ctl.scala 139:50]
node _T_39 = bits(btb_bank0_rd_data_way1_f, 21, 17) @[el2_ifu_bp_ctl.scala 136:82] node _T_39 = bits(btb_bank0_rd_data_way1_f, 21, 17) @[el2_ifu_bp_ctl.scala 139:82]
node _T_40 = eq(_T_39, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 136:97] node _T_40 = eq(_T_39, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 139:97]
node _T_41 = and(_T_38, _T_40) @[el2_ifu_bp_ctl.scala 136:55] node _T_41 = and(_T_38, _T_40) @[el2_ifu_bp_ctl.scala 139:55]
node _T_42 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 137:22] node _T_42 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 140:22]
node _T_43 = not(_T_42) @[el2_ifu_bp_ctl.scala 137:3] node _T_43 = not(_T_42) @[el2_ifu_bp_ctl.scala 140:3]
node _T_44 = and(_T_41, _T_43) @[el2_ifu_bp_ctl.scala 136:117] node _T_44 = and(_T_41, _T_43) @[el2_ifu_bp_ctl.scala 139:117]
node _T_45 = and(_T_44, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 137:54] node _T_45 = and(_T_44, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 140:54]
node _T_46 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 137:77] node _T_46 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 140:77]
node tag_match_way1_f = and(_T_45, _T_46) @[el2_ifu_bp_ctl.scala 137:75] node tag_match_way1_f = and(_T_45, _T_46) @[el2_ifu_bp_ctl.scala 140:75]
node _T_47 = bits(btb_bank0_rd_data_way0_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 139:56] node _T_47 = bits(btb_bank0_rd_data_way0_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 142:56]
node _T_48 = bits(btb_bank0_rd_data_way0_p1_f, 21, 17) @[el2_ifu_bp_ctl.scala 139:91] node _T_48 = bits(btb_bank0_rd_data_way0_p1_f, 21, 17) @[el2_ifu_bp_ctl.scala 142:91]
node _T_49 = eq(_T_48, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 139:106] node _T_49 = eq(_T_48, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 142:106]
node _T_50 = and(_T_47, _T_49) @[el2_ifu_bp_ctl.scala 139:61] node _T_50 = and(_T_47, _T_49) @[el2_ifu_bp_ctl.scala 142:61]
node _T_51 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 140:24] node _T_51 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 143:24]
node _T_52 = not(_T_51) @[el2_ifu_bp_ctl.scala 140:5] node _T_52 = not(_T_51) @[el2_ifu_bp_ctl.scala 143:5]
node _T_53 = and(_T_50, _T_52) @[el2_ifu_bp_ctl.scala 139:129] node _T_53 = and(_T_50, _T_52) @[el2_ifu_bp_ctl.scala 142:129]
node _T_54 = and(_T_53, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 140:56] node _T_54 = and(_T_53, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 143:56]
node _T_55 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 140:79] node _T_55 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 143:79]
node tag_match_way0_p1_f = and(_T_54, _T_55) @[el2_ifu_bp_ctl.scala 140:77] node tag_match_way0_p1_f = and(_T_54, _T_55) @[el2_ifu_bp_ctl.scala 143:77]
node _T_56 = bits(btb_bank0_rd_data_way1_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 142:56] node _T_56 = bits(btb_bank0_rd_data_way1_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 145:56]
node _T_57 = bits(btb_bank0_rd_data_way1_p1_f, 21, 17) @[el2_ifu_bp_ctl.scala 142:91] node _T_57 = bits(btb_bank0_rd_data_way1_p1_f, 21, 17) @[el2_ifu_bp_ctl.scala 145:91]
node _T_58 = eq(_T_57, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 142:106] node _T_58 = eq(_T_57, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 145:106]
node _T_59 = and(_T_56, _T_58) @[el2_ifu_bp_ctl.scala 142:61] node _T_59 = and(_T_56, _T_58) @[el2_ifu_bp_ctl.scala 145:61]
node _T_60 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 143:24] node _T_60 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 146:24]
node _T_61 = not(_T_60) @[el2_ifu_bp_ctl.scala 143:5] node _T_61 = not(_T_60) @[el2_ifu_bp_ctl.scala 146:5]
node _T_62 = and(_T_59, _T_61) @[el2_ifu_bp_ctl.scala 142:129] node _T_62 = and(_T_59, _T_61) @[el2_ifu_bp_ctl.scala 145:129]
node _T_63 = and(_T_62, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 143:56] node _T_63 = and(_T_62, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 146:56]
node _T_64 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 143:79] node _T_64 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 146:79]
node tag_match_way1_p1_f = and(_T_63, _T_64) @[el2_ifu_bp_ctl.scala 143:77] node tag_match_way1_p1_f = and(_T_63, _T_64) @[el2_ifu_bp_ctl.scala 146:77]
node _T_65 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[el2_ifu_bp_ctl.scala 149:84]
node _T_66 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[el2_ifu_bp_ctl.scala 149:117]
node _T_67 = xor(_T_65, _T_66) @[el2_ifu_bp_ctl.scala 149:91]
node _T_68 = and(tag_match_way0_f, _T_67) @[el2_ifu_bp_ctl.scala 149:56]
node _T_69 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[el2_ifu_bp_ctl.scala 150:50]
node _T_70 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[el2_ifu_bp_ctl.scala 150:83]
node _T_71 = xor(_T_69, _T_70) @[el2_ifu_bp_ctl.scala 150:57]
node _T_72 = not(_T_71) @[el2_ifu_bp_ctl.scala 150:24]
node _T_73 = and(tag_match_way0_f, _T_72) @[el2_ifu_bp_ctl.scala 150:22]
node tag_match_way0_expanded_f = cat(_T_68, _T_73) @[Cat.scala 29:58]
node _T_74 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[el2_ifu_bp_ctl.scala 152:84]
node _T_75 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[el2_ifu_bp_ctl.scala 152:117]
node _T_76 = xor(_T_74, _T_75) @[el2_ifu_bp_ctl.scala 152:91]
node _T_77 = and(tag_match_way1_f, _T_76) @[el2_ifu_bp_ctl.scala 152:56]
node _T_78 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[el2_ifu_bp_ctl.scala 153:50]
node _T_79 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[el2_ifu_bp_ctl.scala 153:83]
node _T_80 = xor(_T_78, _T_79) @[el2_ifu_bp_ctl.scala 153:57]
node _T_81 = not(_T_80) @[el2_ifu_bp_ctl.scala 153:24]
node _T_82 = and(tag_match_way1_f, _T_81) @[el2_ifu_bp_ctl.scala 153:22]
node tag_match_way1_expanded_f = cat(_T_77, _T_82) @[Cat.scala 29:58]
node _T_83 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 156:93]
node _T_84 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 156:129]
node _T_85 = xor(_T_83, _T_84) @[el2_ifu_bp_ctl.scala 156:100]
node _T_86 = and(tag_match_way0_p1_f, _T_85) @[el2_ifu_bp_ctl.scala 156:62]
node _T_87 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 157:56]
node _T_88 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 157:92]
node _T_89 = xor(_T_87, _T_88) @[el2_ifu_bp_ctl.scala 157:63]
node _T_90 = not(_T_89) @[el2_ifu_bp_ctl.scala 157:27]
node _T_91 = and(tag_match_way0_p1_f, _T_90) @[el2_ifu_bp_ctl.scala 157:25]
node tag_match_way0_expanded_p1_f = cat(_T_86, _T_91) @[Cat.scala 29:58]
node _T_92 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 159:93]
node _T_93 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 159:129]
node _T_94 = xor(_T_92, _T_93) @[el2_ifu_bp_ctl.scala 159:100]
node _T_95 = and(tag_match_way1_p1_f, _T_94) @[el2_ifu_bp_ctl.scala 159:62]
node _T_96 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 160:56]
node _T_97 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 160:92]
node _T_98 = xor(_T_96, _T_97) @[el2_ifu_bp_ctl.scala 160:63]
node _T_99 = not(_T_98) @[el2_ifu_bp_ctl.scala 160:27]
node _T_100 = and(tag_match_way1_p1_f, _T_99) @[el2_ifu_bp_ctl.scala 160:25]
node tag_match_way1_expanded_p1_f = cat(_T_95, _T_100) @[Cat.scala 29:58]
node wayhit_f = or(tag_match_way0_expanded_f, tag_match_way1_expanded_f) @[el2_ifu_bp_ctl.scala 162:44]
node wayhit_p1_f = or(tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f) @[el2_ifu_bp_ctl.scala 164:50]
node _T_101 = bits(tag_match_way0_expanded_f, 0, 0) @[el2_ifu_bp_ctl.scala 167:65]
node _T_102 = bits(_T_101, 0, 0) @[el2_ifu_bp_ctl.scala 167:69]
node _T_103 = bits(tag_match_way1_expanded_f, 0, 0) @[el2_ifu_bp_ctl.scala 168:30]
node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_bp_ctl.scala 168:34]
node _T_105 = mux(_T_102, btb_bank0_rd_data_way0_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_106 = mux(_T_104, btb_bank0_rd_data_way1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_107 = or(_T_105, _T_106) @[Mux.scala 27:72]
wire btb_bank0e_rd_data_f : UInt<22> @[Mux.scala 27:72]
btb_bank0e_rd_data_f <= _T_107 @[Mux.scala 27:72]
node _T_108 = bits(tag_match_way0_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 170:65]
node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_bp_ctl.scala 170:69]
node _T_110 = bits(tag_match_way1_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 171:30]
node _T_111 = bits(_T_110, 0, 0) @[el2_ifu_bp_ctl.scala 171:34]
node _T_112 = mux(_T_109, btb_bank0_rd_data_way0_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_113 = mux(_T_111, btb_bank0_rd_data_way1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_114 = or(_T_112, _T_113) @[Mux.scala 27:72]
wire btb_bank0o_rd_data_f : UInt<22> @[Mux.scala 27:72]
btb_bank0o_rd_data_f <= _T_114 @[Mux.scala 27:72]
node _T_115 = bits(tag_match_way0_expanded_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 173:71]
node _T_116 = bits(_T_115, 0, 0) @[el2_ifu_bp_ctl.scala 173:75]
node _T_117 = bits(tag_match_way1_expanded_p1_f, 1, 1) @[el2_ifu_bp_ctl.scala 174:33]
node _T_118 = bits(_T_117, 0, 0) @[el2_ifu_bp_ctl.scala 174:37]
node _T_119 = mux(_T_116, btb_bank0_rd_data_way0_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_120 = mux(_T_118, btb_bank0_rd_data_way1_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_121 = or(_T_119, _T_120) @[Mux.scala 27:72]
wire btb_bank0e_rd_data_p1_f : UInt<22> @[Mux.scala 27:72]
btb_bank0e_rd_data_p1_f <= _T_121 @[Mux.scala 27:72]
node _T_122 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 177:60]
node _T_123 = not(_T_122) @[el2_ifu_bp_ctl.scala 177:40]
node _T_124 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 178:24]
node _T_125 = mux(_T_123, btb_bank0e_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_126 = mux(_T_124, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_127 = or(_T_125, _T_126) @[Mux.scala 27:72]
wire btb_vbank0_rd_data_f : UInt<22> @[Mux.scala 27:72]
btb_vbank0_rd_data_f <= _T_127 @[Mux.scala 27:72]
node _T_128 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_bp_ctl.scala 180:60]
node _T_129 = not(_T_128) @[el2_ifu_bp_ctl.scala 180:40]
node _T_130 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_bp_ctl.scala 181:24]
node _T_131 = mux(_T_129, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_132 = mux(_T_130, btb_bank0e_rd_data_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_133 = or(_T_131, _T_132) @[Mux.scala 27:72]
wire btb_vbank1_rd_data_f : UInt<22> @[Mux.scala 27:72]
btb_vbank1_rd_data_f <= _T_133 @[Mux.scala 27:72]
node mp_wrindex_dec = dshl(UInt<1>("h00"), io.exu_mp_index) @[el2_ifu_bp_ctl.scala 184:38]
node fetch_wrindex_dec = dshl(UInt<1>("h00"), btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 185:41]
node fetch_wrindex_p1_dec = dshl(UInt<1>("h00"), btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 186:44]
node _T_134 = bits(exu_mp_valid, 0, 0) @[Bitwise.scala 72:15]
node _T_135 = mux(_T_134, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
node mp_wrlru_b0 = and(mp_wrindex_dec, _T_135) @[el2_ifu_bp_ctl.scala 187:36]
node _T_136 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 189:49]
node _T_137 = bits(_T_136, 0, 0) @[el2_ifu_bp_ctl.scala 189:53]
node _T_138 = not(_T_137) @[el2_ifu_bp_ctl.scala 189:29]
node _T_139 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 190:24]
node _T_140 = bits(_T_139, 0, 0) @[el2_ifu_bp_ctl.scala 190:28]
node _T_141 = bits(wayhit_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 190:51]
node _T_142 = bits(wayhit_f, 1, 1) @[el2_ifu_bp_ctl.scala 190:64]
node _T_143 = cat(_T_141, _T_142) @[Cat.scala 29:58]
node _T_144 = mux(_T_138, wayhit_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_145 = mux(_T_140, _T_143, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_146 = or(_T_144, _T_145) @[Mux.scala 27:72]
wire _T_147 : UInt<2> @[Mux.scala 27:72]
_T_147 <= _T_146 @[Mux.scala 27:72]
node _T_148 = cat(eoc_mask, UInt<1>("h01")) @[Cat.scala 29:58]
node vwayhit_f = and(_T_147, _T_148) @[el2_ifu_bp_ctl.scala 190:71]
node _T_149 = bits(vwayhit_f, 0, 0) @[el2_ifu_bp_ctl.scala 191:38]
node _T_150 = bits(vwayhit_f, 1, 1) @[el2_ifu_bp_ctl.scala 191:53]
node _T_151 = or(_T_149, _T_150) @[el2_ifu_bp_ctl.scala 191:42]
node _T_152 = and(_T_151, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 191:58]
node _T_153 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 191:81]
node lru_update_valid_f = and(_T_152, _T_153) @[el2_ifu_bp_ctl.scala 191:79]
node _T_154 = bits(lru_update_valid_f, 0, 0) @[Bitwise.scala 72:15]
node _T_155 = mux(_T_154, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
node fetch_wrlru_b0 = and(fetch_wrindex_dec, _T_155) @[el2_ifu_bp_ctl.scala 193:42]
node _T_156 = bits(lru_update_valid_f, 0, 0) @[Bitwise.scala 72:15]
node _T_157 = mux(_T_156, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
node fetch_wrlru_p1_b0 = and(fetch_wrindex_p1_dec, _T_157) @[el2_ifu_bp_ctl.scala 194:48]
node _T_158 = not(mp_wrlru_b0) @[el2_ifu_bp_ctl.scala 196:25]
node _T_159 = not(fetch_wrlru_b0) @[el2_ifu_bp_ctl.scala 196:40]
node btb_lru_b0_hold = and(_T_158, _T_159) @[el2_ifu_bp_ctl.scala 196:38]
node _T_160 = bits(io.exu_mp_pkt.way, 0, 0) @[el2_ifu_bp_ctl.scala 200:45]
node _T_161 = not(_T_160) @[el2_ifu_bp_ctl.scala 200:33]
node _T_162 = bits(tag_match_way0_f, 0, 0) @[el2_ifu_bp_ctl.scala 201:22]
node _T_163 = bits(tag_match_way0_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 201:65]
node _T_164 = mux(_T_161, mp_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_165 = mux(_T_162, fetch_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_166 = mux(_T_163, fetch_wrlru_p1_b0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_167 = or(_T_164, _T_165) @[Mux.scala 27:72]
node _T_168 = or(_T_167, _T_166) @[Mux.scala 27:72]
wire _T_169 : UInt<256> @[Mux.scala 27:72]
_T_169 <= _T_168 @[Mux.scala 27:72]
node _T_170 = and(btb_lru_b0_hold, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 201:111]
node btb_lru_b0_ns = or(_T_169, _T_170) @[el2_ifu_bp_ctl.scala 201:93]
node _T_171 = bits(fetch_mp_collision_f, 0, 0) @[el2_ifu_bp_ctl.scala 203:37]
node _T_172 = and(fetch_wrindex_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 203:78]
node _T_173 = orr(_T_172) @[el2_ifu_bp_ctl.scala 203:94]
node btb_lru_rd_f = mux(_T_171, exu_mp_way_f, _T_173) @[el2_ifu_bp_ctl.scala 203:25]
node _T_174 = bits(fetch_mp_collision_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 204:43]
node _T_175 = and(fetch_wrindex_p1_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 204:87]
node _T_176 = orr(_T_175) @[el2_ifu_bp_ctl.scala 204:103]
node btb_lru_rd_p1_f = mux(_T_174, exu_mp_way_f, _T_176) @[el2_ifu_bp_ctl.scala 204:28]
node _T_177 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 206:53]
node _T_178 = bits(_T_177, 0, 0) @[el2_ifu_bp_ctl.scala 206:57]
node _T_179 = not(_T_178) @[el2_ifu_bp_ctl.scala 206:33]
node _T_180 = cat(btb_lru_rd_f, btb_lru_rd_f) @[Cat.scala 29:58]
node _T_181 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 207:24]
node _T_182 = bits(_T_181, 0, 0) @[el2_ifu_bp_ctl.scala 207:28]
node _T_183 = cat(btb_lru_rd_p1_f, btb_lru_rd_f) @[Cat.scala 29:58]
node _T_184 = mux(_T_179, _T_180, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_185 = mux(_T_182, _T_183, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_186 = or(_T_184, _T_185) @[Mux.scala 27:72]
wire btb_vlru_rd_f : UInt @[Mux.scala 27:72]
btb_vlru_rd_f <= _T_186 @[Mux.scala 27:72]

1606
el2_ifu_compress.fir
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File diff suppressed because it is too large Load Diff

426
el2_ifu_compress.v
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@ -9,8 +9,8 @@ module el2_ifu_compress(
output [4:0] io_out_rs3, output [4:0] io_out_rs3,
output io_rvc output io_rvc
); );
wire _T_3 = |io_in[12:5]; // @[el2_ifu_compress.scala 49:29] wire _T_3 = |io_in[12:5]; // @[el2_ifu_compress.scala 48:29]
wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 49:20] wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 48:20]
wire [4:0] _T_14 = {2'h1,io_in[4:2]}; // @[Cat.scala 29:58] wire [4:0] _T_14 = {2'h1,io_in[4:2]}; // @[Cat.scala 29:58]
wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58] wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58]
wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58] wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
@ -26,33 +26,33 @@ module el2_ifu_compress(
wire [6:0] _T_205 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12] wire [6:0] _T_205 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [11:0] _T_207 = {_T_205,io_in[6:2]}; // @[Cat.scala 29:58] wire [11:0] _T_207 = {_T_205,io_in[6:2]}; // @[Cat.scala 29:58]
wire [31:0] _T_213 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58] wire [31:0] _T_213 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire _T_221 = |io_in[11:7]; // @[el2_ifu_compress.scala 73:24] wire _T_221 = |io_in[11:7]; // @[el2_ifu_compress.scala 72:24]
wire [6:0] _T_222 = _T_221 ? 7'h1b : 7'h1f; // @[el2_ifu_compress.scala 73:20] wire [6:0] _T_222 = _T_221 ? 7'h1b : 7'h1f; // @[el2_ifu_compress.scala 72:20]
wire [31:0] _T_233 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],_T_222}; // @[Cat.scala 29:58] wire [31:0] _T_233 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],_T_222}; // @[Cat.scala 29:58]
wire [31:0] _T_249 = {_T_205,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58] wire [31:0] _T_249 = {_T_205,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire _T_260 = |_T_207; // @[el2_ifu_compress.scala 86:29] wire _T_260 = |_T_207; // @[el2_ifu_compress.scala 85:29]
wire [6:0] _T_261 = _T_260 ? 7'h37 : 7'h3f; // @[el2_ifu_compress.scala 86:20] wire [6:0] _T_261 = _T_260 ? 7'h37 : 7'h3f; // @[el2_ifu_compress.scala 85:20]
wire [14:0] _T_264 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12] wire [14:0] _T_264 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_267 = {_T_264,io_in[6:2],12'h0}; // @[Cat.scala 29:58] wire [31:0] _T_267 = {_T_264,io_in[6:2],12'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_271 = {_T_267[31:12],io_in[11:7],_T_261}; // @[Cat.scala 29:58] wire [31:0] _T_271 = {_T_267[31:12],io_in[11:7],_T_261}; // @[Cat.scala 29:58]
wire _T_279 = io_in[11:7] == 5'h0; // @[el2_ifu_compress.scala 88:14] wire _T_279 = io_in[11:7] == 5'h0; // @[el2_ifu_compress.scala 87:14]
wire _T_281 = io_in[11:7] == 5'h2; // @[el2_ifu_compress.scala 88:27] wire _T_281 = io_in[11:7] == 5'h2; // @[el2_ifu_compress.scala 87:27]
wire _T_282 = _T_279 | _T_281; // @[el2_ifu_compress.scala 88:21] wire _T_282 = _T_279 | _T_281; // @[el2_ifu_compress.scala 87:21]
wire [6:0] _T_289 = _T_260 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 82:20] wire [6:0] _T_289 = _T_260 ? 7'h13 : 7'h1f; // @[el2_ifu_compress.scala 81:20]
wire [2:0] _T_292 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [2:0] _T_292 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_307 = {_T_292,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_289}; // @[Cat.scala 29:58] wire [31:0] _T_307 = {_T_292,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_289}; // @[Cat.scala 29:58]
wire [31:0] _T_314_bits = _T_282 ? _T_307 : _T_271; // @[el2_ifu_compress.scala 88:10] wire [31:0] _T_314_bits = _T_282 ? _T_307 : _T_271; // @[el2_ifu_compress.scala 87:10]
wire [4:0] _T_314_rd = _T_282 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 88:10] wire [4:0] _T_314_rd = _T_282 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 87:10]
wire [4:0] _T_314_rs2 = _T_282 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 88:10] wire [4:0] _T_314_rs2 = _T_282 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 87:10]
wire [4:0] _T_314_rs3 = _T_282 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 88:10] wire [4:0] _T_314_rs3 = _T_282 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 87:10]
wire [25:0] _T_325 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58] wire [25:0] _T_325 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
wire [30:0] _GEN_172 = {{5'd0}, _T_325}; // @[el2_ifu_compress.scala 95:23] wire [30:0] _GEN_172 = {{5'd0}, _T_325}; // @[el2_ifu_compress.scala 94:23]
wire [30:0] _T_337 = _GEN_172 | 31'h40000000; // @[el2_ifu_compress.scala 95:23] wire [30:0] _T_337 = _GEN_172 | 31'h40000000; // @[el2_ifu_compress.scala 94:23]
wire [31:0] _T_350 = {_T_205,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58] wire [31:0] _T_350 = {_T_205,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
wire [2:0] _T_354 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58] wire [2:0] _T_354 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58]
wire _T_356 = io_in[6:5] == 2'h0; // @[el2_ifu_compress.scala 99:30] wire _T_356 = io_in[6:5] == 2'h0; // @[el2_ifu_compress.scala 98:30]
wire [30:0] _T_357 = _T_356 ? 31'h40000000 : 31'h0; // @[el2_ifu_compress.scala 99:22] wire [30:0] _T_357 = _T_356 ? 31'h40000000 : 31'h0; // @[el2_ifu_compress.scala 98:22]
wire [6:0] _T_359 = io_in[12] ? 7'h3b : 7'h33; // @[el2_ifu_compress.scala 100:22] wire [6:0] _T_359 = io_in[12] ? 7'h3b : 7'h33; // @[el2_ifu_compress.scala 99:22]
wire [2:0] _GEN_1 = 3'h1 == _T_354 ? 3'h4 : 3'h0; // @[Cat.scala 29:58] wire [2:0] _GEN_1 = 3'h1 == _T_354 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
wire [2:0] _GEN_2 = 3'h2 == _T_354 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58] wire [2:0] _GEN_2 = 3'h2 == _T_354 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
wire [2:0] _GEN_3 = 3'h3 == _T_354 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58] wire [2:0] _GEN_3 = 3'h3 == _T_354 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
@ -61,14 +61,14 @@ module el2_ifu_compress(
wire [2:0] _GEN_6 = 3'h6 == _T_354 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58] wire [2:0] _GEN_6 = 3'h6 == _T_354 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
wire [2:0] _GEN_7 = 3'h7 == _T_354 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58] wire [2:0] _GEN_7 = 3'h7 == _T_354 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
wire [24:0] _T_369 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_359}; // @[Cat.scala 29:58] wire [24:0] _T_369 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_359}; // @[Cat.scala 29:58]
wire [30:0] _GEN_173 = {{6'd0}, _T_369}; // @[el2_ifu_compress.scala 101:43] wire [30:0] _GEN_173 = {{6'd0}, _T_369}; // @[el2_ifu_compress.scala 100:43]
wire [30:0] _T_370 = _GEN_173 | _T_357; // @[el2_ifu_compress.scala 101:43] wire [30:0] _T_370 = _GEN_173 | _T_357; // @[el2_ifu_compress.scala 100:43]
wire [31:0] _T_371_0 = {{6'd0}, _T_325}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19] wire [31:0] _T_371_0 = {{6'd0}, _T_325}; // @[el2_ifu_compress.scala 102:19 el2_ifu_compress.scala 102:19]
wire [31:0] _T_371_1 = {{1'd0}, _T_337}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19] wire [31:0] _T_371_1 = {{1'd0}, _T_337}; // @[el2_ifu_compress.scala 102:19 el2_ifu_compress.scala 102:19]
wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_371_1 : _T_371_0; // @[el2_ifu_compress.scala 18:14] wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_371_1 : _T_371_0; // @[el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_350 : _GEN_9; // @[el2_ifu_compress.scala 18:14] wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_350 : _GEN_9; // @[el2_ifu_compress.scala 17:14]
wire [31:0] _T_371_3 = {{1'd0}, _T_370}; // @[el2_ifu_compress.scala 103:19 el2_ifu_compress.scala 103:19] wire [31:0] _T_371_3 = {{1'd0}, _T_370}; // @[el2_ifu_compress.scala 102:19 el2_ifu_compress.scala 102:19]
wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_371_3 : _GEN_10; // @[el2_ifu_compress.scala 18:14] wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_371_3 : _GEN_10; // @[el2_ifu_compress.scala 17:14]
wire [9:0] _T_383 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12] wire [9:0] _T_383 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
wire [20:0] _T_398 = {_T_383,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58] wire [20:0] _T_398 = {_T_383,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_461 = {_T_398[20],_T_398[10:1],_T_398[11],_T_398[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58] wire [31:0] _T_461 = {_T_398[20],_T_398[10:1],_T_398[11],_T_398[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
@ -76,7 +76,7 @@ module el2_ifu_compress(
wire [12:0] _T_479 = {_T_470,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_479 = {_T_470,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_528 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58] wire [31:0] _T_528 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58]
wire [31:0] _T_595 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58] wire [31:0] _T_595 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58]
wire [6:0] _T_602 = _T_221 ? 7'h3 : 7'h1f; // @[el2_ifu_compress.scala 109:23] wire [6:0] _T_602 = _T_221 ? 7'h3 : 7'h1f; // @[el2_ifu_compress.scala 108:23]
wire [25:0] _T_611 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58] wire [25:0] _T_611 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire [28:0] _T_627 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58] wire [28:0] _T_627 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
wire [27:0] _T_642 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_602}; // @[Cat.scala 29:58] wire [27:0] _T_642 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_602}; // @[Cat.scala 29:58]
@ -85,197 +85,197 @@ module el2_ifu_compress(
wire [24:0] _T_678 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58] wire [24:0] _T_678 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
wire [24:0] _T_689 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58] wire [24:0] _T_689 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
wire [24:0] _T_691 = {_T_689[24:7],7'h1f}; // @[Cat.scala 29:58] wire [24:0] _T_691 = {_T_689[24:7],7'h1f}; // @[Cat.scala 29:58]
wire [24:0] _T_694 = _T_221 ? _T_689 : _T_691; // @[el2_ifu_compress.scala 130:33] wire [24:0] _T_694 = _T_221 ? _T_689 : _T_691; // @[el2_ifu_compress.scala 129:33]
wire _T_700 = |io_in[6:2]; // @[el2_ifu_compress.scala 131:27] wire _T_700 = |io_in[6:2]; // @[el2_ifu_compress.scala 130:27]
wire [31:0] _T_671_bits = {{7'd0}, _T_667}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_671_bits = {{7'd0}, _T_667}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _T_698_bits = {{7'd0}, _T_694}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_698_bits = {{7'd0}, _T_694}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _T_701_bits = _T_700 ? _T_671_bits : _T_698_bits; // @[el2_ifu_compress.scala 131:22] wire [31:0] _T_701_bits = _T_700 ? _T_671_bits : _T_698_bits; // @[el2_ifu_compress.scala 130:22]
wire [4:0] _T_701_rd = _T_700 ? io_in[11:7] : 5'h0; // @[el2_ifu_compress.scala 131:22] wire [4:0] _T_701_rd = _T_700 ? io_in[11:7] : 5'h0; // @[el2_ifu_compress.scala 130:22]
wire [4:0] _T_701_rs1 = _T_700 ? 5'h0 : io_in[11:7]; // @[el2_ifu_compress.scala 131:22] wire [4:0] _T_701_rs1 = _T_700 ? 5'h0 : io_in[11:7]; // @[el2_ifu_compress.scala 130:22]
wire [4:0] _T_701_rs2 = _T_700 ? io_in[6:2] : io_in[6:2]; // @[el2_ifu_compress.scala 131:22] wire [4:0] _T_701_rs2 = _T_700 ? io_in[6:2] : io_in[6:2]; // @[el2_ifu_compress.scala 130:22]
wire [4:0] _T_701_rs3 = _T_700 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 131:22] wire [4:0] _T_701_rs3 = _T_700 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 130:22]
wire [24:0] _T_707 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58] wire [24:0] _T_707 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
wire [24:0] _T_709 = {_T_689[24:7],7'h73}; // @[Cat.scala 29:58] wire [24:0] _T_709 = {_T_689[24:7],7'h73}; // @[Cat.scala 29:58]
wire [24:0] _T_710 = _T_709 | 25'h100000; // @[el2_ifu_compress.scala 133:46] wire [24:0] _T_710 = _T_709 | 25'h100000; // @[el2_ifu_compress.scala 132:46]
wire [24:0] _T_713 = _T_221 ? _T_707 : _T_710; // @[el2_ifu_compress.scala 134:33] wire [24:0] _T_713 = _T_221 ? _T_707 : _T_710; // @[el2_ifu_compress.scala 133:33]
wire [31:0] _T_683_bits = {{7'd0}, _T_678}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_683_bits = {{7'd0}, _T_678}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _T_717_bits = {{7'd0}, _T_713}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_717_bits = {{7'd0}, _T_713}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _T_720_bits = _T_700 ? _T_683_bits : _T_717_bits; // @[el2_ifu_compress.scala 135:25] wire [31:0] _T_720_bits = _T_700 ? _T_683_bits : _T_717_bits; // @[el2_ifu_compress.scala 134:25]
wire [4:0] _T_720_rd = _T_700 ? io_in[11:7] : 5'h1; // @[el2_ifu_compress.scala 135:25] wire [4:0] _T_720_rd = _T_700 ? io_in[11:7] : 5'h1; // @[el2_ifu_compress.scala 134:25]
wire [4:0] _T_720_rs1 = _T_700 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 135:25] wire [4:0] _T_720_rs1 = _T_700 ? io_in[11:7] : io_in[11:7]; // @[el2_ifu_compress.scala 134:25]
wire [31:0] _T_722_bits = io_in[12] ? _T_720_bits : _T_701_bits; // @[el2_ifu_compress.scala 136:10] wire [31:0] _T_722_bits = io_in[12] ? _T_720_bits : _T_701_bits; // @[el2_ifu_compress.scala 135:10]
wire [4:0] _T_722_rd = io_in[12] ? _T_720_rd : _T_701_rd; // @[el2_ifu_compress.scala 136:10] wire [4:0] _T_722_rd = io_in[12] ? _T_720_rd : _T_701_rd; // @[el2_ifu_compress.scala 135:10]
wire [4:0] _T_722_rs1 = io_in[12] ? _T_720_rs1 : _T_701_rs1; // @[el2_ifu_compress.scala 136:10] wire [4:0] _T_722_rs1 = io_in[12] ? _T_720_rs1 : _T_701_rs1; // @[el2_ifu_compress.scala 135:10]
wire [4:0] _T_722_rs2 = io_in[12] ? _T_701_rs2 : _T_701_rs2; // @[el2_ifu_compress.scala 136:10] wire [4:0] _T_722_rs2 = io_in[12] ? _T_701_rs2 : _T_701_rs2; // @[el2_ifu_compress.scala 135:10]
wire [4:0] _T_722_rs3 = io_in[12] ? _T_701_rs3 : _T_701_rs3; // @[el2_ifu_compress.scala 136:10] wire [4:0] _T_722_rs3 = io_in[12] ? _T_701_rs3 : _T_701_rs3; // @[el2_ifu_compress.scala 135:10]
wire [8:0] _T_726 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58] wire [8:0] _T_726 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
wire [28:0] _T_738 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h27}; // @[Cat.scala 29:58] wire [28:0] _T_738 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h27}; // @[Cat.scala 29:58]
wire [7:0] _T_746 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58] wire [7:0] _T_746 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58]
wire [27:0] _T_758 = {_T_746[7:5],io_in[6:2],5'h2,3'h2,_T_746[4:0],7'h23}; // @[Cat.scala 29:58] wire [27:0] _T_758 = {_T_746[7:5],io_in[6:2],5'h2,3'h2,_T_746[4:0],7'h23}; // @[Cat.scala 29:58]
wire [28:0] _T_778 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h23}; // @[Cat.scala 29:58] wire [28:0] _T_778 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h23}; // @[Cat.scala 29:58]
wire [4:0] _T_826 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58] wire [4:0] _T_826 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58]
wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_17 = 5'h1 == _T_826 ? _T_44_bits : _T_24_bits; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_17 = 5'h1 == _T_826 ? _T_44_bits : _T_24_bits; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_18 = 5'h1 == _T_826 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_18 = 5'h1 == _T_826 ? _T_14 : _T_14; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_19 = 5'h1 == _T_826 ? _T_30 : 5'h2; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_19 = 5'h1 == _T_826 ? _T_30 : 5'h2; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_21 = 5'h1 == _T_826 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_21 = 5'h1 == _T_826 ? io_in[31:27] : io_in[31:27]; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_22 = 5'h2 == _T_826 ? _T_66_bits : _GEN_17; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_22 = 5'h2 == _T_826 ? _T_66_bits : _GEN_17; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_23 = 5'h2 == _T_826 ? _T_14 : _GEN_18; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_23 = 5'h2 == _T_826 ? _T_14 : _GEN_18; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_24 = 5'h2 == _T_826 ? _T_30 : _GEN_19; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_24 = 5'h2 == _T_826 ? _T_30 : _GEN_19; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_26 = 5'h2 == _T_826 ? io_in[31:27] : _GEN_21; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_26 = 5'h2 == _T_826 ? io_in[31:27] : _GEN_21; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_86_bits = {{4'd0}, _T_78}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_86_bits = {{4'd0}, _T_78}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_27 = 5'h3 == _T_826 ? _T_86_bits : _GEN_22; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_27 = 5'h3 == _T_826 ? _T_86_bits : _GEN_22; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_28 = 5'h3 == _T_826 ? _T_14 : _GEN_23; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_28 = 5'h3 == _T_826 ? _T_14 : _GEN_23; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_29 = 5'h3 == _T_826 ? _T_30 : _GEN_24; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_29 = 5'h3 == _T_826 ? _T_30 : _GEN_24; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_31 = 5'h3 == _T_826 ? io_in[31:27] : _GEN_26; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_31 = 5'h3 == _T_826 ? io_in[31:27] : _GEN_26; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_117_bits = {{5'd0}, _T_109}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_117_bits = {{5'd0}, _T_109}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_32 = 5'h4 == _T_826 ? _T_117_bits : _GEN_27; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_32 = 5'h4 == _T_826 ? _T_117_bits : _GEN_27; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_33 = 5'h4 == _T_826 ? _T_14 : _GEN_28; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_33 = 5'h4 == _T_826 ? _T_14 : _GEN_28; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_34 = 5'h4 == _T_826 ? _T_30 : _GEN_29; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_34 = 5'h4 == _T_826 ? _T_30 : _GEN_29; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_36 = 5'h4 == _T_826 ? io_in[31:27] : _GEN_31; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_36 = 5'h4 == _T_826 ? io_in[31:27] : _GEN_31; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_144_bits = {{4'd0}, _T_136}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_144_bits = {{4'd0}, _T_136}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_37 = 5'h5 == _T_826 ? _T_144_bits : _GEN_32; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_37 = 5'h5 == _T_826 ? _T_144_bits : _GEN_32; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_38 = 5'h5 == _T_826 ? _T_14 : _GEN_33; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_38 = 5'h5 == _T_826 ? _T_14 : _GEN_33; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_39 = 5'h5 == _T_826 ? _T_30 : _GEN_34; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_39 = 5'h5 == _T_826 ? _T_30 : _GEN_34; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_41 = 5'h5 == _T_826 ? io_in[31:27] : _GEN_36; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_41 = 5'h5 == _T_826 ? io_in[31:27] : _GEN_36; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_175_bits = {{5'd0}, _T_167}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_175_bits = {{5'd0}, _T_167}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_42 = 5'h6 == _T_826 ? _T_175_bits : _GEN_37; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_42 = 5'h6 == _T_826 ? _T_175_bits : _GEN_37; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_43 = 5'h6 == _T_826 ? _T_14 : _GEN_38; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_43 = 5'h6 == _T_826 ? _T_14 : _GEN_38; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_44 = 5'h6 == _T_826 ? _T_30 : _GEN_39; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_44 = 5'h6 == _T_826 ? _T_30 : _GEN_39; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_46 = 5'h6 == _T_826 ? io_in[31:27] : _GEN_41; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_46 = 5'h6 == _T_826 ? io_in[31:27] : _GEN_41; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_202_bits = {{4'd0}, _T_194}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_202_bits = {{4'd0}, _T_194}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_47 = 5'h7 == _T_826 ? _T_202_bits : _GEN_42; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_47 = 5'h7 == _T_826 ? _T_202_bits : _GEN_42; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_48 = 5'h7 == _T_826 ? _T_14 : _GEN_43; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_48 = 5'h7 == _T_826 ? _T_14 : _GEN_43; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_49 = 5'h7 == _T_826 ? _T_30 : _GEN_44; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_49 = 5'h7 == _T_826 ? _T_30 : _GEN_44; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_51 = 5'h7 == _T_826 ? io_in[31:27] : _GEN_46; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_51 = 5'h7 == _T_826 ? io_in[31:27] : _GEN_46; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_52 = 5'h8 == _T_826 ? _T_213 : _GEN_47; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_52 = 5'h8 == _T_826 ? _T_213 : _GEN_47; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_53 = 5'h8 == _T_826 ? io_in[11:7] : _GEN_48; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_53 = 5'h8 == _T_826 ? io_in[11:7] : _GEN_48; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_54 = 5'h8 == _T_826 ? io_in[11:7] : _GEN_49; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_54 = 5'h8 == _T_826 ? io_in[11:7] : _GEN_49; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_55 = 5'h8 == _T_826 ? _T_14 : _GEN_48; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_55 = 5'h8 == _T_826 ? _T_14 : _GEN_48; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_56 = 5'h8 == _T_826 ? io_in[31:27] : _GEN_51; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_56 = 5'h8 == _T_826 ? io_in[31:27] : _GEN_51; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_57 = 5'h9 == _T_826 ? _T_233 : _GEN_52; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_57 = 5'h9 == _T_826 ? _T_233 : _GEN_52; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_58 = 5'h9 == _T_826 ? io_in[11:7] : _GEN_53; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_58 = 5'h9 == _T_826 ? io_in[11:7] : _GEN_53; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_59 = 5'h9 == _T_826 ? io_in[11:7] : _GEN_54; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_59 = 5'h9 == _T_826 ? io_in[11:7] : _GEN_54; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_60 = 5'h9 == _T_826 ? _T_14 : _GEN_55; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_60 = 5'h9 == _T_826 ? _T_14 : _GEN_55; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_61 = 5'h9 == _T_826 ? io_in[31:27] : _GEN_56; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_61 = 5'h9 == _T_826 ? io_in[31:27] : _GEN_56; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_62 = 5'ha == _T_826 ? _T_249 : _GEN_57; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_62 = 5'ha == _T_826 ? _T_249 : _GEN_57; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_63 = 5'ha == _T_826 ? io_in[11:7] : _GEN_58; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_63 = 5'ha == _T_826 ? io_in[11:7] : _GEN_58; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_64 = 5'ha == _T_826 ? 5'h0 : _GEN_59; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_64 = 5'ha == _T_826 ? 5'h0 : _GEN_59; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_65 = 5'ha == _T_826 ? _T_14 : _GEN_60; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_65 = 5'ha == _T_826 ? _T_14 : _GEN_60; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_66 = 5'ha == _T_826 ? io_in[31:27] : _GEN_61; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_66 = 5'ha == _T_826 ? io_in[31:27] : _GEN_61; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_67 = 5'hb == _T_826 ? _T_314_bits : _GEN_62; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_67 = 5'hb == _T_826 ? _T_314_bits : _GEN_62; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_68 = 5'hb == _T_826 ? _T_314_rd : _GEN_63; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_68 = 5'hb == _T_826 ? _T_314_rd : _GEN_63; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_69 = 5'hb == _T_826 ? _T_314_rd : _GEN_64; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_69 = 5'hb == _T_826 ? _T_314_rd : _GEN_64; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_70 = 5'hb == _T_826 ? _T_314_rs2 : _GEN_65; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_70 = 5'hb == _T_826 ? _T_314_rs2 : _GEN_65; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_71 = 5'hb == _T_826 ? _T_314_rs3 : _GEN_66; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_71 = 5'hb == _T_826 ? _T_314_rs3 : _GEN_66; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_72 = 5'hc == _T_826 ? _GEN_11 : _GEN_67; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_72 = 5'hc == _T_826 ? _GEN_11 : _GEN_67; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_73 = 5'hc == _T_826 ? _T_30 : _GEN_68; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_73 = 5'hc == _T_826 ? _T_30 : _GEN_68; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_74 = 5'hc == _T_826 ? _T_30 : _GEN_69; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_74 = 5'hc == _T_826 ? _T_30 : _GEN_69; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_75 = 5'hc == _T_826 ? _T_14 : _GEN_70; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_75 = 5'hc == _T_826 ? _T_14 : _GEN_70; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_76 = 5'hc == _T_826 ? io_in[31:27] : _GEN_71; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_76 = 5'hc == _T_826 ? io_in[31:27] : _GEN_71; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_77 = 5'hd == _T_826 ? _T_461 : _GEN_72; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_77 = 5'hd == _T_826 ? _T_461 : _GEN_72; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_78 = 5'hd == _T_826 ? 5'h0 : _GEN_73; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_78 = 5'hd == _T_826 ? 5'h0 : _GEN_73; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_79 = 5'hd == _T_826 ? _T_30 : _GEN_74; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_79 = 5'hd == _T_826 ? _T_30 : _GEN_74; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_80 = 5'hd == _T_826 ? _T_14 : _GEN_75; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_80 = 5'hd == _T_826 ? _T_14 : _GEN_75; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_81 = 5'hd == _T_826 ? io_in[31:27] : _GEN_76; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_81 = 5'hd == _T_826 ? io_in[31:27] : _GEN_76; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_82 = 5'he == _T_826 ? _T_528 : _GEN_77; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_82 = 5'he == _T_826 ? _T_528 : _GEN_77; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_83 = 5'he == _T_826 ? _T_30 : _GEN_78; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_83 = 5'he == _T_826 ? _T_30 : _GEN_78; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_84 = 5'he == _T_826 ? _T_30 : _GEN_79; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_84 = 5'he == _T_826 ? _T_30 : _GEN_79; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_85 = 5'he == _T_826 ? 5'h0 : _GEN_80; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_85 = 5'he == _T_826 ? 5'h0 : _GEN_80; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_86 = 5'he == _T_826 ? io_in[31:27] : _GEN_81; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_86 = 5'he == _T_826 ? io_in[31:27] : _GEN_81; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_87 = 5'hf == _T_826 ? _T_595 : _GEN_82; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_87 = 5'hf == _T_826 ? _T_595 : _GEN_82; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_88 = 5'hf == _T_826 ? 5'h0 : _GEN_83; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_88 = 5'hf == _T_826 ? 5'h0 : _GEN_83; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_89 = 5'hf == _T_826 ? _T_30 : _GEN_84; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_89 = 5'hf == _T_826 ? _T_30 : _GEN_84; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_90 = 5'hf == _T_826 ? 5'h0 : _GEN_85; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_90 = 5'hf == _T_826 ? 5'h0 : _GEN_85; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_91 = 5'hf == _T_826 ? io_in[31:27] : _GEN_86; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_91 = 5'hf == _T_826 ? io_in[31:27] : _GEN_86; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_616_bits = {{6'd0}, _T_611}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_616_bits = {{6'd0}, _T_611}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_92 = 5'h10 == _T_826 ? _T_616_bits : _GEN_87; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_92 = 5'h10 == _T_826 ? _T_616_bits : _GEN_87; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_93 = 5'h10 == _T_826 ? io_in[11:7] : _GEN_88; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_93 = 5'h10 == _T_826 ? io_in[11:7] : _GEN_88; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_94 = 5'h10 == _T_826 ? io_in[11:7] : _GEN_89; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_94 = 5'h10 == _T_826 ? io_in[11:7] : _GEN_89; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_95 = 5'h10 == _T_826 ? io_in[6:2] : _GEN_90; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_95 = 5'h10 == _T_826 ? io_in[6:2] : _GEN_90; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_96 = 5'h10 == _T_826 ? io_in[31:27] : _GEN_91; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_96 = 5'h10 == _T_826 ? io_in[31:27] : _GEN_91; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_631_bits = {{3'd0}, _T_627}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_631_bits = {{3'd0}, _T_627}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_97 = 5'h11 == _T_826 ? _T_631_bits : _GEN_92; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_97 = 5'h11 == _T_826 ? _T_631_bits : _GEN_92; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_98 = 5'h11 == _T_826 ? io_in[11:7] : _GEN_93; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_98 = 5'h11 == _T_826 ? io_in[11:7] : _GEN_93; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_99 = 5'h11 == _T_826 ? 5'h2 : _GEN_94; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_99 = 5'h11 == _T_826 ? 5'h2 : _GEN_94; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_100 = 5'h11 == _T_826 ? io_in[6:2] : _GEN_95; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_100 = 5'h11 == _T_826 ? io_in[6:2] : _GEN_95; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_101 = 5'h11 == _T_826 ? io_in[31:27] : _GEN_96; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_101 = 5'h11 == _T_826 ? io_in[31:27] : _GEN_96; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_646_bits = {{4'd0}, _T_642}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_646_bits = {{4'd0}, _T_642}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_102 = 5'h12 == _T_826 ? _T_646_bits : _GEN_97; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_102 = 5'h12 == _T_826 ? _T_646_bits : _GEN_97; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_103 = 5'h12 == _T_826 ? io_in[11:7] : _GEN_98; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_103 = 5'h12 == _T_826 ? io_in[11:7] : _GEN_98; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_104 = 5'h12 == _T_826 ? 5'h2 : _GEN_99; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_104 = 5'h12 == _T_826 ? 5'h2 : _GEN_99; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_105 = 5'h12 == _T_826 ? io_in[6:2] : _GEN_100; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_105 = 5'h12 == _T_826 ? io_in[6:2] : _GEN_100; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_106 = 5'h12 == _T_826 ? io_in[31:27] : _GEN_101; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_106 = 5'h12 == _T_826 ? io_in[31:27] : _GEN_101; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_661_bits = {{3'd0}, _T_657}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_661_bits = {{3'd0}, _T_657}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_107 = 5'h13 == _T_826 ? _T_661_bits : _GEN_102; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_107 = 5'h13 == _T_826 ? _T_661_bits : _GEN_102; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_108 = 5'h13 == _T_826 ? io_in[11:7] : _GEN_103; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_108 = 5'h13 == _T_826 ? io_in[11:7] : _GEN_103; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_109 = 5'h13 == _T_826 ? 5'h2 : _GEN_104; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_109 = 5'h13 == _T_826 ? 5'h2 : _GEN_104; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_110 = 5'h13 == _T_826 ? io_in[6:2] : _GEN_105; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_110 = 5'h13 == _T_826 ? io_in[6:2] : _GEN_105; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_111 = 5'h13 == _T_826 ? io_in[31:27] : _GEN_106; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_111 = 5'h13 == _T_826 ? io_in[31:27] : _GEN_106; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_112 = 5'h14 == _T_826 ? _T_722_bits : _GEN_107; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_112 = 5'h14 == _T_826 ? _T_722_bits : _GEN_107; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_113 = 5'h14 == _T_826 ? _T_722_rd : _GEN_108; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_113 = 5'h14 == _T_826 ? _T_722_rd : _GEN_108; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_114 = 5'h14 == _T_826 ? _T_722_rs1 : _GEN_109; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_114 = 5'h14 == _T_826 ? _T_722_rs1 : _GEN_109; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_115 = 5'h14 == _T_826 ? _T_722_rs2 : _GEN_110; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_115 = 5'h14 == _T_826 ? _T_722_rs2 : _GEN_110; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_116 = 5'h14 == _T_826 ? _T_722_rs3 : _GEN_111; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_116 = 5'h14 == _T_826 ? _T_722_rs3 : _GEN_111; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_742_bits = {{3'd0}, _T_738}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_742_bits = {{3'd0}, _T_738}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_117 = 5'h15 == _T_826 ? _T_742_bits : _GEN_112; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_117 = 5'h15 == _T_826 ? _T_742_bits : _GEN_112; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_118 = 5'h15 == _T_826 ? io_in[11:7] : _GEN_113; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_118 = 5'h15 == _T_826 ? io_in[11:7] : _GEN_113; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_119 = 5'h15 == _T_826 ? 5'h2 : _GEN_114; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_119 = 5'h15 == _T_826 ? 5'h2 : _GEN_114; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_120 = 5'h15 == _T_826 ? io_in[6:2] : _GEN_115; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_120 = 5'h15 == _T_826 ? io_in[6:2] : _GEN_115; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_121 = 5'h15 == _T_826 ? io_in[31:27] : _GEN_116; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_121 = 5'h15 == _T_826 ? io_in[31:27] : _GEN_116; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_762_bits = {{4'd0}, _T_758}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_762_bits = {{4'd0}, _T_758}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_122 = 5'h16 == _T_826 ? _T_762_bits : _GEN_117; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_122 = 5'h16 == _T_826 ? _T_762_bits : _GEN_117; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_123 = 5'h16 == _T_826 ? io_in[11:7] : _GEN_118; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_123 = 5'h16 == _T_826 ? io_in[11:7] : _GEN_118; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_124 = 5'h16 == _T_826 ? 5'h2 : _GEN_119; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_124 = 5'h16 == _T_826 ? 5'h2 : _GEN_119; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_125 = 5'h16 == _T_826 ? io_in[6:2] : _GEN_120; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_125 = 5'h16 == _T_826 ? io_in[6:2] : _GEN_120; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_126 = 5'h16 == _T_826 ? io_in[31:27] : _GEN_121; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_126 = 5'h16 == _T_826 ? io_in[31:27] : _GEN_121; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _T_782_bits = {{3'd0}, _T_778}; // @[el2_ifu_compress.scala 17:19 el2_ifu_compress.scala 18:14] wire [31:0] _T_782_bits = {{3'd0}, _T_778}; // @[el2_ifu_compress.scala 16:19 el2_ifu_compress.scala 17:14]
wire [31:0] _GEN_127 = 5'h17 == _T_826 ? _T_782_bits : _GEN_122; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_127 = 5'h17 == _T_826 ? _T_782_bits : _GEN_122; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_128 = 5'h17 == _T_826 ? io_in[11:7] : _GEN_123; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_128 = 5'h17 == _T_826 ? io_in[11:7] : _GEN_123; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_129 = 5'h17 == _T_826 ? 5'h2 : _GEN_124; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_129 = 5'h17 == _T_826 ? 5'h2 : _GEN_124; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_130 = 5'h17 == _T_826 ? io_in[6:2] : _GEN_125; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_130 = 5'h17 == _T_826 ? io_in[6:2] : _GEN_125; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_131 = 5'h17 == _T_826 ? io_in[31:27] : _GEN_126; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_131 = 5'h17 == _T_826 ? io_in[31:27] : _GEN_126; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_132 = 5'h18 == _T_826 ? io_in : _GEN_127; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_132 = 5'h18 == _T_826 ? io_in : _GEN_127; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_133 = 5'h18 == _T_826 ? io_in[11:7] : _GEN_128; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_133 = 5'h18 == _T_826 ? io_in[11:7] : _GEN_128; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_134 = 5'h18 == _T_826 ? io_in[19:15] : _GEN_129; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_134 = 5'h18 == _T_826 ? io_in[19:15] : _GEN_129; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_135 = 5'h18 == _T_826 ? io_in[24:20] : _GEN_130; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_135 = 5'h18 == _T_826 ? io_in[24:20] : _GEN_130; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_136 = 5'h18 == _T_826 ? io_in[31:27] : _GEN_131; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_136 = 5'h18 == _T_826 ? io_in[31:27] : _GEN_131; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_137 = 5'h19 == _T_826 ? io_in : _GEN_132; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_137 = 5'h19 == _T_826 ? io_in : _GEN_132; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_138 = 5'h19 == _T_826 ? io_in[11:7] : _GEN_133; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_138 = 5'h19 == _T_826 ? io_in[11:7] : _GEN_133; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_139 = 5'h19 == _T_826 ? io_in[19:15] : _GEN_134; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_139 = 5'h19 == _T_826 ? io_in[19:15] : _GEN_134; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_140 = 5'h19 == _T_826 ? io_in[24:20] : _GEN_135; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_140 = 5'h19 == _T_826 ? io_in[24:20] : _GEN_135; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_141 = 5'h19 == _T_826 ? io_in[31:27] : _GEN_136; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_141 = 5'h19 == _T_826 ? io_in[31:27] : _GEN_136; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_142 = 5'h1a == _T_826 ? io_in : _GEN_137; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_142 = 5'h1a == _T_826 ? io_in : _GEN_137; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_143 = 5'h1a == _T_826 ? io_in[11:7] : _GEN_138; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_143 = 5'h1a == _T_826 ? io_in[11:7] : _GEN_138; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_144 = 5'h1a == _T_826 ? io_in[19:15] : _GEN_139; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_144 = 5'h1a == _T_826 ? io_in[19:15] : _GEN_139; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_145 = 5'h1a == _T_826 ? io_in[24:20] : _GEN_140; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_145 = 5'h1a == _T_826 ? io_in[24:20] : _GEN_140; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_146 = 5'h1a == _T_826 ? io_in[31:27] : _GEN_141; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_146 = 5'h1a == _T_826 ? io_in[31:27] : _GEN_141; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_147 = 5'h1b == _T_826 ? io_in : _GEN_142; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_147 = 5'h1b == _T_826 ? io_in : _GEN_142; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_148 = 5'h1b == _T_826 ? io_in[11:7] : _GEN_143; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_148 = 5'h1b == _T_826 ? io_in[11:7] : _GEN_143; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_149 = 5'h1b == _T_826 ? io_in[19:15] : _GEN_144; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_149 = 5'h1b == _T_826 ? io_in[19:15] : _GEN_144; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_150 = 5'h1b == _T_826 ? io_in[24:20] : _GEN_145; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_150 = 5'h1b == _T_826 ? io_in[24:20] : _GEN_145; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_151 = 5'h1b == _T_826 ? io_in[31:27] : _GEN_146; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_151 = 5'h1b == _T_826 ? io_in[31:27] : _GEN_146; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_152 = 5'h1c == _T_826 ? io_in : _GEN_147; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_152 = 5'h1c == _T_826 ? io_in : _GEN_147; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_153 = 5'h1c == _T_826 ? io_in[11:7] : _GEN_148; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_153 = 5'h1c == _T_826 ? io_in[11:7] : _GEN_148; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_154 = 5'h1c == _T_826 ? io_in[19:15] : _GEN_149; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_154 = 5'h1c == _T_826 ? io_in[19:15] : _GEN_149; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_155 = 5'h1c == _T_826 ? io_in[24:20] : _GEN_150; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_155 = 5'h1c == _T_826 ? io_in[24:20] : _GEN_150; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_156 = 5'h1c == _T_826 ? io_in[31:27] : _GEN_151; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_156 = 5'h1c == _T_826 ? io_in[31:27] : _GEN_151; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_157 = 5'h1d == _T_826 ? io_in : _GEN_152; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_157 = 5'h1d == _T_826 ? io_in : _GEN_152; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_158 = 5'h1d == _T_826 ? io_in[11:7] : _GEN_153; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_158 = 5'h1d == _T_826 ? io_in[11:7] : _GEN_153; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_159 = 5'h1d == _T_826 ? io_in[19:15] : _GEN_154; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_159 = 5'h1d == _T_826 ? io_in[19:15] : _GEN_154; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_160 = 5'h1d == _T_826 ? io_in[24:20] : _GEN_155; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_160 = 5'h1d == _T_826 ? io_in[24:20] : _GEN_155; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_161 = 5'h1d == _T_826 ? io_in[31:27] : _GEN_156; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_161 = 5'h1d == _T_826 ? io_in[31:27] : _GEN_156; // @[el2_ifu_compress.scala 194:12]
wire [31:0] _GEN_162 = 5'h1e == _T_826 ? io_in : _GEN_157; // @[el2_ifu_compress.scala 195:12] wire [31:0] _GEN_162 = 5'h1e == _T_826 ? io_in : _GEN_157; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_163 = 5'h1e == _T_826 ? io_in[11:7] : _GEN_158; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_163 = 5'h1e == _T_826 ? io_in[11:7] : _GEN_158; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_164 = 5'h1e == _T_826 ? io_in[19:15] : _GEN_159; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_164 = 5'h1e == _T_826 ? io_in[19:15] : _GEN_159; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_165 = 5'h1e == _T_826 ? io_in[24:20] : _GEN_160; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_165 = 5'h1e == _T_826 ? io_in[24:20] : _GEN_160; // @[el2_ifu_compress.scala 194:12]
wire [4:0] _GEN_166 = 5'h1e == _T_826 ? io_in[31:27] : _GEN_161; // @[el2_ifu_compress.scala 195:12] wire [4:0] _GEN_166 = 5'h1e == _T_826 ? io_in[31:27] : _GEN_161; // @[el2_ifu_compress.scala 194:12]
assign io_out_bits = 5'h1f == _T_826 ? io_in : _GEN_162; // @[el2_ifu_compress.scala 195:12] assign io_out_bits = 5'h1f == _T_826 ? io_in : _GEN_162; // @[el2_ifu_compress.scala 194:12]
assign io_out_rd = 5'h1f == _T_826 ? io_in[11:7] : _GEN_163; // @[el2_ifu_compress.scala 195:12] assign io_out_rd = 5'h1f == _T_826 ? io_in[11:7] : _GEN_163; // @[el2_ifu_compress.scala 194:12]
assign io_out_rs1 = 5'h1f == _T_826 ? io_in[19:15] : _GEN_164; // @[el2_ifu_compress.scala 195:12] assign io_out_rs1 = 5'h1f == _T_826 ? io_in[19:15] : _GEN_164; // @[el2_ifu_compress.scala 194:12]
assign io_out_rs2 = 5'h1f == _T_826 ? io_in[24:20] : _GEN_165; // @[el2_ifu_compress.scala 195:12] assign io_out_rs2 = 5'h1f == _T_826 ? io_in[24:20] : _GEN_165; // @[el2_ifu_compress.scala 194:12]
assign io_out_rs3 = 5'h1f == _T_826 ? io_in[31:27] : _GEN_166; // @[el2_ifu_compress.scala 195:12] assign io_out_rs3 = 5'h1f == _T_826 ? io_in[31:27] : _GEN_166; // @[el2_ifu_compress.scala 194:12]
assign io_rvc = io_in[1:0] != 2'h3; // @[el2_ifu_compress.scala 193:12] assign io_rvc = io_in[1:0] != 2'h3; // @[el2_ifu_compress.scala 192:12]
endmodule endmodule

14
el2_ifu_ifc_ctrl.anno.json
View File

@ -1,4 +1,18 @@
[ [
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_test_out",
"sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_pmu_fetch_stall", "sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_pmu_fetch_stall",

372
el2_ifu_ifc_ctrl.fir
View File

@ -3,8 +3,10 @@ circuit el2_ifu_ifc_ctrl :
module el2_ifu_ifc_ctrl : module el2_ifu_ifc_ctrl :
input clock : Clock input clock : Clock
input reset : UInt<1> input reset : UInt<1>
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<31>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>} output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, test_out : UInt}
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 40:30]
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 41:24]
wire fetch_addr_bf : UInt<32> wire fetch_addr_bf : UInt<32>
fetch_addr_bf <= UInt<1>("h00") fetch_addr_bf <= UInt<1>("h00")
wire fetch_addr_next : UInt<32> wire fetch_addr_next : UInt<32>
@ -33,7 +35,8 @@ circuit el2_ifu_ifc_ctrl :
sel_next_addr_bf <= UInt<1>("h00") sel_next_addr_bf <= UInt<1>("h00")
wire miss_f : UInt<1> wire miss_f : UInt<1>
miss_f <= UInt<1>("h00") miss_f <= UInt<1>("h00")
wire miss_a : UInt<1> @[el2_ifu_ifc_ctrl.scala 53:20] wire miss_a : UInt<1>
miss_a <= UInt<1>("h00")
wire flush_fb : UInt<1> wire flush_fb : UInt<1>
flush_fb <= UInt<1>("h00") flush_fb <= UInt<1>("h00")
wire mb_empty_mod : UInt<1> wire mb_empty_mod : UInt<1>
@ -48,125 +51,114 @@ circuit el2_ifu_ifc_ctrl :
line_wrap <= UInt<1>("h00") line_wrap <= UInt<1>("h00")
wire state : UInt<2> wire state : UInt<2>
state <= UInt<1>("h00") state <= UInt<1>("h00")
io.ifc_fetch_addr_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 64:23] wire dma_iccm_stall_any_f : UInt<1>
io.ifc_fetch_addr_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 65:24] dma_iccm_stall_any_f <= UInt<1>("h00")
io.ifc_fetch_req_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 66:22] node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 69:36]
io.ifu_pmu_fetch_stall <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 67:26] reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 70:34]
io.ifc_fetch_uncacheable_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 68:31] _T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 70:34]
io.ifc_fetch_req_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 69:23] dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctrl.scala 70:24]
io.ifc_fetch_req_bf_raw <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 70:27] reg _T_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 72:20]
io.ifc_iccm_access_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 71:25] _T_1 <= miss_f @[el2_ifu_ifc_ctrl.scala 72:20]
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 72:30] miss_a <= _T_1 @[el2_ifu_ifc_ctrl.scala 72:10]
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 73:24] node _T_2 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 74:23]
reg dma_iccm_stall_any_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 75:37] node _T_3 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 74:46]
dma_iccm_stall_any_f <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 75:37] node _T_4 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 74:68]
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 76:36] node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctrl.scala 74:66]
reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 77:20] node _T_6 = and(_T_2, _T_5) @[el2_ifu_ifc_ctrl.scala 74:43]
_T <= miss_f @[el2_ifu_ifc_ctrl.scala 77:20] sel_last_addr_bf <= _T_6 @[el2_ifu_ifc_ctrl.scala 74:20]
miss_a <= _T @[el2_ifu_ifc_ctrl.scala 77:10] node _T_7 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 75:23]
node _T_1 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 79:23] node _T_8 = and(_T_7, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 75:43]
node _T_2 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 79:46] node _T_9 = and(_T_8, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 75:64]
node _T_3 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 79:68] node _T_10 = and(_T_9, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 75:88]
node _T_4 = or(_T_2, _T_3) @[el2_ifu_ifc_ctrl.scala 79:66] sel_btb_addr_bf <= _T_10 @[el2_ifu_ifc_ctrl.scala 75:20]
node _T_5 = and(_T_1, _T_4) @[el2_ifu_ifc_ctrl.scala 79:43] node _T_11 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 76:23]
sel_last_addr_bf <= _T_5 @[el2_ifu_ifc_ctrl.scala 79:20] node _T_12 = and(_T_11, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 76:43]
node _T_6 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 80:23] node _T_13 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 76:66]
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 80:43] node _T_14 = and(_T_12, _T_13) @[el2_ifu_ifc_ctrl.scala 76:64]
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 80:64] node _T_15 = and(_T_14, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 76:89]
node _T_9 = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 80:88] sel_next_addr_bf <= _T_15 @[el2_ifu_ifc_ctrl.scala 76:20]
sel_btb_addr_bf <= _T_9 @[el2_ifu_ifc_ctrl.scala 80:20] node _T_16 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 79:56]
node _T_10 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 81:23] node _T_17 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 80:46]
node _T_11 = and(_T_10, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 81:43] node _T_18 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 81:45]
node _T_12 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 81:66] node _T_19 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 82:46]
node _T_13 = and(_T_11, _T_12) @[el2_ifu_ifc_ctrl.scala 81:64] node _T_20 = mux(_T_16, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_14 = and(_T_13, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 81:89] node _T_21 = mux(_T_17, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
sel_next_addr_bf <= _T_14 @[el2_ifu_ifc_ctrl.scala 81:20] node _T_22 = mux(_T_18, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_15 = add(io.ifc_fetch_addr_f, UInt<2>("h02")) @[el2_ifu_ifc_ctrl.scala 84:42] node _T_23 = mux(_T_19, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_16 = tail(_T_15, 1) @[el2_ifu_ifc_ctrl.scala 84:42] node _T_24 = or(_T_20, _T_21) @[Mux.scala 27:72]
node _T_17 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 85:25] node _T_25 = or(_T_24, _T_22) @[Mux.scala 27:72]
node _T_18 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 85:53] node _T_26 = or(_T_25, _T_23) @[Mux.scala 27:72]
node _T_19 = mux(_T_17, UInt<1>("h00"), _T_18) @[el2_ifu_ifc_ctrl.scala 85:8] wire _T_27 : UInt<32> @[Mux.scala 27:72]
node _T_20 = or(_T_16, _T_19) @[el2_ifu_ifc_ctrl.scala 84:48] _T_27 <= _T_26 @[Mux.scala 27:72]
fetch_addr_next <= _T_20 @[el2_ifu_ifc_ctrl.scala 84:19] io.ifc_fetch_addr_bf <= _T_27 @[el2_ifu_ifc_ctrl.scala 79:24]
node _T_21 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 89:56] io.test_out <= io.ifc_fetch_addr_bf @[el2_ifu_ifc_ctrl.scala 84:15]
node _T_22 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 90:46] line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 86:13]
node _T_23 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 91:45] node _T_28 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctrl.scala 88:46]
node _T_24 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 92:46] node _T_29 = add(_T_28, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 88:52]
node _T_25 = mux(_T_21, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72] node _T_30 = tail(_T_29, 1) @[el2_ifu_ifc_ctrl.scala 88:52]
node _T_26 = mux(_T_22, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_31 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 89:25]
node _T_27 = mux(_T_23, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_32 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 89:53]
node _T_28 = mux(_T_24, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72] node _T_33 = mux(_T_31, UInt<1>("h00"), _T_32) @[el2_ifu_ifc_ctrl.scala 89:8]
node _T_29 = or(_T_25, _T_26) @[Mux.scala 27:72] node _T_34 = or(_T_30, _T_33) @[el2_ifu_ifc_ctrl.scala 88:58]
node _T_30 = or(_T_29, _T_27) @[Mux.scala 27:72] fetch_addr_next <= _T_34 @[el2_ifu_ifc_ctrl.scala 88:19]
node _T_31 = or(_T_30, _T_28) @[Mux.scala 27:72] node _T_35 = not(idle) @[el2_ifu_ifc_ctrl.scala 93:30]
wire _T_32 : UInt<32> @[Mux.scala 27:72] io.ifc_fetch_req_bf_raw <= _T_35 @[el2_ifu_ifc_ctrl.scala 93:27]
_T_32 <= _T_31 @[Mux.scala 27:72] node _T_36 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 95:91]
io.ifc_fetch_addr_bf <= _T_32 @[el2_ifu_ifc_ctrl.scala 89:24] node _T_37 = not(_T_36) @[el2_ifu_ifc_ctrl.scala 95:70]
node _T_33 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 95:88] node _T_38 = and(fb_full_f_ns, _T_37) @[el2_ifu_ifc_ctrl.scala 95:68]
reg _T_34 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] node _T_39 = not(_T_38) @[el2_ifu_ifc_ctrl.scala 95:53]
when _T_33 : @[Reg.scala 28:19] node _T_40 = and(io.ifc_fetch_req_bf_raw, _T_39) @[el2_ifu_ifc_ctrl.scala 95:51]
_T_34 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23] node _T_41 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 96:5]
skip @[Reg.scala 28:19] node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctrl.scala 95:114]
io.ifc_fetch_addr_f <= _T_34 @[el2_ifu_ifc_ctrl.scala 95:23] node _T_43 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 96:18]
node _T_35 = not(idle) @[el2_ifu_ifc_ctrl.scala 97:30] node _T_44 = and(_T_42, _T_43) @[el2_ifu_ifc_ctrl.scala 96:16]
io.ifc_fetch_req_bf_raw <= _T_35 @[el2_ifu_ifc_ctrl.scala 97:27] node _T_45 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 96:39]
reg _T_36 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 99:32] node _T_46 = and(_T_44, _T_45) @[el2_ifu_ifc_ctrl.scala 96:37]
_T_36 <= io.ifc_fetch_addr_bf @[el2_ifu_ifc_ctrl.scala 99:32] io.ifc_fetch_req_bf <= _T_46 @[el2_ifu_ifc_ctrl.scala 95:23]
io.ifc_fetch_req_f <= _T_36 @[el2_ifu_ifc_ctrl.scala 99:22] node _T_47 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 98:37]
node _T_37 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 101:91] fetch_bf_en <= _T_47 @[el2_ifu_ifc_ctrl.scala 98:15]
node _T_38 = not(_T_37) @[el2_ifu_ifc_ctrl.scala 101:70] node _T_48 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 100:34]
node _T_39 = and(fb_full_f_ns, _T_38) @[el2_ifu_ifc_ctrl.scala 101:68] node _T_49 = and(io.ifc_fetch_req_f, _T_48) @[el2_ifu_ifc_ctrl.scala 100:32]
node _T_40 = not(_T_39) @[el2_ifu_ifc_ctrl.scala 101:53] node _T_50 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 100:49]
node _T_41 = and(io.ifc_fetch_req_bf_raw, _T_40) @[el2_ifu_ifc_ctrl.scala 101:51] node _T_51 = and(_T_49, _T_50) @[el2_ifu_ifc_ctrl.scala 100:47]
node _T_42 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 102:5] miss_f <= _T_51 @[el2_ifu_ifc_ctrl.scala 100:10]
node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctrl.scala 101:114] node _T_52 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 102:39]
node _T_44 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 102:18] node _T_53 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 102:63]
node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctrl.scala 102:16] node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctrl.scala 102:61]
node _T_46 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 102:39] node _T_55 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 102:76]
node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctrl.scala 102:37] node _T_56 = and(_T_54, _T_55) @[el2_ifu_ifc_ctrl.scala 102:74]
io.ifc_fetch_req_bf <= _T_47 @[el2_ifu_ifc_ctrl.scala 101:23] node _T_57 = not(miss_a) @[el2_ifu_ifc_ctrl.scala 102:86]
node _T_48 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 104:34] node _T_58 = and(_T_56, _T_57) @[el2_ifu_ifc_ctrl.scala 102:84]
node _T_49 = and(io.ifc_fetch_req_f, _T_48) @[el2_ifu_ifc_ctrl.scala 104:32] mb_empty_mod <= _T_58 @[el2_ifu_ifc_ctrl.scala 102:16]
node _T_50 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 104:49] node _T_59 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 104:35]
node _T_51 = and(_T_49, _T_50) @[el2_ifu_ifc_ctrl.scala 104:47] goto_idle <= _T_59 @[el2_ifu_ifc_ctrl.scala 104:13]
miss_f <= _T_51 @[el2_ifu_ifc_ctrl.scala 104:10] node _T_60 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 106:38]
node _T_52 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 106:35] node _T_61 = and(io.exu_flush_final, _T_60) @[el2_ifu_ifc_ctrl.scala 106:36]
goto_idle <= _T_52 @[el2_ifu_ifc_ctrl.scala 106:13] node _T_62 = and(_T_61, idle) @[el2_ifu_ifc_ctrl.scala 106:67]
node _T_53 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 108:39] leave_idle <= _T_62 @[el2_ifu_ifc_ctrl.scala 106:14]
node _T_54 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 108:63] node _T_63 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 108:29]
node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctrl.scala 108:61] node _T_64 = not(_T_63) @[el2_ifu_ifc_ctrl.scala 108:23]
node _T_56 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 108:76] node _T_65 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 108:40]
node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctrl.scala 108:74] node _T_66 = and(_T_64, _T_65) @[el2_ifu_ifc_ctrl.scala 108:33]
node _T_58 = not(miss_a) @[el2_ifu_ifc_ctrl.scala 108:86] node _T_67 = and(_T_66, miss_f) @[el2_ifu_ifc_ctrl.scala 108:44]
node _T_59 = and(_T_57, _T_58) @[el2_ifu_ifc_ctrl.scala 108:84] node _T_68 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 108:55]
mb_empty_mod <= _T_59 @[el2_ifu_ifc_ctrl.scala 108:16] node _T_69 = and(_T_67, _T_68) @[el2_ifu_ifc_ctrl.scala 108:53]
node _T_60 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 110:38] node _T_70 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 109:11]
node _T_61 = and(io.exu_flush_final, _T_60) @[el2_ifu_ifc_ctrl.scala 110:36] node _T_71 = not(mb_empty_mod) @[el2_ifu_ifc_ctrl.scala 109:17]
node _T_62 = and(_T_61, idle) @[el2_ifu_ifc_ctrl.scala 110:67] node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctrl.scala 109:15]
leave_idle <= _T_62 @[el2_ifu_ifc_ctrl.scala 110:14] node _T_73 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 109:33]
node _T_63 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 112:29] node _T_74 = and(_T_72, _T_73) @[el2_ifu_ifc_ctrl.scala 109:31]
node _T_64 = not(_T_63) @[el2_ifu_ifc_ctrl.scala 112:23] node next_state_1 = or(_T_69, _T_74) @[el2_ifu_ifc_ctrl.scala 108:67]
node _T_65 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 112:40] node _T_75 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 111:23]
node _T_66 = and(_T_64, _T_65) @[el2_ifu_ifc_ctrl.scala 112:33] node _T_76 = and(_T_75, leave_idle) @[el2_ifu_ifc_ctrl.scala 111:34]
node _T_67 = and(_T_66, miss_f) @[el2_ifu_ifc_ctrl.scala 112:44] node _T_77 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 111:56]
node _T_68 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 112:55] node _T_78 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 111:62]
node _T_69 = and(_T_67, _T_68) @[el2_ifu_ifc_ctrl.scala 112:53] node _T_79 = and(_T_77, _T_78) @[el2_ifu_ifc_ctrl.scala 111:60]
node _T_70 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 113:11] node next_state_0 = or(_T_76, _T_79) @[el2_ifu_ifc_ctrl.scala 111:48]
node _T_71 = not(mb_empty_mod) @[el2_ifu_ifc_ctrl.scala 113:17]
node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctrl.scala 113:15]
node _T_73 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 113:33]
node _T_74 = and(_T_72, _T_73) @[el2_ifu_ifc_ctrl.scala 113:31]
node next_state_1 = or(_T_69, _T_74) @[el2_ifu_ifc_ctrl.scala 112:67]
node _T_75 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 115:23]
node _T_76 = and(_T_75, leave_idle) @[el2_ifu_ifc_ctrl.scala 115:34]
node _T_77 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 115:56]
node _T_78 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 115:62]
node _T_79 = and(_T_77, _T_78) @[el2_ifu_ifc_ctrl.scala 115:60]
node next_state_0 = or(_T_76, _T_79) @[el2_ifu_ifc_ctrl.scala 115:48]
node _T_80 = cat(next_state_0, next_state_0) @[Cat.scala 29:58] node _T_80 = cat(next_state_0, next_state_0) @[Cat.scala 29:58]
reg _T_81 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 117:19] reg _T_81 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 113:19]
_T_81 <= _T_80 @[el2_ifu_ifc_ctrl.scala 117:19] _T_81 <= _T_80 @[el2_ifu_ifc_ctrl.scala 113:19]
state <= _T_81 @[el2_ifu_ifc_ctrl.scala 117:9] state <= _T_81 @[el2_ifu_ifc_ctrl.scala 113:9]
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 119:12] flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 119:12]
node _T_82 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 121:38] node _T_82 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 121:38]
node _T_83 = and(io.ifu_fb_consume1, _T_82) @[el2_ifu_ifc_ctrl.scala 121:36] node _T_83 = and(io.ifu_fb_consume1, _T_82) @[el2_ifu_ifc_ctrl.scala 121:36]
@ -186,71 +178,85 @@ circuit el2_ifu_ifc_ctrl :
node _T_95 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 125:80] node _T_95 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 125:80]
node _T_96 = and(_T_94, _T_95) @[el2_ifu_ifc_ctrl.scala 125:78] node _T_96 = and(_T_94, _T_95) @[el2_ifu_ifc_ctrl.scala 125:78]
fb_left <= _T_96 @[el2_ifu_ifc_ctrl.scala 125:11] fb_left <= _T_96 @[el2_ifu_ifc_ctrl.scala 125:11]
node _T_97 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 128:6] node _T_97 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctrl.scala 127:37]
node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctrl.scala 128:16] node _T_98 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 128:6]
node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctrl.scala 128:28] node _T_99 = and(_T_98, fb_right) @[el2_ifu_ifc_ctrl.scala 128:16]
node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 128:62] node _T_100 = bits(_T_99, 0, 0) @[el2_ifu_ifc_ctrl.scala 128:28]
node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58] node _T_101 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 128:62]
node _T_102 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 129:6] node _T_102 = cat(UInt<1>("h00"), _T_101) @[Cat.scala 29:58]
node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctrl.scala 129:16] node _T_103 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 129:6]
node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctrl.scala 129:29] node _T_104 = and(_T_103, fb_right2) @[el2_ifu_ifc_ctrl.scala 129:16]
node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 129:63] node _T_105 = bits(_T_104, 0, 0) @[el2_ifu_ifc_ctrl.scala 129:29]
node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58] node _T_106 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 129:63]
node _T_107 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 130:6] node _T_107 = cat(UInt<2>("h00"), _T_106) @[Cat.scala 29:58]
node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctrl.scala 130:16] node _T_108 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 130:6]
node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctrl.scala 130:27] node _T_109 = and(_T_108, fb_left) @[el2_ifu_ifc_ctrl.scala 130:16]
node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 130:51] node _T_110 = bits(_T_109, 0, 0) @[el2_ifu_ifc_ctrl.scala 130:27]
node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58] node _T_111 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 130:51]
node _T_112 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 131:6] node _T_112 = cat(_T_111, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_113 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 131:18] node _T_113 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 131:6]
node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctrl.scala 131:16] node _T_114 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 131:18]
node _T_115 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 131:30] node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctrl.scala 131:16]
node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctrl.scala 131:28] node _T_116 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 131:30]
node _T_117 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 131:43] node _T_117 = and(_T_115, _T_116) @[el2_ifu_ifc_ctrl.scala 131:28]
node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctrl.scala 131:41] node _T_118 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 131:43]
node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctrl.scala 131:53] node _T_119 = and(_T_117, _T_118) @[el2_ifu_ifc_ctrl.scala 131:41]
node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 131:73] node _T_120 = bits(_T_119, 0, 0) @[el2_ifu_ifc_ctrl.scala 131:53]
node _T_121 = mux(io.exu_flush_final, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_121 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 131:73]
node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72] node _T_122 = mux(_T_97, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72] node _T_123 = mux(_T_100, _T_102, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_124 = mux(_T_109, _T_111, UInt<1>("h00")) @[Mux.scala 27:72] node _T_124 = mux(_T_105, _T_107, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_125 = mux(_T_119, _T_120, UInt<1>("h00")) @[Mux.scala 27:72] node _T_125 = mux(_T_110, _T_112, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_126 = or(_T_121, _T_122) @[Mux.scala 27:72] node _T_126 = mux(_T_120, _T_121, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72] node _T_127 = or(_T_122, _T_123) @[Mux.scala 27:72]
node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72] node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72] node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72]
wire _T_130 : UInt<4> @[Mux.scala 27:72] node _T_130 = or(_T_129, _T_126) @[Mux.scala 27:72]
_T_130 <= _T_129 @[Mux.scala 27:72] wire _T_131 : UInt<4> @[Mux.scala 27:72]
fb_write_ns <= _T_130 @[el2_ifu_ifc_ctrl.scala 127:15] _T_131 <= _T_130 @[Mux.scala 27:72]
reg _T_131 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 134:26] fb_write_ns <= _T_131 @[el2_ifu_ifc_ctrl.scala 127:15]
_T_131 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 134:26] node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 134:38]
fb_full_f_ns <= _T_131 @[el2_ifu_ifc_ctrl.scala 134:16] reg _T_133 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 134:26]
node _T_132 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 136:17] _T_133 <= _T_132 @[el2_ifu_ifc_ctrl.scala 134:26]
idle <= _T_132 @[el2_ifu_ifc_ctrl.scala 136:8] fb_full_f_ns <= _T_133 @[el2_ifu_ifc_ctrl.scala 134:16]
node _T_133 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 137:16] node _T_134 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 136:17]
wfm <= _T_133 @[el2_ifu_ifc_ctrl.scala 137:7] idle <= _T_134 @[el2_ifu_ifc_ctrl.scala 136:8]
node _T_134 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 139:30] node _T_135 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 137:16]
fb_full_f_ns <= _T_134 @[el2_ifu_ifc_ctrl.scala 139:16] wfm <= _T_135 @[el2_ifu_ifc_ctrl.scala 137:7]
node _T_136 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 139:30]
fb_full_f_ns <= _T_136 @[el2_ifu_ifc_ctrl.scala 139:16]
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 140:26] reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 140:26]
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 140:26] fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 140:26]
node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 143:26] reg _T_137 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 141:24]
node _T_136 = or(_T_135, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 143:47] _T_137 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 141:24]
node _T_137 = not(_T_136) @[el2_ifu_ifc_ctrl.scala 143:5] fb_write_f <= _T_137 @[el2_ifu_ifc_ctrl.scala 141:14]
node _T_138 = and(fb_full_f, _T_137) @[el2_ifu_ifc_ctrl.scala 142:75] node _T_138 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 144:26]
node _T_139 = or(_T_138, dma_stall) @[el2_ifu_ifc_ctrl.scala 143:70] node _T_139 = or(_T_138, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 144:47]
node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[el2_ifu_ifc_ctrl.scala 142:60] node _T_140 = not(_T_139) @[el2_ifu_ifc_ctrl.scala 144:5]
node _T_141 = or(wfm, _T_140) @[el2_ifu_ifc_ctrl.scala 142:33] node _T_141 = and(fb_full_f, _T_140) @[el2_ifu_ifc_ctrl.scala 143:75]
io.ifu_pmu_fetch_stall <= _T_141 @[el2_ifu_ifc_ctrl.scala 142:26] node _T_142 = or(_T_141, dma_stall) @[el2_ifu_ifc_ctrl.scala 144:70]
node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_143 = and(io.ifc_fetch_req_bf_raw, _T_142) @[el2_ifu_ifc_ctrl.scala 143:60]
node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 203:25] node _T_144 = or(wfm, _T_143) @[el2_ifu_ifc_ctrl.scala 143:33]
node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 203:47] io.ifu_pmu_fetch_stall <= _T_144 @[el2_ifu_ifc_ctrl.scala 143:26]
node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 206:14] node _T_145 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 206:29] node _T_146 = bits(_T_145, 31, 28) @[el2_lib.scala 204:25]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 149:25] node iccm_acc_in_region_bf = eq(_T_146, UInt<4>("h0e")) @[el2_lib.scala 204:47]
node _T_145 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 150:78] node _T_147 = bits(_T_145, 31, 16) @[el2_lib.scala 207:14]
node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58] node iccm_acc_in_range_bf = eq(_T_147, UInt<16>("h0ee00")) @[el2_lib.scala 207:29]
node _T_147 = dshr(io.dec_tlu_mrac_ff, _T_146) @[el2_ifu_ifc_ctrl.scala 150:53] io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 150:25]
node _T_148 = bits(_T_147, 0, 0) @[el2_ifu_ifc_ctrl.scala 150:53] node _T_148 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 151:78]
node _T_149 = not(_T_148) @[el2_ifu_ifc_ctrl.scala 150:34] node _T_149 = cat(_T_148, UInt<1>("h00")) @[Cat.scala 29:58]
io.ifc_fetch_uncacheable_bf <= _T_149 @[el2_ifu_ifc_ctrl.scala 150:31] node _T_150 = dshr(io.dec_tlu_mrac_ff, _T_149) @[el2_ifu_ifc_ctrl.scala 151:53]
node _T_151 = bits(_T_150, 0, 0) @[el2_ifu_ifc_ctrl.scala 151:53]
node _T_152 = not(_T_151) @[el2_ifu_ifc_ctrl.scala 151:34]
io.ifc_fetch_uncacheable_bf <= _T_152 @[el2_ifu_ifc_ctrl.scala 151:31]
reg _T_153 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 155:32]
_T_153 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 155:32]
io.ifc_fetch_req_f <= _T_153 @[el2_ifu_ifc_ctrl.scala 155:22]
node _T_154 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 158:88]
reg _T_155 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_154 : @[Reg.scala 28:19]
_T_155 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
io.ifc_fetch_addr_f <= _T_155 @[el2_ifu_ifc_ctrl.scala 158:23]

201
el2_ifu_ifc_ctrl.v
View File

@ -17,7 +17,7 @@ module el2_ifu_ifc_ctrl(
input io_ic_dma_active, input io_ic_dma_active,
input io_ic_write_stall, input io_ic_write_stall,
input io_dma_iccm_stall_any, input io_dma_iccm_stall_any,
input [30:0] io_dec_tlu_mrac_ff, input [31:0] io_dec_tlu_mrac_ff,
output [30:0] io_ifc_fetch_addr_f, output [30:0] io_ifc_fetch_addr_f,
output [30:0] io_ifc_fetch_addr_bf, output [30:0] io_ifc_fetch_addr_bf,
output io_ifc_fetch_req_f, output io_ifc_fetch_req_f,
@ -27,7 +27,8 @@ module el2_ifu_ifc_ctrl(
output io_ifc_fetch_req_bf_raw, output io_ifc_fetch_req_bf_raw,
output io_ifc_iccm_access_bf, output io_ifc_iccm_access_bf,
output io_ifc_region_acc_fault_bf, output io_ifc_region_acc_fault_bf,
output io_ifc_dma_access_ok output io_ifc_dma_access_ok,
output [30:0] io_test_out
); );
`ifdef RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0; reg [31:0] _RAND_0;
@ -35,77 +36,114 @@ module el2_ifu_ifc_ctrl(
reg [31:0] _RAND_2; reg [31:0] _RAND_2;
reg [31:0] _RAND_3; reg [31:0] _RAND_3;
reg [31:0] _RAND_4; reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 75:37] reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 70:34]
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 76:36] wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 69:36]
wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 79:23] wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 74:23]
wire _T_2 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 79:46] wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 74:46]
wire _T_3 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 79:68] wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 74:68]
wire _T_4 = _T_2 | _T_3; // @[el2_ifu_ifc_ctrl.scala 79:66] wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctrl.scala 74:66]
wire sel_last_addr_bf = _T_1 & _T_4; // @[el2_ifu_ifc_ctrl.scala 79:43] wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctrl.scala 74:43]
wire _T_7 = _T_1 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 80:43] wire _T_8 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 75:43]
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 80:64] wire _T_9 = _T_8 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 75:64]
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 80:88] wire sel_btb_addr_bf = _T_9 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 75:88]
wire _T_12 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 81:66] wire _T_13 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 76:66]
wire _T_13 = _T_7 & _T_12; // @[el2_ifu_ifc_ctrl.scala 81:64] wire _T_14 = _T_8 & _T_13; // @[el2_ifu_ifc_ctrl.scala 76:64]
wire sel_next_addr_bf = _T_13 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 81:89] wire sel_next_addr_bf = _T_14 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 76:89]
wire [30:0] _T_16 = io_ifc_fetch_addr_f + 31'h2; // @[el2_ifu_ifc_ctrl.scala 84:42] wire [30:0] _T_20 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _GEN_1 = {{30'd0}, io_ifc_fetch_addr_f[0]}; // @[el2_ifu_ifc_ctrl.scala 84:48] wire [30:0] _T_21 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_20 = _T_16 | _GEN_1; // @[el2_ifu_ifc_ctrl.scala 84:48] wire [30:0] _T_22 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_25 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72] wire [29:0] _T_30 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 88:52]
wire [30:0] _T_26 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72] wire [29:0] _GEN_1 = {{29'd0}, io_ifc_fetch_addr_f[0]}; // @[el2_ifu_ifc_ctrl.scala 88:58]
wire [30:0] _T_27 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72] wire [29:0] _T_34 = _T_30 | _GEN_1; // @[el2_ifu_ifc_ctrl.scala 88:58]
wire [31:0] fetch_addr_next = {{1'd0}, _T_20}; // @[el2_ifu_ifc_ctrl.scala 84:19] wire [31:0] fetch_addr_next = {{2'd0}, _T_34}; // @[el2_ifu_ifc_ctrl.scala 88:19]
wire [31:0] _T_28 = sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_23 = sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72]
wire [30:0] _T_29 = _T_25 | _T_26; // @[Mux.scala 27:72] wire [30:0] _T_24 = _T_20 | _T_21; // @[Mux.scala 27:72]
wire [30:0] _T_30 = _T_29 | _T_27; // @[Mux.scala 27:72] wire [30:0] _T_25 = _T_24 | _T_22; // @[Mux.scala 27:72]
wire [31:0] _GEN_2 = {{1'd0}, _T_30}; // @[Mux.scala 27:72] wire [31:0] _GEN_2 = {{1'd0}, _T_25}; // @[Mux.scala 27:72]
wire [31:0] _T_31 = _GEN_2 | _T_28; // @[Mux.scala 27:72] wire [31:0] _T_26 = _GEN_2 | _T_23; // @[Mux.scala 27:72]
wire _T_33 = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 95:88] reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 113:19]
reg [30:0] _T_34; // @[Reg.scala 27:20]
reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 117:19]
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 136:17] wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 136:17]
reg [30:0] _T_36; // @[el2_ifu_ifc_ctrl.scala 99:32] wire _T_36 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 95:91]
wire _T_37 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 101:91] wire _T_37 = ~_T_36; // @[el2_ifu_ifc_ctrl.scala 95:70]
wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctrl.scala 101:70] wire [3:0] _T_122 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] fb_write_ns = {{3'd0}, io_exu_flush_final}; // @[Mux.scala 27:72] wire _T_82 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 121:38]
wire _T_83 = io_ifu_fb_consume1 & _T_82; // @[el2_ifu_ifc_ctrl.scala 121:36]
wire _T_49 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctrl.scala 100:32]
wire miss_f = _T_49 & _T_2; // @[el2_ifu_ifc_ctrl.scala 100:47]
wire _T_85 = _T_3 | miss_f; // @[el2_ifu_ifc_ctrl.scala 121:81]
wire _T_86 = _T_83 & _T_85; // @[el2_ifu_ifc_ctrl.scala 121:58]
wire _T_87 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 122:25]
wire fb_right = _T_86 | _T_87; // @[el2_ifu_ifc_ctrl.scala 121:92]
wire _T_99 = _T_2 & fb_right; // @[el2_ifu_ifc_ctrl.scala 128:16]
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctrl.scala 141:24]
wire [3:0] _T_102 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
wire [3:0] _T_123 = _T_99 ? _T_102 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_127 = _T_122 | _T_123; // @[Mux.scala 27:72]
wire fb_right2 = io_ifu_fb_consume2 & _T_85; // @[el2_ifu_ifc_ctrl.scala 124:36]
wire _T_104 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctrl.scala 129:16]
wire [3:0] _T_107 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
wire [3:0] _T_124 = _T_104 ? _T_107 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
wire _T_92 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 125:56]
wire _T_93 = ~_T_92; // @[el2_ifu_ifc_ctrl.scala 125:35]
wire _T_94 = io_ifc_fetch_req_f & _T_93; // @[el2_ifu_ifc_ctrl.scala 125:33]
wire _T_95 = ~miss_f; // @[el2_ifu_ifc_ctrl.scala 125:80]
wire fb_left = _T_94 & _T_95; // @[el2_ifu_ifc_ctrl.scala 125:78]
wire _T_109 = _T_2 & fb_left; // @[el2_ifu_ifc_ctrl.scala 130:16]
wire [3:0] _T_112 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
wire [3:0] _T_125 = _T_109 ? _T_112 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_129 = _T_128 | _T_125; // @[Mux.scala 27:72]
wire _T_114 = ~fb_right; // @[el2_ifu_ifc_ctrl.scala 131:18]
wire _T_115 = _T_2 & _T_114; // @[el2_ifu_ifc_ctrl.scala 131:16]
wire _T_116 = ~fb_right2; // @[el2_ifu_ifc_ctrl.scala 131:30]
wire _T_117 = _T_115 & _T_116; // @[el2_ifu_ifc_ctrl.scala 131:28]
wire _T_118 = ~fb_left; // @[el2_ifu_ifc_ctrl.scala 131:43]
wire _T_119 = _T_117 & _T_118; // @[el2_ifu_ifc_ctrl.scala 131:41]
wire [3:0] _T_126 = _T_119 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
wire [3:0] fb_write_ns = _T_129 | _T_126; // @[Mux.scala 27:72]
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 139:30] wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 139:30]
wire _T_39 = fb_full_f_ns & _T_38; // @[el2_ifu_ifc_ctrl.scala 101:68] wire _T_38 = fb_full_f_ns & _T_37; // @[el2_ifu_ifc_ctrl.scala 95:68]
wire _T_40 = ~_T_39; // @[el2_ifu_ifc_ctrl.scala 101:53] wire _T_39 = ~_T_38; // @[el2_ifu_ifc_ctrl.scala 95:53]
wire _T_41 = io_ifc_fetch_req_bf_raw & _T_40; // @[el2_ifu_ifc_ctrl.scala 101:51] wire _T_40 = io_ifc_fetch_req_bf_raw & _T_39; // @[el2_ifu_ifc_ctrl.scala 95:51]
wire _T_42 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 102:5] wire _T_41 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 96:5]
wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctrl.scala 101:114] wire _T_42 = _T_40 & _T_41; // @[el2_ifu_ifc_ctrl.scala 95:114]
wire _T_44 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 102:18] wire _T_43 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 96:18]
wire _T_45 = _T_43 & _T_44; // @[el2_ifu_ifc_ctrl.scala 102:16] wire _T_44 = _T_42 & _T_43; // @[el2_ifu_ifc_ctrl.scala 96:16]
wire _T_46 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 102:39] wire _T_45 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 96:39]
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 106:35] wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 98:37]
wire _T_61 = io_exu_flush_final & _T_46; // @[el2_ifu_ifc_ctrl.scala 110:36] wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 104:35]
wire leave_idle = _T_61 & idle; // @[el2_ifu_ifc_ctrl.scala 110:67] wire _T_61 = io_exu_flush_final & _T_45; // @[el2_ifu_ifc_ctrl.scala 106:36]
wire _T_68 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 112:55] wire leave_idle = _T_61 & idle; // @[el2_ifu_ifc_ctrl.scala 106:67]
wire _T_76 = _T_68 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 115:34] wire _T_68 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 108:55]
wire _T_79 = state[0] & _T_68; // @[el2_ifu_ifc_ctrl.scala 115:60] wire _T_76 = _T_68 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 111:34]
wire next_state_0 = _T_76 | _T_79; // @[el2_ifu_ifc_ctrl.scala 115:48] wire _T_79 = state[0] & _T_68; // @[el2_ifu_ifc_ctrl.scala 111:60]
wire next_state_0 = _T_76 | _T_79; // @[el2_ifu_ifc_ctrl.scala 111:48]
wire [1:0] _T_80 = {next_state_0,next_state_0}; // @[Cat.scala 29:58] wire [1:0] _T_80 = {next_state_0,next_state_0}; // @[Cat.scala 29:58]
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 137:16] wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 137:16]
reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 140:26] reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 140:26]
wire _T_136 = _T_37 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 143:47] wire _T_139 = _T_36 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 144:47]
wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctrl.scala 143:5] wire _T_140 = ~_T_139; // @[el2_ifu_ifc_ctrl.scala 144:5]
wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctrl.scala 142:75] wire _T_141 = fb_full_f & _T_140; // @[el2_ifu_ifc_ctrl.scala 143:75]
wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 143:70] wire _T_142 = _T_141 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 144:70]
wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctrl.scala 142:60] wire _T_143 = io_ifc_fetch_req_bf_raw & _T_142; // @[el2_ifu_ifc_ctrl.scala 143:60]
wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_145 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
wire [4:0] _T_146 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58] wire [4:0] _T_149 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
wire [30:0] _T_147 = io_dec_tlu_mrac_ff >> _T_146; // @[el2_ifu_ifc_ctrl.scala 150:53] wire [31:0] _T_150 = io_dec_tlu_mrac_ff >> _T_149; // @[el2_ifu_ifc_ctrl.scala 151:53]
assign io_ifc_fetch_addr_f = _T_34; // @[el2_ifu_ifc_ctrl.scala 64:23 el2_ifu_ifc_ctrl.scala 95:23] reg _T_153; // @[el2_ifu_ifc_ctrl.scala 155:32]
assign io_ifc_fetch_addr_bf = _T_31[30:0]; // @[el2_ifu_ifc_ctrl.scala 65:24 el2_ifu_ifc_ctrl.scala 89:24] reg [30:0] _T_155; // @[Reg.scala 27:20]
assign io_ifc_fetch_req_f = _T_36[0]; // @[el2_ifu_ifc_ctrl.scala 66:22 el2_ifu_ifc_ctrl.scala 99:22] assign io_ifc_fetch_addr_f = _T_155; // @[el2_ifu_ifc_ctrl.scala 158:23]
assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctrl.scala 67:26 el2_ifu_ifc_ctrl.scala 142:26] assign io_ifc_fetch_addr_bf = _T_26[30:0]; // @[el2_ifu_ifc_ctrl.scala 79:24]
assign io_ifc_fetch_uncacheable_bf = ~_T_147[0]; // @[el2_ifu_ifc_ctrl.scala 68:31 el2_ifu_ifc_ctrl.scala 150:31] assign io_ifc_fetch_req_f = _T_153; // @[el2_ifu_ifc_ctrl.scala 155:22]
assign io_ifc_fetch_req_bf = _T_45 & _T_46; // @[el2_ifu_ifc_ctrl.scala 69:23 el2_ifu_ifc_ctrl.scala 101:23] assign io_ifu_pmu_fetch_stall = wfm | _T_143; // @[el2_ifu_ifc_ctrl.scala 143:26]
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 70:27 el2_ifu_ifc_ctrl.scala 97:27] assign io_ifc_fetch_uncacheable_bf = ~_T_150[0]; // @[el2_ifu_ifc_ctrl.scala 151:31]
assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 71:25 el2_ifu_ifc_ctrl.scala 149:25] assign io_ifc_fetch_req_bf = _T_44 & _T_45; // @[el2_ifu_ifc_ctrl.scala 95:23]
assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 72:30] assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 93:27]
assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 73:24] assign io_ifc_iccm_access_bf = _T_145[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 150:25]
assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 40:30]
assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 41:24]
assign io_test_out = io_ifc_fetch_addr_bf; // @[el2_ifu_ifc_ctrl.scala 84:15]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
`endif `endif
@ -144,13 +182,15 @@ initial begin
_RAND_0 = {1{`RANDOM}}; _RAND_0 = {1{`RANDOM}};
dma_iccm_stall_any_f = _RAND_0[0:0]; dma_iccm_stall_any_f = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}}; _RAND_1 = {1{`RANDOM}};
_T_34 = _RAND_1[30:0]; state = _RAND_1[1:0];
_RAND_2 = {1{`RANDOM}}; _RAND_2 = {1{`RANDOM}};
state = _RAND_2[1:0]; fb_write_f = _RAND_2[3:0];
_RAND_3 = {1{`RANDOM}}; _RAND_3 = {1{`RANDOM}};
_T_36 = _RAND_3[30:0]; fb_full_f = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}}; _RAND_4 = {1{`RANDOM}};
fb_full_f = _RAND_4[0:0]; _T_153 = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
_T_155 = _RAND_5[30:0];
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE `endif // RANDOMIZE
end // initial end // initial
@ -164,25 +204,30 @@ end // initial
end else begin end else begin
dma_iccm_stall_any_f <= io_dma_iccm_stall_any; dma_iccm_stall_any_f <= io_dma_iccm_stall_any;
end end
if (reset) begin
_T_34 <= 31'h0;
end else if (_T_33) begin
_T_34 <= io_ifc_fetch_addr_bf;
end
if (reset) begin if (reset) begin
state <= 2'h0; state <= 2'h0;
end else begin end else begin
state <= _T_80; state <= _T_80;
end end
if (reset) begin if (reset) begin
_T_36 <= 31'h0; fb_write_f <= 4'h0;
end else begin end else begin
_T_36 <= io_ifc_fetch_addr_bf; fb_write_f <= fb_write_ns;
end end
if (reset) begin if (reset) begin
fb_full_f <= 1'h0; fb_full_f <= 1'h0;
end else begin end else begin
fb_full_f <= fb_full_f_ns; fb_full_f <= fb_full_f_ns;
end end
if (reset) begin
_T_153 <= 1'h0;
end else begin
_T_153 <= io_ifc_fetch_req_bf;
end
if (reset) begin
_T_155 <= 31'h0;
end else if (fetch_bf_en) begin
_T_155 <= io_ifc_fetch_addr_bf;
end
end end
endmodule endmodule

25
encoder_generator.anno.json Normal file
View File

@ -0,0 +1,25 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~encoder_generator|encoder_generator>io_out",
"sources":[
"~encoder_generator|encoder_generator>io_in"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"encoder_generator"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

22
encoder_generator.fir Normal file
View File

@ -0,0 +1,22 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit encoder_generator :
module encoder_generator :
input clock : Clock
input reset : UInt<1>
output io : {flip in : UInt<4>, out : UInt<2>}
node _T = bits(io.in, 0, 0) @[Mux.scala 29:36]
node _T_1 = bits(io.in, 1, 1) @[Mux.scala 29:36]
node _T_2 = bits(io.in, 2, 2) @[Mux.scala 29:36]
node _T_3 = bits(io.in, 3, 3) @[Mux.scala 29:36]
node _T_4 = mux(_T, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_5 = mux(_T_1, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_6 = mux(_T_2, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_7 = mux(_T_3, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_8 = or(_T_4, _T_5) @[Mux.scala 27:72]
node _T_9 = or(_T_8, _T_6) @[Mux.scala 27:72]
node _T_10 = or(_T_9, _T_7) @[Mux.scala 27:72]
wire _T_11 : UInt<2> @[Mux.scala 27:72]
_T_11 <= _T_10 @[Mux.scala 27:72]
io.out <= _T_11 @[el2_ifu_bp_ctl.scala 198:10]

12
encoder_generator.v Normal file
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@ -0,0 +1,12 @@
module encoder_generator(
input clock,
input reset,
input [3:0] io_in,
output [1:0] io_out
);
wire [1:0] _T_6 = io_in[2] ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_7 = io_in[3] ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_0 = {{1'd0}, io_in[1]}; // @[Mux.scala 27:72]
wire [1:0] _T_9 = _GEN_0 | _T_6; // @[Mux.scala 27:72]
assign io_out = _T_9 | _T_7; // @[el2_ifu_bp_ctl.scala 198:10]
endmodule

74
src/main/scala/ifu/el2_ifu_bp_ctl.scala
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@ -95,8 +95,11 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
val btb_bank0_rd_data_way1_f = WireInit(UInt((TAG_START+1).W), 0.U) val btb_bank0_rd_data_way1_f = WireInit(UInt((TAG_START+1).W), 0.U)
val btb_bank0_rd_data_way0_p1_f = WireInit(UInt((TAG_START+1).W), 0.U) val btb_bank0_rd_data_way0_p1_f = WireInit(UInt((TAG_START+1).W), 0.U)
val btb_bank0_rd_data_way1_p1_f = WireInit(UInt((TAG_START+1).W), 0.U) val btb_bank0_rd_data_way1_p1_f = WireInit(UInt((TAG_START+1).W), 0.U)
val eoc_mask = WireInit(Bool(), 0.U)
val btb_lru_b0_f = WireInit(UInt(LRU_SIZE.W), init = 0.U)
val dec_tlu_way_wb = WireInit(Bool(), 0.U) val dec_tlu_way_wb = WireInit(Bool(), 0.U)
// Hash the first PC // Hash the first PC
val btb_rd_addr_f = el2_btb_addr_hash(io.ifc_fetch_addr_f) val btb_rd_addr_f = el2_btb_addr_hash(io.ifc_fetch_addr_f)
// Second pc = pc +4 // Second pc = pc +4
@ -141,8 +144,77 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
val tag_match_way1_p1_f = btb_bank0_rd_data_way1_p1_f(BV) & (btb_bank0_rd_data_way1_p1_f(TAG_START,17) === fetch_rd_tag_p1_f) & val tag_match_way1_p1_f = btb_bank0_rd_data_way1_p1_f(BV) & (btb_bank0_rd_data_way1_p1_f(TAG_START,17) === fetch_rd_tag_p1_f) &
~(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & ~leak_one_f ~(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & ~leak_one_f
// Reordering to avoid multiple hit
val tag_match_way0_expanded_f = Cat(tag_match_way0_f & (btb_bank0_rd_data_way0_f(BOFF) ^ btb_bank0_rd_data_way0_f(PC4)),
tag_match_way0_f & ~(btb_bank0_rd_data_way0_f(BOFF) ^ btb_bank0_rd_data_way0_f(PC4)))
val tag_match_way1_expanded_f = Cat(tag_match_way1_f & (btb_bank0_rd_data_way1_f(BOFF) ^ btb_bank0_rd_data_way1_f(PC4)),
tag_match_way1_f & ~(btb_bank0_rd_data_way1_f(BOFF) ^ btb_bank0_rd_data_way1_f(PC4)))
val tag_match_way0_expanded_p1_f = Cat(tag_match_way0_p1_f & (btb_bank0_rd_data_way0_p1_f(BOFF) ^ btb_bank0_rd_data_way0_p1_f(PC4)),
tag_match_way0_p1_f & ~(btb_bank0_rd_data_way0_p1_f(BOFF) ^ btb_bank0_rd_data_way0_p1_f(PC4)))
val tag_match_way1_expanded_p1_f = Cat(tag_match_way1_p1_f & (btb_bank0_rd_data_way1_p1_f(BOFF) ^ btb_bank0_rd_data_way1_p1_f(PC4)),
tag_match_way1_p1_f & ~(btb_bank0_rd_data_way1_p1_f(BOFF) ^ btb_bank0_rd_data_way1_p1_f(PC4)))
val wayhit_f = tag_match_way0_expanded_f | tag_match_way1_expanded_f
val wayhit_p1_f = tag_match_way0_expanded_p1_f | tag_match_way1_expanded_p1_f
// Chopping off the ways that had a hit
val btb_bank0e_rd_data_f = Mux1H(Seq(tag_match_way0_expanded_f(0).asBool->btb_bank0_rd_data_way0_f,
tag_match_way1_expanded_f(0).asBool->btb_bank0_rd_data_way1_f))
val btb_bank0o_rd_data_f = Mux1H(Seq(tag_match_way0_expanded_f(1).asBool->btb_bank0_rd_data_way0_f,
tag_match_way1_expanded_f(1).asBool->btb_bank0_rd_data_way1_f))
val btb_bank0e_rd_data_p1_f = Mux1H(Seq(tag_match_way0_expanded_p1_f(0).asBool->btb_bank0_rd_data_way0_p1_f,
tag_match_way1_expanded_p1_f(1).asBool->btb_bank0_rd_data_way1_p1_f))
// Making virtual banks, made bit 1 of the pc to check
val btb_vbank0_rd_data_f = Mux1H(Seq(~io.ifc_fetch_addr_f(1)->btb_bank0e_rd_data_f,
io.ifc_fetch_addr_f(1)->btb_bank0o_rd_data_f))
val btb_vbank1_rd_data_f = Mux1H(Seq(~io.ifc_fetch_addr_f(0)->btb_bank0o_rd_data_f,
io.ifc_fetch_addr_f(0)->btb_bank0e_rd_data_p1_f))
// Implimenting the LRU for a 2-way BTB
val mp_wrindex_dec = 1.U(LRU_SIZE) << exu_mp_addr
val fetch_wrindex_dec = 1.U(LRU_SIZE) << btb_rd_addr_f
val fetch_wrindex_p1_dec = 1.U(LRU_SIZE) << btb_rd_addr_p1_f
val mp_wrlru_b0 = mp_wrindex_dec & Fill(LRU_SIZE, exu_mp_valid)
val vwayhit_f = Mux1H(Seq(~io.ifc_fetch_addr_f(1).asBool->wayhit_f,
io.ifc_fetch_addr_f(1).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
val lru_update_valid_f = (vwayhit_f(0) | vwayhit_f(1)) & io.ifc_fetch_req_f & ~leak_one_f
val fetch_wrlru_b0 = fetch_wrindex_dec & Fill(fetch_wrindex_dec.getWidth, lru_update_valid_f)
val fetch_wrlru_p1_b0 = fetch_wrindex_p1_dec & Fill(fetch_wrindex_dec.getWidth, lru_update_valid_f)
val btb_lru_b0_hold = ~mp_wrlru_b0 & ~fetch_wrlru_b0
val use_mp_way = fetch_mp_collision_f
val use_mp_way_p1 = fetch_mp_collision_p1_f
val btb_lru_b0_ns = Mux1H(Seq(~exu_mp_way.asBool->mp_wrlru_b0,
tag_match_way0_f.asBool->fetch_wrlru_b0,tag_match_way0_p1_f.asBool->fetch_wrlru_p1_b0)) | btb_lru_b0_hold & btb_lru_b0_f
val btb_lru_rd_f = Mux(use_mp_way.asBool, exu_mp_way_f, (fetch_wrindex_dec & btb_lru_b0_f).orR)
val btb_lru_rd_p1_f = Mux(use_mp_way_p1.asBool, exu_mp_way_f, (fetch_wrindex_p1_dec & btb_lru_b0_f).orR)
val btb_vlru_rd_f = Mux1H(Seq(~io.ifc_fetch_addr_f(1).asBool->Cat(btb_lru_rd_f, btb_lru_rd_f),
io.ifc_fetch_addr_f(1).asBool->Cat(btb_lru_rd_p1_f, btb_lru_rd_f)))
val tag_match_vway1_expanded_f = Mux1H(Seq(~io.ifc_fetch_addr_f(1).asBool->tag_match_way1_expanded_f,
io.ifc_fetch_addr_f(1).asBool->Cat(tag_match_way1_expanded_p1_f(0),tag_match_way1_expanded_f(1))))
val way_raw = tag_match_vway1_expanded_f | (~vwayhit_f & btb_vlru_rd_f)
//val btb_lru_b0_f = RegNext(btb_lru_b0_ns, init = 0.U)
} }
object ifu_bp extends App { object ifu_bp extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl())) println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl()))
} }

1
src/main/scala/ifu/el2_ifu_compress.scala
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@ -2,7 +2,6 @@ package ifu
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import lib.ExpandedInstruction
class ExpandedInstruction extends Bundle { class ExpandedInstruction extends Bundle {
val bits = UInt(32.W) val bits = UInt(32.W)

66
src/main/scala/ifu/el2_ifu_ifc_ctrl.scala
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@ -21,10 +21,11 @@ val io = IO(new Bundle{
val ic_dma_active = Input(Bool()) val ic_dma_active = Input(Bool())
val ic_write_stall = Input(Bool()) val ic_write_stall = Input(Bool())
val dma_iccm_stall_any = Input(Bool()) val dma_iccm_stall_any = Input(Bool())
val dec_tlu_mrac_ff = Input(UInt(31.W)) val dec_tlu_mrac_ff = Input(UInt(32.W))
val ifc_fetch_addr_f = Output(UInt(31.W)) val ifc_fetch_addr_f = Output(UInt(31.W))
val ifc_fetch_addr_bf = Output(UInt(31.W)) val ifc_fetch_addr_bf = Output(UInt(31.W))
val ifc_fetch_req_f = Output(Bool()) val ifc_fetch_req_f = Output(Bool())
val ifu_pmu_fetch_stall = Output(Bool()) val ifu_pmu_fetch_stall = Output(Bool())
val ifc_fetch_uncacheable_bf = Output(Bool()) val ifc_fetch_uncacheable_bf = Output(Bool())
@ -33,14 +34,16 @@ val io = IO(new Bundle{
val ifc_iccm_access_bf = Output(Bool()) val ifc_iccm_access_bf = Output(Bool())
val ifc_region_acc_fault_bf = Output(Bool()) val ifc_region_acc_fault_bf = Output(Bool())
val ifc_dma_access_ok = Output(Bool()) val ifc_dma_access_ok = Output(Bool())
val test_out = Output(UInt())
}) })
io.ifc_region_acc_fault_bf := 0.U
io.ifc_dma_access_ok := 0.U
val fetch_addr_bf = WireInit(UInt(32.W), init = 0.U) val fetch_addr_bf = WireInit(UInt(32.W), init = 0.U)
val fetch_addr_next = WireInit(UInt(32.W), init = 0.U) val fetch_addr_next = WireInit(UInt(32.W), init = 0.U)
val fb_write_ns = WireInit(UInt(4.W), init = 0.U) val fb_write_ns = WireInit(UInt(4.W), init = 0.U)
val fb_write_f = WireInit(UInt(4.W), init = 0.U) val fb_write_f = WireInit(UInt(4.W), init = 0.U)
val fb_full_f_ns = WireInit(Bool(), init = 0.U) val fb_full_f_ns = WireInit(Bool(), init = 0.U)
//val fb_full_f = WireInit(Bool(), init = 0.U)
val fb_right = WireInit(Bool(), init = 0.U) val fb_right = WireInit(Bool(), init = 0.U)
val fb_right2 = WireInit(Bool(), init = 0.U) val fb_right2 = WireInit(Bool(), init = 0.U)
val fb_left = WireInit(Bool(), init = 0.U) val fb_left = WireInit(Bool(), init = 0.U)
@ -50,7 +53,7 @@ val io = IO(new Bundle{
val sel_btb_addr_bf = WireInit(Bool(), init = 0.U) val sel_btb_addr_bf = WireInit(Bool(), init = 0.U)
val sel_next_addr_bf = WireInit(Bool(), init = 0.U) val sel_next_addr_bf = WireInit(Bool(), init = 0.U)
val miss_f = WireInit(Bool(), init = 0.U) val miss_f = WireInit(Bool(), init = 0.U)
val miss_a = Wire(Bool()) val miss_a = WireInit(Bool(), init = 0.U)
val flush_fb = WireInit(Bool(), init = 0.U) val flush_fb = WireInit(Bool(), init = 0.U)
val mb_empty_mod = WireInit(Bool(), init = 0.U) val mb_empty_mod = WireInit(Bool(), init = 0.U)
val goto_idle = WireInit(Bool(), init = 0.U) val goto_idle = WireInit(Bool(), init = 0.U)
@ -59,54 +62,45 @@ val io = IO(new Bundle{
val line_wrap = WireInit(Bool(), init = 0.U) val line_wrap = WireInit(Bool(), init = 0.U)
//val fetch_addr_next_1 = WireInit(Bool(), init = 0.U) //val fetch_addr_next_1 = WireInit(Bool(), init = 0.U)
val state = WireInit(UInt(2.W), init = 0.U) val state = WireInit(UInt(2.W), init = 0.U)
val dma_iccm_stall_any_f = WireInit(Bool(), init = 0.U)
val idle_E :: fetch_E :: stall_E :: wfm_E :: Nil = Enum(4) val idle_E :: fetch_E :: stall_E :: wfm_E :: Nil = Enum(4)
io.ifc_fetch_addr_f := 0.U
io.ifc_fetch_addr_bf := 0.U
io.ifc_fetch_req_f := 0.U
io.ifu_pmu_fetch_stall := 0.U
io.ifc_fetch_uncacheable_bf := 0.U
io.ifc_fetch_req_bf := 0.U
io.ifc_fetch_req_bf_raw := 0.U
io.ifc_iccm_access_bf := 0.U
io.ifc_region_acc_fault_bf := 0.U
io.ifc_dma_access_ok := 0.U
val dma_iccm_stall_any_f = RegNext(io.dma_iccm_stall_any, init=0.U)
val dma_stall = io.ic_dma_active | dma_iccm_stall_any_f val dma_stall = io.ic_dma_active | dma_iccm_stall_any_f
dma_iccm_stall_any_f := RegNext(io.dma_iccm_stall_any, init=0.U)
miss_a := RegNext(miss_f, init=0.U) miss_a := RegNext(miss_f, init=0.U)
sel_last_addr_bf := ~io.exu_flush_final & (~io.ifc_fetch_req_f | ~io.ic_hit_f) sel_last_addr_bf := ~io.exu_flush_final & (~io.ifc_fetch_req_f | ~io.ic_hit_f)
sel_btb_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f sel_btb_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f
sel_next_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & ~io.ifu_bp_hit_taken_f & io.ic_hit_f sel_next_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & ~io.ifu_bp_hit_taken_f & io.ic_hit_f
fetch_addr_next := (io.ifc_fetch_addr_f+2.U) |
Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0))
// TODO: Make an assertion for the 1H-Mux under here // TODO: Make an assertion for the 1H-Mux under here
io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC
sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4 sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
io.test_out := io.ifc_fetch_addr_bf
io.ifc_fetch_addr_f := RegEnable(io.ifc_fetch_addr_bf, init = 0.U, io.exu_flush_final|io.ifc_fetch_req_f) line_wrap := 0.U//fetch_addr_next(ICACHE_TAG_INDEX_LO) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO)
fetch_addr_next := Cat((io.ifc_fetch_addr_f(30,1)+1.U) |
Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0)))
io.ifc_fetch_req_bf_raw := ~idle io.ifc_fetch_req_bf_raw := ~idle
io.ifc_fetch_req_f := RegNext(io.ifc_fetch_addr_bf, init=0.U)
io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & ~(fb_full_f_ns & ~(io.ifu_fb_consume2 | io.ifu_fb_consume1)) & io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & ~(fb_full_f_ns & ~(io.ifu_fb_consume2 | io.ifu_fb_consume1)) &
~dma_stall & ~io.ic_write_stall & ~io.dec_tlu_flush_noredir_wb ~dma_stall & ~io.ic_write_stall & ~io.dec_tlu_flush_noredir_wb
fetch_bf_en := io.exu_flush_final | io.ifc_fetch_req_f
miss_f := io.ifc_fetch_req_f & ~io.ic_hit_f & ~io.exu_flush_final miss_f := io.ifc_fetch_req_f & ~io.ic_hit_f & ~io.exu_flush_final
goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb
mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & ~dma_stall & ~miss_f & ~miss_a mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & ~dma_stall & ~miss_f & ~miss_a
goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb
leave_idle := io.exu_flush_final & ~io.dec_tlu_flush_noredir_wb & idle leave_idle := io.exu_flush_final & ~io.dec_tlu_flush_noredir_wb & idle
val next_state_1 = (~state(1) & state(0) & miss_f & ~goto_idle) | val next_state_1 = (~state(1) & state(0) & miss_f & ~goto_idle) |
@ -116,6 +110,9 @@ val io = IO(new Bundle{
state := RegNext(Cat(next_state_0, next_state_0), init = 0.U) state := RegNext(Cat(next_state_0, next_state_0), init = 0.U)
flush_fb := io.exu_flush_final flush_fb := io.exu_flush_final
fb_right := ( io.ifu_fb_consume1 & ~io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) | fb_right := ( io.ifu_fb_consume1 & ~io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) |
@ -124,20 +121,21 @@ val io = IO(new Bundle{
fb_right2 := (io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) fb_right2 := (io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f))
fb_left := io.ifc_fetch_req_f & ~(io.ifu_fb_consume1 | io.ifu_fb_consume2) & ~miss_f fb_left := io.ifc_fetch_req_f & ~(io.ifu_fb_consume1 | io.ifu_fb_consume2) & ~miss_f
fb_write_ns := Mux1H(Seq(io.exu_flush_final -> 1.U, fb_write_ns := Mux1H(Seq(flush_fb.asBool -> 1.U(4.W),
(~flush_fb & fb_right).asBool -> Cat(0.U(1.W), fb_write_f(3,1)), (~flush_fb & fb_right).asBool -> Cat(0.U(1.W), fb_write_f(3,1)),
(~flush_fb & fb_right2).asBool -> Cat(0.U(2.W), fb_write_f(3,2)), (~flush_fb & fb_right2).asBool -> Cat(0.U(2.W), fb_write_f(3,2)),
(~flush_fb & fb_left).asBool -> Cat(fb_write_f(2,0), 0.U(1.W)), (~flush_fb & fb_left).asBool -> Cat(fb_write_f(2,0), 0.U(1.W)),
(~flush_fb & ~fb_right & ~fb_right2 & ~fb_left).asBool -> fb_write_f(3,0) (~flush_fb & ~fb_right & ~fb_right2 & ~fb_left).asBool -> fb_write_f(3,0)
)) ))
fb_full_f_ns := RegNext(fb_write_ns, init = 0.U) fb_full_f_ns := RegNext(fb_write_ns(3), init = 0.U)
idle := state === idle_E idle := state === 0.U(2.W)
wfm := state === wfm_E wfm := state === 3.U(2.W)
fb_full_f_ns := fb_write_ns(3) fb_full_f_ns := fb_write_ns(3)
val fb_full_f = RegNext(fb_full_f_ns, init = 0.U) val fb_full_f = RegNext(fb_full_f_ns, init = 0.U)
fb_write_f := RegNext(fb_write_ns, 0.U)
io.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw & ( (fb_full_f & io.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw & ( (fb_full_f &
~(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall)) ~(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
@ -148,5 +146,15 @@ val io = IO(new Bundle{
io.ifc_iccm_access_bf := iccm_acc_in_range_bf io.ifc_iccm_access_bf := iccm_acc_in_range_bf
io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U)) io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U))
io.ifc_fetch_req_f := RegNext(io.ifc_fetch_req_bf, init=0.U)
io.ifc_fetch_addr_f := RegEnable(io.ifc_fetch_addr_bf, init = 0.U, io.exu_flush_final|io.ifc_fetch_req_f)
} }
object ifu_ifc extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctrl()))
}

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target/scala-2.12/classes/ifu/ExpandedInstruction.class
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target/scala-2.12/classes/ifu/RVCDecoder.class
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target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
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target/scala-2.12/classes/ifu/el2_ifu_compress$$anon$1.class
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target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl.class
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target/scala-2.12/classes/ifu/ifu_bp$.class
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9
test.anno.json
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@ -1,13 +1,4 @@
[ [
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~test|test>io_out",
"sources":[
"~test|test>io_in3",
"~test|test>io_in1",
"~test|test>io_in2"
]
},
{ {
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"

76
test.fir
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@ -3,79 +3,7 @@ circuit test :
module test : module test :
input clock : Clock input clock : Clock
input reset : UInt<1> input reset : UInt<1>
output io : {flip in1 : UInt<8>, flip in2 : UInt<8>, flip in3 : UInt<1>, out : UInt<1>} output io : {flip in1 : UInt<4>, flip in2 : {waleed : UInt<5>, laraib : UInt<5>, hameed : UInt<5>}, out2 : {waleed : UInt<5>, laraib : UInt<5>, hameed : UInt<5>}, out1 : UInt}
wire _T : UInt<1>[8] @[el2_lib.scala 211:24] io.out1 <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 235:13]
node _T_1 = andr(io.in1) @[el2_lib.scala 212:45]
node _T_2 = not(_T_1) @[el2_lib.scala 212:39]
node _T_3 = and(io.in3, _T_2) @[el2_lib.scala 212:37]
node _T_4 = bits(io.in1, 0, 0) @[el2_lib.scala 213:48]
node _T_5 = bits(io.in2, 0, 0) @[el2_lib.scala 213:60]
node _T_6 = eq(_T_4, _T_5) @[el2_lib.scala 213:52]
node _T_7 = or(_T_3, _T_6) @[el2_lib.scala 213:41]
_T[0] <= _T_7 @[el2_lib.scala 213:18]
node _T_8 = bits(io.in1, 0, 0) @[el2_lib.scala 215:28]
node _T_9 = andr(_T_8) @[el2_lib.scala 215:36]
node _T_10 = and(_T_9, _T_3) @[el2_lib.scala 215:41]
node _T_11 = bits(io.in1, 1, 1) @[el2_lib.scala 215:74]
node _T_12 = bits(io.in2, 1, 1) @[el2_lib.scala 215:86]
node _T_13 = eq(_T_11, _T_12) @[el2_lib.scala 215:78]
node _T_14 = mux(_T_10, UInt<1>("h01"), _T_13) @[el2_lib.scala 215:23]
_T[1] <= _T_14 @[el2_lib.scala 215:17]
node _T_15 = bits(io.in1, 1, 0) @[el2_lib.scala 215:28]
node _T_16 = andr(_T_15) @[el2_lib.scala 215:36]
node _T_17 = and(_T_16, _T_3) @[el2_lib.scala 215:41]
node _T_18 = bits(io.in1, 2, 2) @[el2_lib.scala 215:74]
node _T_19 = bits(io.in2, 2, 2) @[el2_lib.scala 215:86]
node _T_20 = eq(_T_18, _T_19) @[el2_lib.scala 215:78]
node _T_21 = mux(_T_17, UInt<1>("h01"), _T_20) @[el2_lib.scala 215:23]
_T[2] <= _T_21 @[el2_lib.scala 215:17]
node _T_22 = bits(io.in1, 2, 0) @[el2_lib.scala 215:28]
node _T_23 = andr(_T_22) @[el2_lib.scala 215:36]
node _T_24 = and(_T_23, _T_3) @[el2_lib.scala 215:41]
node _T_25 = bits(io.in1, 3, 3) @[el2_lib.scala 215:74]
node _T_26 = bits(io.in2, 3, 3) @[el2_lib.scala 215:86]
node _T_27 = eq(_T_25, _T_26) @[el2_lib.scala 215:78]
node _T_28 = mux(_T_24, UInt<1>("h01"), _T_27) @[el2_lib.scala 215:23]
_T[3] <= _T_28 @[el2_lib.scala 215:17]
node _T_29 = bits(io.in1, 3, 0) @[el2_lib.scala 215:28]
node _T_30 = andr(_T_29) @[el2_lib.scala 215:36]
node _T_31 = and(_T_30, _T_3) @[el2_lib.scala 215:41]
node _T_32 = bits(io.in1, 4, 4) @[el2_lib.scala 215:74]
node _T_33 = bits(io.in2, 4, 4) @[el2_lib.scala 215:86]
node _T_34 = eq(_T_32, _T_33) @[el2_lib.scala 215:78]
node _T_35 = mux(_T_31, UInt<1>("h01"), _T_34) @[el2_lib.scala 215:23]
_T[4] <= _T_35 @[el2_lib.scala 215:17]
node _T_36 = bits(io.in1, 4, 0) @[el2_lib.scala 215:28]
node _T_37 = andr(_T_36) @[el2_lib.scala 215:36]
node _T_38 = and(_T_37, _T_3) @[el2_lib.scala 215:41]
node _T_39 = bits(io.in1, 5, 5) @[el2_lib.scala 215:74]
node _T_40 = bits(io.in2, 5, 5) @[el2_lib.scala 215:86]
node _T_41 = eq(_T_39, _T_40) @[el2_lib.scala 215:78]
node _T_42 = mux(_T_38, UInt<1>("h01"), _T_41) @[el2_lib.scala 215:23]
_T[5] <= _T_42 @[el2_lib.scala 215:17]
node _T_43 = bits(io.in1, 5, 0) @[el2_lib.scala 215:28]
node _T_44 = andr(_T_43) @[el2_lib.scala 215:36]
node _T_45 = and(_T_44, _T_3) @[el2_lib.scala 215:41]
node _T_46 = bits(io.in1, 6, 6) @[el2_lib.scala 215:74]
node _T_47 = bits(io.in2, 6, 6) @[el2_lib.scala 215:86]
node _T_48 = eq(_T_46, _T_47) @[el2_lib.scala 215:78]
node _T_49 = mux(_T_45, UInt<1>("h01"), _T_48) @[el2_lib.scala 215:23]
_T[6] <= _T_49 @[el2_lib.scala 215:17]
node _T_50 = bits(io.in1, 6, 0) @[el2_lib.scala 215:28]
node _T_51 = andr(_T_50) @[el2_lib.scala 215:36]
node _T_52 = and(_T_51, _T_3) @[el2_lib.scala 215:41]
node _T_53 = bits(io.in1, 7, 7) @[el2_lib.scala 215:74]
node _T_54 = bits(io.in2, 7, 7) @[el2_lib.scala 215:86]
node _T_55 = eq(_T_53, _T_54) @[el2_lib.scala 215:78]
node _T_56 = mux(_T_52, UInt<1>("h01"), _T_55) @[el2_lib.scala 215:23]
_T[7] <= _T_56 @[el2_lib.scala 215:17]
node _T_57 = cat(_T[1], _T[0]) @[el2_lib.scala 216:14]
node _T_58 = cat(_T[3], _T[2]) @[el2_lib.scala 216:14]
node _T_59 = cat(_T_58, _T_57) @[el2_lib.scala 216:14]
node _T_60 = cat(_T[5], _T[4]) @[el2_lib.scala 216:14]
node _T_61 = cat(_T[7], _T[6]) @[el2_lib.scala 216:14]
node _T_62 = cat(_T_61, _T_60) @[el2_lib.scala 216:14]
node _T_63 = cat(_T_62, _T_59) @[el2_lib.scala 216:14]
io.out <= _T_63 @[el2_ifu_ifc_ctrl.scala 12:10]

51
test.v
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@ -1,44 +1,17 @@
module test( module test(
input clock, input clock,
input reset, input reset,
input [7:0] io_in1, input [3:0] io_in1,
input [7:0] io_in2, input [4:0] io_in2_waleed,
input io_in3, input [4:0] io_in2_laraib,
output io_out input [4:0] io_in2_hameed,
output [4:0] io_out2_waleed,
output [4:0] io_out2_laraib,
output [4:0] io_out2_hameed,
output io_out1
); );
wire _T_1 = &io_in1; // @[el2_lib.scala 212:45] assign io_out2_waleed = 5'h0; // @[el2_ifu_bp_ctl.scala 228:20]
wire _T_2 = ~_T_1; // @[el2_lib.scala 212:39] assign io_out2_laraib = 5'h0; // @[el2_ifu_bp_ctl.scala 229:20]
wire _T_3 = io_in3 & _T_2; // @[el2_lib.scala 212:37] assign io_out2_hameed = 5'h0; // @[el2_ifu_bp_ctl.scala 230:20]
wire _T_6 = io_in1[0] == io_in2[0]; // @[el2_lib.scala 213:52] assign io_out1 = 1'h0; // @[el2_ifu_bp_ctl.scala 231:13]
wire _T_7 = _T_3 | _T_6; // @[el2_lib.scala 213:41]
wire _T_9 = &io_in1[0]; // @[el2_lib.scala 215:36]
wire _T_10 = _T_9 & _T_3; // @[el2_lib.scala 215:41]
wire _T_13 = io_in1[1] == io_in2[1]; // @[el2_lib.scala 215:78]
wire _T_14 = _T_10 | _T_13; // @[el2_lib.scala 215:23]
wire _T_16 = &io_in1[1:0]; // @[el2_lib.scala 215:36]
wire _T_17 = _T_16 & _T_3; // @[el2_lib.scala 215:41]
wire _T_20 = io_in1[2] == io_in2[2]; // @[el2_lib.scala 215:78]
wire _T_21 = _T_17 | _T_20; // @[el2_lib.scala 215:23]
wire _T_23 = &io_in1[2:0]; // @[el2_lib.scala 215:36]
wire _T_24 = _T_23 & _T_3; // @[el2_lib.scala 215:41]
wire _T_27 = io_in1[3] == io_in2[3]; // @[el2_lib.scala 215:78]
wire _T_28 = _T_24 | _T_27; // @[el2_lib.scala 215:23]
wire _T_30 = &io_in1[3:0]; // @[el2_lib.scala 215:36]
wire _T_31 = _T_30 & _T_3; // @[el2_lib.scala 215:41]
wire _T_34 = io_in1[4] == io_in2[4]; // @[el2_lib.scala 215:78]
wire _T_35 = _T_31 | _T_34; // @[el2_lib.scala 215:23]
wire _T_37 = &io_in1[4:0]; // @[el2_lib.scala 215:36]
wire _T_38 = _T_37 & _T_3; // @[el2_lib.scala 215:41]
wire _T_41 = io_in1[5] == io_in2[5]; // @[el2_lib.scala 215:78]
wire _T_42 = _T_38 | _T_41; // @[el2_lib.scala 215:23]
wire _T_44 = &io_in1[5:0]; // @[el2_lib.scala 215:36]
wire _T_45 = _T_44 & _T_3; // @[el2_lib.scala 215:41]
wire _T_48 = io_in1[6] == io_in2[6]; // @[el2_lib.scala 215:78]
wire _T_49 = _T_45 | _T_48; // @[el2_lib.scala 215:23]
wire _T_51 = &io_in1[6:0]; // @[el2_lib.scala 215:36]
wire _T_52 = _T_51 & _T_3; // @[el2_lib.scala 215:41]
wire _T_55 = io_in1[7] == io_in2[7]; // @[el2_lib.scala 215:78]
wire _T_56 = _T_52 | _T_55; // @[el2_lib.scala 215:23]
wire [7:0] _T_63 = {_T_56,_T_49,_T_42,_T_35,_T_28,_T_21,_T_14,_T_7}; // @[el2_lib.scala 216:14]
assign io_out = _T_63[0]; // @[el2_ifu_ifc_ctrl.scala 12:10]
endmodule endmodule