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package dmi
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import chisel3._
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import lib._
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class dmi_wrapper extends Module with el2_lib {
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val io = IO(new Bundle{
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val trst_n = Input(Bool())
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val tck = Input(Clock())
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val tms = Input(UInt(1.W))
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val tdi = Input(UInt(1.W))
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val tdo = Output(UInt(1.W))
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val tdoEnable = Output(UInt(1.W))
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val core_rst_n = Input(AsyncReset())
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val core_clk = Input(Clock())
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val jtag_id = Input(UInt(32.W))
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val rd_data = Input(UInt(32.W))
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val reg_wr_data = Output(UInt(32.W))
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val reg_wr_addr = Output(UInt(7.W))
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val reg_en = Output(UInt(1.W))
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val reg_wr_en = Output(UInt(1.W))
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val dmi_hard_reset = Output(UInt(1.W))
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})
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val dwrap = {Module(new dmi_wrapper)}
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dwrap.io.trst_n := io.trst_n
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dwrap.io.tck := io.tck
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dwrap.io.tms := io.tms
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dwrap.io.tdi := io.tdi
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io.tdo := dwrap.io.tdo
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io.tdoEnable := dwrap.io.tdoEnable
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dwrap.io.core_rst_n := io.core_rst_n
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dwrap.io.core_clk := io.core_clk
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dwrap.io.jtag_id := io.jtag_id
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dwrap.io.rd_data := io.rd_data
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io.reg_wr_data := dwrap.io.reg_wr_data
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io.reg_wr_addr := dwrap.io.reg_wr_addr
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io.reg_en := dwrap.io.reg_en
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io.reg_wr_en := dwrap.io.reg_wr_en
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io.dmi_hard_reset := dwrap.io.dmi_hard_reset
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}
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object dmiwrapper_main extends App{
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println("Generate Verilog")
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println((new chisel3.stage.ChiselStage).emitVerilog(new dmi_wrapper()))
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}
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