Regression so far

firrtl_black_box_resource_files.f

@@ -1 +1,3 @@
 /home/waleedbinehsan/Desktop/Quasar-master/gated_latch.v
+/home/waleedbinehsan/Desktop/Quasar-master/dmi_wrapper.sv
+/home/waleedbinehsan/Desktop/Quasar-master/mem.sv

src/main/scala/dec/dec_tlu_ctl.scala

@@ -48,18 +48,18 @@ class dec_tlu_ctl_IO extends Bundle with lib {
 	val active_clk    = Input(Clock())
 	val free_clk      = Input(Clock())
 	val scan_mode     = Input(Bool())
-	val        rst_vec         = Input(UInt(31.W))    // reset vector, from core pins
+	val rst_vec         = Input(UInt(31.W))    // reset vector, from core pins
-	val        nmi_int         = Input(UInt(1.W))    // nmi pin
+	val nmi_int         = Input(UInt(1.W))    // nmi pin
-	val        nmi_vec         = Input(UInt(31.W))    // nmi vector
+	val nmi_vec         = Input(UInt(31.W))    // nmi vector
-	val  i_cpu_halt_req        = Input(UInt(1.W))        // Asynchronous Halt request to CPU
+	val i_cpu_halt_req        = Input(UInt(1.W))        // Asynchronous Halt request to CPU
-	val  i_cpu_run_req         = Input(UInt(1.W))        // Asynchronous Restart request to CPU
+	val i_cpu_run_req         = Input(UInt(1.W))        // Asynchronous Restart request to CPU
 	val lsu_fastint_stall_any  = Input(UInt(1.W))   // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
-	val       lsu_idle_any                = Input(UInt(1.W)) // lsu is idle
+	val lsu_idle_any                = Input(UInt(1.W)) // lsu is idle
 	// perf counter inputs
-	val       dec_pmu_instr_decoded   = Input(UInt(1.W))// decoded instructions
+	val dec_pmu_instr_decoded   = Input(UInt(1.W))// decoded instructions
-	val       dec_pmu_decode_stall    = Input(UInt(1.W))// decode stall
+	val dec_pmu_decode_stall    = Input(UInt(1.W))// decode stall
-	val       dec_pmu_presync_stall   = Input(UInt(1.W))// decode stall due to presync'd inst
+	val dec_pmu_presync_stall   = Input(UInt(1.W))// decode stall due to presync'd inst
-	val       dec_pmu_postsync_stall  = Input(UInt(1.W))// decode stall due to postsync'd inst
+	val dec_pmu_postsync_stall  = Input(UInt(1.W))// decode stall due to postsync'd inst
 	val       lsu_store_stall_any     = Input(UInt(1.W))// SB or WB is full, stall decode
 	val     lsu_fir_addr           = Input(UInt(31.W)) // Fast int address
 	val     lsu_fir_error           = Input(UInt(2.W)) // Fast int lookup error

src/main/scala/include/bundle.scala

@@ -34,7 +34,6 @@ class tlu_dma extends Bundle{
 
 class dec_bp extends Bundle{
   val dec_tlu_br0_r_pkt = Flipped(Valid(new br_tlu_pkt_t))
-  //  val dec_tlu_flush_lower_wb = Input(Bool())
   val dec_tlu_flush_leak_one_wb = Input(Bool())
   val dec_tlu_bpred_disable = Input(Bool())
 }
@@ -340,7 +339,7 @@ class tlu_exu extends Bundle with lib{
   val		exu_i0_br_hist_r		  =Output(UInt(2.W))                          // to DEC  I0 branch history
   val		exu_i0_br_error_r		  =Output(UInt(1.W))                          // to DEC  I0 branch error
   val		exu_i0_br_start_error_r	=Output(UInt(1.W))                       	// to DEC  I0 branch start error
-  val		exu_i0_br_index_r		  =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W))  // to DEC  I0 branch index
+//  val		exu_i0_br_index_r		  =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W))  // to DEC  I0 branch index
   val		exu_i0_br_valid_r		  =Output(UInt(1.W))                          // to DEC  I0 branch valid
   val		exu_i0_br_mp_r			  =Output(UInt(1.W))                          // to DEC  I0 branch mispredict
   val		exu_i0_br_middle_r		=Output(UInt(1.W))                          // to DEC  I0 branch middle

src/main/scala/quasar.scala

@@ -100,8 +100,8 @@ class quasar extends Module with RequireAsyncReset with lib {
   ifu.io.ic <> io.ic
   ifu.io.iccm <> io.iccm
   ifu.io.exu_ifu.exu_bp <> exu.io.exu_bp
-  ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r
+  //ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r
-  ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r
+  //ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r
   ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
   ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt <> dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt