Updated LEC scripts
This commit is contained in:
komaljaved-lm
parent
cc61f85e64
commit
031cee8e0a
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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]
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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]
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/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/scala-2.12/sbt-1.0/classes
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# Load Configurations for LEC of Golden and Revised Design
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import re
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import re
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infile= open("./design/snapshots/default/param.vh",'r')
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infile= open("./design/snapshots/default/param.vh",'r')
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params = []
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params = []
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lines = infile.readlines()
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lines = infile.readlines() # Read Param.vh file.
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for line in lines:
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for line in lines:
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patern_1=re.match(r'(.*):(.*)' , line )
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patern_1=re.match(r'(.*):(.*)' , line )
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if ((patern_1)):
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if ((patern_1)):
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lesson_group2=patern_1.group(1)
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# Group string to the left side of colon
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splittedl = lesson_group2.split()
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patern_group1=patern_1.group(1)
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split_data=''
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split_bef_col = patern_group1.split()
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for x in splittedl:
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bef_col=''
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split_data=split_data+" "+x
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print("split_bef_col = ",split_bef_col)
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lesson_group3=patern_1.group(2)
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for parametr in split_bef_col:
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splittedl2 = lesson_group3.split()
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bef_col=bef_col+" "+parametr
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split_data2=''
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# Group string to the right side of colon
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for x in splittedl2:
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patern_group2=patern_1.group(2)
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split_data2=split_data2+" "+x
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split_after_col = patern_group2.split()
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after_col=''
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for strng in split_after_col:
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after_col=after_col+strng
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else:
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else:
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continue
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continue
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params.append(split_data+" = " + split_data2)
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# concatenate the string obtained before and after colon
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params.append(bef_col+" = " + after_col)
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#writing to a file
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# Writing configurations to file
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filename2 = "./verif/LEC/LEC_RTL/Golden_RTL/parameter.sv"
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filename2 = "./verif/LEC/LEC_RTL/Golden_RTL/parameter.sv"
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#w+ tells python we are opening the file to write into it
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outfile = open(filename2, 'w+')
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outfile = open(filename2, 'w+')
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outfile.write("#(parameter"+"\n")
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outfile.write("#(parameter"+"\n")
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outfile.write("\t"+" AWIDTH = 7,"+"\n")
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outfile.write("\t"+" AWIDTH = 7,"+"\n")
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outfile.write("\t"+" TAG = 1'h1,"+"\n")
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outfile.write("\t"+" TAG = 1'h1,"+"\n")
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for x in params:
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for parameters in params:
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if ("DCCM_INDEX_BITS") in x:
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if ("DCCM_INDEX_BITS") in parameters:
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y="// " + "DCCM_INDEX_BITS = 4'hC ,"
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commented=" //" + parameters
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outfile.write("\t"+str(y)+"\n")
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outfile.write("\t"+str(commented)+"\n")
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else:
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else:
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outfile.write("\t"+str(x)+"\n")
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outfile.write("\t"+str(parameters)+"\n")
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outfile.write(")"+"\n")
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outfile.write(")"+"\n")
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outfile.close() #Close file
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outfile.close() #Close file
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print("Done...!")
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print("\nConfiguration file for LEC is updated successfully.\n")
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# Set Search Path for Golden/Implementation Design
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# Set Search Path for Golden/Implementation Design
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set search_path "./verif/LEC ./verif/LEC/LEC_RTL/Golden_RTL ./verif/LEC/LEC_RTL/generated_rtl"
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set search_path "./verif/LEC ./verif/LEC/LEC_RTL/Golden_RTL ./verif/LEC/LEC_RTL/Imp_BB_RTL"
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# Set LEC_ROOT to presentt working directory
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# Set LEC_ROOT to presentt working directory
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set LEC_ROOT [pwd]/verif/LEC
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set LEC_ROOT [pwd]/verif/LEC
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@ -70,17 +70,17 @@ if {![file isdirectory $fm_path_r]} {
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}
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}
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# Loading verilog implementation file
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# Loading verilog implementation file
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read_sverilog -i " \
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read_sverilog -i " \
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$LEC_ROOT/LEC_RTL/BB_RTL/pkt.sv
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$LEC_ROOT/LEC_RTL/Imp_BB_RTL/pkt.sv
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$LEC_ROOT/LEC_RTL/BB_RTL/beh_lib.sv
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$LEC_ROOT/LEC_RTL/Imp_BB_RTL/beh_lib.sv
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$LEC_ROOT/LEC_RTL/BB_RTL/mem_lib.sv
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$LEC_ROOT/LEC_RTL/Imp_BB_RTL/mem_lib.sv
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$LEC_ROOT/LEC_RTL/BB_RTL/ifu_ic_mem.sv
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$LEC_ROOT/LEC_RTL/Imp_BB_RTL/ifu_ic_mem.sv
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$LEC_ROOT/LEC_RTL/BB_RTL/gated_latch.sv
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$LEC_ROOT/LEC_RTL/Imp_BB_RTL/gated_latch.sv
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$LEC_ROOT/LEC_RTL/BB_RTL/ifu_iccm_mem.sv
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$LEC_ROOT/LEC_RTL/Imp_BB_RTL/ifu_iccm_mem.sv
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$LEC_ROOT/LEC_RTL/BB_RTL/lsu_dccm_mem.sv
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$LEC_ROOT/LEC_RTL/Imp_BB_RTL/lsu_dccm_mem.sv
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$LEC_ROOT/LEC_RTL/BB_RTL/mem.sv
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$LEC_ROOT/LEC_RTL/Imp_BB_RTL/mem.sv
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$LEC_ROOT/LEC_RTL/BB_RTL/dmi_jtag_to_core_sync.sv
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$LEC_ROOT/LEC_RTL/Imp_BB_RTL/dmi_jtag_to_core_sync.sv
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$LEC_ROOT/LEC_RTL/BB_RTL/rvjtag_tap.sv
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$LEC_ROOT/LEC_RTL/Imp_BB_RTL/rvjtag_tap.sv
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$LEC_ROOT/LEC_RTL/BB_RTL/dmi_wrapper.sv
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$LEC_ROOT/LEC_RTL/Imp_BB_RTL/dmi_wrapper.sv
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./generated_rtl/quasar_wrapper.sv
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./generated_rtl/quasar_wrapper.sv
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@ -93,25 +93,25 @@ if {![file isdirectory $fm_path_r]} {
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set_black_box i:/WORK/mem_DCCM_BANK_BITS*
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set_black_box i:/WORK/mem_DCCM_BANK_BITS*
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# Setting User Match on input ports
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# Setting User Match on input ports
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source $LEC_ROOT/setup_files/Input_ports_1.3.fms
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source $LEC_ROOT/setup_files/Input_ports_2.0.fms
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# Setting User Match on output ports
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# Setting User Match on output ports
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source $LEC_ROOT/setup_files/Output_ports_1.3.fms
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source $LEC_ROOT/setup_files/Output_ports_2.0.fms
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# Setting User Match on input Black Box Pins
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# Setting User Match on input Black Box Pins
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source $LEC_ROOT/setup_files/BB_input_pins_1.3.fms
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source $LEC_ROOT/setup_files/BB_input_pins_2.0.fms
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# Setting User Match on output Black Box Pins
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# Setting User Match on output Black Box Pins
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source $LEC_ROOT/setup_files/BB_output_pins_1.3.fms
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source $LEC_ROOT/setup_files/BB_output_pins_2.0.fms
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# Setting User Match on Flip Flops
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# Setting User Match on Flip Flops
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source $LEC_ROOT/setup_files/DFF_1.3.fms
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source $LEC_ROOT/setup_files/DFF_2.0.fms
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# Setting up constants potentially constant registers
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# Setting up constants potentially constant registers
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source $LEC_ROOT/setup_files/Constant_1.3.fms
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source $LEC_ROOT/setup_files/Constant_2.0.fms
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# Setting up dont verify points
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# Setting up dont verify points
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source $LEC_ROOT/setup_files/Dont_verify_points_1.3.fms
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source $LEC_ROOT/setup_files/Dont_verify_points_2.0.fms
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if {[verify] != 1} {
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if {[verify] != 1} {
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set verification_failing_points_limit 500
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set verification_failing_points_limit 500
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