From 03acbe1229aaa6af49bc7cfb6876a9b0ff25bf8d Mon Sep 17 00:00:00 2001
From: waleed-lm <waleed.ehsan@lampromellon.com>
Date: Tue, 20 Oct 2020 10:51:36 +0500
Subject: [PATCH] Branch Predictor started

---
 el2_ifu_mem_ctl.anno.json                     |   36 +-
 el2_ifu_mem_ctl.fir                           | 2190 ++++++++++++++++-
 el2_ifu_mem_ctl.v                             |  526 +++-
 src/main/scala/ifu/el2_ifu_mem_ctl.scala      |   56 +-
 .../classes/ifu/el2_ifu_mem_ctl$$anon$1.class |  Bin 18304 -> 0 bytes
 .../classes/ifu/el2_ifu_mem_ctl.class         |  Bin 555010 -> 0 bytes
 target/scala-2.12/classes/ifu/ifu_mem$.class  |  Bin 3876 -> 0 bytes
 .../ifu/ifu_mem$delayedInit$body.class        |  Bin 736 -> 0 bytes
 target/scala-2.12/classes/ifu/ifu_mem.class   |  Bin 780 -> 0 bytes
 9 files changed, 2699 insertions(+), 109 deletions(-)
 delete mode 100644 target/scala-2.12/classes/ifu/el2_ifu_mem_ctl$$anon$1.class
 delete mode 100644 target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
 delete mode 100644 target/scala-2.12/classes/ifu/ifu_mem$.class
 delete mode 100644 target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class
 delete mode 100644 target/scala-2.12/classes/ifu/ifu_mem.class

diff --git a/el2_ifu_mem_ctl.anno.json b/el2_ifu_mem_ctl.anno.json
index bf2607a2..a63cf3de 100644
--- a/el2_ifu_mem_ctl.anno.json
+++ b/el2_ifu_mem_ctl.anno.json
@@ -7,6 +7,16 @@
       "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_write_stall",
+    "sources":[
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
@@ -59,18 +69,6 @@
       "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data"
     ]
   },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_test",
-    "sources":[
-      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_data_ecc",
-      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_core_ecc_disable",
-      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
-      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_fetch_val_f",
-      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
-      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
-    ]
-  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err",
@@ -116,6 +114,20 @@
       "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_en",
+    "sources":[
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_iccm_access_bf",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_req_bf",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_uncacheable_bf",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_force_halt",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_bp_hit_taken_f",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_wr_data",
diff --git a/el2_ifu_mem_ctl.fir b/el2_ifu_mem_ctl.fir
index ec011ff2..cc8a770e 100644
--- a/el2_ifu_mem_ctl.fir
+++ b/el2_ifu_mem_ctl.fir
@@ -48,6 +48,390 @@ circuit el2_ifu_mem_ctl :
     clkhdr.EN <= io.en @[el2_lib.scala 406:18]
     clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
     
+  extmodule TEC_RV_ICG_2 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_2 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_3 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_3 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_4 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_4 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_5 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_5 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_6 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_6 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_7 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_7 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_8 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_8 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_9 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_9 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_10 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_10 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_11 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_11 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_12 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_12 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_12 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_13 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_13 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_13 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_14 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_14 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_14 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_15 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_15 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_15 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_16 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_16 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_16 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_17 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_17 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_17 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
   module el2_ifu_mem_ctl : 
     input clock : Clock
     input reset : UInt<1>
@@ -5539,11 +5923,11 @@ circuit el2_ifu_mem_ctl :
     node iccm_corrected_ecc_f_mux = mux(_T_3845, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[el2_ifu_mem_ctl.scala 718:37]
     wire iccm_rd_ecc_single_err_ff : UInt<1>
     iccm_rd_ecc_single_err_ff <= UInt<1>("h00")
-    node _T_3846 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 720:61]
-    node _T_3847 = and(io.iccm_rd_ecc_single_err, _T_3846) @[el2_ifu_mem_ctl.scala 720:59]
-    node _T_3848 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 720:91]
-    node _T_3849 = and(_T_3847, _T_3848) @[el2_ifu_mem_ctl.scala 720:89]
-    node iccm_ecc_write_status = or(_T_3849, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 720:112]
+    node _T_3846 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 720:76]
+    node _T_3847 = and(io.iccm_rd_ecc_single_err, _T_3846) @[el2_ifu_mem_ctl.scala 720:74]
+    node _T_3848 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 720:106]
+    node _T_3849 = and(_T_3847, _T_3848) @[el2_ifu_mem_ctl.scala 720:104]
+    node iccm_ecc_write_status = or(_T_3849, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 720:127]
     node _T_3850 = or(io.iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[el2_ifu_mem_ctl.scala 721:67]
     node _T_3851 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 721:98]
     node iccm_rd_ecc_single_err_hold_in = and(_T_3850, _T_3851) @[el2_ifu_mem_ctl.scala 721:96]
@@ -5555,5 +5939,1799 @@ circuit el2_ifu_mem_ctl :
     node _T_3854 = add(iccm_rw_addr_f, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 724:102]
     node _T_3855 = tail(_T_3854, 1) @[el2_ifu_mem_ctl.scala 724:102]
     node iccm_ecc_corr_index_in = mux(_T_3853, iccm_rw_addr_f, _T_3855) @[el2_ifu_mem_ctl.scala 724:35]
-    io.test <= iccm_corrected_ecc[0] @[el2_ifu_mem_ctl.scala 725:11]
+    node _T_3856 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_mem_ctl.scala 725:67]
+    reg _T_3857 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 725:51]
+    _T_3857 <= _T_3856 @[el2_ifu_mem_ctl.scala 725:51]
+    iccm_rw_addr_f <= _T_3857 @[el2_ifu_mem_ctl.scala 725:18]
+    reg _T_3858 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 726:62]
+    _T_3858 <= iccm_rd_ecc_single_err_hold_in @[el2_ifu_mem_ctl.scala 726:62]
+    iccm_rd_ecc_single_err_ff <= _T_3858 @[el2_ifu_mem_ctl.scala 726:29]
+    node _T_3859 = cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux) @[Cat.scala 29:58]
+    node _T_3860 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 727:152]
+    reg _T_3861 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3860 : @[Reg.scala 28:19]
+      _T_3861 <= _T_3859 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    iccm_ecc_corr_data_ff <= _T_3861 @[el2_ifu_mem_ctl.scala 727:25]
+    node _T_3862 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 728:119]
+    reg _T_3863 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3862 : @[Reg.scala 28:19]
+      _T_3863 <= iccm_ecc_corr_index_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    iccm_ecc_corr_index_ff <= _T_3863 @[el2_ifu_mem_ctl.scala 728:26]
+    node _T_3864 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 729:41]
+    node _T_3865 = and(io.ifc_fetch_req_bf, _T_3864) @[el2_ifu_mem_ctl.scala 729:39]
+    node _T_3866 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 729:72]
+    node _T_3867 = and(_T_3865, _T_3866) @[el2_ifu_mem_ctl.scala 729:70]
+    node _T_3868 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 730:19]
+    node _T_3869 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 730:34]
+    node _T_3870 = and(_T_3868, _T_3869) @[el2_ifu_mem_ctl.scala 730:32]
+    node _T_3871 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 731:19]
+    node _T_3872 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 731:39]
+    node _T_3873 = and(_T_3871, _T_3872) @[el2_ifu_mem_ctl.scala 731:37]
+    node _T_3874 = or(_T_3870, _T_3873) @[el2_ifu_mem_ctl.scala 730:88]
+    node _T_3875 = eq(miss_state, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 732:19]
+    node _T_3876 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 732:43]
+    node _T_3877 = and(_T_3875, _T_3876) @[el2_ifu_mem_ctl.scala 732:41]
+    node _T_3878 = or(_T_3874, _T_3877) @[el2_ifu_mem_ctl.scala 731:88]
+    node _T_3879 = eq(miss_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 733:19]
+    node _T_3880 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 733:37]
+    node _T_3881 = and(_T_3879, _T_3880) @[el2_ifu_mem_ctl.scala 733:35]
+    node _T_3882 = or(_T_3878, _T_3881) @[el2_ifu_mem_ctl.scala 732:88]
+    node _T_3883 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 734:19]
+    node _T_3884 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 734:40]
+    node _T_3885 = and(_T_3883, _T_3884) @[el2_ifu_mem_ctl.scala 734:38]
+    node _T_3886 = or(_T_3882, _T_3885) @[el2_ifu_mem_ctl.scala 733:88]
+    node _T_3887 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 735:19]
+    node _T_3888 = and(_T_3887, miss_state_en) @[el2_ifu_mem_ctl.scala 735:37]
+    node _T_3889 = eq(miss_nxtstate, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 735:71]
+    node _T_3890 = and(_T_3888, _T_3889) @[el2_ifu_mem_ctl.scala 735:54]
+    node _T_3891 = or(_T_3886, _T_3890) @[el2_ifu_mem_ctl.scala 734:57]
+    node _T_3892 = eq(_T_3891, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 730:5]
+    node _T_3893 = and(_T_3867, _T_3892) @[el2_ifu_mem_ctl.scala 729:96]
+    node _T_3894 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 736:28]
+    node _T_3895 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 736:52]
+    node _T_3896 = and(_T_3894, _T_3895) @[el2_ifu_mem_ctl.scala 736:50]
+    node _T_3897 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 736:83]
+    node _T_3898 = and(_T_3896, _T_3897) @[el2_ifu_mem_ctl.scala 736:81]
+    node _T_3899 = or(_T_3893, _T_3898) @[el2_ifu_mem_ctl.scala 735:93]
+    io.ic_rd_en <= _T_3899 @[el2_ifu_mem_ctl.scala 729:15]
+    wire bus_ic_wr_en : UInt<1>
+    bus_ic_wr_en <= UInt<1>("h00")
+    node _T_3900 = bits(write_ic_16_bytes, 0, 0) @[Bitwise.scala 72:15]
+    node _T_3901 = mux(_T_3900, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_3902 = and(bus_ic_wr_en, _T_3901) @[el2_ifu_mem_ctl.scala 738:31]
+    io.ic_wr_en <= _T_3902 @[el2_ifu_mem_ctl.scala 738:15]
+    node _T_3903 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 739:59]
+    node _T_3904 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 739:91]
+    node _T_3905 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 739:127]
+    node _T_3906 = or(_T_3905, stream_eol_f) @[el2_ifu_mem_ctl.scala 739:151]
+    node _T_3907 = eq(_T_3906, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:106]
+    node _T_3908 = and(_T_3904, _T_3907) @[el2_ifu_mem_ctl.scala 739:104]
+    node _T_3909 = or(_T_3903, _T_3908) @[el2_ifu_mem_ctl.scala 739:77]
+    node _T_3910 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 739:191]
+    node _T_3911 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:205]
+    node _T_3912 = and(_T_3910, _T_3911) @[el2_ifu_mem_ctl.scala 739:203]
+    node _T_3913 = eq(_T_3912, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:172]
+    node _T_3914 = and(_T_3909, _T_3913) @[el2_ifu_mem_ctl.scala 739:170]
+    node _T_3915 = eq(_T_3914, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 739:44]
+    node _T_3916 = and(write_ic_16_bytes, _T_3915) @[el2_ifu_mem_ctl.scala 739:42]
+    io.ic_write_stall <= _T_3916 @[el2_ifu_mem_ctl.scala 739:21]
+    reg _T_3917 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 740:53]
+    _T_3917 <= io.dec_tlu_fence_i_wb @[el2_ifu_mem_ctl.scala 740:53]
+    reset_all_tags <= _T_3917 @[el2_ifu_mem_ctl.scala 740:18]
+    node _T_3918 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:18]
+    node _T_3919 = or(reset_ic_in, reset_ic_ff) @[el2_ifu_mem_ctl.scala 741:62]
+    node _T_3920 = eq(_T_3919, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:48]
+    node _T_3921 = and(_T_3918, _T_3920) @[el2_ifu_mem_ctl.scala 741:46]
+    node _T_3922 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:79]
+    node ic_valid = and(_T_3921, _T_3922) @[el2_ifu_mem_ctl.scala 741:77]
+    node _T_3923 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 742:59]
+    node _T_3924 = and(_T_3923, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 742:81]
+    node _T_3925 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 742:122]
+    node _T_3926 = bits(ifu_status_wr_addr, 11, 5) @[el2_ifu_mem_ctl.scala 743:23]
+    node ifu_status_wr_addr_w_debug = mux(_T_3924, _T_3925, _T_3926) @[el2_ifu_mem_ctl.scala 742:39]
+    reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 744:61]
+    ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[el2_ifu_mem_ctl.scala 744:61]
+    wire way_status_wr_en : UInt<1>
+    way_status_wr_en <= UInt<1>("h00")
+    node _T_3927 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 746:73]
+    node way_status_wr_en_w_debug = or(way_status_wr_en, _T_3927) @[el2_ifu_mem_ctl.scala 746:51]
+    reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 747:59]
+    way_status_wr_en_ff <= way_status_wr_en_w_debug @[el2_ifu_mem_ctl.scala 747:59]
+    wire way_status_new : UInt<1>
+    way_status_new <= UInt<1>("h00")
+    node _T_3928 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 749:54]
+    node _T_3929 = bits(io.ic_debug_wr_data, 4, 4) @[el2_ifu_mem_ctl.scala 750:55]
+    node _T_3930 = bits(io.ic_debug_wr_data, 6, 4) @[el2_ifu_mem_ctl.scala 750:79]
+    node _T_3931 = mux(UInt<1>("h01"), _T_3929, _T_3930) @[el2_ifu_mem_ctl.scala 750:8]
+    node way_status_new_w_debug = mux(_T_3928, _T_3931, way_status_new) @[el2_ifu_mem_ctl.scala 749:35]
+    reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 751:57]
+    way_status_new_ff <= way_status_new_w_debug @[el2_ifu_mem_ctl.scala 751:57]
+    node _T_3932 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_0 = eq(_T_3932, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3933 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_1 = eq(_T_3933, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3934 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_2 = eq(_T_3934, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3935 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_3 = eq(_T_3935, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3936 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_4 = eq(_T_3936, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3937 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_5 = eq(_T_3937, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3938 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_6 = eq(_T_3938, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3939 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_7 = eq(_T_3939, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3940 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_8 = eq(_T_3940, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3941 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_9 = eq(_T_3941, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3942 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_10 = eq(_T_3942, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3943 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_11 = eq(_T_3943, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3944 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_12 = eq(_T_3944, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3945 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_13 = eq(_T_3945, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3946 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_14 = eq(_T_3946, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 752:122]
+    node _T_3947 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 752:83]
+    node way_status_clken_15 = eq(_T_3947, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 752:122]
+    inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 412:22]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_2.io.en <= way_status_clken_0 @[el2_lib.scala 414:16]
+    rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 412:22]
+    rvclkhdr_3.clock <= clock
+    rvclkhdr_3.reset <= reset
+    rvclkhdr_3.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_3.io.en <= way_status_clken_1 @[el2_lib.scala 414:16]
+    rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 412:22]
+    rvclkhdr_4.clock <= clock
+    rvclkhdr_4.reset <= reset
+    rvclkhdr_4.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_4.io.en <= way_status_clken_2 @[el2_lib.scala 414:16]
+    rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 412:22]
+    rvclkhdr_5.clock <= clock
+    rvclkhdr_5.reset <= reset
+    rvclkhdr_5.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_5.io.en <= way_status_clken_3 @[el2_lib.scala 414:16]
+    rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 412:22]
+    rvclkhdr_6.clock <= clock
+    rvclkhdr_6.reset <= reset
+    rvclkhdr_6.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_6.io.en <= way_status_clken_4 @[el2_lib.scala 414:16]
+    rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 412:22]
+    rvclkhdr_7.clock <= clock
+    rvclkhdr_7.reset <= reset
+    rvclkhdr_7.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_7.io.en <= way_status_clken_5 @[el2_lib.scala 414:16]
+    rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 412:22]
+    rvclkhdr_8.clock <= clock
+    rvclkhdr_8.reset <= reset
+    rvclkhdr_8.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_8.io.en <= way_status_clken_6 @[el2_lib.scala 414:16]
+    rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 412:22]
+    rvclkhdr_9.clock <= clock
+    rvclkhdr_9.reset <= reset
+    rvclkhdr_9.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_9.io.en <= way_status_clken_7 @[el2_lib.scala 414:16]
+    rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 412:22]
+    rvclkhdr_10.clock <= clock
+    rvclkhdr_10.reset <= reset
+    rvclkhdr_10.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_10.io.en <= way_status_clken_8 @[el2_lib.scala 414:16]
+    rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 412:22]
+    rvclkhdr_11.clock <= clock
+    rvclkhdr_11.reset <= reset
+    rvclkhdr_11.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_11.io.en <= way_status_clken_9 @[el2_lib.scala 414:16]
+    rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 412:22]
+    rvclkhdr_12.clock <= clock
+    rvclkhdr_12.reset <= reset
+    rvclkhdr_12.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_12.io.en <= way_status_clken_10 @[el2_lib.scala 414:16]
+    rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 412:22]
+    rvclkhdr_13.clock <= clock
+    rvclkhdr_13.reset <= reset
+    rvclkhdr_13.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_13.io.en <= way_status_clken_11 @[el2_lib.scala 414:16]
+    rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 412:22]
+    rvclkhdr_14.clock <= clock
+    rvclkhdr_14.reset <= reset
+    rvclkhdr_14.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_14.io.en <= way_status_clken_12 @[el2_lib.scala 414:16]
+    rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 412:22]
+    rvclkhdr_15.clock <= clock
+    rvclkhdr_15.reset <= reset
+    rvclkhdr_15.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_15.io.en <= way_status_clken_13 @[el2_lib.scala 414:16]
+    rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 412:22]
+    rvclkhdr_16.clock <= clock
+    rvclkhdr_16.reset <= reset
+    rvclkhdr_16.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_16.io.en <= way_status_clken_14 @[el2_lib.scala 414:16]
+    rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 412:22]
+    rvclkhdr_17.clock <= clock
+    rvclkhdr_17.reset <= reset
+    rvclkhdr_17.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_17.io.en <= way_status_clken_15 @[el2_lib.scala 414:16]
+    rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    wire way_status_out : UInt<1>[128] @[el2_ifu_mem_ctl.scala 754:28]
+    node _T_3948 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3949 = and(_T_3948, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3950 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3949 : @[Reg.scala 28:19]
+      _T_3950 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[0] <= _T_3950 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3951 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3952 = and(_T_3951, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3953 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3952 : @[Reg.scala 28:19]
+      _T_3953 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[1] <= _T_3953 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3954 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3955 = and(_T_3954, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3956 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3955 : @[Reg.scala 28:19]
+      _T_3956 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[2] <= _T_3956 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3957 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3958 = and(_T_3957, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3959 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3958 : @[Reg.scala 28:19]
+      _T_3959 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[3] <= _T_3959 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3960 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3961 = and(_T_3960, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3962 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3961 : @[Reg.scala 28:19]
+      _T_3962 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[4] <= _T_3962 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3963 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3964 = and(_T_3963, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3965 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3964 : @[Reg.scala 28:19]
+      _T_3965 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[5] <= _T_3965 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3966 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3967 = and(_T_3966, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3968 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3967 : @[Reg.scala 28:19]
+      _T_3968 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[6] <= _T_3968 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3969 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3970 = and(_T_3969, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3971 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3970 : @[Reg.scala 28:19]
+      _T_3971 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[7] <= _T_3971 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3972 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3973 = and(_T_3972, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3974 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3973 : @[Reg.scala 28:19]
+      _T_3974 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[8] <= _T_3974 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3975 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3976 = and(_T_3975, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3977 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3976 : @[Reg.scala 28:19]
+      _T_3977 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[9] <= _T_3977 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3978 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3979 = and(_T_3978, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3980 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3979 : @[Reg.scala 28:19]
+      _T_3980 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[10] <= _T_3980 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3981 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3982 = and(_T_3981, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3983 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3982 : @[Reg.scala 28:19]
+      _T_3983 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[11] <= _T_3983 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3984 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3985 = and(_T_3984, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3986 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3985 : @[Reg.scala 28:19]
+      _T_3986 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[12] <= _T_3986 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3987 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3988 = and(_T_3987, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3989 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3988 : @[Reg.scala 28:19]
+      _T_3989 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[13] <= _T_3989 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3990 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3991 = and(_T_3990, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3992 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3991 : @[Reg.scala 28:19]
+      _T_3992 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[14] <= _T_3992 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3993 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3994 = and(_T_3993, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3995 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3994 : @[Reg.scala 28:19]
+      _T_3995 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[15] <= _T_3995 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3996 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_3997 = and(_T_3996, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_3998 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3997 : @[Reg.scala 28:19]
+      _T_3998 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[16] <= _T_3998 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_3999 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4000 = and(_T_3999, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4001 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4000 : @[Reg.scala 28:19]
+      _T_4001 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[17] <= _T_4001 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4002 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4003 = and(_T_4002, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4004 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4003 : @[Reg.scala 28:19]
+      _T_4004 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[18] <= _T_4004 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4005 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4006 = and(_T_4005, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4007 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4006 : @[Reg.scala 28:19]
+      _T_4007 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[19] <= _T_4007 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4008 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4009 = and(_T_4008, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4010 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4009 : @[Reg.scala 28:19]
+      _T_4010 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[20] <= _T_4010 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4011 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4012 = and(_T_4011, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4013 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4012 : @[Reg.scala 28:19]
+      _T_4013 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[21] <= _T_4013 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4014 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4015 = and(_T_4014, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4016 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4015 : @[Reg.scala 28:19]
+      _T_4016 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[22] <= _T_4016 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4017 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4018 = and(_T_4017, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4019 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4018 : @[Reg.scala 28:19]
+      _T_4019 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[23] <= _T_4019 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4020 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4021 = and(_T_4020, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4022 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4021 : @[Reg.scala 28:19]
+      _T_4022 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[24] <= _T_4022 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4023 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4024 = and(_T_4023, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4025 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4024 : @[Reg.scala 28:19]
+      _T_4025 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[25] <= _T_4025 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4026 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4027 = and(_T_4026, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4028 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4027 : @[Reg.scala 28:19]
+      _T_4028 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[26] <= _T_4028 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4029 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4030 = and(_T_4029, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4031 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4030 : @[Reg.scala 28:19]
+      _T_4031 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[27] <= _T_4031 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4032 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4033 = and(_T_4032, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4034 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4033 : @[Reg.scala 28:19]
+      _T_4034 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[28] <= _T_4034 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4035 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4036 = and(_T_4035, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4037 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4036 : @[Reg.scala 28:19]
+      _T_4037 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[29] <= _T_4037 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4038 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4039 = and(_T_4038, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4040 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4039 : @[Reg.scala 28:19]
+      _T_4040 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[30] <= _T_4040 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4041 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4042 = and(_T_4041, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4043 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4042 : @[Reg.scala 28:19]
+      _T_4043 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[31] <= _T_4043 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4044 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4045 = and(_T_4044, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4046 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4045 : @[Reg.scala 28:19]
+      _T_4046 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[32] <= _T_4046 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4047 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4048 = and(_T_4047, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4049 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4048 : @[Reg.scala 28:19]
+      _T_4049 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[33] <= _T_4049 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4050 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4051 = and(_T_4050, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4052 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4051 : @[Reg.scala 28:19]
+      _T_4052 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[34] <= _T_4052 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4053 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4054 = and(_T_4053, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4055 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4054 : @[Reg.scala 28:19]
+      _T_4055 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[35] <= _T_4055 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4056 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4057 = and(_T_4056, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4058 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4057 : @[Reg.scala 28:19]
+      _T_4058 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[36] <= _T_4058 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4059 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4060 = and(_T_4059, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4061 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4060 : @[Reg.scala 28:19]
+      _T_4061 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[37] <= _T_4061 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4062 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4063 = and(_T_4062, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4064 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4063 : @[Reg.scala 28:19]
+      _T_4064 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[38] <= _T_4064 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4065 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4066 = and(_T_4065, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4067 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4066 : @[Reg.scala 28:19]
+      _T_4067 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[39] <= _T_4067 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4068 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4069 = and(_T_4068, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4070 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4069 : @[Reg.scala 28:19]
+      _T_4070 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[40] <= _T_4070 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4071 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4072 = and(_T_4071, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4073 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4072 : @[Reg.scala 28:19]
+      _T_4073 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[41] <= _T_4073 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4074 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4075 = and(_T_4074, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4076 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4075 : @[Reg.scala 28:19]
+      _T_4076 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[42] <= _T_4076 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4077 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4078 = and(_T_4077, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4079 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4078 : @[Reg.scala 28:19]
+      _T_4079 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[43] <= _T_4079 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4080 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4081 = and(_T_4080, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4082 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4081 : @[Reg.scala 28:19]
+      _T_4082 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[44] <= _T_4082 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4083 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4084 = and(_T_4083, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4085 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4084 : @[Reg.scala 28:19]
+      _T_4085 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[45] <= _T_4085 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4086 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4087 = and(_T_4086, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4088 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4087 : @[Reg.scala 28:19]
+      _T_4088 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[46] <= _T_4088 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4089 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4090 = and(_T_4089, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4091 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4090 : @[Reg.scala 28:19]
+      _T_4091 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[47] <= _T_4091 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4092 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4093 = and(_T_4092, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4094 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4093 : @[Reg.scala 28:19]
+      _T_4094 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[48] <= _T_4094 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4095 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4096 = and(_T_4095, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4097 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4096 : @[Reg.scala 28:19]
+      _T_4097 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[49] <= _T_4097 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4098 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4099 = and(_T_4098, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4100 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4099 : @[Reg.scala 28:19]
+      _T_4100 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[50] <= _T_4100 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4101 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4102 = and(_T_4101, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4103 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4102 : @[Reg.scala 28:19]
+      _T_4103 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[51] <= _T_4103 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4104 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4105 = and(_T_4104, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4106 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4105 : @[Reg.scala 28:19]
+      _T_4106 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[52] <= _T_4106 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4107 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4108 = and(_T_4107, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4109 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4108 : @[Reg.scala 28:19]
+      _T_4109 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[53] <= _T_4109 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4110 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4111 = and(_T_4110, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4112 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4111 : @[Reg.scala 28:19]
+      _T_4112 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[54] <= _T_4112 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4113 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4114 = and(_T_4113, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4115 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4114 : @[Reg.scala 28:19]
+      _T_4115 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[55] <= _T_4115 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4116 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4117 = and(_T_4116, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4118 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4117 : @[Reg.scala 28:19]
+      _T_4118 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[56] <= _T_4118 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4119 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4120 = and(_T_4119, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4121 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4120 : @[Reg.scala 28:19]
+      _T_4121 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[57] <= _T_4121 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4122 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4123 = and(_T_4122, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4124 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4123 : @[Reg.scala 28:19]
+      _T_4124 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[58] <= _T_4124 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4125 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4126 = and(_T_4125, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4127 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4126 : @[Reg.scala 28:19]
+      _T_4127 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[59] <= _T_4127 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4128 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4129 = and(_T_4128, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4130 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4129 : @[Reg.scala 28:19]
+      _T_4130 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[60] <= _T_4130 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4131 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4132 = and(_T_4131, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4133 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4132 : @[Reg.scala 28:19]
+      _T_4133 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[61] <= _T_4133 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4134 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4135 = and(_T_4134, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4136 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4135 : @[Reg.scala 28:19]
+      _T_4136 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[62] <= _T_4136 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4137 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4138 = and(_T_4137, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4139 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4138 : @[Reg.scala 28:19]
+      _T_4139 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[63] <= _T_4139 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4140 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4141 = and(_T_4140, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4142 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4141 : @[Reg.scala 28:19]
+      _T_4142 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[64] <= _T_4142 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4143 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4144 = and(_T_4143, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4145 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4144 : @[Reg.scala 28:19]
+      _T_4145 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[65] <= _T_4145 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4146 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4147 = and(_T_4146, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4148 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4147 : @[Reg.scala 28:19]
+      _T_4148 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[66] <= _T_4148 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4149 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4150 = and(_T_4149, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4151 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4150 : @[Reg.scala 28:19]
+      _T_4151 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[67] <= _T_4151 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4152 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4153 = and(_T_4152, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4154 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4153 : @[Reg.scala 28:19]
+      _T_4154 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[68] <= _T_4154 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4155 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4156 = and(_T_4155, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4157 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4156 : @[Reg.scala 28:19]
+      _T_4157 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[69] <= _T_4157 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4158 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4159 = and(_T_4158, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4160 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4159 : @[Reg.scala 28:19]
+      _T_4160 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[70] <= _T_4160 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4161 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4162 = and(_T_4161, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4163 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4162 : @[Reg.scala 28:19]
+      _T_4163 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[71] <= _T_4163 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4164 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4165 = and(_T_4164, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4166 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4165 : @[Reg.scala 28:19]
+      _T_4166 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[72] <= _T_4166 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4167 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4168 = and(_T_4167, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4169 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4168 : @[Reg.scala 28:19]
+      _T_4169 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[73] <= _T_4169 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4170 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4171 = and(_T_4170, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4172 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4171 : @[Reg.scala 28:19]
+      _T_4172 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[74] <= _T_4172 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4173 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4174 = and(_T_4173, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4175 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4174 : @[Reg.scala 28:19]
+      _T_4175 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[75] <= _T_4175 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4176 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4177 = and(_T_4176, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4178 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4177 : @[Reg.scala 28:19]
+      _T_4178 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[76] <= _T_4178 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4179 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4180 = and(_T_4179, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4181 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4180 : @[Reg.scala 28:19]
+      _T_4181 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[77] <= _T_4181 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4182 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4183 = and(_T_4182, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4184 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4183 : @[Reg.scala 28:19]
+      _T_4184 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[78] <= _T_4184 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4185 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4186 = and(_T_4185, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4187 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4186 : @[Reg.scala 28:19]
+      _T_4187 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[79] <= _T_4187 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4188 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4189 = and(_T_4188, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4190 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4189 : @[Reg.scala 28:19]
+      _T_4190 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[80] <= _T_4190 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4191 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4192 = and(_T_4191, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4193 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4192 : @[Reg.scala 28:19]
+      _T_4193 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[81] <= _T_4193 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4194 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4195 = and(_T_4194, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4196 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4195 : @[Reg.scala 28:19]
+      _T_4196 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[82] <= _T_4196 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4197 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4198 = and(_T_4197, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4199 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4198 : @[Reg.scala 28:19]
+      _T_4199 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[83] <= _T_4199 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4200 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4201 = and(_T_4200, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4202 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4201 : @[Reg.scala 28:19]
+      _T_4202 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[84] <= _T_4202 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4203 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4204 = and(_T_4203, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4205 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4204 : @[Reg.scala 28:19]
+      _T_4205 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[85] <= _T_4205 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4206 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4207 = and(_T_4206, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4208 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4207 : @[Reg.scala 28:19]
+      _T_4208 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[86] <= _T_4208 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4209 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4210 = and(_T_4209, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4211 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4210 : @[Reg.scala 28:19]
+      _T_4211 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[87] <= _T_4211 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4212 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4213 = and(_T_4212, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4214 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4213 : @[Reg.scala 28:19]
+      _T_4214 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[88] <= _T_4214 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4215 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4216 = and(_T_4215, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4217 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4216 : @[Reg.scala 28:19]
+      _T_4217 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[89] <= _T_4217 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4218 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4219 = and(_T_4218, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4220 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4219 : @[Reg.scala 28:19]
+      _T_4220 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[90] <= _T_4220 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4221 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4222 = and(_T_4221, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4223 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4222 : @[Reg.scala 28:19]
+      _T_4223 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[91] <= _T_4223 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4224 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4225 = and(_T_4224, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4226 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4225 : @[Reg.scala 28:19]
+      _T_4226 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[92] <= _T_4226 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4227 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4228 = and(_T_4227, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4229 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4228 : @[Reg.scala 28:19]
+      _T_4229 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[93] <= _T_4229 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4230 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4231 = and(_T_4230, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4232 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4231 : @[Reg.scala 28:19]
+      _T_4232 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[94] <= _T_4232 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4233 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4234 = and(_T_4233, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4235 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4234 : @[Reg.scala 28:19]
+      _T_4235 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[95] <= _T_4235 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4236 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4237 = and(_T_4236, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4238 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4237 : @[Reg.scala 28:19]
+      _T_4238 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[96] <= _T_4238 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4239 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4240 = and(_T_4239, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4241 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4240 : @[Reg.scala 28:19]
+      _T_4241 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[97] <= _T_4241 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4242 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4243 = and(_T_4242, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4244 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4243 : @[Reg.scala 28:19]
+      _T_4244 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[98] <= _T_4244 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4245 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4246 = and(_T_4245, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4247 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4246 : @[Reg.scala 28:19]
+      _T_4247 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[99] <= _T_4247 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4248 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4249 = and(_T_4248, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4250 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4249 : @[Reg.scala 28:19]
+      _T_4250 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[100] <= _T_4250 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4251 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4252 = and(_T_4251, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4253 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4252 : @[Reg.scala 28:19]
+      _T_4253 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[101] <= _T_4253 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4254 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4255 = and(_T_4254, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4256 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4255 : @[Reg.scala 28:19]
+      _T_4256 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[102] <= _T_4256 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4257 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4258 = and(_T_4257, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4259 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4258 : @[Reg.scala 28:19]
+      _T_4259 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[103] <= _T_4259 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4260 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4261 = and(_T_4260, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4262 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4261 : @[Reg.scala 28:19]
+      _T_4262 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[104] <= _T_4262 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4263 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4264 = and(_T_4263, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4265 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4264 : @[Reg.scala 28:19]
+      _T_4265 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[105] <= _T_4265 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4266 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4267 = and(_T_4266, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4268 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4267 : @[Reg.scala 28:19]
+      _T_4268 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[106] <= _T_4268 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4269 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4270 = and(_T_4269, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4271 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4270 : @[Reg.scala 28:19]
+      _T_4271 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[107] <= _T_4271 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4272 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4273 = and(_T_4272, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4274 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4273 : @[Reg.scala 28:19]
+      _T_4274 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[108] <= _T_4274 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4275 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4276 = and(_T_4275, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4277 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4276 : @[Reg.scala 28:19]
+      _T_4277 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[109] <= _T_4277 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4278 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4279 = and(_T_4278, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4280 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4279 : @[Reg.scala 28:19]
+      _T_4280 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[110] <= _T_4280 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4281 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4282 = and(_T_4281, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4283 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4282 : @[Reg.scala 28:19]
+      _T_4283 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[111] <= _T_4283 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4284 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4285 = and(_T_4284, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4286 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4285 : @[Reg.scala 28:19]
+      _T_4286 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[112] <= _T_4286 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4287 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4288 = and(_T_4287, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4289 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4288 : @[Reg.scala 28:19]
+      _T_4289 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[113] <= _T_4289 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4290 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4291 = and(_T_4290, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4292 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4291 : @[Reg.scala 28:19]
+      _T_4292 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[114] <= _T_4292 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4293 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4294 = and(_T_4293, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4295 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4294 : @[Reg.scala 28:19]
+      _T_4295 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[115] <= _T_4295 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4296 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4297 = and(_T_4296, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4298 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4297 : @[Reg.scala 28:19]
+      _T_4298 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[116] <= _T_4298 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4299 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4300 = and(_T_4299, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4301 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4300 : @[Reg.scala 28:19]
+      _T_4301 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[117] <= _T_4301 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4302 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4303 = and(_T_4302, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4304 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4303 : @[Reg.scala 28:19]
+      _T_4304 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[118] <= _T_4304 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4305 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4306 = and(_T_4305, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4307 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4306 : @[Reg.scala 28:19]
+      _T_4307 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[119] <= _T_4307 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4308 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4309 = and(_T_4308, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4310 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4309 : @[Reg.scala 28:19]
+      _T_4310 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[120] <= _T_4310 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4311 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4312 = and(_T_4311, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4313 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4312 : @[Reg.scala 28:19]
+      _T_4313 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[121] <= _T_4313 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4314 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4315 = and(_T_4314, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4316 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4315 : @[Reg.scala 28:19]
+      _T_4316 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[122] <= _T_4316 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4317 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4318 = and(_T_4317, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4319 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4318 : @[Reg.scala 28:19]
+      _T_4319 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[123] <= _T_4319 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4320 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4321 = and(_T_4320, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4322 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4321 : @[Reg.scala 28:19]
+      _T_4322 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[124] <= _T_4322 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4323 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4324 = and(_T_4323, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4325 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4324 : @[Reg.scala 28:19]
+      _T_4325 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[125] <= _T_4325 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4326 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4327 = and(_T_4326, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4328 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4327 : @[Reg.scala 28:19]
+      _T_4328 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[126] <= _T_4328 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4329 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 756:112]
+    node _T_4330 = and(_T_4329, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 756:119]
+    reg _T_4331 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4330 : @[Reg.scala 28:19]
+      _T_4331 <= way_status_new_ff @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    way_status_out[127] <= _T_4331 @[el2_ifu_mem_ctl.scala 756:25]
+    node _T_4332 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4333 = bits(_T_4332, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4334 = mux(_T_4333, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4335 = and(_T_4334, way_status_out[0]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4336 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4337 = bits(_T_4336, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4338 = mux(_T_4337, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4339 = and(_T_4338, way_status_out[1]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4340 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4341 = bits(_T_4340, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4342 = mux(_T_4341, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4343 = and(_T_4342, way_status_out[2]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4344 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4345 = bits(_T_4344, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4346 = mux(_T_4345, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4347 = and(_T_4346, way_status_out[3]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4348 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4349 = bits(_T_4348, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4350 = mux(_T_4349, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4351 = and(_T_4350, way_status_out[4]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4352 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4353 = bits(_T_4352, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4354 = mux(_T_4353, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4355 = and(_T_4354, way_status_out[5]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4356 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4357 = bits(_T_4356, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4358 = mux(_T_4357, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4359 = and(_T_4358, way_status_out[6]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4360 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4361 = bits(_T_4360, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4362 = mux(_T_4361, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4363 = and(_T_4362, way_status_out[7]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4364 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4365 = bits(_T_4364, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4366 = mux(_T_4365, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4367 = and(_T_4366, way_status_out[8]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4368 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4369 = bits(_T_4368, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4370 = mux(_T_4369, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4371 = and(_T_4370, way_status_out[9]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4372 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4373 = bits(_T_4372, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4374 = mux(_T_4373, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4375 = and(_T_4374, way_status_out[10]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4376 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4377 = bits(_T_4376, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4378 = mux(_T_4377, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4379 = and(_T_4378, way_status_out[11]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4380 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4381 = bits(_T_4380, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4382 = mux(_T_4381, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4383 = and(_T_4382, way_status_out[12]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4384 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4385 = bits(_T_4384, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4386 = mux(_T_4385, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4387 = and(_T_4386, way_status_out[13]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4388 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4389 = bits(_T_4388, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4390 = mux(_T_4389, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4391 = and(_T_4390, way_status_out[14]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4392 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4393 = bits(_T_4392, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4394 = mux(_T_4393, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4395 = and(_T_4394, way_status_out[15]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4396 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4397 = bits(_T_4396, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4398 = mux(_T_4397, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4399 = and(_T_4398, way_status_out[16]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4400 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4401 = bits(_T_4400, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4402 = mux(_T_4401, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4403 = and(_T_4402, way_status_out[17]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4404 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4405 = bits(_T_4404, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4406 = mux(_T_4405, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4407 = and(_T_4406, way_status_out[18]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4408 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4409 = bits(_T_4408, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4410 = mux(_T_4409, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4411 = and(_T_4410, way_status_out[19]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4412 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4413 = bits(_T_4412, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4414 = mux(_T_4413, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4415 = and(_T_4414, way_status_out[20]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4416 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4417 = bits(_T_4416, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4418 = mux(_T_4417, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4419 = and(_T_4418, way_status_out[21]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4420 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4421 = bits(_T_4420, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4422 = mux(_T_4421, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4423 = and(_T_4422, way_status_out[22]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4424 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4425 = bits(_T_4424, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4426 = mux(_T_4425, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4427 = and(_T_4426, way_status_out[23]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4428 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4429 = bits(_T_4428, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4430 = mux(_T_4429, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4431 = and(_T_4430, way_status_out[24]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4432 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4433 = bits(_T_4432, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4434 = mux(_T_4433, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4435 = and(_T_4434, way_status_out[25]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4436 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4437 = bits(_T_4436, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4438 = mux(_T_4437, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4439 = and(_T_4438, way_status_out[26]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4440 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4441 = bits(_T_4440, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4442 = mux(_T_4441, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4443 = and(_T_4442, way_status_out[27]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4444 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4445 = bits(_T_4444, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4446 = mux(_T_4445, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4447 = and(_T_4446, way_status_out[28]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4448 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4449 = bits(_T_4448, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4450 = mux(_T_4449, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4451 = and(_T_4450, way_status_out[29]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4452 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4453 = bits(_T_4452, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4454 = mux(_T_4453, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4455 = and(_T_4454, way_status_out[30]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4456 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4457 = bits(_T_4456, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4458 = mux(_T_4457, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4459 = and(_T_4458, way_status_out[31]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4460 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4461 = bits(_T_4460, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4462 = mux(_T_4461, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4463 = and(_T_4462, way_status_out[32]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4464 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4465 = bits(_T_4464, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4466 = mux(_T_4465, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4467 = and(_T_4466, way_status_out[33]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4468 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4469 = bits(_T_4468, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4470 = mux(_T_4469, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4471 = and(_T_4470, way_status_out[34]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4472 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4473 = bits(_T_4472, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4474 = mux(_T_4473, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4475 = and(_T_4474, way_status_out[35]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4476 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4477 = bits(_T_4476, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4478 = mux(_T_4477, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4479 = and(_T_4478, way_status_out[36]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4480 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4481 = bits(_T_4480, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4482 = mux(_T_4481, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4483 = and(_T_4482, way_status_out[37]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4484 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4485 = bits(_T_4484, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4486 = mux(_T_4485, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4487 = and(_T_4486, way_status_out[38]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4488 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4489 = bits(_T_4488, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4490 = mux(_T_4489, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4491 = and(_T_4490, way_status_out[39]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4492 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4493 = bits(_T_4492, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4494 = mux(_T_4493, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4495 = and(_T_4494, way_status_out[40]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4496 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4497 = bits(_T_4496, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4498 = mux(_T_4497, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4499 = and(_T_4498, way_status_out[41]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4500 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4501 = bits(_T_4500, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4502 = mux(_T_4501, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4503 = and(_T_4502, way_status_out[42]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4504 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4505 = bits(_T_4504, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4506 = mux(_T_4505, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4507 = and(_T_4506, way_status_out[43]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4508 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4509 = bits(_T_4508, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4510 = mux(_T_4509, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4511 = and(_T_4510, way_status_out[44]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4512 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4513 = bits(_T_4512, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4514 = mux(_T_4513, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4515 = and(_T_4514, way_status_out[45]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4516 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4517 = bits(_T_4516, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4518 = mux(_T_4517, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4519 = and(_T_4518, way_status_out[46]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4520 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4521 = bits(_T_4520, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4522 = mux(_T_4521, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4523 = and(_T_4522, way_status_out[47]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4524 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4525 = bits(_T_4524, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4526 = mux(_T_4525, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4527 = and(_T_4526, way_status_out[48]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4528 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4529 = bits(_T_4528, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4530 = mux(_T_4529, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4531 = and(_T_4530, way_status_out[49]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4532 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4533 = bits(_T_4532, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4534 = mux(_T_4533, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4535 = and(_T_4534, way_status_out[50]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4536 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4537 = bits(_T_4536, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4538 = mux(_T_4537, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4539 = and(_T_4538, way_status_out[51]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4540 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4541 = bits(_T_4540, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4542 = mux(_T_4541, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4543 = and(_T_4542, way_status_out[52]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4544 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4545 = bits(_T_4544, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4546 = mux(_T_4545, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4547 = and(_T_4546, way_status_out[53]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4548 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4549 = bits(_T_4548, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4550 = mux(_T_4549, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4551 = and(_T_4550, way_status_out[54]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4552 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4553 = bits(_T_4552, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4554 = mux(_T_4553, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4555 = and(_T_4554, way_status_out[55]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4556 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4557 = bits(_T_4556, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4558 = mux(_T_4557, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4559 = and(_T_4558, way_status_out[56]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4560 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4561 = bits(_T_4560, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4562 = mux(_T_4561, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4563 = and(_T_4562, way_status_out[57]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4564 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4565 = bits(_T_4564, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4566 = mux(_T_4565, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4567 = and(_T_4566, way_status_out[58]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4568 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4569 = bits(_T_4568, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4570 = mux(_T_4569, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4571 = and(_T_4570, way_status_out[59]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4572 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4573 = bits(_T_4572, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4574 = mux(_T_4573, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4575 = and(_T_4574, way_status_out[60]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4576 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4577 = bits(_T_4576, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4578 = mux(_T_4577, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4579 = and(_T_4578, way_status_out[61]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4580 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4581 = bits(_T_4580, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4582 = mux(_T_4581, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4583 = and(_T_4582, way_status_out[62]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4584 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4585 = bits(_T_4584, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4586 = mux(_T_4585, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4587 = and(_T_4586, way_status_out[63]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4588 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4589 = bits(_T_4588, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4590 = mux(_T_4589, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4591 = and(_T_4590, way_status_out[64]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4592 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4593 = bits(_T_4592, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4594 = mux(_T_4593, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4595 = and(_T_4594, way_status_out[65]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4596 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4597 = bits(_T_4596, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4598 = mux(_T_4597, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4599 = and(_T_4598, way_status_out[66]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4600 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4601 = bits(_T_4600, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4602 = mux(_T_4601, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4603 = and(_T_4602, way_status_out[67]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4604 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4605 = bits(_T_4604, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4606 = mux(_T_4605, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4607 = and(_T_4606, way_status_out[68]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4608 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4609 = bits(_T_4608, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4610 = mux(_T_4609, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4611 = and(_T_4610, way_status_out[69]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4612 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4613 = bits(_T_4612, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4614 = mux(_T_4613, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4615 = and(_T_4614, way_status_out[70]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4616 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4617 = bits(_T_4616, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4618 = mux(_T_4617, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4619 = and(_T_4618, way_status_out[71]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4620 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4621 = bits(_T_4620, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4622 = mux(_T_4621, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4623 = and(_T_4622, way_status_out[72]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4624 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4625 = bits(_T_4624, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4626 = mux(_T_4625, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4627 = and(_T_4626, way_status_out[73]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4628 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4629 = bits(_T_4628, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4630 = mux(_T_4629, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4631 = and(_T_4630, way_status_out[74]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4632 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4633 = bits(_T_4632, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4634 = mux(_T_4633, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4635 = and(_T_4634, way_status_out[75]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4636 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4637 = bits(_T_4636, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4638 = mux(_T_4637, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4639 = and(_T_4638, way_status_out[76]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4640 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4641 = bits(_T_4640, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4642 = mux(_T_4641, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4643 = and(_T_4642, way_status_out[77]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4644 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4645 = bits(_T_4644, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4646 = mux(_T_4645, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4647 = and(_T_4646, way_status_out[78]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4648 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4649 = bits(_T_4648, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4650 = mux(_T_4649, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4651 = and(_T_4650, way_status_out[79]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4652 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4653 = bits(_T_4652, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4654 = mux(_T_4653, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4655 = and(_T_4654, way_status_out[80]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4656 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4657 = bits(_T_4656, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4658 = mux(_T_4657, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4659 = and(_T_4658, way_status_out[81]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4660 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4661 = bits(_T_4660, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4662 = mux(_T_4661, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4663 = and(_T_4662, way_status_out[82]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4664 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4665 = bits(_T_4664, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4666 = mux(_T_4665, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4667 = and(_T_4666, way_status_out[83]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4668 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4669 = bits(_T_4668, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4670 = mux(_T_4669, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4671 = and(_T_4670, way_status_out[84]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4672 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4673 = bits(_T_4672, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4674 = mux(_T_4673, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4675 = and(_T_4674, way_status_out[85]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4676 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4677 = bits(_T_4676, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4678 = mux(_T_4677, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4679 = and(_T_4678, way_status_out[86]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4680 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4681 = bits(_T_4680, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4682 = mux(_T_4681, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4683 = and(_T_4682, way_status_out[87]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4684 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4685 = bits(_T_4684, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4686 = mux(_T_4685, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4687 = and(_T_4686, way_status_out[88]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4688 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4689 = bits(_T_4688, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4690 = mux(_T_4689, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4691 = and(_T_4690, way_status_out[89]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4692 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4693 = bits(_T_4692, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4694 = mux(_T_4693, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4695 = and(_T_4694, way_status_out[90]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4696 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4697 = bits(_T_4696, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4698 = mux(_T_4697, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4699 = and(_T_4698, way_status_out[91]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4700 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4701 = bits(_T_4700, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4702 = mux(_T_4701, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4703 = and(_T_4702, way_status_out[92]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4704 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4705 = bits(_T_4704, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4706 = mux(_T_4705, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4707 = and(_T_4706, way_status_out[93]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4708 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4709 = bits(_T_4708, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4710 = mux(_T_4709, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4711 = and(_T_4710, way_status_out[94]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4712 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4713 = bits(_T_4712, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4714 = mux(_T_4713, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4715 = and(_T_4714, way_status_out[95]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4716 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4717 = bits(_T_4716, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4718 = mux(_T_4717, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4719 = and(_T_4718, way_status_out[96]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4720 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4721 = bits(_T_4720, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4722 = mux(_T_4721, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4723 = and(_T_4722, way_status_out[97]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4724 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4725 = bits(_T_4724, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4726 = mux(_T_4725, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4727 = and(_T_4726, way_status_out[98]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4728 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4729 = bits(_T_4728, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4730 = mux(_T_4729, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4731 = and(_T_4730, way_status_out[99]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4732 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4733 = bits(_T_4732, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4734 = mux(_T_4733, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4735 = and(_T_4734, way_status_out[100]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4736 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4737 = bits(_T_4736, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4738 = mux(_T_4737, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4739 = and(_T_4738, way_status_out[101]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4741 = bits(_T_4740, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4742 = mux(_T_4741, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4743 = and(_T_4742, way_status_out[102]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4744 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4745 = bits(_T_4744, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4746 = mux(_T_4745, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4747 = and(_T_4746, way_status_out[103]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4748 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4749 = bits(_T_4748, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4750 = mux(_T_4749, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4751 = and(_T_4750, way_status_out[104]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4752 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4753 = bits(_T_4752, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4754 = mux(_T_4753, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4755 = and(_T_4754, way_status_out[105]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4756 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4757 = bits(_T_4756, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4758 = mux(_T_4757, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4759 = and(_T_4758, way_status_out[106]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4760 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4761 = bits(_T_4760, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4762 = mux(_T_4761, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4763 = and(_T_4762, way_status_out[107]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4764 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4765 = bits(_T_4764, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4766 = mux(_T_4765, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4767 = and(_T_4766, way_status_out[108]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4768 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4769 = bits(_T_4768, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4770 = mux(_T_4769, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4771 = and(_T_4770, way_status_out[109]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4772 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4773 = bits(_T_4772, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4774 = mux(_T_4773, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4775 = and(_T_4774, way_status_out[110]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4776 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4777 = bits(_T_4776, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4778 = mux(_T_4777, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4779 = and(_T_4778, way_status_out[111]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4781 = bits(_T_4780, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4782 = mux(_T_4781, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4783 = and(_T_4782, way_status_out[112]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4784 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4785 = bits(_T_4784, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4786 = mux(_T_4785, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4787 = and(_T_4786, way_status_out[113]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4788 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4789 = bits(_T_4788, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4790 = mux(_T_4789, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4791 = and(_T_4790, way_status_out[114]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4792 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4793 = bits(_T_4792, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4794 = mux(_T_4793, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4795 = and(_T_4794, way_status_out[115]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4796 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4797 = bits(_T_4796, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4798 = mux(_T_4797, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4799 = and(_T_4798, way_status_out[116]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4800 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4801 = bits(_T_4800, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4802 = mux(_T_4801, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4803 = and(_T_4802, way_status_out[117]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4804 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4805 = bits(_T_4804, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4806 = mux(_T_4805, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4807 = and(_T_4806, way_status_out[118]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4808 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4809 = bits(_T_4808, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4810 = mux(_T_4809, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4811 = and(_T_4810, way_status_out[119]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4812 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4813 = bits(_T_4812, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4814 = mux(_T_4813, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4815 = and(_T_4814, way_status_out[120]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4816 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4817 = bits(_T_4816, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4818 = mux(_T_4817, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4819 = and(_T_4818, way_status_out[121]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4820 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4821 = bits(_T_4820, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4822 = mux(_T_4821, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4823 = and(_T_4822, way_status_out[122]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4824 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4825 = bits(_T_4824, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4826 = mux(_T_4825, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4827 = and(_T_4826, way_status_out[123]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4828 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4829 = bits(_T_4828, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4830 = mux(_T_4829, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4831 = and(_T_4830, way_status_out[124]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4832 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4833 = bits(_T_4832, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4834 = mux(_T_4833, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4835 = and(_T_4834, way_status_out[125]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4836 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4837 = bits(_T_4836, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4838 = mux(_T_4837, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4839 = and(_T_4838, way_status_out[126]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 757:114]
+    node _T_4841 = bits(_T_4840, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4842 = mux(_T_4841, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_4843 = and(_T_4842, way_status_out[127]) @[el2_ifu_mem_ctl.scala 757:122]
+    node _T_4844 = cat(_T_4843, _T_4839) @[Cat.scala 29:58]
+    node _T_4845 = cat(_T_4844, _T_4835) @[Cat.scala 29:58]
+    node _T_4846 = cat(_T_4845, _T_4831) @[Cat.scala 29:58]
+    node _T_4847 = cat(_T_4846, _T_4827) @[Cat.scala 29:58]
+    node _T_4848 = cat(_T_4847, _T_4823) @[Cat.scala 29:58]
+    node _T_4849 = cat(_T_4848, _T_4819) @[Cat.scala 29:58]
+    node _T_4850 = cat(_T_4849, _T_4815) @[Cat.scala 29:58]
+    node _T_4851 = cat(_T_4850, _T_4811) @[Cat.scala 29:58]
+    node _T_4852 = cat(_T_4851, _T_4807) @[Cat.scala 29:58]
+    node _T_4853 = cat(_T_4852, _T_4803) @[Cat.scala 29:58]
+    node _T_4854 = cat(_T_4853, _T_4799) @[Cat.scala 29:58]
+    node _T_4855 = cat(_T_4854, _T_4795) @[Cat.scala 29:58]
+    node _T_4856 = cat(_T_4855, _T_4791) @[Cat.scala 29:58]
+    node _T_4857 = cat(_T_4856, _T_4787) @[Cat.scala 29:58]
+    node _T_4858 = cat(_T_4857, _T_4783) @[Cat.scala 29:58]
+    node _T_4859 = cat(_T_4858, _T_4779) @[Cat.scala 29:58]
+    node _T_4860 = cat(_T_4859, _T_4775) @[Cat.scala 29:58]
+    node _T_4861 = cat(_T_4860, _T_4771) @[Cat.scala 29:58]
+    node _T_4862 = cat(_T_4861, _T_4767) @[Cat.scala 29:58]
+    node _T_4863 = cat(_T_4862, _T_4763) @[Cat.scala 29:58]
+    node _T_4864 = cat(_T_4863, _T_4759) @[Cat.scala 29:58]
+    node _T_4865 = cat(_T_4864, _T_4755) @[Cat.scala 29:58]
+    node _T_4866 = cat(_T_4865, _T_4751) @[Cat.scala 29:58]
+    node _T_4867 = cat(_T_4866, _T_4747) @[Cat.scala 29:58]
+    node _T_4868 = cat(_T_4867, _T_4743) @[Cat.scala 29:58]
+    node _T_4869 = cat(_T_4868, _T_4739) @[Cat.scala 29:58]
+    node _T_4870 = cat(_T_4869, _T_4735) @[Cat.scala 29:58]
+    node _T_4871 = cat(_T_4870, _T_4731) @[Cat.scala 29:58]
+    node _T_4872 = cat(_T_4871, _T_4727) @[Cat.scala 29:58]
+    node _T_4873 = cat(_T_4872, _T_4723) @[Cat.scala 29:58]
+    node _T_4874 = cat(_T_4873, _T_4719) @[Cat.scala 29:58]
+    node _T_4875 = cat(_T_4874, _T_4715) @[Cat.scala 29:58]
+    node _T_4876 = cat(_T_4875, _T_4711) @[Cat.scala 29:58]
+    node _T_4877 = cat(_T_4876, _T_4707) @[Cat.scala 29:58]
+    node _T_4878 = cat(_T_4877, _T_4703) @[Cat.scala 29:58]
+    node _T_4879 = cat(_T_4878, _T_4699) @[Cat.scala 29:58]
+    node _T_4880 = cat(_T_4879, _T_4695) @[Cat.scala 29:58]
+    node _T_4881 = cat(_T_4880, _T_4691) @[Cat.scala 29:58]
+    node _T_4882 = cat(_T_4881, _T_4687) @[Cat.scala 29:58]
+    node _T_4883 = cat(_T_4882, _T_4683) @[Cat.scala 29:58]
+    node _T_4884 = cat(_T_4883, _T_4679) @[Cat.scala 29:58]
+    node _T_4885 = cat(_T_4884, _T_4675) @[Cat.scala 29:58]
+    node _T_4886 = cat(_T_4885, _T_4671) @[Cat.scala 29:58]
+    node _T_4887 = cat(_T_4886, _T_4667) @[Cat.scala 29:58]
+    node _T_4888 = cat(_T_4887, _T_4663) @[Cat.scala 29:58]
+    node _T_4889 = cat(_T_4888, _T_4659) @[Cat.scala 29:58]
+    node _T_4890 = cat(_T_4889, _T_4655) @[Cat.scala 29:58]
+    node _T_4891 = cat(_T_4890, _T_4651) @[Cat.scala 29:58]
+    node _T_4892 = cat(_T_4891, _T_4647) @[Cat.scala 29:58]
+    node _T_4893 = cat(_T_4892, _T_4643) @[Cat.scala 29:58]
+    node _T_4894 = cat(_T_4893, _T_4639) @[Cat.scala 29:58]
+    node _T_4895 = cat(_T_4894, _T_4635) @[Cat.scala 29:58]
+    node _T_4896 = cat(_T_4895, _T_4631) @[Cat.scala 29:58]
+    node _T_4897 = cat(_T_4896, _T_4627) @[Cat.scala 29:58]
+    node _T_4898 = cat(_T_4897, _T_4623) @[Cat.scala 29:58]
+    node _T_4899 = cat(_T_4898, _T_4619) @[Cat.scala 29:58]
+    node _T_4900 = cat(_T_4899, _T_4615) @[Cat.scala 29:58]
+    node _T_4901 = cat(_T_4900, _T_4611) @[Cat.scala 29:58]
+    node _T_4902 = cat(_T_4901, _T_4607) @[Cat.scala 29:58]
+    node _T_4903 = cat(_T_4902, _T_4603) @[Cat.scala 29:58]
+    node _T_4904 = cat(_T_4903, _T_4599) @[Cat.scala 29:58]
+    node _T_4905 = cat(_T_4904, _T_4595) @[Cat.scala 29:58]
+    node _T_4906 = cat(_T_4905, _T_4591) @[Cat.scala 29:58]
+    node _T_4907 = cat(_T_4906, _T_4587) @[Cat.scala 29:58]
+    node _T_4908 = cat(_T_4907, _T_4583) @[Cat.scala 29:58]
+    node _T_4909 = cat(_T_4908, _T_4579) @[Cat.scala 29:58]
+    node _T_4910 = cat(_T_4909, _T_4575) @[Cat.scala 29:58]
+    node _T_4911 = cat(_T_4910, _T_4571) @[Cat.scala 29:58]
+    node _T_4912 = cat(_T_4911, _T_4567) @[Cat.scala 29:58]
+    node _T_4913 = cat(_T_4912, _T_4563) @[Cat.scala 29:58]
+    node _T_4914 = cat(_T_4913, _T_4559) @[Cat.scala 29:58]
+    node _T_4915 = cat(_T_4914, _T_4555) @[Cat.scala 29:58]
+    node _T_4916 = cat(_T_4915, _T_4551) @[Cat.scala 29:58]
+    node _T_4917 = cat(_T_4916, _T_4547) @[Cat.scala 29:58]
+    node _T_4918 = cat(_T_4917, _T_4543) @[Cat.scala 29:58]
+    node _T_4919 = cat(_T_4918, _T_4539) @[Cat.scala 29:58]
+    node _T_4920 = cat(_T_4919, _T_4535) @[Cat.scala 29:58]
+    node _T_4921 = cat(_T_4920, _T_4531) @[Cat.scala 29:58]
+    node _T_4922 = cat(_T_4921, _T_4527) @[Cat.scala 29:58]
+    node _T_4923 = cat(_T_4922, _T_4523) @[Cat.scala 29:58]
+    node _T_4924 = cat(_T_4923, _T_4519) @[Cat.scala 29:58]
+    node _T_4925 = cat(_T_4924, _T_4515) @[Cat.scala 29:58]
+    node _T_4926 = cat(_T_4925, _T_4511) @[Cat.scala 29:58]
+    node _T_4927 = cat(_T_4926, _T_4507) @[Cat.scala 29:58]
+    node _T_4928 = cat(_T_4927, _T_4503) @[Cat.scala 29:58]
+    node _T_4929 = cat(_T_4928, _T_4499) @[Cat.scala 29:58]
+    node _T_4930 = cat(_T_4929, _T_4495) @[Cat.scala 29:58]
+    node _T_4931 = cat(_T_4930, _T_4491) @[Cat.scala 29:58]
+    node _T_4932 = cat(_T_4931, _T_4487) @[Cat.scala 29:58]
+    node _T_4933 = cat(_T_4932, _T_4483) @[Cat.scala 29:58]
+    node _T_4934 = cat(_T_4933, _T_4479) @[Cat.scala 29:58]
+    node _T_4935 = cat(_T_4934, _T_4475) @[Cat.scala 29:58]
+    node _T_4936 = cat(_T_4935, _T_4471) @[Cat.scala 29:58]
+    node _T_4937 = cat(_T_4936, _T_4467) @[Cat.scala 29:58]
+    node _T_4938 = cat(_T_4937, _T_4463) @[Cat.scala 29:58]
+    node _T_4939 = cat(_T_4938, _T_4459) @[Cat.scala 29:58]
+    node _T_4940 = cat(_T_4939, _T_4455) @[Cat.scala 29:58]
+    node _T_4941 = cat(_T_4940, _T_4451) @[Cat.scala 29:58]
+    node _T_4942 = cat(_T_4941, _T_4447) @[Cat.scala 29:58]
+    node _T_4943 = cat(_T_4942, _T_4443) @[Cat.scala 29:58]
+    node _T_4944 = cat(_T_4943, _T_4439) @[Cat.scala 29:58]
+    node _T_4945 = cat(_T_4944, _T_4435) @[Cat.scala 29:58]
+    node _T_4946 = cat(_T_4945, _T_4431) @[Cat.scala 29:58]
+    node _T_4947 = cat(_T_4946, _T_4427) @[Cat.scala 29:58]
+    node _T_4948 = cat(_T_4947, _T_4423) @[Cat.scala 29:58]
+    node _T_4949 = cat(_T_4948, _T_4419) @[Cat.scala 29:58]
+    node _T_4950 = cat(_T_4949, _T_4415) @[Cat.scala 29:58]
+    node _T_4951 = cat(_T_4950, _T_4411) @[Cat.scala 29:58]
+    node _T_4952 = cat(_T_4951, _T_4407) @[Cat.scala 29:58]
+    node _T_4953 = cat(_T_4952, _T_4403) @[Cat.scala 29:58]
+    node _T_4954 = cat(_T_4953, _T_4399) @[Cat.scala 29:58]
+    node _T_4955 = cat(_T_4954, _T_4395) @[Cat.scala 29:58]
+    node _T_4956 = cat(_T_4955, _T_4391) @[Cat.scala 29:58]
+    node _T_4957 = cat(_T_4956, _T_4387) @[Cat.scala 29:58]
+    node _T_4958 = cat(_T_4957, _T_4383) @[Cat.scala 29:58]
+    node _T_4959 = cat(_T_4958, _T_4379) @[Cat.scala 29:58]
+    node _T_4960 = cat(_T_4959, _T_4375) @[Cat.scala 29:58]
+    node _T_4961 = cat(_T_4960, _T_4371) @[Cat.scala 29:58]
+    node _T_4962 = cat(_T_4961, _T_4367) @[Cat.scala 29:58]
+    node _T_4963 = cat(_T_4962, _T_4363) @[Cat.scala 29:58]
+    node _T_4964 = cat(_T_4963, _T_4359) @[Cat.scala 29:58]
+    node _T_4965 = cat(_T_4964, _T_4355) @[Cat.scala 29:58]
+    node _T_4966 = cat(_T_4965, _T_4351) @[Cat.scala 29:58]
+    node _T_4967 = cat(_T_4966, _T_4347) @[Cat.scala 29:58]
+    node _T_4968 = cat(_T_4967, _T_4343) @[Cat.scala 29:58]
+    node _T_4969 = cat(_T_4968, _T_4339) @[Cat.scala 29:58]
+    node _T_4970 = cat(_T_4969, _T_4335) @[Cat.scala 29:58]
+    way_status <= _T_4970 @[el2_ifu_mem_ctl.scala 757:14]
+    node _T_4971 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 758:59]
+    node _T_4972 = and(_T_4971, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 758:81]
+    node _T_4973 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 759:21]
+    node _T_4974 = bits(ic_rw_addr, 11, 5) @[el2_ifu_mem_ctl.scala 759:82]
+    node ifu_ic_rw_int_addr_w_debug = mux(_T_4972, _T_4973, _T_4974) @[el2_ifu_mem_ctl.scala 758:39]
+    reg _T_4975 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 760:58]
+    _T_4975 <= ifu_ic_rw_int_addr_w_debug @[el2_ifu_mem_ctl.scala 760:58]
+    ifu_ic_rw_int_addr_ff <= _T_4975 @[el2_ifu_mem_ctl.scala 760:25]
+    wire ifu_tag_wren : UInt<2>
+    ifu_tag_wren <= UInt<1>("h00")
+    wire ic_debug_tag_wr_en : UInt<2>
+    ic_debug_tag_wr_en <= UInt<1>("h00")
+    node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[el2_ifu_mem_ctl.scala 763:43]
+    reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 764:55]
+    ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[el2_ifu_mem_ctl.scala 764:55]
+    node _T_4976 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 765:48]
+    node _T_4977 = bits(io.ic_debug_wr_data, 0, 0) @[el2_ifu_mem_ctl.scala 765:92]
+    node ic_valid_w_debug = mux(_T_4976, _T_4977, ic_valid) @[el2_ifu_mem_ctl.scala 765:29]
+    reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 766:51]
+    ic_valid_ff <= ic_valid_w_debug @[el2_ifu_mem_ctl.scala 766:51]
+    io.test <= ic_valid_ff @[el2_ifu_mem_ctl.scala 767:11]
     
diff --git a/el2_ifu_mem_ctl.v b/el2_ifu_mem_ctl.v
index bca9ac38..7f8a6d18 100644
--- a/el2_ifu_mem_ctl.v
+++ b/el2_ifu_mem_ctl.v
@@ -139,7 +139,7 @@ module el2_ifu_mem_ctl(
   output        io_ifu_ic_debug_rd_data_valid,
   output        io_iccm_buf_correct_ecc,
   output        io_iccm_correction_state,
-  output [6:0]  io_test,
+  output        io_test,
   input         io_scan_mode
 );
 `ifdef RANDOMIZE_REG_INIT
@@ -167,10 +167,10 @@ module el2_ifu_mem_ctl(
   reg [31:0] _RAND_21;
   reg [31:0] _RAND_22;
   reg [31:0] _RAND_23;
-  reg [63:0] _RAND_24;
-  reg [63:0] _RAND_25;
-  reg [63:0] _RAND_26;
-  reg [63:0] _RAND_27;
+  reg [31:0] _RAND_24;
+  reg [31:0] _RAND_25;
+  reg [31:0] _RAND_26;
+  reg [31:0] _RAND_27;
   reg [63:0] _RAND_28;
   reg [63:0] _RAND_29;
   reg [63:0] _RAND_30;
@@ -184,17 +184,27 @@ module el2_ifu_mem_ctl(
   reg [63:0] _RAND_38;
   reg [63:0] _RAND_39;
   reg [63:0] _RAND_40;
-  reg [31:0] _RAND_41;
-  reg [31:0] _RAND_42;
-  reg [95:0] _RAND_43;
-  reg [31:0] _RAND_44;
+  reg [63:0] _RAND_41;
+  reg [63:0] _RAND_42;
+  reg [63:0] _RAND_43;
+  reg [63:0] _RAND_44;
   reg [31:0] _RAND_45;
   reg [31:0] _RAND_46;
-  reg [31:0] _RAND_47;
+  reg [95:0] _RAND_47;
   reg [31:0] _RAND_48;
   reg [31:0] _RAND_49;
   reg [31:0] _RAND_50;
   reg [63:0] _RAND_51;
+  reg [31:0] _RAND_52;
+  reg [31:0] _RAND_53;
+  reg [31:0] _RAND_54;
+  reg [31:0] _RAND_55;
+  reg [63:0] _RAND_56;
+  reg [31:0] _RAND_57;
+  reg [31:0] _RAND_58;
+  reg [31:0] _RAND_59;
+  reg [31:0] _RAND_60;
+  reg [31:0] _RAND_61;
 `endif // RANDOMIZE_REG_INIT
   wire  rvclkhdr_io_clk; // @[el2_lib.scala 412:22]
   wire  rvclkhdr_io_en; // @[el2_lib.scala 412:22]
@@ -202,6 +212,54 @@ module el2_ifu_mem_ctl(
   wire  rvclkhdr_1_io_clk; // @[el2_lib.scala 412:22]
   wire  rvclkhdr_1_io_en; // @[el2_lib.scala 412:22]
   wire  rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_2_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_2_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_3_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_3_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_4_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_4_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_5_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_5_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_6_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_6_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_7_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_7_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_8_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_8_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_9_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_9_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_10_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_10_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_11_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_11_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_12_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_12_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_13_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_13_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_14_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_14_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_15_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_15_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_16_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_16_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_17_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_17_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 412:22]
   reg  flush_final_f; // @[el2_ifu_mem_ctl.scala 234:30]
   reg  ifc_fetch_req_f_raw; // @[el2_ifu_mem_ctl.scala 367:36]
   wire  _T_308 = ~io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 368:44]
@@ -210,26 +268,27 @@ module el2_ifu_mem_ctl(
   reg [2:0] miss_state; // @[Reg.scala 27:20]
   wire  miss_pending = miss_state != 3'h0; // @[el2_ifu_mem_ctl.scala 300:30]
   wire  _T_1 = _T | miss_pending; // @[el2_ifu_mem_ctl.scala 235:71]
+  wire  debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_mem_ctl.scala 236:42]
   wire [3:0] ic_fetch_val_int_f = {2'h0,io_ic_fetch_val_f}; // @[Cat.scala 29:58]
   reg [30:0] ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 355:34]
-  wire [4:0] _GEN_74 = {{1'd0}, ic_fetch_val_int_f}; // @[el2_ifu_mem_ctl.scala 705:53]
-  wire [4:0] ic_fetch_val_shift_right = _GEN_74 << ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 705:53]
-  wire [1:0] _GEN_75 = {{1'd0}, _T_308}; // @[el2_ifu_mem_ctl.scala 708:91]
-  wire [1:0] _T_3058 = ic_fetch_val_shift_right[3:2] & _GEN_75; // @[el2_ifu_mem_ctl.scala 708:91]
+  wire [4:0] _GEN_204 = {{1'd0}, ic_fetch_val_int_f}; // @[el2_ifu_mem_ctl.scala 705:53]
+  wire [4:0] ic_fetch_val_shift_right = _GEN_204 << ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 705:53]
+  wire [1:0] _GEN_205 = {{1'd0}, _T_308}; // @[el2_ifu_mem_ctl.scala 708:91]
+  wire [1:0] _T_3058 = ic_fetch_val_shift_right[3:2] & _GEN_205; // @[el2_ifu_mem_ctl.scala 708:91]
   reg  ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 369:31]
   wire  fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 322:46]
-  wire [1:0] _GEN_76 = {{1'd0}, fetch_req_iccm_f}; // @[el2_ifu_mem_ctl.scala 708:113]
-  wire [1:0] _T_3059 = _T_3058 & _GEN_76; // @[el2_ifu_mem_ctl.scala 708:113]
+  wire [1:0] _GEN_206 = {{1'd0}, fetch_req_iccm_f}; // @[el2_ifu_mem_ctl.scala 708:113]
+  wire [1:0] _T_3059 = _T_3058 & _GEN_206; // @[el2_ifu_mem_ctl.scala 708:113]
   reg  iccm_dma_rvalid_in; // @[el2_ifu_mem_ctl.scala 694:59]
-  wire [1:0] _GEN_77 = {{1'd0}, iccm_dma_rvalid_in}; // @[el2_ifu_mem_ctl.scala 708:130]
-  wire [1:0] _T_3060 = _T_3059 | _GEN_77; // @[el2_ifu_mem_ctl.scala 708:130]
+  wire [1:0] _GEN_207 = {{1'd0}, iccm_dma_rvalid_in}; // @[el2_ifu_mem_ctl.scala 708:130]
+  wire [1:0] _T_3060 = _T_3059 | _GEN_207; // @[el2_ifu_mem_ctl.scala 708:130]
   wire  _T_3061 = ~io_dec_tlu_core_ecc_disable; // @[el2_ifu_mem_ctl.scala 708:154]
-  wire [1:0] _GEN_78 = {{1'd0}, _T_3061}; // @[el2_ifu_mem_ctl.scala 708:152]
-  wire [1:0] _T_3062 = _T_3060 & _GEN_78; // @[el2_ifu_mem_ctl.scala 708:152]
-  wire [1:0] _T_3051 = ic_fetch_val_shift_right[1:0] & _GEN_75; // @[el2_ifu_mem_ctl.scala 708:91]
-  wire [1:0] _T_3052 = _T_3051 & _GEN_76; // @[el2_ifu_mem_ctl.scala 708:113]
-  wire [1:0] _T_3053 = _T_3052 | _GEN_77; // @[el2_ifu_mem_ctl.scala 708:130]
-  wire [1:0] _T_3055 = _T_3053 & _GEN_78; // @[el2_ifu_mem_ctl.scala 708:152]
+  wire [1:0] _GEN_208 = {{1'd0}, _T_3061}; // @[el2_ifu_mem_ctl.scala 708:152]
+  wire [1:0] _T_3062 = _T_3060 & _GEN_208; // @[el2_ifu_mem_ctl.scala 708:152]
+  wire [1:0] _T_3051 = ic_fetch_val_shift_right[1:0] & _GEN_205; // @[el2_ifu_mem_ctl.scala 708:91]
+  wire [1:0] _T_3052 = _T_3051 & _GEN_206; // @[el2_ifu_mem_ctl.scala 708:113]
+  wire [1:0] _T_3053 = _T_3052 | _GEN_207; // @[el2_ifu_mem_ctl.scala 708:130]
+  wire [1:0] _T_3055 = _T_3053 & _GEN_208; // @[el2_ifu_mem_ctl.scala 708:152]
   wire [3:0] iccm_ecc_word_enable = {_T_3062,_T_3055}; // @[Cat.scala 29:58]
   wire  _T_3162 = ^io_iccm_rd_data_ecc[31:0]; // @[el2_lib.scala 296:30]
   wire  _T_3163 = ^io_iccm_rd_data_ecc[38:32]; // @[el2_lib.scala 296:44]
@@ -324,9 +383,11 @@ module el2_ifu_mem_ctl(
   wire  _T_15 = _T_14 & io_ifu_axi_rready; // @[el2_ifu_mem_ctl.scala 242:65]
   wire  _T_219 = |io_ic_rd_hit; // @[el2_ifu_mem_ctl.scala 330:37]
   wire  _T_220 = ~_T_219; // @[el2_ifu_mem_ctl.scala 330:23]
+  reg  reset_all_tags; // @[el2_ifu_mem_ctl.scala 740:53]
+  wire  _T_221 = _T_220 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 330:41]
   wire  _T_199 = ~ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 321:48]
   wire  fetch_req_icache_f = ifc_fetch_req_f & _T_199; // @[el2_ifu_mem_ctl.scala 321:46]
-  wire  _T_222 = _T_220 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 330:59]
+  wire  _T_222 = _T_221 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 330:59]
   wire  _T_223 = ~miss_pending; // @[el2_ifu_mem_ctl.scala 330:82]
   wire  ic_act_miss_f = _T_222 & _T_223; // @[el2_ifu_mem_ctl.scala 330:80]
   reg  ifu_bus_rvalid_unq_ff; // @[Reg.scala 27:20]
@@ -484,7 +545,8 @@ module el2_ifu_mem_ctl(
   wire [2:0] _T_120 = _T_118 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 270:27]
   wire  _T_124 = 3'h2 == miss_state; // @[Conditional.scala 37:30]
   wire  _T_228 = io_ic_rd_hit == 2'h0; // @[el2_ifu_mem_ctl.scala 331:28]
-  wire  _T_230 = _T_228 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 331:60]
+  wire  _T_229 = _T_228 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 331:42]
+  wire  _T_230 = _T_229 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 331:60]
   wire  _T_231 = miss_state == 3'h2; // @[el2_ifu_mem_ctl.scala 331:94]
   wire  _T_232 = _T_230 & _T_231; // @[el2_ifu_mem_ctl.scala 331:81]
   wire  _T_235 = imb_ff[30:5] != ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 332:39]
@@ -567,17 +629,33 @@ module el2_ifu_mem_ctl(
   wire  sel_hold_imb = _T_179 | _T_181; // @[el2_ifu_mem_ctl.scala 303:93]
   wire  _T_183 = _T_18 | ic_miss_under_miss_f; // @[el2_ifu_mem_ctl.scala 306:57]
   wire  sel_hold_imb_scnd = _T_183 & _T_166; // @[el2_ifu_mem_ctl.scala 306:81]
+  wire  _T_187 = ~reset_all_tags; // @[el2_ifu_mem_ctl.scala 309:96]
   reg [30:0] imb_scnd_ff; // @[el2_ifu_mem_ctl.scala 313:25]
+  wire [2:0] _T_198 = bus_ifu_wr_en_ff ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
   reg [2:0] ifu_bus_rid_ff; // @[Reg.scala 27:20]
+  wire [2:0] ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & _T_198; // @[el2_ifu_mem_ctl.scala 318:45]
   wire  _T_204 = _T_223 | _T_231; // @[el2_ifu_mem_ctl.scala 323:59]
   wire  _T_206 = _T_204 | _T_2216; // @[el2_ifu_mem_ctl.scala 323:91]
   wire  ic_iccm_hit_f = fetch_req_iccm_f & _T_206; // @[el2_ifu_mem_ctl.scala 323:41]
   wire  _T_211 = _T_219 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 329:39]
-  wire  _T_217 = _T_211 & _T_204; // @[el2_ifu_mem_ctl.scala 329:78]
+  wire  _T_213 = _T_211 & _T_187; // @[el2_ifu_mem_ctl.scala 329:60]
+  wire  _T_217 = _T_213 & _T_204; // @[el2_ifu_mem_ctl.scala 329:78]
   wire  ic_act_hit_f = _T_217 & _T_239; // @[el2_ifu_mem_ctl.scala 329:126]
   wire  _T_254 = ic_act_hit_f | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 336:31]
   wire  uncacheable_miss_in = sel_hold_imb ? uncacheable_miss_ff : io_ifc_fetch_uncacheable_bf; // @[el2_ifu_mem_ctl.scala 337:84]
+  reg [1:0] ifu_bus_rresp_ff; // @[Reg.scala 27:20]
+  wire  _T_2599 = |ifu_bus_rresp_ff; // @[el2_ifu_mem_ctl.scala 662:48]
+  wire  _T_2600 = _T_2599 & ifu_bus_rvalid_ff; // @[el2_ifu_mem_ctl.scala 662:52]
+  wire  bus_ifu_wr_data_error_ff = _T_2600 & miss_pending; // @[el2_ifu_mem_ctl.scala 662:73]
+  reg  ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 412:61]
+  wire  ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 411:55]
+  wire  _T_268 = ~ifu_wr_cumulative_err_data; // @[el2_ifu_mem_ctl.scala 340:145]
   reg  scnd_miss_req_q; // @[el2_ifu_mem_ctl.scala 589:52]
+  wire  _T_288 = ~scnd_miss_req_q; // @[el2_ifu_mem_ctl.scala 352:36]
+  wire  _T_289 = miss_pending & _T_288; // @[el2_ifu_mem_ctl.scala 352:34]
+  reg  reset_ic_ff; // @[el2_ifu_mem_ctl.scala 353:25]
+  wire  _T_290 = reset_all_tags | reset_ic_ff; // @[el2_ifu_mem_ctl.scala 352:72]
+  wire  reset_ic_in = _T_289 & _T_290; // @[el2_ifu_mem_ctl.scala 352:53]
   reg [25:0] miss_addr; // @[el2_ifu_mem_ctl.scala 362:23]
   wire  _T_304 = _T_2230 & flush_final_f; // @[el2_ifu_mem_ctl.scala 366:87]
   wire  _T_305 = ~_T_304; // @[el2_ifu_mem_ctl.scala 366:55]
@@ -620,6 +698,13 @@ module el2_ifu_mem_ctl(
   wire  _T_2593 = ic_act_miss_f_delayed & _T_2231; // @[el2_ifu_mem_ctl.scala 660:53]
   wire  reset_tag_valid_for_miss = _T_2593 & _T_52; // @[el2_ifu_mem_ctl.scala 660:84]
   wire  sel_mb_addr = _T_321 | reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 378:79]
+  wire [30:0] _T_326 = {imb_ff[30:5],ic_wr_addr_bits_hi_3,imb_ff[1:0]}; // @[Cat.scala 29:58]
+  wire  _T_335 = _T_321 & last_beat; // @[el2_ifu_mem_ctl.scala 382:84]
+  wire  _T_2587 = ~_T_2599; // @[el2_ifu_mem_ctl.scala 657:84]
+  wire  _T_2588 = _T_92 & _T_2587; // @[el2_ifu_mem_ctl.scala 657:82]
+  wire  bus_ifu_wr_en_ff_q = _T_2588 & write_ic_16_bytes; // @[el2_ifu_mem_ctl.scala 657:108]
+  wire  sel_mb_status_addr = _T_335 & bus_ifu_wr_en_ff_q; // @[el2_ifu_mem_ctl.scala 382:96]
+  wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_326 : ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 383:31]
   reg [63:0] ifu_bus_rdata_ff; // @[Reg.scala 27:20]
   wire [7:0] _T_559 = {ifu_bus_rdata_ff[11],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[4],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[1],ifu_bus_rdata_ff[0]}; // @[el2_lib.scala 343:27]
   wire [16:0] _T_568 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[26],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[13],_T_559}; // @[el2_lib.scala 343:27]
@@ -895,8 +980,8 @@ module el2_ifu_mem_ctl(
   wire  _T_1480 = _T_1479 | _T_1473; // @[Mux.scala 27:72]
   wire  _T_1482 = _T_1449 & _T_1480; // @[el2_ifu_mem_ctl.scala 463:69]
   wire  _T_1483 = _T_1445 | _T_1482; // @[el2_ifu_mem_ctl.scala 462:94]
-  wire [4:0] _GEN_83 = {{2'd0}, bypass_index[4:2]}; // @[el2_ifu_mem_ctl.scala 464:95]
-  wire  _T_1486 = _GEN_83 == 5'h1f; // @[el2_ifu_mem_ctl.scala 464:95]
+  wire [4:0] _GEN_437 = {{2'd0}, bypass_index[4:2]}; // @[el2_ifu_mem_ctl.scala 464:95]
+  wire  _T_1486 = _GEN_437 == 5'h1f; // @[el2_ifu_mem_ctl.scala 464:95]
   wire  _T_1487 = bypass_valid_value_check & _T_1486; // @[el2_ifu_mem_ctl.scala 464:56]
   wire  bypass_data_ready_in = _T_1483 | _T_1487; // @[el2_ifu_mem_ctl.scala 463:181]
   wire  _T_1488 = bypass_data_ready_in & crit_wd_byp_ok_ff; // @[el2_ifu_mem_ctl.scala 468:53]
@@ -958,6 +1043,7 @@ module el2_ifu_mem_ctl(
   wire  _T_2400 = ~ifc_bus_acc_fault_f; // @[el2_ifu_mem_ctl.scala 513:60]
   wire  ic_rd_parity_final_err = _T_2398 & _T_2400; // @[el2_ifu_mem_ctl.scala 513:58]
   reg [70:0] _T_1200; // @[el2_ifu_mem_ctl.scala 400:37]
+  wire  ifu_wr_cumulative_err = ifu_wr_cumulative_err_data & _T_2528; // @[el2_ifu_mem_ctl.scala 410:80]
   wire  fetch_req_f_qual = io_ic_hit_f & _T_308; // @[el2_ifu_mem_ctl.scala 428:38]
   wire [1:0] _T_1264 = ifc_region_acc_fault_f ? 2'h2 : 2'h0; // @[el2_ifu_mem_ctl.scala 432:8]
   wire [7:0] _T_1345 = {ic_miss_buff_data_valid_in_7,ic_miss_buff_data_valid_in_6,ic_miss_buff_data_valid_in_5,ic_miss_buff_data_valid_in_4,ic_miss_buff_data_valid_in_3,ic_miss_buff_data_valid_in_2,ic_miss_buff_data_valid_in_1,ic_miss_buff_data_valid_in_0}; // @[Cat.scala 29:58]
@@ -1113,6 +1199,8 @@ module el2_ifu_mem_ctl(
   wire [13:0] dma_mem_ecc = {_T_2822,_T_2742,_T_2760,_T_2778,_T_2793,_T_2808,_T_2814,_T_3019}; // @[Cat.scala 29:58]
   wire  _T_3021 = ~_T_2615; // @[el2_ifu_mem_ctl.scala 679:45]
   wire  _T_3022 = iccm_correct_ecc & _T_3021; // @[el2_ifu_mem_ctl.scala 679:43]
+  reg [38:0] iccm_ecc_corr_data_ff; // @[Reg.scala 27:20]
+  wire [77:0] _T_3023 = {iccm_ecc_corr_data_ff,iccm_ecc_corr_data_ff}; // @[Cat.scala 29:58]
   wire [77:0] _T_3030 = {dma_mem_ecc[13:7],io_dma_mem_wdata[63:32],dma_mem_ecc[6:0],io_dma_mem_wdata[31:0]}; // @[Cat.scala 29:58]
   reg [1:0] dma_mem_addr_ff; // @[el2_ifu_mem_ctl.scala 693:53]
   wire  _T_3362 = _T_3274[5:0] == 6'h27; // @[el2_lib.scala 302:41]
@@ -1228,13 +1316,69 @@ module el2_ifu_mem_ctl(
   reg [63:0] iccm_dma_rdata; // @[el2_ifu_mem_ctl.scala 699:70]
   wire  _T_3040 = _T_2615 & _T_2604; // @[el2_ifu_mem_ctl.scala 702:65]
   wire  _T_3043 = _T_3021 & iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 703:50]
-  wire [15:0] _T_3046 = _T_3043 ? 16'h0 : io_ifc_fetch_addr_bf[15:0]; // @[el2_ifu_mem_ctl.scala 703:8]
+  reg [13:0] iccm_ecc_corr_index_ff; // @[Reg.scala 27:20]
+  wire [14:0] _T_3044 = {iccm_ecc_corr_index_ff,1'h0}; // @[Cat.scala 29:58]
+  wire [15:0] _T_3046 = _T_3043 ? {{1'd0}, _T_3044} : io_ifc_fetch_addr_bf[15:0]; // @[el2_ifu_mem_ctl.scala 703:8]
   wire [31:0] _T_3047 = _T_3040 ? io_dma_mem_addr : {{16'd0}, _T_3046}; // @[el2_ifu_mem_ctl.scala 702:25]
   wire  _T_3436 = _T_3274 == 7'h40; // @[el2_lib.scala 308:62]
   wire  _T_3437 = _T_3424[38] ^ _T_3436; // @[el2_lib.scala 308:44]
-  wire [3:0] _T_3444 = {_T_3424[7],_T_3424[3],_T_3424[1:0]}; // @[Cat.scala 29:58]
-  wire [2:0] _T_3446 = {_T_3437,_T_3424[31],_T_3424[15]}; // @[Cat.scala 29:58]
+  wire [6:0] iccm_corrected_ecc_0 = {_T_3437,_T_3424[31],_T_3424[15],_T_3424[7],_T_3424[3],_T_3424[1:0]}; // @[Cat.scala 29:58]
+  wire  _T_3821 = _T_3659 == 7'h40; // @[el2_lib.scala 308:62]
+  wire  _T_3822 = _T_3809[38] ^ _T_3821; // @[el2_lib.scala 308:44]
+  wire [6:0] iccm_corrected_ecc_1 = {_T_3822,_T_3809[31],_T_3809[15],_T_3809[7],_T_3809[3],_T_3809[1:0]}; // @[Cat.scala 29:58]
   wire  _T_3838 = _T_4 & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 715:58]
+  wire [31:0] iccm_corrected_data_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[el2_ifu_mem_ctl.scala 717:38]
+  wire [6:0] iccm_corrected_ecc_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_ecc_0 : iccm_corrected_ecc_1; // @[el2_ifu_mem_ctl.scala 718:37]
+  reg  iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 726:62]
+  wire  _T_3846 = ~iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 720:76]
+  wire  _T_3847 = io_iccm_rd_ecc_single_err & _T_3846; // @[el2_ifu_mem_ctl.scala 720:74]
+  wire  _T_3849 = _T_3847 & _T_308; // @[el2_ifu_mem_ctl.scala 720:104]
+  wire  iccm_ecc_write_status = _T_3849 | io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 720:127]
+  wire  _T_3850 = io_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 721:67]
+  wire  iccm_rd_ecc_single_err_hold_in = _T_3850 & _T_308; // @[el2_ifu_mem_ctl.scala 721:96]
+  reg [13:0] iccm_rw_addr_f; // @[el2_ifu_mem_ctl.scala 725:51]
+  wire [13:0] _T_3855 = iccm_rw_addr_f + 14'h1; // @[el2_ifu_mem_ctl.scala 724:102]
+  wire [38:0] _T_3859 = {iccm_corrected_ecc_f_mux,iccm_corrected_data_f_mux}; // @[Cat.scala 29:58]
+  wire  _T_3864 = ~io_ifc_fetch_uncacheable_bf; // @[el2_ifu_mem_ctl.scala 729:41]
+  wire  _T_3865 = io_ifc_fetch_req_bf & _T_3864; // @[el2_ifu_mem_ctl.scala 729:39]
+  wire  _T_3866 = ~io_ifc_iccm_access_bf; // @[el2_ifu_mem_ctl.scala 729:72]
+  wire  _T_3867 = _T_3865 & _T_3866; // @[el2_ifu_mem_ctl.scala 729:70]
+  wire  _T_3869 = ~miss_state_en; // @[el2_ifu_mem_ctl.scala 730:34]
+  wire  _T_3870 = _T_2216 & _T_3869; // @[el2_ifu_mem_ctl.scala 730:32]
+  wire  _T_3873 = _T_2231 & _T_3869; // @[el2_ifu_mem_ctl.scala 731:37]
+  wire  _T_3874 = _T_3870 | _T_3873; // @[el2_ifu_mem_ctl.scala 730:88]
+  wire  _T_3875 = miss_state == 3'h7; // @[el2_ifu_mem_ctl.scala 732:19]
+  wire  _T_3877 = _T_3875 & _T_3869; // @[el2_ifu_mem_ctl.scala 732:41]
+  wire  _T_3878 = _T_3874 | _T_3877; // @[el2_ifu_mem_ctl.scala 731:88]
+  wire  _T_3879 = miss_state == 3'h3; // @[el2_ifu_mem_ctl.scala 733:19]
+  wire  _T_3881 = _T_3879 & _T_3869; // @[el2_ifu_mem_ctl.scala 733:35]
+  wire  _T_3882 = _T_3878 | _T_3881; // @[el2_ifu_mem_ctl.scala 732:88]
+  wire  _T_3885 = _T_2230 & _T_3869; // @[el2_ifu_mem_ctl.scala 734:38]
+  wire  _T_3886 = _T_3882 | _T_3885; // @[el2_ifu_mem_ctl.scala 733:88]
+  wire  _T_3888 = _T_2231 & miss_state_en; // @[el2_ifu_mem_ctl.scala 735:37]
+  wire  _T_3889 = miss_nxtstate == 3'h3; // @[el2_ifu_mem_ctl.scala 735:71]
+  wire  _T_3890 = _T_3888 & _T_3889; // @[el2_ifu_mem_ctl.scala 735:54]
+  wire  _T_3891 = _T_3886 | _T_3890; // @[el2_ifu_mem_ctl.scala 734:57]
+  wire  _T_3892 = ~_T_3891; // @[el2_ifu_mem_ctl.scala 730:5]
+  wire  _T_3893 = _T_3867 & _T_3892; // @[el2_ifu_mem_ctl.scala 729:96]
+  wire  _T_3894 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 736:28]
+  wire  _T_3896 = _T_3894 & _T_3864; // @[el2_ifu_mem_ctl.scala 736:50]
+  wire  _T_3898 = _T_3896 & _T_3866; // @[el2_ifu_mem_ctl.scala 736:81]
+  wire  _T_3907 = ~_T_100; // @[el2_ifu_mem_ctl.scala 739:106]
+  wire  _T_3908 = _T_2216 & _T_3907; // @[el2_ifu_mem_ctl.scala 739:104]
+  wire  _T_3909 = _T_2231 | _T_3908; // @[el2_ifu_mem_ctl.scala 739:77]
+  wire  _T_3913 = ~_T_53; // @[el2_ifu_mem_ctl.scala 739:172]
+  wire  _T_3914 = _T_3909 & _T_3913; // @[el2_ifu_mem_ctl.scala 739:170]
+  wire  _T_3915 = ~_T_3914; // @[el2_ifu_mem_ctl.scala 739:44]
+  wire  _T_3919 = reset_ic_in | reset_ic_ff; // @[el2_ifu_mem_ctl.scala 741:62]
+  wire  _T_3920 = ~_T_3919; // @[el2_ifu_mem_ctl.scala 741:48]
+  wire  _T_3921 = _T_268 & _T_3920; // @[el2_ifu_mem_ctl.scala 741:46]
+  wire  _T_3922 = ~reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 741:79]
+  wire  ic_valid = _T_3921 & _T_3922; // @[el2_ifu_mem_ctl.scala 741:77]
+  wire  _T_3924 = debug_c1_clken & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 742:81]
+  reg [6:0] ifu_status_wr_addr_ff; // @[el2_ifu_mem_ctl.scala 744:61]
+  wire  way_status_wr_en_w_debug = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 746:73]
+  reg  ic_valid_ff; // @[el2_ifu_mem_ctl.scala 766:51]
   rvclkhdr rvclkhdr ( // @[el2_lib.scala 412:22]
     .io_clk(rvclkhdr_io_clk),
     .io_en(rvclkhdr_io_en),
@@ -1245,10 +1389,90 @@ module el2_ifu_mem_ctl(
     .io_en(rvclkhdr_1_io_en),
     .io_scan_mode(rvclkhdr_1_io_scan_mode)
   );
+  rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_2_io_clk),
+    .io_en(rvclkhdr_2_io_en),
+    .io_scan_mode(rvclkhdr_2_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_3_io_clk),
+    .io_en(rvclkhdr_3_io_en),
+    .io_scan_mode(rvclkhdr_3_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_4_io_clk),
+    .io_en(rvclkhdr_4_io_en),
+    .io_scan_mode(rvclkhdr_4_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_5_io_clk),
+    .io_en(rvclkhdr_5_io_en),
+    .io_scan_mode(rvclkhdr_5_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_6_io_clk),
+    .io_en(rvclkhdr_6_io_en),
+    .io_scan_mode(rvclkhdr_6_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_7_io_clk),
+    .io_en(rvclkhdr_7_io_en),
+    .io_scan_mode(rvclkhdr_7_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_8_io_clk),
+    .io_en(rvclkhdr_8_io_en),
+    .io_scan_mode(rvclkhdr_8_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_9_io_clk),
+    .io_en(rvclkhdr_9_io_en),
+    .io_scan_mode(rvclkhdr_9_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_10_io_clk),
+    .io_en(rvclkhdr_10_io_en),
+    .io_scan_mode(rvclkhdr_10_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_11_io_clk),
+    .io_en(rvclkhdr_11_io_en),
+    .io_scan_mode(rvclkhdr_11_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_12_io_clk),
+    .io_en(rvclkhdr_12_io_en),
+    .io_scan_mode(rvclkhdr_12_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_13_io_clk),
+    .io_en(rvclkhdr_13_io_en),
+    .io_scan_mode(rvclkhdr_13_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_14_io_clk),
+    .io_en(rvclkhdr_14_io_en),
+    .io_scan_mode(rvclkhdr_14_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_15_io_clk),
+    .io_en(rvclkhdr_15_io_en),
+    .io_scan_mode(rvclkhdr_15_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_16_io_clk),
+    .io_en(rvclkhdr_16_io_en),
+    .io_scan_mode(rvclkhdr_16_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_17_io_clk),
+    .io_en(rvclkhdr_17_io_en),
+    .io_scan_mode(rvclkhdr_17_io_scan_mode)
+  );
   assign io_ifu_miss_state_idle = 1'h0; // @[el2_ifu_mem_ctl.scala 131:25]
   assign io_ifu_ic_mb_empty = 1'h0; // @[el2_ifu_mem_ctl.scala 132:21]
   assign io_ic_dma_active = _T_12 | io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 133:19 el2_ifu_mem_ctl.scala 241:20]
-  assign io_ic_write_stall = 1'h0; // @[el2_ifu_mem_ctl.scala 134:20]
+  assign io_ic_write_stall = write_ic_16_bytes & _T_3915; // @[el2_ifu_mem_ctl.scala 134:20 el2_ifu_mem_ctl.scala 739:21]
   assign io_ifu_pmu_ic_miss = 1'h0; // @[el2_ifu_mem_ctl.scala 135:21]
   assign io_ifu_pmu_ic_hit = 1'h0; // @[el2_ifu_mem_ctl.scala 136:20]
   assign io_ifu_pmu_bus_error = 1'h0; // @[el2_ifu_mem_ctl.scala 137:23]
@@ -1288,8 +1512,8 @@ module el2_ifu_mem_ctl(
   assign io_iccm_dma_rtag = iccm_dma_rtag; // @[el2_ifu_mem_ctl.scala 171:19 el2_ifu_mem_ctl.scala 691:20]
   assign io_iccm_ready = 1'h0; // @[el2_ifu_mem_ctl.scala 172:16]
   assign io_ic_rw_addr = 31'h0; // @[el2_ifu_mem_ctl.scala 173:16]
-  assign io_ic_wr_en = 2'h0; // @[el2_ifu_mem_ctl.scala 174:14]
-  assign io_ic_rd_en = 1'h0; // @[el2_ifu_mem_ctl.scala 175:14]
+  assign io_ic_wr_en = 2'h0; // @[el2_ifu_mem_ctl.scala 174:14 el2_ifu_mem_ctl.scala 738:15]
+  assign io_ic_rd_en = _T_3893 | _T_3898; // @[el2_ifu_mem_ctl.scala 175:14 el2_ifu_mem_ctl.scala 729:15]
   assign io_ic_wr_data_0 = ic_wr_16bytes_data[70:0]; // @[el2_ifu_mem_ctl.scala 176:16 el2_ifu_mem_ctl.scala 391:17]
   assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[el2_ifu_mem_ctl.scala 176:16 el2_ifu_mem_ctl.scala 391:17]
   assign io_ic_debug_wr_data = io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu_mem_ctl.scala 177:22 el2_ifu_mem_ctl.scala 392:23]
@@ -1303,7 +1527,7 @@ module el2_ifu_mem_ctl(
   assign io_iccm_rw_addr = _T_3047[14:0]; // @[el2_ifu_mem_ctl.scala 180:18 el2_ifu_mem_ctl.scala 702:19]
   assign io_iccm_wren = _T_2616 | iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 181:15 el2_ifu_mem_ctl.scala 673:16]
   assign io_iccm_rden = _T_2620 | _T_2621; // @[el2_ifu_mem_ctl.scala 182:15 el2_ifu_mem_ctl.scala 674:16]
-  assign io_iccm_wr_data = _T_3022 ? 78'h0 : _T_3030; // @[el2_ifu_mem_ctl.scala 183:18 el2_ifu_mem_ctl.scala 679:19]
+  assign io_iccm_wr_data = _T_3022 ? _T_3023 : _T_3030; // @[el2_ifu_mem_ctl.scala 183:18 el2_ifu_mem_ctl.scala 679:19]
   assign io_iccm_wr_size = _T_2626 & io_dma_mem_sz; // @[el2_ifu_mem_ctl.scala 184:18 el2_ifu_mem_ctl.scala 676:19]
   assign io_ic_hit_f = _T_254 | ic_iccm_hit_f; // @[el2_ifu_mem_ctl.scala 185:14 el2_ifu_mem_ctl.scala 336:15]
   assign io_ic_access_fault_f = ifc_bus_acc_fault_f & _T_308; // @[el2_ifu_mem_ctl.scala 186:23 el2_ifu_mem_ctl.scala 430:24]
@@ -1320,13 +1544,61 @@ module el2_ifu_mem_ctl(
   assign io_ifu_ic_debug_rd_data_valid = 1'h0; // @[el2_ifu_mem_ctl.scala 197:32]
   assign io_iccm_buf_correct_ecc = 1'h0; // @[el2_ifu_mem_ctl.scala 198:26]
   assign io_iccm_correction_state = 1'h0; // @[el2_ifu_mem_ctl.scala 199:27]
-  assign io_test = {_T_3446,_T_3444}; // @[el2_ifu_mem_ctl.scala 466:11 el2_ifu_mem_ctl.scala 725:11]
+  assign io_test = ic_valid_ff; // @[el2_ifu_mem_ctl.scala 466:11 el2_ifu_mem_ctl.scala 767:11]
   assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 413:17]
   assign rvclkhdr_io_en = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_lib.scala 414:16]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
   assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 413:17]
   assign rvclkhdr_1_io_en = _T_1 | io_exu_flush_final; // @[el2_lib.scala 414:16]
   assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_2_io_en = ifu_status_wr_addr_ff[6:3] == 4'h0; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_3_io_en = ifu_status_wr_addr_ff[6:3] == 4'h1; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_4_io_en = ifu_status_wr_addr_ff[6:3] == 4'h2; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_5_io_en = ifu_status_wr_addr_ff[6:3] == 4'h3; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_6_io_en = ifu_status_wr_addr_ff[6:3] == 4'h4; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_7_io_en = ifu_status_wr_addr_ff[6:3] == 4'h5; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_8_io_en = ifu_status_wr_addr_ff[6:3] == 4'h6; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_9_io_en = ifu_status_wr_addr_ff[6:3] == 4'h7; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_10_io_en = ifu_status_wr_addr_ff[6:3] == 4'h8; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_11_io_en = ifu_status_wr_addr_ff[6:3] == 4'h9; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_12_io_en = ifu_status_wr_addr_ff[6:3] == 4'ha; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_13_io_en = ifu_status_wr_addr_ff[6:3] == 4'hb; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_14_io_en = ifu_status_wr_addr_ff[6:3] == 4'hc; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_15_io_en = ifu_status_wr_addr_ff[6:3] == 4'hd; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_16_io_en = ifu_status_wr_addr_ff[6:3] == 4'he; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_17_io_en = ifu_status_wr_addr_ff[6:3] == 4'hf; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -1381,91 +1653,111 @@ initial begin
   _RAND_8 = {1{`RANDOM}};
   err_stop_state = _RAND_8[1:0];
   _RAND_9 = {1{`RANDOM}};
-  ifu_bus_rvalid_unq_ff = _RAND_9[0:0];
+  reset_all_tags = _RAND_9[0:0];
   _RAND_10 = {1{`RANDOM}};
-  bus_ifu_bus_clk_en_ff = _RAND_10[0:0];
+  ifu_bus_rvalid_unq_ff = _RAND_10[0:0];
   _RAND_11 = {1{`RANDOM}};
-  uncacheable_miss_ff = _RAND_11[0:0];
+  bus_ifu_bus_clk_en_ff = _RAND_11[0:0];
   _RAND_12 = {1{`RANDOM}};
-  bus_data_beat_count = _RAND_12[2:0];
+  uncacheable_miss_ff = _RAND_12[0:0];
   _RAND_13 = {1{`RANDOM}};
-  ic_miss_buff_data_valid = _RAND_13[7:0];
+  bus_data_beat_count = _RAND_13[2:0];
   _RAND_14 = {1{`RANDOM}};
-  imb_ff = _RAND_14[30:0];
+  ic_miss_buff_data_valid = _RAND_14[7:0];
   _RAND_15 = {1{`RANDOM}};
-  last_data_recieved_ff = _RAND_15[0:0];
+  imb_ff = _RAND_15[30:0];
   _RAND_16 = {1{`RANDOM}};
-  sel_mb_addr_ff = _RAND_16[0:0];
+  last_data_recieved_ff = _RAND_16[0:0];
   _RAND_17 = {1{`RANDOM}};
-  imb_scnd_ff = _RAND_17[30:0];
+  sel_mb_addr_ff = _RAND_17[0:0];
   _RAND_18 = {1{`RANDOM}};
-  ifu_bus_rid_ff = _RAND_18[2:0];
+  imb_scnd_ff = _RAND_18[30:0];
   _RAND_19 = {1{`RANDOM}};
-  scnd_miss_req_q = _RAND_19[0:0];
+  ifu_bus_rid_ff = _RAND_19[2:0];
   _RAND_20 = {1{`RANDOM}};
-  miss_addr = _RAND_20[25:0];
+  ifu_bus_rresp_ff = _RAND_20[1:0];
   _RAND_21 = {1{`RANDOM}};
-  ifc_region_acc_fault_f = _RAND_21[0:0];
+  ifu_wr_data_comb_err_ff = _RAND_21[0:0];
   _RAND_22 = {1{`RANDOM}};
-  bus_rd_addr_count = _RAND_22[2:0];
+  scnd_miss_req_q = _RAND_22[0:0];
   _RAND_23 = {1{`RANDOM}};
-  ic_act_miss_f_delayed = _RAND_23[0:0];
-  _RAND_24 = {2{`RANDOM}};
-  ifu_bus_rdata_ff = _RAND_24[63:0];
-  _RAND_25 = {2{`RANDOM}};
-  _T_1284 = _RAND_25[63:0];
-  _RAND_26 = {2{`RANDOM}};
-  _T_1286 = _RAND_26[63:0];
-  _RAND_27 = {2{`RANDOM}};
-  _T_1288 = _RAND_27[63:0];
+  reset_ic_ff = _RAND_23[0:0];
+  _RAND_24 = {1{`RANDOM}};
+  miss_addr = _RAND_24[25:0];
+  _RAND_25 = {1{`RANDOM}};
+  ifc_region_acc_fault_f = _RAND_25[0:0];
+  _RAND_26 = {1{`RANDOM}};
+  bus_rd_addr_count = _RAND_26[2:0];
+  _RAND_27 = {1{`RANDOM}};
+  ic_act_miss_f_delayed = _RAND_27[0:0];
   _RAND_28 = {2{`RANDOM}};
-  _T_1290 = _RAND_28[63:0];
+  ifu_bus_rdata_ff = _RAND_28[63:0];
   _RAND_29 = {2{`RANDOM}};
-  _T_1292 = _RAND_29[63:0];
+  _T_1284 = _RAND_29[63:0];
   _RAND_30 = {2{`RANDOM}};
-  _T_1294 = _RAND_30[63:0];
+  _T_1286 = _RAND_30[63:0];
   _RAND_31 = {2{`RANDOM}};
-  _T_1296 = _RAND_31[63:0];
+  _T_1288 = _RAND_31[63:0];
   _RAND_32 = {2{`RANDOM}};
-  _T_1298 = _RAND_32[63:0];
+  _T_1290 = _RAND_32[63:0];
   _RAND_33 = {2{`RANDOM}};
-  _T_1300 = _RAND_33[63:0];
+  _T_1292 = _RAND_33[63:0];
   _RAND_34 = {2{`RANDOM}};
-  _T_1302 = _RAND_34[63:0];
+  _T_1294 = _RAND_34[63:0];
   _RAND_35 = {2{`RANDOM}};
-  _T_1304 = _RAND_35[63:0];
+  _T_1296 = _RAND_35[63:0];
   _RAND_36 = {2{`RANDOM}};
-  _T_1306 = _RAND_36[63:0];
+  _T_1298 = _RAND_36[63:0];
   _RAND_37 = {2{`RANDOM}};
-  _T_1308 = _RAND_37[63:0];
+  _T_1300 = _RAND_37[63:0];
   _RAND_38 = {2{`RANDOM}};
-  _T_1310 = _RAND_38[63:0];
+  _T_1302 = _RAND_38[63:0];
   _RAND_39 = {2{`RANDOM}};
-  _T_1312 = _RAND_39[63:0];
+  _T_1304 = _RAND_39[63:0];
   _RAND_40 = {2{`RANDOM}};
-  _T_1314 = _RAND_40[63:0];
-  _RAND_41 = {1{`RANDOM}};
-  ic_crit_wd_rdy_new_ff = _RAND_41[0:0];
-  _RAND_42 = {1{`RANDOM}};
-  ic_miss_buff_data_error = _RAND_42[7:0];
-  _RAND_43 = {3{`RANDOM}};
-  _T_1200 = _RAND_43[70:0];
-  _RAND_44 = {1{`RANDOM}};
-  ifu_bus_cmd_valid = _RAND_44[0:0];
+  _T_1306 = _RAND_40[63:0];
+  _RAND_41 = {2{`RANDOM}};
+  _T_1308 = _RAND_41[63:0];
+  _RAND_42 = {2{`RANDOM}};
+  _T_1310 = _RAND_42[63:0];
+  _RAND_43 = {2{`RANDOM}};
+  _T_1312 = _RAND_43[63:0];
+  _RAND_44 = {2{`RANDOM}};
+  _T_1314 = _RAND_44[63:0];
   _RAND_45 = {1{`RANDOM}};
-  bus_cmd_beat_count = _RAND_45[2:0];
+  ic_crit_wd_rdy_new_ff = _RAND_45[0:0];
   _RAND_46 = {1{`RANDOM}};
-  ifc_dma_access_ok_prev = _RAND_46[0:0];
-  _RAND_47 = {1{`RANDOM}};
-  dma_mem_addr_ff = _RAND_47[1:0];
+  ic_miss_buff_data_error = _RAND_46[7:0];
+  _RAND_47 = {3{`RANDOM}};
+  _T_1200 = _RAND_47[70:0];
   _RAND_48 = {1{`RANDOM}};
-  dma_mem_tag_ff = _RAND_48[2:0];
+  ifu_bus_cmd_valid = _RAND_48[0:0];
   _RAND_49 = {1{`RANDOM}};
-  iccm_dma_rtag = _RAND_49[2:0];
+  bus_cmd_beat_count = _RAND_49[2:0];
   _RAND_50 = {1{`RANDOM}};
-  iccm_dma_rvalid = _RAND_50[0:0];
+  ifc_dma_access_ok_prev = _RAND_50[0:0];
   _RAND_51 = {2{`RANDOM}};
-  iccm_dma_rdata = _RAND_51[63:0];
+  iccm_ecc_corr_data_ff = _RAND_51[38:0];
+  _RAND_52 = {1{`RANDOM}};
+  dma_mem_addr_ff = _RAND_52[1:0];
+  _RAND_53 = {1{`RANDOM}};
+  dma_mem_tag_ff = _RAND_53[2:0];
+  _RAND_54 = {1{`RANDOM}};
+  iccm_dma_rtag = _RAND_54[2:0];
+  _RAND_55 = {1{`RANDOM}};
+  iccm_dma_rvalid = _RAND_55[0:0];
+  _RAND_56 = {2{`RANDOM}};
+  iccm_dma_rdata = _RAND_56[63:0];
+  _RAND_57 = {1{`RANDOM}};
+  iccm_ecc_corr_index_ff = _RAND_57[13:0];
+  _RAND_58 = {1{`RANDOM}};
+  iccm_rd_ecc_single_err_ff = _RAND_58[0:0];
+  _RAND_59 = {1{`RANDOM}};
+  iccm_rw_addr_f = _RAND_59[13:0];
+  _RAND_60 = {1{`RANDOM}};
+  ifu_status_wr_addr_ff = _RAND_60[6:0];
+  _RAND_61 = {1{`RANDOM}};
+  ic_valid_ff = _RAND_61[0:0];
 `endif // RANDOMIZE_REG_INIT
   `endif // RANDOMIZE
 end // initial
@@ -1594,6 +1886,12 @@ end // initial
     end else if (io_ifu_bus_clk_en) begin
       ifu_bus_rid_ff <= io_ifu_axi_rid;
     end
+    if (reset) begin
+      ifu_bus_rresp_ff <= 2'h0;
+    end else if (io_ifu_bus_clk_en) begin
+      ifu_bus_rresp_ff <= io_ifu_axi_rresp;
+    end
+    reset_ic_ff <= _T_289 & _T_290;
     if (reset) begin
       miss_addr <= 26'h0;
     end else if (_T_223) begin
@@ -1818,6 +2116,11 @@ end // initial
     end else begin
       sel_mb_addr_ff <= sel_mb_addr;
     end
+    if (reset) begin
+      ifu_wr_data_comb_err_ff <= 1'h0;
+    end else begin
+      ifu_wr_data_comb_err_ff <= ifu_wr_cumulative_err;
+    end
     if (reset) begin
       scnd_miss_req_q <= 1'h0;
     end else begin
@@ -1843,6 +2146,11 @@ end // initial
     end else begin
       ifc_dma_access_ok_prev <= ifc_dma_access_ok_d;
     end
+    if (reset) begin
+      iccm_ecc_corr_data_ff <= 39'h0;
+    end else if (iccm_ecc_write_status) begin
+      iccm_ecc_corr_data_ff <= _T_3859;
+    end
     if (reset) begin
       dma_mem_addr_ff <= 2'h0;
     end else begin
@@ -1870,5 +2178,45 @@ end // initial
     end else begin
       iccm_dma_rdata <= _T_3035;
     end
+    if (reset) begin
+      iccm_ecc_corr_index_ff <= 14'h0;
+    end else if (iccm_ecc_write_status) begin
+      if (iccm_single_ecc_error[0]) begin
+        iccm_ecc_corr_index_ff <= iccm_rw_addr_f;
+      end else begin
+        iccm_ecc_corr_index_ff <= _T_3855;
+      end
+    end
+    if (reset) begin
+      iccm_rd_ecc_single_err_ff <= 1'h0;
+    end else begin
+      iccm_rd_ecc_single_err_ff <= iccm_rd_ecc_single_err_hold_in;
+    end
+    if (reset) begin
+      iccm_rw_addr_f <= 14'h0;
+    end else begin
+      iccm_rw_addr_f <= io_iccm_rw_addr[14:1];
+    end
+    if (reset) begin
+      ifu_status_wr_addr_ff <= 7'h0;
+    end else if (_T_3924) begin
+      ifu_status_wr_addr_ff <= io_ic_debug_addr[9:3];
+    end else begin
+      ifu_status_wr_addr_ff <= ifu_status_wr_addr[11:5];
+    end
+    if (reset) begin
+      ic_valid_ff <= 1'h0;
+    end else if (way_status_wr_en_w_debug) begin
+      ic_valid_ff <= io_ic_debug_wr_data[0];
+    end else begin
+      ic_valid_ff <= ic_valid;
+    end
+  end
+  always @(posedge io_active_clk) begin
+    if (reset) begin
+      reset_all_tags <= 1'h0;
+    end else begin
+      reset_all_tags <= io_dec_tlu_fence_i_wb;
+    end
   end
 endmodule
diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
index f49040fa..459668c9 100644
--- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
@@ -717,12 +717,64 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   val iccm_corrected_data_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_data(0), iccm_corrected_data(1))
   val iccm_corrected_ecc_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_ecc(0), iccm_corrected_ecc(1))
   val iccm_rd_ecc_single_err_ff = WireInit(Bool(), false.B)
-  val iccm_ecc_write_status = ((io.iccm_rd_ecc_single_err & !iccm_rd_ecc_single_err_ff) & !io.exu_flush_final) | io.iccm_dma_sb_error
+  val iccm_ecc_write_status = if(ICCM_ENABLE)((io.iccm_rd_ecc_single_err & !iccm_rd_ecc_single_err_ff) & !io.exu_flush_final) | io.iccm_dma_sb_error else 0.U
   val iccm_rd_ecc_single_err_hold_in = (io.iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff) & !io.exu_flush_final
   iccm_error_start := io.iccm_rd_ecc_single_err
   val iccm_rw_addr_f = WireInit(UInt((ICCM_BITS-2).W), 0.U)
   val iccm_ecc_corr_index_in = Mux(iccm_single_ecc_error(0).asBool(), iccm_rw_addr_f, iccm_rw_addr_f + 1.U)
-  io.test := iccm_corrected_ecc(0)
+  iccm_rw_addr_f := withClock(io.free_clk){RegNext(io.iccm_rw_addr(ICCM_BITS-2,1), 0.U)}
+  iccm_rd_ecc_single_err_ff := withClock(io.free_clk){RegNext(iccm_rd_ecc_single_err_hold_in, false.B)}
+  iccm_ecc_corr_data_ff := withClock(io.free_clk){RegEnable(Cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux), 0.U, iccm_ecc_write_status.asBool())}
+  iccm_ecc_corr_index_ff := withClock(io.free_clk){RegEnable(iccm_ecc_corr_index_in, 0.U, iccm_ecc_write_status.asBool())}
+  io.ic_rd_en := (io.ifc_fetch_req_bf & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf  &
+    !(((miss_state===stream_C) & !miss_state_en)                                       |
+      ((miss_state===crit_byp_ok_C) & !miss_state_en)                                  |
+      ((miss_state===stall_scnd_miss_C) & !miss_state_en)                              |
+      ((miss_state===miss_wait_C) & !miss_state_en)                                    |
+      ((miss_state===crit_wrd_rdy_C) & !miss_state_en)  |
+      ((miss_state===crit_byp_ok_C) &  miss_state_en &  (miss_nxtstate===miss_wait_C))  ))  |
+      (io.ifc_fetch_req_bf & io.exu_flush_final  & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf)
+  val bus_ic_wr_en = WireInit(Bool(), false.B)
+  io.ic_wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes)
+  io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff)))
+  reset_all_tags := withClock(io.active_clk){RegNext(io.dec_tlu_fence_i_wb, false.B)}
+  val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss
+  val ifu_status_wr_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en ) & io.ic_debug_tag_array, io.ic_debug_addr(ICACHE_INDEX_HI-3,ICACHE_TAG_INDEX_LO-3),
+    ifu_status_wr_addr(ICACHE_INDEX_HI-1,ICACHE_TAG_INDEX_LO-1))
+  val ifu_status_wr_addr_ff = withClock(io.free_clk){RegNext(ifu_status_wr_addr_w_debug, 0.U)}
+  val way_status_wr_en = WireInit(Bool(), false.B)
+  val way_status_wr_en_w_debug = way_status_wr_en | (io.ic_debug_wr_en  & io.ic_debug_tag_array)
+  val way_status_wr_en_ff = withClock(io.free_clk){RegNext(way_status_wr_en_w_debug, false.B)}
+  val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
+  val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
+    Mux((ICACHE_STATUS_BITS==1).B, io.ic_debug_wr_data(4), io.ic_debug_wr_data(6,4)), way_status_new)
+  val way_status_new_ff = withClock(io.free_clk){RegNext(way_status_new_w_debug, 0.U)}
+  val way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>ifu_status_wr_addr_ff(ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO,3)===i.U)
+  val way_status_clk = way_status_clken.map(rvclkhdr(clock, _ , io.scan_mode))
+  val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W)))
+  for(i<- 0 until ICACHE_TAG_DEPTH/8; j<- 0 until 8)
+  way_status_out(8*i+j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, ifu_status_wr_addr_ff===j.U & way_status_wr_en_ff)}
+  way_status := (0 until ICACHE_TAG_DEPTH).map(i=> Fill(ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO,ifu_ic_rw_int_addr_ff===i.U) & way_status_out(i)).reverse.reduce(Cat(_,_))
+  val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en ) & io.ic_debug_tag_array,
+    io.ic_debug_addr(ICACHE_INDEX_HI-3,ICACHE_TAG_INDEX_LO-3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI-1,ICACHE_TAG_INDEX_LO-1))
+  ifu_ic_rw_int_addr_ff := withClock(io.free_clk){RegNext(ifu_ic_rw_int_addr_w_debug, 0.U)}
+  val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
+  val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
+  val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en
+  val ifu_tag_wren_ff = withClock(io.free_clk){RegNext(ifu_tag_wren_w_debug, 0.U)}
+  val ic_valid_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, io.ic_debug_wr_data(0), ic_valid)
+  val ic_valid_ff = withClock(io.free_clk){RegNext(ic_valid_w_debug, false.B)}
+  val tag_valid_clken = (0 until ICACHE_TAG_DEPTH/32).map(i=>(0 until ICACHE_NUM_WAYS).map(j=>
+  if(ICACHE_TAG_DEPTH==32) (ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags)
+  else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO,5)===i.U) & ifu_tag_wren_ff(j)) |
+  ((perr_ic_index_ff(ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO,5)===i.U) & perr_err_inv_way(j)) |
+    reset_all_tags).reduce(Cat(_,_)))
+  val tag_valid_clk = (0 until ICACHE_TAG_DEPTH/32).map(i=>(0 until ICACHE_NUM_WAYS).map(j=>rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
+  val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, UInt(ICACHE_TAG_DEPTH.W)))
+  //for(i<-0 until )
+
+
+  io.test := ic_valid_ff
 }
 object ifu_mem extends App {
   println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl()))
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl$$anon$1.class
deleted file mode 100644
index 4551039e058e205aacded7b0393ca0e6ec4ea62a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
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