adder out 2 corrected

exu_div_new_2bit_fullshortq.fir

@@ -1159,7 +1159,7 @@ circuit exu_div_new_2bit_fullshortq :
     node _T_90 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 516:54]
     node _T_91 = add(_T_89, _T_90) @[exu_div_ctl.scala 516:48]
     node adder1_out = tail(_T_91, 1) @[exu_div_ctl.scala 516:48]
-    node _T_92 = bits(r_ff, 30, 0) @[exu_div_ctl.scala 517:28]
+    node _T_92 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 517:28]
     node _T_93 = bits(a_ff, 31, 30) @[exu_div_ctl.scala 517:39]
     node _T_94 = cat(_T_92, _T_93) @[Cat.scala 29:58]
     node _T_95 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 517:58]

exu_div_new_2bit_fullshortq.v

@@ -355,16 +355,16 @@ module exu_div_new_2bit_fullshortq(
   wire  _T_113 = adder3_out == 35'h0; // @[exu_div_ctl.scala 519:98]
   wire  _T_114 = _T_112 & _T_113; // @[exu_div_ctl.scala 519:84]
   wire  _T_115 = _T_110 | _T_114; // @[exu_div_ctl.scala 519:60]
-  wire [32:0] _T_94 = {r_ff[30:0],a_ff[31:30]}; // @[Cat.scala 29:58]
+  wire [33:0] _T_94 = {r_ff,a_ff[31:30]}; // @[Cat.scala 29:58]
   wire [33:0] _T_96 = {b_ff[32:0],1'h0}; // @[Cat.scala 29:58]
-  wire [33:0] _GEN_12 = {{1'd0}, _T_94}; // @[exu_div_ctl.scala 517:48]
-  wire [33:0] adder2_out = _GEN_12 + _T_96; // @[exu_div_ctl.scala 517:48]
+  wire [33:0] adder2_out = _T_94 + _T_96; // @[exu_div_ctl.scala 517:48]
   wire  _T_117 = ~adder2_out[33]; // @[exu_div_ctl.scala 520:6]
   wire  _T_118 = _T_117 ^ control_ff[2]; // @[exu_div_ctl.scala 520:22]
   wire  _T_121 = adder2_out == 34'h0; // @[exu_div_ctl.scala 520:80]
   wire  _T_122 = _T_112 & _T_121; // @[exu_div_ctl.scala 520:66]
   wire  _T_123 = _T_118 | _T_122; // @[exu_div_ctl.scala 520:42]
-  wire [32:0] adder1_out = _T_94 + b_ff[32:0]; // @[exu_div_ctl.scala 516:48]
+  wire [32:0] _T_89 = {r_ff[30:0],a_ff[31:30]}; // @[Cat.scala 29:58]
+  wire [32:0] adder1_out = _T_89 + b_ff[32:0]; // @[exu_div_ctl.scala 516:48]
   wire  _T_125 = ~adder1_out[32]; // @[exu_div_ctl.scala 521:6]
   wire  _T_126 = _T_125 ^ control_ff[2]; // @[exu_div_ctl.scala 521:22]
   wire  _T_129 = adder1_out == 33'h0; // @[exu_div_ctl.scala 521:80]

src/main/scala/exu/exu_div_ctl.scala

@@ -514,7 +514,7 @@ class exu_div_new_2bit_fullshortq extends Module with RequireAsyncReset with lib
   val r_adder2_sel         =  running_state & (quotient_new === 2.U) & !shortq_enable_ff
   val r_adder3_sel         =  running_state & (quotient_new === 3.U) & !shortq_enable_ff
   val adder1_out = Cat(r_ff(30,0),a_ff(31,30)) + b_ff(32,0)
-  val adder2_out = Cat(r_ff(30,0),a_ff(31,30)) + Cat(b_ff(32,0),0.U)
+  val adder2_out = Cat(r_ff(31,0),a_ff(31,30)) + Cat(b_ff(32,0),0.U)
   val adder3_out = Cat(r_ff(31),r_ff(31,0),a_ff(31,30)) + Cat(b_ff(33,0),0.U) + b_ff
   quotient_raw := Cat((!adder3_out(34) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder3_out === 0.U)),
     (!adder2_out(33) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder2_out === 0.U)),