colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

IFU complete

This commit is contained in:
waleed-lm 2020-11-02 10:14:16 +05:00
parent b328da3cec
commit 04329c474a
15 changed files with 58587 additions and 36822 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
el2_ifu_aln_ctl.anno.json
View File

@ -33,6 +33,11 @@
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"
}, },
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_ifu_aln_ctl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{ {
"class":"firrtl.options.TargetDirAnnotation", "class":"firrtl.options.TargetDirAnnotation",
"directory":"." "directory":"."

514
el2_ifu_aln_ctl.fir
View File

@ -1,5 +1,293 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_aln_ctl : circuit el2_ifu_aln_ctl :
extmodule TEC_RV_ICG :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
extmodule TEC_RV_ICG_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
extmodule TEC_RV_ICG_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
extmodule TEC_RV_ICG_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
extmodule TEC_RV_ICG_4 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_4 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
extmodule TEC_RV_ICG_5 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_5 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
extmodule TEC_RV_ICG_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
extmodule TEC_RV_ICG_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
extmodule TEC_RV_ICG_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_8 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
extmodule TEC_RV_ICG_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_9 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
extmodule TEC_RV_ICG_10 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_10 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
extmodule TEC_RV_ICG_11 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = TEC_RV_ICG
module rvclkhdr_11 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 459:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 460:14]
clkhdr.CK <= io.clk @[el2_lib.scala 461:18]
clkhdr.EN <= io.en @[el2_lib.scala 462:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 463:18]
module el2_ifu_compress_ctl : module el2_ifu_compress_ctl :
input clock : Clock input clock : Clock
input reset : Reset input reset : Reset
@ -1996,7 +2284,7 @@ circuit el2_ifu_aln_ctl :
module el2_ifu_aln_ctl : module el2_ifu_aln_ctl :
input clock : Clock input clock : Clock
input reset : AsyncReset input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}} output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<32>, way : UInt<1>, ret : UInt<1>}}
io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19] io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19]
io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18] io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18]
@ -2134,74 +2422,122 @@ circuit el2_ifu_aln_ctl :
q1off <= q1off_in @[el2_ifu_aln_ctl.scala 137:48] q1off <= q1off_in @[el2_ifu_aln_ctl.scala 137:48]
reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 138:48] reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 138:48]
q0off <= q0off_in @[el2_ifu_aln_ctl.scala 138:48] q0off <= q0off_in @[el2_ifu_aln_ctl.scala 138:48]
node _T_4 = bits(f2_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 140:55] node _T_4 = bits(f2_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 140:47]
reg f2pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] inst rvclkhdr of rvclkhdr @[el2_lib.scala 493:23]
when _T_4 : @[Reg.scala 28:19] rvclkhdr.clock <= clock
f2pc <= io.ifu_fetch_pc @[Reg.scala 28:23] rvclkhdr.reset <= reset
skip @[Reg.scala 28:19] rvclkhdr.io.clk <= clock @[el2_lib.scala 495:18]
node _T_5 = bits(f1_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 141:53] rvclkhdr.io.en <= _T_4 @[el2_lib.scala 496:17]
reg f1pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
when _T_5 : @[Reg.scala 28:19] reg f2pc : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
f1pc <= f1pc_in @[Reg.scala 28:23] f2pc <= io.ifu_fetch_pc @[el2_lib.scala 499:16]
skip @[Reg.scala 28:19] node _T_5 = bits(f1_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 141:45]
node _T_6 = bits(f0_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 142:53] inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 493:23]
reg f0pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] rvclkhdr_1.clock <= clock
when _T_6 : @[Reg.scala 28:19] rvclkhdr_1.reset <= reset
f0pc <= f0pc_in @[Reg.scala 28:23] rvclkhdr_1.io.clk <= clock @[el2_lib.scala 495:18]
skip @[Reg.scala 28:19] rvclkhdr_1.io.en <= _T_5 @[el2_lib.scala 496:17]
node _T_7 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 144:44] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
reg _T_8 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg f1pc : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
when _T_7 : @[Reg.scala 28:19] f1pc <= f1pc_in @[el2_lib.scala 499:16]
_T_8 <= brdata_in @[Reg.scala 28:23] node _T_6 = bits(f0_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 142:45]
skip @[Reg.scala 28:19] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 493:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 495:18]
rvclkhdr_2.io.en <= _T_6 @[el2_lib.scala 496:17]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
reg f0pc : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
f0pc <= f0pc_in @[el2_lib.scala 499:16]
node _T_7 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 144:36]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 493:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 495:18]
rvclkhdr_3.io.en <= _T_7 @[el2_lib.scala 496:17]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
reg _T_8 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
_T_8 <= brdata_in @[el2_lib.scala 499:16]
brdata2 <= _T_8 @[el2_ifu_aln_ctl.scala 144:11] brdata2 <= _T_8 @[el2_ifu_aln_ctl.scala 144:11]
node _T_9 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 145:44] node _T_9 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 145:36]
reg _T_10 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 493:23]
when _T_9 : @[Reg.scala 28:19] rvclkhdr_4.clock <= clock
_T_10 <= brdata_in @[Reg.scala 28:23] rvclkhdr_4.reset <= reset
skip @[Reg.scala 28:19] rvclkhdr_4.io.clk <= clock @[el2_lib.scala 495:18]
rvclkhdr_4.io.en <= _T_9 @[el2_lib.scala 496:17]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
reg _T_10 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
_T_10 <= brdata_in @[el2_lib.scala 499:16]
brdata1 <= _T_10 @[el2_ifu_aln_ctl.scala 145:11] brdata1 <= _T_10 @[el2_ifu_aln_ctl.scala 145:11]
node _T_11 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 146:44] node _T_11 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 146:36]
reg _T_12 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 493:23]
when _T_11 : @[Reg.scala 28:19] rvclkhdr_5.clock <= clock
_T_12 <= brdata_in @[Reg.scala 28:23] rvclkhdr_5.reset <= reset
skip @[Reg.scala 28:19] rvclkhdr_5.io.clk <= clock @[el2_lib.scala 495:18]
rvclkhdr_5.io.en <= _T_11 @[el2_lib.scala 496:17]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
reg _T_12 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
_T_12 <= brdata_in @[el2_lib.scala 499:16]
brdata0 <= _T_12 @[el2_ifu_aln_ctl.scala 146:11] brdata0 <= _T_12 @[el2_ifu_aln_ctl.scala 146:11]
node _T_13 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 148:45] node _T_13 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 148:37]
reg _T_14 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 493:23]
when _T_13 : @[Reg.scala 28:19] rvclkhdr_6.clock <= clock
_T_14 <= misc_data_in @[Reg.scala 28:23] rvclkhdr_6.reset <= reset
skip @[Reg.scala 28:19] rvclkhdr_6.io.clk <= clock @[el2_lib.scala 495:18]
rvclkhdr_6.io.en <= _T_13 @[el2_lib.scala 496:17]
rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
reg _T_14 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
_T_14 <= misc_data_in @[el2_lib.scala 499:16]
misc2 <= _T_14 @[el2_ifu_aln_ctl.scala 148:9] misc2 <= _T_14 @[el2_ifu_aln_ctl.scala 148:9]
node _T_15 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 149:45] node _T_15 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 149:37]
reg _T_16 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 493:23]
when _T_15 : @[Reg.scala 28:19] rvclkhdr_7.clock <= clock
_T_16 <= misc_data_in @[Reg.scala 28:23] rvclkhdr_7.reset <= reset
skip @[Reg.scala 28:19] rvclkhdr_7.io.clk <= clock @[el2_lib.scala 495:18]
rvclkhdr_7.io.en <= _T_15 @[el2_lib.scala 496:17]
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
reg _T_16 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
_T_16 <= misc_data_in @[el2_lib.scala 499:16]
misc1 <= _T_16 @[el2_ifu_aln_ctl.scala 149:9] misc1 <= _T_16 @[el2_ifu_aln_ctl.scala 149:9]
node _T_17 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 150:45] node _T_17 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 150:37]
reg _T_18 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 493:23]
when _T_17 : @[Reg.scala 28:19] rvclkhdr_8.clock <= clock
_T_18 <= misc_data_in @[Reg.scala 28:23] rvclkhdr_8.reset <= reset
skip @[Reg.scala 28:19] rvclkhdr_8.io.clk <= clock @[el2_lib.scala 495:18]
rvclkhdr_8.io.en <= _T_17 @[el2_lib.scala 496:17]
rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
reg _T_18 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
_T_18 <= misc_data_in @[el2_lib.scala 499:16]
misc0 <= _T_18 @[el2_ifu_aln_ctl.scala 150:9] misc0 <= _T_18 @[el2_ifu_aln_ctl.scala 150:9]
node _T_19 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 152:49] node _T_19 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 152:41]
reg _T_20 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 493:23]
when _T_19 : @[Reg.scala 28:19] rvclkhdr_9.clock <= clock
_T_20 <= io.ifu_fetch_data_f @[Reg.scala 28:23] rvclkhdr_9.reset <= reset
skip @[Reg.scala 28:19] rvclkhdr_9.io.clk <= clock @[el2_lib.scala 495:18]
rvclkhdr_9.io.en <= _T_19 @[el2_lib.scala 496:17]
rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
reg _T_20 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
_T_20 <= io.ifu_fetch_data_f @[el2_lib.scala 499:16]
q2 <= _T_20 @[el2_ifu_aln_ctl.scala 152:6] q2 <= _T_20 @[el2_ifu_aln_ctl.scala 152:6]
node _T_21 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 153:49] node _T_21 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 153:41]
reg _T_22 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 493:23]
when _T_21 : @[Reg.scala 28:19] rvclkhdr_10.clock <= clock
_T_22 <= io.ifu_fetch_data_f @[Reg.scala 28:23] rvclkhdr_10.reset <= reset
skip @[Reg.scala 28:19] rvclkhdr_10.io.clk <= clock @[el2_lib.scala 495:18]
rvclkhdr_10.io.en <= _T_21 @[el2_lib.scala 496:17]
rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
reg _T_22 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
_T_22 <= io.ifu_fetch_data_f @[el2_lib.scala 499:16]
q1 <= _T_22 @[el2_ifu_aln_ctl.scala 153:6] q1 <= _T_22 @[el2_ifu_aln_ctl.scala 153:6]
node _T_23 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 154:49] node _T_23 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 154:41]
reg _T_24 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 493:23]
when _T_23 : @[Reg.scala 28:19] rvclkhdr_11.clock <= clock
_T_24 <= io.ifu_fetch_data_f @[Reg.scala 28:23] rvclkhdr_11.reset <= reset
skip @[Reg.scala 28:19] rvclkhdr_11.io.clk <= clock @[el2_lib.scala 495:18]
rvclkhdr_11.io.en <= _T_23 @[el2_lib.scala 496:17]
rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 497:24]
reg _T_24 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 499:16]
_T_24 <= io.ifu_fetch_data_f @[el2_lib.scala 499:16]
q0 <= _T_24 @[el2_ifu_aln_ctl.scala 154:6] q0 <= _T_24 @[el2_ifu_aln_ctl.scala 154:6]
f2_wr_en <= fetch_to_f2 @[el2_ifu_aln_ctl.scala 156:18] f2_wr_en <= fetch_to_f2 @[el2_ifu_aln_ctl.scala 156:18]
node _T_25 = or(fetch_to_f1, shift_f2_f1) @[el2_ifu_aln_ctl.scala 157:33] node _T_25 = or(fetch_to_f1, shift_f2_f1) @[el2_ifu_aln_ctl.scala 157:33]
@ -3018,34 +3354,34 @@ circuit el2_ifu_aln_ctl :
wire _T_699 : UInt<32> @[Mux.scala 27:72] wire _T_699 : UInt<32> @[Mux.scala 27:72]
_T_699 <= _T_698 @[Mux.scala 27:72] _T_699 <= _T_698 @[Mux.scala 27:72]
io.ifu_i0_instr <= _T_699 @[el2_ifu_aln_ctl.scala 368:19] io.ifu_i0_instr <= _T_699 @[el2_ifu_aln_ctl.scala 368:19]
node _T_700 = bits(f0pc, 8, 1) @[el2_lib.scala 191:12] node _T_700 = bits(f0pc, 8, 1) @[el2_lib.scala 196:13]
node _T_701 = bits(f0pc, 16, 9) @[el2_lib.scala 191:50] node _T_701 = bits(f0pc, 16, 9) @[el2_lib.scala 196:51]
node _T_702 = xor(_T_700, _T_701) @[el2_lib.scala 191:46] node _T_702 = xor(_T_700, _T_701) @[el2_lib.scala 196:47]
node _T_703 = bits(f0pc, 24, 17) @[el2_lib.scala 191:88] node _T_703 = bits(f0pc, 24, 17) @[el2_lib.scala 196:89]
node firstpc_hash = xor(_T_702, _T_703) @[el2_lib.scala 191:84] node firstpc_hash = xor(_T_702, _T_703) @[el2_lib.scala 196:85]
node _T_704 = bits(secondpc, 8, 1) @[el2_lib.scala 191:12] node _T_704 = bits(secondpc, 8, 1) @[el2_lib.scala 196:13]
node _T_705 = bits(secondpc, 16, 9) @[el2_lib.scala 191:50] node _T_705 = bits(secondpc, 16, 9) @[el2_lib.scala 196:51]
node _T_706 = xor(_T_704, _T_705) @[el2_lib.scala 191:46] node _T_706 = xor(_T_704, _T_705) @[el2_lib.scala 196:47]
node _T_707 = bits(secondpc, 24, 17) @[el2_lib.scala 191:88] node _T_707 = bits(secondpc, 24, 17) @[el2_lib.scala 196:89]
node secondpc_hash = xor(_T_706, _T_707) @[el2_lib.scala 191:84] node secondpc_hash = xor(_T_706, _T_707) @[el2_lib.scala 196:85]
node _T_708 = bits(f0pc, 13, 9) @[el2_lib.scala 182:32] node _T_708 = bits(f0pc, 13, 9) @[el2_lib.scala 187:32]
node _T_709 = bits(f0pc, 18, 14) @[el2_lib.scala 182:32] node _T_709 = bits(f0pc, 18, 14) @[el2_lib.scala 187:32]
node _T_710 = bits(f0pc, 23, 19) @[el2_lib.scala 182:32] node _T_710 = bits(f0pc, 23, 19) @[el2_lib.scala 187:32]
wire _T_711 : UInt<5>[3] @[el2_lib.scala 182:24] wire _T_711 : UInt<5>[3] @[el2_lib.scala 187:24]
_T_711[0] <= _T_708 @[el2_lib.scala 182:24] _T_711[0] <= _T_708 @[el2_lib.scala 187:24]
_T_711[1] <= _T_709 @[el2_lib.scala 182:24] _T_711[1] <= _T_709 @[el2_lib.scala 187:24]
_T_711[2] <= _T_710 @[el2_lib.scala 182:24] _T_711[2] <= _T_710 @[el2_lib.scala 187:24]
node _T_712 = xor(_T_711[0], _T_711[1]) @[el2_lib.scala 182:111] node _T_712 = xor(_T_711[0], _T_711[1]) @[el2_lib.scala 187:111]
node firstbrtag_hash = xor(_T_712, _T_711[2]) @[el2_lib.scala 182:111] node firstbrtag_hash = xor(_T_712, _T_711[2]) @[el2_lib.scala 187:111]
node _T_713 = bits(secondpc, 13, 9) @[el2_lib.scala 182:32] node _T_713 = bits(secondpc, 13, 9) @[el2_lib.scala 187:32]
node _T_714 = bits(secondpc, 18, 14) @[el2_lib.scala 182:32] node _T_714 = bits(secondpc, 18, 14) @[el2_lib.scala 187:32]
node _T_715 = bits(secondpc, 23, 19) @[el2_lib.scala 182:32] node _T_715 = bits(secondpc, 23, 19) @[el2_lib.scala 187:32]
wire _T_716 : UInt<5>[3] @[el2_lib.scala 182:24] wire _T_716 : UInt<5>[3] @[el2_lib.scala 187:24]
_T_716[0] <= _T_713 @[el2_lib.scala 182:24] _T_716[0] <= _T_713 @[el2_lib.scala 187:24]
_T_716[1] <= _T_714 @[el2_lib.scala 182:24] _T_716[1] <= _T_714 @[el2_lib.scala 187:24]
_T_716[2] <= _T_715 @[el2_lib.scala 182:24] _T_716[2] <= _T_715 @[el2_lib.scala 187:24]
node _T_717 = xor(_T_716[0], _T_716[1]) @[el2_lib.scala 182:111] node _T_717 = xor(_T_716[0], _T_716[1]) @[el2_lib.scala 187:111]
node secondbrtag_hash = xor(_T_717, _T_716[2]) @[el2_lib.scala 182:111] node secondbrtag_hash = xor(_T_717, _T_716[2]) @[el2_lib.scala 187:111]
node _T_718 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 378:42] node _T_718 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 378:42]
node _T_719 = and(first2B, _T_718) @[el2_ifu_aln_ctl.scala 378:30] node _T_719 = and(first2B, _T_718) @[el2_ifu_aln_ctl.scala 378:30]
node _T_720 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 378:70] node _T_720 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 378:70]

393
el2_ifu_aln_ctl.v → el2_ifu_aln_ctl.sv
View File

@ -1,3 +1,38 @@
module TEC_RV_ICG(
(
input logic SE, EN, CK,
output Q
);
logic en_ff;
logic enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 459:26]
wire clkhdr_CK; // @[el2_lib.scala 459:26]
wire clkhdr_EN; // @[el2_lib.scala 459:26]
wire clkhdr_SE; // @[el2_lib.scala 459:26]
TEC_RV_ICG clkhdr ( // @[el2_lib.scala 459:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 460:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 461:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 462:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 463:18]
endmodule
module el2_ifu_compress_ctl( module el2_ifu_compress_ctl(
input [15:0] io_din, input [15:0] io_din,
output [31:0] io_dout output [31:0] io_dout
@ -551,7 +586,7 @@ module el2_ifu_aln_ctl(
output io_i0_brp_br_error, output io_i0_brp_br_error,
output io_i0_brp_br_start_error, output io_i0_brp_br_start_error,
output io_i0_brp_bank, output io_i0_brp_bank,
output [30:0] io_i0_brp_prett, output [31:0] io_i0_brp_prett,
output io_i0_brp_way, output io_i0_brp_way,
output io_i0_brp_ret output io_i0_brp_ret
); );
@ -578,6 +613,54 @@ module el2_ifu_aln_ctl(
reg [63:0] _RAND_19; reg [63:0] _RAND_19;
reg [63:0] _RAND_20; reg [63:0] _RAND_20;
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 493:23]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 493:23]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 493:23]
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 493:23]
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_4_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 493:23]
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_5_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 493:23]
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_6_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 493:23]
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_7_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 493:23]
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_8_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 493:23]
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_9_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 493:23]
wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_10_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_10_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 493:23]
wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_11_io_clk; // @[el2_lib.scala 493:23]
wire rvclkhdr_11_io_en; // @[el2_lib.scala 493:23]
wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 493:23]
wire [15:0] decompressed_io_din; // @[el2_ifu_aln_ctl.scala 366:28] wire [15:0] decompressed_io_din; // @[el2_ifu_aln_ctl.scala 366:28]
wire [31:0] decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 366:28] wire [31:0] decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 366:28]
reg error_stall; // @[el2_ifu_aln_ctl.scala 128:51] reg error_stall; // @[el2_ifu_aln_ctl.scala 128:51]
@ -604,11 +687,11 @@ module el2_ifu_aln_ctl(
wire _T_202 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 194:26] wire _T_202 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 194:26]
wire [1:0] q0sel = {q0ptr,_T_202}; // @[Cat.scala 29:58] wire [1:0] q0sel = {q0ptr,_T_202}; // @[Cat.scala 29:58]
wire [2:0] qren = {_T_188,_T_187,_T_186}; // @[Cat.scala 29:58] wire [2:0] qren = {_T_188,_T_187,_T_186}; // @[Cat.scala 29:58]
reg [31:0] q1; // @[Reg.scala 27:20] reg [31:0] q1; // @[el2_lib.scala 499:16]
reg [31:0] q0; // @[Reg.scala 27:20] reg [31:0] q0; // @[el2_lib.scala 499:16]
wire [63:0] _T_479 = {q1,q0}; // @[Cat.scala 29:58] wire [63:0] _T_479 = {q1,q0}; // @[Cat.scala 29:58]
wire [63:0] _T_486 = qren[0] ? _T_479 : 64'h0; // @[Mux.scala 27:72] wire [63:0] _T_486 = qren[0] ? _T_479 : 64'h0; // @[Mux.scala 27:72]
reg [31:0] q2; // @[Reg.scala 27:20] reg [31:0] q2; // @[el2_lib.scala 499:16]
wire [63:0] _T_482 = {q2,q1}; // @[Cat.scala 29:58] wire [63:0] _T_482 = {q2,q1}; // @[Cat.scala 29:58]
wire [63:0] _T_487 = qren[1] ? _T_482 : 64'h0; // @[Mux.scala 27:72] wire [63:0] _T_487 = qren[1] ? _T_482 : 64'h0; // @[Mux.scala 27:72]
wire [63:0] _T_489 = _T_486 | _T_487; // @[Mux.scala 27:72] wire [63:0] _T_489 = _T_486 | _T_487; // @[Mux.scala 27:72]
@ -618,8 +701,8 @@ module el2_ifu_aln_ctl(
wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 310:42] wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 310:42]
wire [31:0] _T_496 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_496 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72]
wire [15:0] _T_497 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_497 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72]
wire [31:0] _GEN_12 = {{16'd0}, _T_497}; // @[Mux.scala 27:72] wire [31:0] _GEN_0 = {{16'd0}, _T_497}; // @[Mux.scala 27:72]
wire [31:0] q0final = _T_496 | _GEN_12; // @[Mux.scala 27:72] wire [31:0] q0final = _T_496 | _GEN_0; // @[Mux.scala 27:72]
wire [31:0] _T_520 = f0val[1] ? q0final : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_520 = f0val[1] ? q0final : 32'h0; // @[Mux.scala 27:72]
wire _T_513 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 316:58] wire _T_513 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 316:58]
wire _T_515 = _T_513 & f0val[0]; // @[el2_ifu_aln_ctl.scala 316:68] wire _T_515 = _T_513 & f0val[0]; // @[el2_ifu_aln_ctl.scala 316:68]
@ -655,8 +738,8 @@ module el2_ifu_aln_ctl(
wire _T_417 = f1_shift_2B & f1val[1]; // @[Mux.scala 27:72] wire _T_417 = f1_shift_2B & f1val[1]; // @[Mux.scala 27:72]
wire _T_416 = ~f1_shift_2B; // @[el2_ifu_aln_ctl.scala 293:53] wire _T_416 = ~f1_shift_2B; // @[el2_ifu_aln_ctl.scala 293:53]
wire [1:0] _T_418 = _T_416 ? f1val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_418 = _T_416 ? f1val : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_13 = {{1'd0}, _T_417}; // @[Mux.scala 27:72] wire [1:0] _GEN_1 = {{1'd0}, _T_417}; // @[Mux.scala 27:72]
wire [1:0] sf1val = _GEN_13 | _T_418; // @[Mux.scala 27:72] wire [1:0] sf1val = _GEN_1 | _T_418; // @[Mux.scala 27:72]
wire sf1_valid = sf1val[0]; // @[el2_ifu_aln_ctl.scala 252:22] wire sf1_valid = sf1val[0]; // @[el2_ifu_aln_ctl.scala 252:22]
wire _T_352 = _T_351 & sf1_valid; // @[el2_ifu_aln_ctl.scala 272:37] wire _T_352 = _T_351 & sf1_valid; // @[el2_ifu_aln_ctl.scala 272:37]
wire f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 251:20] wire f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 251:20]
@ -668,7 +751,7 @@ module el2_ifu_aln_ctl(
wire _T_357 = _T_355 & _T_356; // @[el2_ifu_aln_ctl.scala 273:50] wire _T_357 = _T_355 & _T_356; // @[el2_ifu_aln_ctl.scala 273:50]
wire _T_358 = _T_357 & ifvalid; // @[el2_ifu_aln_ctl.scala 273:62] wire _T_358 = _T_357 & ifvalid; // @[el2_ifu_aln_ctl.scala 273:62]
wire fetch_to_f2 = _T_354 | _T_358; // @[el2_ifu_aln_ctl.scala 272:74] wire fetch_to_f2 = _T_354 | _T_358; // @[el2_ifu_aln_ctl.scala 272:74]
reg [30:0] f2pc; // @[Reg.scala 27:20] reg [30:0] f2pc; // @[el2_lib.scala 499:16]
wire _T_335 = ~sf1_valid; // @[el2_ifu_aln_ctl.scala 268:39] wire _T_335 = ~sf1_valid; // @[el2_ifu_aln_ctl.scala 268:39]
wire _T_336 = _T_351 & _T_335; // @[el2_ifu_aln_ctl.scala 268:37] wire _T_336 = _T_351 & _T_335; // @[el2_ifu_aln_ctl.scala 268:37]
wire _T_337 = _T_336 & f2_valid; // @[el2_ifu_aln_ctl.scala 268:50] wire _T_337 = _T_336 & f2_valid; // @[el2_ifu_aln_ctl.scala 268:50]
@ -681,42 +764,13 @@ module el2_ifu_aln_ctl(
wire _T_349 = _T_348 & ifvalid; // @[el2_ifu_aln_ctl.scala 270:62] wire _T_349 = _T_348 & ifvalid; // @[el2_ifu_aln_ctl.scala 270:62]
wire fetch_to_f1 = _T_344 | _T_349; // @[el2_ifu_aln_ctl.scala 269:74] wire fetch_to_f1 = _T_344 | _T_349; // @[el2_ifu_aln_ctl.scala 269:74]
wire _T_25 = fetch_to_f1 | _T_353; // @[el2_ifu_aln_ctl.scala 157:33] wire _T_25 = fetch_to_f1 | _T_353; // @[el2_ifu_aln_ctl.scala 157:33]
wire f1_shift_wr_en = _T_25 | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 157:47] reg [30:0] f1pc; // @[el2_lib.scala 499:16]
reg [30:0] f1pc; // @[Reg.scala 27:20]
wire [30:0] _T_375 = fetch_to_f1 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_376 = _T_353 ? f2pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_378 = _T_375 | _T_376; // @[Mux.scala 27:72]
wire _T_371 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 283:6]
wire _T_372 = ~_T_353; // @[el2_ifu_aln_ctl.scala 283:21]
wire _T_373 = _T_371 & _T_372; // @[el2_ifu_aln_ctl.scala 283:19]
wire [30:0] _T_363 = f1_shift_2B ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
wire [30:0] f1pc_plus1 = f1pc + 31'h1; // @[el2_ifu_aln_ctl.scala 277:25]
wire [30:0] _T_364 = _T_363 & f1pc_plus1; // @[el2_ifu_aln_ctl.scala 279:38]
wire [30:0] _T_367 = _T_416 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
wire [30:0] _T_368 = _T_367 & f1pc; // @[el2_ifu_aln_ctl.scala 279:78]
wire [30:0] sf1pc = _T_364 | _T_368; // @[el2_ifu_aln_ctl.scala 279:52]
wire [30:0] _T_377 = _T_373 ? sf1pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] f1pc_in = _T_378 | _T_377; // @[Mux.scala 27:72]
wire _T_332 = _T_336 & _T_356; // @[el2_ifu_aln_ctl.scala 267:50] wire _T_332 = _T_336 & _T_356; // @[el2_ifu_aln_ctl.scala 267:50]
wire fetch_to_f0 = _T_332 & ifvalid; // @[el2_ifu_aln_ctl.scala 267:62] wire fetch_to_f0 = _T_332 & ifvalid; // @[el2_ifu_aln_ctl.scala 267:62]
wire _T_27 = fetch_to_f0 | _T_337; // @[el2_ifu_aln_ctl.scala 158:33] wire _T_27 = fetch_to_f0 | _T_337; // @[el2_ifu_aln_ctl.scala 158:33]
wire _T_28 = _T_27 | _T_352; // @[el2_ifu_aln_ctl.scala 158:47] wire _T_28 = _T_27 | _T_352; // @[el2_ifu_aln_ctl.scala 158:47]
wire _T_29 = _T_28 | shift_2B; // @[el2_ifu_aln_ctl.scala 158:61] wire _T_29 = _T_28 | shift_2B; // @[el2_ifu_aln_ctl.scala 158:61]
wire f0_shift_wr_en = _T_29 | shift_4B; // @[el2_ifu_aln_ctl.scala 158:72] reg [30:0] f0pc; // @[el2_lib.scala 499:16]
reg [30:0] f0pc; // @[Reg.scala 27:20]
wire [30:0] _T_390 = fetch_to_f0 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_391 = _T_337 ? f2pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_394 = _T_390 | _T_391; // @[Mux.scala 27:72]
wire [30:0] _T_392 = _T_352 ? sf1pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_395 = _T_394 | _T_392; // @[Mux.scala 27:72]
wire _T_384 = ~fetch_to_f0; // @[el2_ifu_aln_ctl.scala 288:24]
wire _T_385 = ~_T_337; // @[el2_ifu_aln_ctl.scala 288:39]
wire _T_386 = _T_384 & _T_385; // @[el2_ifu_aln_ctl.scala 288:37]
wire _T_387 = ~_T_352; // @[el2_ifu_aln_ctl.scala 288:54]
wire _T_388 = _T_386 & _T_387; // @[el2_ifu_aln_ctl.scala 288:52]
wire [30:0] f0pc_plus1 = f0pc + 31'h1; // @[el2_ifu_aln_ctl.scala 275:25]
wire [30:0] _T_393 = _T_388 ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72]
wire [30:0] f0pc_in = _T_395 | _T_393; // @[Mux.scala 27:72]
wire _T_35 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 161:21] wire _T_35 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 161:21]
wire _T_36 = _T_35 & ifvalid; // @[el2_ifu_aln_ctl.scala 161:29] wire _T_36 = _T_35 & ifvalid; // @[el2_ifu_aln_ctl.scala 161:29]
wire _T_37 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 161:46] wire _T_37 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 161:46]
@ -724,15 +778,12 @@ module el2_ifu_aln_ctl(
wire _T_39 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 161:71] wire _T_39 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 161:71]
wire _T_40 = _T_39 & ifvalid; // @[el2_ifu_aln_ctl.scala 161:79] wire _T_40 = _T_39 & ifvalid; // @[el2_ifu_aln_ctl.scala 161:79]
wire [2:0] qwen = {_T_36,_T_38,_T_40}; // @[Cat.scala 29:58] wire [2:0] qwen = {_T_36,_T_38,_T_40}; // @[Cat.scala 29:58]
reg [11:0] brdata2; // @[Reg.scala 27:20] reg [11:0] brdata2; // @[el2_lib.scala 499:16]
wire [5:0] _T_241 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58] reg [11:0] brdata1; // @[el2_lib.scala 499:16]
wire [11:0] brdata_in = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1],_T_241}; // @[Cat.scala 29:58] reg [11:0] brdata0; // @[el2_lib.scala 499:16]
reg [11:0] brdata1; // @[Reg.scala 27:20] reg [54:0] misc2; // @[el2_lib.scala 499:16]
reg [11:0] brdata0; // @[Reg.scala 27:20] reg [54:0] misc1; // @[el2_lib.scala 499:16]
reg [54:0] misc2; // @[Reg.scala 27:20] reg [54:0] misc0; // @[el2_lib.scala 499:16]
wire [54:0] misc_data_in = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f,io_ifu_bp_btb_target_f,io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58]
reg [54:0] misc1; // @[Reg.scala 27:20]
reg [54:0] misc0; // @[Reg.scala 27:20]
wire _T_44 = qren[0] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 163:34] wire _T_44 = qren[0] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 163:34]
wire _T_46 = _T_44 & _T_1; // @[el2_ifu_aln_ctl.scala 163:55] wire _T_46 = _T_44 & _T_1; // @[el2_ifu_aln_ctl.scala 163:55]
wire _T_49 = qren[1] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 164:14] wire _T_49 = qren[1] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 164:14]
@ -748,19 +799,19 @@ module el2_ifu_aln_ctl(
wire [1:0] _T_80 = _T_51 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_80 = _T_51 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_82 = _T_61 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_82 = _T_61 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_85 = _T_77 ? rdptr : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_85 = _T_77 ? rdptr : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_14 = {{1'd0}, _T_46}; // @[Mux.scala 27:72] wire [1:0] _GEN_2 = {{1'd0}, _T_46}; // @[Mux.scala 27:72]
wire [1:0] _T_86 = _GEN_14 | _T_80; // @[Mux.scala 27:72] wire [1:0] _T_86 = _GEN_2 | _T_80; // @[Mux.scala 27:72]
wire [1:0] _T_88 = _T_86 | _T_82; // @[Mux.scala 27:72] wire [1:0] _T_88 = _T_86 | _T_82; // @[Mux.scala 27:72]
wire [1:0] _GEN_15 = {{1'd0}, _T_71}; // @[Mux.scala 27:72] wire [1:0] _GEN_3 = {{1'd0}, _T_71}; // @[Mux.scala 27:72]
wire [1:0] _T_90 = _T_88 | _GEN_15; // @[Mux.scala 27:72] wire [1:0] _T_90 = _T_88 | _GEN_3; // @[Mux.scala 27:72]
wire _T_95 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 171:34] wire _T_95 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 171:34]
wire _T_99 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 172:14] wire _T_99 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 172:14]
wire _T_105 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 174:6] wire _T_105 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 174:6]
wire _T_107 = _T_105 & _T_1; // @[el2_ifu_aln_ctl.scala 174:15] wire _T_107 = _T_105 & _T_1; // @[el2_ifu_aln_ctl.scala 174:15]
wire [1:0] _T_110 = _T_99 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_110 = _T_99 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_112 = _T_107 ? wrptr : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_112 = _T_107 ? wrptr : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_16 = {{1'd0}, _T_95}; // @[Mux.scala 27:72] wire [1:0] _GEN_4 = {{1'd0}, _T_95}; // @[Mux.scala 27:72]
wire [1:0] _T_113 = _GEN_16 | _T_110; // @[Mux.scala 27:72] wire [1:0] _T_113 = _GEN_4 | _T_110; // @[Mux.scala 27:72]
wire _T_118 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 176:26] wire _T_118 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 176:26]
wire _T_120 = _T_118 & _T_188; // @[el2_ifu_aln_ctl.scala 176:35] wire _T_120 = _T_118 & _T_188; // @[el2_ifu_aln_ctl.scala 176:35]
wire _T_795 = shift_2B & f0val[0]; // @[Mux.scala 27:72] wire _T_795 = shift_2B & f0val[0]; // @[Mux.scala 27:72]
@ -794,6 +845,8 @@ module el2_ifu_aln_ctl(
wire _T_181 = _T_172 & _T_174; // @[Mux.scala 27:72] wire _T_181 = _T_172 & _T_174; // @[Mux.scala 27:72]
wire _T_182 = _T_178 & q0off; // @[Mux.scala 27:72] wire _T_182 = _T_178 & q0off; // @[Mux.scala 27:72]
wire _T_183 = _T_180 | _T_181; // @[Mux.scala 27:72] wire _T_183 = _T_180 | _T_181; // @[Mux.scala 27:72]
wire [50:0] _T_205 = {io_ifu_bp_btb_target_f,io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58]
wire [3:0] _T_207 = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f}; // @[Cat.scala 29:58]
wire [109:0] _T_211 = {misc1,misc0}; // @[Cat.scala 29:58] wire [109:0] _T_211 = {misc1,misc0}; // @[Cat.scala 29:58]
wire [109:0] _T_214 = {misc2,misc1}; // @[Cat.scala 29:58] wire [109:0] _T_214 = {misc2,misc1}; // @[Cat.scala 29:58]
wire [109:0] _T_217 = {misc0,misc2}; // @[Cat.scala 29:58] wire [109:0] _T_217 = {misc0,misc2}; // @[Cat.scala 29:58]
@ -816,6 +869,8 @@ module el2_ifu_aln_ctl(
wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 219:25] wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 219:25]
wire [11:0] f0poffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 220:27] wire [11:0] f0poffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 220:27]
wire [7:0] f0fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 221:24] wire [7:0] f0fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 221:24]
wire [5:0] _T_241 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58]
wire [5:0] _T_246 = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1]}; // @[Cat.scala 29:58]
wire [23:0] _T_250 = {brdata1,brdata0}; // @[Cat.scala 29:58] wire [23:0] _T_250 = {brdata1,brdata0}; // @[Cat.scala 29:58]
wire [23:0] _T_253 = {brdata2,brdata1}; // @[Cat.scala 29:58] wire [23:0] _T_253 = {brdata2,brdata1}; // @[Cat.scala 29:58]
wire [23:0] _T_256 = {brdata0,brdata2}; // @[Cat.scala 29:58] wire [23:0] _T_256 = {brdata0,brdata2}; // @[Cat.scala 29:58]
@ -828,12 +883,12 @@ module el2_ifu_aln_ctl(
wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 231:61] wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 231:61]
wire [11:0] _T_267 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_267 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72]
wire [5:0] _T_268 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72] wire [5:0] _T_268 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72]
wire [11:0] _GEN_17 = {{6'd0}, _T_268}; // @[Mux.scala 27:72] wire [11:0] _GEN_5 = {{6'd0}, _T_268}; // @[Mux.scala 27:72]
wire [11:0] brdata0final = _T_267 | _GEN_17; // @[Mux.scala 27:72] wire [11:0] brdata0final = _T_267 | _GEN_5; // @[Mux.scala 27:72]
wire [11:0] _T_275 = q1sel[0] ? brdata1eff : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_275 = q1sel[0] ? brdata1eff : 12'h0; // @[Mux.scala 27:72]
wire [5:0] _T_276 = q1sel[1] ? brdata1eff[11:6] : 6'h0; // @[Mux.scala 27:72] wire [5:0] _T_276 = q1sel[1] ? brdata1eff[11:6] : 6'h0; // @[Mux.scala 27:72]
wire [11:0] _GEN_18 = {{6'd0}, _T_276}; // @[Mux.scala 27:72] wire [11:0] _GEN_6 = {{6'd0}, _T_276}; // @[Mux.scala 27:72]
wire [11:0] brdata1final = _T_275 | _GEN_18; // @[Mux.scala 27:72] wire [11:0] brdata1final = _T_275 | _GEN_6; // @[Mux.scala 27:72]
wire [1:0] f0ret = {brdata0final[6],brdata0final[0]}; // @[Cat.scala 29:58] wire [1:0] f0ret = {brdata0final[6],brdata0final[0]}; // @[Cat.scala 29:58]
wire [1:0] f0brend = {brdata0final[7],brdata0final[1]}; // @[Cat.scala 29:58] wire [1:0] f0brend = {brdata0final[7],brdata0final[1]}; // @[Cat.scala 29:58]
wire [1:0] f0way = {brdata0final[8],brdata0final[2]}; // @[Cat.scala 29:58] wire [1:0] f0way = {brdata0final[8],brdata0final[2]}; // @[Cat.scala 29:58]
@ -851,6 +906,31 @@ module el2_ifu_aln_ctl(
wire _T_311 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 258:39] wire _T_311 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 258:39]
wire _T_312 = consume_fb0 & _T_311; // @[el2_ifu_aln_ctl.scala 258:37] wire _T_312 = consume_fb0 & _T_311; // @[el2_ifu_aln_ctl.scala 258:37]
wire _T_315 = consume_fb0 & consume_fb1; // @[el2_ifu_aln_ctl.scala 259:37] wire _T_315 = consume_fb0 & consume_fb1; // @[el2_ifu_aln_ctl.scala 259:37]
wire [30:0] f0pc_plus1 = f0pc + 31'h1; // @[el2_ifu_aln_ctl.scala 275:25]
wire [30:0] f1pc_plus1 = f1pc + 31'h1; // @[el2_ifu_aln_ctl.scala 277:25]
wire [30:0] _T_363 = f1_shift_2B ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
wire [30:0] _T_364 = _T_363 & f1pc_plus1; // @[el2_ifu_aln_ctl.scala 279:38]
wire [30:0] _T_367 = _T_416 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
wire [30:0] _T_368 = _T_367 & f1pc; // @[el2_ifu_aln_ctl.scala 279:78]
wire [30:0] sf1pc = _T_364 | _T_368; // @[el2_ifu_aln_ctl.scala 279:52]
wire _T_371 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 283:6]
wire _T_372 = ~_T_353; // @[el2_ifu_aln_ctl.scala 283:21]
wire _T_373 = _T_371 & _T_372; // @[el2_ifu_aln_ctl.scala 283:19]
wire [30:0] _T_375 = fetch_to_f1 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_376 = _T_353 ? f2pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_377 = _T_373 ? sf1pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_378 = _T_375 | _T_376; // @[Mux.scala 27:72]
wire _T_384 = ~fetch_to_f0; // @[el2_ifu_aln_ctl.scala 288:24]
wire _T_385 = ~_T_337; // @[el2_ifu_aln_ctl.scala 288:39]
wire _T_386 = _T_384 & _T_385; // @[el2_ifu_aln_ctl.scala 288:37]
wire _T_387 = ~_T_352; // @[el2_ifu_aln_ctl.scala 288:54]
wire _T_388 = _T_386 & _T_387; // @[el2_ifu_aln_ctl.scala 288:52]
wire [30:0] _T_390 = fetch_to_f0 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_391 = _T_337 ? f2pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_392 = _T_352 ? sf1pc : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_393 = _T_388 ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_394 = _T_390 | _T_391; // @[Mux.scala 27:72]
wire [30:0] _T_395 = _T_394 | _T_392; // @[Mux.scala 27:72]
wire _T_399 = fetch_to_f2 & _T_1; // @[el2_ifu_aln_ctl.scala 290:38] wire _T_399 = fetch_to_f2 & _T_1; // @[el2_ifu_aln_ctl.scala 290:38]
wire _T_401 = ~fetch_to_f2; // @[el2_ifu_aln_ctl.scala 291:25] wire _T_401 = ~fetch_to_f2; // @[el2_ifu_aln_ctl.scala 291:25]
wire _T_403 = _T_401 & _T_372; // @[el2_ifu_aln_ctl.scala 291:38] wire _T_403 = _T_401 & _T_372; // @[el2_ifu_aln_ctl.scala 291:38]
@ -883,8 +963,8 @@ module el2_ifu_aln_ctl(
wire [1:0] _T_542 = {f1icaf,f0icaf}; // @[Cat.scala 29:58] wire [1:0] _T_542 = {f1icaf,f0icaf}; // @[Cat.scala 29:58]
wire _T_543 = f0val[1] & f0icaf; // @[Mux.scala 27:72] wire _T_543 = f0val[1] & f0icaf; // @[Mux.scala 27:72]
wire [1:0] _T_544 = _T_515 ? _T_542 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_544 = _T_515 ? _T_542 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_19 = {{1'd0}, _T_543}; // @[Mux.scala 27:72] wire [1:0] _GEN_7 = {{1'd0}, _T_543}; // @[Mux.scala 27:72]
wire [1:0] alignicaf = _GEN_19 | _T_544; // @[Mux.scala 27:72] wire [1:0] alignicaf = _GEN_7 | _T_544; // @[Mux.scala 27:72]
wire [1:0] _T_549 = f0dbecc ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_549 = f0dbecc ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_555 = {f1dbecc,f0dbecc}; // @[Cat.scala 29:58] wire [1:0] _T_555 = {f1dbecc,f0dbecc}; // @[Cat.scala 29:58]
wire [1:0] _T_556 = f0val[1] ? _T_549 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_556 = f0val[1] ? _T_549 : 2'h0; // @[Mux.scala 27:72]
@ -935,14 +1015,14 @@ module el2_ifu_aln_ctl(
wire _T_691 = first2B & aligndbecc[0]; // @[Mux.scala 27:72] wire _T_691 = first2B & aligndbecc[0]; // @[Mux.scala 27:72]
wire [31:0] _T_696 = first4B ? aligndata : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_696 = first4B ? aligndata : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_697 = first2B ? decompressed_io_dout : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_697 = first2B ? decompressed_io_dout : 32'h0; // @[Mux.scala 27:72]
wire [7:0] _T_702 = f0pc[8:1] ^ f0pc[16:9]; // @[el2_lib.scala 191:46] wire [7:0] _T_702 = f0pc[8:1] ^ f0pc[16:9]; // @[el2_lib.scala 196:47]
wire [7:0] firstpc_hash = _T_702 ^ f0pc[24:17]; // @[el2_lib.scala 191:84] wire [7:0] firstpc_hash = _T_702 ^ f0pc[24:17]; // @[el2_lib.scala 196:85]
wire [7:0] _T_706 = secondpc[8:1] ^ secondpc[16:9]; // @[el2_lib.scala 191:46] wire [7:0] _T_706 = secondpc[8:1] ^ secondpc[16:9]; // @[el2_lib.scala 196:47]
wire [7:0] secondpc_hash = _T_706 ^ secondpc[24:17]; // @[el2_lib.scala 191:84] wire [7:0] secondpc_hash = _T_706 ^ secondpc[24:17]; // @[el2_lib.scala 196:85]
wire [4:0] _T_712 = f0pc[13:9] ^ f0pc[18:14]; // @[el2_lib.scala 182:111] wire [4:0] _T_712 = f0pc[13:9] ^ f0pc[18:14]; // @[el2_lib.scala 187:111]
wire [4:0] firstbrtag_hash = _T_712 ^ f0pc[23:19]; // @[el2_lib.scala 182:111] wire [4:0] firstbrtag_hash = _T_712 ^ f0pc[23:19]; // @[el2_lib.scala 187:111]
wire [4:0] _T_717 = secondpc[13:9] ^ secondpc[18:14]; // @[el2_lib.scala 182:111] wire [4:0] _T_717 = secondpc[13:9] ^ secondpc[18:14]; // @[el2_lib.scala 187:111]
wire [4:0] secondbrtag_hash = _T_717 ^ secondpc[23:19]; // @[el2_lib.scala 182:111] wire [4:0] secondbrtag_hash = _T_717 ^ secondpc[23:19]; // @[el2_lib.scala 187:111]
wire _T_719 = first2B & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:30] wire _T_719 = first2B & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:30]
wire _T_721 = first4B & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 378:58] wire _T_721 = first4B & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 378:58]
wire _T_722 = _T_719 | _T_721; // @[el2_ifu_aln_ctl.scala 378:47] wire _T_722 = _T_719 | _T_721; // @[el2_ifu_aln_ctl.scala 378:47]
@ -960,11 +1040,84 @@ module el2_ifu_aln_ctl(
wire _T_751 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 387:42] wire _T_751 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 387:42]
wire _T_752 = _T_749 | _T_751; // @[el2_ifu_aln_ctl.scala 387:31] wire _T_752 = _T_749 | _T_751; // @[el2_ifu_aln_ctl.scala 387:31]
wire i0_ends_f1 = first4B & _T_515; // @[el2_ifu_aln_ctl.scala 389:28] wire i0_ends_f1 = first4B & _T_515; // @[el2_ifu_aln_ctl.scala 389:28]
wire [30:0] _T_757 = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:25]
wire _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:42] wire _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:42]
wire _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:56] wire _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:56]
wire _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:89] wire _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:89]
wire _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:87] wire _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:87]
wire _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:101] wire _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:101]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_4_io_l1clk),
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en),
.io_scan_mode(rvclkhdr_4_io_scan_mode)
);
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_5_io_l1clk),
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode)
);
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_6_io_l1clk),
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en),
.io_scan_mode(rvclkhdr_6_io_scan_mode)
);
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_7_io_l1clk),
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en),
.io_scan_mode(rvclkhdr_7_io_scan_mode)
);
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_8_io_l1clk),
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en),
.io_scan_mode(rvclkhdr_8_io_scan_mode)
);
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_9_io_l1clk),
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en),
.io_scan_mode(rvclkhdr_9_io_scan_mode)
);
rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_10_io_l1clk),
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en),
.io_scan_mode(rvclkhdr_10_io_scan_mode)
);
rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 493:23]
.io_l1clk(rvclkhdr_11_io_l1clk),
.io_clk(rvclkhdr_11_io_clk),
.io_en(rvclkhdr_11_io_en),
.io_scan_mode(rvclkhdr_11_io_scan_mode)
);
el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 366:28] el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 366:28]
.io_din(decompressed_io_din), .io_din(decompressed_io_din),
.io_dout(decompressed_io_dout) .io_dout(decompressed_io_dout)
@ -990,9 +1143,45 @@ module el2_ifu_aln_ctl(
assign io_i0_brp_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:22] assign io_i0_brp_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:22]
assign io_i0_brp_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29] assign io_i0_brp_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29]
assign io_i0_brp_bank = _T_738 ? f0pc[0] : secondpc[0]; // @[el2_ifu_aln_ctl.scala 396:29] assign io_i0_brp_bank = _T_738 ? f0pc[0] : secondpc[0]; // @[el2_ifu_aln_ctl.scala 396:29]
assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:19] assign io_i0_brp_prett = {{1'd0}, _T_757}; // @[el2_ifu_aln_ctl.scala 392:19]
assign io_i0_brp_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17] assign io_i0_brp_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17]
assign io_i0_brp_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:17] assign io_i0_brp_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:17]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_io_en = _T_354 | _T_358; // @[el2_lib.scala 496:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_1_io_en = _T_25 | f1_shift_2B; // @[el2_lib.scala 496:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_2_io_en = _T_29 | shift_4B; // @[el2_lib.scala 496:17]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_3_io_en = qwen[2]; // @[el2_lib.scala 496:17]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_4_io_en = qwen[1]; // @[el2_lib.scala 496:17]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_5_io_en = qwen[0]; // @[el2_lib.scala 496:17]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_6_io_en = qwen[2]; // @[el2_lib.scala 496:17]
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_7_io_en = qwen[1]; // @[el2_lib.scala 496:17]
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_8_io_en = qwen[0]; // @[el2_lib.scala 496:17]
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_9_io_en = qwen[2]; // @[el2_lib.scala 496:17]
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_10_io_en = qwen[1]; // @[el2_lib.scala 496:17]
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 495:18]
assign rvclkhdr_11_io_en = qwen[0]; // @[el2_lib.scala 496:17]
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 497:24]
assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 406:23] assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 406:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
@ -1204,88 +1393,88 @@ end // initial
q0off <= _T_183 | _T_182; q0off <= _T_183 | _T_182;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
q1 <= 32'h0; q1 <= 32'h0;
end else if (qwen[1]) begin end else begin
q1 <= io_ifu_fetch_data_f; q1 <= io_ifu_fetch_data_f;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
q0 <= 32'h0; q0 <= 32'h0;
end else if (qwen[0]) begin end else begin
q0 <= io_ifu_fetch_data_f; q0 <= io_ifu_fetch_data_f;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
q2 <= 32'h0; q2 <= 32'h0;
end else if (qwen[2]) begin end else begin
q2 <= io_ifu_fetch_data_f; q2 <= io_ifu_fetch_data_f;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
f2pc <= 31'h0; f2pc <= 31'h0;
end else if (fetch_to_f2) begin end else begin
f2pc <= io_ifu_fetch_pc; f2pc <= io_ifu_fetch_pc;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
f1pc <= 31'h0; f1pc <= 31'h0;
end else if (f1_shift_wr_en) begin end else begin
f1pc <= f1pc_in; f1pc <= _T_378 | _T_377;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
f0pc <= 31'h0; f0pc <= 31'h0;
end else if (f0_shift_wr_en) begin end else begin
f0pc <= f0pc_in; f0pc <= _T_395 | _T_393;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
brdata2 <= 12'h0; brdata2 <= 12'h0;
end else if (qwen[2]) begin end else begin
brdata2 <= brdata_in; brdata2 <= {_T_246,_T_241};
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
brdata1 <= 12'h0; brdata1 <= 12'h0;
end else if (qwen[1]) begin end else begin
brdata1 <= brdata_in; brdata1 <= {_T_246,_T_241};
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
brdata0 <= 12'h0; brdata0 <= 12'h0;
end else if (qwen[0]) begin end else begin
brdata0 <= brdata_in; brdata0 <= {_T_246,_T_241};
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
misc2 <= 55'h0; misc2 <= 55'h0;
end else if (qwen[2]) begin end else begin
misc2 <= misc_data_in; misc2 <= {_T_207,_T_205};
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
misc1 <= 55'h0; misc1 <= 55'h0;
end else if (qwen[1]) begin end else begin
misc1 <= misc_data_in; misc1 <= {_T_207,_T_205};
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
misc0 <= 55'h0; misc0 <= 55'h0;
end else if (qwen[0]) begin end else begin
misc0 <= misc_data_in; misc0 <= {_T_207,_T_205};
end end
end end
endmodule endmodule

5
el2_ifu_bp_ctl.anno.json
View File

@ -134,6 +134,11 @@
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"
}, },
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_ifu_bp_ctl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{ {
"class":"firrtl.options.TargetDirAnnotation", "class":"firrtl.options.TargetDirAnnotation",
"directory":"." "directory":"."

69083
el2_ifu_bp_ctl.fir
View File

File diff suppressed because it is too large Load Diff

24003
el2_ifu_bp_ctl.v
View File

File diff suppressed because it is too large Load Diff

24
src/main/scala/ifu/el2_ifu_aln_ctl.scala
View File

@ -137,21 +137,21 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)} val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)} val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
val f2pc = RegEnable(io.ifu_fetch_pc, 0.U, f2_wr_en.asBool) val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode)
val f1pc = RegEnable(f1pc_in, 0.U, f1_shift_wr_en.asBool) val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode)
val f0pc = RegEnable(f0pc_in, 0.U, f0_shift_wr_en.asBool) val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode)
brdata2 := RegEnable(brdata_in, 0.U, qwen(2)) brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode)
brdata1 := RegEnable(brdata_in, 0.U, qwen(1)) brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode)
brdata0 := RegEnable(brdata_in, 0.U, qwen(0)) brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode)
misc2 := RegEnable(misc_data_in, 0.U, qwen(2)) misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode)
misc1 := RegEnable(misc_data_in, 0.U, qwen(1)) misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode)
misc0 := RegEnable(misc_data_in, 0.U, qwen(0)) misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode)
q2 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(2)) q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode)
q1 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(1)) q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode)
q0 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(0)) q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode)
f2_wr_en := fetch_to_f2 f2_wr_en := fetch_to_f2
f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B

19
src/main/scala/ifu/el2_ifu_bp_ctl.scala
View File

@ -39,6 +39,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val ifu_bp_valid_f = Output(UInt(2.W)) val ifu_bp_valid_f = Output(UInt(2.W))
val ifu_bp_poffset_f = Output(UInt(12.W)) val ifu_bp_poffset_f = Output(UInt(12.W))
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val test = Output(UInt())
}) })
val TAG_START = 16+BTB_BTAG_SIZE val TAG_START = 16+BTB_BTAG_SIZE
@ -64,6 +65,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val btb_bank0_rd_data_way1_p1_f = WireInit(UInt((TAG_START+1).W), 0.U) val btb_bank0_rd_data_way1_p1_f = WireInit(UInt((TAG_START+1).W), 0.U)
val eoc_mask = WireInit(Bool(), 0.U) val eoc_mask = WireInit(Bool(), 0.U)
val btb_lru_b0_f = WireInit(UInt(LRU_SIZE.W), init = 0.U) val btb_lru_b0_f = WireInit(UInt(LRU_SIZE.W), init = 0.U)
io.test := btb_lru_b0_f
val dec_tlu_way_wb = WireInit(Bool(), 0.U) val dec_tlu_way_wb = WireInit(Bool(), 0.U)
///////////////////////////////////////////////////////// /////////////////////////////////////////////////////////
// Misprediction packet // Misprediction packet
@ -225,7 +227,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val use_mp_way_p1 = fetch_mp_collision_p1_f val use_mp_way_p1 = fetch_mp_collision_p1_f
// Calculate the lru next value and flop it // Calculate the lru next value and flop it
val btb_lru_b0_ns = Mux1H(Seq(!exu_mp_way.asBool -> mp_wrlru_b0, val btb_lru_b0_ns : UInt = Mux1H(Seq(!exu_mp_way.asBool -> mp_wrlru_b0,
tag_match_way0_f.asBool -> fetch_wrlru_b0, tag_match_way0_f.asBool -> fetch_wrlru_b0,
tag_match_way0_p1_f.asBool -> fetch_wrlru_p1_b0)) | btb_lru_b0_hold & btb_lru_b0_f tag_match_way0_p1_f.asBool -> fetch_wrlru_p1_b0)) | btb_lru_b0_hold & btb_lru_b0_f
@ -245,8 +247,8 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
io.ifu_bp_way_f := tag_match_vway1_expanded_f | (~vwayhit_f & btb_vlru_rd_f) io.ifu_bp_way_f := tag_match_vway1_expanded_f | (~vwayhit_f & btb_vlru_rd_f)
// update the lru // update the lru
btb_lru_b0_f := RegEnable(btb_lru_b0_ns, init = 0.U, (io.ifc_fetch_req_f|exu_mp_valid).asBool) btb_lru_b0_f := rvdffe(btb_lru_b0_ns, (io.ifc_fetch_req_f|exu_mp_valid).asBool, clock, io.scan_mode)
//io.test := btb_lru_b0_ns
// Checking if the end of line is near // Checking if the end of line is near
val eoc_near = io.ifc_fetch_addr_f(ICACHE_BEAT_ADDR_HI-1, 2).andR val eoc_near = io.ifc_fetch_addr_f(ICACHE_BEAT_ADDR_HI-1, 2).andR
@ -349,7 +351,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val btb_fg_crossing_f = fetch_start_f(0) & btb_sel_f(0) & btb_rd_pc4_f val btb_fg_crossing_f = fetch_start_f(0) & btb_sel_f(0) & btb_rd_pc4_f
val bp_total_branch_offset_f = bloc_f(1)^btb_rd_pc4_f val bp_total_branch_offset_f = bloc_f(1)^btb_rd_pc4_f
val ifc_fetch_adder_prior = RegEnable(io.ifc_fetch_addr_f(30,1), 0.U, (io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f).asBool) val ifc_fetch_adder_prior = rvdffe(io.ifc_fetch_addr_f(30,1), (io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f).asBool, clock, io.scan_mode)
io.ifu_bp_poffset_f := btb_rd_tgt_f io.ifu_bp_poffset_f := btb_rd_tgt_f
@ -385,7 +387,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
rs_pop.asBool ->rets_out(i+1)))) rs_pop.asBool ->rets_out(i+1))))
// Make flops for poping the data // Make flops for poping the data
rets_out := (0 until RET_STACK_SIZE).map(i=>RegEnable(rets_in(i),0.U,rsenable(i).asBool)) rets_out := (0 until RET_STACK_SIZE).map(i=>rvdffe(rets_in(i), rsenable(i).asBool, clock, io.scan_mode))
val btb_valid = exu_mp_valid & (!dec_tlu_error_wb) val btb_valid = exu_mp_valid & (!dec_tlu_error_wb)
val btb_wr_tag = io.exu_mp_btag val btb_wr_tag = io.exu_mp_btag
@ -422,8 +424,8 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
// BTB // BTB
// Entry -> Tag[BTB-BTAG-SIZE], toffset[12], pc4, boffset, call, ret, valid // Entry -> Tag[BTB-BTAG-SIZE], toffset[12], pc4, boffset, call, ret, valid
val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i=>RegEnable(btb_wr_data,0.U,((btb_wr_addr===i.U) & btb_wr_en_way0).asBool)) val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i=>rvdffe(btb_wr_data, ((btb_wr_addr===i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode))
val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i=>RegEnable(btb_wr_data,0.U,((btb_wr_addr===i.U) & btb_wr_en_way1).asBool)) val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i=>rvdffe(btb_wr_data, ((btb_wr_addr===i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode))
btb_bank0_rd_data_way0_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_f===i.U).asBool->btb_bank0_rd_data_way0_out(i))) btb_bank0_rd_data_way0_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_f===i.U).asBool->btb_bank0_rd_data_way0_out(i)))
btb_bank0_rd_data_way1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_f===i.U).asBool->btb_bank0_rd_data_way1_out(i))) btb_bank0_rd_data_way1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_f===i.U).asBool->btb_bank0_rd_data_way1_out(i)))
@ -433,6 +435,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_p1_f===i.U).asBool->btb_bank0_rd_data_way1_out(i))) btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_p1_f===i.U).asBool->btb_bank0_rd_data_way1_out(i)))
val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool()))) val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool())))
val bht_bank_clk = (0 until 2).map(i=>(0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)).map(k=>rvclkhdr(clock, bht_bank_clken(i)(k), io.scan_mode)))
for(i<-0 until 2; k<- 0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)){ for(i<-0 until 2; k<- 0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)){
// Checking if there is a write enable with address for the BHT // Checking if there is a write enable with address for the BHT
bht_bank_clken(i)(k) := (bht_wr_en0(i) & ((bht_wr_addr0(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-2)===k.U) | BHT_NO_ADDR_MATCH.B)) | bht_bank_clken(i)(k) := (bht_wr_en0(i) & ((bht_wr_addr0(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-2)===k.U) | BHT_NO_ADDR_MATCH.B)) |
@ -456,7 +459,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
// Reading the BHT with i->way, k->block and the j->offset // Reading the BHT with i->way, k->block and the j->offset
val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W)))) val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W))))
for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){ for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j) & bht_bank_clken(i)(k)) bht_bank_rd_data_out(i)((16*k)+j) := withClock(bht_bank_clk(i)(k)){RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j))}
} }
// Make the final read mux // Make the final read mux

4
src/main/scala/include/el2_bundle.scala
View File

@ -75,7 +75,7 @@ class el2_br_pkt_t extends Bundle {
val br_error = UInt(1.W) val br_error = UInt(1.W)
val br_start_error = UInt(1.W) val br_start_error = UInt(1.W)
val bank = UInt(1.W) val bank = UInt(1.W)
val prett = UInt(32.W) // predicted ret target val prett = UInt(31.W) // predicted ret target
val way = UInt(1.W) val way = UInt(1.W)
val ret = UInt(1.W) val ret = UInt(1.W)
} }
@ -100,7 +100,7 @@ class el2_predict_pkt_t extends Bundle {
val valid = UInt(1.W) val valid = UInt(1.W)
val br_error = UInt(1.W) val br_error = UInt(1.W)
val br_start_error = UInt(1.W) val br_start_error = UInt(1.W)
val prett = UInt(32.W) val prett = UInt(31.W)
val pcall = UInt(1.W) val pcall = UInt(1.W)
val pret = UInt(1.W) val pret = UInt(1.W)
val pja = UInt(1.W) val pja = UInt(1.W)

1265
src/main/scala/lsu/el2_lsu_bus_buffer.scala
View File

File diff suppressed because it is too large Load Diff

BIN
target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/el2_ifu_bp_ctl$$anon$1.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/ifu_bp$.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/ifu_bp$delayedInit$body.class
View File

Binary file not shown.