From 04eba9f5f5a90b99273bed02f9df8d8fc9589278 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Wed, 2 Dec 2020 16:20:44 +0500 Subject: [PATCH] axi to ahb update --- axi4_to_ahb.fir | 1634 ++++++++--------- axi4_to_ahb.v | 452 ++--- src/main/scala/lib/ahb_to_axi4.scala | 14 +- src/main/scala/lib/axi4_to_ahb.scala | 3 +- target/scala-2.12/classes/lib/AHB_main$.class | Bin 3903 -> 3903 bytes .../lib/AHB_main$delayedInit$body.class | Bin 738 -> 738 bytes target/scala-2.12/classes/lib/AXImain$.class | Bin 3898 -> 3898 bytes .../lib/AXImain$delayedInit$body.class | Bin 732 -> 732 bytes .../scala-2.12/classes/lib/ahb_to_axi4.class | Bin 111457 -> 111428 bytes .../scala-2.12/classes/lib/axi4_to_ahb.class | Bin 107007 -> 106923 bytes 10 files changed, 1046 insertions(+), 1057 deletions(-) diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir index 8a2e3626..2d6046f2 100644 --- a/axi4_to_ahb.fir +++ b/axi4_to_ahb.fir @@ -411,148 +411,148 @@ circuit axi4_to_ahb : wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") wire buf_clk : Clock @[axi4_to_ahb.scala 157:21] - node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 198:27] - wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 198:14] - node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 199:30] - master_valid <= _T_8 @[axi4_to_ahb.scala 199:16] - node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 200:38] - node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 200:51] - node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 200:76] - node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 200:20] - master_tag <= _T_12 @[axi4_to_ahb.scala 200:14] - node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 201:38] - node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 201:20] - master_opc <= _T_14 @[axi4_to_ahb.scala 201:14] - node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 202:39] - node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 202:53] - node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 202:75] - node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 202:21] - master_addr <= _T_18 @[axi4_to_ahb.scala 202:15] - node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 203:39] - node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 203:53] - node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 203:74] - node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 203:21] - master_size <= _T_22 @[axi4_to_ahb.scala 203:15] - node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 204:32] - master_byteen <= _T_23 @[axi4_to_ahb.scala 204:17] - node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 205:29] - master_wdata <= _T_24 @[axi4_to_ahb.scala 205:16] - node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 208:32] - node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 208:57] - node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 208:46] - io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 208:17] - node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 209:32] - node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 209:59] - node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 209:49] - node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 209:22] - io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 209:16] - node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 210:26] - io.axi_bid <= _T_32 @[axi4_to_ahb.scala 210:14] - node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 212:32] - node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 212:58] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 212:65] - node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 212:46] - io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 212:17] - node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 213:32] - node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 213:59] - node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 213:49] - node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 213:22] - io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 213:16] - node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 214:26] - io.axi_rid <= _T_41 @[axi4_to_ahb.scala 214:14] - node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 215:30] - io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 215:16] - node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 216:32] - slave_ready <= _T_43 @[axi4_to_ahb.scala 216:15] - node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 219:56] - node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 219:91] - node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 219:74] - node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 219:37] - bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 219:20] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 177:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 177:14] + node _T_8 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 178:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 178:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 179:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 179:51] + node _T_11 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 179:76] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 179:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 179:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 180:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 180:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 180:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 181:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 181:53] + node _T_17 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 181:75] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 181:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 181:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 182:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 182:53] + node _T_21 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 182:74] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 182:21] + master_size <= _T_22 @[axi4_to_ahb.scala 182:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 183:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 183:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 184:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 184:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 187:32] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 187:57] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 187:46] + io.axi_bvalid <= _T_27 @[axi4_to_ahb.scala 187:17] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 188:32] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 188:59] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 188:49] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 188:22] + io.axi_bresp <= _T_31 @[axi4_to_ahb.scala 188:16] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 189:26] + io.axi_bid <= _T_32 @[axi4_to_ahb.scala 189:14] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 191:32] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 191:58] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 191:65] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 191:46] + io.axi_rvalid <= _T_36 @[axi4_to_ahb.scala 191:17] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 192:32] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 192:59] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 192:49] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 192:22] + io.axi_rresp <= _T_40 @[axi4_to_ahb.scala 192:16] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 193:26] + io.axi_rid <= _T_41 @[axi4_to_ahb.scala 193:14] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 194:30] + io.axi_rdata <= _T_42 @[axi4_to_ahb.scala 194:16] + node _T_43 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 195:32] + slave_ready <= _T_43 @[axi4_to_ahb.scala 195:15] + node _T_44 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 198:56] + node _T_45 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 198:91] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 198:74] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 198:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 198:20] inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 221:11] - node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 222:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 200:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 201:59] inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_1.io.en <= _T_48 @[el2_lib.scala 485:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 222:17] - io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 225:17] - master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 226:16] - buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 227:16] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 228:18] - buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 230:18] - slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 231:21] - slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 232:21] - buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 233:18] - cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 234:18] - trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 235:18] - buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 236:23] - buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 237:20] - slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 238:21] - slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 239:19] - bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 240:20] - rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 241:18] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 201:17] + io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 204:17] + master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 205:16] + buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 206:16] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 207:18] + buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 209:18] + slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 210:21] + slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 211:21] + buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 212:18] + cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 213:18] + trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 214:18] + buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 215:23] + buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 216:20] + slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 217:21] + slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 218:19] + bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 219:20] + rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 220:18] node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] when _T_49 : @[Conditional.scala 40:58] - master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 245:20] - node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 246:34] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 246:41] - buf_write_in <= _T_51 @[axi4_to_ahb.scala 246:20] - node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 247:46] - node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 247:26] - buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 247:20] - node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 248:36] - buf_state_en <= _T_54 @[axi4_to_ahb.scala 248:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 249:17] - node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 250:54] - node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 250:38] - buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 250:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 251:27] - node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 253:50] - node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 253:94] - node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 182:52] - node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 182:52] - node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 182:24] - node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 183:44] - node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 183:62] - node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 183:48] - node _T_65 = orr(_T_64) @[axi4_to_ahb.scala 183:77] - node _T_66 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 183:44] - node _T_67 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 183:62] - node _T_68 = and(_T_66, _T_67) @[axi4_to_ahb.scala 183:48] - node _T_69 = orr(_T_68) @[axi4_to_ahb.scala 183:77] - node _T_70 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 183:44] - node _T_71 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 183:62] - node _T_72 = and(_T_70, _T_71) @[axi4_to_ahb.scala 183:48] - node _T_73 = orr(_T_72) @[axi4_to_ahb.scala 183:77] - node _T_74 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 183:44] - node _T_75 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 183:62] - node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 183:48] - node _T_77 = orr(_T_76) @[axi4_to_ahb.scala 183:77] - node _T_78 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 183:44] - node _T_79 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 183:62] - node _T_80 = and(_T_78, _T_79) @[axi4_to_ahb.scala 183:48] - node _T_81 = orr(_T_80) @[axi4_to_ahb.scala 183:77] - node _T_82 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 183:44] - node _T_83 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 183:62] - node _T_84 = and(_T_82, _T_83) @[axi4_to_ahb.scala 183:48] - node _T_85 = orr(_T_84) @[axi4_to_ahb.scala 183:77] - node _T_86 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 183:44] - node _T_87 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 183:62] - node _T_88 = and(_T_86, _T_87) @[axi4_to_ahb.scala 183:48] - node _T_89 = orr(_T_88) @[axi4_to_ahb.scala 183:77] - node _T_90 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 183:44] - node _T_91 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 183:62] - node _T_92 = and(_T_90, _T_91) @[axi4_to_ahb.scala 183:48] - node _T_93 = orr(_T_92) @[axi4_to_ahb.scala 183:77] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 224:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 225:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 225:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 225:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 226:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 226:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 226:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 227:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 227:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 228:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 229:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 229:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 229:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 230:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 232:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 232:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 174:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 174:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 175:45] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 175:63] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 175:49] + node _T_65 = orr(_T_64) @[axi4_to_ahb.scala 175:78] + node _T_66 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 175:45] + node _T_67 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 175:63] + node _T_68 = and(_T_66, _T_67) @[axi4_to_ahb.scala 175:49] + node _T_69 = orr(_T_68) @[axi4_to_ahb.scala 175:78] + node _T_70 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 175:45] + node _T_71 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 175:63] + node _T_72 = and(_T_70, _T_71) @[axi4_to_ahb.scala 175:49] + node _T_73 = orr(_T_72) @[axi4_to_ahb.scala 175:78] + node _T_74 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 175:45] + node _T_75 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 175:63] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 175:49] + node _T_77 = orr(_T_76) @[axi4_to_ahb.scala 175:78] + node _T_78 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 175:45] + node _T_79 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 175:63] + node _T_80 = and(_T_78, _T_79) @[axi4_to_ahb.scala 175:49] + node _T_81 = orr(_T_80) @[axi4_to_ahb.scala 175:78] + node _T_82 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 175:45] + node _T_83 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 175:63] + node _T_84 = and(_T_82, _T_83) @[axi4_to_ahb.scala 175:49] + node _T_85 = orr(_T_84) @[axi4_to_ahb.scala 175:78] + node _T_86 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 175:45] + node _T_87 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 175:63] + node _T_88 = and(_T_86, _T_87) @[axi4_to_ahb.scala 175:49] + node _T_89 = orr(_T_88) @[axi4_to_ahb.scala 175:78] + node _T_90 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:45] + node _T_91 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:63] + node _T_92 = and(_T_90, _T_91) @[axi4_to_ahb.scala 175:49] + node _T_93 = orr(_T_92) @[axi4_to_ahb.scala 175:78] node _T_94 = mux(_T_93, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] node _T_95 = mux(_T_89, UInt<3>("h06"), _T_94) @[Mux.scala 98:16] node _T_96 = mux(_T_85, UInt<3>("h05"), _T_95) @[Mux.scala 98:16] @@ -561,201 +561,201 @@ circuit axi4_to_ahb : node _T_99 = mux(_T_73, UInt<2>("h02"), _T_98) @[Mux.scala 98:16] node _T_100 = mux(_T_69, UInt<1>("h01"), _T_99) @[Mux.scala 98:16] node _T_101 = mux(_T_65, UInt<1>("h00"), _T_100) @[Mux.scala 98:16] - node _T_102 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 253:124] - node _T_103 = mux(_T_57, _T_101, _T_102) @[axi4_to_ahb.scala 253:30] - buf_cmd_byte_ptr <= _T_103 @[axi4_to_ahb.scala 253:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 254:17] - node _T_104 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 255:51] - node _T_105 = and(bypass_en, _T_104) @[axi4_to_ahb.scala 255:35] - rd_bypass_idle <= _T_105 @[axi4_to_ahb.scala 255:22] + node _T_102 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 232:124] + node _T_103 = mux(_T_57, _T_101, _T_102) @[axi4_to_ahb.scala 232:30] + buf_cmd_byte_ptr <= _T_103 @[axi4_to_ahb.scala 232:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 233:17] + node _T_104 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 234:51] + node _T_105 = and(bypass_en, _T_104) @[axi4_to_ahb.scala 234:35] + rd_bypass_idle <= _T_105 @[axi4_to_ahb.scala 234:22] node _T_106 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_107 = mux(_T_106, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_108 = and(_T_107, UInt<2>("h02")) @[axi4_to_ahb.scala 256:45] - io.ahb_htrans <= _T_108 @[axi4_to_ahb.scala 256:21] + node _T_108 = and(_T_107, UInt<2>("h02")) @[axi4_to_ahb.scala 235:45] + io.ahb_htrans <= _T_108 @[axi4_to_ahb.scala 235:21] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_109 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_109 : @[Conditional.scala 39:67] - node _T_110 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 260:54] - node _T_111 = eq(_T_110, UInt<1>("h00")) @[axi4_to_ahb.scala 260:61] - node _T_112 = and(master_valid, _T_111) @[axi4_to_ahb.scala 260:41] - node _T_113 = bits(_T_112, 0, 0) @[axi4_to_ahb.scala 260:82] - node _T_114 = mux(_T_113, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 260:26] - buf_nxtstate <= _T_114 @[axi4_to_ahb.scala 260:20] - node _T_115 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 261:51] - node _T_116 = neq(_T_115, UInt<1>("h00")) @[axi4_to_ahb.scala 261:58] - node _T_117 = and(ahb_hready_q, _T_116) @[axi4_to_ahb.scala 261:36] - node _T_118 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 261:72] - node _T_119 = and(_T_117, _T_118) @[axi4_to_ahb.scala 261:70] - buf_state_en <= _T_119 @[axi4_to_ahb.scala 261:20] - node _T_120 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 262:34] - node _T_121 = and(buf_state_en, _T_120) @[axi4_to_ahb.scala 262:32] - cmd_done <= _T_121 @[axi4_to_ahb.scala 262:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 263:20] - node _T_122 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 264:52] - node _T_123 = neq(_T_122, UInt<1>("h00")) @[axi4_to_ahb.scala 264:59] - node _T_124 = and(ahb_hready_q, _T_123) @[axi4_to_ahb.scala 264:37] - node _T_125 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 264:73] - node _T_126 = and(_T_124, _T_125) @[axi4_to_ahb.scala 264:71] - node _T_127 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 264:122] - node _T_128 = eq(_T_127, UInt<1>("h00")) @[axi4_to_ahb.scala 264:129] - node _T_129 = and(master_valid, _T_128) @[axi4_to_ahb.scala 264:109] - node _T_130 = bits(_T_129, 0, 0) @[axi4_to_ahb.scala 264:150] - node _T_131 = mux(_T_130, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 264:94] - node _T_132 = eq(_T_131, UInt<3>("h06")) @[axi4_to_ahb.scala 264:174] - node _T_133 = and(_T_126, _T_132) @[axi4_to_ahb.scala 264:88] - master_ready <= _T_133 @[axi4_to_ahb.scala 264:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 265:17] - node _T_134 = and(master_ready, master_valid) @[axi4_to_ahb.scala 266:33] - bypass_en <= _T_134 @[axi4_to_ahb.scala 266:17] - node _T_135 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 267:47] - node _T_136 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 267:62] - node _T_137 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 267:78] - node _T_138 = mux(_T_135, _T_136, _T_137) @[axi4_to_ahb.scala 267:30] - buf_cmd_byte_ptr <= _T_138 @[axi4_to_ahb.scala 267:24] - node _T_139 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 268:44] - node _T_140 = or(_T_139, bypass_en) @[axi4_to_ahb.scala 268:58] + node _T_110 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 239:54] + node _T_111 = eq(_T_110, UInt<1>("h00")) @[axi4_to_ahb.scala 239:61] + node _T_112 = and(master_valid, _T_111) @[axi4_to_ahb.scala 239:41] + node _T_113 = bits(_T_112, 0, 0) @[axi4_to_ahb.scala 239:82] + node _T_114 = mux(_T_113, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 239:26] + buf_nxtstate <= _T_114 @[axi4_to_ahb.scala 239:20] + node _T_115 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 240:51] + node _T_116 = neq(_T_115, UInt<1>("h00")) @[axi4_to_ahb.scala 240:58] + node _T_117 = and(ahb_hready_q, _T_116) @[axi4_to_ahb.scala 240:36] + node _T_118 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 240:72] + node _T_119 = and(_T_117, _T_118) @[axi4_to_ahb.scala 240:70] + buf_state_en <= _T_119 @[axi4_to_ahb.scala 240:20] + node _T_120 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 241:34] + node _T_121 = and(buf_state_en, _T_120) @[axi4_to_ahb.scala 241:32] + cmd_done <= _T_121 @[axi4_to_ahb.scala 241:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 242:20] + node _T_122 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 243:52] + node _T_123 = neq(_T_122, UInt<1>("h00")) @[axi4_to_ahb.scala 243:59] + node _T_124 = and(ahb_hready_q, _T_123) @[axi4_to_ahb.scala 243:37] + node _T_125 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 243:73] + node _T_126 = and(_T_124, _T_125) @[axi4_to_ahb.scala 243:71] + node _T_127 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 243:122] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[axi4_to_ahb.scala 243:129] + node _T_129 = and(master_valid, _T_128) @[axi4_to_ahb.scala 243:109] + node _T_130 = bits(_T_129, 0, 0) @[axi4_to_ahb.scala 243:150] + node _T_131 = mux(_T_130, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 243:94] + node _T_132 = eq(_T_131, UInt<3>("h06")) @[axi4_to_ahb.scala 243:174] + node _T_133 = and(_T_126, _T_132) @[axi4_to_ahb.scala 243:88] + master_ready <= _T_133 @[axi4_to_ahb.scala 243:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 244:17] + node _T_134 = and(master_ready, master_valid) @[axi4_to_ahb.scala 245:33] + bypass_en <= _T_134 @[axi4_to_ahb.scala 245:17] + node _T_135 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 246:47] + node _T_136 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 246:62] + node _T_137 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 246:78] + node _T_138 = mux(_T_135, _T_136, _T_137) @[axi4_to_ahb.scala 246:30] + buf_cmd_byte_ptr <= _T_138 @[axi4_to_ahb.scala 246:24] + node _T_139 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 247:44] + node _T_140 = or(_T_139, bypass_en) @[axi4_to_ahb.scala 247:58] node _T_141 = bits(_T_140, 0, 0) @[Bitwise.scala 72:15] node _T_142 = mux(_T_141, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_143 = and(UInt<2>("h02"), _T_142) @[axi4_to_ahb.scala 268:32] - io.ahb_htrans <= _T_143 @[axi4_to_ahb.scala 268:21] + node _T_143 = and(UInt<2>("h02"), _T_142) @[axi4_to_ahb.scala 247:32] + io.ahb_htrans <= _T_143 @[axi4_to_ahb.scala 247:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_144 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_144 : @[Conditional.scala 39:67] - node _T_145 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 272:39] - node _T_146 = and(ahb_hready_q, _T_145) @[axi4_to_ahb.scala 272:37] - node _T_147 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 272:82] - node _T_148 = eq(_T_147, UInt<1>("h01")) @[axi4_to_ahb.scala 272:89] - node _T_149 = and(master_valid, _T_148) @[axi4_to_ahb.scala 272:70] - node _T_150 = eq(_T_149, UInt<1>("h00")) @[axi4_to_ahb.scala 272:55] - node _T_151 = and(_T_146, _T_150) @[axi4_to_ahb.scala 272:53] - master_ready <= _T_151 @[axi4_to_ahb.scala 272:20] - node _T_152 = and(master_valid, master_ready) @[axi4_to_ahb.scala 273:34] - node _T_153 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 273:62] - node _T_154 = eq(_T_153, UInt<1>("h00")) @[axi4_to_ahb.scala 273:69] - node _T_155 = and(_T_152, _T_154) @[axi4_to_ahb.scala 273:49] - buf_wr_en <= _T_155 @[axi4_to_ahb.scala 273:17] - node _T_156 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 274:45] - node _T_157 = and(master_valid, master_ready) @[axi4_to_ahb.scala 274:82] - node _T_158 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 274:110] - node _T_159 = eq(_T_158, UInt<1>("h00")) @[axi4_to_ahb.scala 274:117] - node _T_160 = and(_T_157, _T_159) @[axi4_to_ahb.scala 274:97] - node _T_161 = bits(_T_160, 0, 0) @[axi4_to_ahb.scala 274:138] - node _T_162 = mux(_T_161, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 274:67] - node _T_163 = mux(_T_156, UInt<3>("h07"), _T_162) @[axi4_to_ahb.scala 274:26] - buf_nxtstate <= _T_163 @[axi4_to_ahb.scala 274:20] - node _T_164 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 275:37] - buf_state_en <= _T_164 @[axi4_to_ahb.scala 275:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 276:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 277:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 278:23] - node _T_165 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 279:41] - node _T_166 = and(buf_state_en, _T_165) @[axi4_to_ahb.scala 279:39] - slave_valid_pre <= _T_166 @[axi4_to_ahb.scala 279:23] - node _T_167 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 280:34] - node _T_168 = and(buf_state_en, _T_167) @[axi4_to_ahb.scala 280:32] - cmd_done <= _T_168 @[axi4_to_ahb.scala 280:16] - node _T_169 = and(master_ready, master_valid) @[axi4_to_ahb.scala 281:33] - node _T_170 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 281:64] - node _T_171 = and(_T_169, _T_170) @[axi4_to_ahb.scala 281:48] - node _T_172 = and(_T_171, buf_state_en) @[axi4_to_ahb.scala 281:79] - bypass_en <= _T_172 @[axi4_to_ahb.scala 281:17] - node _T_173 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 282:47] - node _T_174 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 282:62] - node _T_175 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 282:78] - node _T_176 = mux(_T_173, _T_174, _T_175) @[axi4_to_ahb.scala 282:30] - buf_cmd_byte_ptr <= _T_176 @[axi4_to_ahb.scala 282:24] - node _T_177 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 283:59] - node _T_178 = and(_T_177, buf_state_en) @[axi4_to_ahb.scala 283:74] - node _T_179 = eq(_T_178, UInt<1>("h00")) @[axi4_to_ahb.scala 283:43] + node _T_145 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 251:39] + node _T_146 = and(ahb_hready_q, _T_145) @[axi4_to_ahb.scala 251:37] + node _T_147 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 251:82] + node _T_148 = eq(_T_147, UInt<1>("h01")) @[axi4_to_ahb.scala 251:89] + node _T_149 = and(master_valid, _T_148) @[axi4_to_ahb.scala 251:70] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[axi4_to_ahb.scala 251:55] + node _T_151 = and(_T_146, _T_150) @[axi4_to_ahb.scala 251:53] + master_ready <= _T_151 @[axi4_to_ahb.scala 251:20] + node _T_152 = and(master_valid, master_ready) @[axi4_to_ahb.scala 252:34] + node _T_153 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 252:62] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[axi4_to_ahb.scala 252:69] + node _T_155 = and(_T_152, _T_154) @[axi4_to_ahb.scala 252:49] + buf_wr_en <= _T_155 @[axi4_to_ahb.scala 252:17] + node _T_156 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 253:45] + node _T_157 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:82] + node _T_158 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 253:110] + node _T_159 = eq(_T_158, UInt<1>("h00")) @[axi4_to_ahb.scala 253:117] + node _T_160 = and(_T_157, _T_159) @[axi4_to_ahb.scala 253:97] + node _T_161 = bits(_T_160, 0, 0) @[axi4_to_ahb.scala 253:138] + node _T_162 = mux(_T_161, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 253:67] + node _T_163 = mux(_T_156, UInt<3>("h07"), _T_162) @[axi4_to_ahb.scala 253:26] + buf_nxtstate <= _T_163 @[axi4_to_ahb.scala 253:20] + node _T_164 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 254:37] + buf_state_en <= _T_164 @[axi4_to_ahb.scala 254:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 255:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 256:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 257:23] + node _T_165 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 258:41] + node _T_166 = and(buf_state_en, _T_165) @[axi4_to_ahb.scala 258:39] + slave_valid_pre <= _T_166 @[axi4_to_ahb.scala 258:23] + node _T_167 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 259:34] + node _T_168 = and(buf_state_en, _T_167) @[axi4_to_ahb.scala 259:32] + cmd_done <= _T_168 @[axi4_to_ahb.scala 259:16] + node _T_169 = and(master_ready, master_valid) @[axi4_to_ahb.scala 260:33] + node _T_170 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 260:64] + node _T_171 = and(_T_169, _T_170) @[axi4_to_ahb.scala 260:48] + node _T_172 = and(_T_171, buf_state_en) @[axi4_to_ahb.scala 260:79] + bypass_en <= _T_172 @[axi4_to_ahb.scala 260:17] + node _T_173 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 261:47] + node _T_174 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 261:62] + node _T_175 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 261:78] + node _T_176 = mux(_T_173, _T_174, _T_175) @[axi4_to_ahb.scala 261:30] + buf_cmd_byte_ptr <= _T_176 @[axi4_to_ahb.scala 261:24] + node _T_177 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 262:59] + node _T_178 = and(_T_177, buf_state_en) @[axi4_to_ahb.scala 262:74] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[axi4_to_ahb.scala 262:43] node _T_180 = bits(_T_179, 0, 0) @[Bitwise.scala 72:15] node _T_181 = mux(_T_180, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_182 = and(UInt<2>("h02"), _T_181) @[axi4_to_ahb.scala 283:32] - io.ahb_htrans <= _T_182 @[axi4_to_ahb.scala 283:21] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 284:20] + node _T_182 = and(UInt<2>("h02"), _T_181) @[axi4_to_ahb.scala 262:32] + io.ahb_htrans <= _T_182 @[axi4_to_ahb.scala 262:21] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 263:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_183 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_183 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 288:20] - node _T_184 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 289:51] - node _T_185 = neq(_T_184, UInt<1>("h00")) @[axi4_to_ahb.scala 289:58] - node _T_186 = and(ahb_hready_q, _T_185) @[axi4_to_ahb.scala 289:36] - node _T_187 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 289:72] - node _T_188 = and(_T_186, _T_187) @[axi4_to_ahb.scala 289:70] - buf_state_en <= _T_188 @[axi4_to_ahb.scala 289:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 290:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 291:20] - node _T_189 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 292:35] - buf_cmd_byte_ptr <= _T_189 @[axi4_to_ahb.scala 292:24] - node _T_190 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 293:47] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 267:20] + node _T_184 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 268:51] + node _T_185 = neq(_T_184, UInt<1>("h00")) @[axi4_to_ahb.scala 268:58] + node _T_186 = and(ahb_hready_q, _T_185) @[axi4_to_ahb.scala 268:36] + node _T_187 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 268:72] + node _T_188 = and(_T_186, _T_187) @[axi4_to_ahb.scala 268:70] + buf_state_en <= _T_188 @[axi4_to_ahb.scala 268:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 269:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 270:20] + node _T_189 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 271:35] + buf_cmd_byte_ptr <= _T_189 @[axi4_to_ahb.scala 271:24] + node _T_190 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 272:47] node _T_191 = bits(_T_190, 0, 0) @[Bitwise.scala 72:15] node _T_192 = mux(_T_191, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_193 = and(UInt<2>("h02"), _T_192) @[axi4_to_ahb.scala 293:37] - io.ahb_htrans <= _T_193 @[axi4_to_ahb.scala 293:21] + node _T_193 = and(UInt<2>("h02"), _T_192) @[axi4_to_ahb.scala 272:37] + io.ahb_htrans <= _T_193 @[axi4_to_ahb.scala 272:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_194 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_194 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 297:20] - node _T_195 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 298:37] - buf_state_en <= _T_195 @[axi4_to_ahb.scala 298:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 299:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 300:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 301:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 302:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 276:20] + node _T_195 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 277:37] + buf_state_en <= _T_195 @[axi4_to_ahb.scala 277:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 278:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 279:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 280:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 281:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_196 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_196 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 306:20] - node _T_197 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 307:33] - node _T_198 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 307:63] - node _T_199 = neq(_T_198, UInt<1>("h00")) @[axi4_to_ahb.scala 307:70] - node _T_200 = and(_T_197, _T_199) @[axi4_to_ahb.scala 307:48] - trxn_done <= _T_200 @[axi4_to_ahb.scala 307:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 308:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 309:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 310:20] - node _T_201 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 311:47] - node _T_202 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 311:85] - node _T_203 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 311:103] - node _T_204 = add(_T_202, UInt<1>("h01")) @[axi4_to_ahb.scala 182:52] - node _T_205 = tail(_T_204, 1) @[axi4_to_ahb.scala 182:52] - node _T_206 = mux(UInt<1>("h01"), _T_205, _T_202) @[axi4_to_ahb.scala 182:24] - node _T_207 = bits(_T_203, 0, 0) @[axi4_to_ahb.scala 183:44] - node _T_208 = geq(UInt<1>("h00"), _T_206) @[axi4_to_ahb.scala 183:62] - node _T_209 = and(_T_207, _T_208) @[axi4_to_ahb.scala 183:48] - node _T_210 = orr(_T_209) @[axi4_to_ahb.scala 183:77] - node _T_211 = bits(_T_203, 1, 1) @[axi4_to_ahb.scala 183:44] - node _T_212 = geq(UInt<1>("h01"), _T_206) @[axi4_to_ahb.scala 183:62] - node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 183:48] - node _T_214 = orr(_T_213) @[axi4_to_ahb.scala 183:77] - node _T_215 = bits(_T_203, 2, 2) @[axi4_to_ahb.scala 183:44] - node _T_216 = geq(UInt<2>("h02"), _T_206) @[axi4_to_ahb.scala 183:62] - node _T_217 = and(_T_215, _T_216) @[axi4_to_ahb.scala 183:48] - node _T_218 = orr(_T_217) @[axi4_to_ahb.scala 183:77] - node _T_219 = bits(_T_203, 3, 3) @[axi4_to_ahb.scala 183:44] - node _T_220 = geq(UInt<2>("h03"), _T_206) @[axi4_to_ahb.scala 183:62] - node _T_221 = and(_T_219, _T_220) @[axi4_to_ahb.scala 183:48] - node _T_222 = orr(_T_221) @[axi4_to_ahb.scala 183:77] - node _T_223 = bits(_T_203, 4, 4) @[axi4_to_ahb.scala 183:44] - node _T_224 = geq(UInt<3>("h04"), _T_206) @[axi4_to_ahb.scala 183:62] - node _T_225 = and(_T_223, _T_224) @[axi4_to_ahb.scala 183:48] - node _T_226 = orr(_T_225) @[axi4_to_ahb.scala 183:77] - node _T_227 = bits(_T_203, 5, 5) @[axi4_to_ahb.scala 183:44] - node _T_228 = geq(UInt<3>("h05"), _T_206) @[axi4_to_ahb.scala 183:62] - node _T_229 = and(_T_227, _T_228) @[axi4_to_ahb.scala 183:48] - node _T_230 = orr(_T_229) @[axi4_to_ahb.scala 183:77] - node _T_231 = bits(_T_203, 6, 6) @[axi4_to_ahb.scala 183:44] - node _T_232 = geq(UInt<3>("h06"), _T_206) @[axi4_to_ahb.scala 183:62] - node _T_233 = and(_T_231, _T_232) @[axi4_to_ahb.scala 183:48] - node _T_234 = orr(_T_233) @[axi4_to_ahb.scala 183:77] - node _T_235 = bits(_T_203, 7, 7) @[axi4_to_ahb.scala 183:44] - node _T_236 = geq(UInt<3>("h07"), _T_206) @[axi4_to_ahb.scala 183:62] - node _T_237 = and(_T_235, _T_236) @[axi4_to_ahb.scala 183:48] - node _T_238 = orr(_T_237) @[axi4_to_ahb.scala 183:77] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 285:20] + node _T_197 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 286:33] + node _T_198 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 286:63] + node _T_199 = neq(_T_198, UInt<1>("h00")) @[axi4_to_ahb.scala 286:70] + node _T_200 = and(_T_197, _T_199) @[axi4_to_ahb.scala 286:48] + trxn_done <= _T_200 @[axi4_to_ahb.scala 286:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 287:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 288:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 289:20] + node _T_201 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 290:47] + node _T_202 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 290:85] + node _T_203 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 290:103] + node _T_204 = add(_T_202, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_205 = tail(_T_204, 1) @[axi4_to_ahb.scala 174:52] + node _T_206 = mux(UInt<1>("h01"), _T_205, _T_202) @[axi4_to_ahb.scala 174:24] + node _T_207 = bits(_T_203, 0, 0) @[axi4_to_ahb.scala 175:45] + node _T_208 = geq(UInt<1>("h00"), _T_206) @[axi4_to_ahb.scala 175:63] + node _T_209 = and(_T_207, _T_208) @[axi4_to_ahb.scala 175:49] + node _T_210 = orr(_T_209) @[axi4_to_ahb.scala 175:78] + node _T_211 = bits(_T_203, 1, 1) @[axi4_to_ahb.scala 175:45] + node _T_212 = geq(UInt<1>("h01"), _T_206) @[axi4_to_ahb.scala 175:63] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 175:49] + node _T_214 = orr(_T_213) @[axi4_to_ahb.scala 175:78] + node _T_215 = bits(_T_203, 2, 2) @[axi4_to_ahb.scala 175:45] + node _T_216 = geq(UInt<2>("h02"), _T_206) @[axi4_to_ahb.scala 175:63] + node _T_217 = and(_T_215, _T_216) @[axi4_to_ahb.scala 175:49] + node _T_218 = orr(_T_217) @[axi4_to_ahb.scala 175:78] + node _T_219 = bits(_T_203, 3, 3) @[axi4_to_ahb.scala 175:45] + node _T_220 = geq(UInt<2>("h03"), _T_206) @[axi4_to_ahb.scala 175:63] + node _T_221 = and(_T_219, _T_220) @[axi4_to_ahb.scala 175:49] + node _T_222 = orr(_T_221) @[axi4_to_ahb.scala 175:78] + node _T_223 = bits(_T_203, 4, 4) @[axi4_to_ahb.scala 175:45] + node _T_224 = geq(UInt<3>("h04"), _T_206) @[axi4_to_ahb.scala 175:63] + node _T_225 = and(_T_223, _T_224) @[axi4_to_ahb.scala 175:49] + node _T_226 = orr(_T_225) @[axi4_to_ahb.scala 175:78] + node _T_227 = bits(_T_203, 5, 5) @[axi4_to_ahb.scala 175:45] + node _T_228 = geq(UInt<3>("h05"), _T_206) @[axi4_to_ahb.scala 175:63] + node _T_229 = and(_T_227, _T_228) @[axi4_to_ahb.scala 175:49] + node _T_230 = orr(_T_229) @[axi4_to_ahb.scala 175:78] + node _T_231 = bits(_T_203, 6, 6) @[axi4_to_ahb.scala 175:45] + node _T_232 = geq(UInt<3>("h06"), _T_206) @[axi4_to_ahb.scala 175:63] + node _T_233 = and(_T_231, _T_232) @[axi4_to_ahb.scala 175:49] + node _T_234 = orr(_T_233) @[axi4_to_ahb.scala 175:78] + node _T_235 = bits(_T_203, 7, 7) @[axi4_to_ahb.scala 175:45] + node _T_236 = geq(UInt<3>("h07"), _T_206) @[axi4_to_ahb.scala 175:63] + node _T_237 = and(_T_235, _T_236) @[axi4_to_ahb.scala 175:49] + node _T_238 = orr(_T_237) @[axi4_to_ahb.scala 175:78] node _T_239 = mux(_T_238, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] node _T_240 = mux(_T_234, UInt<3>("h06"), _T_239) @[Mux.scala 98:16] node _T_241 = mux(_T_230, UInt<3>("h05"), _T_240) @[Mux.scala 98:16] @@ -764,47 +764,47 @@ circuit axi4_to_ahb : node _T_244 = mux(_T_218, UInt<2>("h02"), _T_243) @[Mux.scala 98:16] node _T_245 = mux(_T_214, UInt<1>("h01"), _T_244) @[Mux.scala 98:16] node _T_246 = mux(_T_210, UInt<1>("h00"), _T_245) @[Mux.scala 98:16] - node _T_247 = mux(_T_201, _T_246, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 311:30] - buf_cmd_byte_ptr <= _T_247 @[axi4_to_ahb.scala 311:24] - node _T_248 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 312:65] - node _T_249 = or(buf_aligned, _T_248) @[axi4_to_ahb.scala 312:44] - node _T_250 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 312:127] - node _T_251 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 312:145] - node _T_252 = add(_T_250, UInt<1>("h01")) @[axi4_to_ahb.scala 182:52] - node _T_253 = tail(_T_252, 1) @[axi4_to_ahb.scala 182:52] - node _T_254 = mux(UInt<1>("h01"), _T_253, _T_250) @[axi4_to_ahb.scala 182:24] - node _T_255 = bits(_T_251, 0, 0) @[axi4_to_ahb.scala 183:44] - node _T_256 = geq(UInt<1>("h00"), _T_254) @[axi4_to_ahb.scala 183:62] - node _T_257 = and(_T_255, _T_256) @[axi4_to_ahb.scala 183:48] - node _T_258 = orr(_T_257) @[axi4_to_ahb.scala 183:77] - node _T_259 = bits(_T_251, 1, 1) @[axi4_to_ahb.scala 183:44] - node _T_260 = geq(UInt<1>("h01"), _T_254) @[axi4_to_ahb.scala 183:62] - node _T_261 = and(_T_259, _T_260) @[axi4_to_ahb.scala 183:48] - node _T_262 = orr(_T_261) @[axi4_to_ahb.scala 183:77] - node _T_263 = bits(_T_251, 2, 2) @[axi4_to_ahb.scala 183:44] - node _T_264 = geq(UInt<2>("h02"), _T_254) @[axi4_to_ahb.scala 183:62] - node _T_265 = and(_T_263, _T_264) @[axi4_to_ahb.scala 183:48] - node _T_266 = orr(_T_265) @[axi4_to_ahb.scala 183:77] - node _T_267 = bits(_T_251, 3, 3) @[axi4_to_ahb.scala 183:44] - node _T_268 = geq(UInt<2>("h03"), _T_254) @[axi4_to_ahb.scala 183:62] - node _T_269 = and(_T_267, _T_268) @[axi4_to_ahb.scala 183:48] - node _T_270 = orr(_T_269) @[axi4_to_ahb.scala 183:77] - node _T_271 = bits(_T_251, 4, 4) @[axi4_to_ahb.scala 183:44] - node _T_272 = geq(UInt<3>("h04"), _T_254) @[axi4_to_ahb.scala 183:62] - node _T_273 = and(_T_271, _T_272) @[axi4_to_ahb.scala 183:48] - node _T_274 = orr(_T_273) @[axi4_to_ahb.scala 183:77] - node _T_275 = bits(_T_251, 5, 5) @[axi4_to_ahb.scala 183:44] - node _T_276 = geq(UInt<3>("h05"), _T_254) @[axi4_to_ahb.scala 183:62] - node _T_277 = and(_T_275, _T_276) @[axi4_to_ahb.scala 183:48] - node _T_278 = orr(_T_277) @[axi4_to_ahb.scala 183:77] - node _T_279 = bits(_T_251, 6, 6) @[axi4_to_ahb.scala 183:44] - node _T_280 = geq(UInt<3>("h06"), _T_254) @[axi4_to_ahb.scala 183:62] - node _T_281 = and(_T_279, _T_280) @[axi4_to_ahb.scala 183:48] - node _T_282 = orr(_T_281) @[axi4_to_ahb.scala 183:77] - node _T_283 = bits(_T_251, 7, 7) @[axi4_to_ahb.scala 183:44] - node _T_284 = geq(UInt<3>("h07"), _T_254) @[axi4_to_ahb.scala 183:62] - node _T_285 = and(_T_283, _T_284) @[axi4_to_ahb.scala 183:48] - node _T_286 = orr(_T_285) @[axi4_to_ahb.scala 183:77] + node _T_247 = mux(_T_201, _T_246, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 290:30] + buf_cmd_byte_ptr <= _T_247 @[axi4_to_ahb.scala 290:24] + node _T_248 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 291:65] + node _T_249 = or(buf_aligned, _T_248) @[axi4_to_ahb.scala 291:44] + node _T_250 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:127] + node _T_251 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:145] + node _T_252 = add(_T_250, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_253 = tail(_T_252, 1) @[axi4_to_ahb.scala 174:52] + node _T_254 = mux(UInt<1>("h01"), _T_253, _T_250) @[axi4_to_ahb.scala 174:24] + node _T_255 = bits(_T_251, 0, 0) @[axi4_to_ahb.scala 175:45] + node _T_256 = geq(UInt<1>("h00"), _T_254) @[axi4_to_ahb.scala 175:63] + node _T_257 = and(_T_255, _T_256) @[axi4_to_ahb.scala 175:49] + node _T_258 = orr(_T_257) @[axi4_to_ahb.scala 175:78] + node _T_259 = bits(_T_251, 1, 1) @[axi4_to_ahb.scala 175:45] + node _T_260 = geq(UInt<1>("h01"), _T_254) @[axi4_to_ahb.scala 175:63] + node _T_261 = and(_T_259, _T_260) @[axi4_to_ahb.scala 175:49] + node _T_262 = orr(_T_261) @[axi4_to_ahb.scala 175:78] + node _T_263 = bits(_T_251, 2, 2) @[axi4_to_ahb.scala 175:45] + node _T_264 = geq(UInt<2>("h02"), _T_254) @[axi4_to_ahb.scala 175:63] + node _T_265 = and(_T_263, _T_264) @[axi4_to_ahb.scala 175:49] + node _T_266 = orr(_T_265) @[axi4_to_ahb.scala 175:78] + node _T_267 = bits(_T_251, 3, 3) @[axi4_to_ahb.scala 175:45] + node _T_268 = geq(UInt<2>("h03"), _T_254) @[axi4_to_ahb.scala 175:63] + node _T_269 = and(_T_267, _T_268) @[axi4_to_ahb.scala 175:49] + node _T_270 = orr(_T_269) @[axi4_to_ahb.scala 175:78] + node _T_271 = bits(_T_251, 4, 4) @[axi4_to_ahb.scala 175:45] + node _T_272 = geq(UInt<3>("h04"), _T_254) @[axi4_to_ahb.scala 175:63] + node _T_273 = and(_T_271, _T_272) @[axi4_to_ahb.scala 175:49] + node _T_274 = orr(_T_273) @[axi4_to_ahb.scala 175:78] + node _T_275 = bits(_T_251, 5, 5) @[axi4_to_ahb.scala 175:45] + node _T_276 = geq(UInt<3>("h05"), _T_254) @[axi4_to_ahb.scala 175:63] + node _T_277 = and(_T_275, _T_276) @[axi4_to_ahb.scala 175:49] + node _T_278 = orr(_T_277) @[axi4_to_ahb.scala 175:78] + node _T_279 = bits(_T_251, 6, 6) @[axi4_to_ahb.scala 175:45] + node _T_280 = geq(UInt<3>("h06"), _T_254) @[axi4_to_ahb.scala 175:63] + node _T_281 = and(_T_279, _T_280) @[axi4_to_ahb.scala 175:49] + node _T_282 = orr(_T_281) @[axi4_to_ahb.scala 175:78] + node _T_283 = bits(_T_251, 7, 7) @[axi4_to_ahb.scala 175:45] + node _T_284 = geq(UInt<3>("h07"), _T_254) @[axi4_to_ahb.scala 175:63] + node _T_285 = and(_T_283, _T_284) @[axi4_to_ahb.scala 175:49] + node _T_286 = orr(_T_285) @[axi4_to_ahb.scala 175:78] node _T_287 = mux(_T_286, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] node _T_288 = mux(_T_282, UInt<3>("h06"), _T_287) @[Mux.scala 98:16] node _T_289 = mux(_T_278, UInt<3>("h05"), _T_288) @[Mux.scala 98:16] @@ -813,94 +813,94 @@ circuit axi4_to_ahb : node _T_292 = mux(_T_266, UInt<2>("h02"), _T_291) @[Mux.scala 98:16] node _T_293 = mux(_T_262, UInt<1>("h01"), _T_292) @[Mux.scala 98:16] node _T_294 = mux(_T_258, UInt<1>("h00"), _T_293) @[Mux.scala 98:16] - node _T_295 = dshr(buf_byteen, _T_294) @[axi4_to_ahb.scala 312:92] - node _T_296 = bits(_T_295, 0, 0) @[axi4_to_ahb.scala 312:92] - node _T_297 = eq(_T_296, UInt<1>("h00")) @[axi4_to_ahb.scala 312:163] - node _T_298 = or(_T_249, _T_297) @[axi4_to_ahb.scala 312:79] - node _T_299 = and(trxn_done, _T_298) @[axi4_to_ahb.scala 312:29] - cmd_done <= _T_299 @[axi4_to_ahb.scala 312:16] - node _T_300 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 313:43] - node _T_301 = eq(_T_300, UInt<1>("h00")) @[axi4_to_ahb.scala 313:32] + node _T_295 = dshr(buf_byteen, _T_294) @[axi4_to_ahb.scala 291:92] + node _T_296 = bits(_T_295, 0, 0) @[axi4_to_ahb.scala 291:92] + node _T_297 = eq(_T_296, UInt<1>("h00")) @[axi4_to_ahb.scala 291:163] + node _T_298 = or(_T_249, _T_297) @[axi4_to_ahb.scala 291:79] + node _T_299 = and(trxn_done, _T_298) @[axi4_to_ahb.scala 291:29] + cmd_done <= _T_299 @[axi4_to_ahb.scala 291:16] + node _T_300 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 292:43] + node _T_301 = eq(_T_300, UInt<1>("h00")) @[axi4_to_ahb.scala 292:32] node _T_302 = bits(_T_301, 0, 0) @[Bitwise.scala 72:15] node _T_303 = mux(_T_302, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_304 = and(_T_303, UInt<2>("h02")) @[axi4_to_ahb.scala 313:57] - io.ahb_htrans <= _T_304 @[axi4_to_ahb.scala 313:21] + node _T_304 = and(_T_303, UInt<2>("h02")) @[axi4_to_ahb.scala 292:57] + io.ahb_htrans <= _T_304 @[axi4_to_ahb.scala 292:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_305 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_305 : @[Conditional.scala 39:67] - node _T_306 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 317:34] - node _T_307 = or(_T_306, ahb_hresp_q) @[axi4_to_ahb.scala 317:50] - buf_state_en <= _T_307 @[axi4_to_ahb.scala 317:20] - node _T_308 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 318:35] - node _T_309 = or(_T_308, ahb_hresp_q) @[axi4_to_ahb.scala 318:51] - node _T_310 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 318:68] - node _T_311 = and(_T_309, _T_310) @[axi4_to_ahb.scala 318:66] - node _T_312 = and(_T_311, slave_ready) @[axi4_to_ahb.scala 318:81] - master_ready <= _T_312 @[axi4_to_ahb.scala 318:20] - node _T_313 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 319:42] - node _T_314 = or(ahb_hresp_q, _T_313) @[axi4_to_ahb.scala 319:40] - node _T_315 = bits(_T_314, 0, 0) @[axi4_to_ahb.scala 319:62] - node _T_316 = and(master_valid, master_ready) @[axi4_to_ahb.scala 319:90] - node _T_317 = bits(_T_316, 0, 0) @[axi4_to_ahb.scala 319:112] - node _T_318 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 319:131] - node _T_319 = eq(_T_318, UInt<1>("h01")) @[axi4_to_ahb.scala 319:138] - node _T_320 = mux(_T_319, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 319:119] - node _T_321 = mux(_T_317, _T_320, UInt<3>("h00")) @[axi4_to_ahb.scala 319:75] - node _T_322 = mux(_T_315, UInt<3>("h05"), _T_321) @[axi4_to_ahb.scala 319:26] - buf_nxtstate <= _T_322 @[axi4_to_ahb.scala 319:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 320:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 321:23] - node _T_323 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 322:34] - node _T_324 = eq(_T_323, UInt<1>("h01")) @[axi4_to_ahb.scala 322:41] - buf_write_in <= _T_324 @[axi4_to_ahb.scala 322:20] - node _T_325 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 323:50] - node _T_326 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 323:78] - node _T_327 = or(_T_325, _T_326) @[axi4_to_ahb.scala 323:62] - node _T_328 = and(buf_state_en, _T_327) @[axi4_to_ahb.scala 323:33] - buf_wr_en <= _T_328 @[axi4_to_ahb.scala 323:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 324:22] - node _T_329 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 325:63] - node _T_330 = neq(_T_329, UInt<1>("h00")) @[axi4_to_ahb.scala 325:70] - node _T_331 = and(ahb_hready_q, _T_330) @[axi4_to_ahb.scala 325:48] - node _T_332 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 325:104] - node _T_333 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 325:166] - node _T_334 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 325:184] - node _T_335 = add(_T_333, UInt<1>("h01")) @[axi4_to_ahb.scala 182:52] - node _T_336 = tail(_T_335, 1) @[axi4_to_ahb.scala 182:52] - node _T_337 = mux(UInt<1>("h01"), _T_336, _T_333) @[axi4_to_ahb.scala 182:24] - node _T_338 = bits(_T_334, 0, 0) @[axi4_to_ahb.scala 183:44] - node _T_339 = geq(UInt<1>("h00"), _T_337) @[axi4_to_ahb.scala 183:62] - node _T_340 = and(_T_338, _T_339) @[axi4_to_ahb.scala 183:48] - node _T_341 = orr(_T_340) @[axi4_to_ahb.scala 183:77] - node _T_342 = bits(_T_334, 1, 1) @[axi4_to_ahb.scala 183:44] - node _T_343 = geq(UInt<1>("h01"), _T_337) @[axi4_to_ahb.scala 183:62] - node _T_344 = and(_T_342, _T_343) @[axi4_to_ahb.scala 183:48] - node _T_345 = orr(_T_344) @[axi4_to_ahb.scala 183:77] - node _T_346 = bits(_T_334, 2, 2) @[axi4_to_ahb.scala 183:44] - node _T_347 = geq(UInt<2>("h02"), _T_337) @[axi4_to_ahb.scala 183:62] - node _T_348 = and(_T_346, _T_347) @[axi4_to_ahb.scala 183:48] - node _T_349 = orr(_T_348) @[axi4_to_ahb.scala 183:77] - node _T_350 = bits(_T_334, 3, 3) @[axi4_to_ahb.scala 183:44] - node _T_351 = geq(UInt<2>("h03"), _T_337) @[axi4_to_ahb.scala 183:62] - node _T_352 = and(_T_350, _T_351) @[axi4_to_ahb.scala 183:48] - node _T_353 = orr(_T_352) @[axi4_to_ahb.scala 183:77] - node _T_354 = bits(_T_334, 4, 4) @[axi4_to_ahb.scala 183:44] - node _T_355 = geq(UInt<3>("h04"), _T_337) @[axi4_to_ahb.scala 183:62] - node _T_356 = and(_T_354, _T_355) @[axi4_to_ahb.scala 183:48] - node _T_357 = orr(_T_356) @[axi4_to_ahb.scala 183:77] - node _T_358 = bits(_T_334, 5, 5) @[axi4_to_ahb.scala 183:44] - node _T_359 = geq(UInt<3>("h05"), _T_337) @[axi4_to_ahb.scala 183:62] - node _T_360 = and(_T_358, _T_359) @[axi4_to_ahb.scala 183:48] - node _T_361 = orr(_T_360) @[axi4_to_ahb.scala 183:77] - node _T_362 = bits(_T_334, 6, 6) @[axi4_to_ahb.scala 183:44] - node _T_363 = geq(UInt<3>("h06"), _T_337) @[axi4_to_ahb.scala 183:62] - node _T_364 = and(_T_362, _T_363) @[axi4_to_ahb.scala 183:48] - node _T_365 = orr(_T_364) @[axi4_to_ahb.scala 183:77] - node _T_366 = bits(_T_334, 7, 7) @[axi4_to_ahb.scala 183:44] - node _T_367 = geq(UInt<3>("h07"), _T_337) @[axi4_to_ahb.scala 183:62] - node _T_368 = and(_T_366, _T_367) @[axi4_to_ahb.scala 183:48] - node _T_369 = orr(_T_368) @[axi4_to_ahb.scala 183:77] + node _T_306 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 296:34] + node _T_307 = or(_T_306, ahb_hresp_q) @[axi4_to_ahb.scala 296:50] + buf_state_en <= _T_307 @[axi4_to_ahb.scala 296:20] + node _T_308 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:35] + node _T_309 = or(_T_308, ahb_hresp_q) @[axi4_to_ahb.scala 297:51] + node _T_310 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 297:68] + node _T_311 = and(_T_309, _T_310) @[axi4_to_ahb.scala 297:66] + node _T_312 = and(_T_311, slave_ready) @[axi4_to_ahb.scala 297:81] + master_ready <= _T_312 @[axi4_to_ahb.scala 297:20] + node _T_313 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 298:42] + node _T_314 = or(ahb_hresp_q, _T_313) @[axi4_to_ahb.scala 298:40] + node _T_315 = bits(_T_314, 0, 0) @[axi4_to_ahb.scala 298:62] + node _T_316 = and(master_valid, master_ready) @[axi4_to_ahb.scala 298:90] + node _T_317 = bits(_T_316, 0, 0) @[axi4_to_ahb.scala 298:112] + node _T_318 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 298:131] + node _T_319 = eq(_T_318, UInt<1>("h01")) @[axi4_to_ahb.scala 298:138] + node _T_320 = mux(_T_319, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 298:119] + node _T_321 = mux(_T_317, _T_320, UInt<3>("h00")) @[axi4_to_ahb.scala 298:75] + node _T_322 = mux(_T_315, UInt<3>("h05"), _T_321) @[axi4_to_ahb.scala 298:26] + buf_nxtstate <= _T_322 @[axi4_to_ahb.scala 298:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 299:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 300:23] + node _T_323 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 301:34] + node _T_324 = eq(_T_323, UInt<1>("h01")) @[axi4_to_ahb.scala 301:41] + buf_write_in <= _T_324 @[axi4_to_ahb.scala 301:20] + node _T_325 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 302:50] + node _T_326 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 302:78] + node _T_327 = or(_T_325, _T_326) @[axi4_to_ahb.scala 302:62] + node _T_328 = and(buf_state_en, _T_327) @[axi4_to_ahb.scala 302:33] + buf_wr_en <= _T_328 @[axi4_to_ahb.scala 302:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 303:22] + node _T_329 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 304:63] + node _T_330 = neq(_T_329, UInt<1>("h00")) @[axi4_to_ahb.scala 304:70] + node _T_331 = and(ahb_hready_q, _T_330) @[axi4_to_ahb.scala 304:48] + node _T_332 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 304:104] + node _T_333 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 304:166] + node _T_334 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 304:184] + node _T_335 = add(_T_333, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_336 = tail(_T_335, 1) @[axi4_to_ahb.scala 174:52] + node _T_337 = mux(UInt<1>("h01"), _T_336, _T_333) @[axi4_to_ahb.scala 174:24] + node _T_338 = bits(_T_334, 0, 0) @[axi4_to_ahb.scala 175:45] + node _T_339 = geq(UInt<1>("h00"), _T_337) @[axi4_to_ahb.scala 175:63] + node _T_340 = and(_T_338, _T_339) @[axi4_to_ahb.scala 175:49] + node _T_341 = orr(_T_340) @[axi4_to_ahb.scala 175:78] + node _T_342 = bits(_T_334, 1, 1) @[axi4_to_ahb.scala 175:45] + node _T_343 = geq(UInt<1>("h01"), _T_337) @[axi4_to_ahb.scala 175:63] + node _T_344 = and(_T_342, _T_343) @[axi4_to_ahb.scala 175:49] + node _T_345 = orr(_T_344) @[axi4_to_ahb.scala 175:78] + node _T_346 = bits(_T_334, 2, 2) @[axi4_to_ahb.scala 175:45] + node _T_347 = geq(UInt<2>("h02"), _T_337) @[axi4_to_ahb.scala 175:63] + node _T_348 = and(_T_346, _T_347) @[axi4_to_ahb.scala 175:49] + node _T_349 = orr(_T_348) @[axi4_to_ahb.scala 175:78] + node _T_350 = bits(_T_334, 3, 3) @[axi4_to_ahb.scala 175:45] + node _T_351 = geq(UInt<2>("h03"), _T_337) @[axi4_to_ahb.scala 175:63] + node _T_352 = and(_T_350, _T_351) @[axi4_to_ahb.scala 175:49] + node _T_353 = orr(_T_352) @[axi4_to_ahb.scala 175:78] + node _T_354 = bits(_T_334, 4, 4) @[axi4_to_ahb.scala 175:45] + node _T_355 = geq(UInt<3>("h04"), _T_337) @[axi4_to_ahb.scala 175:63] + node _T_356 = and(_T_354, _T_355) @[axi4_to_ahb.scala 175:49] + node _T_357 = orr(_T_356) @[axi4_to_ahb.scala 175:78] + node _T_358 = bits(_T_334, 5, 5) @[axi4_to_ahb.scala 175:45] + node _T_359 = geq(UInt<3>("h05"), _T_337) @[axi4_to_ahb.scala 175:63] + node _T_360 = and(_T_358, _T_359) @[axi4_to_ahb.scala 175:49] + node _T_361 = orr(_T_360) @[axi4_to_ahb.scala 175:78] + node _T_362 = bits(_T_334, 6, 6) @[axi4_to_ahb.scala 175:45] + node _T_363 = geq(UInt<3>("h06"), _T_337) @[axi4_to_ahb.scala 175:63] + node _T_364 = and(_T_362, _T_363) @[axi4_to_ahb.scala 175:49] + node _T_365 = orr(_T_364) @[axi4_to_ahb.scala 175:78] + node _T_366 = bits(_T_334, 7, 7) @[axi4_to_ahb.scala 175:45] + node _T_367 = geq(UInt<3>("h07"), _T_337) @[axi4_to_ahb.scala 175:63] + node _T_368 = and(_T_366, _T_367) @[axi4_to_ahb.scala 175:49] + node _T_369 = orr(_T_368) @[axi4_to_ahb.scala 175:78] node _T_370 = mux(_T_369, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] node _T_371 = mux(_T_365, UInt<3>("h06"), _T_370) @[Mux.scala 98:16] node _T_372 = mux(_T_361, UInt<3>("h05"), _T_371) @[Mux.scala 98:16] @@ -909,70 +909,70 @@ circuit axi4_to_ahb : node _T_375 = mux(_T_349, UInt<2>("h02"), _T_374) @[Mux.scala 98:16] node _T_376 = mux(_T_345, UInt<1>("h01"), _T_375) @[Mux.scala 98:16] node _T_377 = mux(_T_341, UInt<1>("h00"), _T_376) @[Mux.scala 98:16] - node _T_378 = dshr(buf_byteen, _T_377) @[axi4_to_ahb.scala 325:131] - node _T_379 = bits(_T_378, 0, 0) @[axi4_to_ahb.scala 325:131] - node _T_380 = eq(_T_379, UInt<1>("h00")) @[axi4_to_ahb.scala 325:202] - node _T_381 = or(_T_332, _T_380) @[axi4_to_ahb.scala 325:118] - node _T_382 = and(_T_331, _T_381) @[axi4_to_ahb.scala 325:82] - node _T_383 = or(ahb_hresp_q, _T_382) @[axi4_to_ahb.scala 325:32] - cmd_done <= _T_383 @[axi4_to_ahb.scala 325:16] - node _T_384 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 326:33] - node _T_385 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 326:64] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 326:48] - bypass_en <= _T_386 @[axi4_to_ahb.scala 326:17] - node _T_387 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 327:44] - node _T_388 = eq(_T_387, UInt<1>("h00")) @[axi4_to_ahb.scala 327:33] - node _T_389 = or(_T_388, bypass_en) @[axi4_to_ahb.scala 327:57] + node _T_378 = dshr(buf_byteen, _T_377) @[axi4_to_ahb.scala 304:131] + node _T_379 = bits(_T_378, 0, 0) @[axi4_to_ahb.scala 304:131] + node _T_380 = eq(_T_379, UInt<1>("h00")) @[axi4_to_ahb.scala 304:202] + node _T_381 = or(_T_332, _T_380) @[axi4_to_ahb.scala 304:118] + node _T_382 = and(_T_331, _T_381) @[axi4_to_ahb.scala 304:82] + node _T_383 = or(ahb_hresp_q, _T_382) @[axi4_to_ahb.scala 304:32] + cmd_done <= _T_383 @[axi4_to_ahb.scala 304:16] + node _T_384 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 305:33] + node _T_385 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 305:64] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 305:48] + bypass_en <= _T_386 @[axi4_to_ahb.scala 305:17] + node _T_387 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 306:44] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[axi4_to_ahb.scala 306:33] + node _T_389 = or(_T_388, bypass_en) @[axi4_to_ahb.scala 306:57] node _T_390 = bits(_T_389, 0, 0) @[Bitwise.scala 72:15] node _T_391 = mux(_T_390, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_392 = and(_T_391, UInt<2>("h02")) @[axi4_to_ahb.scala 327:71] - io.ahb_htrans <= _T_392 @[axi4_to_ahb.scala 327:21] - node _T_393 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 328:55] - node _T_394 = and(buf_state_en, _T_393) @[axi4_to_ahb.scala 328:39] - slave_valid_pre <= _T_394 @[axi4_to_ahb.scala 328:23] - node _T_395 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 329:33] - node _T_396 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 329:63] - node _T_397 = neq(_T_396, UInt<1>("h00")) @[axi4_to_ahb.scala 329:70] - node _T_398 = and(_T_395, _T_397) @[axi4_to_ahb.scala 329:48] - trxn_done <= _T_398 @[axi4_to_ahb.scala 329:17] - node _T_399 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 330:40] - buf_cmd_byte_ptr_en <= _T_399 @[axi4_to_ahb.scala 330:27] - node _T_400 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 333:76] - node _T_401 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 182:52] - node _T_402 = tail(_T_401, 1) @[axi4_to_ahb.scala 182:52] - node _T_403 = mux(UInt<1>("h00"), _T_402, UInt<1>("h00")) @[axi4_to_ahb.scala 182:24] - node _T_404 = bits(_T_400, 0, 0) @[axi4_to_ahb.scala 183:44] - node _T_405 = geq(UInt<1>("h00"), _T_403) @[axi4_to_ahb.scala 183:62] - node _T_406 = and(_T_404, _T_405) @[axi4_to_ahb.scala 183:48] - node _T_407 = orr(_T_406) @[axi4_to_ahb.scala 183:77] - node _T_408 = bits(_T_400, 1, 1) @[axi4_to_ahb.scala 183:44] - node _T_409 = geq(UInt<1>("h01"), _T_403) @[axi4_to_ahb.scala 183:62] - node _T_410 = and(_T_408, _T_409) @[axi4_to_ahb.scala 183:48] - node _T_411 = orr(_T_410) @[axi4_to_ahb.scala 183:77] - node _T_412 = bits(_T_400, 2, 2) @[axi4_to_ahb.scala 183:44] - node _T_413 = geq(UInt<2>("h02"), _T_403) @[axi4_to_ahb.scala 183:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 183:48] - node _T_415 = orr(_T_414) @[axi4_to_ahb.scala 183:77] - node _T_416 = bits(_T_400, 3, 3) @[axi4_to_ahb.scala 183:44] - node _T_417 = geq(UInt<2>("h03"), _T_403) @[axi4_to_ahb.scala 183:62] - node _T_418 = and(_T_416, _T_417) @[axi4_to_ahb.scala 183:48] - node _T_419 = orr(_T_418) @[axi4_to_ahb.scala 183:77] - node _T_420 = bits(_T_400, 4, 4) @[axi4_to_ahb.scala 183:44] - node _T_421 = geq(UInt<3>("h04"), _T_403) @[axi4_to_ahb.scala 183:62] - node _T_422 = and(_T_420, _T_421) @[axi4_to_ahb.scala 183:48] - node _T_423 = orr(_T_422) @[axi4_to_ahb.scala 183:77] - node _T_424 = bits(_T_400, 5, 5) @[axi4_to_ahb.scala 183:44] - node _T_425 = geq(UInt<3>("h05"), _T_403) @[axi4_to_ahb.scala 183:62] - node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 183:48] - node _T_427 = orr(_T_426) @[axi4_to_ahb.scala 183:77] - node _T_428 = bits(_T_400, 6, 6) @[axi4_to_ahb.scala 183:44] - node _T_429 = geq(UInt<3>("h06"), _T_403) @[axi4_to_ahb.scala 183:62] - node _T_430 = and(_T_428, _T_429) @[axi4_to_ahb.scala 183:48] - node _T_431 = orr(_T_430) @[axi4_to_ahb.scala 183:77] - node _T_432 = bits(_T_400, 7, 7) @[axi4_to_ahb.scala 183:44] - node _T_433 = geq(UInt<3>("h07"), _T_403) @[axi4_to_ahb.scala 183:62] - node _T_434 = and(_T_432, _T_433) @[axi4_to_ahb.scala 183:48] - node _T_435 = orr(_T_434) @[axi4_to_ahb.scala 183:77] + node _T_392 = and(_T_391, UInt<2>("h02")) @[axi4_to_ahb.scala 306:71] + io.ahb_htrans <= _T_392 @[axi4_to_ahb.scala 306:21] + node _T_393 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 307:55] + node _T_394 = and(buf_state_en, _T_393) @[axi4_to_ahb.scala 307:39] + slave_valid_pre <= _T_394 @[axi4_to_ahb.scala 307:23] + node _T_395 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 308:33] + node _T_396 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 308:63] + node _T_397 = neq(_T_396, UInt<1>("h00")) @[axi4_to_ahb.scala 308:70] + node _T_398 = and(_T_395, _T_397) @[axi4_to_ahb.scala 308:48] + trxn_done <= _T_398 @[axi4_to_ahb.scala 308:17] + node _T_399 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 309:40] + buf_cmd_byte_ptr_en <= _T_399 @[axi4_to_ahb.scala 309:27] + node _T_400 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 310:76] + node _T_401 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_402 = tail(_T_401, 1) @[axi4_to_ahb.scala 174:52] + node _T_403 = mux(UInt<1>("h00"), _T_402, UInt<1>("h00")) @[axi4_to_ahb.scala 174:24] + node _T_404 = bits(_T_400, 0, 0) @[axi4_to_ahb.scala 175:45] + node _T_405 = geq(UInt<1>("h00"), _T_403) @[axi4_to_ahb.scala 175:63] + node _T_406 = and(_T_404, _T_405) @[axi4_to_ahb.scala 175:49] + node _T_407 = orr(_T_406) @[axi4_to_ahb.scala 175:78] + node _T_408 = bits(_T_400, 1, 1) @[axi4_to_ahb.scala 175:45] + node _T_409 = geq(UInt<1>("h01"), _T_403) @[axi4_to_ahb.scala 175:63] + node _T_410 = and(_T_408, _T_409) @[axi4_to_ahb.scala 175:49] + node _T_411 = orr(_T_410) @[axi4_to_ahb.scala 175:78] + node _T_412 = bits(_T_400, 2, 2) @[axi4_to_ahb.scala 175:45] + node _T_413 = geq(UInt<2>("h02"), _T_403) @[axi4_to_ahb.scala 175:63] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 175:49] + node _T_415 = orr(_T_414) @[axi4_to_ahb.scala 175:78] + node _T_416 = bits(_T_400, 3, 3) @[axi4_to_ahb.scala 175:45] + node _T_417 = geq(UInt<2>("h03"), _T_403) @[axi4_to_ahb.scala 175:63] + node _T_418 = and(_T_416, _T_417) @[axi4_to_ahb.scala 175:49] + node _T_419 = orr(_T_418) @[axi4_to_ahb.scala 175:78] + node _T_420 = bits(_T_400, 4, 4) @[axi4_to_ahb.scala 175:45] + node _T_421 = geq(UInt<3>("h04"), _T_403) @[axi4_to_ahb.scala 175:63] + node _T_422 = and(_T_420, _T_421) @[axi4_to_ahb.scala 175:49] + node _T_423 = orr(_T_422) @[axi4_to_ahb.scala 175:78] + node _T_424 = bits(_T_400, 5, 5) @[axi4_to_ahb.scala 175:45] + node _T_425 = geq(UInt<3>("h05"), _T_403) @[axi4_to_ahb.scala 175:63] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 175:49] + node _T_427 = orr(_T_426) @[axi4_to_ahb.scala 175:78] + node _T_428 = bits(_T_400, 6, 6) @[axi4_to_ahb.scala 175:45] + node _T_429 = geq(UInt<3>("h06"), _T_403) @[axi4_to_ahb.scala 175:63] + node _T_430 = and(_T_428, _T_429) @[axi4_to_ahb.scala 175:49] + node _T_431 = orr(_T_430) @[axi4_to_ahb.scala 175:78] + node _T_432 = bits(_T_400, 7, 7) @[axi4_to_ahb.scala 175:45] + node _T_433 = geq(UInt<3>("h07"), _T_403) @[axi4_to_ahb.scala 175:63] + node _T_434 = and(_T_432, _T_433) @[axi4_to_ahb.scala 175:49] + node _T_435 = orr(_T_434) @[axi4_to_ahb.scala 175:78] node _T_436 = mux(_T_435, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] node _T_437 = mux(_T_431, UInt<3>("h06"), _T_436) @[Mux.scala 98:16] node _T_438 = mux(_T_427, UInt<3>("h05"), _T_437) @[Mux.scala 98:16] @@ -981,43 +981,43 @@ circuit axi4_to_ahb : node _T_441 = mux(_T_415, UInt<2>("h02"), _T_440) @[Mux.scala 98:16] node _T_442 = mux(_T_411, UInt<1>("h01"), _T_441) @[Mux.scala 98:16] node _T_443 = mux(_T_407, UInt<1>("h00"), _T_442) @[Mux.scala 98:16] - node _T_444 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 333:142] - node _T_445 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 333:160] - node _T_446 = add(_T_444, UInt<1>("h01")) @[axi4_to_ahb.scala 182:52] - node _T_447 = tail(_T_446, 1) @[axi4_to_ahb.scala 182:52] - node _T_448 = mux(UInt<1>("h01"), _T_447, _T_444) @[axi4_to_ahb.scala 182:24] - node _T_449 = bits(_T_445, 0, 0) @[axi4_to_ahb.scala 183:44] - node _T_450 = geq(UInt<1>("h00"), _T_448) @[axi4_to_ahb.scala 183:62] - node _T_451 = and(_T_449, _T_450) @[axi4_to_ahb.scala 183:48] - node _T_452 = orr(_T_451) @[axi4_to_ahb.scala 183:77] - node _T_453 = bits(_T_445, 1, 1) @[axi4_to_ahb.scala 183:44] - node _T_454 = geq(UInt<1>("h01"), _T_448) @[axi4_to_ahb.scala 183:62] - node _T_455 = and(_T_453, _T_454) @[axi4_to_ahb.scala 183:48] - node _T_456 = orr(_T_455) @[axi4_to_ahb.scala 183:77] - node _T_457 = bits(_T_445, 2, 2) @[axi4_to_ahb.scala 183:44] - node _T_458 = geq(UInt<2>("h02"), _T_448) @[axi4_to_ahb.scala 183:62] - node _T_459 = and(_T_457, _T_458) @[axi4_to_ahb.scala 183:48] - node _T_460 = orr(_T_459) @[axi4_to_ahb.scala 183:77] - node _T_461 = bits(_T_445, 3, 3) @[axi4_to_ahb.scala 183:44] - node _T_462 = geq(UInt<2>("h03"), _T_448) @[axi4_to_ahb.scala 183:62] - node _T_463 = and(_T_461, _T_462) @[axi4_to_ahb.scala 183:48] - node _T_464 = orr(_T_463) @[axi4_to_ahb.scala 183:77] - node _T_465 = bits(_T_445, 4, 4) @[axi4_to_ahb.scala 183:44] - node _T_466 = geq(UInt<3>("h04"), _T_448) @[axi4_to_ahb.scala 183:62] - node _T_467 = and(_T_465, _T_466) @[axi4_to_ahb.scala 183:48] - node _T_468 = orr(_T_467) @[axi4_to_ahb.scala 183:77] - node _T_469 = bits(_T_445, 5, 5) @[axi4_to_ahb.scala 183:44] - node _T_470 = geq(UInt<3>("h05"), _T_448) @[axi4_to_ahb.scala 183:62] - node _T_471 = and(_T_469, _T_470) @[axi4_to_ahb.scala 183:48] - node _T_472 = orr(_T_471) @[axi4_to_ahb.scala 183:77] - node _T_473 = bits(_T_445, 6, 6) @[axi4_to_ahb.scala 183:44] - node _T_474 = geq(UInt<3>("h06"), _T_448) @[axi4_to_ahb.scala 183:62] - node _T_475 = and(_T_473, _T_474) @[axi4_to_ahb.scala 183:48] - node _T_476 = orr(_T_475) @[axi4_to_ahb.scala 183:77] - node _T_477 = bits(_T_445, 7, 7) @[axi4_to_ahb.scala 183:44] - node _T_478 = geq(UInt<3>("h07"), _T_448) @[axi4_to_ahb.scala 183:62] - node _T_479 = and(_T_477, _T_478) @[axi4_to_ahb.scala 183:48] - node _T_480 = orr(_T_479) @[axi4_to_ahb.scala 183:77] + node _T_444 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 310:142] + node _T_445 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 310:160] + node _T_446 = add(_T_444, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_447 = tail(_T_446, 1) @[axi4_to_ahb.scala 174:52] + node _T_448 = mux(UInt<1>("h01"), _T_447, _T_444) @[axi4_to_ahb.scala 174:24] + node _T_449 = bits(_T_445, 0, 0) @[axi4_to_ahb.scala 175:45] + node _T_450 = geq(UInt<1>("h00"), _T_448) @[axi4_to_ahb.scala 175:63] + node _T_451 = and(_T_449, _T_450) @[axi4_to_ahb.scala 175:49] + node _T_452 = orr(_T_451) @[axi4_to_ahb.scala 175:78] + node _T_453 = bits(_T_445, 1, 1) @[axi4_to_ahb.scala 175:45] + node _T_454 = geq(UInt<1>("h01"), _T_448) @[axi4_to_ahb.scala 175:63] + node _T_455 = and(_T_453, _T_454) @[axi4_to_ahb.scala 175:49] + node _T_456 = orr(_T_455) @[axi4_to_ahb.scala 175:78] + node _T_457 = bits(_T_445, 2, 2) @[axi4_to_ahb.scala 175:45] + node _T_458 = geq(UInt<2>("h02"), _T_448) @[axi4_to_ahb.scala 175:63] + node _T_459 = and(_T_457, _T_458) @[axi4_to_ahb.scala 175:49] + node _T_460 = orr(_T_459) @[axi4_to_ahb.scala 175:78] + node _T_461 = bits(_T_445, 3, 3) @[axi4_to_ahb.scala 175:45] + node _T_462 = geq(UInt<2>("h03"), _T_448) @[axi4_to_ahb.scala 175:63] + node _T_463 = and(_T_461, _T_462) @[axi4_to_ahb.scala 175:49] + node _T_464 = orr(_T_463) @[axi4_to_ahb.scala 175:78] + node _T_465 = bits(_T_445, 4, 4) @[axi4_to_ahb.scala 175:45] + node _T_466 = geq(UInt<3>("h04"), _T_448) @[axi4_to_ahb.scala 175:63] + node _T_467 = and(_T_465, _T_466) @[axi4_to_ahb.scala 175:49] + node _T_468 = orr(_T_467) @[axi4_to_ahb.scala 175:78] + node _T_469 = bits(_T_445, 5, 5) @[axi4_to_ahb.scala 175:45] + node _T_470 = geq(UInt<3>("h05"), _T_448) @[axi4_to_ahb.scala 175:63] + node _T_471 = and(_T_469, _T_470) @[axi4_to_ahb.scala 175:49] + node _T_472 = orr(_T_471) @[axi4_to_ahb.scala 175:78] + node _T_473 = bits(_T_445, 6, 6) @[axi4_to_ahb.scala 175:45] + node _T_474 = geq(UInt<3>("h06"), _T_448) @[axi4_to_ahb.scala 175:63] + node _T_475 = and(_T_473, _T_474) @[axi4_to_ahb.scala 175:49] + node _T_476 = orr(_T_475) @[axi4_to_ahb.scala 175:78] + node _T_477 = bits(_T_445, 7, 7) @[axi4_to_ahb.scala 175:45] + node _T_478 = geq(UInt<3>("h07"), _T_448) @[axi4_to_ahb.scala 175:63] + node _T_479 = and(_T_477, _T_478) @[axi4_to_ahb.scala 175:49] + node _T_480 = orr(_T_479) @[axi4_to_ahb.scala 175:78] node _T_481 = mux(_T_480, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] node _T_482 = mux(_T_476, UInt<3>("h06"), _T_481) @[Mux.scala 98:16] node _T_483 = mux(_T_472, UInt<3>("h05"), _T_482) @[Mux.scala 98:16] @@ -1026,268 +1026,268 @@ circuit axi4_to_ahb : node _T_486 = mux(_T_460, UInt<2>("h02"), _T_485) @[Mux.scala 98:16] node _T_487 = mux(_T_456, UInt<1>("h01"), _T_486) @[Mux.scala 98:16] node _T_488 = mux(_T_452, UInt<1>("h00"), _T_487) @[Mux.scala 98:16] - node _T_489 = mux(trxn_done, _T_488, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 333:97] - node _T_490 = mux(bypass_en, _T_443, _T_489) @[axi4_to_ahb.scala 333:30] - buf_cmd_byte_ptr <= _T_490 @[axi4_to_ahb.scala 333:24] + node _T_489 = mux(trxn_done, _T_488, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 310:97] + node _T_490 = mux(bypass_en, _T_443, _T_489) @[axi4_to_ahb.scala 310:30] + buf_cmd_byte_ptr <= _T_490 @[axi4_to_ahb.scala 310:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_491 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_491 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 337:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 338:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 339:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 340:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 314:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 315:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 316:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 317:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 344:16] - node _T_492 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 345:33] - node _T_493 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 345:73] - node _T_494 = eq(_T_493, UInt<1>("h01")) @[axi4_to_ahb.scala 345:80] - node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 345:60] - node _T_496 = bits(_T_495, 0, 0) @[axi4_to_ahb.scala 345:100] - node _T_497 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 345:132] - node _T_498 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 174:50] - node _T_499 = eq(_T_498, UInt<8>("h0ff")) @[axi4_to_ahb.scala 174:57] - node _T_500 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 174:81] - node _T_501 = eq(_T_500, UInt<8>("h0f")) @[axi4_to_ahb.scala 174:88] - node _T_502 = or(_T_499, _T_501) @[axi4_to_ahb.scala 174:70] - node _T_503 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 174:117] - node _T_504 = eq(_T_503, UInt<8>("h03")) @[axi4_to_ahb.scala 174:124] - node _T_505 = or(_T_502, _T_504) @[axi4_to_ahb.scala 174:106] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 321:16] + node _T_492 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 322:33] + node _T_493 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 322:73] + node _T_494 = eq(_T_493, UInt<1>("h01")) @[axi4_to_ahb.scala 322:80] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 322:60] + node _T_496 = bits(_T_495, 0, 0) @[axi4_to_ahb.scala 322:100] + node _T_497 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 322:132] + node _T_498 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 166:50] + node _T_499 = eq(_T_498, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:57] + node _T_500 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 166:81] + node _T_501 = eq(_T_500, UInt<8>("h0f")) @[axi4_to_ahb.scala 166:88] + node _T_502 = or(_T_499, _T_501) @[axi4_to_ahb.scala 166:70] + node _T_503 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 166:117] + node _T_504 = eq(_T_503, UInt<8>("h03")) @[axi4_to_ahb.scala 166:124] + node _T_505 = or(_T_502, _T_504) @[axi4_to_ahb.scala 166:106] node _T_506 = bits(_T_505, 0, 0) @[Bitwise.scala 72:15] node _T_507 = mux(_T_506, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_508 = and(UInt<3>("h00"), _T_507) @[axi4_to_ahb.scala 174:29] - node _T_509 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 175:35] - node _T_510 = eq(_T_509, UInt<8>("h0c")) @[axi4_to_ahb.scala 175:42] + node _T_508 = and(UInt<3>("h00"), _T_507) @[axi4_to_ahb.scala 166:29] + node _T_509 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 167:35] + node _T_510 = eq(_T_509, UInt<8>("h0c")) @[axi4_to_ahb.scala 167:42] node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] node _T_512 = mux(_T_511, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 175:15] - node _T_514 = or(_T_508, _T_513) @[axi4_to_ahb.scala 174:146] - node _T_515 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 176:36] - node _T_516 = eq(_T_515, UInt<8>("h0f0")) @[axi4_to_ahb.scala 176:43] - node _T_517 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 176:67] - node _T_518 = eq(_T_517, UInt<8>("h03")) @[axi4_to_ahb.scala 176:74] - node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 176:56] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 167:15] + node _T_514 = or(_T_508, _T_513) @[axi4_to_ahb.scala 166:146] + node _T_515 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 168:36] + node _T_516 = eq(_T_515, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:43] + node _T_517 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 168:67] + node _T_518 = eq(_T_517, UInt<8>("h03")) @[axi4_to_ahb.scala 168:74] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 168:56] node _T_520 = bits(_T_519, 0, 0) @[Bitwise.scala 72:15] node _T_521 = mux(_T_520, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_522 = and(UInt<3>("h04"), _T_521) @[axi4_to_ahb.scala 176:15] - node _T_523 = or(_T_514, _T_522) @[axi4_to_ahb.scala 175:63] - node _T_524 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 177:37] - node _T_525 = eq(_T_524, UInt<8>("h0c0")) @[axi4_to_ahb.scala 177:44] + node _T_522 = and(UInt<3>("h04"), _T_521) @[axi4_to_ahb.scala 168:15] + node _T_523 = or(_T_514, _T_522) @[axi4_to_ahb.scala 167:63] + node _T_524 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 169:37] + node _T_525 = eq(_T_524, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:44] node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] node _T_527 = mux(_T_526, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(UInt<3>("h06"), _T_527) @[axi4_to_ahb.scala 177:17] - node _T_529 = or(_T_523, _T_528) @[axi4_to_ahb.scala 176:96] - node _T_530 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 178:37] - node _T_531 = eq(_T_530, UInt<8>("h0c0")) @[axi4_to_ahb.scala 178:44] + node _T_528 = and(UInt<3>("h06"), _T_527) @[axi4_to_ahb.scala 169:17] + node _T_529 = or(_T_523, _T_528) @[axi4_to_ahb.scala 168:96] + node _T_530 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 170:37] + node _T_531 = eq(_T_530, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:44] node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] node _T_533 = mux(_T_532, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_534 = and(UInt<3>("h06"), _T_533) @[axi4_to_ahb.scala 178:17] - node _T_535 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 345:152] - node _T_536 = mux(_T_496, _T_529, _T_535) @[axi4_to_ahb.scala 345:43] + node _T_534 = and(UInt<3>("h06"), _T_533) @[axi4_to_ahb.scala 170:17] + node _T_535 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 322:152] + node _T_536 = mux(_T_496, _T_529, _T_535) @[axi4_to_ahb.scala 322:43] node _T_537 = cat(_T_492, _T_536) @[Cat.scala 29:58] - buf_addr_in <= _T_537 @[axi4_to_ahb.scala 345:15] - node _T_538 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 346:27] - buf_tag_in <= _T_538 @[axi4_to_ahb.scala 346:14] - node _T_539 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 347:32] - buf_byteen_in <= _T_539 @[axi4_to_ahb.scala 347:17] - node _T_540 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 348:33] - node _T_541 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 348:59] - node _T_542 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 348:80] - node _T_543 = mux(_T_540, _T_541, _T_542) @[axi4_to_ahb.scala 348:21] - buf_data_in <= _T_543 @[axi4_to_ahb.scala 348:15] - node _T_544 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:52] - node _T_545 = eq(_T_544, UInt<2>("h03")) @[axi4_to_ahb.scala 349:58] - node _T_546 = and(buf_aligned_in, _T_545) @[axi4_to_ahb.scala 349:38] - node _T_547 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 349:84] - node _T_548 = eq(_T_547, UInt<1>("h01")) @[axi4_to_ahb.scala 349:91] - node _T_549 = and(_T_546, _T_548) @[axi4_to_ahb.scala 349:71] - node _T_550 = bits(_T_549, 0, 0) @[axi4_to_ahb.scala 349:111] - node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:142] - node _T_552 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 167:42] - node _T_553 = eq(_T_552, UInt<8>("h0ff")) @[axi4_to_ahb.scala 167:49] + buf_addr_in <= _T_537 @[axi4_to_ahb.scala 322:15] + node _T_538 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 323:27] + buf_tag_in <= _T_538 @[axi4_to_ahb.scala 323:14] + node _T_539 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 324:32] + buf_byteen_in <= _T_539 @[axi4_to_ahb.scala 324:17] + node _T_540 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 325:33] + node _T_541 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 325:59] + node _T_542 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 325:80] + node _T_543 = mux(_T_540, _T_541, _T_542) @[axi4_to_ahb.scala 325:21] + buf_data_in <= _T_543 @[axi4_to_ahb.scala 325:15] + node _T_544 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 326:52] + node _T_545 = eq(_T_544, UInt<2>("h03")) @[axi4_to_ahb.scala 326:58] + node _T_546 = and(buf_aligned_in, _T_545) @[axi4_to_ahb.scala 326:38] + node _T_547 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 326:84] + node _T_548 = eq(_T_547, UInt<1>("h01")) @[axi4_to_ahb.scala 326:91] + node _T_549 = and(_T_546, _T_548) @[axi4_to_ahb.scala 326:71] + node _T_550 = bits(_T_549, 0, 0) @[axi4_to_ahb.scala 326:111] + node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 326:142] + node _T_552 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 160:40] + node _T_553 = eq(_T_552, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:47] node _T_554 = bits(_T_553, 0, 0) @[Bitwise.scala 72:15] node _T_555 = mux(_T_554, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_556 = and(UInt<2>("h03"), _T_555) @[axi4_to_ahb.scala 167:25] - node _T_557 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 168:35] - node _T_558 = eq(_T_557, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:42] - node _T_559 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 168:64] - node _T_560 = eq(_T_559, UInt<8>("h0f")) @[axi4_to_ahb.scala 168:71] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 168:55] + node _T_556 = and(UInt<2>("h03"), _T_555) @[axi4_to_ahb.scala 160:23] + node _T_557 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 161:35] + node _T_558 = eq(_T_557, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:42] + node _T_559 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 161:64] + node _T_560 = eq(_T_559, UInt<8>("h0f")) @[axi4_to_ahb.scala 161:71] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 161:55] node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] node _T_563 = mux(_T_562, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_564 = and(UInt<2>("h02"), _T_563) @[axi4_to_ahb.scala 168:16] - node _T_565 = or(_T_556, _T_564) @[axi4_to_ahb.scala 167:64] - node _T_566 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 169:40] - node _T_567 = eq(_T_566, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:47] - node _T_568 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 169:69] - node _T_569 = eq(_T_568, UInt<6>("h030")) @[axi4_to_ahb.scala 169:76] - node _T_570 = or(_T_567, _T_569) @[axi4_to_ahb.scala 169:60] - node _T_571 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 169:98] - node _T_572 = eq(_T_571, UInt<8>("h0c")) @[axi4_to_ahb.scala 169:105] - node _T_573 = or(_T_570, _T_572) @[axi4_to_ahb.scala 169:89] - node _T_574 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 169:132] - node _T_575 = eq(_T_574, UInt<8>("h03")) @[axi4_to_ahb.scala 169:139] - node _T_576 = or(_T_573, _T_575) @[axi4_to_ahb.scala 169:123] + node _T_564 = and(UInt<2>("h02"), _T_563) @[axi4_to_ahb.scala 161:16] + node _T_565 = or(_T_556, _T_564) @[axi4_to_ahb.scala 160:62] + node _T_566 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 162:40] + node _T_567 = eq(_T_566, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:47] + node _T_568 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 162:69] + node _T_569 = eq(_T_568, UInt<6>("h030")) @[axi4_to_ahb.scala 162:76] + node _T_570 = or(_T_567, _T_569) @[axi4_to_ahb.scala 162:60] + node _T_571 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 162:98] + node _T_572 = eq(_T_571, UInt<8>("h0c")) @[axi4_to_ahb.scala 162:105] + node _T_573 = or(_T_570, _T_572) @[axi4_to_ahb.scala 162:89] + node _T_574 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 162:132] + node _T_575 = eq(_T_574, UInt<8>("h03")) @[axi4_to_ahb.scala 162:139] + node _T_576 = or(_T_573, _T_575) @[axi4_to_ahb.scala 162:123] node _T_577 = bits(_T_576, 0, 0) @[Bitwise.scala 72:15] node _T_578 = mux(_T_577, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_579 = and(UInt<2>("h01"), _T_578) @[axi4_to_ahb.scala 169:21] - node _T_580 = or(_T_565, _T_579) @[axi4_to_ahb.scala 168:93] - node _T_581 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:161] - node _T_582 = mux(_T_550, _T_580, _T_581) @[axi4_to_ahb.scala 349:21] - buf_size_in <= _T_582 @[axi4_to_ahb.scala 349:15] - node _T_583 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 350:32] - node _T_584 = eq(_T_583, UInt<1>("h00")) @[axi4_to_ahb.scala 350:39] - node _T_585 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:17] - node _T_586 = eq(_T_585, UInt<1>("h00")) @[axi4_to_ahb.scala 351:24] - node _T_587 = or(_T_584, _T_586) @[axi4_to_ahb.scala 350:48] - node _T_588 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:47] - node _T_589 = eq(_T_588, UInt<2>("h01")) @[axi4_to_ahb.scala 351:54] - node _T_590 = or(_T_587, _T_589) @[axi4_to_ahb.scala 351:33] - node _T_591 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:86] - node _T_592 = eq(_T_591, UInt<2>("h02")) @[axi4_to_ahb.scala 351:93] - node _T_593 = or(_T_590, _T_592) @[axi4_to_ahb.scala 351:72] - node _T_594 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 352:18] - node _T_595 = eq(_T_594, UInt<2>("h03")) @[axi4_to_ahb.scala 352:25] - node _T_596 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:55] - node _T_597 = eq(_T_596, UInt<2>("h03")) @[axi4_to_ahb.scala 352:62] - node _T_598 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:90] - node _T_599 = eq(_T_598, UInt<4>("h0c")) @[axi4_to_ahb.scala 352:97] - node _T_600 = or(_T_597, _T_599) @[axi4_to_ahb.scala 352:74] - node _T_601 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:125] - node _T_602 = eq(_T_601, UInt<6>("h030")) @[axi4_to_ahb.scala 352:132] - node _T_603 = or(_T_600, _T_602) @[axi4_to_ahb.scala 352:109] - node _T_604 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:161] - node _T_605 = eq(_T_604, UInt<8>("h0c0")) @[axi4_to_ahb.scala 352:168] - node _T_606 = or(_T_603, _T_605) @[axi4_to_ahb.scala 352:145] - node _T_607 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 353:21] - node _T_608 = eq(_T_607, UInt<4>("h0f")) @[axi4_to_ahb.scala 353:28] - node _T_609 = or(_T_606, _T_608) @[axi4_to_ahb.scala 352:181] - node _T_610 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 353:56] - node _T_611 = eq(_T_610, UInt<8>("h0f0")) @[axi4_to_ahb.scala 353:63] - node _T_612 = or(_T_609, _T_611) @[axi4_to_ahb.scala 353:40] - node _T_613 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 353:92] - node _T_614 = eq(_T_613, UInt<8>("h0ff")) @[axi4_to_ahb.scala 353:99] - node _T_615 = or(_T_612, _T_614) @[axi4_to_ahb.scala 353:76] - node _T_616 = and(_T_595, _T_615) @[axi4_to_ahb.scala 352:38] - node _T_617 = or(_T_593, _T_616) @[axi4_to_ahb.scala 351:106] - buf_aligned_in <= _T_617 @[axi4_to_ahb.scala 350:18] - node _T_618 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 355:39] - node _T_619 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 355:58] - node _T_620 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 355:83] + node _T_579 = and(UInt<2>("h01"), _T_578) @[axi4_to_ahb.scala 162:21] + node _T_580 = or(_T_565, _T_579) @[axi4_to_ahb.scala 161:93] + node _T_581 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 326:161] + node _T_582 = mux(_T_550, _T_580, _T_581) @[axi4_to_ahb.scala 326:21] + buf_size_in <= _T_582 @[axi4_to_ahb.scala 326:15] + node _T_583 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 327:32] + node _T_584 = eq(_T_583, UInt<1>("h00")) @[axi4_to_ahb.scala 327:39] + node _T_585 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 328:17] + node _T_586 = eq(_T_585, UInt<1>("h00")) @[axi4_to_ahb.scala 328:24] + node _T_587 = or(_T_584, _T_586) @[axi4_to_ahb.scala 327:48] + node _T_588 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 328:47] + node _T_589 = eq(_T_588, UInt<2>("h01")) @[axi4_to_ahb.scala 328:54] + node _T_590 = or(_T_587, _T_589) @[axi4_to_ahb.scala 328:33] + node _T_591 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 328:86] + node _T_592 = eq(_T_591, UInt<2>("h02")) @[axi4_to_ahb.scala 328:93] + node _T_593 = or(_T_590, _T_592) @[axi4_to_ahb.scala 328:72] + node _T_594 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:18] + node _T_595 = eq(_T_594, UInt<2>("h03")) @[axi4_to_ahb.scala 329:25] + node _T_596 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 329:55] + node _T_597 = eq(_T_596, UInt<2>("h03")) @[axi4_to_ahb.scala 329:62] + node _T_598 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 329:90] + node _T_599 = eq(_T_598, UInt<4>("h0c")) @[axi4_to_ahb.scala 329:97] + node _T_600 = or(_T_597, _T_599) @[axi4_to_ahb.scala 329:74] + node _T_601 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 329:125] + node _T_602 = eq(_T_601, UInt<6>("h030")) @[axi4_to_ahb.scala 329:132] + node _T_603 = or(_T_600, _T_602) @[axi4_to_ahb.scala 329:109] + node _T_604 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 329:161] + node _T_605 = eq(_T_604, UInt<8>("h0c0")) @[axi4_to_ahb.scala 329:168] + node _T_606 = or(_T_603, _T_605) @[axi4_to_ahb.scala 329:145] + node _T_607 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:21] + node _T_608 = eq(_T_607, UInt<4>("h0f")) @[axi4_to_ahb.scala 330:28] + node _T_609 = or(_T_606, _T_608) @[axi4_to_ahb.scala 329:181] + node _T_610 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:56] + node _T_611 = eq(_T_610, UInt<8>("h0f0")) @[axi4_to_ahb.scala 330:63] + node _T_612 = or(_T_609, _T_611) @[axi4_to_ahb.scala 330:40] + node _T_613 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:92] + node _T_614 = eq(_T_613, UInt<8>("h0ff")) @[axi4_to_ahb.scala 330:99] + node _T_615 = or(_T_612, _T_614) @[axi4_to_ahb.scala 330:76] + node _T_616 = and(_T_595, _T_615) @[axi4_to_ahb.scala 329:38] + node _T_617 = or(_T_593, _T_616) @[axi4_to_ahb.scala 328:106] + buf_aligned_in <= _T_617 @[axi4_to_ahb.scala 327:18] + node _T_618 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 332:39] + node _T_619 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 332:58] + node _T_620 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 332:83] node _T_621 = cat(_T_619, _T_620) @[Cat.scala 29:58] - node _T_622 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 355:104] - node _T_623 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 355:129] + node _T_622 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 332:104] + node _T_623 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 332:129] node _T_624 = cat(_T_622, _T_623) @[Cat.scala 29:58] - node _T_625 = mux(_T_618, _T_621, _T_624) @[axi4_to_ahb.scala 355:22] - io.ahb_haddr <= _T_625 @[axi4_to_ahb.scala 355:16] - node _T_626 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 356:39] + node _T_625 = mux(_T_618, _T_621, _T_624) @[axi4_to_ahb.scala 332:22] + io.ahb_haddr <= _T_625 @[axi4_to_ahb.scala 332:16] + node _T_626 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 333:39] node _T_627 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_628 = mux(_T_627, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_629 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 356:90] - node _T_630 = and(_T_628, _T_629) @[axi4_to_ahb.scala 356:77] + node _T_629 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 333:90] + node _T_630 = and(_T_628, _T_629) @[axi4_to_ahb.scala 333:77] node _T_631 = cat(UInt<1>("h00"), _T_630) @[Cat.scala 29:58] node _T_632 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_633 = mux(_T_632, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_634 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 356:144] - node _T_635 = and(_T_633, _T_634) @[axi4_to_ahb.scala 356:134] + node _T_634 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 333:144] + node _T_635 = and(_T_633, _T_634) @[axi4_to_ahb.scala 333:134] node _T_636 = cat(UInt<1>("h00"), _T_635) @[Cat.scala 29:58] - node _T_637 = mux(_T_626, _T_631, _T_636) @[axi4_to_ahb.scala 356:22] - io.ahb_hsize <= _T_637 @[axi4_to_ahb.scala 356:16] - io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 358:17] - io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 359:20] - node _T_638 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 360:47] - node _T_639 = not(_T_638) @[axi4_to_ahb.scala 360:33] + node _T_637 = mux(_T_626, _T_631, _T_636) @[axi4_to_ahb.scala 333:22] + io.ahb_hsize <= _T_637 @[axi4_to_ahb.scala 333:16] + io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 335:17] + io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 336:20] + node _T_638 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 337:47] + node _T_639 = not(_T_638) @[axi4_to_ahb.scala 337:33] node _T_640 = cat(UInt<1>("h01"), _T_639) @[Cat.scala 29:58] - io.ahb_hprot <= _T_640 @[axi4_to_ahb.scala 360:16] - node _T_641 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 361:40] - node _T_642 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 361:55] - node _T_643 = eq(_T_642, UInt<1>("h01")) @[axi4_to_ahb.scala 361:62] - node _T_644 = mux(_T_641, _T_643, buf_write) @[axi4_to_ahb.scala 361:23] - io.ahb_hwrite <= _T_644 @[axi4_to_ahb.scala 361:17] - node _T_645 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 362:28] - io.ahb_hwdata <= _T_645 @[axi4_to_ahb.scala 362:17] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 364:15] - node _T_646 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 365:43] - node _T_647 = mux(_T_646, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 365:23] + io.ahb_hprot <= _T_640 @[axi4_to_ahb.scala 337:16] + node _T_641 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 338:40] + node _T_642 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 338:55] + node _T_643 = eq(_T_642, UInt<1>("h01")) @[axi4_to_ahb.scala 338:62] + node _T_644 = mux(_T_641, _T_643, buf_write) @[axi4_to_ahb.scala 338:23] + io.ahb_hwrite <= _T_644 @[axi4_to_ahb.scala 338:17] + node _T_645 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 339:28] + io.ahb_hwdata <= _T_645 @[axi4_to_ahb.scala 339:17] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 341:15] + node _T_646 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 342:43] + node _T_647 = mux(_T_646, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 342:23] node _T_648 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_649 = mux(_T_648, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_650 = and(_T_649, UInt<2>("h02")) @[axi4_to_ahb.scala 365:88] + node _T_650 = and(_T_649, UInt<2>("h02")) @[axi4_to_ahb.scala 342:88] node _T_651 = cat(_T_647, _T_650) @[Cat.scala 29:58] - slave_opc <= _T_651 @[axi4_to_ahb.scala 365:13] - node _T_652 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 366:41] - node _T_653 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 366:66] + slave_opc <= _T_651 @[axi4_to_ahb.scala 342:13] + node _T_652 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 343:41] + node _T_653 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 343:66] node _T_654 = cat(_T_653, _T_653) @[Cat.scala 29:58] - node _T_655 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 366:91] - node _T_656 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 366:110] - node _T_657 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 366:131] - node _T_658 = mux(_T_655, _T_656, _T_657) @[axi4_to_ahb.scala 366:79] - node _T_659 = mux(_T_652, _T_654, _T_658) @[axi4_to_ahb.scala 366:21] - slave_rdata <= _T_659 @[axi4_to_ahb.scala 366:15] - node _T_660 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 367:26] - slave_tag <= _T_660 @[axi4_to_ahb.scala 367:13] - node _T_661 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 369:33] - node _T_662 = neq(_T_661, UInt<1>("h00")) @[axi4_to_ahb.scala 369:40] - node _T_663 = and(_T_662, io.ahb_hready) @[axi4_to_ahb.scala 369:52] - node _T_664 = and(_T_663, io.ahb_hwrite) @[axi4_to_ahb.scala 369:68] - last_addr_en <= _T_664 @[axi4_to_ahb.scala 369:16] - node _T_665 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 371:30] - node _T_666 = and(_T_665, master_ready) @[axi4_to_ahb.scala 371:47] - wrbuf_en <= _T_666 @[axi4_to_ahb.scala 371:12] - node _T_667 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 372:34] - node _T_668 = and(_T_667, master_ready) @[axi4_to_ahb.scala 372:50] - wrbuf_data_en <= _T_668 @[axi4_to_ahb.scala 372:17] - node _T_669 = and(master_valid, master_ready) @[axi4_to_ahb.scala 373:34] - node _T_670 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 373:62] - node _T_671 = eq(_T_670, UInt<1>("h01")) @[axi4_to_ahb.scala 373:69] - node _T_672 = and(_T_669, _T_671) @[axi4_to_ahb.scala 373:49] - wrbuf_cmd_sent <= _T_672 @[axi4_to_ahb.scala 373:18] - node _T_673 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 374:33] - node _T_674 = and(wrbuf_cmd_sent, _T_673) @[axi4_to_ahb.scala 374:31] - wrbuf_rst <= _T_674 @[axi4_to_ahb.scala 374:13] - node _T_675 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 376:35] - node _T_676 = and(wrbuf_vld, _T_675) @[axi4_to_ahb.scala 376:33] - node _T_677 = eq(_T_676, UInt<1>("h00")) @[axi4_to_ahb.scala 376:21] - node _T_678 = and(_T_677, master_ready) @[axi4_to_ahb.scala 376:52] - io.axi_awready <= _T_678 @[axi4_to_ahb.scala 376:18] - node _T_679 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 377:39] - node _T_680 = and(wrbuf_data_vld, _T_679) @[axi4_to_ahb.scala 377:37] - node _T_681 = eq(_T_680, UInt<1>("h00")) @[axi4_to_ahb.scala 377:20] - node _T_682 = and(_T_681, master_ready) @[axi4_to_ahb.scala 377:56] - io.axi_wready <= _T_682 @[axi4_to_ahb.scala 377:17] - node _T_683 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 378:33] - node _T_684 = eq(_T_683, UInt<1>("h00")) @[axi4_to_ahb.scala 378:21] - node _T_685 = and(_T_684, master_ready) @[axi4_to_ahb.scala 378:51] - io.axi_arready <= _T_685 @[axi4_to_ahb.scala 378:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 379:16] - node _T_686 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:68] - node _T_687 = mux(_T_686, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 382:52] - node _T_688 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 382:88] - node _T_689 = and(_T_687, _T_688) @[axi4_to_ahb.scala 382:86] - reg _T_690 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 382:48] - _T_690 <= _T_689 @[axi4_to_ahb.scala 382:48] - wrbuf_vld <= _T_690 @[axi4_to_ahb.scala 382:18] - node _T_691 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:73] - node _T_692 = mux(_T_691, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 383:52] - node _T_693 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 383:99] - node _T_694 = and(_T_692, _T_693) @[axi4_to_ahb.scala 383:97] - reg _T_695 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 383:48] - _T_695 <= _T_694 @[axi4_to_ahb.scala 383:48] - wrbuf_data_vld <= _T_695 @[axi4_to_ahb.scala 383:18] - node _T_696 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 385:57] - node _T_697 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 385:91] + node _T_655 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 343:91] + node _T_656 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 343:110] + node _T_657 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 343:131] + node _T_658 = mux(_T_655, _T_656, _T_657) @[axi4_to_ahb.scala 343:79] + node _T_659 = mux(_T_652, _T_654, _T_658) @[axi4_to_ahb.scala 343:21] + slave_rdata <= _T_659 @[axi4_to_ahb.scala 343:15] + node _T_660 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 344:26] + slave_tag <= _T_660 @[axi4_to_ahb.scala 344:13] + node _T_661 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 346:33] + node _T_662 = neq(_T_661, UInt<1>("h00")) @[axi4_to_ahb.scala 346:40] + node _T_663 = and(_T_662, io.ahb_hready) @[axi4_to_ahb.scala 346:52] + node _T_664 = and(_T_663, io.ahb_hwrite) @[axi4_to_ahb.scala 346:68] + last_addr_en <= _T_664 @[axi4_to_ahb.scala 346:16] + node _T_665 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 348:30] + node _T_666 = and(_T_665, master_ready) @[axi4_to_ahb.scala 348:47] + wrbuf_en <= _T_666 @[axi4_to_ahb.scala 348:12] + node _T_667 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 349:34] + node _T_668 = and(_T_667, master_ready) @[axi4_to_ahb.scala 349:50] + wrbuf_data_en <= _T_668 @[axi4_to_ahb.scala 349:17] + node _T_669 = and(master_valid, master_ready) @[axi4_to_ahb.scala 350:34] + node _T_670 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 350:62] + node _T_671 = eq(_T_670, UInt<1>("h01")) @[axi4_to_ahb.scala 350:69] + node _T_672 = and(_T_669, _T_671) @[axi4_to_ahb.scala 350:49] + wrbuf_cmd_sent <= _T_672 @[axi4_to_ahb.scala 350:18] + node _T_673 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 351:33] + node _T_674 = and(wrbuf_cmd_sent, _T_673) @[axi4_to_ahb.scala 351:31] + wrbuf_rst <= _T_674 @[axi4_to_ahb.scala 351:13] + node _T_675 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 353:35] + node _T_676 = and(wrbuf_vld, _T_675) @[axi4_to_ahb.scala 353:33] + node _T_677 = eq(_T_676, UInt<1>("h00")) @[axi4_to_ahb.scala 353:21] + node _T_678 = and(_T_677, master_ready) @[axi4_to_ahb.scala 353:52] + io.axi_awready <= _T_678 @[axi4_to_ahb.scala 353:18] + node _T_679 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 354:39] + node _T_680 = and(wrbuf_data_vld, _T_679) @[axi4_to_ahb.scala 354:37] + node _T_681 = eq(_T_680, UInt<1>("h00")) @[axi4_to_ahb.scala 354:20] + node _T_682 = and(_T_681, master_ready) @[axi4_to_ahb.scala 354:56] + io.axi_wready <= _T_682 @[axi4_to_ahb.scala 354:17] + node _T_683 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 355:33] + node _T_684 = eq(_T_683, UInt<1>("h00")) @[axi4_to_ahb.scala 355:21] + node _T_685 = and(_T_684, master_ready) @[axi4_to_ahb.scala 355:51] + io.axi_arready <= _T_685 @[axi4_to_ahb.scala 355:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 356:16] + node _T_686 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 358:71] + node _T_687 = mux(_T_686, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 358:55] + node _T_688 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 358:91] + node _T_689 = and(_T_687, _T_688) @[axi4_to_ahb.scala 358:89] + reg _T_690 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 358:51] + _T_690 <= _T_689 @[axi4_to_ahb.scala 358:51] + wrbuf_vld <= _T_690 @[axi4_to_ahb.scala 358:21] + node _T_691 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 359:76] + node _T_692 = mux(_T_691, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 359:55] + node _T_693 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 359:102] + node _T_694 = and(_T_692, _T_693) @[axi4_to_ahb.scala 359:100] + reg _T_695 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 359:51] + _T_695 <= _T_694 @[axi4_to_ahb.scala 359:51] + wrbuf_data_vld <= _T_695 @[axi4_to_ahb.scala 359:21] + node _T_696 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 360:65] + node _T_697 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 360:99] reg _T_698 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_697 : @[Reg.scala 28:19] _T_698 <= _T_696 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_698 @[axi4_to_ahb.scala 385:13] - node _T_699 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 386:60] - node _T_700 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 386:88] + wrbuf_tag <= _T_698 @[axi4_to_ahb.scala 360:21] + node _T_699 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 361:67] + node _T_700 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 361:95] reg _T_701 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_700 : @[Reg.scala 28:19] _T_701 <= _T_699 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_701 @[axi4_to_ahb.scala 386:14] - node _T_702 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 388:48] + wrbuf_size <= _T_701 @[axi4_to_ahb.scala 361:21] + node _T_702 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 362:55] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -1296,8 +1296,8 @@ circuit axi4_to_ahb : rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_703 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_703 <= io.axi_awaddr @[el2_lib.scala 514:16] - wrbuf_addr <= _T_703 @[axi4_to_ahb.scala 388:14] - node _T_704 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 389:52] + wrbuf_addr <= _T_703 @[axi4_to_ahb.scala 362:21] + node _T_704 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 363:59] inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -1306,37 +1306,37 @@ circuit axi4_to_ahb : rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_705 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_705 <= io.axi_wdata @[el2_lib.scala 514:16] - wrbuf_data <= _T_705 @[axi4_to_ahb.scala 389:14] - node _T_706 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 392:27] - node _T_707 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 392:60] + wrbuf_data <= _T_705 @[axi4_to_ahb.scala 363:21] + node _T_706 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 364:66] + node _T_707 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 364:99] reg _T_708 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_707 : @[Reg.scala 28:19] _T_708 <= _T_706 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_708 @[axi4_to_ahb.scala 391:16] - node _T_709 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 395:27] - node _T_710 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 395:60] + wrbuf_byteen <= _T_708 @[axi4_to_ahb.scala 364:21] + node _T_709 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 365:67] + node _T_710 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 365:100] reg _T_711 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_710 : @[Reg.scala 28:19] _T_711 <= _T_709 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_711 @[axi4_to_ahb.scala 394:17] - node _T_712 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 403:50] + last_bus_addr <= _T_711 @[axi4_to_ahb.scala 365:21] + node _T_712 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 366:89] reg _T_713 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_712 : @[Reg.scala 28:19] _T_713 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_713 @[axi4_to_ahb.scala 402:13] - node _T_714 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 406:25] - node _T_715 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 406:60] + buf_write <= _T_713 @[axi4_to_ahb.scala 366:21] + node _T_714 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 367:64] + node _T_715 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 367:99] reg _T_716 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_715 : @[Reg.scala 28:19] _T_716 <= _T_714 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_716 @[axi4_to_ahb.scala 405:11] - node _T_717 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 409:33] - node _T_718 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 409:52] - node _T_719 = bits(_T_718, 0, 0) @[axi4_to_ahb.scala 409:69] + buf_tag <= _T_716 @[axi4_to_ahb.scala 367:21] + node _T_717 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 368:42] + node _T_718 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 368:61] + node _T_719 = bits(_T_718, 0, 0) @[axi4_to_ahb.scala 368:78] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -1345,30 +1345,30 @@ circuit axi4_to_ahb : rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_720 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_720 <= _T_717 @[el2_lib.scala 514:16] - buf_addr <= _T_720 @[axi4_to_ahb.scala 409:12] - node _T_721 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 412:26] - node _T_722 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 412:55] + buf_addr <= _T_720 @[axi4_to_ahb.scala 368:21] + node _T_721 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 369:65] + node _T_722 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 369:94] reg _T_723 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_722 : @[Reg.scala 28:19] _T_723 <= _T_721 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_723 @[axi4_to_ahb.scala 411:12] - node _T_724 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 415:52] + buf_size <= _T_723 @[axi4_to_ahb.scala 369:21] + node _T_724 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 370:91] reg _T_725 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_724 : @[Reg.scala 28:19] _T_725 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_725 @[axi4_to_ahb.scala 414:15] - node _T_726 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 418:28] - node _T_727 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 418:57] + buf_aligned <= _T_725 @[axi4_to_ahb.scala 370:21] + node _T_726 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 371:67] + node _T_727 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 371:96] reg _T_728 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_727 : @[Reg.scala 28:19] _T_728 <= _T_726 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_728 @[axi4_to_ahb.scala 417:14] - node _T_729 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 421:33] - node _T_730 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 421:57] - node _T_731 = bits(_T_730, 0, 0) @[axi4_to_ahb.scala 421:80] + buf_byteen <= _T_728 @[axi4_to_ahb.scala 371:21] + node _T_729 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 372:42] + node _T_730 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 372:66] + node _T_731 = bits(_T_730, 0, 0) @[axi4_to_ahb.scala 372:89] inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -1377,96 +1377,96 @@ circuit axi4_to_ahb : rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_732 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_732 <= _T_729 @[el2_lib.scala 514:16] - buf_data <= _T_732 @[axi4_to_ahb.scala 421:12] - node _T_733 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 424:50] + buf_data <= _T_732 @[axi4_to_ahb.scala 372:21] + node _T_733 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 373:89] reg _T_734 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_733 : @[Reg.scala 28:19] _T_734 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_734 @[axi4_to_ahb.scala 423:16] - node _T_735 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 427:22] - node _T_736 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 427:60] + slvbuf_write <= _T_734 @[axi4_to_ahb.scala 373:21] + node _T_735 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 374:61] + node _T_736 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 374:99] reg _T_737 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_736 : @[Reg.scala 28:19] _T_737 <= _T_735 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_737 @[axi4_to_ahb.scala 426:14] - node _T_738 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 430:59] + slvbuf_tag <= _T_737 @[axi4_to_ahb.scala 374:21] + node _T_738 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 375:99] reg _T_739 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_738 : @[Reg.scala 28:19] _T_739 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_739 @[axi4_to_ahb.scala 429:16] - node _T_740 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 434:32] - node _T_741 = mux(_T_740, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 434:16] - node _T_742 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 434:52] - node _T_743 = and(_T_741, _T_742) @[axi4_to_ahb.scala 434:50] - reg _T_744 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 434:12] - _T_744 <= _T_743 @[axi4_to_ahb.scala 434:12] - cmd_doneQ <= _T_744 @[axi4_to_ahb.scala 433:13] - node _T_745 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 438:31] - node _T_746 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 438:70] + slvbuf_error <= _T_739 @[axi4_to_ahb.scala 375:21] + node _T_740 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 376:72] + node _T_741 = mux(_T_740, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 376:56] + node _T_742 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 376:92] + node _T_743 = and(_T_741, _T_742) @[axi4_to_ahb.scala 376:90] + reg _T_744 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 376:52] + _T_744 <= _T_743 @[axi4_to_ahb.scala 376:52] + cmd_doneQ <= _T_744 @[axi4_to_ahb.scala 376:21] + node _T_745 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 377:71] + node _T_746 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 377:110] reg _T_747 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_746 : @[Reg.scala 28:19] _T_747 <= _T_745 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_747 @[axi4_to_ahb.scala 437:21] - reg _T_748 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 443:12] - _T_748 <= io.ahb_hready @[axi4_to_ahb.scala 443:12] - ahb_hready_q <= _T_748 @[axi4_to_ahb.scala 442:16] - node _T_749 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 446:26] - reg _T_750 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 446:12] - _T_750 <= _T_749 @[axi4_to_ahb.scala 446:12] - ahb_htrans_q <= _T_750 @[axi4_to_ahb.scala 445:16] - reg _T_751 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 449:12] - _T_751 <= io.ahb_hwrite @[axi4_to_ahb.scala 449:12] - ahb_hwrite_q <= _T_751 @[axi4_to_ahb.scala 448:16] - reg _T_752 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 452:12] - _T_752 <= io.ahb_hresp @[axi4_to_ahb.scala 452:12] - ahb_hresp_q <= _T_752 @[axi4_to_ahb.scala 451:15] - node _T_753 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 455:26] - reg _T_754 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 455:12] - _T_754 <= _T_753 @[axi4_to_ahb.scala 455:12] - ahb_hrdata_q <= _T_754 @[axi4_to_ahb.scala 454:16] - node _T_755 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 458:43] - node _T_756 = or(_T_755, io.clk_override) @[axi4_to_ahb.scala 458:58] - node _T_757 = and(io.bus_clk_en, _T_756) @[axi4_to_ahb.scala 458:30] - buf_clken <= _T_757 @[axi4_to_ahb.scala 458:13] - node _T_758 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 459:69] - node _T_759 = and(io.ahb_hready, _T_758) @[axi4_to_ahb.scala 459:54] - node _T_760 = or(_T_759, io.clk_override) @[axi4_to_ahb.scala 459:74] - node _T_761 = and(io.bus_clk_en, _T_760) @[axi4_to_ahb.scala 459:36] - ahbm_addr_clken <= _T_761 @[axi4_to_ahb.scala 459:19] - node _T_762 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 460:50] - node _T_763 = or(_T_762, io.clk_override) @[axi4_to_ahb.scala 460:60] - node _T_764 = and(io.bus_clk_en, _T_763) @[axi4_to_ahb.scala 460:36] - ahbm_data_clken <= _T_764 @[axi4_to_ahb.scala 460:19] + buf_cmd_byte_ptrQ <= _T_747 @[axi4_to_ahb.scala 377:21] + reg _T_748 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 378:52] + _T_748 <= io.ahb_hready @[axi4_to_ahb.scala 378:52] + ahb_hready_q <= _T_748 @[axi4_to_ahb.scala 378:21] + node _T_749 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 379:66] + reg _T_750 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:52] + _T_750 <= _T_749 @[axi4_to_ahb.scala 379:52] + ahb_htrans_q <= _T_750 @[axi4_to_ahb.scala 379:21] + reg _T_751 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 380:57] + _T_751 <= io.ahb_hwrite @[axi4_to_ahb.scala 380:57] + ahb_hwrite_q <= _T_751 @[axi4_to_ahb.scala 380:21] + reg _T_752 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 381:52] + _T_752 <= io.ahb_hresp @[axi4_to_ahb.scala 381:52] + ahb_hresp_q <= _T_752 @[axi4_to_ahb.scala 381:21] + node _T_753 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 382:71] + reg _T_754 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 382:57] + _T_754 <= _T_753 @[axi4_to_ahb.scala 382:57] + ahb_hrdata_q <= _T_754 @[axi4_to_ahb.scala 382:21] + node _T_755 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 384:43] + node _T_756 = or(_T_755, io.clk_override) @[axi4_to_ahb.scala 384:58] + node _T_757 = and(io.bus_clk_en, _T_756) @[axi4_to_ahb.scala 384:30] + buf_clken <= _T_757 @[axi4_to_ahb.scala 384:13] + node _T_758 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 385:69] + node _T_759 = and(io.ahb_hready, _T_758) @[axi4_to_ahb.scala 385:54] + node _T_760 = or(_T_759, io.clk_override) @[axi4_to_ahb.scala 385:74] + node _T_761 = and(io.bus_clk_en, _T_760) @[axi4_to_ahb.scala 385:36] + ahbm_addr_clken <= _T_761 @[axi4_to_ahb.scala 385:19] + node _T_762 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 386:50] + node _T_763 = or(_T_762, io.clk_override) @[axi4_to_ahb.scala 386:60] + node _T_764 = and(io.bus_clk_en, _T_763) @[axi4_to_ahb.scala 386:36] + ahbm_data_clken <= _T_764 @[axi4_to_ahb.scala 386:19] inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_6.io.en <= buf_clken @[el2_lib.scala 485:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 463:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 389:12] inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_7.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 464:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 390:12] inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[el2_lib.scala 485:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 465:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 391:17] inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_9.io.en <= ahbm_data_clken @[el2_lib.scala 485:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 466:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 392:17] diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v index 5d0a8eb1..2ce4e51f 100644 --- a/axi4_to_ahb.v +++ b/axi4_to_ahb.v @@ -132,31 +132,31 @@ module axi4_to_ahb( wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 63:22 axi4_to_ahb.scala 464:12] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 63:22 axi4_to_ahb.scala 390:12] reg [2:0] buf_state; // @[axi4_to_ahb.scala 69:45] wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 89:21 axi4_to_ahb.scala 221:11] - reg wrbuf_vld; // @[axi4_to_ahb.scala 382:48] - reg wrbuf_data_vld; // @[axi4_to_ahb.scala 383:48] - wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 198:27] - wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 199:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 89:21 axi4_to_ahb.scala 200:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 358:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 359:51] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 177:27] + wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 178:30] wire _T_109 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 443:12] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 446:12] - wire _T_116 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 261:58] - wire _T_117 = ahb_hready_q & _T_116; // @[axi4_to_ahb.scala 261:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 465:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 449:12] - wire _T_118 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 261:72] - wire _T_119 = _T_117 & _T_118; // @[axi4_to_ahb.scala 261:70] + reg ahb_hready_q; // @[axi4_to_ahb.scala 378:52] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 379:52] + wire _T_116 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 240:58] + wire _T_117 = ahb_hready_q & _T_116; // @[axi4_to_ahb.scala 240:36] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 391:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 380:57] + wire _T_118 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 240:72] + wire _T_119 = _T_117 & _T_118; // @[axi4_to_ahb.scala 240:70] wire _T_144 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 452:12] - wire _T_164 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 275:37] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 381:52] + wire _T_164 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 254:37] wire _T_183 = 3'h7 == buf_state; // @[Conditional.scala 37:30] wire _T_194 = 3'h3 == buf_state; // @[Conditional.scala 37:30] wire _T_196 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_197 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 307:33] - wire _T_200 = _T_197 & _T_116; // @[axi4_to_ahb.scala 307:48] + wire _T_197 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 286:33] + wire _T_200 = _T_197 & _T_116; // @[axi4_to_ahb.scala 286:48] wire _T_305 = 3'h4 == buf_state; // @[Conditional.scala 37:30] wire _GEN_15 = _T_305 & _T_200; // @[Conditional.scala 39:67] wire _GEN_19 = _T_196 ? _T_200 : _GEN_15; // @[Conditional.scala 39:67] @@ -165,11 +165,11 @@ module axi4_to_ahb( wire _GEN_79 = _T_144 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] wire _GEN_95 = _T_109 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 434:12] - wire _T_306 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 317:34] - wire _T_307 = _T_306 | ahb_hresp_q; // @[axi4_to_ahb.scala 317:50] + reg cmd_doneQ; // @[axi4_to_ahb.scala 376:52] + wire _T_306 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 296:34] + wire _T_307 = _T_306 | ahb_hresp_q; // @[axi4_to_ahb.scala 296:50] wire _T_491 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 216:32] + wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 195:32] wire _GEN_1 = _T_491 & slave_ready; // @[Conditional.scala 39:67] wire _GEN_3 = _T_305 ? _T_307 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_20 = _T_196 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] @@ -178,9 +178,9 @@ module axi4_to_ahb( wire _GEN_69 = _T_144 ? _T_164 : _GEN_51; // @[Conditional.scala 39:67] wire _GEN_83 = _T_109 ? _T_119 : _GEN_69; // @[Conditional.scala 39:67] wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] - wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 201:20] - wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 201:14] - wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 246:41] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 180:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 180:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 225:41] wire _GEN_8 = _T_305 & _T_51; // @[Conditional.scala 39:67] wire _GEN_29 = _T_196 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] wire _GEN_46 = _T_194 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] @@ -188,19 +188,19 @@ module axi4_to_ahb( wire _GEN_81 = _T_144 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] wire _GEN_97 = _T_109 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 247:26] - wire _T_111 = master_opc == 3'h0; // @[axi4_to_ahb.scala 260:61] - wire _T_112 = master_valid & _T_111; // @[axi4_to_ahb.scala 260:41] - wire [2:0] _T_114 = _T_112 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 260:26] - wire _T_132 = _T_114 == 3'h6; // @[axi4_to_ahb.scala 264:174] - wire _T_133 = _T_119 & _T_132; // @[axi4_to_ahb.scala 264:88] - wire _T_145 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 272:39] - wire _T_146 = ahb_hready_q & _T_145; // @[axi4_to_ahb.scala 272:37] - wire _T_149 = master_valid & _T_51; // @[axi4_to_ahb.scala 272:70] - wire _T_150 = ~_T_149; // @[axi4_to_ahb.scala 272:55] - wire _T_151 = _T_146 & _T_150; // @[axi4_to_ahb.scala 272:53] - wire _T_311 = _T_307 & _T_145; // @[axi4_to_ahb.scala 318:66] - wire _T_312 = _T_311 & slave_ready; // @[axi4_to_ahb.scala 318:81] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 226:26] + wire _T_111 = master_opc == 3'h0; // @[axi4_to_ahb.scala 239:61] + wire _T_112 = master_valid & _T_111; // @[axi4_to_ahb.scala 239:41] + wire [2:0] _T_114 = _T_112 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 239:26] + wire _T_132 = _T_114 == 3'h6; // @[axi4_to_ahb.scala 243:174] + wire _T_133 = _T_119 & _T_132; // @[axi4_to_ahb.scala 243:88] + wire _T_145 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 251:39] + wire _T_146 = ahb_hready_q & _T_145; // @[axi4_to_ahb.scala 251:37] + wire _T_149 = master_valid & _T_51; // @[axi4_to_ahb.scala 251:70] + wire _T_150 = ~_T_149; // @[axi4_to_ahb.scala 251:55] + wire _T_151 = _T_146 & _T_150; // @[axi4_to_ahb.scala 251:53] + wire _T_311 = _T_307 & _T_145; // @[axi4_to_ahb.scala 297:66] + wire _T_312 = _T_311 & slave_ready; // @[axi4_to_ahb.scala 297:81] wire _GEN_4 = _T_305 & _T_312; // @[Conditional.scala 39:67] wire _GEN_26 = _T_196 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] wire _GEN_45 = _T_194 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] @@ -208,15 +208,15 @@ module axi4_to_ahb( wire _GEN_66 = _T_144 ? _T_151 : _GEN_62; // @[Conditional.scala 39:67] wire _GEN_86 = _T_109 ? _T_133 : _GEN_66; // @[Conditional.scala 39:67] wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_157 = master_valid & master_ready; // @[axi4_to_ahb.scala 274:82] - wire _T_160 = _T_157 & _T_111; // @[axi4_to_ahb.scala 274:97] - wire [2:0] _T_162 = _T_160 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 274:67] - wire [2:0] _T_163 = ahb_hresp_q ? 3'h7 : _T_162; // @[axi4_to_ahb.scala 274:26] - wire _T_313 = ~slave_ready; // @[axi4_to_ahb.scala 319:42] - wire _T_314 = ahb_hresp_q | _T_313; // @[axi4_to_ahb.scala 319:40] - wire [2:0] _T_320 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 319:119] - wire [2:0] _T_321 = _T_157 ? _T_320 : 3'h0; // @[axi4_to_ahb.scala 319:75] - wire [2:0] _T_322 = _T_314 ? 3'h5 : _T_321; // @[axi4_to_ahb.scala 319:26] + wire _T_157 = master_valid & master_ready; // @[axi4_to_ahb.scala 253:82] + wire _T_160 = _T_157 & _T_111; // @[axi4_to_ahb.scala 253:97] + wire [2:0] _T_162 = _T_160 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 253:67] + wire [2:0] _T_163 = ahb_hresp_q ? 3'h7 : _T_162; // @[axi4_to_ahb.scala 253:26] + wire _T_313 = ~slave_ready; // @[axi4_to_ahb.scala 298:42] + wire _T_314 = ahb_hresp_q | _T_313; // @[axi4_to_ahb.scala 298:40] + wire [2:0] _T_320 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 298:119] + wire [2:0] _T_321 = _T_157 ? _T_320 : 3'h0; // @[axi4_to_ahb.scala 298:75] + wire [2:0] _T_322 = _T_314 ? 3'h5 : _T_321; // @[axi4_to_ahb.scala 298:26] wire [2:0] _GEN_5 = _T_305 ? _T_322 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_18 = _T_196 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] wire [2:0] _GEN_34 = _T_194 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] @@ -226,14 +226,14 @@ module axi4_to_ahb( wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] reg wrbuf_tag; // @[Reg.scala 27:20] reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16] - wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 202:21] + wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 181:21] reg [2:0] wrbuf_size; // @[Reg.scala 27:20] - wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 203:21] + wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 182:21] reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16] - wire _T_166 = buf_state_en & _T_145; // @[axi4_to_ahb.scala 279:39] - wire _T_393 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 328:55] - wire _T_394 = buf_state_en & _T_393; // @[axi4_to_ahb.scala 328:39] + wire _T_166 = buf_state_en & _T_145; // @[axi4_to_ahb.scala 258:39] + wire _T_393 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 307:55] + wire _T_394 = buf_state_en & _T_393; // @[axi4_to_ahb.scala 307:39] wire _GEN_14 = _T_305 ? _T_394 : _T_491; // @[Conditional.scala 39:67] wire _GEN_33 = _T_196 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] wire _GEN_49 = _T_194 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] @@ -241,37 +241,37 @@ module axi4_to_ahb( wire _GEN_73 = _T_144 ? _T_166 : _GEN_52; // @[Conditional.scala 39:67] wire _GEN_94 = _T_109 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 208:32] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 157:21 axi4_to_ahb.scala 463:12] + wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 187:32] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 157:21 axi4_to_ahb.scala 389:12] reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_647 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 365:23] + wire [1:0] _T_647 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 342:23] reg slvbuf_error; // @[Reg.scala 27:20] wire [1:0] _T_649 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_650 = _T_649 & 2'h2; // @[axi4_to_ahb.scala 365:88] + wire [1:0] _T_650 = _T_649 & 2'h2; // @[axi4_to_ahb.scala 342:88] wire [3:0] slave_opc = {_T_647,_T_650}; // @[Cat.scala 29:58] - wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 209:49] + wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 188:49] reg slvbuf_tag; // @[Reg.scala 27:20] - wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 212:65] + wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 191:65] reg [31:0] last_bus_addr; // @[Reg.scala 27:20] wire [63:0] _T_654 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_655 = buf_state == 3'h5; // @[axi4_to_ahb.scala 366:91] + wire _T_655 = buf_state == 3'h5; // @[axi4_to_ahb.scala 343:91] reg [63:0] buf_data; // @[el2_lib.scala 514:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 65:27 axi4_to_ahb.scala 466:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 455:12] - wire [63:0] _T_658 = _T_655 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 366:79] - wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 219:56] - wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 219:91] - wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 219:74] - wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 250:54] - wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 250:38] - wire _T_65 = |wrbuf_byteen[0]; // @[axi4_to_ahb.scala 183:77] - wire _T_69 = |wrbuf_byteen[1]; // @[axi4_to_ahb.scala 183:77] - wire _T_73 = |wrbuf_byteen[2]; // @[axi4_to_ahb.scala 183:77] - wire _T_77 = |wrbuf_byteen[3]; // @[axi4_to_ahb.scala 183:77] - wire _T_81 = |wrbuf_byteen[4]; // @[axi4_to_ahb.scala 183:77] - wire _T_85 = |wrbuf_byteen[5]; // @[axi4_to_ahb.scala 183:77] - wire _T_89 = |wrbuf_byteen[6]; // @[axi4_to_ahb.scala 183:77] - wire _T_93 = |wrbuf_byteen[7]; // @[axi4_to_ahb.scala 183:77] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 65:27 axi4_to_ahb.scala 392:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 382:57] + wire [63:0] _T_658 = _T_655 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 343:79] + wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 198:56] + wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 198:91] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 198:74] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 229:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 229:38] + wire _T_65 = |wrbuf_byteen[0]; // @[axi4_to_ahb.scala 175:78] + wire _T_69 = |wrbuf_byteen[1]; // @[axi4_to_ahb.scala 175:78] + wire _T_73 = |wrbuf_byteen[2]; // @[axi4_to_ahb.scala 175:78] + wire _T_77 = |wrbuf_byteen[3]; // @[axi4_to_ahb.scala 175:78] + wire _T_81 = |wrbuf_byteen[4]; // @[axi4_to_ahb.scala 175:78] + wire _T_85 = |wrbuf_byteen[5]; // @[axi4_to_ahb.scala 175:78] + wire _T_89 = |wrbuf_byteen[6]; // @[axi4_to_ahb.scala 175:78] + wire _T_93 = |wrbuf_byteen[7]; // @[axi4_to_ahb.scala 175:78] wire [2:0] _T_94 = _T_93 ? 3'h7 : 3'h0; // @[Mux.scala 98:16] wire [2:0] _T_95 = _T_89 ? 3'h6 : _T_94; // @[Mux.scala 98:16] wire [2:0] _T_96 = _T_85 ? 3'h5 : _T_95; // @[Mux.scala 98:16] @@ -280,14 +280,14 @@ module axi4_to_ahb( wire [2:0] _T_99 = _T_73 ? 3'h2 : _T_98; // @[Mux.scala 98:16] wire [2:0] _T_100 = _T_69 ? 3'h1 : _T_99; // @[Mux.scala 98:16] wire [2:0] _T_101 = _T_65 ? 3'h0 : _T_100; // @[Mux.scala 98:16] - wire [2:0] _T_103 = buf_write_in ? _T_101 : master_addr[2:0]; // @[axi4_to_ahb.scala 253:30] - wire _T_104 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 255:51] - wire _T_134 = master_ready & master_valid; // @[axi4_to_ahb.scala 266:33] - wire _T_170 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 281:64] - wire _T_171 = _T_134 & _T_170; // @[axi4_to_ahb.scala 281:48] - wire _T_172 = _T_171 & buf_state_en; // @[axi4_to_ahb.scala 281:79] - wire _T_384 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 326:33] - wire _T_386 = _T_384 & _T_55; // @[axi4_to_ahb.scala 326:48] + wire [2:0] _T_103 = buf_write_in ? _T_101 : master_addr[2:0]; // @[axi4_to_ahb.scala 232:30] + wire _T_104 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 234:51] + wire _T_134 = master_ready & master_valid; // @[axi4_to_ahb.scala 245:33] + wire _T_170 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 260:64] + wire _T_171 = _T_134 & _T_170; // @[axi4_to_ahb.scala 260:48] + wire _T_172 = _T_171 & buf_state_en; // @[axi4_to_ahb.scala 260:79] + wire _T_384 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 305:33] + wire _T_386 = _T_384 & _T_55; // @[axi4_to_ahb.scala 305:48] wire _GEN_12 = _T_305 & _T_386; // @[Conditional.scala 39:67] wire _GEN_32 = _T_196 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] wire _GEN_48 = _T_194 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] @@ -296,47 +296,47 @@ module axi4_to_ahb( wire _GEN_88 = _T_109 ? _T_134 : _GEN_75; // @[Conditional.scala 39:67] wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] wire [1:0] _T_107 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_108 = _T_107 & 2'h2; // @[axi4_to_ahb.scala 256:45] - wire _T_120 = ~master_valid; // @[axi4_to_ahb.scala 262:34] - wire _T_121 = buf_state_en & _T_120; // @[axi4_to_ahb.scala 262:32] + wire [1:0] _T_108 = _T_107 & 2'h2; // @[axi4_to_ahb.scala 235:45] + wire _T_120 = ~master_valid; // @[axi4_to_ahb.scala 241:34] + wire _T_121 = buf_state_en & _T_120; // @[axi4_to_ahb.scala 241:32] reg [31:0] buf_addr; // @[el2_lib.scala 514:16] - wire [2:0] _T_138 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 267:30] - wire _T_139 = ~buf_state_en; // @[axi4_to_ahb.scala 268:44] - wire _T_140 = _T_139 | bypass_en; // @[axi4_to_ahb.scala 268:58] + wire [2:0] _T_138 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 246:30] + wire _T_139 = ~buf_state_en; // @[axi4_to_ahb.scala 247:44] + wire _T_140 = _T_139 | bypass_en; // @[axi4_to_ahb.scala 247:58] wire [1:0] _T_142 = _T_140 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_143 = 2'h2 & _T_142; // @[axi4_to_ahb.scala 268:32] - wire _T_177 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 283:59] - wire _T_178 = _T_177 & buf_state_en; // @[axi4_to_ahb.scala 283:74] - wire _T_179 = ~_T_178; // @[axi4_to_ahb.scala 283:43] + wire [1:0] _T_143 = 2'h2 & _T_142; // @[axi4_to_ahb.scala 247:32] + wire _T_177 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 262:59] + wire _T_178 = _T_177 & buf_state_en; // @[axi4_to_ahb.scala 262:74] + wire _T_179 = ~_T_178; // @[axi4_to_ahb.scala 262:43] wire [1:0] _T_181 = _T_179 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_182 = 2'h2 & _T_181; // @[axi4_to_ahb.scala 283:32] + wire [1:0] _T_182 = 2'h2 & _T_181; // @[axi4_to_ahb.scala 262:32] wire [1:0] _T_192 = _T_139 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_193 = 2'h2 & _T_192; // @[axi4_to_ahb.scala 293:37] + wire [1:0] _T_193 = 2'h2 & _T_192; // @[axi4_to_ahb.scala 272:37] reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_205 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 182:52] - wire _T_208 = 3'h0 >= _T_205; // @[axi4_to_ahb.scala 183:62] - wire _T_209 = buf_byteen[0] & _T_208; // @[axi4_to_ahb.scala 183:48] - wire _T_210 = |_T_209; // @[axi4_to_ahb.scala 183:77] - wire _T_212 = 3'h1 >= _T_205; // @[axi4_to_ahb.scala 183:62] - wire _T_213 = buf_byteen[1] & _T_212; // @[axi4_to_ahb.scala 183:48] - wire _T_214 = |_T_213; // @[axi4_to_ahb.scala 183:77] - wire _T_216 = 3'h2 >= _T_205; // @[axi4_to_ahb.scala 183:62] - wire _T_217 = buf_byteen[2] & _T_216; // @[axi4_to_ahb.scala 183:48] - wire _T_218 = |_T_217; // @[axi4_to_ahb.scala 183:77] - wire _T_220 = 3'h3 >= _T_205; // @[axi4_to_ahb.scala 183:62] - wire _T_221 = buf_byteen[3] & _T_220; // @[axi4_to_ahb.scala 183:48] - wire _T_222 = |_T_221; // @[axi4_to_ahb.scala 183:77] - wire _T_224 = 3'h4 >= _T_205; // @[axi4_to_ahb.scala 183:62] - wire _T_225 = buf_byteen[4] & _T_224; // @[axi4_to_ahb.scala 183:48] - wire _T_226 = |_T_225; // @[axi4_to_ahb.scala 183:77] - wire _T_228 = 3'h5 >= _T_205; // @[axi4_to_ahb.scala 183:62] - wire _T_229 = buf_byteen[5] & _T_228; // @[axi4_to_ahb.scala 183:48] - wire _T_230 = |_T_229; // @[axi4_to_ahb.scala 183:77] - wire _T_232 = 3'h6 >= _T_205; // @[axi4_to_ahb.scala 183:62] - wire _T_233 = buf_byteen[6] & _T_232; // @[axi4_to_ahb.scala 183:48] - wire _T_234 = |_T_233; // @[axi4_to_ahb.scala 183:77] - wire _T_238 = |buf_byteen[7]; // @[axi4_to_ahb.scala 183:77] + wire [2:0] _T_205 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 174:52] + wire _T_208 = 3'h0 >= _T_205; // @[axi4_to_ahb.scala 175:63] + wire _T_209 = buf_byteen[0] & _T_208; // @[axi4_to_ahb.scala 175:49] + wire _T_210 = |_T_209; // @[axi4_to_ahb.scala 175:78] + wire _T_212 = 3'h1 >= _T_205; // @[axi4_to_ahb.scala 175:63] + wire _T_213 = buf_byteen[1] & _T_212; // @[axi4_to_ahb.scala 175:49] + wire _T_214 = |_T_213; // @[axi4_to_ahb.scala 175:78] + wire _T_216 = 3'h2 >= _T_205; // @[axi4_to_ahb.scala 175:63] + wire _T_217 = buf_byteen[2] & _T_216; // @[axi4_to_ahb.scala 175:49] + wire _T_218 = |_T_217; // @[axi4_to_ahb.scala 175:78] + wire _T_220 = 3'h3 >= _T_205; // @[axi4_to_ahb.scala 175:63] + wire _T_221 = buf_byteen[3] & _T_220; // @[axi4_to_ahb.scala 175:49] + wire _T_222 = |_T_221; // @[axi4_to_ahb.scala 175:78] + wire _T_224 = 3'h4 >= _T_205; // @[axi4_to_ahb.scala 175:63] + wire _T_225 = buf_byteen[4] & _T_224; // @[axi4_to_ahb.scala 175:49] + wire _T_226 = |_T_225; // @[axi4_to_ahb.scala 175:78] + wire _T_228 = 3'h5 >= _T_205; // @[axi4_to_ahb.scala 175:63] + wire _T_229 = buf_byteen[5] & _T_228; // @[axi4_to_ahb.scala 175:49] + wire _T_230 = |_T_229; // @[axi4_to_ahb.scala 175:78] + wire _T_232 = 3'h6 >= _T_205; // @[axi4_to_ahb.scala 175:63] + wire _T_233 = buf_byteen[6] & _T_232; // @[axi4_to_ahb.scala 175:49] + wire _T_234 = |_T_233; // @[axi4_to_ahb.scala 175:78] + wire _T_238 = |buf_byteen[7]; // @[axi4_to_ahb.scala 175:78] wire [2:0] _T_239 = _T_238 ? 3'h7 : 3'h0; // @[Mux.scala 98:16] wire [2:0] _T_240 = _T_234 ? 3'h6 : _T_239; // @[Mux.scala 98:16] wire [2:0] _T_241 = _T_230 ? 3'h5 : _T_240; // @[Mux.scala 98:16] @@ -345,17 +345,17 @@ module axi4_to_ahb( wire [2:0] _T_244 = _T_218 ? 3'h2 : _T_243; // @[Mux.scala 98:16] wire [2:0] _T_245 = _T_214 ? 3'h1 : _T_244; // @[Mux.scala 98:16] wire [2:0] _T_246 = _T_210 ? 3'h0 : _T_245; // @[Mux.scala 98:16] - wire [2:0] _T_247 = trxn_done ? _T_246 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 311:30] - wire _T_248 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 312:65] + wire [2:0] _T_247 = trxn_done ? _T_246 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 290:30] + wire _T_248 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 291:65] reg buf_aligned; // @[Reg.scala 27:20] - wire _T_249 = buf_aligned | _T_248; // @[axi4_to_ahb.scala 312:44] - wire [7:0] _T_295 = buf_byteen >> _T_246; // @[axi4_to_ahb.scala 312:92] - wire _T_297 = ~_T_295[0]; // @[axi4_to_ahb.scala 312:163] - wire _T_298 = _T_249 | _T_297; // @[axi4_to_ahb.scala 312:79] - wire _T_299 = trxn_done & _T_298; // @[axi4_to_ahb.scala 312:29] - wire _T_381 = _T_248 | _T_297; // @[axi4_to_ahb.scala 325:118] - wire _T_382 = _T_117 & _T_381; // @[axi4_to_ahb.scala 325:82] - wire _T_383 = ahb_hresp_q | _T_382; // @[axi4_to_ahb.scala 325:32] + wire _T_249 = buf_aligned | _T_248; // @[axi4_to_ahb.scala 291:44] + wire [7:0] _T_295 = buf_byteen >> _T_246; // @[axi4_to_ahb.scala 291:92] + wire _T_297 = ~_T_295[0]; // @[axi4_to_ahb.scala 291:163] + wire _T_298 = _T_249 | _T_297; // @[axi4_to_ahb.scala 291:79] + wire _T_299 = trxn_done & _T_298; // @[axi4_to_ahb.scala 291:29] + wire _T_381 = _T_248 | _T_297; // @[axi4_to_ahb.scala 304:118] + wire _T_382 = _T_117 & _T_381; // @[axi4_to_ahb.scala 304:82] + wire _T_383 = ahb_hresp_q | _T_382; // @[axi4_to_ahb.scala 304:32] wire _GEN_11 = _T_305 & _T_383; // @[Conditional.scala 39:67] wire _GEN_24 = _T_196 ? _T_299 : _GEN_11; // @[Conditional.scala 39:67] wire _GEN_43 = _T_194 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] @@ -363,17 +363,17 @@ module axi4_to_ahb( wire _GEN_74 = _T_144 ? _T_121 : _GEN_61; // @[Conditional.scala 39:67] wire _GEN_84 = _T_109 ? _T_121 : _GEN_74; // @[Conditional.scala 39:67] wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_300 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 313:43] - wire _T_301 = ~_T_300; // @[axi4_to_ahb.scala 313:32] + wire _T_300 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 292:43] + wire _T_301 = ~_T_300; // @[axi4_to_ahb.scala 292:32] wire [1:0] _T_303 = _T_301 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_304 = _T_303 & 2'h2; // @[axi4_to_ahb.scala 313:57] - wire _T_327 = _T_55 | _T_104; // @[axi4_to_ahb.scala 323:62] - wire _T_328 = buf_state_en & _T_327; // @[axi4_to_ahb.scala 323:33] - wire _T_389 = _T_301 | bypass_en; // @[axi4_to_ahb.scala 327:57] + wire [1:0] _T_304 = _T_303 & 2'h2; // @[axi4_to_ahb.scala 292:57] + wire _T_327 = _T_55 | _T_104; // @[axi4_to_ahb.scala 302:62] + wire _T_328 = buf_state_en & _T_327; // @[axi4_to_ahb.scala 302:33] + wire _T_389 = _T_301 | bypass_en; // @[axi4_to_ahb.scala 306:57] wire [1:0] _T_391 = _T_389 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_392 = _T_391 & 2'h2; // @[axi4_to_ahb.scala 327:71] - wire _T_399 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 330:40] - wire [2:0] _T_490 = bypass_en ? _T_101 : _T_247; // @[axi4_to_ahb.scala 333:30] + wire [1:0] _T_392 = _T_391 & 2'h2; // @[axi4_to_ahb.scala 306:71] + wire _T_399 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 309:40] + wire [2:0] _T_490 = bypass_en ? _T_101 : _T_247; // @[axi4_to_ahb.scala 310:30] wire _GEN_6 = _T_305 & ahb_hresp_q; // @[Conditional.scala 39:67] wire _GEN_7 = _T_305 ? buf_state_en : _T_491; // @[Conditional.scala 39:67] wire _GEN_9 = _T_305 & _T_328; // @[Conditional.scala 39:67] @@ -422,92 +422,92 @@ module axi4_to_ahb( wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_103 : _GEN_89; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_586 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 351:24] - wire _T_587 = _T_111 | _T_586; // @[axi4_to_ahb.scala 350:48] - wire _T_589 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 351:54] - wire _T_590 = _T_587 | _T_589; // @[axi4_to_ahb.scala 351:33] - wire _T_592 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 351:93] - wire _T_593 = _T_590 | _T_592; // @[axi4_to_ahb.scala 351:72] - wire _T_595 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 352:25] - wire _T_597 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 352:62] - wire _T_599 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 352:97] - wire _T_600 = _T_597 | _T_599; // @[axi4_to_ahb.scala 352:74] - wire _T_602 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 352:132] - wire _T_603 = _T_600 | _T_602; // @[axi4_to_ahb.scala 352:109] - wire _T_605 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 352:168] - wire _T_606 = _T_603 | _T_605; // @[axi4_to_ahb.scala 352:145] - wire _T_608 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 353:28] - wire _T_609 = _T_606 | _T_608; // @[axi4_to_ahb.scala 352:181] - wire _T_611 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 353:63] - wire _T_612 = _T_609 | _T_611; // @[axi4_to_ahb.scala 353:40] - wire _T_614 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 353:99] - wire _T_615 = _T_612 | _T_614; // @[axi4_to_ahb.scala 353:76] - wire _T_616 = _T_595 & _T_615; // @[axi4_to_ahb.scala 352:38] - wire buf_aligned_in = _T_593 | _T_616; // @[axi4_to_ahb.scala 351:106] - wire _T_495 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 345:60] + wire _T_586 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 328:24] + wire _T_587 = _T_111 | _T_586; // @[axi4_to_ahb.scala 327:48] + wire _T_589 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 328:54] + wire _T_590 = _T_587 | _T_589; // @[axi4_to_ahb.scala 328:33] + wire _T_592 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 328:93] + wire _T_593 = _T_590 | _T_592; // @[axi4_to_ahb.scala 328:72] + wire _T_595 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 329:25] + wire _T_597 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 329:62] + wire _T_599 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 329:97] + wire _T_600 = _T_597 | _T_599; // @[axi4_to_ahb.scala 329:74] + wire _T_602 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 329:132] + wire _T_603 = _T_600 | _T_602; // @[axi4_to_ahb.scala 329:109] + wire _T_605 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 329:168] + wire _T_606 = _T_603 | _T_605; // @[axi4_to_ahb.scala 329:145] + wire _T_608 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 330:28] + wire _T_609 = _T_606 | _T_608; // @[axi4_to_ahb.scala 329:181] + wire _T_611 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 330:63] + wire _T_612 = _T_609 | _T_611; // @[axi4_to_ahb.scala 330:40] + wire _T_614 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 330:99] + wire _T_615 = _T_612 | _T_614; // @[axi4_to_ahb.scala 330:76] + wire _T_616 = _T_595 & _T_615; // @[axi4_to_ahb.scala 329:38] + wire buf_aligned_in = _T_593 | _T_616; // @[axi4_to_ahb.scala 328:106] + wire _T_495 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 322:60] wire [2:0] _T_512 = _T_599 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_513 = 3'h2 & _T_512; // @[axi4_to_ahb.scala 175:15] - wire _T_519 = _T_611 | _T_597; // @[axi4_to_ahb.scala 176:56] + wire [2:0] _T_513 = 3'h2 & _T_512; // @[axi4_to_ahb.scala 167:15] + wire _T_519 = _T_611 | _T_597; // @[axi4_to_ahb.scala 168:56] wire [2:0] _T_521 = _T_519 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_522 = 3'h4 & _T_521; // @[axi4_to_ahb.scala 176:15] - wire [2:0] _T_523 = _T_513 | _T_522; // @[axi4_to_ahb.scala 175:63] + wire [2:0] _T_522 = 3'h4 & _T_521; // @[axi4_to_ahb.scala 168:15] + wire [2:0] _T_523 = _T_513 | _T_522; // @[axi4_to_ahb.scala 167:63] wire [2:0] _T_527 = _T_605 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_528 = 3'h6 & _T_527; // @[axi4_to_ahb.scala 177:17] - wire [2:0] _T_529 = _T_523 | _T_528; // @[axi4_to_ahb.scala 176:96] - wire [2:0] _T_536 = _T_495 ? _T_529 : master_addr[2:0]; // @[axi4_to_ahb.scala 345:43] - wire _T_540 = buf_state == 3'h3; // @[axi4_to_ahb.scala 348:33] - wire _T_546 = buf_aligned_in & _T_595; // @[axi4_to_ahb.scala 349:38] - wire _T_549 = _T_546 & _T_51; // @[axi4_to_ahb.scala 349:71] + wire [2:0] _T_528 = 3'h6 & _T_527; // @[axi4_to_ahb.scala 169:17] + wire [2:0] _T_529 = _T_523 | _T_528; // @[axi4_to_ahb.scala 168:96] + wire [2:0] _T_536 = _T_495 ? _T_529 : master_addr[2:0]; // @[axi4_to_ahb.scala 322:43] + wire _T_540 = buf_state == 3'h3; // @[axi4_to_ahb.scala 325:33] + wire _T_546 = buf_aligned_in & _T_595; // @[axi4_to_ahb.scala 326:38] + wire _T_549 = _T_546 & _T_51; // @[axi4_to_ahb.scala 326:71] wire [1:0] _T_555 = _T_614 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_561 = _T_611 | _T_608; // @[axi4_to_ahb.scala 168:55] + wire _T_561 = _T_611 | _T_608; // @[axi4_to_ahb.scala 161:55] wire [1:0] _T_563 = _T_561 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_564 = 2'h2 & _T_563; // @[axi4_to_ahb.scala 168:16] - wire [1:0] _T_565 = _T_555 | _T_564; // @[axi4_to_ahb.scala 167:64] - wire _T_570 = _T_605 | _T_602; // @[axi4_to_ahb.scala 169:60] - wire _T_573 = _T_570 | _T_599; // @[axi4_to_ahb.scala 169:89] - wire _T_576 = _T_573 | _T_597; // @[axi4_to_ahb.scala 169:123] + wire [1:0] _T_564 = 2'h2 & _T_563; // @[axi4_to_ahb.scala 161:16] + wire [1:0] _T_565 = _T_555 | _T_564; // @[axi4_to_ahb.scala 160:62] + wire _T_570 = _T_605 | _T_602; // @[axi4_to_ahb.scala 162:60] + wire _T_573 = _T_570 | _T_599; // @[axi4_to_ahb.scala 162:89] + wire _T_576 = _T_573 | _T_597; // @[axi4_to_ahb.scala 162:123] wire [1:0] _T_578 = _T_576 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_579 = 2'h1 & _T_578; // @[axi4_to_ahb.scala 169:21] - wire [1:0] _T_580 = _T_565 | _T_579; // @[axi4_to_ahb.scala 168:93] - wire [1:0] _T_582 = _T_549 ? _T_580 : master_size[1:0]; // @[axi4_to_ahb.scala 349:21] + wire [1:0] _T_579 = 2'h1 & _T_578; // @[axi4_to_ahb.scala 162:21] + wire [1:0] _T_580 = _T_565 | _T_579; // @[axi4_to_ahb.scala 161:93] + wire [1:0] _T_582 = _T_549 ? _T_580 : master_size[1:0]; // @[axi4_to_ahb.scala 326:21] wire [31:0] _T_621 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [31:0] _T_624 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [1:0] _T_628 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_582}; // @[axi4_to_ahb.scala 349:15] - wire [1:0] _T_630 = _T_628 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 356:77] + wire [2:0] buf_size_in = {{1'd0}, _T_582}; // @[axi4_to_ahb.scala 326:15] + wire [1:0] _T_630 = _T_628 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 333:77] wire [2:0] _T_631 = {1'h0,_T_630}; // @[Cat.scala 29:58] wire [1:0] _T_633 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_635 = _T_633 & buf_size; // @[axi4_to_ahb.scala 356:134] + wire [1:0] _T_635 = _T_633 & buf_size; // @[axi4_to_ahb.scala 333:134] wire [2:0] _T_636 = {1'h0,_T_635}; // @[Cat.scala 29:58] - wire _T_639 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 360:33] + wire _T_639 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 337:33] wire [1:0] _T_640 = {1'h1,_T_639}; // @[Cat.scala 29:58] reg buf_write; // @[Reg.scala 27:20] - wire _T_662 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 369:40] - wire _T_663 = _T_662 & io_ahb_hready; // @[axi4_to_ahb.scala 369:52] - wire last_addr_en = _T_663 & io_ahb_hwrite; // @[axi4_to_ahb.scala 369:68] - wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 371:47] - wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 372:50] - wire wrbuf_cmd_sent = _T_157 & _T_51; // @[axi4_to_ahb.scala 373:49] - wire _T_673 = ~wrbuf_en; // @[axi4_to_ahb.scala 374:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_673; // @[axi4_to_ahb.scala 374:31] - wire _T_675 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 376:35] - wire _T_676 = wrbuf_vld & _T_675; // @[axi4_to_ahb.scala 376:33] - wire _T_677 = ~_T_676; // @[axi4_to_ahb.scala 376:21] - wire _T_680 = wrbuf_data_vld & _T_675; // @[axi4_to_ahb.scala 377:37] - wire _T_681 = ~_T_680; // @[axi4_to_ahb.scala 377:20] - wire _T_684 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 378:21] - wire _T_687 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 382:52] - wire _T_688 = ~wrbuf_rst; // @[axi4_to_ahb.scala 382:88] - wire _T_692 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 383:52] + wire _T_662 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 346:40] + wire _T_663 = _T_662 & io_ahb_hready; // @[axi4_to_ahb.scala 346:52] + wire last_addr_en = _T_663 & io_ahb_hwrite; // @[axi4_to_ahb.scala 346:68] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 348:47] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 349:50] + wire wrbuf_cmd_sent = _T_157 & _T_51; // @[axi4_to_ahb.scala 350:49] + wire _T_673 = ~wrbuf_en; // @[axi4_to_ahb.scala 351:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_673; // @[axi4_to_ahb.scala 351:31] + wire _T_675 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 353:35] + wire _T_676 = wrbuf_vld & _T_675; // @[axi4_to_ahb.scala 353:33] + wire _T_677 = ~_T_676; // @[axi4_to_ahb.scala 353:21] + wire _T_680 = wrbuf_data_vld & _T_675; // @[axi4_to_ahb.scala 354:37] + wire _T_681 = ~_T_680; // @[axi4_to_ahb.scala 354:20] + wire _T_684 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 355:21] + wire _T_687 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 358:55] + wire _T_688 = ~wrbuf_rst; // @[axi4_to_ahb.scala 358:91] + wire _T_692 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 359:55] reg buf_tag; // @[Reg.scala 27:20] - wire _T_742 = ~slave_valid_pre; // @[axi4_to_ahb.scala 434:52] - wire _T_755 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 458:43] - wire _T_756 = _T_755 | io_clk_override; // @[axi4_to_ahb.scala 458:58] - wire _T_759 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 459:54] - wire _T_760 = _T_759 | io_clk_override; // @[axi4_to_ahb.scala 459:74] - wire _T_762 = buf_state != 3'h0; // @[axi4_to_ahb.scala 460:50] - wire _T_763 = _T_762 | io_clk_override; // @[axi4_to_ahb.scala 460:60] + wire _T_742 = ~slave_valid_pre; // @[axi4_to_ahb.scala 376:92] + wire _T_755 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 384:43] + wire _T_756 = _T_755 | io_clk_override; // @[axi4_to_ahb.scala 384:58] + wire _T_759 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 385:54] + wire _T_760 = _T_759 | io_clk_override; // @[axi4_to_ahb.scala 385:74] + wire _T_762 = buf_state != 3'h0; // @[axi4_to_ahb.scala 386:50] + wire _T_763 = _T_762 | io_clk_override; // @[axi4_to_ahb.scala 386:60] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -568,25 +568,25 @@ module axi4_to_ahb( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - assign io_axi_awready = _T_677 & master_ready; // @[axi4_to_ahb.scala 376:18] - assign io_axi_wready = _T_681 & master_ready; // @[axi4_to_ahb.scala 377:17] - assign io_axi_bvalid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 208:17] - assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 209:16] - assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 210:14] - assign io_axi_arready = _T_684 & master_ready; // @[axi4_to_ahb.scala 378:18] - assign io_axi_rvalid = _T_25 & _T_35; // @[axi4_to_ahb.scala 212:17] - assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 214:14] - assign io_axi_rdata = slvbuf_error ? _T_654 : _T_658; // @[axi4_to_ahb.scala 215:16] - assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 213:16] - assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 379:16] - assign io_ahb_haddr = bypass_en ? _T_621 : _T_624; // @[axi4_to_ahb.scala 355:16] - assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 358:17] - assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 359:20] - assign io_ahb_hprot = {{2'd0}, _T_640}; // @[axi4_to_ahb.scala 360:16] - assign io_ahb_hsize = bypass_en ? _T_631 : _T_636; // @[axi4_to_ahb.scala 356:16] - assign io_ahb_htrans = _T_49 ? _T_108 : _GEN_90; // @[axi4_to_ahb.scala 225:17 axi4_to_ahb.scala 256:21 axi4_to_ahb.scala 268:21 axi4_to_ahb.scala 283:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 313:21 axi4_to_ahb.scala 327:21] - assign io_ahb_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 361:17] - assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 362:17] + assign io_axi_awready = _T_677 & master_ready; // @[axi4_to_ahb.scala 353:18] + assign io_axi_wready = _T_681 & master_ready; // @[axi4_to_ahb.scala 354:17] + assign io_axi_bvalid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 187:17] + assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 188:16] + assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 189:14] + assign io_axi_arready = _T_684 & master_ready; // @[axi4_to_ahb.scala 355:18] + assign io_axi_rvalid = _T_25 & _T_35; // @[axi4_to_ahb.scala 191:17] + assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 193:14] + assign io_axi_rdata = slvbuf_error ? _T_654 : _T_658; // @[axi4_to_ahb.scala 194:16] + assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 192:16] + assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 356:16] + assign io_ahb_haddr = bypass_en ? _T_621 : _T_624; // @[axi4_to_ahb.scala 332:16] + assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 335:17] + assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 336:20] + assign io_ahb_hprot = {{2'd0}, _T_640}; // @[axi4_to_ahb.scala 337:16] + assign io_ahb_hsize = bypass_en ? _T_631 : _T_636; // @[axi4_to_ahb.scala 333:16] + assign io_ahb_htrans = _T_49 ? _T_108 : _GEN_90; // @[axi4_to_ahb.scala 204:17 axi4_to_ahb.scala 235:21 axi4_to_ahb.scala 247:21 axi4_to_ahb.scala 262:21 axi4_to_ahb.scala 272:21 axi4_to_ahb.scala 292:21 axi4_to_ahb.scala 306:21] + assign io_ahb_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 338:17] + assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 339:17] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala index aa6c4eb4..040587aa 100644 --- a/src/main/scala/lib/ahb_to_axi4.scala +++ b/src/main/scala/lib/ahb_to_axi4.scala @@ -98,19 +98,9 @@ class ahb_to_axi4 extends Module with el2_lib with RequireAsyncReset { val bus_clk = Wire(Clock()) // Address check dccm - val (ahb_addr_in_dccm_region_nc,ahb_addr_in_dccm) = rvrangecheck(DCCM_SADR,DCCM_SIZE,ahb_haddr_q) + val (ahb_addr_in_dccm_region_nc,ahb_addr_in_dccm) = rvrangecheck(DCCM_SADR,DCCM_SIZE,ahb_haddr_q) val (ahb_addr_in_iccm_region_nc,ahb_addr_in_iccm) = if(ICCM_ENABLE) rvrangecheck(ICCM_SADR ,ICCM_SIZE,ahb_haddr_q) else (0.U,0.U) - // Address check iccm -// if (ICCM_ENABLE == 1) { -// ahb_addr_in_iccm := rvrangecheck(ahb_haddr_q.asUInt, aslong(ICCM_SADR).asUInt(), ICCM_SIZE)._1 -// ahb_addr_in_iccm_region_nc := rvrangecheck(ahb_haddr_q.asUInt, aslong(ICCM_SADR).asUInt(), ICCM_SIZE)._2 -// } -// else { -// ahb_addr_in_iccm := 0.U -// ahb_addr_in_iccm_region_nc := 0.U -// -// } -val (ahb_addr_in_pic_region_nc, ahb_addr_in_pic) = rvrangecheck(PIC_BASE_ADDR,PIC_SIZE,ahb_haddr_q) + val (ahb_addr_in_pic_region_nc, ahb_addr_in_pic) = rvrangecheck(PIC_BASE_ADDR,PIC_SIZE,ahb_haddr_q) // PIC memory address check // FSM to control the bus states and when to block the hready and load the command buffer val buf_state = WireInit(idle) diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 03ac9751..b0c5124e 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -172,8 +172,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config } def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = { val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr) - val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)).orR -> j.U) - MuxCase(0.U, temp) + MuxCase(0.U,(0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)).orR -> j.U) ) } wr_cmd_vld := wrbuf_vld & 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