From 5474c212a2408a3f52a4dc1a28149e726b1c403b Mon Sep 17 00:00:00 2001 From: Junaid Ahmed <67728633+junaidahmed-lm@users.noreply.github.com> Date: Tue, 22 Sep 2020 12:59:01 +0500 Subject: [PATCH 1/3] Update el2_lsu_addrcheck.scala --- src/main/scala/lsu/el2_lsu_addrcheck.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/lsu/el2_lsu_addrcheck.scala b/src/main/scala/lsu/el2_lsu_addrcheck.scala index 86a71eed..f0245865 100644 --- a/src/main/scala/lsu/el2_lsu_addrcheck.scala +++ b/src/main/scala/lsu/el2_lsu_addrcheck.scala @@ -14,7 +14,7 @@ import chisel3.tester._ import chisel3.tester.RawTester.test import chisel3.util.HasBlackBoxResource -class el2_lsu_addrcheck extends Module +class el2_lsu_addrcheck extends Module with RequireAsyncReset {val io = IO(new Bundle{ val lsu_c2_m_clk = Input(Clock()) val start_addr_d = Input(UInt(32.W)) @@ -148,12 +148,12 @@ class el2_lsu_addrcheck extends Module io.exc_mscause_d := Mux(io.misaligned_fault_d.asBool, misaligned_fault_mscause_d(3,0), access_fault_mscause_d(3,0)) io.fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)|(end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int io.fir_nondccm_access_error_d := ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int - withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d)} //TBD for clock and reset + + withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d,0.U)} //TBD for clock and reset } //println(chisel3.Driver.emitVerilog(new el2_lsu_addrcheck)) -/* + object main extends App{ println("Generate Verilog") chisel3.Driver.execute(args, ()=> new el2_lsu_addrcheck) } -*/ From ccdab1e35c89c51adb8922a4d7d857dfff3c6be1 Mon Sep 17 00:00:00 2001 From: Junaid Ahmed <67728633+junaidahmed-lm@users.noreply.github.com> Date: Tue, 22 Sep 2020 14:39:44 +0500 Subject: [PATCH 2/3] Update el2_bundle.scala --- src/main/scala/include/el2_bundle.scala | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/main/scala/include/el2_bundle.scala b/src/main/scala/include/el2_bundle.scala index af0264da..e453abd1 100644 --- a/src/main/scala/include/el2_bundle.scala +++ b/src/main/scala/include/el2_bundle.scala @@ -55,7 +55,7 @@ class el2_br_pkt_t extends Bundle { val br_error = UInt(1.W) val br_start_error = UInt(1.W) val bank = UInt(1.W) - val prett = UInt(32.W) // predicted ret target + val prett = UInt(32.W) // predicted ret target //[31:1] in swerv val way = UInt(1.W) val ret = UInt(1.W) } @@ -80,7 +80,7 @@ class el2_predict_pkt_t extends Bundle { val valid = UInt(1.W) val br_error = UInt(1.W) val br_start_error = UInt(1.W) - val prett = UInt(32.W) + val prett = UInt(32.W) //[31:1] in swerv val pcall = UInt(1.W) val pret = UInt(1.W) val pja = UInt(1.W) @@ -102,7 +102,7 @@ class el2_trap_pkt_t extends Bundle { } class el2_dest_pkt_t extends Bundle { - val i0rd = UInt(4.W) + val i0rd = UInt(5.W) val i0load = UInt(1.W) val i0store = UInt(1.W) val i0div = UInt(1.W) @@ -169,8 +169,8 @@ class el2_lsu_error_pkt_t extends Bundle { val single_ecc_error = UInt(1.W) val inst_type = UInt(1.W) //0: Load, 1: Store val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault - val mscause = UInt(1.W) - val addr = UInt(1.W) + val mscause = UInt(4.W) + val addr = UInt(32.W) } class el2_dec_pkt_t extends Bundle { @@ -322,4 +322,3 @@ class el2_cache_debug_pkt_t extends Bundle { val icache_wr_valid = UInt(1.W) } - From 33a6ca89b3bc450eb89355b52de0fc452c92e45b Mon Sep 17 00:00:00 2001 From: Junaid Ahmed <67728633+junaidahmed-lm@users.noreply.github.com> Date: Tue, 22 Sep 2020 16:15:11 +0500 Subject: [PATCH 3/3] Update beh_ib_func.scala --- src/main/scala/lib/beh_ib_func.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/lib/beh_ib_func.scala b/src/main/scala/lib/beh_ib_func.scala index 32bc5e06..76dfcbc1 100644 --- a/src/main/scala/lib/beh_ib_func.scala +++ b/src/main/scala/lib/beh_ib_func.scala @@ -6,8 +6,9 @@ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource import chisel3.withClock -object beh_ib_func { - +object beh_ib_func { + // use this for rvdffsc = > io.out := RegEnable(io.din & repl(io.din.getWidth, io.clear), 0.U, io.en) + // use this for rvdffs = > io.out := RegEnable(io.din, 0.U, io.en) def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_)) def rvsyncss(din:UInt) = RegNext(RegNext(din,0.U),0.U)