From 08c9a49f4ec354aebeb70b3ac5dccc2481077f2a Mon Sep 17 00:00:00 2001 From: laraibkhan-lm <73219142+laraibkhan-lm@users.noreply.github.com> Date: Fri, 8 Jan 2021 11:10:56 +0500 Subject: [PATCH] Update lsu_lsc_ctl.scala --- design/src/main/scala/lsu/lsu_lsc_ctl.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/design/src/main/scala/lsu/lsu_lsc_ctl.scala b/design/src/main/scala/lsu/lsu_lsc_ctl.scala index 28d0dc78..b1f8cf5e 100644 --- a/design/src/main/scala/lsu/lsu_lsc_ctl.scala +++ b/design/src/main/scala/lsu/lsu_lsc_ctl.scala @@ -73,7 +73,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val addr_in_pic_m = Output(UInt(1.W)) val addr_in_pic_r = Output(UInt(1.W)) - val addr_external_m = Output(UInt(1.W)) + val addr_external_m = Output(Bool()) // DMA slave val dma_lsc_ctl = new dma_lsc_ctl() @@ -91,6 +91,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib val lsu_pkt_m_in = Wire(Valid(new lsu_pkt_t())) val lsu_pkt_r_in = Wire(Valid(new lsu_pkt_t())) val lsu_error_pkt_m = Wire(Valid(new lsu_error_pkt_t())) + lsu_error_pkt_m := 0.U.asTypeOf(lsu_error_pkt_m) val lsu_rs1_d = Mux(io.dec_lsu_valid_raw_d.asBool,io.lsu_exu.exu_lsu_rs1_d,io.dma_lsc_ctl.dma_mem_addr) val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d)