From 0a6000b99de7a666be65a11c84491bca17c7a4ff Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Thu, 10 Dec 2020 11:23:17 +0500 Subject: [PATCH] Only 1 obj --- dmi_wrapper.sv | 90 ++++ mem.sv | 16 +- src/main/resources/vsrc/beh_lib.sv | 506 ++++++++++++++++++ .../resources/vsrc/dmi_jtag_to_core_sync.sv | 64 +++ src/main/resources/vsrc/dmi_wrapper.sv | 90 ++++ src/main/resources/vsrc/gated_latch.sv | 14 + src/main/resources/vsrc/ifu_ic_mem.sv | 10 +- src/main/resources/vsrc/lsu_dccm_mem.sv | 2 +- src/main/resources/vsrc/mem.sv | 16 +- src/main/resources/vsrc/mem_lib.sv | 202 +++++++ src/main/resources/vsrc/mem_mod.sv | 64 +++ src/main/resources/vsrc/rvjtag_tap.sv | 223 ++++++++ src/main/scala/lib/axi4_to_ahb.scala | 5 - target/scala-2.12/classes/vsrc/beh_lib.sv | 506 ++++++++++++++++++ .../classes/vsrc/dmi_jtag_to_core_sync.sv | 64 +++ target/scala-2.12/classes/vsrc/dmi_wrapper.sv | 90 ++++ target/scala-2.12/classes/vsrc/gated_latch.sv | 14 + target/scala-2.12/classes/vsrc/ifu_ic_mem.sv | 10 +- .../scala-2.12/classes/vsrc/lsu_dccm_mem.sv | 2 +- target/scala-2.12/classes/vsrc/mem.sv | 16 +- target/scala-2.12/classes/vsrc/mem_lib.sv | 202 +++++++ target/scala-2.12/classes/vsrc/mem_mod.sv | 64 +++ target/scala-2.12/classes/vsrc/rvjtag_tap.sv | 223 ++++++++ 23 files changed, 2458 insertions(+), 35 deletions(-) create mode 100644 src/main/resources/vsrc/beh_lib.sv create mode 100644 src/main/resources/vsrc/gated_latch.sv create mode 100644 src/main/resources/vsrc/mem_lib.sv create mode 100644 src/main/resources/vsrc/mem_mod.sv create mode 100644 src/main/resources/vsrc/rvjtag_tap.sv create mode 100644 target/scala-2.12/classes/vsrc/beh_lib.sv create mode 100644 target/scala-2.12/classes/vsrc/gated_latch.sv create mode 100644 target/scala-2.12/classes/vsrc/mem_lib.sv create mode 100644 target/scala-2.12/classes/vsrc/mem_mod.sv create mode 100644 target/scala-2.12/classes/vsrc/rvjtag_tap.sv diff --git a/dmi_wrapper.sv b/dmi_wrapper.sv index e69de29b..d9fd7410 100644 --- a/dmi_wrapper.sv +++ b/dmi_wrapper.sv @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2018 +// Owner : Anusha Narayanamoorthy +// Description: +// Wrapper module for JTAG_TAP and DMI synchronizer +// +//------------------------------------------------------------------------------------- + +module dmi_wrapper( + + // JTAG signals + input trst_n, // JTAG reset + input tck, // JTAG clock + input tms, // Test mode select + input tdi, // Test Data Input + output tdo, // Test Data Output + output tdoEnable, // Test Data Output enable + + // Processor Signals + input core_rst_n, // Core reset + input core_clk, // Core clock + input [31:1] jtag_id, // JTAG ID + input [31:0] rd_data, // 32 bit Read data from Processor + output [31:0] reg_wr_data, // 32 bit Write data to Processor + output [6:0] reg_wr_addr, // 7 bit reg address to Processor + output reg_en, // 1 bit Read enable to Processor + output reg_wr_en, // 1 bit Write enable to Processor + output dmi_hard_reset +); + + + + + + //Wire Declaration + wire rd_en; + wire wr_en; + wire dmireset; + + + //jtag_tap instantiation + rvjtag_tap i_jtag_tap( + .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset + .tck(tck), // dedicated JTAG TCK pad signal + .tms(tms), // dedicated JTAG TMS pad signal + .tdi(tdi), // dedicated JTAG TDI pad signal + .tdo(tdo), // dedicated JTAG TDO pad signal + .tdoEnable(tdoEnable), // enable for TDO pad + .wr_data(reg_wr_data), // 32 bit Write data + .wr_addr(reg_wr_addr), // 7 bit Write address + .rd_en(rd_en), // 1 bit read enable + .wr_en(wr_en), // 1 bit Write enable + .rd_data(rd_data), // 32 bit Read data + .rd_status(2'b0), + .idle(3'h0), // no need to wait to sample data + .dmi_stat(2'b0), // no need to wait or error possible + .version(4'h1), // debug spec 0.13 compliant + .jtag_id(jtag_id), + .dmi_hard_reset(dmi_hard_reset), + .dmi_reset(dmireset) +); + + + // dmi_jtag_to_core_sync instantiation + dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync( + .wr_en(wr_en), // 1 bit Write enable + .rd_en(rd_en), // 1 bit Read enable + + .rst_n(core_rst_n), + .clk(core_clk), + .reg_en(reg_en), // 1 bit Write interface bit + .reg_wr_en(reg_wr_en) // 1 bit Write enable + ); + +endmodule diff --git a/mem.sv b/mem.sv index 56e9fe57..0aee1897 100644 --- a/mem.sv +++ b/mem.sv @@ -15,14 +15,14 @@ module mem #( parameter DCCM_NUM_BANKS, parameter ICACHE_BANK_HI, parameter ICACHE_BANK_LO, - parameter DCCM_ENABLE, + parameter DCCM_ENABLE= 'b1, parameter ICACHE_TAG_LO, parameter ICACHE_DATA_INDEX_LO, parameter ICCM_NUM_BANKS, parameter ICACHE_ECC, - parameter ICACHE_ENABLE, + parameter ICACHE_ENABLE= 'b1, parameter DCCM_BANK_BITS, - parameter ICCM_ENABLE, + parameter ICCM_ENABLE= 'b1, parameter ICCM_BANK_BITS, parameter ICACHE_TAG_DEPTH, parameter ICACHE_WAYPACK, @@ -77,8 +77,9 @@ module mem #( input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic ic_sel_premux_data, // Premux data sel - input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC - input logic [70:0] ic_debug_wr_data, // Debug wr cache. + input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC + input logic [70:0] ic_wr_data_1, + input logic [70:0] ic_debug_wr_data, // Debug wr cache. output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. input logic ic_debug_rd_en, // Icache debug rd @@ -100,6 +101,9 @@ module mem #( ); + logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data; +assign ic_wr_data [0] = ic_wr_data_0; +assign ic_wr_data [1] = ic_wr_data_1; // DCCM Instantiation if (DCCM_ENABLE == 1) begin: Gen_dccm_enable lsu_dccm_mem #( @@ -142,7 +146,7 @@ else begin assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0; assign ic_tag_perr = '0 ; assign ic_rd_data = '0 ; - assign ic_stag_debug_rd_data = '0 ; + assign ic_tag_debug_rd_data = '0 ; end // else: !if( ICACHE_ENABLE ) diff --git a/src/main/resources/vsrc/beh_lib.sv b/src/main/resources/vsrc/beh_lib.sv new file mode 100644 index 00000000..ea8f8dea --- /dev/null +++ b/src/main/resources/vsrc/beh_lib.sv @@ -0,0 +1,506 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// all flops call the rvdff flop + + +module rvdff #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic clk, + input logic rst_l, + + output logic [WIDTH-1:0] dout + ); + +if (SHORT == 1) begin + assign dout = din; +end +else begin +`ifdef CLOCKGATE + always @(posedge tb_top.clk) begin + #0 $strobe("CG: %0t %m din %x dout %x clk %b width %d",$time,din,dout,clk,WIDTH); + end +`endif + + always_ff @(posedge clk or negedge rst_l) begin + if (rst_l == 0) + dout[WIDTH-1:0] <= 0; + else + dout[WIDTH-1:0] <= din[WIDTH-1:0]; + end + +end +endmodule + +// rvdff with 2:1 input mux to flop din iff sel==1 +module rvdffs #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic en, + input logic clk, + input logic rst_l, + output logic [WIDTH-1:0] dout + ); + +if (SHORT == 1) begin : genblock + assign dout = din; +end +else begin : genblock + rvdff #(WIDTH) dffs (.din((en) ? din[WIDTH-1:0] : dout[WIDTH-1:0]), .*); +end + +endmodule + +// rvdff with en and clear +module rvdffsc #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic en, + input logic clear, + input logic clk, + input logic rst_l, + output logic [WIDTH-1:0] dout + ); + + logic [WIDTH-1:0] din_new; +if (SHORT == 1) begin + assign dout = din; +end +else begin + assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]); + rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*); +end +endmodule + +module rvdffe #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic en, + input logic clk, + input logic rst_l, + input logic scan_mode, + output logic [WIDTH-1:0] dout + ); + + logic l1clk; + +if (SHORT == 1) begin : genblock + if (1) begin : genblock + assign dout = din; + end +end +else begin : genblock + +`ifndef PHYSICAL + if (WIDTH >= 8) begin: genblock +`endif + +`ifdef RV_FPGA_OPTIMIZE + rvdffs #(WIDTH) dff ( .* ); +`else + rvclkhdr clkhdr ( .* ); + rvdff #(WIDTH) dff (.*, .clk(l1clk)); +`endif + +`ifndef PHYSICAL + end + else + $error(" rvdffe width must be >= 8"); +`endif +end // else: !if(SHORT == 1) + +endmodule // rvdffe + +module rvsyncss #(parameter WIDTH = 251) + ( + input logic clk, + input logic rst_l, + input logic [WIDTH-1:0] din, + output logic [WIDTH-1:0] dout + ); + + logic [WIDTH-1:0] din_ff1; + + rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0])); + rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0])); + +endmodule // rvsyncss + +module rvlsadder + ( + input logic [31:0] rs1, + input logic [11:0] offset, + + output logic [31:0] dout + ); + + logic cout; + logic sign; + + logic [31:12] rs1_inc; + logic [31:12] rs1_dec; + + assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]}; + + assign rs1_inc[31:12] = rs1[31:12] + 1; + + assign rs1_dec[31:12] = rs1[31:12] - 1; + + assign sign = offset[11]; + + assign dout[31:12] = ({20{ sign ^~ cout}} & rs1[31:12]) | + ({20{ ~sign & cout}} & rs1_inc[31:12]) | + ({20{ sign & ~cout}} & rs1_dec[31:12]); + +endmodule // rvlsadder + +// assume we only maintain pc[31:1] in the pipe + +module rvbradder + ( + input [31:1] pc, + input [12:1] offset, + + output [31:1] dout + ); + + logic cout; + logic sign; + + logic [31:13] pc_inc; + logic [31:13] pc_dec; + + assign {cout,dout[12:1]} = {1'b0,pc[12:1]} + {1'b0,offset[12:1]}; + + assign pc_inc[31:13] = pc[31:13] + 1; + + assign pc_dec[31:13] = pc[31:13] - 1; + + assign sign = offset[12]; + + + assign dout[31:13] = ({19{ sign ^~ cout}} & pc[31:13]) | + ({19{ ~sign & cout}} & pc_inc[31:13]) | + ({19{ sign & ~cout}} & pc_dec[31:13]); + + +endmodule // rvbradder + + +// 2s complement circuit +module rvtwoscomp #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] din, + + output logic [WIDTH-1:0] dout + ); + + logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din + + genvar i; + + for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one + assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i]; + end : flip_after_first_one + + assign dout[WIDTH-1:0] = { dout_temp[WIDTH-1:1], din[0] }; + +endmodule // 2'scomp + +// find first +module rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) ) + ( + input logic [WIDTH-1:0] din, + + output logic [SHIFT-1:0] dout + ); + logic done; + + always_comb begin + dout[SHIFT-1:0] = {SHIFT{1'b0}}; + done = 1'b0; + + for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one + done |= din[i]; + dout[SHIFT-1:0] += done ? 1'b0 : 1'b1; + end : find_first_one + end +endmodule // rvfindfirst1 + +module rvfindfirst1hot #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] din, + + output logic [WIDTH-1:0] dout + ); + logic done; + + always_comb begin + dout[WIDTH-1:0] = {WIDTH{1'b0}}; + done = 1'b0; + for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one + dout[i] = ~done & din[i]; + done |= din[i]; + end : find_first_one + end +endmodule // rvfindfirst1hot + +// mask and match function matches bits after finding the first 0 position +// find first starting from LSB. Skip that location and match the rest of the bits +module rvmaskandmatch #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] mask, // this will have the mask in the lower bit positions + input logic [WIDTH-1:0] data, // this is what needs to be matched on the upper bits with the mask's upper bits + input logic masken, // when 1 : do mask. 0 : full match + output logic match + ); + + logic [WIDTH-1:0] matchvec; + logic masken_or_fullmask; + + assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]); + + assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]); + genvar i; + + for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero + assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]); + end : match_after_first_zero + + assign match = &matchvec[WIDTH-1:0]; // all bits either matched or were masked off + +endmodule // rvmaskandmatch + + + + +// Check if the S_ADDR <= addr < E_ADDR +module rvrangecheck #(CCM_SADR = 32'h0, + CCM_SIZE = 128) ( + input logic [31:0] addr, // Address to be checked for range + output logic in_range, // S_ADDR <= start_addr < E_ADDR + output logic in_region +); + + localparam REGION_BITS = 4; + localparam MASK_BITS = 10 + $clog2(CCM_SIZE); + + logic [31:0] start_addr; + logic [3:0] region; + + assign start_addr[31:0] = CCM_SADR; + assign region[REGION_BITS-1:0] = start_addr[31:(32-REGION_BITS)]; + + assign in_region = (addr[31:(32-REGION_BITS)] == region[REGION_BITS-1:0]); + if (CCM_SIZE == 48) + assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS-1 : MASK_BITS-2]); + else + assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]); + +endmodule // rvrangechecker + +// 16 bit even parity generator +module rveven_paritygen #(WIDTH = 16) ( + input logic [WIDTH-1:0] data_in, // Data + output logic parity_out // generated even parity + ); + + assign parity_out = ^(data_in[WIDTH-1:0]) ; + +endmodule // rveven_paritygen + +module rveven_paritycheck #(WIDTH = 16) ( + input logic [WIDTH-1:0] data_in, // Data + input logic parity_in, + output logic parity_err // Parity error + ); + + assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ; + +endmodule // rveven_paritycheck + +module rvecc_encode ( + input [31:0] din, + output [6:0] ecc_out + ); +logic [5:0] ecc_out_temp; + + assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; + assign ecc_out_temp[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]; + assign ecc_out_temp[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]; + assign ecc_out_temp[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_out_temp[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_out_temp[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]; + + assign ecc_out[6:0] = {(^din[31:0])^(^ecc_out_temp[5:0]),ecc_out_temp[5:0]}; + +endmodule // rvecc_encode + +module rvecc_decode ( + input en, + input [31:0] din, + input [6:0] ecc_in, + input sed_ded, // only do detection and no correction. Used for the I$ + output [31:0] dout, + output [6:0] ecc_out, + output single_ecc_error, + output double_ecc_error + + ); + + logic [6:0] ecc_check; + logic [38:0] error_mask; + logic [38:0] din_plus_parity, dout_plus_parity; + + // Generate the ecc bits + assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; + assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]; + assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]; + assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]; + + // This is the parity bit + assign ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0])) & ~sed_ded; + + assign single_ecc_error = en & (ecc_check[6:0] != 0) & ecc_check[6]; // this will never be on for sed_ded + assign double_ecc_error = en & (ecc_check[6:0] != 0) & ~ecc_check[6]; // all errors in the sed_ded case will be recorded as DE + + // Generate the mask for error correctiong + for (genvar i=1; i<40; i++) begin + assign error_mask[i-1] = (ecc_check[5:0] == i); + end + + // Generate the corrected data + assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]}; + + assign dout_plus_parity[38:0] = single_ecc_error ? (error_mask[38:0] ^ din_plus_parity[38:0]) : din_plus_parity[38:0]; + assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]}; + assign ecc_out[6:0] = {(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]}; + +endmodule // rvecc_decode + +module rvecc_encode_64 ( + input [63:0] din, + output [6:0] ecc_out + ); + assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63]; + + assign ecc_out[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63]; + + assign ecc_out[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_out[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[6] = din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63]; + +endmodule // rvecc_encode_64 + + +module rvecc_decode_64 ( + input en, + input [63:0] din, + input [6:0] ecc_in, + output ecc_error + ); + + logic [6:0] ecc_check; + + // Generate the ecc bits + assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63]; + + assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63]; + + assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[6] = ecc_in[6]^din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_error = en & (ecc_check[6:0] != 0); // all errors in the sed_ded case will be recorded as DE + + endmodule // rvecc_decode_64 + + +module gated_flop + ( + input logic SE, EN, CK, + output Q + ); + + logic en_ff; + logic enable; + + assign enable = EN | SE; + +`ifdef VERILATOR + always @(negedge CK) begin + en_ff <= enable; + end +`else + always @(CK, enable) begin + if(!CK) + en_ff = enable; + end +`endif + assign Q = CK & en_ff; + +endmodule + +module rvclkhdr + ( + input logic en, + input logic clk, + input logic scan_mode, + output logic l1clk + ); + + logic SE; + assign SE = scan_mode; + + gated_flop clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk)); + +endmodule // rvclkhdr + +module rvoclkhdr + ( + input logic en, + input logic clk, + input logic scan_mode, + output logic l1clk + ); + + logic SE; + assign SE = scan_mode; + +`ifdef RV_FPGA_OPTIMIZE + assign l1clk = clk; +`else + gated_flop clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk)); +`endif + +endmodule + + + diff --git a/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv b/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv index e69de29b..562f815e 100644 --- a/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv +++ b/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2019 +// Owner : Alex Grobman +// Description: +// This module Synchronizes the signals between JTAG (TCK) and +// processor (Core_clk) +// +//------------------------------------------------------------------------------------- + +module dmi_jtag_to_core_sync ( +// JTAG signals +input rd_en, // 1 bit Read Enable from JTAG +input wr_en, // 1 bit Write enable from JTAG + +// Processor Signals +input rst_n, // Core reset +input clk, // Core clock + +output reg_en, // 1 bit Write interface bit to Processor +output reg_wr_en // 1 bit Write enable to Processor +); + +wire c_rd_en; +wire c_wr_en; +reg [2:0] rden, wren; + + +// Outputs +assign reg_en = c_wr_en | c_rd_en; +assign reg_wr_en = c_wr_en; + + +// synchronizers +always @ ( posedge clk or negedge rst_n) begin + if(!rst_n) begin + rden <= '0; + wren <= '0; + end + else begin + rden <= {rden[1:0], rd_en}; + wren <= {wren[1:0], wr_en}; + end +end + +assign c_rd_en = rden[1] & ~rden[2]; +assign c_wr_en = wren[1] & ~wren[2]; + + +endmodule diff --git a/src/main/resources/vsrc/dmi_wrapper.sv b/src/main/resources/vsrc/dmi_wrapper.sv index e69de29b..d9fd7410 100644 --- a/src/main/resources/vsrc/dmi_wrapper.sv +++ b/src/main/resources/vsrc/dmi_wrapper.sv @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2018 +// Owner : Anusha Narayanamoorthy +// Description: +// Wrapper module for JTAG_TAP and DMI synchronizer +// +//------------------------------------------------------------------------------------- + +module dmi_wrapper( + + // JTAG signals + input trst_n, // JTAG reset + input tck, // JTAG clock + input tms, // Test mode select + input tdi, // Test Data Input + output tdo, // Test Data Output + output tdoEnable, // Test Data Output enable + + // Processor Signals + input core_rst_n, // Core reset + input core_clk, // Core clock + input [31:1] jtag_id, // JTAG ID + input [31:0] rd_data, // 32 bit Read data from Processor + output [31:0] reg_wr_data, // 32 bit Write data to Processor + output [6:0] reg_wr_addr, // 7 bit reg address to Processor + output reg_en, // 1 bit Read enable to Processor + output reg_wr_en, // 1 bit Write enable to Processor + output dmi_hard_reset +); + + + + + + //Wire Declaration + wire rd_en; + wire wr_en; + wire dmireset; + + + //jtag_tap instantiation + rvjtag_tap i_jtag_tap( + .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset + .tck(tck), // dedicated JTAG TCK pad signal + .tms(tms), // dedicated JTAG TMS pad signal + .tdi(tdi), // dedicated JTAG TDI pad signal + .tdo(tdo), // dedicated JTAG TDO pad signal + .tdoEnable(tdoEnable), // enable for TDO pad + .wr_data(reg_wr_data), // 32 bit Write data + .wr_addr(reg_wr_addr), // 7 bit Write address + .rd_en(rd_en), // 1 bit read enable + .wr_en(wr_en), // 1 bit Write enable + .rd_data(rd_data), // 32 bit Read data + .rd_status(2'b0), + .idle(3'h0), // no need to wait to sample data + .dmi_stat(2'b0), // no need to wait or error possible + .version(4'h1), // debug spec 0.13 compliant + .jtag_id(jtag_id), + .dmi_hard_reset(dmi_hard_reset), + .dmi_reset(dmireset) +); + + + // dmi_jtag_to_core_sync instantiation + dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync( + .wr_en(wr_en), // 1 bit Write enable + .rd_en(rd_en), // 1 bit Read enable + + .rst_n(core_rst_n), + .clk(core_clk), + .reg_en(reg_en), // 1 bit Write interface bit + .reg_wr_en(reg_wr_en) // 1 bit Write enable + ); + +endmodule diff --git a/src/main/resources/vsrc/gated_latch.sv b/src/main/resources/vsrc/gated_latch.sv new file mode 100644 index 00000000..51b96c9d --- /dev/null +++ b/src/main/resources/vsrc/gated_latch.sv @@ -0,0 +1,14 @@ +module gated_latch + ( + input logic SE, EN, CK, + output Q + ); + logic en_ff; + logic enable; + assign enable = EN | SE; + always @(CK, enable) begin + if(!CK) + en_ff = enable; + end + assign Q = CK & en_ff; +endmodule diff --git a/src/main/resources/vsrc/ifu_ic_mem.sv b/src/main/resources/vsrc/ifu_ic_mem.sv index 8f7a1f12..269925a6 100644 --- a/src/main/resources/vsrc/ifu_ic_mem.sv +++ b/src/main/resources/vsrc/ifu_ic_mem.sv @@ -23,7 +23,7 @@ module ifu_ic_mem parameter ICACHE_NUM_WAYS, parameter ICACHE_BANK_BITS, parameter ICACHE_BEAT_ADDR_HI, - parameter ICACHE_BANKS_WAY, + parameter ICACHE_BANKS_WAY=2, parameter ICACHE_INDEX_HI, parameter ICACHE_BANK_HI, parameter ICACHE_BANK_LO, @@ -67,7 +67,7 @@ module ifu_ic_mem ) ; - IC_TAG #( + EL2_IC_TAG #( .ICACHE_BEAT_BITS(ICACHE_BEAT_BITS), .ICACHE_NUM_WAYS(ICACHE_NUM_WAYS), .ICACHE_BANK_BITS(ICACHE_BANK_BITS), @@ -90,7 +90,7 @@ module ifu_ic_mem .ic_rw_addr (ic_rw_addr[31:3]) ) ; - IC_DATA #( + EL2_IC_DATA #( .ICACHE_BEAT_BITS(ICACHE_BEAT_BITS), .ICACHE_NUM_WAYS(ICACHE_NUM_WAYS), .ICACHE_BANK_BITS(ICACHE_BANK_BITS), @@ -119,7 +119,7 @@ module ifu_ic_mem ///////////////////////////////////////////////// ////// ICACHE DATA MODULE //////////////////// ///////////////////////////////////////////////// -module IC_DATA +module EL2_IC_DATA #( parameter ICACHE_BEAT_BITS, parameter ICACHE_NUM_WAYS, @@ -990,7 +990,7 @@ endmodule // EL2_IC_DATA ///////////////////////////////////////////////// ////// ICACHE TAG MODULE //////////////////// ///////////////////////////////////////////////// -module IC_TAG +module EL2_IC_TAG #( parameter ICACHE_BEAT_BITS, parameter ICACHE_NUM_WAYS, diff --git a/src/main/resources/vsrc/lsu_dccm_mem.sv b/src/main/resources/vsrc/lsu_dccm_mem.sv index 1608a603..85c81c49 100644 --- a/src/main/resources/vsrc/lsu_dccm_mem.sv +++ b/src/main/resources/vsrc/lsu_dccm_mem.sv @@ -27,7 +27,7 @@ // //******************************************************************************** -module el2_lsu_dccm_mem +module lsu_dccm_mem #( parameter DCCM_BYTE_WIDTH, parameter DCCM_BITS, diff --git a/src/main/resources/vsrc/mem.sv b/src/main/resources/vsrc/mem.sv index 56e9fe57..0aee1897 100644 --- a/src/main/resources/vsrc/mem.sv +++ b/src/main/resources/vsrc/mem.sv @@ -15,14 +15,14 @@ module mem #( parameter DCCM_NUM_BANKS, parameter ICACHE_BANK_HI, parameter ICACHE_BANK_LO, - parameter DCCM_ENABLE, + parameter DCCM_ENABLE= 'b1, parameter ICACHE_TAG_LO, parameter ICACHE_DATA_INDEX_LO, parameter ICCM_NUM_BANKS, parameter ICACHE_ECC, - parameter ICACHE_ENABLE, + parameter ICACHE_ENABLE= 'b1, parameter DCCM_BANK_BITS, - parameter ICCM_ENABLE, + parameter ICCM_ENABLE= 'b1, parameter ICCM_BANK_BITS, parameter ICACHE_TAG_DEPTH, parameter ICACHE_WAYPACK, @@ -77,8 +77,9 @@ module mem #( input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic ic_sel_premux_data, // Premux data sel - input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC - input logic [70:0] ic_debug_wr_data, // Debug wr cache. + input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC + input logic [70:0] ic_wr_data_1, + input logic [70:0] ic_debug_wr_data, // Debug wr cache. output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. input logic ic_debug_rd_en, // Icache debug rd @@ -100,6 +101,9 @@ module mem #( ); + logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data; +assign ic_wr_data [0] = ic_wr_data_0; +assign ic_wr_data [1] = ic_wr_data_1; // DCCM Instantiation if (DCCM_ENABLE == 1) begin: Gen_dccm_enable lsu_dccm_mem #( @@ -142,7 +146,7 @@ else begin assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0; assign ic_tag_perr = '0 ; assign ic_rd_data = '0 ; - assign ic_stag_debug_rd_data = '0 ; + assign ic_tag_debug_rd_data = '0 ; end // else: !if( ICACHE_ENABLE ) diff --git a/src/main/resources/vsrc/mem_lib.sv b/src/main/resources/vsrc/mem_lib.sv new file mode 100644 index 00000000..e741c618 --- /dev/null +++ b/src/main/resources/vsrc/mem_lib.sv @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`define EL2_LOCAL_RAM_TEST_IO \ +input logic WE, \ +input logic ME, \ +input logic CLK + +`define EL2_RAM(depth, width) \ +module ram_``depth``x``width( \ + input logic [$clog2(depth)-1:0] ADR, \ + input logic [(width-1):0] D, \ + output logic [(width-1):0] Q, \ + `EL2_LOCAL_RAM_TEST_IO \ +); \ +reg [(width-1):0] ram_core [(depth-1):0]; \ + \ +always @(posedge CLK) begin \ + if (ME && WE) ram_core[ADR] = D; \ + if (ME && ~WE) Q <= ram_core[ADR]; \ +end \ + \ +endmodule + +`define EL2_RAM_BE(depth, width) \ +module ram_be_``depth``x``width( \ + input logic [$clog2(depth)-1:0] ADR, \ + input logic [(width-1):0] D, WEM, \ + output logic [(width-1):0] Q, \ + `EL2_LOCAL_RAM_TEST_IO \ +); \ +reg [(width-1):0] ram_core [(depth-1):0]; \ + \ +always @(posedge CLK) begin \ + if (ME && WE) ram_core[ADR] = D & WEM | ~WEM & ram_core[ADR];\ + if (ME && ~WE) Q <= ram_core[ADR]; \ +end \ + \ + \ +endmodule + +// parameterizable RAM for verilator sims +module el2_ram #(depth=4096, width=39) ( +input logic [$clog2(depth)-1:0] ADR, +input logic [(width-1):0] D, +output logic [(width-1):0] Q, + `EL2_LOCAL_RAM_TEST_IO +); +reg [(width-1):0] ram_core [(depth-1):0]; + +always @(posedge CLK) begin + if (ME && WE) ram_core[ADR] = D; + if (ME && ~WE) Q <= ram_core[ADR]; +end +endmodule + +//========================================================================================================================= +//=================================== START OF CCM ======================================================================= +//============= Possible sram sizes for a 39 bit wide memory ( 4 bytes + 7 bits ECC ) ===================================== +//------------------------------------------------------------------------------------------------------------------------- +`EL2_RAM(32768, 39) +`EL2_RAM(16384, 39) +`EL2_RAM(8192, 39) +`EL2_RAM(4096, 39) +`EL2_RAM(3072, 39) +`EL2_RAM(2048, 39) +`EL2_RAM(1536, 39) // need this for the 48KB DCCM option) +`EL2_RAM(1024, 39) +`EL2_RAM(768, 39) +`EL2_RAM(512, 39) +`EL2_RAM(256, 39) +`EL2_RAM(128, 39) +`EL2_RAM(1024, 20) +`EL2_RAM(512, 20) +`EL2_RAM(256, 20) +`EL2_RAM(128, 20) +`EL2_RAM(64, 20) +`EL2_RAM(4096, 34) +`EL2_RAM(2048, 34) +`EL2_RAM(1024, 34) +`EL2_RAM(512, 34) +`EL2_RAM(256, 34) +`EL2_RAM(128, 34) +`EL2_RAM(64, 34) +`EL2_RAM(8192, 68) +`EL2_RAM(4096, 68) +`EL2_RAM(2048, 68) +`EL2_RAM(1024, 68) +`EL2_RAM(512, 68) +`EL2_RAM(256, 68) +`EL2_RAM(128, 68) +`EL2_RAM(64, 68) +`EL2_RAM(8192, 71) +`EL2_RAM(4096, 71) +`EL2_RAM(2048, 71) +`EL2_RAM(1024, 71) +`EL2_RAM(512, 71) +`EL2_RAM(256, 71) +`EL2_RAM(128, 71) +`EL2_RAM(64, 71) +`EL2_RAM(4096, 42) +`EL2_RAM(2048, 42) +`EL2_RAM(1024, 42) +`EL2_RAM(512, 42) +`EL2_RAM(256, 42) +`EL2_RAM(128, 42) +`EL2_RAM(64, 42) +`EL2_RAM(4096, 22) +`EL2_RAM(2048, 22) +`EL2_RAM(1024, 22) +`EL2_RAM(512, 22) +`EL2_RAM(256, 22) +`EL2_RAM(128, 22) +`EL2_RAM(64, 22) +`EL2_RAM(1024, 26) +`EL2_RAM(4096, 26) +`EL2_RAM(2048, 26) +`EL2_RAM(512, 26) +`EL2_RAM(256, 26) +`EL2_RAM(128, 26) +`EL2_RAM(64, 26) +`EL2_RAM(32, 26) +`EL2_RAM(32, 22) +`EL2_RAM_BE(8192, 142) +`EL2_RAM_BE(4096, 142) +`EL2_RAM_BE(2048, 142) +`EL2_RAM_BE(1024, 142) +`EL2_RAM_BE(512, 142) +`EL2_RAM_BE(256, 142) +`EL2_RAM_BE(128, 142) +`EL2_RAM_BE(64, 142) +`EL2_RAM_BE(8192, 284) +`EL2_RAM_BE(4096, 284) +`EL2_RAM_BE(2048, 284) +`EL2_RAM_BE(1024, 284) +`EL2_RAM_BE(512, 284) +`EL2_RAM_BE(256, 284) +`EL2_RAM_BE(128, 284) +`EL2_RAM_BE(64, 284) +`EL2_RAM_BE(8192, 136) +`EL2_RAM_BE(4096, 136) +`EL2_RAM_BE(2048, 136) +`EL2_RAM_BE(1024, 136) +`EL2_RAM_BE(512, 136) +`EL2_RAM_BE(256, 136) +`EL2_RAM_BE(128, 136) +`EL2_RAM_BE(64, 136) +`EL2_RAM_BE(8192, 272) +`EL2_RAM_BE(4096, 272) +`EL2_RAM_BE(2048, 272) +`EL2_RAM_BE(1024, 272) +`EL2_RAM_BE(512, 272) +`EL2_RAM_BE(256, 272) +`EL2_RAM_BE(128, 272) +`EL2_RAM_BE(64, 272) +`EL2_RAM_BE(4096, 52) +`EL2_RAM_BE(2048, 52) +`EL2_RAM_BE(1024, 52) +`EL2_RAM_BE(512, 52) +`EL2_RAM_BE(256, 52) +`EL2_RAM_BE(128, 52) +`EL2_RAM_BE(64, 52) +`EL2_RAM_BE(4096, 104) +`EL2_RAM_BE(2048, 104) +`EL2_RAM_BE(1024, 104) +`EL2_RAM_BE(512, 104) +`EL2_RAM_BE(256, 104) +`EL2_RAM_BE(128, 104) +`EL2_RAM_BE(64, 104) +`EL2_RAM_BE(4096, 44) +`EL2_RAM_BE(2048, 44) +`EL2_RAM_BE(1024, 44) +`EL2_RAM_BE(512, 44) +`EL2_RAM_BE(256, 44) +`EL2_RAM_BE(128, 44) +`EL2_RAM_BE(64, 44) +`EL2_RAM_BE(4096, 88) +`EL2_RAM_BE(2048, 88) +`EL2_RAM_BE(1024, 88) +`EL2_RAM_BE(512, 88) +`EL2_RAM_BE(256, 88) +`EL2_RAM_BE(128, 88) +`EL2_RAM_BE(64, 88) + + +`undef EL2_RAM +`undef EL2_RAM_BE +`undef EL2_LOCAL_RAM_TEST_IO + + diff --git a/src/main/resources/vsrc/mem_mod.sv b/src/main/resources/vsrc/mem_mod.sv new file mode 100644 index 00000000..6f71a3c1 --- /dev/null +++ b/src/main/resources/vsrc/mem_mod.sv @@ -0,0 +1,64 @@ +module el2_btb_tag_hash #( +`include "el2_param.vh" + ) ( + input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc, + output logic [pt.BTB_BTAG_SIZE-1:0] hash + ); + + assign hash = {(pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])}; +endmodule + +module el2_btb_tag_hash_fold #( +`include "el2_param.vh" + )( + input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc, + output logic [pt.BTB_BTAG_SIZE-1:0] hash + ); + + assign hash = {( + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])}; + +endmodule + +module el2_btb_addr_hash #( +`include "el2_param.vh" + )( + input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc, + output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash + ); + + +if(pt.BTB_FOLD2_INDEX_HASH) begin : fold2 + assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^ + pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO]; +end + else begin + assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^ + pc[pt.BTB_INDEX2_HI:pt.BTB_INDEX2_LO] ^ + pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO]; +end + +endmodule + +module el2_btb_ghr_hash #( +`include "el2_param.vh" + )( + input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin, + input logic [pt.BHT_GHR_SIZE-1:0] ghr, + output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash + ); + + // The hash function is too complex to write in verilog for all cases. + // The config script generates the logic string based on the bp config. + if(pt.BHT_GHR_HASH_1) begin : ghrhash_cfg1 + assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { ghr[pt.BHT_GHR_SIZE-1:pt.BTB_INDEX1_HI-1], hashin[pt.BTB_INDEX1_HI:2]^ghr[pt.BTB_INDEX1_HI-2:0]}; + end + else begin : ghrhash_cfg2 + assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { hashin[pt.BHT_GHR_SIZE+1:2]^ghr[pt.BHT_GHR_SIZE-1:0]}; + end + + +endmodule diff --git a/src/main/resources/vsrc/rvjtag_tap.sv b/src/main/resources/vsrc/rvjtag_tap.sv new file mode 100644 index 00000000..24634344 --- /dev/null +++ b/src/main/resources/vsrc/rvjtag_tap.sv @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License + +module rvjtag_tap #( +parameter AWIDTH = 7 +) +( +input trst, +input tck, +input tms, +input tdi, +output reg tdo, +output tdoEnable, + +output [31:0] wr_data, +output [AWIDTH-1:0] wr_addr, +output wr_en, +output rd_en, + +input [31:0] rd_data, +input [1:0] rd_status, + +output reg dmi_reset, +output reg dmi_hard_reset, + +input [2:0] idle, +input [1:0] dmi_stat, +/* +-- revisionCode : 4'h0; +-- manufacturersIdCode : 11'h45; +-- deviceIdCode : 16'h0001; +-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB] +*/ +input [31:1] jtag_id, +input [3:0] version +); + +localparam USER_DR_LENGTH = AWIDTH + 34; + + +reg [USER_DR_LENGTH-1:0] sr, nsr, dr; + +/////////////////////////////////////////////////////// +// Tap controller +/////////////////////////////////////////////////////// +logic[3:0] state, nstate; +logic [4:0] ir; +wire jtag_reset; +wire shift_dr; +wire pause_dr; +wire update_dr; +wire capture_dr; +wire shift_ir; +wire pause_ir ; +wire update_ir ; +wire capture_ir; +wire[1:0] dr_en; +wire devid_sel; +wire [5:0] abits; + +assign abits = AWIDTH[5:0]; + + +localparam TEST_LOGIC_RESET_STATE = 0; +localparam RUN_TEST_IDLE_STATE = 1; +localparam SELECT_DR_SCAN_STATE = 2; +localparam CAPTURE_DR_STATE = 3; +localparam SHIFT_DR_STATE = 4; +localparam EXIT1_DR_STATE = 5; +localparam PAUSE_DR_STATE = 6; +localparam EXIT2_DR_STATE = 7; +localparam UPDATE_DR_STATE = 8; +localparam SELECT_IR_SCAN_STATE = 9; +localparam CAPTURE_IR_STATE = 10; +localparam SHIFT_IR_STATE = 11; +localparam EXIT1_IR_STATE = 12; +localparam PAUSE_IR_STATE = 13; +localparam EXIT2_IR_STATE = 14; +localparam UPDATE_IR_STATE = 15; + +always_comb begin + nstate = state; + case(state) + TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE; + RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE; + CAPTURE_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE; + SHIFT_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE; + EXIT1_DR_STATE: nstate = tms ? UPDATE_DR_STATE : PAUSE_DR_STATE; + PAUSE_DR_STATE: nstate = tms ? EXIT2_DR_STATE : PAUSE_DR_STATE; + EXIT2_DR_STATE: nstate = tms ? UPDATE_DR_STATE : SHIFT_DR_STATE; + UPDATE_DR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + SELECT_IR_SCAN_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE; + CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; + SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; + EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE; + PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE; + EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE; + UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + default: nstate = TEST_LOGIC_RESET_STATE; + endcase +end + +always @ (posedge tck or negedge trst) begin + if(!trst) state <= TEST_LOGIC_RESET_STATE; + else state <= nstate; +end + +assign jtag_reset = state == TEST_LOGIC_RESET_STATE; +assign shift_dr = state == SHIFT_DR_STATE; +assign pause_dr = state == PAUSE_DR_STATE; +assign update_dr = state == UPDATE_DR_STATE; +assign capture_dr = state == CAPTURE_DR_STATE; +assign shift_ir = state == SHIFT_IR_STATE; +assign pause_ir = state == PAUSE_IR_STATE; +assign update_ir = state == UPDATE_IR_STATE; +assign capture_ir = state == CAPTURE_IR_STATE; + +assign tdoEnable = shift_dr | shift_ir; + +/////////////////////////////////////////////////////// +// IR register +/////////////////////////////////////////////////////// + +always @ (negedge tck or negedge trst) begin + if (!trst) ir <= 5'b1; + else begin + if (jtag_reset) ir <= 5'b1; + else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0]; + end +end + + +assign devid_sel = ir == 5'b00001; +assign dr_en[0] = ir == 5'b10000; +assign dr_en[1] = ir == 5'b10001; + +/////////////////////////////////////////////////////// +// Shift register +/////////////////////////////////////////////////////// +always @ (posedge tck or negedge trst) begin + if(!trst)begin + sr <= '0; + end + else begin + sr <= nsr; + end +end + +// SR next value +always_comb begin + nsr = sr; + case(1) + shift_dr: begin + case(1) + dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]}; + + dr_en[0], + devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]}; + default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass + endcase + end + capture_dr: begin + case(1) + dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version}; + dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status}; + devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1}; + endcase + end + shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]}; + capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1}; + endcase +end + +// TDO retiming +always @ (negedge tck ) tdo <= sr[0]; + +// DMI CS register +always @ (posedge tck or negedge trst) begin + if(!trst) begin + dmi_hard_reset <= 1'b0; + dmi_reset <= 1'b0; + end + else if (update_dr & dr_en[0]) begin + dmi_hard_reset <= sr[17]; + dmi_reset <= sr[16]; + end + else begin + dmi_hard_reset <= 1'b0; + dmi_reset <= 1'b0; + end +end + +// DR register +always @ (posedge tck or negedge trst) begin + if(!trst) + dr <= '0; + else begin + if (update_dr & dr_en[1]) + dr <= sr; + else + dr <= {dr[USER_DR_LENGTH-1:2],2'b0}; + end +end + +assign {wr_addr, wr_data, wr_en, rd_en} = dr; + + + + +endmodule diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 1d300e88..d237bee7 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -410,9 +410,4 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { ahbm_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode) ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode) -} - -object AXImain extends App { - println("Generate Verilog") - println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb())) } \ No newline at end of file diff --git a/target/scala-2.12/classes/vsrc/beh_lib.sv b/target/scala-2.12/classes/vsrc/beh_lib.sv new file mode 100644 index 00000000..ea8f8dea --- /dev/null +++ b/target/scala-2.12/classes/vsrc/beh_lib.sv @@ -0,0 +1,506 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// all flops call the rvdff flop + + +module rvdff #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic clk, + input logic rst_l, + + output logic [WIDTH-1:0] dout + ); + +if (SHORT == 1) begin + assign dout = din; +end +else begin +`ifdef CLOCKGATE + always @(posedge tb_top.clk) begin + #0 $strobe("CG: %0t %m din %x dout %x clk %b width %d",$time,din,dout,clk,WIDTH); + end +`endif + + always_ff @(posedge clk or negedge rst_l) begin + if (rst_l == 0) + dout[WIDTH-1:0] <= 0; + else + dout[WIDTH-1:0] <= din[WIDTH-1:0]; + end + +end +endmodule + +// rvdff with 2:1 input mux to flop din iff sel==1 +module rvdffs #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic en, + input logic clk, + input logic rst_l, + output logic [WIDTH-1:0] dout + ); + +if (SHORT == 1) begin : genblock + assign dout = din; +end +else begin : genblock + rvdff #(WIDTH) dffs (.din((en) ? din[WIDTH-1:0] : dout[WIDTH-1:0]), .*); +end + +endmodule + +// rvdff with en and clear +module rvdffsc #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic en, + input logic clear, + input logic clk, + input logic rst_l, + output logic [WIDTH-1:0] dout + ); + + logic [WIDTH-1:0] din_new; +if (SHORT == 1) begin + assign dout = din; +end +else begin + assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]); + rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*); +end +endmodule + +module rvdffe #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic en, + input logic clk, + input logic rst_l, + input logic scan_mode, + output logic [WIDTH-1:0] dout + ); + + logic l1clk; + +if (SHORT == 1) begin : genblock + if (1) begin : genblock + assign dout = din; + end +end +else begin : genblock + +`ifndef PHYSICAL + if (WIDTH >= 8) begin: genblock +`endif + +`ifdef RV_FPGA_OPTIMIZE + rvdffs #(WIDTH) dff ( .* ); +`else + rvclkhdr clkhdr ( .* ); + rvdff #(WIDTH) dff (.*, .clk(l1clk)); +`endif + +`ifndef PHYSICAL + end + else + $error(" rvdffe width must be >= 8"); +`endif +end // else: !if(SHORT == 1) + +endmodule // rvdffe + +module rvsyncss #(parameter WIDTH = 251) + ( + input logic clk, + input logic rst_l, + input logic [WIDTH-1:0] din, + output logic [WIDTH-1:0] dout + ); + + logic [WIDTH-1:0] din_ff1; + + rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0])); + rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0])); + +endmodule // rvsyncss + +module rvlsadder + ( + input logic [31:0] rs1, + input logic [11:0] offset, + + output logic [31:0] dout + ); + + logic cout; + logic sign; + + logic [31:12] rs1_inc; + logic [31:12] rs1_dec; + + assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]}; + + assign rs1_inc[31:12] = rs1[31:12] + 1; + + assign rs1_dec[31:12] = rs1[31:12] - 1; + + assign sign = offset[11]; + + assign dout[31:12] = ({20{ sign ^~ cout}} & rs1[31:12]) | + ({20{ ~sign & cout}} & rs1_inc[31:12]) | + ({20{ sign & ~cout}} & rs1_dec[31:12]); + +endmodule // rvlsadder + +// assume we only maintain pc[31:1] in the pipe + +module rvbradder + ( + input [31:1] pc, + input [12:1] offset, + + output [31:1] dout + ); + + logic cout; + logic sign; + + logic [31:13] pc_inc; + logic [31:13] pc_dec; + + assign {cout,dout[12:1]} = {1'b0,pc[12:1]} + {1'b0,offset[12:1]}; + + assign pc_inc[31:13] = pc[31:13] + 1; + + assign pc_dec[31:13] = pc[31:13] - 1; + + assign sign = offset[12]; + + + assign dout[31:13] = ({19{ sign ^~ cout}} & pc[31:13]) | + ({19{ ~sign & cout}} & pc_inc[31:13]) | + ({19{ sign & ~cout}} & pc_dec[31:13]); + + +endmodule // rvbradder + + +// 2s complement circuit +module rvtwoscomp #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] din, + + output logic [WIDTH-1:0] dout + ); + + logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din + + genvar i; + + for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one + assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i]; + end : flip_after_first_one + + assign dout[WIDTH-1:0] = { dout_temp[WIDTH-1:1], din[0] }; + +endmodule // 2'scomp + +// find first +module rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) ) + ( + input logic [WIDTH-1:0] din, + + output logic [SHIFT-1:0] dout + ); + logic done; + + always_comb begin + dout[SHIFT-1:0] = {SHIFT{1'b0}}; + done = 1'b0; + + for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one + done |= din[i]; + dout[SHIFT-1:0] += done ? 1'b0 : 1'b1; + end : find_first_one + end +endmodule // rvfindfirst1 + +module rvfindfirst1hot #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] din, + + output logic [WIDTH-1:0] dout + ); + logic done; + + always_comb begin + dout[WIDTH-1:0] = {WIDTH{1'b0}}; + done = 1'b0; + for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one + dout[i] = ~done & din[i]; + done |= din[i]; + end : find_first_one + end +endmodule // rvfindfirst1hot + +// mask and match function matches bits after finding the first 0 position +// find first starting from LSB. Skip that location and match the rest of the bits +module rvmaskandmatch #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] mask, // this will have the mask in the lower bit positions + input logic [WIDTH-1:0] data, // this is what needs to be matched on the upper bits with the mask's upper bits + input logic masken, // when 1 : do mask. 0 : full match + output logic match + ); + + logic [WIDTH-1:0] matchvec; + logic masken_or_fullmask; + + assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]); + + assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]); + genvar i; + + for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero + assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]); + end : match_after_first_zero + + assign match = &matchvec[WIDTH-1:0]; // all bits either matched or were masked off + +endmodule // rvmaskandmatch + + + + +// Check if the S_ADDR <= addr < E_ADDR +module rvrangecheck #(CCM_SADR = 32'h0, + CCM_SIZE = 128) ( + input logic [31:0] addr, // Address to be checked for range + output logic in_range, // S_ADDR <= start_addr < E_ADDR + output logic in_region +); + + localparam REGION_BITS = 4; + localparam MASK_BITS = 10 + $clog2(CCM_SIZE); + + logic [31:0] start_addr; + logic [3:0] region; + + assign start_addr[31:0] = CCM_SADR; + assign region[REGION_BITS-1:0] = start_addr[31:(32-REGION_BITS)]; + + assign in_region = (addr[31:(32-REGION_BITS)] == region[REGION_BITS-1:0]); + if (CCM_SIZE == 48) + assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS-1 : MASK_BITS-2]); + else + assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]); + +endmodule // rvrangechecker + +// 16 bit even parity generator +module rveven_paritygen #(WIDTH = 16) ( + input logic [WIDTH-1:0] data_in, // Data + output logic parity_out // generated even parity + ); + + assign parity_out = ^(data_in[WIDTH-1:0]) ; + +endmodule // rveven_paritygen + +module rveven_paritycheck #(WIDTH = 16) ( + input logic [WIDTH-1:0] data_in, // Data + input logic parity_in, + output logic parity_err // Parity error + ); + + assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ; + +endmodule // rveven_paritycheck + +module rvecc_encode ( + input [31:0] din, + output [6:0] ecc_out + ); +logic [5:0] ecc_out_temp; + + assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; + assign ecc_out_temp[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]; + assign ecc_out_temp[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]; + assign ecc_out_temp[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_out_temp[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_out_temp[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]; + + assign ecc_out[6:0] = {(^din[31:0])^(^ecc_out_temp[5:0]),ecc_out_temp[5:0]}; + +endmodule // rvecc_encode + +module rvecc_decode ( + input en, + input [31:0] din, + input [6:0] ecc_in, + input sed_ded, // only do detection and no correction. Used for the I$ + output [31:0] dout, + output [6:0] ecc_out, + output single_ecc_error, + output double_ecc_error + + ); + + logic [6:0] ecc_check; + logic [38:0] error_mask; + logic [38:0] din_plus_parity, dout_plus_parity; + + // Generate the ecc bits + assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; + assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]; + assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]; + assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]; + + // This is the parity bit + assign ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0])) & ~sed_ded; + + assign single_ecc_error = en & (ecc_check[6:0] != 0) & ecc_check[6]; // this will never be on for sed_ded + assign double_ecc_error = en & (ecc_check[6:0] != 0) & ~ecc_check[6]; // all errors in the sed_ded case will be recorded as DE + + // Generate the mask for error correctiong + for (genvar i=1; i<40; i++) begin + assign error_mask[i-1] = (ecc_check[5:0] == i); + end + + // Generate the corrected data + assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]}; + + assign dout_plus_parity[38:0] = single_ecc_error ? (error_mask[38:0] ^ din_plus_parity[38:0]) : din_plus_parity[38:0]; + assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]}; + assign ecc_out[6:0] = {(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]}; + +endmodule // rvecc_decode + +module rvecc_encode_64 ( + input [63:0] din, + output [6:0] ecc_out + ); + assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63]; + + assign ecc_out[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63]; + + assign ecc_out[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_out[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[6] = din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63]; + +endmodule // rvecc_encode_64 + + +module rvecc_decode_64 ( + input en, + input [63:0] din, + input [6:0] ecc_in, + output ecc_error + ); + + logic [6:0] ecc_check; + + // Generate the ecc bits + assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63]; + + assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63]; + + assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[6] = ecc_in[6]^din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_error = en & (ecc_check[6:0] != 0); // all errors in the sed_ded case will be recorded as DE + + endmodule // rvecc_decode_64 + + +module gated_flop + ( + input logic SE, EN, CK, + output Q + ); + + logic en_ff; + logic enable; + + assign enable = EN | SE; + +`ifdef VERILATOR + always @(negedge CK) begin + en_ff <= enable; + end +`else + always @(CK, enable) begin + if(!CK) + en_ff = enable; + end +`endif + assign Q = CK & en_ff; + +endmodule + +module rvclkhdr + ( + input logic en, + input logic clk, + input logic scan_mode, + output logic l1clk + ); + + logic SE; + assign SE = scan_mode; + + gated_flop clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk)); + +endmodule // rvclkhdr + +module rvoclkhdr + ( + input logic en, + input logic clk, + input logic scan_mode, + output logic l1clk + ); + + logic SE; + assign SE = scan_mode; + +`ifdef RV_FPGA_OPTIMIZE + assign l1clk = clk; +`else + gated_flop clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk)); +`endif + +endmodule + + + diff --git a/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv b/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv index e69de29b..562f815e 100644 --- a/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv +++ b/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2019 +// Owner : Alex Grobman +// Description: +// This module Synchronizes the signals between JTAG (TCK) and +// processor (Core_clk) +// +//------------------------------------------------------------------------------------- + +module dmi_jtag_to_core_sync ( +// JTAG signals +input rd_en, // 1 bit Read Enable from JTAG +input wr_en, // 1 bit Write enable from JTAG + +// Processor Signals +input rst_n, // Core reset +input clk, // Core clock + +output reg_en, // 1 bit Write interface bit to Processor +output reg_wr_en // 1 bit Write enable to Processor +); + +wire c_rd_en; +wire c_wr_en; +reg [2:0] rden, wren; + + +// Outputs +assign reg_en = c_wr_en | c_rd_en; +assign reg_wr_en = c_wr_en; + + +// synchronizers +always @ ( posedge clk or negedge rst_n) begin + if(!rst_n) begin + rden <= '0; + wren <= '0; + end + else begin + rden <= {rden[1:0], rd_en}; + wren <= {wren[1:0], wr_en}; + end +end + +assign c_rd_en = rden[1] & ~rden[2]; +assign c_wr_en = wren[1] & ~wren[2]; + + +endmodule diff --git a/target/scala-2.12/classes/vsrc/dmi_wrapper.sv b/target/scala-2.12/classes/vsrc/dmi_wrapper.sv index e69de29b..d9fd7410 100644 --- a/target/scala-2.12/classes/vsrc/dmi_wrapper.sv +++ b/target/scala-2.12/classes/vsrc/dmi_wrapper.sv @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2018 +// Owner : Anusha Narayanamoorthy +// Description: +// Wrapper module for JTAG_TAP and DMI synchronizer +// +//------------------------------------------------------------------------------------- + +module dmi_wrapper( + + // JTAG signals + input trst_n, // JTAG reset + input tck, // JTAG clock + input tms, // Test mode select + input tdi, // Test Data Input + output tdo, // Test Data Output + output tdoEnable, // Test Data Output enable + + // Processor Signals + input core_rst_n, // Core reset + input core_clk, // Core clock + input [31:1] jtag_id, // JTAG ID + input [31:0] rd_data, // 32 bit Read data from Processor + output [31:0] reg_wr_data, // 32 bit Write data to Processor + output [6:0] reg_wr_addr, // 7 bit reg address to Processor + output reg_en, // 1 bit Read enable to Processor + output reg_wr_en, // 1 bit Write enable to Processor + output dmi_hard_reset +); + + + + + + //Wire Declaration + wire rd_en; + wire wr_en; + wire dmireset; + + + //jtag_tap instantiation + rvjtag_tap i_jtag_tap( + .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset + .tck(tck), // dedicated JTAG TCK pad signal + .tms(tms), // dedicated JTAG TMS pad signal + .tdi(tdi), // dedicated JTAG TDI pad signal + .tdo(tdo), // dedicated JTAG TDO pad signal + .tdoEnable(tdoEnable), // enable for TDO pad + .wr_data(reg_wr_data), // 32 bit Write data + .wr_addr(reg_wr_addr), // 7 bit Write address + .rd_en(rd_en), // 1 bit read enable + .wr_en(wr_en), // 1 bit Write enable + .rd_data(rd_data), // 32 bit Read data + .rd_status(2'b0), + .idle(3'h0), // no need to wait to sample data + .dmi_stat(2'b0), // no need to wait or error possible + .version(4'h1), // debug spec 0.13 compliant + .jtag_id(jtag_id), + .dmi_hard_reset(dmi_hard_reset), + .dmi_reset(dmireset) +); + + + // dmi_jtag_to_core_sync instantiation + dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync( + .wr_en(wr_en), // 1 bit Write enable + .rd_en(rd_en), // 1 bit Read enable + + .rst_n(core_rst_n), + .clk(core_clk), + .reg_en(reg_en), // 1 bit Write interface bit + .reg_wr_en(reg_wr_en) // 1 bit Write enable + ); + +endmodule diff --git a/target/scala-2.12/classes/vsrc/gated_latch.sv b/target/scala-2.12/classes/vsrc/gated_latch.sv new file mode 100644 index 00000000..51b96c9d --- /dev/null +++ b/target/scala-2.12/classes/vsrc/gated_latch.sv @@ -0,0 +1,14 @@ +module gated_latch + ( + input logic SE, EN, CK, + output Q + ); + logic en_ff; + logic enable; + assign enable = EN | SE; + always @(CK, enable) begin + if(!CK) + en_ff = enable; + end + assign Q = CK & en_ff; +endmodule diff --git a/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv b/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv index 8f7a1f12..269925a6 100644 --- a/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv +++ b/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv @@ -23,7 +23,7 @@ module ifu_ic_mem parameter ICACHE_NUM_WAYS, parameter ICACHE_BANK_BITS, parameter ICACHE_BEAT_ADDR_HI, - parameter ICACHE_BANKS_WAY, + parameter ICACHE_BANKS_WAY=2, parameter ICACHE_INDEX_HI, parameter ICACHE_BANK_HI, parameter ICACHE_BANK_LO, @@ -67,7 +67,7 @@ module ifu_ic_mem ) ; - IC_TAG #( + EL2_IC_TAG #( .ICACHE_BEAT_BITS(ICACHE_BEAT_BITS), .ICACHE_NUM_WAYS(ICACHE_NUM_WAYS), .ICACHE_BANK_BITS(ICACHE_BANK_BITS), @@ -90,7 +90,7 @@ module ifu_ic_mem .ic_rw_addr (ic_rw_addr[31:3]) ) ; - IC_DATA #( + EL2_IC_DATA #( .ICACHE_BEAT_BITS(ICACHE_BEAT_BITS), .ICACHE_NUM_WAYS(ICACHE_NUM_WAYS), .ICACHE_BANK_BITS(ICACHE_BANK_BITS), @@ -119,7 +119,7 @@ module ifu_ic_mem ///////////////////////////////////////////////// ////// ICACHE DATA MODULE //////////////////// ///////////////////////////////////////////////// -module IC_DATA +module EL2_IC_DATA #( parameter ICACHE_BEAT_BITS, parameter ICACHE_NUM_WAYS, @@ -990,7 +990,7 @@ endmodule // EL2_IC_DATA ///////////////////////////////////////////////// ////// ICACHE TAG MODULE //////////////////// ///////////////////////////////////////////////// -module IC_TAG +module EL2_IC_TAG #( parameter ICACHE_BEAT_BITS, parameter ICACHE_NUM_WAYS, diff --git a/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv b/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv index 1608a603..85c81c49 100644 --- a/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv +++ b/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv @@ -27,7 +27,7 @@ // //******************************************************************************** -module el2_lsu_dccm_mem +module lsu_dccm_mem #( parameter DCCM_BYTE_WIDTH, parameter DCCM_BITS, diff --git a/target/scala-2.12/classes/vsrc/mem.sv b/target/scala-2.12/classes/vsrc/mem.sv index 56e9fe57..0aee1897 100644 --- a/target/scala-2.12/classes/vsrc/mem.sv +++ b/target/scala-2.12/classes/vsrc/mem.sv @@ -15,14 +15,14 @@ module mem #( parameter DCCM_NUM_BANKS, parameter ICACHE_BANK_HI, parameter ICACHE_BANK_LO, - parameter DCCM_ENABLE, + parameter DCCM_ENABLE= 'b1, parameter ICACHE_TAG_LO, parameter ICACHE_DATA_INDEX_LO, parameter ICCM_NUM_BANKS, parameter ICACHE_ECC, - parameter ICACHE_ENABLE, + parameter ICACHE_ENABLE= 'b1, parameter DCCM_BANK_BITS, - parameter ICCM_ENABLE, + parameter ICCM_ENABLE= 'b1, parameter ICCM_BANK_BITS, parameter ICACHE_TAG_DEPTH, parameter ICACHE_WAYPACK, @@ -77,8 +77,9 @@ module mem #( input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic ic_sel_premux_data, // Premux data sel - input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC - input logic [70:0] ic_debug_wr_data, // Debug wr cache. + input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC + input logic [70:0] ic_wr_data_1, + input logic [70:0] ic_debug_wr_data, // Debug wr cache. output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. input logic ic_debug_rd_en, // Icache debug rd @@ -100,6 +101,9 @@ module mem #( ); + logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data; +assign ic_wr_data [0] = ic_wr_data_0; +assign ic_wr_data [1] = ic_wr_data_1; // DCCM Instantiation if (DCCM_ENABLE == 1) begin: Gen_dccm_enable lsu_dccm_mem #( @@ -142,7 +146,7 @@ else begin assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0; assign ic_tag_perr = '0 ; assign ic_rd_data = '0 ; - assign ic_stag_debug_rd_data = '0 ; + assign ic_tag_debug_rd_data = '0 ; end // else: !if( ICACHE_ENABLE ) diff --git a/target/scala-2.12/classes/vsrc/mem_lib.sv b/target/scala-2.12/classes/vsrc/mem_lib.sv new file mode 100644 index 00000000..e741c618 --- /dev/null +++ b/target/scala-2.12/classes/vsrc/mem_lib.sv @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`define EL2_LOCAL_RAM_TEST_IO \ +input logic WE, \ +input logic ME, \ +input logic CLK + +`define EL2_RAM(depth, width) \ +module ram_``depth``x``width( \ + input logic [$clog2(depth)-1:0] ADR, \ + input logic [(width-1):0] D, \ + output logic [(width-1):0] Q, \ + `EL2_LOCAL_RAM_TEST_IO \ +); \ +reg [(width-1):0] ram_core [(depth-1):0]; \ + \ +always @(posedge CLK) begin \ + if (ME && WE) ram_core[ADR] = D; \ + if (ME && ~WE) Q <= ram_core[ADR]; \ +end \ + \ +endmodule + +`define EL2_RAM_BE(depth, width) \ +module ram_be_``depth``x``width( \ + input logic [$clog2(depth)-1:0] ADR, \ + input logic [(width-1):0] D, WEM, \ + output logic [(width-1):0] Q, \ + `EL2_LOCAL_RAM_TEST_IO \ +); \ +reg [(width-1):0] ram_core [(depth-1):0]; \ + \ +always @(posedge CLK) begin \ + if (ME && WE) ram_core[ADR] = D & WEM | ~WEM & ram_core[ADR];\ + if (ME && ~WE) Q <= ram_core[ADR]; \ +end \ + \ + \ +endmodule + +// parameterizable RAM for verilator sims +module el2_ram #(depth=4096, width=39) ( +input logic [$clog2(depth)-1:0] ADR, +input logic [(width-1):0] D, +output logic [(width-1):0] Q, + `EL2_LOCAL_RAM_TEST_IO +); +reg [(width-1):0] ram_core [(depth-1):0]; + +always @(posedge CLK) begin + if (ME && WE) ram_core[ADR] = D; + if (ME && ~WE) Q <= ram_core[ADR]; +end +endmodule + +//========================================================================================================================= +//=================================== START OF CCM ======================================================================= +//============= Possible sram sizes for a 39 bit wide memory ( 4 bytes + 7 bits ECC ) ===================================== +//------------------------------------------------------------------------------------------------------------------------- +`EL2_RAM(32768, 39) +`EL2_RAM(16384, 39) +`EL2_RAM(8192, 39) +`EL2_RAM(4096, 39) +`EL2_RAM(3072, 39) +`EL2_RAM(2048, 39) +`EL2_RAM(1536, 39) // need this for the 48KB DCCM option) +`EL2_RAM(1024, 39) +`EL2_RAM(768, 39) +`EL2_RAM(512, 39) +`EL2_RAM(256, 39) +`EL2_RAM(128, 39) +`EL2_RAM(1024, 20) +`EL2_RAM(512, 20) +`EL2_RAM(256, 20) +`EL2_RAM(128, 20) +`EL2_RAM(64, 20) +`EL2_RAM(4096, 34) +`EL2_RAM(2048, 34) +`EL2_RAM(1024, 34) +`EL2_RAM(512, 34) +`EL2_RAM(256, 34) +`EL2_RAM(128, 34) +`EL2_RAM(64, 34) +`EL2_RAM(8192, 68) +`EL2_RAM(4096, 68) +`EL2_RAM(2048, 68) +`EL2_RAM(1024, 68) +`EL2_RAM(512, 68) +`EL2_RAM(256, 68) +`EL2_RAM(128, 68) +`EL2_RAM(64, 68) +`EL2_RAM(8192, 71) +`EL2_RAM(4096, 71) +`EL2_RAM(2048, 71) +`EL2_RAM(1024, 71) +`EL2_RAM(512, 71) +`EL2_RAM(256, 71) +`EL2_RAM(128, 71) +`EL2_RAM(64, 71) +`EL2_RAM(4096, 42) +`EL2_RAM(2048, 42) +`EL2_RAM(1024, 42) +`EL2_RAM(512, 42) +`EL2_RAM(256, 42) +`EL2_RAM(128, 42) +`EL2_RAM(64, 42) +`EL2_RAM(4096, 22) +`EL2_RAM(2048, 22) +`EL2_RAM(1024, 22) +`EL2_RAM(512, 22) +`EL2_RAM(256, 22) +`EL2_RAM(128, 22) +`EL2_RAM(64, 22) +`EL2_RAM(1024, 26) +`EL2_RAM(4096, 26) +`EL2_RAM(2048, 26) +`EL2_RAM(512, 26) +`EL2_RAM(256, 26) +`EL2_RAM(128, 26) +`EL2_RAM(64, 26) +`EL2_RAM(32, 26) +`EL2_RAM(32, 22) +`EL2_RAM_BE(8192, 142) +`EL2_RAM_BE(4096, 142) +`EL2_RAM_BE(2048, 142) +`EL2_RAM_BE(1024, 142) +`EL2_RAM_BE(512, 142) +`EL2_RAM_BE(256, 142) +`EL2_RAM_BE(128, 142) +`EL2_RAM_BE(64, 142) +`EL2_RAM_BE(8192, 284) +`EL2_RAM_BE(4096, 284) +`EL2_RAM_BE(2048, 284) +`EL2_RAM_BE(1024, 284) +`EL2_RAM_BE(512, 284) +`EL2_RAM_BE(256, 284) +`EL2_RAM_BE(128, 284) +`EL2_RAM_BE(64, 284) +`EL2_RAM_BE(8192, 136) +`EL2_RAM_BE(4096, 136) +`EL2_RAM_BE(2048, 136) +`EL2_RAM_BE(1024, 136) +`EL2_RAM_BE(512, 136) +`EL2_RAM_BE(256, 136) +`EL2_RAM_BE(128, 136) +`EL2_RAM_BE(64, 136) +`EL2_RAM_BE(8192, 272) +`EL2_RAM_BE(4096, 272) +`EL2_RAM_BE(2048, 272) +`EL2_RAM_BE(1024, 272) +`EL2_RAM_BE(512, 272) +`EL2_RAM_BE(256, 272) +`EL2_RAM_BE(128, 272) +`EL2_RAM_BE(64, 272) +`EL2_RAM_BE(4096, 52) +`EL2_RAM_BE(2048, 52) +`EL2_RAM_BE(1024, 52) +`EL2_RAM_BE(512, 52) +`EL2_RAM_BE(256, 52) +`EL2_RAM_BE(128, 52) +`EL2_RAM_BE(64, 52) +`EL2_RAM_BE(4096, 104) +`EL2_RAM_BE(2048, 104) +`EL2_RAM_BE(1024, 104) +`EL2_RAM_BE(512, 104) +`EL2_RAM_BE(256, 104) +`EL2_RAM_BE(128, 104) +`EL2_RAM_BE(64, 104) +`EL2_RAM_BE(4096, 44) +`EL2_RAM_BE(2048, 44) +`EL2_RAM_BE(1024, 44) +`EL2_RAM_BE(512, 44) +`EL2_RAM_BE(256, 44) +`EL2_RAM_BE(128, 44) +`EL2_RAM_BE(64, 44) +`EL2_RAM_BE(4096, 88) +`EL2_RAM_BE(2048, 88) +`EL2_RAM_BE(1024, 88) +`EL2_RAM_BE(512, 88) +`EL2_RAM_BE(256, 88) +`EL2_RAM_BE(128, 88) +`EL2_RAM_BE(64, 88) + + +`undef EL2_RAM +`undef EL2_RAM_BE +`undef EL2_LOCAL_RAM_TEST_IO + + diff --git a/target/scala-2.12/classes/vsrc/mem_mod.sv b/target/scala-2.12/classes/vsrc/mem_mod.sv new file mode 100644 index 00000000..6f71a3c1 --- /dev/null +++ b/target/scala-2.12/classes/vsrc/mem_mod.sv @@ -0,0 +1,64 @@ +module el2_btb_tag_hash #( +`include "el2_param.vh" + ) ( + input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc, + output logic [pt.BTB_BTAG_SIZE-1:0] hash + ); + + assign hash = {(pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])}; +endmodule + +module el2_btb_tag_hash_fold #( +`include "el2_param.vh" + )( + input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc, + output logic [pt.BTB_BTAG_SIZE-1:0] hash + ); + + assign hash = {( + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])}; + +endmodule + +module el2_btb_addr_hash #( +`include "el2_param.vh" + )( + input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc, + output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash + ); + + +if(pt.BTB_FOLD2_INDEX_HASH) begin : fold2 + assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^ + pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO]; +end + else begin + assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^ + pc[pt.BTB_INDEX2_HI:pt.BTB_INDEX2_LO] ^ + pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO]; +end + +endmodule + +module el2_btb_ghr_hash #( +`include "el2_param.vh" + )( + input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin, + input logic [pt.BHT_GHR_SIZE-1:0] ghr, + output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash + ); + + // The hash function is too complex to write in verilog for all cases. + // The config script generates the logic string based on the bp config. + if(pt.BHT_GHR_HASH_1) begin : ghrhash_cfg1 + assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { ghr[pt.BHT_GHR_SIZE-1:pt.BTB_INDEX1_HI-1], hashin[pt.BTB_INDEX1_HI:2]^ghr[pt.BTB_INDEX1_HI-2:0]}; + end + else begin : ghrhash_cfg2 + assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { hashin[pt.BHT_GHR_SIZE+1:2]^ghr[pt.BHT_GHR_SIZE-1:0]}; + end + + +endmodule diff --git a/target/scala-2.12/classes/vsrc/rvjtag_tap.sv b/target/scala-2.12/classes/vsrc/rvjtag_tap.sv new file mode 100644 index 00000000..24634344 --- /dev/null +++ b/target/scala-2.12/classes/vsrc/rvjtag_tap.sv @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License + +module rvjtag_tap #( +parameter AWIDTH = 7 +) +( +input trst, +input tck, +input tms, +input tdi, +output reg tdo, +output tdoEnable, + +output [31:0] wr_data, +output [AWIDTH-1:0] wr_addr, +output wr_en, +output rd_en, + +input [31:0] rd_data, +input [1:0] rd_status, + +output reg dmi_reset, +output reg dmi_hard_reset, + +input [2:0] idle, +input [1:0] dmi_stat, +/* +-- revisionCode : 4'h0; +-- manufacturersIdCode : 11'h45; +-- deviceIdCode : 16'h0001; +-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB] +*/ +input [31:1] jtag_id, +input [3:0] version +); + +localparam USER_DR_LENGTH = AWIDTH + 34; + + +reg [USER_DR_LENGTH-1:0] sr, nsr, dr; + +/////////////////////////////////////////////////////// +// Tap controller +/////////////////////////////////////////////////////// +logic[3:0] state, nstate; +logic [4:0] ir; +wire jtag_reset; +wire shift_dr; +wire pause_dr; +wire update_dr; +wire capture_dr; +wire shift_ir; +wire pause_ir ; +wire update_ir ; +wire capture_ir; +wire[1:0] dr_en; +wire devid_sel; +wire [5:0] abits; + +assign abits = AWIDTH[5:0]; + + +localparam TEST_LOGIC_RESET_STATE = 0; +localparam RUN_TEST_IDLE_STATE = 1; +localparam SELECT_DR_SCAN_STATE = 2; +localparam CAPTURE_DR_STATE = 3; +localparam SHIFT_DR_STATE = 4; +localparam EXIT1_DR_STATE = 5; +localparam PAUSE_DR_STATE = 6; +localparam EXIT2_DR_STATE = 7; +localparam UPDATE_DR_STATE = 8; +localparam SELECT_IR_SCAN_STATE = 9; +localparam CAPTURE_IR_STATE = 10; +localparam SHIFT_IR_STATE = 11; +localparam EXIT1_IR_STATE = 12; +localparam PAUSE_IR_STATE = 13; +localparam EXIT2_IR_STATE = 14; +localparam UPDATE_IR_STATE = 15; + +always_comb begin + nstate = state; + case(state) + TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE; + RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE; + CAPTURE_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE; + SHIFT_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE; + EXIT1_DR_STATE: nstate = tms ? UPDATE_DR_STATE : PAUSE_DR_STATE; + PAUSE_DR_STATE: nstate = tms ? EXIT2_DR_STATE : PAUSE_DR_STATE; + EXIT2_DR_STATE: nstate = tms ? UPDATE_DR_STATE : SHIFT_DR_STATE; + UPDATE_DR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + SELECT_IR_SCAN_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE; + CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; + SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; + EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE; + PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE; + EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE; + UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + default: nstate = TEST_LOGIC_RESET_STATE; + endcase +end + +always @ (posedge tck or negedge trst) begin + if(!trst) state <= TEST_LOGIC_RESET_STATE; + else state <= nstate; +end + +assign jtag_reset = state == TEST_LOGIC_RESET_STATE; +assign shift_dr = state == SHIFT_DR_STATE; +assign pause_dr = state == PAUSE_DR_STATE; +assign update_dr = state == UPDATE_DR_STATE; +assign capture_dr = state == CAPTURE_DR_STATE; +assign shift_ir = state == SHIFT_IR_STATE; +assign pause_ir = state == PAUSE_IR_STATE; +assign update_ir = state == UPDATE_IR_STATE; +assign capture_ir = state == CAPTURE_IR_STATE; + +assign tdoEnable = shift_dr | shift_ir; + +/////////////////////////////////////////////////////// +// IR register +/////////////////////////////////////////////////////// + +always @ (negedge tck or negedge trst) begin + if (!trst) ir <= 5'b1; + else begin + if (jtag_reset) ir <= 5'b1; + else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0]; + end +end + + +assign devid_sel = ir == 5'b00001; +assign dr_en[0] = ir == 5'b10000; +assign dr_en[1] = ir == 5'b10001; + +/////////////////////////////////////////////////////// +// Shift register +/////////////////////////////////////////////////////// +always @ (posedge tck or negedge trst) begin + if(!trst)begin + sr <= '0; + end + else begin + sr <= nsr; + end +end + +// SR next value +always_comb begin + nsr = sr; + case(1) + shift_dr: begin + case(1) + dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]}; + + dr_en[0], + devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]}; + default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass + endcase + end + capture_dr: begin + case(1) + dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version}; + dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status}; + devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1}; + endcase + end + shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]}; + capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1}; + endcase +end + +// TDO retiming +always @ (negedge tck ) tdo <= sr[0]; + +// DMI CS register +always @ (posedge tck or negedge trst) begin + if(!trst) begin + dmi_hard_reset <= 1'b0; + dmi_reset <= 1'b0; + end + else if (update_dr & dr_en[0]) begin + dmi_hard_reset <= sr[17]; + dmi_reset <= sr[16]; + end + else begin + dmi_hard_reset <= 1'b0; + dmi_reset <= 1'b0; + end +end + +// DR register +always @ (posedge tck or negedge trst) begin + if(!trst) + dr <= '0; + else begin + if (update_dr & dr_en[1]) + dr <= sr; + else + dr <= {dr[USER_DR_LENGTH-1:2],2'b0}; + end +end + +assign {wr_addr, wr_data, wr_en, rd_en} = dr; + + + + +endmodule