Final BP

el2_ifu_bp_ctl.anno.json

@@ -134,6 +134,11 @@
     "class":"firrtl.EmitCircuitAnnotation",
     "emitter":"firrtl.VerilogEmitter"
   },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"el2_ifu_bp_ctl.TEC_RV_ICG",
+    "resourceId":"/vsrc/TEC_RV_ICG.v"
+  },
   {
     "class":"firrtl.options.TargetDirAnnotation",
     "directory":"."

src/main/scala/ifu/el2_ifu_bp_ctl.scala

@@ -377,6 +377,11 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
                             (bht_wr_en2(i) & ((bht_wr_addr2(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-2)===k.U) |  BHT_NO_ADDR_MATCH.B))
   }
 
+
+  val bht_bank_clk = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>
+    rvclkhdr(clock, bht_bank_clken(i)(k), 1.U.asBool)))
+
+
   val bht_bank_wr_data = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>(0 until NUM_BHT_LOOP).map(j=>
     Mux((bht_wr_en2(i)&(bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt)&(bht_wr_addr2(BHT_ADDR_HI-NUM_BHT_LOOP_OUTER_LO+1,NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt)|BHT_NO_ADDR_MATCH.B).asBool, bht_wr_data2, bht_wr_data0))))
   val bht_bank_sel = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Vec(NUM_BHT_LOOP, Bool()))))
@@ -389,9 +394,11 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
 // Blah blah
   val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W))))
   for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
-    bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j)&bht_bank_clken(i)(k))
+    bht_bank_rd_data_out(i)((16*k)+j) := withClock(bht_bank_clk(i)(k)){RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j))}
   }
 
+
+
   bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i)))
   bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
   bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))

src/main/scala/lib/el2_lib.scala

@@ -412,6 +412,21 @@ trait el2_lib extends param{
     }
   }
 
+//  class rvclkhdr extends Module {
+//    val io = IO(new Bundle {
+//      val l1clk = Output(Clock())
+//      val clk  = Input(Clock())
+//      val en  = Input(Bool())
+//      val scan_mode = Input(Bool())
+//    })
+//    val clkhdr = { Module(new TEC_RV_ICG) }
+//    io.l1clk := clkhdr.io.Q
+//    clkhdr.io.CK := io.clk
+//    clkhdr.io.EN := io.en
+//    clkhdr.io.SE := io.scan_mode
+//  }
+
+
   object rvdffe {
     def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = {
       val obj = Module(new rvclkhdr())
@@ -434,4 +449,14 @@ trait el2_lib extends param{
       }
     }
   }
+
+//    def rvclkhdr_M(clk: Clock, en: Bool, scan_mode: Bool): Clock = {
+//      val cg = Module(new rvclkhdr)
+//      cg.io.clk := clk
+//      cg.io.en := en
+//      cg.io.scan_mode := scan_mode
+//      cg.io.l1clk
+//    }
+
+
 }