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This commit is contained in:
Junaid Ahmed
GitHub
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39de042d82
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0e4fff42ab
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@ -0,0 +1,188 @@
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class el2_lsu_addrcheck extends MultiIOModule
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{
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val lsu_c2_m_clk = IO(Input(Clock()))
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//val rst_l = IO(Input(1.W)) //implicit
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val start_addr_d = IO(Input(UInt(32.W)))
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val end_addr_d = IO(Input(UInt(32.W)))
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val lsu_pkt_d = IO(Input(new el2_lsu_pkt_t))
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val dec_tlu_mrac_ff = IO(Input(UInt(32.W)))
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val rs1_region_d = IO(Input(UInt(4.W)))
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val rs1_d = IO(Input(UInt(32.W)))
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val is_sideeffects_m = IO(Output(UInt(1.W)))
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val addr_in_dccm_d = IO(Output(UInt(1.W)))
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val addr_in_pic_d = IO(Output(UInt(1.W)))
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val addr_external_d = IO(Output(UInt(1.W)))
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val access_fault_d = IO(Output(UInt(1.W)))
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val misaligned_fault_d = IO(Output(UInt(1.W)))
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val exc_mscause_d = IO(Output(UInt(4.W)))
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val fir_dccm_access_error_d = IO(Output(UInt(1.W)))
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val fir_nondccm_access_error_d = IO(Output(UInt(1.W)))
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val scan_mode = IO(Input(UInt(1.W)))
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val start_addr_in_dccm_d = WireInit(0.U(1.W))
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val start_addr_in_dccm_region_d = WireInit(0.U(1.W))
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val end_addr_in_dccm_d = WireInit(0.U(1.W))
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val end_addr_in_dccm_region_d = WireInit(0.U(1.W))
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//DCCM check
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// Start address check
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if(pt1.DCCM_ENABLE==1){ // Gen_dccm_enable
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val start_addr_dccm_rangecheck = Module(new rvrangecheck(pt1.DCCM_SADR,pt1.DCCM_SIZE))
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start_addr_dccm_rangecheck.io.addr := start_addr_d
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start_addr_in_dccm_d := start_addr_dccm_rangecheck.io.in_range
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start_addr_in_dccm_region_d := start_addr_dccm_rangecheck.io.in_region
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// End address check
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val end_addr_dccm_rangecheck = Module(new rvrangecheck(pt1.DCCM_SADR,pt1.DCCM_SIZE))
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end_addr_dccm_rangecheck.io.addr := end_addr_d
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end_addr_in_dccm_d := end_addr_dccm_rangecheck.io.in_range
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end_addr_in_dccm_region_d := end_addr_dccm_rangecheck.io.in_region
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}
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else{ //Gen_dccm_disable
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start_addr_in_dccm_d := 0.U
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start_addr_in_dccm_region_d := 0.U
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end_addr_in_dccm_d := 0.U
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end_addr_in_dccm_region_d := 0.U
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}
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val addr_in_iccm = WireInit(0.U(1.W))
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if(pt1.ICCM_ENABLE == 1){ //check_iccm
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addr_in_iccm := (start_addr_d(31,28) === pt.ICCM_REGION)
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}
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else{
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addr_in_iccm := 1.U
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}
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//PIC memory check
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//start address check
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val start_addr_pic_rangecheck = Module(new rvrangecheck(pt1.PIC_BASE_ADDR,pt1.PIC_SIZE))
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start_addr_pic_rangecheck.io.addr := start_addr_d(31,0)
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val start_addr_in_pic_d = start_addr_pic_rangecheck.io.in_range
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val start_addr_in_pic_region_d = start_addr_pic_rangecheck.io.in_region
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//End address check
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val end_addr_pic_rangecheck = Module(new rvrangecheck(pt1.PIC_BASE_ADDR,pt1.PIC_SIZE))
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end_addr_pic_rangecheck.io.addr := end_addr_d(31,0)
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val end_addr_in_pic_d = end_addr_pic_rangecheck.io.in_range
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val end_addr_in_pic_region_d = end_addr_pic_rangecheck.io.in_region
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val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d
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val base_reg_dccm_or_pic = (rs1_region_d(3,0) === pt.DCCM_REGION) | (rs1_region_d(3,0) === pt.PIC_REGION) //base region
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addr_in_dccm_d := (start_addr_in_dccm_d & end_addr_in_dccm_d)
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addr_in_pic_d := (start_addr_in_pic_d & end_addr_in_pic_d)
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addr_external_d := ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d); //if start address does not belong to dccm/pic
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val csr_idx = Cat(start_addr_d(31,28),"b1".U)
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val is_sideeffects_d = dec_tlu_mrac_ff(csr_idx) & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & lsu_pkt_d.valid & (lsu_pkt_d.store | lsu_pkt_d.load) //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
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val is_aligned_d = (lsu_pkt_d.word & (start_addr_d(1,0) === "b00".U)) | (lsu_pkt_d.half & (start_addr_d(0) === "b0".U)) | lsu_pkt_d.by
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val non_dccm_access_ok = (~(Cat(pt.DATA_ACCESS_ENABLE0,pt.DATA_ACCESS_ENABLE1,pt.DATA_ACCESS_ENABLE2,pt.DATA_ACCESS_ENABLE3,
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pt.DATA_ACCESS_ENABLE4,pt.DATA_ACCESS_ENABLE5,pt.DATA_ACCESS_ENABLE6,pt.DATA_ACCESS_ENABLE7)).orR) |
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(((pt.DATA_ACCESS_ENABLE0 & ((start_addr_d(31,0) | pt.DATA_ACCESS_MASK0)) === (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) | //0111
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(pt.DATA_ACCESS_ENABLE1 & ((start_addr_d(31,0) | pt.DATA_ACCESS_MASK1)) === (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) | //1111
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(pt.DATA_ACCESS_ENABLE2 & ((start_addr_d(31,0) | pt.DATA_ACCESS_MASK2)) === (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) | //1011
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(pt.DATA_ACCESS_ENABLE3 & ((start_addr_d(31,0) | pt.DATA_ACCESS_MASK3)) === (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) | //1000
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(pt.DATA_ACCESS_ENABLE4 & ((start_addr_d(31,0) | pt.DATA_ACCESS_MASK4)) === (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) |
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(pt.DATA_ACCESS_ENABLE5 & ((start_addr_d(31,0) | pt.DATA_ACCESS_MASK5)) === (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) |
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(pt.DATA_ACCESS_ENABLE6 & ((start_addr_d(31,0) | pt.DATA_ACCESS_MASK6)) === (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) |
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(pt.DATA_ACCESS_ENABLE7 & ((start_addr_d(31,0) | pt.DATA_ACCESS_MASK7)) === (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7)))
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&
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((pt.DATA_ACCESS_ENABLE0 & ((end_addr_d(31,0) | pt.DATA_ACCESS_MASK0)) === (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) |
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(pt.DATA_ACCESS_ENABLE1 & ((end_addr_d(31,0) | pt.DATA_ACCESS_MASK1)) === (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) |
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(pt.DATA_ACCESS_ENABLE2 & ((end_addr_d(31,0) | pt.DATA_ACCESS_MASK2)) === (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) |
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(pt.DATA_ACCESS_ENABLE3 & ((end_addr_d(31,0) | pt.DATA_ACCESS_MASK3)) === (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) |
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(pt.DATA_ACCESS_ENABLE4 & ((end_addr_d(31,0) | pt.DATA_ACCESS_MASK4)) === (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) |
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(pt.DATA_ACCESS_ENABLE5 & ((end_addr_d(31,0) | pt.DATA_ACCESS_MASK5)) === (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) |
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(pt.DATA_ACCESS_ENABLE6 & ((end_addr_d(31,0) | pt.DATA_ACCESS_MASK6)) === (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) |
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(pt.DATA_ACCESS_ENABLE7 & ((end_addr_d(31,0) | pt.DATA_ACCESS_MASK7)) === (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7))))
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val regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic)
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val picm_access_fault_d = (addr_in_pic_d & ((start_addr_d(1,0) != "b00".U) | ~lsu_pkt_d.word))
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val unmapped_access_fault_d = WireInit(1.U(1.W))
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val mpu_access_fault_d = WireInit(1.U(1.W))
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if(pt1.DCCM_REGION == pt1.PIC_REGION){
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unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d)) |
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// 0. Addr in dccm/pic region but not in dccm/pic offset
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(end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d)) |
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// 0. Addr in dccm/pic region but not in dccm/pic offset
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(start_addr_in_dccm_d & end_addr_in_pic_d) |
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// 0. DCCM -> PIC cross when DCCM/PIC in same region
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(start_addr_in_pic_d & end_addr_in_dccm_d))
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// 0. DCCM -> PIC cross when DCCM/PIC in same region
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mpu_access_fault_d := (~start_addr_in_dccm_region_d & ~non_dccm_access_ok)
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// 3. Address is not in a populated non-dccm region
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}
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else{
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unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) |
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// 0. Addr in dccm region but not in dccm offset
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(end_addr_in_dccm_region_d & ~end_addr_in_dccm_d) |
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// 0. Addr in dccm region but not in dccm offset
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(start_addr_in_pic_region_d & ~start_addr_in_pic_d) |
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// 0. Addr in picm region but not in picm offset
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(end_addr_in_pic_region_d & ~end_addr_in_pic_d))
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// 0. Addr in picm region but not in picm offset
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mpu_access_fault_d := (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);
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// 3. Address is not in a populated non-dccm region
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}
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//check width of access_fault_mscause_d
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access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & lsu_pkt_d.valid & ~lsu_pkt_d.dma
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val access_fault_mscause_d = WireInit(0.U(4.W))
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access_fault_mscause_d := Mux(unmapped_access_fault_d.asBool, "b0010".U, Mux(mpu_access_fault_d.asBool, "b0011".U, Mux(regpred_access_fault_d.asBool, "b0101".U, Mux(picm_access_fault_d.asBool, "b0110".U, "b0000".U))))
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val regcross_misaligned_fault_d = (start_addr_d(31,28) =/= end_addr_d(31,28))
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val sideeffect_misaligned_fault_d = (is_sideeffects_d & ~ is_aligned_d)
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misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & addr_external_d)) & lsu_pkt_d.valid & ~lsu_pkt_d.dma
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val misaligned_fault_mscause_d = WireInit(0.U(4.W))
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misaligned_fault_mscause_d := Mux(regcross_misaligned_fault_d, "b0010".U, Mux(sideeffect_misaligned_fault_d.asBool, "b0001".U, "b0000".U))
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exc_mscause_d := Mux(misaligned_fault_d.asBool, misaligned_fault_mscause_d(3,0), access_fault_mscause_d(3,0))
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// Fast interrupt error logic
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fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) |
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(end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & lsu_pkt_d.valid & lsu_pkt_d.fast_int
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fir_nondccm_access_error_d := ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & lsu_pkt_d.valid & lsu_pkt_d.fast_int
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//rvdff #(.WIDTH(1)) is_sideeffects_mff (.din(is_sideeffects_d), .dout(is_sideeffects_m), .clk(lsu_c2_m_clk), .*);
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val is_sideeffects_mff = Module(new rvdff(1,0)) //TBD for clock and reset
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is_sideeffects_mff.io.din := is_sideeffects_d
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is_sideeffects_m := is_sideeffects_mff.io.dout
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//is_sideeffects_m :=0.U
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// addr_in_dccm_d :=0.U
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// addr_in_pic_d :=0.U
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// addr_external_d :=0.U
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// access_fault_d :=0.U
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// misaligned_fault_d :=0.U
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// exc_mscause_d :=0.U
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// fir_dccm_access_error_d :=0.U
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// fir_nondccm_access_error_d :=0.U
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}
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@ -0,0 +1,108 @@
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class el2_lsu_lsc_ctl extends MultiIOModule
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{
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//val rst_l = IO(Input(1.W)) //implicit
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val lsu_c1_m_clk = IO(Input(Clock()))
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val lsu_c1_r_clk = IO(Input(Clock()))
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val lsu_c2_m_clk = IO(Input(Clock()))
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val lsu_c2_r_clk = IO(Input(Clock()))
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val lsu_store_c1_m_clk = IO(Input(Clock()))
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val lsu_ld_data_r = IO(Input(UInt(32.W))) //DCCM data
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val lsu_ld_data_corr_r = IO(Input(UInt(32.W))) // ECC corrected data
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val lsu_single_ecc_error_r = IO(Input(UInt(1.W)))
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val lsu_double_ecc_error_r = IO(Input(UInt(1.W)))
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val lsu_ld_data_m = IO(Input(UInt(32.W)))
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val lsu_single_ecc_error_m = IO(Input(UInt(1.W)))
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val lsu_double_ecc_error_m = IO(Input(UInt(1.W)))
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val flush_m_up = IO(Input(UInt(1.W)))
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val flush_r = IO(Input(UInt(1.W)))
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val exu_lsu_rs1_d = IO(Input(UInt(32.W))) // address
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val exu_lsu_rs2_d = IO(Input(UInt(32.W))) // store data
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val lsu_p = IO(Input(new el2_lsu_pkt_t())) // lsu control packet //coming from decode
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val dec_lsu_valid_raw_d = IO(Input(UInt(1.W))) // Raw valid for address computation
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val dec_lsu_offset_d = IO(Input(UInt(12.W)))
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val picm_mask_data_m = IO(Input(UInt(32.W)))
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val bus_read_data_m = IO(Input(UInt(32.W))) //coming from bus interface
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val lsu_result_m = IO(Output(UInt(32.W)) )
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val lsu_result_corr_r = IO(Output(UInt(32.W))) // This is the ECC corrected data going to RF
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// lsu address down the pipe
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val lsu_addr_d = IO(Output(UInt(32.W)))
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val lsu_addr_m = IO(Output(UInt(32.W)))
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val lsu_addr_r = IO(Output(UInt(32.W)))
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// lsu address down the pipe - needed to check unaligned
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val end_addr_d = IO(Output(UInt(32.W)))
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val end_addr_m = IO(Output(UInt(32.W)))
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val end_addr_r = IO(Output(UInt(32.W)))
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// store data down the pipe
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val store_data_m = IO(Output(UInt(32.W)))
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val dec_tlu_mrac_ff = IO(Output(UInt(32.W))) // CSR read
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val lsu_exc_m = IO(Output(UInt(1.W)))
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val is_sideeffects_m = IO(Output(UInt(1.W)))
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val lsu_commit_r = IO(Output(UInt(1.W)))
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val lsu_single_ecc_error_incr = IO(Output(UInt(1.W)))
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val lsu_error_pkt_r = IO(Output(new el2_lsu_error_pkt_t()))
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val lsu_fir_addr = IO(Output(UInt(32.W))) //(31:1) in sv // fast interrupt address TBD
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val lsu_fir_error = IO(Output(UInt(2.W))) // Error during fast interrupt lookup TBD
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// address in dccm/pic/external per pipe stage
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val addr_in_dccm_d = IO(Output(UInt(1.W)))
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val addr_in_dccm_m = IO(Output(UInt(1.W)))
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val addr_in_dccm_r = IO(Output(UInt(1.W)))
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val addr_in_pic_d = IO(Output(UInt(1.W)))
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val addr_in_pic_m = IO(Output(UInt(1.W)))
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val addr_in_pic_r = IO(Output(UInt(1.W)))
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val addr_external_m = IO(Output(UInt(1.W)))
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// DMA slave
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val dma_dccm_req = IO(Input(UInt(1.W)))
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val dma_mem_addr = IO(Input(UInt(32.W)))
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val dma_mem_sz = IO(Input(UInt(3.W)))
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val dma_mem_write = IO(Input(UInt(1.W)))
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val dma_mem_wdata = IO(Input(UInt(64.W)))
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// Store buffer related signals
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val lsu_pkt_d = new el2_lsu_pkt_t()
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val lsu_pkt_m = new el2_lsu_pkt_t()
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val lsu_pkt_r = new el2_lsu_pkt_t()
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val scan_mode = IO(Input(UInt(1.W)))
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val dma_pkt_d = new el2_lsu_pkt_t()
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val lsu_pkt_m_in = new el2_lsu_pkt_t()
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val lsu_pkt_r_in = new el2_lsu_pkt_t()
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val lsu_error_pkt_m = new el2_lsu_error_pkt_t()
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val lsu_rs1_d = Mux(dec_lsu_valid_raw_d.asBool,dec_lsu_valid_raw_d, dec_lsu_valid_raw_d)
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val lsu_offset_d = dec_lsu_offset_d(11,0) & Fill(12,dec_lsu_valid_raw_d)
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val rs1_d_raw = lsu_rs1_d
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val offset_d = lsu_offset_d
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val rs1_d = Mux(lsu_pkt_d.load_ldst_bypass_d.asBool,lsu_result_m,rs1_d_raw)
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val lsadder = new rvlsadder()
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lsadder.io.rs1 := rs1_d
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lsadder.io.offset := offset_d
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val full_addr_d = lsadder.io.dout
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}
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