Update beh_lib.scala
This commit is contained in:
Junaid Ahmed
GitHub
parent
aacb784805
commit
0ef2742e74
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@ -1,7 +1,7 @@
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package lib
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import chisel3._
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import chisel3.util._
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import lib.beh_ib_func._
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//import lib.beh_ib_func._
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class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{
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val io = IO(new Bundle{
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@ -109,7 +109,7 @@ class rvbsadder extends Module{ //Done for verification and testing
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val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
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val start_addr = Wire(UInt(32.W))
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start_addr := CCM_SIZE.U
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start_addr := CCM_SADR.U
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val region = start_addr(31,(32-REGION_BITS))
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io.in_region := (io.addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
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@ -141,12 +141,13 @@ class rvbsadder extends Module{ //Done for verification and testing
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val din = Input(UInt(32.W))
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val ecc_out = Output(UInt(7.W))
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})
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val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1).reverse
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val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1).reverse
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val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0).reverse
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val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0).reverse
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val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0).reverse
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val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0).reverse
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val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
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val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
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val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
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val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
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val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
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val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
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val w0 = Wire(Vec(18,UInt(1.W)))
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val w1 = Wire(Vec(18,UInt(1.W)))
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val w2 = Wire(Vec(18,UInt(1.W)))
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@ -154,7 +155,7 @@ class rvbsadder extends Module{ //Done for verification and testing
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val w4 = Wire(Vec(15,UInt(1.W)))
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val w5 = Wire(Vec(6, UInt(1.W)))
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var j = 0;var k = 0;var m = 0;
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var x = 0;var y = 0;var z = 0
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var x = 0;var y = 0;var z = 0;
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for(i <- 0 to 31)
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{
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@ -165,7 +166,7 @@ class rvbsadder extends Module{ //Done for verification and testing
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if(mask4(i)==1) {w4(y) := io.din(i); y = y +1 }
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if(mask5(i)==1) {w5(z) := io.din(i); z = z +1 }
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}
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val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR))
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val w6 = Cat((w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
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io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6)
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}
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@ -182,6 +183,7 @@ class rvbsadder extends Module{ //Done for verification and testing
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val single_ecc_error = Output(UInt(1.W))
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val double_ecc_error = Output(UInt(1.W))
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})
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val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0).reverse
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val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1).reverse
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val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1).reverse
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@ -344,23 +346,23 @@ class rvbsadder extends Module{ //Done for verification and testing
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}
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}
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////Instantiation example///////////////Can be use if using class instead of function rvdffe
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class my_class extends Module{
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val io = IO(new Bundle {
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val l1clk = Output(Clock())
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val clk = Input(Clock())
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val en = Input(Bool())
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val scan_mode = Input(Bool())
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})
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////rvdffe ///////////////////////////////////////////////////////////////////////
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object rvdffe {
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def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = {
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val obj = Module(new rvclkhdr())
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io.l1clk := obj.io.l1clk
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obj.io.clk := io.clk
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obj.io.en := io.en
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obj.io.scan_mode := io.scan_mode
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val l1clk = obj.io.l1clk
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obj.io.clk := clk
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obj.io.en := en
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obj.io.scan_mode := scan_mode
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withClock(l1clk) {
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RegNext(din, 0.U)
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}
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}
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}
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/////////////rvdffe //////////////////////////
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/*
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class class_rvdffe extends Module{
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val io = IO(new Bundle {
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val in = Input(UInt(32.W))
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@ -371,18 +373,12 @@ class class_rvdffe extends Module{
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})
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io.out := rvdffe(io.in,io.en.asBool,io.clk,io.scan_mode.asBool)
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}
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/*
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object main extends App{
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println("Generate Verilog")
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chisel3.Driver.execute(args, ()=> new rvecc_decode_64)
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chisel3.Driver.execute(args, ()=> new rvrangecheck)
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}
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*/
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/*
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object main extends App{
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chisel3.Driver.execute(args,()=> new my_class)
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}*/
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