Lib updated

.idea/modules/chisel-module-template.iml

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<module external.linked.project.id="design [file:/home/waleedbinehsan/Desktop/Quasar/design/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
+<module external.linked.project.id="quasar [file:/home/waleedbinehsan/Desktop/Quasar/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
   <component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8">
     <output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
     <output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />

dmi_wrapper.sv

@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2018 Western Digital Corporation or it's affiliates.
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// 
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//------------------------------------------------------------------------------------
+//
+//  Copyright Western Digital, 2018
+//  Owner : Anusha Narayanamoorthy
+//  Description:  
+//                Wrapper module for JTAG_TAP and DMI synchronizer
+//
+//-------------------------------------------------------------------------------------
+
+module dmi_wrapper(
+
+  // JTAG signals
+  input              trst_n,              // JTAG reset
+  input              tck,                 // JTAG clock
+  input              tms,                 // Test mode select   
+  input              tdi,                 // Test Data Input
+  output             tdo,                 // Test Data Output           
+  output             tdoEnable,           // Test Data Output enable             
+
+  // Processor Signals
+  input              core_rst_n,          // Core reset                  
+  input              core_clk,            // Core clock                  
+  input [31:1]       jtag_id,             // JTAG ID
+  input [31:0]       rd_data,             // 32 bit Read data from  Processor                       
+  output [31:0]      reg_wr_data,         // 32 bit Write data to Processor                      
+  output [6:0]       reg_wr_addr,         // 7 bit reg address to Processor                   
+  output             reg_en,              // 1 bit  Read enable to Processor                                    
+  output             reg_wr_en,           // 1 bit  Write enable to Processor 
+  output             dmi_hard_reset  
+);
+
+
+  
+
+
+  //Wire Declaration
+  wire                     rd_en;
+  wire                     wr_en;
+  wire                     dmireset;
+
+ 
+  //jtag_tap instantiation
+ rvjtag_tap i_jtag_tap(
+   .trst(trst_n),                      // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
+   .tck(tck),                          // dedicated JTAG TCK pad signal
+   .tms(tms),                          // dedicated JTAG TMS pad signal
+   .tdi(tdi),                          // dedicated JTAG TDI pad signal
+   .tdo(tdo),                          // dedicated JTAG TDO pad signal
+   .tdoEnable(tdoEnable),              // enable for TDO pad
+   .wr_data(reg_wr_data),              // 32 bit Write data
+   .wr_addr(reg_wr_addr),              // 7 bit Write address
+   .rd_en(rd_en),                      // 1 bit  read enable
+   .wr_en(wr_en),                      // 1 bit  Write enable
+   .rd_data(rd_data),                  // 32 bit Read data
+   .rd_status(2'b0),
+   .idle(3'h0),                         // no need to wait to sample data
+   .dmi_stat(2'b0),                     // no need to wait or error possible
+   .version(4'h1),                      // debug spec 0.13 compliant
+   .jtag_id(jtag_id),
+   .dmi_hard_reset(dmi_hard_reset),
+   .dmi_reset(dmireset)
+);
+
+
+  // dmi_jtag_to_core_sync instantiation
+  dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
+    .wr_en(wr_en),                          // 1 bit  Write enable
+    .rd_en(rd_en),                          // 1 bit  Read enable
+
+    .rst_n(core_rst_n),
+    .clk(core_clk),
+    .reg_en(reg_en),                          // 1 bit  Write interface bit
+    .reg_wr_en(reg_wr_en)                          // 1 bit  Write enable
+  );
+
+endmodule

firrtl_black_box_resource_files.f

@@ -0,0 +1,3 @@
+/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
+/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
+/home/waleedbinehsan/Desktop/Quasar/mem.sv

gated_latch.v

@@ -0,0 +1,14 @@
+module gated_latch
+  (
+   input wire SE, EN, CK,
+   output Q
+   );
+   reg  en_ff;
+   wire  enable;
+   assign      enable = EN | SE;
+  always @(CK, enable) begin
+      if(!CK)
+        en_ff = enable;
+   end
+   assign Q = CK & en_ff;
+endmodule

mem.sv

@@ -0,0 +1,173 @@
+
+module mem #(
+   parameter ICACHE_BEAT_BITS,
+   parameter ICCM_BITS,
+   parameter ICACHE_NUM_WAYS,
+   parameter DCCM_BYTE_WIDTH,
+   parameter ICCM_BANK_INDEX_LO,
+   parameter ICACHE_BANK_BITS,
+   parameter DCCM_BITS,
+   parameter ICACHE_BEAT_ADDR_HI,
+   parameter ICCM_INDEX_BITS,
+   parameter ICCM_BANK_HI,
+   parameter ICACHE_BANKS_WAY,
+   parameter ICACHE_INDEX_HI,
+   parameter DCCM_NUM_BANKS,
+   parameter ICACHE_BANK_HI,
+   parameter ICACHE_BANK_LO,
+   parameter DCCM_ENABLE= 'b1,
+   parameter ICACHE_TAG_LO,
+   parameter ICACHE_DATA_INDEX_LO,
+   parameter ICCM_NUM_BANKS,
+   parameter ICACHE_ECC,
+   parameter ICACHE_ENABLE= 'b1,
+   parameter DCCM_BANK_BITS,
+   parameter ICCM_ENABLE= 'b1,
+   parameter ICCM_BANK_BITS,
+   parameter ICACHE_TAG_DEPTH,
+   parameter ICACHE_WAYPACK,
+   parameter DCCM_SIZE,
+   parameter DCCM_FDATA_WIDTH,
+   parameter ICACHE_TAG_INDEX_LO,
+   parameter ICACHE_DATA_DEPTH)
+(
+   input logic         clk,
+   input logic         rst_l,
+   input logic         dccm_clk_override,
+   input logic         icm_clk_override,
+   input logic         dec_tlu_core_ecc_disable,
+
+   //DCCM ports
+   input logic         dccm_wren,
+   input logic         dccm_rden,
+   input logic [DCCM_BITS-1:0]  dccm_wr_addr_lo,
+   input logic [DCCM_BITS-1:0]  dccm_wr_addr_hi,
+   input logic [DCCM_BITS-1:0]  dccm_rd_addr_lo,
+   input logic [DCCM_BITS-1:0]  dccm_rd_addr_hi,
+   input logic [DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,
+   input logic [DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,
+
+
+   output logic [DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_lo,
+   output logic [DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_hi,
+
+//`ifdef DCCM_ENABLE
+
+//`endif
+
+   //ICCM ports
+
+   input logic [ICCM_BITS-1:1]  iccm_rw_addr,
+   input logic                                        iccm_buf_correct_ecc,                    // ICCM is doing a single bit error correct cycle
+   input logic                                        iccm_correction_state,               // ICCM is doing a single bit error correct cycle
+   input logic         iccm_wren,
+   input logic         iccm_rden,
+   input logic [2:0]   iccm_wr_size,
+   input logic [77:0]  iccm_wr_data,
+
+   output logic [63:0] iccm_rd_data,
+   output logic [77:0] iccm_rd_data_ecc,
+
+   // Icache and Itag Ports
+
+   input  logic [31:1]  ic_rw_addr,
+   input  logic [ICACHE_NUM_WAYS-1:0]   ic_tag_valid,
+   input  logic [ICACHE_NUM_WAYS-1:0]   ic_wr_en,
+   input  logic         ic_rd_en,
+   input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
+   input  logic         ic_sel_premux_data, // Premux data sel
+
+   input  logic [70:0]               ic_wr_data_0,         // Data to fill to the Icache. With ECC
+	input  logic [70:0]               ic_wr_data_1,
+	input  logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
+   output logic [70:0]               ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+   input  logic [ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
+   input  logic                      ic_debug_rd_en,     // Icache debug rd
+   input  logic                      ic_debug_wr_en,     // Icache debug wr
+   input  logic                      ic_debug_tag_array, // Debug tag array
+   input  logic [ICACHE_NUM_WAYS-1:0]                ic_debug_way,       // Debug way. Rd or Wr.
+
+   output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
+   output logic [25:0]               ic_tag_debug_rd_data,// Debug icache tag.
+
+
+   output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr,    // ecc error per bank
+   output logic [ICACHE_BANKS_WAY-1:0] ic_parerr,          // parity error per bank
+   output logic [ICACHE_NUM_WAYS-1:0]   ic_rd_hit,
+   output logic         ic_tag_perr,        // Icache Tag parity error
+
+
+   input  logic         scan_mode
+
+);
+
+	logic [ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
+assign ic_wr_data [0] = ic_wr_data_0;
+assign ic_wr_data [1] = ic_wr_data_1;
+   // DCCM Instantiation
+   if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
+      lsu_dccm_mem #(
+   .DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
+   .DCCM_BITS(DCCM_BITS),
+   .DCCM_NUM_BANKS(DCCM_NUM_BANKS),
+   .DCCM_BANK_BITS(DCCM_BANK_BITS),
+   .DCCM_SIZE(DCCM_SIZE),
+   .DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
+         .clk_override(dccm_clk_override),
+         .*
+      );
+   end else begin: Gen_dccm_disable
+      assign dccm_rd_data_lo = '0;
+      assign dccm_rd_data_hi = '0;
+   end
+
+if ( ICACHE_ENABLE ) begin: icache
+   ifu_ic_mem #(
+   .ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
+   .ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
+   .ICACHE_BANK_BITS(ICACHE_BANK_BITS),
+   .ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
+   .ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
+   .ICACHE_INDEX_HI(ICACHE_INDEX_HI),
+   .ICACHE_BANK_HI(ICACHE_BANK_HI),
+   .ICACHE_BANK_LO(ICACHE_BANK_LO),
+   .ICACHE_TAG_LO(ICACHE_TAG_LO),
+   .ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
+   .ICACHE_ECC(ICACHE_ECC),
+   .ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
+   .ICACHE_WAYPACK(ICACHE_WAYPACK),
+   .ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
+   .ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm  (
+      .clk_override(icm_clk_override),
+      .*
+   );
+end
+else  begin
+   assign   ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
+   assign   ic_tag_perr    = '0 ;
+   assign   ic_rd_data  = '0 ;
+   assign   ic_tag_debug_rd_data  = '0 ;
+end // else: !if( ICACHE_ENABLE )
+
+
+
+if (ICCM_ENABLE) begin : iccm
+   ifu_iccm_mem  #(
+   .ICCM_BITS(ICCM_BITS),
+   .ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
+   .ICCM_INDEX_BITS(ICCM_INDEX_BITS),
+   .ICCM_BANK_HI(ICCM_BANK_HI),
+   .ICCM_NUM_BANKS(ICCM_NUM_BANKS),
+   .ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
+                  .clk_override(icm_clk_override),
+                  .iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
+                  .iccm_rd_data(iccm_rd_data[63:0])
+                   );
+end
+else  begin
+   assign  iccm_rd_data    = '0 ;
+   assign iccm_rd_data_ecc = '0 ;
+end
+
+
+endmodule

project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs

@@ -1 +1 @@
--1641150927
+38779017

project/target/streams/_global/update/_global/streams/out

@@ -1,3 +1,3 @@
 [debug] "not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/design/project/"), "design-build")...
+[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")...
-[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/design/project/"), "design-build")
+[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")

project/target/streams/compile/_global/_global/compileOutputs/previous

@@ -1 +1 @@
-["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/Quasar/design/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]
+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/Quasar/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]

project/target/streams/compile/exportedProducts/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/design/project/target/scala-2.12/sbt-1.0/classes
+/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes

project/target/streams/runtime/dependencyClasspath/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/design/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
+/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes

project/target/streams/runtime/exportedProducts/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/design/project/target/scala-2.12/sbt-1.0/classes
+/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes

project/target/streams/runtime/fullClasspath/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/design/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
+/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes

project/target/streams/runtime/internalDependencyClasspath/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/design/project/target/scala-2.12/sbt-1.0/classes
+/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes

src/main/scala/lib/lib.scala

@@ -16,7 +16,7 @@ trait lib extends param{
   def flip(tag: Int , ahb_type: Boolean) = if(ahb_type) Flipped(new axi_channels(tag)) else new axi_channels(tag)
 
   def ahb_bridge_gen(ahb_type: Boolean) = if(ahb_type) new Bundle{
-    val ahb= Flipped(new ahb_channel())
+    val sig = Flipped(new ahb_channel())
     val hsel = Input(Bool())
     val hreadyin = Input(Bool())}
   else new ahb_channel()

src/main/scala/lib/param.scala

@@ -22,7 +22,7 @@ trait param {
   val BTB_INDEX3_LO          = 	0x12
   val BTB_SIZE               = 	0x200
   val BUILD_AHB_LITE         = 	0x0
-  val BUILD_AXI4             = 	0x1
+  val BUILD_AXI4             = 	0x0
   val BUILD_AXI_NATIVE       = 	0x1
   val BUS_PRTY_DEFAULT       = 	0x3
   val DATA_ACCESS_ADDR0      = 	0x00000000

target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous

@@ -1 +1 @@
-["sbt.Task[scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]",{"hashes":[["/home/waleedbinehsan/Desktop/Quasar/design/build.sbt","a7487a9519e56bfaf46b5c1967a665ac0baa0b73"],["/home/waleedbinehsan/Desktop/Quasar/design/project/plugins.sbt","361bf1247779b42e03c86deb53015d6b2c401dac"]],"lastModifiedTimes":[]}]
+["sbt.Task[scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]",{"hashes":[["/home/waleedbinehsan/Desktop/Quasar/build.sbt","a7487a9519e56bfaf46b5c1967a665ac0baa0b73"],["/home/waleedbinehsan/Desktop/Quasar/project/plugins.sbt","361bf1247779b42e03c86deb53015d6b2c401dac"]],"lastModifiedTimes":[]}]

target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp

@@ -1 +1 @@
-{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.scalamacros\",\"name\":\"paradise\",\"revision\":\"2.1.0\",\"configurations\":\"plugin->default(compile)\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Full\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/waleedbinehsan/Desktop/Quasar/design/build.sbt","range":{"$fields":["start","end"],"start":42,"end":43}},"type":"RangePosition"},"{\"organization\":\"edu.berkeley.cs\",\"name\":\"chisel-iotesters\",\"revision\":\"1.4.1+\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Binary\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/waleedbinehsan/Desktop/Quasar/design/build.sbt","range":{"$fields":["start","end"],"start":50,"end":52}},"type":"RangePosition"},"{\"organization\":\"edu.berkeley.cs\",\"name\":\"chiseltest\",\"revision\":\"0.2.1+\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Binary\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/waleedbinehsan/Desktop/Quasar/design/build.sbt","range":{"$fields":["start","end"],"start":50,"end":52}},"type":"RangePosition"}}
+{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.scalamacros\",\"name\":\"paradise\",\"revision\":\"2.1.0\",\"configurations\":\"plugin->default(compile)\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Full\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/waleedbinehsan/Desktop/Quasar/build.sbt","range":{"$fields":["start","end"],"start":42,"end":43}},"type":"RangePosition"},"{\"organization\":\"edu.berkeley.cs\",\"name\":\"chisel-iotesters\",\"revision\":\"1.4.1+\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Binary\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/waleedbinehsan/Desktop/Quasar/build.sbt","range":{"$fields":["start","end"],"start":50,"end":52}},"type":"RangePosition"},"{\"organization\":\"edu.berkeley.cs\",\"name\":\"chiseltest\",\"revision\":\"0.2.1+\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Binary\",\"prefix\":\"\",\"suffix\":\"\"}}":{"value":{"$fields":["path","range"],"path":"/home/waleedbinehsan/Desktop/Quasar/build.sbt","range":{"$fields":["start","end"],"start":50,"end":52}},"type":"RangePosition"}}