diff --git a/dbg.fir b/dbg.fir index d3ba81c9..6a3a7890 100644 --- a/dbg.fir +++ b/dbg.fir @@ -144,6 +144,54 @@ circuit dbg : clkhdr.EN <= io.en @[lib.scala 321:18] clkhdr.SE <= io.scan_mode @[lib.scala 322:18] + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 318:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 319:14] + clkhdr.CK <= io.clk @[lib.scala 320:18] + clkhdr.EN <= io.en @[lib.scala 321:18] + clkhdr.SE <= io.scan_mode @[lib.scala 322:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 318:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 319:14] + clkhdr.CK <= io.clk @[lib.scala 320:18] + clkhdr.EN <= io.en @[lib.scala 321:18] + clkhdr.SE <= io.scan_mode @[lib.scala 322:18] + module dbg : input clock : Clock input reset : AsyncReset @@ -640,10 +688,14 @@ circuit dbg : node command_din = cat(_T_300, _T_298) @[Cat.scala 29:58] node _T_301 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 237:32] node _T_302 = asAsyncReset(_T_301) @[dbg.scala 237:59] - reg command_reg : UInt, clock with : (reset => (_T_302, UInt<1>("h00"))) @[Reg.scala 27:20] - when command_wren : @[Reg.scala 28:19] - command_reg <= command_din @[Reg.scala 28:23] - skip @[Reg.scala 28:19] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 352:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= _T_302 + rvclkhdr_5.io.clk <= clock @[lib.scala 354:18] + rvclkhdr_5.io.en <= command_wren @[lib.scala 355:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] + reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_302, UInt<1>("h00"))) @[lib.scala 358:16] + command_reg <= command_din @[lib.scala 358:16] node _T_303 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 241:39] node _T_304 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 241:77] node _T_305 = and(_T_303, _T_304) @[dbg.scala 241:58] @@ -664,10 +716,14 @@ circuit dbg : node data0_din = or(_T_313, _T_316) @[dbg.scala 245:64] node _T_317 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 246:30] node _T_318 = asAsyncReset(_T_317) @[dbg.scala 246:57] - reg data0_reg : UInt, clock with : (reset => (_T_318, UInt<1>("h00"))) @[Reg.scala 27:20] - when data0_reg_wren : @[Reg.scala 28:19] - data0_reg <= data0_din @[Reg.scala 28:23] - skip @[Reg.scala 28:19] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 352:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= _T_318 + rvclkhdr_6.io.clk <= clock @[lib.scala 354:18] + rvclkhdr_6.io.en <= data0_reg_wren @[lib.scala 355:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 356:24] + reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (_T_318, UInt<1>("h00"))) @[lib.scala 358:16] + data0_reg <= data0_din @[lib.scala 358:16] node _T_319 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 250:39] node _T_320 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 250:77] node _T_321 = and(_T_319, _T_320) @[dbg.scala 250:58] @@ -678,13 +734,13 @@ circuit dbg : node data1_din = and(_T_324, io.dmi_reg_wdata) @[dbg.scala 251:44] node _T_325 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 252:27] node _T_326 = asAsyncReset(_T_325) @[dbg.scala 252:54] - inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 352:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= _T_326 - rvclkhdr_5.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_5.io.en <= data1_reg_wren @[lib.scala 355:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_327 : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_326, UInt<1>("h00"))) @[lib.scala 358:16] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 352:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= _T_326 + rvclkhdr_7.io.clk <= clock @[lib.scala 354:18] + rvclkhdr_7.io.en <= data1_reg_wren @[lib.scala 355:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 356:24] + reg _T_327 : UInt, rvclkhdr_7.io.l1clk with : (reset => (_T_326, UInt<1>("h00"))) @[lib.scala 358:16] _T_327 <= data1_din @[lib.scala 358:16] data1_reg <= _T_327 @[dbg.scala 252:13] wire dbg_nxtstate : UInt<3> diff --git a/dbg.v b/dbg.v index 3d32b5ff..6a4fd9a3 100644 --- a/dbg.v +++ b/dbg.v @@ -344,29 +344,36 @@ module dbg( wire [20:0] _T_289 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58] wire _T_294 = dbg_state == 3'h2; // @[dbg.scala 235:100] wire command_wren = _T_235 & _T_294; // @[dbg.scala 235:87] - wire [31:0] command_din = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20],3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] - reg [31:0] command_reg; // @[Reg.scala 27:20] + wire [19:0] _T_298 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] + wire [11:0] _T_300 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 352:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 352:23] + wire rvclkhdr_5_io_en; // @[lib.scala 352:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 352:23] + reg [31:0] command_reg; // @[lib.scala 358:16] wire _T_305 = _T_87 & _T_217; // @[dbg.scala 241:58] wire data0_reg_wren0 = _T_305 & _T_294; // @[dbg.scala 241:89] wire _T_307 = dbg_state == 3'h4; // @[dbg.scala 242:59] wire _T_308 = io_core_dbg_cmd_done & _T_307; // @[dbg.scala 242:46] wire _T_310 = ~command_reg[16]; // @[dbg.scala 242:83] wire data0_reg_wren1 = _T_308 & _T_310; // @[dbg.scala 242:81] - wire data0_reg_wren = data0_reg_wren0 | data0_reg_wren1; // @[dbg.scala 244:40] wire [31:0] _T_312 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_313 = _T_312 & io_dmi_reg_wdata; // @[dbg.scala 245:45] wire [31:0] _T_315 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_316 = _T_315 & io_core_dbg_rddata; // @[dbg.scala 245:92] - wire [31:0] data0_din = _T_313 | _T_316; // @[dbg.scala 245:64] - reg [31:0] data0_reg; // @[Reg.scala 27:20] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 352:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 352:23] + wire rvclkhdr_6_io_en; // @[lib.scala 352:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 352:23] + reg [31:0] data0_reg; // @[lib.scala 358:16] wire _T_320 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 250:77] wire _T_321 = _T_87 & _T_320; // @[dbg.scala 250:58] wire data1_reg_wren = _T_321 & _T_294; // @[dbg.scala 250:89] wire [31:0] _T_324 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 352:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 352:23] - wire rvclkhdr_5_io_en; // @[lib.scala 352:23] - wire rvclkhdr_5_io_scan_mode; // @[lib.scala 352:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 352:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 352:23] + wire rvclkhdr_7_io_en; // @[lib.scala 352:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 352:23] reg [31:0] _T_327; // @[lib.scala 358:16] wire [2:0] dbg_nxtstate; wire _T_328 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] @@ -414,30 +421,30 @@ module dbg( wire _T_424 = 3'h5 == dbg_state; // @[Conditional.scala 37:30] wire _T_433 = 3'h6 == dbg_state; // @[Conditional.scala 37:30] wire _T_436 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 304:40] - wire _GEN_13 = _T_433 & _T_436; // @[Conditional.scala 39:67] - wire _GEN_14 = _T_433 & _T_356; // @[Conditional.scala 39:67] - wire [2:0] _GEN_15 = _T_424 ? _T_348 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_424 | _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_17 = _T_424 & dbg_state_en; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_424 ? _T_356 : _GEN_14; // @[Conditional.scala 39:67] - wire [2:0] _GEN_20 = _T_413 ? _T_415 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_413 ? _T_417 : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_413 ? _T_356 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_23 = _T_413 ? 1'h0 : _GEN_17; // @[Conditional.scala 39:67] - wire [2:0] _GEN_25 = _T_396 ? _T_401 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_396 ? _T_406 : _GEN_21; // @[Conditional.scala 39:67] - wire _GEN_27 = _T_396 ? _T_356 : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_396 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire [2:0] _GEN_30 = _T_358 ? _T_370 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_358 ? _T_384 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_358 ? _T_386 : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_34 = _T_358 & _T_388; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_358 ? _T_356 : _GEN_27; // @[Conditional.scala 39:67] - wire [2:0] _GEN_36 = _T_346 ? _T_348 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_37 = _T_346 ? _T_351 : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_346 ? _T_356 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_11 = _T_433 & _T_436; // @[Conditional.scala 39:67] + wire _GEN_12 = _T_433 & _T_356; // @[Conditional.scala 39:67] + wire [2:0] _GEN_13 = _T_424 ? _T_348 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_14 = _T_424 | _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_15 = _T_424 & dbg_state_en; // @[Conditional.scala 39:67] + wire _GEN_17 = _T_424 ? _T_356 : _GEN_12; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_413 ? _T_415 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_413 ? _T_417 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_413 ? _T_356 : _GEN_17; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_413 ? 1'h0 : _GEN_15; // @[Conditional.scala 39:67] + wire [2:0] _GEN_23 = _T_396 ? _T_401 : _GEN_18; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_396 ? _T_406 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_25 = _T_396 ? _T_356 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_396 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire [2:0] _GEN_28 = _T_358 ? _T_370 : _GEN_23; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_358 ? _T_384 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_358 ? _T_386 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_358 & _T_388; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_358 ? _T_356 : _GEN_25; // @[Conditional.scala 39:67] + wire [2:0] _GEN_34 = _T_346 ? _T_348 : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_346 ? _T_351 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_346 ? _T_356 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_346 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] wire _GEN_39 = _T_346 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_346 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] wire [31:0] _T_445 = _T_217 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_446 = _T_445 & data0_reg; // @[dbg.scala 308:71] wire [31:0] _T_449 = _T_320 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] @@ -489,8 +496,8 @@ module dbg( wire _T_540 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 346:65] wire _T_541 = sbcs_wren & _T_540; // @[dbg.scala 346:38] wire _T_543 = io_dmi_reg_wdata[14:12] == 3'h0; // @[dbg.scala 347:27] - wire [2:0] _GEN_118 = {{2'd0}, _T_543}; // @[dbg.scala 347:53] - wire [2:0] _T_545 = _GEN_118 & sbcs_reg[14:12]; // @[dbg.scala 347:53] + wire [2:0] _GEN_116 = {{2'd0}, _T_543}; // @[dbg.scala 347:53] + wire [2:0] _T_545 = _GEN_116 & sbcs_reg[14:12]; // @[dbg.scala 347:53] wire _T_546 = 4'h1 == sb_state; // @[Conditional.scala 37:30] wire _T_547 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 350:41] wire _T_549 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 351:40] @@ -512,39 +519,39 @@ module dbg( wire _T_575 = 4'h8 == sb_state; // @[Conditional.scala 37:30] wire _T_576 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 385:39] wire _T_578 = 4'h9 == sb_state; // @[Conditional.scala 37:30] - wire _GEN_53 = _T_578 & sbcs_reg[16]; // @[Conditional.scala 39:67] - wire _GEN_55 = _T_575 ? _T_576 : _T_578; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_575 & _T_574; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_575 ? 1'h0 : _T_578; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_575 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_572 ? _T_573 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_572 ? _T_574 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_51 = _T_578 & sbcs_reg[16]; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_575 ? _T_576 : _T_578; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_575 & _T_574; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_575 ? 1'h0 : _T_578; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_575 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_572 ? _T_573 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_572 ? _T_574 : _GEN_54; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_572 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] wire _GEN_65 = _T_572 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_572 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_570 ? _T_571 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_570 ? _T_571 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_570 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] wire _GEN_70 = _T_570 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] wire _GEN_72 = _T_570 ? 1'h0 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_570 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67] - wire _GEN_76 = _T_568 ? _T_569 : _GEN_69; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_568 ? _T_569 : _GEN_67; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_568 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67] wire _GEN_77 = _T_568 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] wire _GEN_79 = _T_568 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_568 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_562 ? _T_567 : _GEN_76; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_562 ? _T_567 : _GEN_74; // @[Conditional.scala 39:67] + wire _GEN_82 = _T_562 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67] wire _GEN_84 = _T_562 ? 1'h0 : _GEN_77; // @[Conditional.scala 39:67] wire _GEN_86 = _T_562 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_562 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire _GEN_90 = _T_560 ? _T_561 : _GEN_83; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_560 ? _T_561 : _GEN_81; // @[Conditional.scala 39:67] + wire _GEN_89 = _T_560 ? 1'h0 : _GEN_82; // @[Conditional.scala 39:67] wire _GEN_91 = _T_560 ? 1'h0 : _GEN_84; // @[Conditional.scala 39:67] wire _GEN_93 = _T_560 ? 1'h0 : _GEN_86; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_560 ? 1'h0 : _GEN_88; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_553 ? _T_550 : _GEN_90; // @[Conditional.scala 39:67] - wire _GEN_98 = _T_553 ? _T_547 : _GEN_91; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_553 ? _T_550 : _GEN_88; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_553 ? _T_547 : _GEN_89; // @[Conditional.scala 39:67] + wire _GEN_98 = _T_553 ? 1'h0 : _GEN_91; // @[Conditional.scala 39:67] wire _GEN_100 = _T_553 ? 1'h0 : _GEN_93; // @[Conditional.scala 39:67] - wire _GEN_102 = _T_553 ? 1'h0 : _GEN_95; // @[Conditional.scala 39:67] - wire _GEN_104 = _T_546 ? _T_550 : _GEN_97; // @[Conditional.scala 39:67] - wire _GEN_105 = _T_546 ? _T_547 : _GEN_98; // @[Conditional.scala 39:67] + wire _GEN_102 = _T_546 ? _T_550 : _GEN_95; // @[Conditional.scala 39:67] + wire _GEN_103 = _T_546 ? _T_547 : _GEN_96; // @[Conditional.scala 39:67] + wire _GEN_105 = _T_546 ? 1'h0 : _GEN_98; // @[Conditional.scala 39:67] wire _GEN_107 = _T_546 ? 1'h0 : _GEN_100; // @[Conditional.scala 39:67] - wire _GEN_109 = _T_546 ? 1'h0 : _GEN_102; // @[Conditional.scala 39:67] reg [3:0] _T_582; // @[Reg.scala 27:20] wire _T_589 = |io_sb_axi_r_bits_resp; // @[dbg.scala 406:69] wire _T_590 = sb_bus_rsp_read & _T_589; // @[dbg.scala 406:39] @@ -569,37 +576,37 @@ module dbg( wire [63:0] _T_638 = _T_634 & _T_637; // @[dbg.scala 420:119] wire [7:0] _T_643 = _T_66 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [14:0] _T_645 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 422:82] - wire [14:0] _GEN_119 = {{7'd0}, _T_643}; // @[dbg.scala 422:67] - wire [14:0] _T_646 = _GEN_119 & _T_645; // @[dbg.scala 422:67] + wire [14:0] _GEN_117 = {{7'd0}, _T_643}; // @[dbg.scala 422:67] + wire [14:0] _T_646 = _GEN_117 & _T_645; // @[dbg.scala 422:67] wire [7:0] _T_650 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [2:0] _T_652 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] wire [14:0] _T_653 = 15'h3 << _T_652; // @[dbg.scala 423:59] - wire [14:0] _GEN_120 = {{7'd0}, _T_650}; // @[dbg.scala 423:44] - wire [14:0] _T_654 = _GEN_120 & _T_653; // @[dbg.scala 423:44] + wire [14:0] _GEN_118 = {{7'd0}, _T_650}; // @[dbg.scala 423:44] + wire [14:0] _T_654 = _GEN_118 & _T_653; // @[dbg.scala 423:44] wire [14:0] _T_655 = _T_646 | _T_654; // @[dbg.scala 422:107] wire [7:0] _T_659 = _T_55 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_661 = {sbaddress0_reg[2],1'h0}; // @[Cat.scala 29:58] wire [10:0] _T_662 = 11'hf << _T_661; // @[dbg.scala 424:59] - wire [10:0] _GEN_121 = {{3'd0}, _T_659}; // @[dbg.scala 424:44] - wire [10:0] _T_663 = _GEN_121 & _T_662; // @[dbg.scala 424:44] - wire [14:0] _GEN_122 = {{4'd0}, _T_663}; // @[dbg.scala 423:97] - wire [14:0] _T_664 = _T_655 | _GEN_122; // @[dbg.scala 423:97] + wire [10:0] _GEN_119 = {{3'd0}, _T_659}; // @[dbg.scala 424:44] + wire [10:0] _T_663 = _GEN_119 & _T_662; // @[dbg.scala 424:44] + wire [14:0] _GEN_120 = {{4'd0}, _T_663}; // @[dbg.scala 423:97] + wire [14:0] _T_664 = _T_655 | _GEN_120; // @[dbg.scala 423:97] wire [7:0] _T_668 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [14:0] _GEN_123 = {{7'd0}, _T_668}; // @[dbg.scala 424:95] - wire [14:0] _T_670 = _T_664 | _GEN_123; // @[dbg.scala 424:95] - wire [3:0] _GEN_124 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99] - wire [6:0] _T_681 = 4'h8 * _GEN_124; // @[dbg.scala 441:99] + wire [14:0] _GEN_121 = {{7'd0}, _T_668}; // @[dbg.scala 424:95] + wire [14:0] _T_670 = _T_664 | _GEN_121; // @[dbg.scala 424:95] + wire [3:0] _GEN_122 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99] + wire [6:0] _T_681 = 4'h8 * _GEN_122; // @[dbg.scala 441:99] wire [63:0] _T_682 = io_sb_axi_r_bits_data >> _T_681; // @[dbg.scala 441:92] wire [63:0] _T_683 = _T_682 & 64'hff; // @[dbg.scala 441:123] wire [63:0] _T_684 = _T_608 & _T_683; // @[dbg.scala 441:59] - wire [4:0] _GEN_125 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86] - wire [6:0] _T_691 = 5'h10 * _GEN_125; // @[dbg.scala 442:86] + wire [4:0] _GEN_123 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86] + wire [6:0] _T_691 = 5'h10 * _GEN_123; // @[dbg.scala 442:86] wire [63:0] _T_692 = io_sb_axi_r_bits_data >> _T_691; // @[dbg.scala 442:78] wire [63:0] _T_693 = _T_692 & 64'hffff; // @[dbg.scala 442:110] wire [63:0] _T_694 = _T_617 & _T_693; // @[dbg.scala 442:45] wire [63:0] _T_695 = _T_684 | _T_694; // @[dbg.scala 441:140] - wire [5:0] _GEN_126 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86] - wire [6:0] _T_702 = 6'h20 * _GEN_126; // @[dbg.scala 443:86] + wire [5:0] _GEN_124 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86] + wire [6:0] _T_702 = 6'h20 * _GEN_124; // @[dbg.scala 443:86] wire [63:0] _T_703 = io_sb_axi_r_bits_data >> _T_702; // @[dbg.scala 443:78] wire [63:0] _T_704 = _T_703 & 64'hffffffff; // @[dbg.scala 443:107] wire [63:0] _T_705 = _T_626 & _T_704; // @[dbg.scala 443:45] @@ -641,10 +648,22 @@ module dbg( .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 352:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 352:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 329:19] assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 100:21] - assign io_dbg_halt_req = _T_328 ? _T_344 : _GEN_38; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23] - assign io_dbg_resume_req = _T_328 ? 1'h0 : _GEN_41; // @[dbg.scala 262:21 dbg.scala 282:25] + assign io_dbg_halt_req = _T_328 ? _T_344 : _GEN_36; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23] + assign io_dbg_resume_req = _T_328 ? 1'h0 : _GEN_39; // @[dbg.scala 262:21 dbg.scala 282:25] assign io_dmi_reg_rdata = _T_502; // @[dbg.scala 320:20] assign io_sb_axi_aw_valid = _T_595 | _T_596; // @[dbg.scala 407:22] assign io_sb_axi_aw_bits_id = 1'h0; // @[dbg.scala 409:24] @@ -686,22 +705,22 @@ module dbg( assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 448:39] assign io_dbg_dma_io_dbg_dma_bubble = _T_515 | _T_307; // @[dbg.scala 330:32] assign dbg_state = _T_499; // @[dbg.scala 315:13] - assign dbg_state_en = _T_328 ? _T_340 : _GEN_37; // @[dbg.scala 258:16 dbg.scala 266:20 dbg.scala 271:20 dbg.scala 278:20 dbg.scala 287:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 304:20] + assign dbg_state_en = _T_328 ? _T_340 : _GEN_35; // @[dbg.scala 258:16 dbg.scala 266:20 dbg.scala 271:20 dbg.scala 278:20 dbg.scala 287:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 304:20] assign sb_state = _T_582; // @[dbg.scala 397:12] - assign sb_state_en = _T_535 ? _T_538 : _GEN_104; // @[dbg.scala 343:19 dbg.scala 351:19 dbg.scala 357:19 dbg.scala 363:19 dbg.scala 367:19 dbg.scala 371:19 dbg.scala 375:19 dbg.scala 379:19 dbg.scala 385:19 dbg.scala 391:19] + assign sb_state_en = _T_535 ? _T_538 : _GEN_102; // @[dbg.scala 343:19 dbg.scala 351:19 dbg.scala 357:19 dbg.scala 363:19 dbg.scala 367:19 dbg.scala 371:19 dbg.scala 375:19 dbg.scala 379:19 dbg.scala 385:19 dbg.scala 391:19] assign dmcontrol_reg = {_T_157,_T_155}; // @[dbg.scala 178:17] assign sbaddress0_reg = _T_128; // @[dbg.scala 159:18] - assign sbcs_sbbusy_wren = _T_535 ? sb_state_en : _GEN_107; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24] - assign sbcs_sberror_wren = _T_535 ? _T_541 : _GEN_105; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25] + assign sbcs_sbbusy_wren = _T_535 ? sb_state_en : _GEN_105; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24] + assign sbcs_sberror_wren = _T_535 ? _T_541 : _GEN_103; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25] assign sb_bus_rdata = _T_706 | _T_712; // @[dbg.scala 441:16] - assign sbaddress0_reg_wren1 = _T_535 ? 1'h0 : _GEN_109; // @[dbg.scala 339:24 dbg.scala 394:28] + assign sbaddress0_reg_wren1 = _T_535 ? 1'h0 : _GEN_107; // @[dbg.scala 339:24 dbg.scala 394:28] assign dmstatus_reg = {_T_177,_T_173}; // @[dbg.scala 184:16] assign dmstatus_havereset = _T_210; // @[dbg.scala 201:22] assign dmstatus_resumeack = _T_201; // @[dbg.scala 193:22] assign dmstatus_unavail = dmcontrol_reg[1] | _T_194; // @[dbg.scala 191:20] assign dmstatus_running = ~_T_197; // @[dbg.scala 192:20] assign dmstatus_halted = _T_206; // @[dbg.scala 197:19] - assign abstractcs_busy_wren = _T_328 ? 1'h0 : _GEN_39; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28] + assign abstractcs_busy_wren = _T_328 ? 1'h0 : _GEN_37; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28] assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 401:19] assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 402:25] assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 403:25] @@ -728,9 +747,15 @@ module dbg( assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign abstractcs_reg = {_T_289,_T_287}; // @[dbg.scala 233:18] assign rvclkhdr_5_io_clk = clock; // @[lib.scala 354:18] - assign rvclkhdr_5_io_en = _T_321 & _T_294; // @[lib.scala 355:17] + assign rvclkhdr_5_io_en = _T_235 & _T_294; // @[lib.scala 355:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] - assign dbg_nxtstate = _T_328 ? _T_331 : _GEN_36; // @[dbg.scala 257:16 dbg.scala 265:20 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 286:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 303:20] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 354:18] + assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[lib.scala 355:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 354:18] + assign rvclkhdr_7_io_en = _T_321 & _T_294; // @[lib.scala 355:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] + assign dbg_nxtstate = _T_328 ? _T_331 : _GEN_34; // @[dbg.scala 257:16 dbg.scala 265:20 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 286:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 303:20] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -1029,21 +1054,21 @@ end // initial abs_temp_10_8 <= _T_276 | _T_281; end end - always @(posedge clock or posedge _T_30) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge _T_30) begin if (_T_30) begin command_reg <= 32'h0; - end else if (command_wren) begin - command_reg <= command_din; + end else begin + command_reg <= {_T_300,_T_298}; end end - always @(posedge clock or posedge _T_30) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge _T_30) begin if (_T_30) begin data0_reg <= 32'h0; - end else if (data0_reg_wren) begin - data0_reg <= data0_din; + end else begin + data0_reg <= _T_313 | _T_316; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge _T_30) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge _T_30) begin if (_T_30) begin _T_327 <= 32'h0; end else begin diff --git a/dma_ctrl.fir b/dma_ctrl.fir index 33587952..f7cc89c3 100644 --- a/dma_ctrl.fir +++ b/dma_ctrl.fir @@ -1830,7 +1830,7 @@ circuit dma_ctrl : node _T_987 = add(num_fifo_vld_tmp, num_fifo_vld_tmp2) @[dma_ctrl.scala 295:45] node _T_988 = tail(_T_987, 1) @[dma_ctrl.scala 295:45] num_fifo_vld <= _T_988 @[dma_ctrl.scala 295:25] - node fifo_full_spec = geq(num_fifo_vld_tmp2, UInt<3>("h05")) @[dma_ctrl.scala 297:46] + node fifo_full_spec = geq(num_fifo_vld, UInt<3>("h05")) @[dma_ctrl.scala 297:41] node _T_989 = or(fifo_full, dbg_dma_bubble_bus) @[dma_ctrl.scala 299:39] node dma_fifo_ready = not(_T_989) @[dma_ctrl.scala 299:27] node _T_990 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 303:38] @@ -1903,230 +1903,250 @@ circuit dma_ctrl : node _T_1056 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 313:26] node _T_1057 = eq(_T_1056, UInt<2>("h03")) @[dma_ctrl.scala 313:32] node _T_1058 = bits(dma_mem_byteen, 6, 3) @[dma_ctrl.scala 313:59] - node _T_1059 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1060 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1061 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1062 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1063 = or(_T_1059, _T_1060) @[Mux.scala 27:72] - node _T_1064 = or(_T_1063, _T_1061) @[Mux.scala 27:72] - node _T_1065 = or(_T_1064, _T_1062) @[Mux.scala 27:72] - wire _T_1066 : UInt<4> @[Mux.scala 27:72] - _T_1066 <= _T_1065 @[Mux.scala 27:72] - node _T_1067 = neq(_T_1066, UInt<4>("h0f")) @[dma_ctrl.scala 313:68] - node _T_1068 = and(_T_1046, _T_1067) @[dma_ctrl.scala 310:78] - node _T_1069 = or(_T_1043, _T_1068) @[dma_ctrl.scala 309:145] - node _T_1070 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 314:62] - node _T_1071 = eq(_T_1070, UInt<2>("h03")) @[dma_ctrl.scala 314:69] - node _T_1072 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1071) @[dma_ctrl.scala 314:45] - node _T_1073 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:97] - node _T_1074 = eq(_T_1073, UInt<4>("h0f")) @[dma_ctrl.scala 314:103] - node _T_1075 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:133] - node _T_1076 = eq(_T_1075, UInt<8>("h0f0")) @[dma_ctrl.scala 314:139] - node _T_1077 = or(_T_1074, _T_1076) @[dma_ctrl.scala 314:116] - node _T_1078 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:169] - node _T_1079 = eq(_T_1078, UInt<8>("h0ff")) @[dma_ctrl.scala 314:175] - node _T_1080 = or(_T_1077, _T_1079) @[dma_ctrl.scala 314:152] - node _T_1081 = eq(_T_1080, UInt<1>("h00")) @[dma_ctrl.scala 314:80] - node _T_1082 = and(_T_1072, _T_1081) @[dma_ctrl.scala 314:78] - node _T_1083 = or(_T_1069, _T_1082) @[dma_ctrl.scala 313:79] - node _T_1084 = and(_T_1010, _T_1083) @[dma_ctrl.scala 304:87] - dma_alignment_error <= _T_1084 @[dma_ctrl.scala 304:25] - node _T_1085 = and(fifo_empty, dbg_dma_bubble_bus) @[dma_ctrl.scala 319:50] - io.dbg_dma_io.dma_dbg_ready <= _T_1085 @[dma_ctrl.scala 319:36] - node _T_1086 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 320:39] - node _T_1087 = bits(_T_1086, 0, 0) @[dma_ctrl.scala 320:39] - node _T_1088 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 320:58] - node _T_1089 = bits(_T_1088, 0, 0) @[dma_ctrl.scala 320:58] - node _T_1090 = and(_T_1087, _T_1089) @[dma_ctrl.scala 320:48] - node _T_1091 = dshr(fifo_done, RspPtr) @[dma_ctrl.scala 320:78] - node _T_1092 = bits(_T_1091, 0, 0) @[dma_ctrl.scala 320:78] - node _T_1093 = and(_T_1090, _T_1092) @[dma_ctrl.scala 320:67] - io.dma_dbg_cmd_done <= _T_1093 @[dma_ctrl.scala 320:25] - node _T_1094 = bits(fifo_addr[RspPtr], 2, 2) @[dma_ctrl.scala 321:49] - node _T_1095 = bits(fifo_data[RspPtr], 63, 32) @[dma_ctrl.scala 321:71] - node _T_1096 = bits(fifo_data[RspPtr], 31, 0) @[dma_ctrl.scala 321:98] - node _T_1097 = mux(_T_1094, _T_1095, _T_1096) @[dma_ctrl.scala 321:31] - io.dma_dbg_rddata <= _T_1097 @[dma_ctrl.scala 321:25] - node _T_1098 = orr(fifo_error[RspPtr]) @[dma_ctrl.scala 322:47] - io.dma_dbg_cmd_fail <= _T_1098 @[dma_ctrl.scala 322:25] - node _T_1099 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 324:38] - node _T_1100 = bits(_T_1099, 0, 0) @[dma_ctrl.scala 324:38] - node _T_1101 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 324:58] - node _T_1102 = bits(_T_1101, 0, 0) @[dma_ctrl.scala 324:58] - node _T_1103 = eq(_T_1102, UInt<1>("h00")) @[dma_ctrl.scala 324:48] - node _T_1104 = and(_T_1100, _T_1103) @[dma_ctrl.scala 324:46] - node _T_1105 = dshr(fifo_dbg, RdPtr) @[dma_ctrl.scala 324:76] - node _T_1106 = bits(_T_1105, 0, 0) @[dma_ctrl.scala 324:76] - node _T_1107 = and(_T_1104, _T_1106) @[dma_ctrl.scala 324:66] - node _T_1108 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[dma_ctrl.scala 324:111] - node _T_1109 = or(_T_1108, dma_mem_addr_in_pic) @[dma_ctrl.scala 324:134] - node _T_1110 = not(_T_1109) @[dma_ctrl.scala 324:88] - node _T_1111 = bits(_T_1110, 0, 0) @[dma_ctrl.scala 324:164] - node _T_1112 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 324:184] - node _T_1113 = neq(_T_1112, UInt<2>("h02")) @[dma_ctrl.scala 324:191] - node _T_1114 = or(_T_1111, _T_1113) @[dma_ctrl.scala 324:167] - node _T_1115 = and(_T_1107, _T_1114) @[dma_ctrl.scala 324:84] - dma_dbg_cmd_error <= _T_1115 @[dma_ctrl.scala 324:25] - node _T_1116 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 328:80] - node _T_1117 = and(dma_mem_req, _T_1116) @[dma_ctrl.scala 328:56] - node _T_1118 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 328:121] - node _T_1119 = and(_T_1117, _T_1118) @[dma_ctrl.scala 328:103] - io.dec_dma.tlu_dma.dma_dccm_stall_any <= _T_1119 @[dma_ctrl.scala 328:41] - node _T_1120 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 329:56] - node _T_1121 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 329:97] - node _T_1122 = and(_T_1120, _T_1121) @[dma_ctrl.scala 329:79] - io.ifu_dma.dma_ifc.dma_iccm_stall_any <= _T_1122 @[dma_ctrl.scala 329:41] - io.dec_dma.tlu_dma.dma_iccm_stall_any <= io.ifu_dma.dma_ifc.dma_iccm_stall_any @[dma_ctrl.scala 330:41] - io.dec_dma.dctl_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dma_ctrl.scala 331:42] - node _T_1123 = orr(fifo_valid) @[dma_ctrl.scala 334:30] - node _T_1124 = not(_T_1123) @[dma_ctrl.scala 334:17] - fifo_empty <= _T_1124 @[dma_ctrl.scala 334:14] - dma_nack_count_csr <= io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[dma_ctrl.scala 338:22] - node _T_1125 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 339:45] - node _T_1126 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 339:115] - node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[dma_ctrl.scala 339:77] - node _T_1128 = bits(_T_1127, 0, 0) @[Bitwise.scala 72:15] - node _T_1129 = mux(_T_1128, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_1130 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 339:171] - node _T_1131 = and(_T_1129, _T_1130) @[dma_ctrl.scala 339:155] - node _T_1132 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 339:196] - node _T_1133 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 339:243] - node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dma_ctrl.scala 339:205] - node _T_1135 = and(_T_1132, _T_1134) @[dma_ctrl.scala 339:203] - node _T_1136 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 339:298] - node _T_1137 = add(_T_1136, UInt<1>("h01")) @[dma_ctrl.scala 339:304] - node _T_1138 = tail(_T_1137, 1) @[dma_ctrl.scala 339:304] - node _T_1139 = mux(_T_1135, _T_1138, UInt<1>("h00")) @[dma_ctrl.scala 339:182] - node dma_nack_count_d = mux(_T_1125, _T_1131, _T_1139) @[dma_ctrl.scala 339:29] - node _T_1140 = bits(dma_nack_count_d, 2, 0) @[dma_ctrl.scala 342:31] - node _T_1141 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 342:55] - reg _T_1142 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_1141 : @[Reg.scala 28:19] - _T_1142 <= _T_1140 @[Reg.scala 28:23] + node _T_1059 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 314:26] + node _T_1060 = eq(_T_1059, UInt<3>("h04")) @[dma_ctrl.scala 314:32] + node _T_1061 = bits(dma_mem_byteen, 7, 4) @[dma_ctrl.scala 314:59] + node _T_1062 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 315:26] + node _T_1063 = eq(_T_1062, UInt<3>("h05")) @[dma_ctrl.scala 315:32] + node _T_1064 = bits(dma_mem_byteen, 7, 5) @[dma_ctrl.scala 315:59] + node _T_1065 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 316:26] + node _T_1066 = eq(_T_1065, UInt<3>("h06")) @[dma_ctrl.scala 316:32] + node _T_1067 = bits(dma_mem_byteen, 7, 6) @[dma_ctrl.scala 316:59] + node _T_1068 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 317:26] + node _T_1069 = eq(_T_1068, UInt<3>("h07")) @[dma_ctrl.scala 317:32] + node _T_1070 = bits(dma_mem_byteen, 7, 7) @[dma_ctrl.scala 317:59] + node _T_1071 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1072 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1073 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1074 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1075 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1076 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1077 = mux(_T_1066, _T_1067, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = or(_T_1071, _T_1072) @[Mux.scala 27:72] + node _T_1080 = or(_T_1079, _T_1073) @[Mux.scala 27:72] + node _T_1081 = or(_T_1080, _T_1074) @[Mux.scala 27:72] + node _T_1082 = or(_T_1081, _T_1075) @[Mux.scala 27:72] + node _T_1083 = or(_T_1082, _T_1076) @[Mux.scala 27:72] + node _T_1084 = or(_T_1083, _T_1077) @[Mux.scala 27:72] + node _T_1085 = or(_T_1084, _T_1078) @[Mux.scala 27:72] + wire _T_1086 : UInt<4> @[Mux.scala 27:72] + _T_1086 <= _T_1085 @[Mux.scala 27:72] + node _T_1087 = neq(_T_1086, UInt<4>("h0f")) @[dma_ctrl.scala 317:66] + node _T_1088 = and(_T_1046, _T_1087) @[dma_ctrl.scala 310:78] + node _T_1089 = or(_T_1043, _T_1088) @[dma_ctrl.scala 309:145] + node _T_1090 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 318:62] + node _T_1091 = eq(_T_1090, UInt<2>("h03")) @[dma_ctrl.scala 318:69] + node _T_1092 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1091) @[dma_ctrl.scala 318:45] + node _T_1093 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 318:97] + node _T_1094 = eq(_T_1093, UInt<4>("h0f")) @[dma_ctrl.scala 318:103] + node _T_1095 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 318:133] + node _T_1096 = eq(_T_1095, UInt<8>("h0f0")) @[dma_ctrl.scala 318:139] + node _T_1097 = or(_T_1094, _T_1096) @[dma_ctrl.scala 318:116] + node _T_1098 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 318:169] + node _T_1099 = eq(_T_1098, UInt<8>("h0ff")) @[dma_ctrl.scala 318:175] + node _T_1100 = or(_T_1097, _T_1099) @[dma_ctrl.scala 318:152] + node _T_1101 = eq(_T_1100, UInt<1>("h00")) @[dma_ctrl.scala 318:80] + node _T_1102 = and(_T_1092, _T_1101) @[dma_ctrl.scala 318:78] + node _T_1103 = or(_T_1089, _T_1102) @[dma_ctrl.scala 317:79] + node _T_1104 = and(_T_1010, _T_1103) @[dma_ctrl.scala 304:87] + dma_alignment_error <= _T_1104 @[dma_ctrl.scala 304:25] + node _T_1105 = and(fifo_empty, dbg_dma_bubble_bus) @[dma_ctrl.scala 323:50] + io.dbg_dma_io.dma_dbg_ready <= _T_1105 @[dma_ctrl.scala 323:36] + node _T_1106 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 324:39] + node _T_1107 = bits(_T_1106, 0, 0) @[dma_ctrl.scala 324:39] + node _T_1108 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 324:58] + node _T_1109 = bits(_T_1108, 0, 0) @[dma_ctrl.scala 324:58] + node _T_1110 = and(_T_1107, _T_1109) @[dma_ctrl.scala 324:48] + node _T_1111 = dshr(fifo_done, RspPtr) @[dma_ctrl.scala 324:78] + node _T_1112 = bits(_T_1111, 0, 0) @[dma_ctrl.scala 324:78] + node _T_1113 = and(_T_1110, _T_1112) @[dma_ctrl.scala 324:67] + io.dma_dbg_cmd_done <= _T_1113 @[dma_ctrl.scala 324:25] + node _T_1114 = bits(fifo_addr[RspPtr], 2, 2) @[dma_ctrl.scala 325:49] + node _T_1115 = bits(fifo_data[RspPtr], 63, 32) @[dma_ctrl.scala 325:71] + node _T_1116 = bits(fifo_data[RspPtr], 31, 0) @[dma_ctrl.scala 325:98] + node _T_1117 = mux(_T_1114, _T_1115, _T_1116) @[dma_ctrl.scala 325:31] + io.dma_dbg_rddata <= _T_1117 @[dma_ctrl.scala 325:25] + node _T_1118 = orr(fifo_error[RspPtr]) @[dma_ctrl.scala 326:47] + io.dma_dbg_cmd_fail <= _T_1118 @[dma_ctrl.scala 326:25] + node _T_1119 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 328:38] + node _T_1120 = bits(_T_1119, 0, 0) @[dma_ctrl.scala 328:38] + node _T_1121 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 328:58] + node _T_1122 = bits(_T_1121, 0, 0) @[dma_ctrl.scala 328:58] + node _T_1123 = eq(_T_1122, UInt<1>("h00")) @[dma_ctrl.scala 328:48] + node _T_1124 = and(_T_1120, _T_1123) @[dma_ctrl.scala 328:46] + node _T_1125 = dshr(fifo_dbg, RdPtr) @[dma_ctrl.scala 328:76] + node _T_1126 = bits(_T_1125, 0, 0) @[dma_ctrl.scala 328:76] + node _T_1127 = and(_T_1124, _T_1126) @[dma_ctrl.scala 328:66] + node _T_1128 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[dma_ctrl.scala 328:111] + node _T_1129 = or(_T_1128, dma_mem_addr_in_pic) @[dma_ctrl.scala 328:134] + node _T_1130 = not(_T_1129) @[dma_ctrl.scala 328:88] + node _T_1131 = bits(_T_1130, 0, 0) @[dma_ctrl.scala 328:164] + node _T_1132 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 328:184] + node _T_1133 = neq(_T_1132, UInt<2>("h02")) @[dma_ctrl.scala 328:191] + node _T_1134 = or(_T_1131, _T_1133) @[dma_ctrl.scala 328:167] + node _T_1135 = and(_T_1127, _T_1134) @[dma_ctrl.scala 328:84] + dma_dbg_cmd_error <= _T_1135 @[dma_ctrl.scala 328:25] + node _T_1136 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 332:80] + node _T_1137 = and(dma_mem_req, _T_1136) @[dma_ctrl.scala 332:56] + node _T_1138 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 332:121] + node _T_1139 = and(_T_1137, _T_1138) @[dma_ctrl.scala 332:103] + io.dec_dma.tlu_dma.dma_dccm_stall_any <= _T_1139 @[dma_ctrl.scala 332:41] + node _T_1140 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 333:56] + node _T_1141 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 333:97] + node _T_1142 = and(_T_1140, _T_1141) @[dma_ctrl.scala 333:79] + io.ifu_dma.dma_ifc.dma_iccm_stall_any <= _T_1142 @[dma_ctrl.scala 333:41] + io.dec_dma.tlu_dma.dma_iccm_stall_any <= io.ifu_dma.dma_ifc.dma_iccm_stall_any @[dma_ctrl.scala 334:41] + io.dec_dma.dctl_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dma_ctrl.scala 335:42] + node _T_1143 = orr(fifo_valid) @[dma_ctrl.scala 338:30] + node _T_1144 = not(_T_1143) @[dma_ctrl.scala 338:17] + fifo_empty <= _T_1144 @[dma_ctrl.scala 338:14] + dma_nack_count_csr <= io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[dma_ctrl.scala 342:22] + node _T_1145 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 343:45] + node _T_1146 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 343:115] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dma_ctrl.scala 343:77] + node _T_1148 = bits(_T_1147, 0, 0) @[Bitwise.scala 72:15] + node _T_1149 = mux(_T_1148, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_1150 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 343:171] + node _T_1151 = and(_T_1149, _T_1150) @[dma_ctrl.scala 343:155] + node _T_1152 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 343:196] + node _T_1153 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 343:243] + node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[dma_ctrl.scala 343:205] + node _T_1155 = and(_T_1152, _T_1154) @[dma_ctrl.scala 343:203] + node _T_1156 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 343:298] + node _T_1157 = add(_T_1156, UInt<1>("h01")) @[dma_ctrl.scala 343:304] + node _T_1158 = tail(_T_1157, 1) @[dma_ctrl.scala 343:304] + node _T_1159 = mux(_T_1155, _T_1158, UInt<1>("h00")) @[dma_ctrl.scala 343:182] + node dma_nack_count_d = mux(_T_1145, _T_1151, _T_1159) @[dma_ctrl.scala 343:29] + node _T_1160 = bits(dma_nack_count_d, 2, 0) @[dma_ctrl.scala 346:31] + node _T_1161 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 346:55] + reg _T_1162 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1161 : @[Reg.scala 28:19] + _T_1162 <= _T_1160 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - dma_nack_count <= _T_1142 @[dma_ctrl.scala 341:22] - node _T_1143 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 347:33] - node _T_1144 = bits(_T_1143, 0, 0) @[dma_ctrl.scala 347:33] - node _T_1145 = dshr(fifo_rpend, RdPtr) @[dma_ctrl.scala 347:54] - node _T_1146 = bits(_T_1145, 0, 0) @[dma_ctrl.scala 347:54] - node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dma_ctrl.scala 347:43] - node _T_1148 = and(_T_1144, _T_1147) @[dma_ctrl.scala 347:41] - node _T_1149 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 347:74] - node _T_1150 = bits(_T_1149, 0, 0) @[dma_ctrl.scala 347:74] - node _T_1151 = eq(_T_1150, UInt<1>("h00")) @[dma_ctrl.scala 347:64] - node _T_1152 = and(_T_1148, _T_1151) @[dma_ctrl.scala 347:62] - node _T_1153 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 347:104] - node _T_1154 = or(_T_1153, dma_dbg_cmd_error) @[dma_ctrl.scala 347:126] - node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[dma_ctrl.scala 347:84] - node _T_1156 = and(_T_1152, _T_1155) @[dma_ctrl.scala 347:82] - dma_mem_req <= _T_1156 @[dma_ctrl.scala 347:20] - node _T_1157 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 348:79] - node _T_1158 = and(dma_mem_req, _T_1157) @[dma_ctrl.scala 348:55] - node _T_1159 = and(_T_1158, io.lsu_dma.dccm_ready) @[dma_ctrl.scala 348:102] - io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= _T_1159 @[dma_ctrl.scala 348:40] - node _T_1160 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 349:55] - node _T_1161 = and(_T_1160, io.iccm_ready) @[dma_ctrl.scala 349:78] - io.ifu_dma.dma_mem_ctl.dma_iccm_req <= _T_1161 @[dma_ctrl.scala 349:40] - io.lsu_dma.dma_mem_tag <= RdPtr @[dma_ctrl.scala 350:28] - dma_mem_addr_int <= fifo_addr[RdPtr] @[dma_ctrl.scala 351:20] - dma_mem_sz_int <= fifo_sz[RdPtr] @[dma_ctrl.scala 352:20] - node _T_1162 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 353:101] - node _T_1163 = eq(_T_1162, UInt<8>("h0f0")) @[dma_ctrl.scala 353:107] - node _T_1164 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1163) @[dma_ctrl.scala 353:84] - node _T_1165 = bits(dma_mem_addr_int, 31, 3) @[dma_ctrl.scala 353:141] - node _T_1166 = bits(dma_mem_addr_int, 1, 0) @[dma_ctrl.scala 353:171] - node _T_1167 = cat(_T_1165, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_1168 = cat(_T_1167, _T_1166) @[Cat.scala 29:58] - node _T_1169 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 353:196] - node _T_1170 = mux(_T_1164, _T_1168, _T_1169) @[dma_ctrl.scala 353:46] - io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= _T_1170 @[dma_ctrl.scala 353:40] - node _T_1171 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 354:102] - node _T_1172 = eq(_T_1171, UInt<4>("h0f")) @[dma_ctrl.scala 354:108] - node _T_1173 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 354:138] - node _T_1174 = eq(_T_1173, UInt<8>("h0f0")) @[dma_ctrl.scala 354:144] - node _T_1175 = or(_T_1172, _T_1174) @[dma_ctrl.scala 354:121] - node _T_1176 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1175) @[dma_ctrl.scala 354:84] - node _T_1177 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 354:178] - node _T_1178 = mux(_T_1176, UInt<2>("h02"), _T_1177) @[dma_ctrl.scala 354:46] - io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= _T_1178 @[dma_ctrl.scala 354:40] - dma_mem_byteen <= fifo_byteen[RdPtr] @[dma_ctrl.scala 355:20] - node _T_1179 = dshr(fifo_write, RdPtr) @[dma_ctrl.scala 356:53] - node _T_1180 = bits(_T_1179, 0, 0) @[dma_ctrl.scala 356:53] - io.lsu_dma.dma_lsc_ctl.dma_mem_write <= _T_1180 @[dma_ctrl.scala 356:40] - io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= fifo_data[RdPtr] @[dma_ctrl.scala 357:40] - node _T_1181 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 361:83] - node _T_1182 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, _T_1181) @[dma_ctrl.scala 361:81] - io.dec_dma.tlu_dma.dma_pmu_dccm_read <= _T_1182 @[dma_ctrl.scala 361:42] - node _T_1183 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 362:81] - io.dec_dma.tlu_dma.dma_pmu_dccm_write <= _T_1183 @[dma_ctrl.scala 362:42] - node _T_1184 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 363:82] - node _T_1185 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 363:123] - node _T_1186 = and(_T_1184, _T_1185) @[dma_ctrl.scala 363:121] - io.dec_dma.tlu_dma.dma_pmu_any_read <= _T_1186 @[dma_ctrl.scala 363:42] - node _T_1187 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 364:82] - node _T_1188 = and(_T_1187, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 364:121] - io.dec_dma.tlu_dma.dma_pmu_any_write <= _T_1188 @[dma_ctrl.scala 364:42] - reg _T_1189 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 369:12] - _T_1189 <= fifo_full_spec @[dma_ctrl.scala 369:12] - fifo_full <= _T_1189 @[dma_ctrl.scala 368:22] - reg _T_1190 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 373:12] - _T_1190 <= io.dbg_dma_io.dbg_dma_bubble @[dma_ctrl.scala 373:12] - dbg_dma_bubble_bus <= _T_1190 @[dma_ctrl.scala 372:22] - reg _T_1191 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 377:12] - _T_1191 <= io.dma_dbg_cmd_done @[dma_ctrl.scala 377:12] - dma_dbg_cmd_done_q <= _T_1191 @[dma_ctrl.scala 376:22] - node _T_1192 = and(bus_cmd_valid, io.dma_bus_clk_en) @[dma_ctrl.scala 382:44] - node _T_1193 = or(_T_1192, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 382:65] - node dma_buffer_c1_clken = or(_T_1193, io.clk_override) @[dma_ctrl.scala 382:99] - node _T_1194 = or(bus_cmd_valid, bus_rsp_valid) @[dma_ctrl.scala 383:44] - node _T_1195 = or(_T_1194, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 383:60] - node _T_1196 = or(_T_1195, io.dma_dbg_cmd_done) @[dma_ctrl.scala 383:94] - node _T_1197 = or(_T_1196, dma_dbg_cmd_done_q) @[dma_ctrl.scala 383:116] - node _T_1198 = orr(fifo_valid) @[dma_ctrl.scala 383:151] - node _T_1199 = or(_T_1197, _T_1198) @[dma_ctrl.scala 383:137] - node dma_free_clken = or(_T_1199, io.clk_override) @[dma_ctrl.scala 383:156] - inst dma_buffer_c1cgc of rvclkhdr_10 @[dma_ctrl.scala 385:32] + dma_nack_count <= _T_1162 @[dma_ctrl.scala 345:22] + node _T_1163 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 351:33] + node _T_1164 = bits(_T_1163, 0, 0) @[dma_ctrl.scala 351:33] + node _T_1165 = dshr(fifo_rpend, RdPtr) @[dma_ctrl.scala 351:54] + node _T_1166 = bits(_T_1165, 0, 0) @[dma_ctrl.scala 351:54] + node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dma_ctrl.scala 351:43] + node _T_1168 = and(_T_1164, _T_1167) @[dma_ctrl.scala 351:41] + node _T_1169 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 351:74] + node _T_1170 = bits(_T_1169, 0, 0) @[dma_ctrl.scala 351:74] + node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[dma_ctrl.scala 351:64] + node _T_1172 = and(_T_1168, _T_1171) @[dma_ctrl.scala 351:62] + node _T_1173 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 351:104] + node _T_1174 = or(_T_1173, dma_dbg_cmd_error) @[dma_ctrl.scala 351:126] + node _T_1175 = eq(_T_1174, UInt<1>("h00")) @[dma_ctrl.scala 351:84] + node _T_1176 = and(_T_1172, _T_1175) @[dma_ctrl.scala 351:82] + dma_mem_req <= _T_1176 @[dma_ctrl.scala 351:20] + node _T_1177 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 352:79] + node _T_1178 = and(dma_mem_req, _T_1177) @[dma_ctrl.scala 352:55] + node _T_1179 = and(_T_1178, io.lsu_dma.dccm_ready) @[dma_ctrl.scala 352:102] + io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= _T_1179 @[dma_ctrl.scala 352:40] + node _T_1180 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 353:55] + node _T_1181 = and(_T_1180, io.iccm_ready) @[dma_ctrl.scala 353:78] + io.ifu_dma.dma_mem_ctl.dma_iccm_req <= _T_1181 @[dma_ctrl.scala 353:40] + io.lsu_dma.dma_mem_tag <= RdPtr @[dma_ctrl.scala 354:28] + dma_mem_addr_int <= fifo_addr[RdPtr] @[dma_ctrl.scala 355:20] + dma_mem_sz_int <= fifo_sz[RdPtr] @[dma_ctrl.scala 356:20] + node _T_1182 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 357:101] + node _T_1183 = eq(_T_1182, UInt<8>("h0f0")) @[dma_ctrl.scala 357:107] + node _T_1184 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1183) @[dma_ctrl.scala 357:84] + node _T_1185 = bits(dma_mem_addr_int, 31, 3) @[dma_ctrl.scala 357:141] + node _T_1186 = bits(dma_mem_addr_int, 1, 0) @[dma_ctrl.scala 357:171] + node _T_1187 = cat(_T_1185, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_1188 = cat(_T_1187, _T_1186) @[Cat.scala 29:58] + node _T_1189 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 357:196] + node _T_1190 = mux(_T_1184, _T_1188, _T_1189) @[dma_ctrl.scala 357:46] + io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= _T_1190 @[dma_ctrl.scala 357:40] + node _T_1191 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 358:102] + node _T_1192 = eq(_T_1191, UInt<4>("h0f")) @[dma_ctrl.scala 358:108] + node _T_1193 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 358:138] + node _T_1194 = eq(_T_1193, UInt<8>("h0f0")) @[dma_ctrl.scala 358:144] + node _T_1195 = or(_T_1192, _T_1194) @[dma_ctrl.scala 358:121] + node _T_1196 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1195) @[dma_ctrl.scala 358:84] + node _T_1197 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 358:178] + node _T_1198 = mux(_T_1196, UInt<2>("h02"), _T_1197) @[dma_ctrl.scala 358:46] + io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= _T_1198 @[dma_ctrl.scala 358:40] + dma_mem_byteen <= fifo_byteen[RdPtr] @[dma_ctrl.scala 359:20] + node _T_1199 = dshr(fifo_write, RdPtr) @[dma_ctrl.scala 360:53] + node _T_1200 = bits(_T_1199, 0, 0) @[dma_ctrl.scala 360:53] + io.lsu_dma.dma_lsc_ctl.dma_mem_write <= _T_1200 @[dma_ctrl.scala 360:40] + io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= fifo_data[RdPtr] @[dma_ctrl.scala 361:40] + node _T_1201 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 365:83] + node _T_1202 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, _T_1201) @[dma_ctrl.scala 365:81] + io.dec_dma.tlu_dma.dma_pmu_dccm_read <= _T_1202 @[dma_ctrl.scala 365:42] + node _T_1203 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 366:81] + io.dec_dma.tlu_dma.dma_pmu_dccm_write <= _T_1203 @[dma_ctrl.scala 366:42] + node _T_1204 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 367:82] + node _T_1205 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 367:123] + node _T_1206 = and(_T_1204, _T_1205) @[dma_ctrl.scala 367:121] + io.dec_dma.tlu_dma.dma_pmu_any_read <= _T_1206 @[dma_ctrl.scala 367:42] + node _T_1207 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 368:82] + node _T_1208 = and(_T_1207, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 368:121] + io.dec_dma.tlu_dma.dma_pmu_any_write <= _T_1208 @[dma_ctrl.scala 368:42] + reg _T_1209 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 373:12] + _T_1209 <= fifo_full_spec @[dma_ctrl.scala 373:12] + fifo_full <= _T_1209 @[dma_ctrl.scala 372:22] + reg _T_1210 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 377:12] + _T_1210 <= io.dbg_dma_io.dbg_dma_bubble @[dma_ctrl.scala 377:12] + dbg_dma_bubble_bus <= _T_1210 @[dma_ctrl.scala 376:22] + reg _T_1211 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 381:12] + _T_1211 <= io.dma_dbg_cmd_done @[dma_ctrl.scala 381:12] + dma_dbg_cmd_done_q <= _T_1211 @[dma_ctrl.scala 380:22] + node _T_1212 = and(bus_cmd_valid, io.dma_bus_clk_en) @[dma_ctrl.scala 386:44] + node _T_1213 = or(_T_1212, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 386:65] + node dma_buffer_c1_clken = or(_T_1213, io.clk_override) @[dma_ctrl.scala 386:99] + node _T_1214 = or(bus_cmd_valid, bus_rsp_valid) @[dma_ctrl.scala 387:44] + node _T_1215 = or(_T_1214, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 387:60] + node _T_1216 = or(_T_1215, io.dma_dbg_cmd_done) @[dma_ctrl.scala 387:94] + node _T_1217 = or(_T_1216, dma_dbg_cmd_done_q) @[dma_ctrl.scala 387:116] + node _T_1218 = orr(fifo_valid) @[dma_ctrl.scala 387:151] + node _T_1219 = or(_T_1217, _T_1218) @[dma_ctrl.scala 387:137] + node dma_free_clken = or(_T_1219, io.clk_override) @[dma_ctrl.scala 387:156] + inst dma_buffer_c1cgc of rvclkhdr_10 @[dma_ctrl.scala 389:32] dma_buffer_c1cgc.clock <= clock dma_buffer_c1cgc.reset <= reset - dma_buffer_c1cgc.io.en <= dma_buffer_c1_clken @[dma_ctrl.scala 386:33] - dma_buffer_c1cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 387:33] - dma_buffer_c1cgc.io.clk <= clock @[dma_ctrl.scala 388:33] - dma_buffer_c1_clk <= dma_buffer_c1cgc.io.l1clk @[dma_ctrl.scala 389:33] - inst dma_free_cgc of rvclkhdr_11 @[dma_ctrl.scala 391:28] + dma_buffer_c1cgc.io.en <= dma_buffer_c1_clken @[dma_ctrl.scala 390:33] + dma_buffer_c1cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 391:33] + dma_buffer_c1cgc.io.clk <= clock @[dma_ctrl.scala 392:33] + dma_buffer_c1_clk <= dma_buffer_c1cgc.io.l1clk @[dma_ctrl.scala 393:33] + inst dma_free_cgc of rvclkhdr_11 @[dma_ctrl.scala 395:28] dma_free_cgc.clock <= clock dma_free_cgc.reset <= reset - dma_free_cgc.io.en <= dma_free_clken @[dma_ctrl.scala 392:29] - dma_free_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 393:29] - dma_free_cgc.io.clk <= clock @[dma_ctrl.scala 394:29] - dma_free_clk <= dma_free_cgc.io.l1clk @[dma_ctrl.scala 395:29] - inst dma_bus_cgc of rvclkhdr_12 @[dma_ctrl.scala 397:27] + dma_free_cgc.io.en <= dma_free_clken @[dma_ctrl.scala 396:29] + dma_free_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 397:29] + dma_free_cgc.io.clk <= clock @[dma_ctrl.scala 398:29] + dma_free_clk <= dma_free_cgc.io.l1clk @[dma_ctrl.scala 399:29] + inst dma_bus_cgc of rvclkhdr_12 @[dma_ctrl.scala 401:27] dma_bus_cgc.clock <= clock dma_bus_cgc.reset <= reset - dma_bus_cgc.io.en <= io.dma_bus_clk_en @[dma_ctrl.scala 398:28] - dma_bus_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 399:28] - dma_bus_cgc.io.clk <= clock @[dma_ctrl.scala 400:28] - dma_bus_clk <= dma_bus_cgc.io.l1clk @[dma_ctrl.scala 401:28] - node wrbuf_en = and(io.dma_axi.aw.valid, io.dma_axi.aw.ready) @[dma_ctrl.scala 405:47] - node wrbuf_data_en = and(io.dma_axi.w.valid, io.dma_axi.w.ready) @[dma_ctrl.scala 406:46] - node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[dma_ctrl.scala 407:40] - node _T_1200 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 408:42] - node _T_1201 = eq(wrbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 408:51] - node wrbuf_rst = and(_T_1200, _T_1201) @[dma_ctrl.scala 408:49] - node _T_1202 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 409:42] - node _T_1203 = eq(wrbuf_data_en, UInt<1>("h00")) @[dma_ctrl.scala 409:51] - node wrbuf_data_rst = and(_T_1202, _T_1203) @[dma_ctrl.scala 409:49] - node _T_1204 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[dma_ctrl.scala 411:63] - node _T_1205 = eq(wrbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 411:92] - node _T_1206 = and(_T_1204, _T_1205) @[dma_ctrl.scala 411:90] - reg _T_1207 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 411:59] - _T_1207 <= _T_1206 @[dma_ctrl.scala 411:59] - wrbuf_vld <= _T_1207 @[dma_ctrl.scala 411:25] - node _T_1208 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[dma_ctrl.scala 413:63] - node _T_1209 = eq(wrbuf_data_rst, UInt<1>("h00")) @[dma_ctrl.scala 413:102] - node _T_1210 = and(_T_1208, _T_1209) @[dma_ctrl.scala 413:100] - reg _T_1211 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 413:59] - _T_1211 <= _T_1210 @[dma_ctrl.scala 413:59] - wrbuf_data_vld <= _T_1211 @[dma_ctrl.scala 413:25] + dma_bus_cgc.io.en <= io.dma_bus_clk_en @[dma_ctrl.scala 402:28] + dma_bus_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 403:28] + dma_bus_cgc.io.clk <= clock @[dma_ctrl.scala 404:28] + dma_bus_clk <= dma_bus_cgc.io.l1clk @[dma_ctrl.scala 405:28] + node wrbuf_en = and(io.dma_axi.aw.valid, io.dma_axi.aw.ready) @[dma_ctrl.scala 409:47] + node wrbuf_data_en = and(io.dma_axi.w.valid, io.dma_axi.w.ready) @[dma_ctrl.scala 410:46] + node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[dma_ctrl.scala 411:40] + node _T_1220 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 412:42] + node _T_1221 = eq(wrbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 412:51] + node wrbuf_rst = and(_T_1220, _T_1221) @[dma_ctrl.scala 412:49] + node _T_1222 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 413:42] + node _T_1223 = eq(wrbuf_data_en, UInt<1>("h00")) @[dma_ctrl.scala 413:51] + node wrbuf_data_rst = and(_T_1222, _T_1223) @[dma_ctrl.scala 413:49] + node _T_1224 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[dma_ctrl.scala 415:63] + node _T_1225 = eq(wrbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 415:92] + node _T_1226 = and(_T_1224, _T_1225) @[dma_ctrl.scala 415:90] + reg _T_1227 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 415:59] + _T_1227 <= _T_1226 @[dma_ctrl.scala 415:59] + wrbuf_vld <= _T_1227 @[dma_ctrl.scala 415:25] + node _T_1228 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[dma_ctrl.scala 417:63] + node _T_1229 = eq(wrbuf_data_rst, UInt<1>("h00")) @[dma_ctrl.scala 417:102] + node _T_1230 = and(_T_1228, _T_1229) @[dma_ctrl.scala 417:100] + reg _T_1231 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 417:59] + _T_1231 <= _T_1230 @[dma_ctrl.scala 417:59] + wrbuf_data_vld <= _T_1231 @[dma_ctrl.scala 417:25] reg wrbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when wrbuf_en : @[Reg.scala 28:19] wrbuf_tag <= io.dma_axi.aw.bits.id @[Reg.scala 28:23] @@ -2135,21 +2155,21 @@ circuit dma_ctrl : when wrbuf_en : @[Reg.scala 28:19] wrbuf_sz <= io.dma_axi.aw.bits.size @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_1212 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 423:68] + node _T_1232 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 427:68] inst rvclkhdr_10 of rvclkhdr_13 @[lib.scala 352:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_10.io.en <= _T_1212 @[lib.scala 355:17] + rvclkhdr_10.io.en <= _T_1232 @[lib.scala 355:17] rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg wrbuf_addr : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] wrbuf_addr <= io.dma_axi.aw.bits.addr @[lib.scala 358:16] - node _T_1213 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 425:72] + node _T_1233 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 429:72] inst rvclkhdr_11 of rvclkhdr_14 @[lib.scala 352:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset rvclkhdr_11.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_11.io.en <= _T_1213 @[lib.scala 355:17] + rvclkhdr_11.io.en <= _T_1233 @[lib.scala 355:17] rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg wrbuf_data : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] wrbuf_data <= io.dma_axi.w.bits.data @[lib.scala 358:16] @@ -2157,18 +2177,18 @@ circuit dma_ctrl : when wrbuf_data_en : @[Reg.scala 28:19] wrbuf_byteen <= io.dma_axi.w.bits.strb @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node rdbuf_en = and(io.dma_axi.ar.valid, io.dma_axi.ar.ready) @[dma_ctrl.scala 433:59] - node _T_1214 = eq(bus_cmd_write, UInt<1>("h00")) @[dma_ctrl.scala 434:44] - node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1214) @[dma_ctrl.scala 434:42] - node _T_1215 = bits(rdbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 435:54] - node _T_1216 = eq(rdbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 435:63] - node rdbuf_rst = and(_T_1215, _T_1216) @[dma_ctrl.scala 435:61] - node _T_1217 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[dma_ctrl.scala 437:51] - node _T_1218 = eq(rdbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 437:80] - node _T_1219 = and(_T_1217, _T_1218) @[dma_ctrl.scala 437:78] - reg _T_1220 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 437:47] - _T_1220 <= _T_1219 @[dma_ctrl.scala 437:47] - rdbuf_vld <= _T_1220 @[dma_ctrl.scala 437:13] + node rdbuf_en = and(io.dma_axi.ar.valid, io.dma_axi.ar.ready) @[dma_ctrl.scala 437:59] + node _T_1234 = eq(bus_cmd_write, UInt<1>("h00")) @[dma_ctrl.scala 438:44] + node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1234) @[dma_ctrl.scala 438:42] + node _T_1235 = bits(rdbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 439:54] + node _T_1236 = eq(rdbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 439:63] + node rdbuf_rst = and(_T_1235, _T_1236) @[dma_ctrl.scala 439:61] + node _T_1237 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[dma_ctrl.scala 441:51] + node _T_1238 = eq(rdbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 441:80] + node _T_1239 = and(_T_1237, _T_1238) @[dma_ctrl.scala 441:78] + reg _T_1240 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 441:47] + _T_1240 <= _T_1239 @[dma_ctrl.scala 441:47] + rdbuf_vld <= _T_1240 @[dma_ctrl.scala 441:13] reg rdbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when rdbuf_en : @[Reg.scala 28:19] rdbuf_tag <= io.dma_axi.ar.bits.id @[Reg.scala 28:23] @@ -2177,100 +2197,100 @@ circuit dma_ctrl : when rdbuf_en : @[Reg.scala 28:19] rdbuf_sz <= io.dma_axi.ar.bits.size @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_1221 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 447:61] + node _T_1241 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 451:61] inst rvclkhdr_12 of rvclkhdr_15 @[lib.scala 352:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_12.io.en <= _T_1221 @[lib.scala 355:17] + rvclkhdr_12.io.en <= _T_1241 @[lib.scala 355:17] rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg rdbuf_addr : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] rdbuf_addr <= io.dma_axi.ar.bits.addr @[lib.scala 358:16] - node _T_1222 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 449:44] - node _T_1223 = and(wrbuf_vld, _T_1222) @[dma_ctrl.scala 449:42] - node _T_1224 = not(_T_1223) @[dma_ctrl.scala 449:30] - io.dma_axi.aw.ready <= _T_1224 @[dma_ctrl.scala 449:27] - node _T_1225 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 450:49] - node _T_1226 = and(wrbuf_data_vld, _T_1225) @[dma_ctrl.scala 450:47] - node _T_1227 = not(_T_1226) @[dma_ctrl.scala 450:30] - io.dma_axi.w.ready <= _T_1227 @[dma_ctrl.scala 450:27] - node _T_1228 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 451:44] - node _T_1229 = and(rdbuf_vld, _T_1228) @[dma_ctrl.scala 451:42] - node _T_1230 = not(_T_1229) @[dma_ctrl.scala 451:30] - io.dma_axi.ar.ready <= _T_1230 @[dma_ctrl.scala 451:27] - node _T_1231 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 455:51] - node _T_1232 = or(_T_1231, rdbuf_vld) @[dma_ctrl.scala 455:69] - bus_cmd_valid <= _T_1232 @[dma_ctrl.scala 455:37] - node _T_1233 = and(bus_cmd_valid, dma_fifo_ready) @[dma_ctrl.scala 456:54] - axi_mstr_prty_en <= _T_1233 @[dma_ctrl.scala 456:37] - bus_cmd_write <= axi_mstr_sel @[dma_ctrl.scala 457:37] - bus_cmd_posted_write <= UInt<1>("h00") @[dma_ctrl.scala 458:25] - node _T_1234 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 459:57] - node _T_1235 = mux(_T_1234, wrbuf_addr, rdbuf_addr) @[dma_ctrl.scala 459:43] - bus_cmd_addr <= _T_1235 @[dma_ctrl.scala 459:37] - node _T_1236 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 460:59] - node _T_1237 = mux(_T_1236, wrbuf_sz, rdbuf_sz) @[dma_ctrl.scala 460:45] - bus_cmd_sz <= _T_1237 @[dma_ctrl.scala 460:39] - bus_cmd_wdata <= wrbuf_data @[dma_ctrl.scala 461:37] - bus_cmd_byteen <= wrbuf_byteen @[dma_ctrl.scala 462:37] - node _T_1238 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 463:57] - node _T_1239 = mux(_T_1238, wrbuf_tag, rdbuf_tag) @[dma_ctrl.scala 463:43] - bus_cmd_tag <= _T_1239 @[dma_ctrl.scala 463:37] - bus_cmd_mid <= UInt<1>("h00") @[dma_ctrl.scala 464:37] - bus_cmd_prty <= UInt<1>("h00") @[dma_ctrl.scala 465:37] - node _T_1240 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 469:43] - node _T_1241 = and(_T_1240, rdbuf_vld) @[dma_ctrl.scala 469:60] - node _T_1242 = eq(_T_1241, UInt<1>("h01")) @[dma_ctrl.scala 469:73] - node _T_1243 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 469:111] - node _T_1244 = mux(_T_1242, axi_mstr_priority, _T_1243) @[dma_ctrl.scala 469:31] - axi_mstr_sel <= _T_1244 @[dma_ctrl.scala 469:25] - node axi_mstr_prty_in = not(axi_mstr_priority) @[dma_ctrl.scala 470:27] - node _T_1245 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 474:55] - reg _T_1246 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_1245 : @[Reg.scala 28:19] - _T_1246 <= axi_mstr_prty_in @[Reg.scala 28:23] + node _T_1242 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 453:44] + node _T_1243 = and(wrbuf_vld, _T_1242) @[dma_ctrl.scala 453:42] + node _T_1244 = not(_T_1243) @[dma_ctrl.scala 453:30] + io.dma_axi.aw.ready <= _T_1244 @[dma_ctrl.scala 453:27] + node _T_1245 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 454:49] + node _T_1246 = and(wrbuf_data_vld, _T_1245) @[dma_ctrl.scala 454:47] + node _T_1247 = not(_T_1246) @[dma_ctrl.scala 454:30] + io.dma_axi.w.ready <= _T_1247 @[dma_ctrl.scala 454:27] + node _T_1248 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 455:44] + node _T_1249 = and(rdbuf_vld, _T_1248) @[dma_ctrl.scala 455:42] + node _T_1250 = not(_T_1249) @[dma_ctrl.scala 455:30] + io.dma_axi.ar.ready <= _T_1250 @[dma_ctrl.scala 455:27] + node _T_1251 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 459:51] + node _T_1252 = or(_T_1251, rdbuf_vld) @[dma_ctrl.scala 459:69] + bus_cmd_valid <= _T_1252 @[dma_ctrl.scala 459:37] + node _T_1253 = and(bus_cmd_valid, dma_fifo_ready) @[dma_ctrl.scala 460:54] + axi_mstr_prty_en <= _T_1253 @[dma_ctrl.scala 460:37] + bus_cmd_write <= axi_mstr_sel @[dma_ctrl.scala 461:37] + bus_cmd_posted_write <= UInt<1>("h00") @[dma_ctrl.scala 462:25] + node _T_1254 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 463:57] + node _T_1255 = mux(_T_1254, wrbuf_addr, rdbuf_addr) @[dma_ctrl.scala 463:43] + bus_cmd_addr <= _T_1255 @[dma_ctrl.scala 463:37] + node _T_1256 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 464:59] + node _T_1257 = mux(_T_1256, wrbuf_sz, rdbuf_sz) @[dma_ctrl.scala 464:45] + bus_cmd_sz <= _T_1257 @[dma_ctrl.scala 464:39] + bus_cmd_wdata <= wrbuf_data @[dma_ctrl.scala 465:37] + bus_cmd_byteen <= wrbuf_byteen @[dma_ctrl.scala 466:37] + node _T_1258 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 467:57] + node _T_1259 = mux(_T_1258, wrbuf_tag, rdbuf_tag) @[dma_ctrl.scala 467:43] + bus_cmd_tag <= _T_1259 @[dma_ctrl.scala 467:37] + bus_cmd_mid <= UInt<1>("h00") @[dma_ctrl.scala 468:37] + bus_cmd_prty <= UInt<1>("h00") @[dma_ctrl.scala 469:37] + node _T_1260 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 473:43] + node _T_1261 = and(_T_1260, rdbuf_vld) @[dma_ctrl.scala 473:60] + node _T_1262 = eq(_T_1261, UInt<1>("h01")) @[dma_ctrl.scala 473:73] + node _T_1263 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 473:111] + node _T_1264 = mux(_T_1262, axi_mstr_priority, _T_1263) @[dma_ctrl.scala 473:31] + axi_mstr_sel <= _T_1264 @[dma_ctrl.scala 473:25] + node axi_mstr_prty_in = not(axi_mstr_priority) @[dma_ctrl.scala 474:27] + node _T_1265 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 478:55] + reg _T_1266 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1265 : @[Reg.scala 28:19] + _T_1266 <= axi_mstr_prty_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - axi_mstr_priority <= _T_1246 @[dma_ctrl.scala 473:27] - node _T_1247 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 477:39] - node _T_1248 = bits(_T_1247, 0, 0) @[dma_ctrl.scala 477:39] - node _T_1249 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 477:59] - node _T_1250 = bits(_T_1249, 0, 0) @[dma_ctrl.scala 477:59] - node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[dma_ctrl.scala 477:50] - node _T_1252 = and(_T_1248, _T_1251) @[dma_ctrl.scala 477:48] - node _T_1253 = dshr(fifo_done_bus, RspPtr) @[dma_ctrl.scala 477:83] - node _T_1254 = bits(_T_1253, 0, 0) @[dma_ctrl.scala 477:83] - node axi_rsp_valid = and(_T_1252, _T_1254) @[dma_ctrl.scala 477:68] - node _T_1255 = dshr(fifo_write, RspPtr) @[dma_ctrl.scala 479:39] - node axi_rsp_write = bits(_T_1255, 0, 0) @[dma_ctrl.scala 479:39] - node _T_1256 = bits(fifo_error[RspPtr], 0, 0) @[dma_ctrl.scala 480:51] - node _T_1257 = bits(fifo_error[RspPtr], 1, 1) @[dma_ctrl.scala 480:83] - node _T_1258 = mux(_T_1257, UInt<2>("h03"), UInt<1>("h00")) @[dma_ctrl.scala 480:64] - node axi_rsp_error = mux(_T_1256, UInt<2>("h02"), _T_1258) @[dma_ctrl.scala 480:32] - node _T_1259 = and(axi_rsp_valid, axi_rsp_write) @[dma_ctrl.scala 486:44] - io.dma_axi.b.valid <= _T_1259 @[dma_ctrl.scala 486:27] - node _T_1260 = bits(axi_rsp_error, 1, 0) @[dma_ctrl.scala 487:57] - io.dma_axi.b.bits.resp <= _T_1260 @[dma_ctrl.scala 487:41] - io.dma_axi.b.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 488:33] - node _T_1261 = eq(axi_rsp_write, UInt<1>("h00")) @[dma_ctrl.scala 490:46] - node _T_1262 = and(axi_rsp_valid, _T_1261) @[dma_ctrl.scala 490:44] - io.dma_axi.r.valid <= _T_1262 @[dma_ctrl.scala 490:27] - io.dma_axi.r.bits.resp <= axi_rsp_error @[dma_ctrl.scala 491:41] - node _T_1263 = bits(fifo_data[RspPtr], 63, 0) @[dma_ctrl.scala 492:59] - io.dma_axi.r.bits.data <= _T_1263 @[dma_ctrl.scala 492:43] - io.dma_axi.r.bits.last <= UInt<1>("h01") @[dma_ctrl.scala 493:41] - io.dma_axi.r.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 494:37] - bus_posted_write_done <= UInt<1>("h00") @[dma_ctrl.scala 496:25] - node _T_1264 = or(io.dma_axi.b.valid, io.dma_axi.r.valid) @[dma_ctrl.scala 497:60] - bus_rsp_valid <= _T_1264 @[dma_ctrl.scala 497:37] - node _T_1265 = and(io.dma_axi.b.valid, io.dma_axi.b.ready) @[dma_ctrl.scala 498:61] - node _T_1266 = and(io.dma_axi.r.valid, io.dma_axi.r.ready) @[dma_ctrl.scala 498:105] - node _T_1267 = or(_T_1265, _T_1266) @[dma_ctrl.scala 498:83] - bus_rsp_sent <= _T_1267 @[dma_ctrl.scala 498:37] - io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 499:40] - io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 500:41] - io.ifu_dma.dma_mem_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[dma_ctrl.scala 501:37] - io.ifu_dma.dma_mem_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 502:39] - io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 503:40] - io.ifu_dma.dma_mem_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[dma_ctrl.scala 504:40] - io.ifu_dma.dma_mem_ctl.dma_mem_tag <= io.lsu_dma.dma_mem_tag @[dma_ctrl.scala 505:38] + axi_mstr_priority <= _T_1266 @[dma_ctrl.scala 477:27] + node _T_1267 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 481:39] + node _T_1268 = bits(_T_1267, 0, 0) @[dma_ctrl.scala 481:39] + node _T_1269 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 481:59] + node _T_1270 = bits(_T_1269, 0, 0) @[dma_ctrl.scala 481:59] + node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[dma_ctrl.scala 481:50] + node _T_1272 = and(_T_1268, _T_1271) @[dma_ctrl.scala 481:48] + node _T_1273 = dshr(fifo_done_bus, RspPtr) @[dma_ctrl.scala 481:83] + node _T_1274 = bits(_T_1273, 0, 0) @[dma_ctrl.scala 481:83] + node axi_rsp_valid = and(_T_1272, _T_1274) @[dma_ctrl.scala 481:68] + node _T_1275 = dshr(fifo_write, RspPtr) @[dma_ctrl.scala 483:39] + node axi_rsp_write = bits(_T_1275, 0, 0) @[dma_ctrl.scala 483:39] + node _T_1276 = bits(fifo_error[RspPtr], 0, 0) @[dma_ctrl.scala 484:51] + node _T_1277 = bits(fifo_error[RspPtr], 1, 1) @[dma_ctrl.scala 484:83] + node _T_1278 = mux(_T_1277, UInt<2>("h03"), UInt<1>("h00")) @[dma_ctrl.scala 484:64] + node axi_rsp_error = mux(_T_1276, UInt<2>("h02"), _T_1278) @[dma_ctrl.scala 484:32] + node _T_1279 = and(axi_rsp_valid, axi_rsp_write) @[dma_ctrl.scala 490:44] + io.dma_axi.b.valid <= _T_1279 @[dma_ctrl.scala 490:27] + node _T_1280 = bits(axi_rsp_error, 1, 0) @[dma_ctrl.scala 491:57] + io.dma_axi.b.bits.resp <= _T_1280 @[dma_ctrl.scala 491:41] + io.dma_axi.b.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 492:33] + node _T_1281 = eq(axi_rsp_write, UInt<1>("h00")) @[dma_ctrl.scala 494:46] + node _T_1282 = and(axi_rsp_valid, _T_1281) @[dma_ctrl.scala 494:44] + io.dma_axi.r.valid <= _T_1282 @[dma_ctrl.scala 494:27] + io.dma_axi.r.bits.resp <= axi_rsp_error @[dma_ctrl.scala 495:41] + node _T_1283 = bits(fifo_data[RspPtr], 63, 0) @[dma_ctrl.scala 496:59] + io.dma_axi.r.bits.data <= _T_1283 @[dma_ctrl.scala 496:43] + io.dma_axi.r.bits.last <= UInt<1>("h01") @[dma_ctrl.scala 497:41] + io.dma_axi.r.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 498:37] + bus_posted_write_done <= UInt<1>("h00") @[dma_ctrl.scala 500:25] + node _T_1284 = or(io.dma_axi.b.valid, io.dma_axi.r.valid) @[dma_ctrl.scala 501:60] + bus_rsp_valid <= _T_1284 @[dma_ctrl.scala 501:37] + node _T_1285 = and(io.dma_axi.b.valid, io.dma_axi.b.ready) @[dma_ctrl.scala 502:61] + node _T_1286 = and(io.dma_axi.r.valid, io.dma_axi.r.ready) @[dma_ctrl.scala 502:105] + node _T_1287 = or(_T_1285, _T_1286) @[dma_ctrl.scala 502:83] + bus_rsp_sent <= _T_1287 @[dma_ctrl.scala 502:37] + io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 503:40] + io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 504:41] + io.ifu_dma.dma_mem_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[dma_ctrl.scala 505:37] + io.ifu_dma.dma_mem_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 506:39] + io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 507:40] + io.ifu_dma.dma_mem_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[dma_ctrl.scala 508:40] + io.ifu_dma.dma_mem_ctl.dma_mem_tag <= io.lsu_dma.dma_mem_tag @[dma_ctrl.scala 509:38] diff --git a/dma_ctrl.v b/dma_ctrl.v index 27cdb2ae..fa7e5608 100644 --- a/dma_ctrl.v +++ b/dma_ctrl.v @@ -231,18 +231,18 @@ module dma_ctrl( wire rvclkhdr_9_io_clk; // @[lib.scala 352:23] wire rvclkhdr_9_io_en; // @[lib.scala 352:23] wire rvclkhdr_9_io_scan_mode; // @[lib.scala 352:23] - wire dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 385:32] - wire dma_buffer_c1cgc_io_clk; // @[dma_ctrl.scala 385:32] - wire dma_buffer_c1cgc_io_en; // @[dma_ctrl.scala 385:32] - wire dma_buffer_c1cgc_io_scan_mode; // @[dma_ctrl.scala 385:32] - wire dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 391:28] - wire dma_free_cgc_io_clk; // @[dma_ctrl.scala 391:28] - wire dma_free_cgc_io_en; // @[dma_ctrl.scala 391:28] - wire dma_free_cgc_io_scan_mode; // @[dma_ctrl.scala 391:28] - wire dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 397:27] - wire dma_bus_cgc_io_clk; // @[dma_ctrl.scala 397:27] - wire dma_bus_cgc_io_en; // @[dma_ctrl.scala 397:27] - wire dma_bus_cgc_io_scan_mode; // @[dma_ctrl.scala 397:27] + wire dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 389:32] + wire dma_buffer_c1cgc_io_clk; // @[dma_ctrl.scala 389:32] + wire dma_buffer_c1cgc_io_en; // @[dma_ctrl.scala 389:32] + wire dma_buffer_c1cgc_io_scan_mode; // @[dma_ctrl.scala 389:32] + wire dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 395:28] + wire dma_free_cgc_io_clk; // @[dma_ctrl.scala 395:28] + wire dma_free_cgc_io_en; // @[dma_ctrl.scala 395:28] + wire dma_free_cgc_io_scan_mode; // @[dma_ctrl.scala 395:28] + wire dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 401:27] + wire dma_bus_cgc_io_clk; // @[dma_ctrl.scala 401:27] + wire dma_bus_cgc_io_en; // @[dma_ctrl.scala 401:27] + wire dma_bus_cgc_io_scan_mode; // @[dma_ctrl.scala 401:27] wire rvclkhdr_10_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_10_io_clk; // @[lib.scala 352:23] wire rvclkhdr_10_io_en; // @[lib.scala 352:23] @@ -255,31 +255,31 @@ module dma_ctrl( wire rvclkhdr_12_io_clk; // @[lib.scala 352:23] wire rvclkhdr_12_io_en; // @[lib.scala 352:23] wire rvclkhdr_12_io_scan_mode; // @[lib.scala 352:23] - wire dma_free_clk = dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 168:26 dma_ctrl.scala 395:29] + wire dma_free_clk = dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 168:26 dma_ctrl.scala 399:29] reg [2:0] RdPtr; // @[Reg.scala 27:20] reg [31:0] fifo_addr_4; // @[lib.scala 358:16] reg [31:0] fifo_addr_3; // @[lib.scala 358:16] reg [31:0] fifo_addr_2; // @[lib.scala 358:16] reg [31:0] fifo_addr_1; // @[lib.scala 358:16] reg [31:0] fifo_addr_0; // @[lib.scala 358:16] - wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 351:20] - wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[dma_ctrl.scala 351:20] - wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[dma_ctrl.scala 351:20] - wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[dma_ctrl.scala 351:20] + wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 355:20] + wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[dma_ctrl.scala 355:20] + wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[dma_ctrl.scala 355:20] + wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[dma_ctrl.scala 355:20] wire dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[lib.scala 345:39] wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 345:39] wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 345:39] - wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 401:28] - reg wrbuf_vld; // @[dma_ctrl.scala 411:59] - reg wrbuf_data_vld; // @[dma_ctrl.scala 413:59] - wire _T_1240 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 469:43] - reg rdbuf_vld; // @[dma_ctrl.scala 437:47] - wire _T_1241 = _T_1240 & rdbuf_vld; // @[dma_ctrl.scala 469:60] + wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 405:28] + reg wrbuf_vld; // @[dma_ctrl.scala 415:59] + reg wrbuf_data_vld; // @[dma_ctrl.scala 417:59] + wire _T_1260 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 473:43] + reg rdbuf_vld; // @[dma_ctrl.scala 441:47] + wire _T_1261 = _T_1260 & rdbuf_vld; // @[dma_ctrl.scala 473:60] reg axi_mstr_priority; // @[Reg.scala 27:20] - wire axi_mstr_sel = _T_1241 ? axi_mstr_priority : _T_1240; // @[dma_ctrl.scala 469:31] + wire axi_mstr_sel = _T_1261 ? axi_mstr_priority : _T_1260; // @[dma_ctrl.scala 473:31] reg [31:0] wrbuf_addr; // @[lib.scala 358:16] reg [31:0] rdbuf_addr; // @[lib.scala 358:16] - wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 459:43] + wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 463:43] wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 195:91] wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 195:91] wire [18:0] _T_18 = 19'hf << _T_17; // @[dma_ctrl.scala 195:83] @@ -288,15 +288,15 @@ module dma_ctrl( wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58] reg [2:0] wrbuf_sz; // @[Reg.scala 27:20] reg [2:0] rdbuf_sz; // @[Reg.scala 27:20] - wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 460:45] + wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 464:45] wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[dma_ctrl.scala 197:33] wire fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 199:33] - wire bus_cmd_valid = _T_1240 | rdbuf_vld; // @[dma_ctrl.scala 455:69] - reg fifo_full; // @[dma_ctrl.scala 369:12] - reg dbg_dma_bubble_bus; // @[dma_ctrl.scala 373:12] + wire bus_cmd_valid = _T_1260 | rdbuf_vld; // @[dma_ctrl.scala 459:69] + reg fifo_full; // @[dma_ctrl.scala 373:12] + reg dbg_dma_bubble_bus; // @[dma_ctrl.scala 377:12] wire _T_989 = fifo_full | dbg_dma_bubble_bus; // @[dma_ctrl.scala 299:39] wire dma_fifo_ready = ~_T_989; // @[dma_ctrl.scala 299:27] - wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 456:54] + wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 460:54] wire _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 206:80] wire _T_31 = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 206:136] wire _T_32 = _T_28 | _T_31; // @[dma_ctrl.scala 206:101] @@ -333,7 +333,7 @@ module dma_ctrl( wire [4:0] _T_992 = fifo_done >> RdPtr; // @[dma_ctrl.scala 303:58] wire _T_994 = ~_T_992[0]; // @[dma_ctrl.scala 303:48] wire _T_995 = _T_990[0] & _T_994; // @[dma_ctrl.scala 303:46] - wire dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 172:31 dma_ctrl.scala 389:33] + wire dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 172:31 dma_ctrl.scala 393:33] reg _T_886; // @[Reg.scala 27:20] reg _T_884; // @[Reg.scala 27:20] reg _T_882; // @[Reg.scala 27:20] @@ -353,10 +353,10 @@ module dma_ctrl( reg [2:0] fifo_sz_2; // @[Reg.scala 27:20] reg [2:0] fifo_sz_1; // @[Reg.scala 27:20] reg [2:0] fifo_sz_0; // @[Reg.scala 27:20] - wire [2:0] _GEN_65 = 3'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[dma_ctrl.scala 352:20] - wire [2:0] _GEN_66 = 3'h2 == RdPtr ? fifo_sz_2 : _GEN_65; // @[dma_ctrl.scala 352:20] - wire [2:0] _GEN_67 = 3'h3 == RdPtr ? fifo_sz_3 : _GEN_66; // @[dma_ctrl.scala 352:20] - wire [2:0] dma_mem_sz_int = 3'h4 == RdPtr ? fifo_sz_4 : _GEN_67; // @[dma_ctrl.scala 352:20] + wire [2:0] _GEN_65 = 3'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[dma_ctrl.scala 356:20] + wire [2:0] _GEN_66 = 3'h2 == RdPtr ? fifo_sz_2 : _GEN_65; // @[dma_ctrl.scala 356:20] + wire [2:0] _GEN_67 = 3'h3 == RdPtr ? fifo_sz_3 : _GEN_66; // @[dma_ctrl.scala 356:20] + wire [2:0] dma_mem_sz_int = 3'h4 == RdPtr ? fifo_sz_4 : _GEN_67; // @[dma_ctrl.scala 356:20] wire _T_1012 = dma_mem_sz_int == 3'h1; // @[dma_ctrl.scala 305:28] wire _T_1014 = _T_1012 & dma_mem_addr_int[0]; // @[dma_ctrl.scala 305:37] wire _T_1016 = dma_mem_sz_int == 3'h2; // @[dma_ctrl.scala 306:29] @@ -383,33 +383,48 @@ module dma_ctrl( reg [7:0] fifo_byteen_2; // @[Reg.scala 27:20] reg [7:0] fifo_byteen_1; // @[Reg.scala 27:20] reg [7:0] fifo_byteen_0; // @[Reg.scala 27:20] - wire [7:0] _GEN_70 = 3'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[dma_ctrl.scala 355:20] - wire [7:0] _GEN_71 = 3'h2 == RdPtr ? fifo_byteen_2 : _GEN_70; // @[dma_ctrl.scala 355:20] - wire [7:0] _GEN_72 = 3'h3 == RdPtr ? fifo_byteen_3 : _GEN_71; // @[dma_ctrl.scala 355:20] - wire [7:0] dma_mem_byteen = 3'h4 == RdPtr ? fifo_byteen_4 : _GEN_72; // @[dma_ctrl.scala 355:20] - wire [3:0] _T_1059 = _T_1048 ? dma_mem_byteen[3:0] : 4'h0; // @[Mux.scala 27:72] + wire [7:0] _GEN_70 = 3'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[dma_ctrl.scala 359:20] + wire [7:0] _GEN_71 = 3'h2 == RdPtr ? fifo_byteen_2 : _GEN_70; // @[dma_ctrl.scala 359:20] + wire [7:0] _GEN_72 = 3'h3 == RdPtr ? fifo_byteen_3 : _GEN_71; // @[dma_ctrl.scala 359:20] + wire [7:0] dma_mem_byteen = 3'h4 == RdPtr ? fifo_byteen_4 : _GEN_72; // @[dma_ctrl.scala 359:20] + wire [3:0] _T_1071 = _T_1048 ? dma_mem_byteen[3:0] : 4'h0; // @[Mux.scala 27:72] wire _T_1051 = dma_mem_addr_int[2:0] == 3'h1; // @[dma_ctrl.scala 311:32] - wire [3:0] _T_1060 = _T_1051 ? dma_mem_byteen[4:1] : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1063 = _T_1059 | _T_1060; // @[Mux.scala 27:72] + wire [3:0] _T_1072 = _T_1051 ? dma_mem_byteen[4:1] : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1079 = _T_1071 | _T_1072; // @[Mux.scala 27:72] wire _T_1054 = dma_mem_addr_int[2:0] == 3'h2; // @[dma_ctrl.scala 312:32] - wire [3:0] _T_1061 = _T_1054 ? dma_mem_byteen[5:2] : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1064 = _T_1063 | _T_1061; // @[Mux.scala 27:72] + wire [3:0] _T_1073 = _T_1054 ? dma_mem_byteen[5:2] : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1080 = _T_1079 | _T_1073; // @[Mux.scala 27:72] wire _T_1057 = dma_mem_addr_int[2:0] == 3'h3; // @[dma_ctrl.scala 313:32] - wire [3:0] _T_1062 = _T_1057 ? dma_mem_byteen[6:3] : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1065 = _T_1064 | _T_1062; // @[Mux.scala 27:72] - wire _T_1067 = _T_1065 != 4'hf; // @[dma_ctrl.scala 313:68] - wire _T_1068 = _T_1046 & _T_1067; // @[dma_ctrl.scala 310:78] - wire _T_1069 = _T_1043 | _T_1068; // @[dma_ctrl.scala 309:145] - wire _T_1072 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1022; // @[dma_ctrl.scala 314:45] - wire _T_1074 = dma_mem_byteen == 8'hf; // @[dma_ctrl.scala 314:103] - wire _T_1076 = dma_mem_byteen == 8'hf0; // @[dma_ctrl.scala 314:139] - wire _T_1077 = _T_1074 | _T_1076; // @[dma_ctrl.scala 314:116] - wire _T_1079 = dma_mem_byteen == 8'hff; // @[dma_ctrl.scala 314:175] - wire _T_1080 = _T_1077 | _T_1079; // @[dma_ctrl.scala 314:152] - wire _T_1081 = ~_T_1080; // @[dma_ctrl.scala 314:80] - wire _T_1082 = _T_1072 & _T_1081; // @[dma_ctrl.scala 314:78] - wire _T_1083 = _T_1069 | _T_1082; // @[dma_ctrl.scala 313:79] - wire dma_alignment_error = _T_1010 & _T_1083; // @[dma_ctrl.scala 304:87] + wire [3:0] _T_1074 = _T_1057 ? dma_mem_byteen[6:3] : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1081 = _T_1080 | _T_1074; // @[Mux.scala 27:72] + wire _T_1060 = dma_mem_addr_int[2:0] == 3'h4; // @[dma_ctrl.scala 314:32] + wire [3:0] _T_1075 = _T_1060 ? dma_mem_byteen[7:4] : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1082 = _T_1081 | _T_1075; // @[Mux.scala 27:72] + wire _T_1063 = dma_mem_addr_int[2:0] == 3'h5; // @[dma_ctrl.scala 315:32] + wire [2:0] _T_1076 = _T_1063 ? dma_mem_byteen[7:5] : 3'h0; // @[Mux.scala 27:72] + wire [3:0] _GEN_91 = {{1'd0}, _T_1076}; // @[Mux.scala 27:72] + wire [3:0] _T_1083 = _T_1082 | _GEN_91; // @[Mux.scala 27:72] + wire _T_1066 = dma_mem_addr_int[2:0] == 3'h6; // @[dma_ctrl.scala 316:32] + wire [1:0] _T_1077 = _T_1066 ? dma_mem_byteen[7:6] : 2'h0; // @[Mux.scala 27:72] + wire [3:0] _GEN_92 = {{2'd0}, _T_1077}; // @[Mux.scala 27:72] + wire [3:0] _T_1084 = _T_1083 | _GEN_92; // @[Mux.scala 27:72] + wire _T_1069 = dma_mem_addr_int[2:0] == 3'h7; // @[dma_ctrl.scala 317:32] + wire _T_1078 = _T_1069 & dma_mem_byteen[7]; // @[Mux.scala 27:72] + wire [3:0] _GEN_93 = {{3'd0}, _T_1078}; // @[Mux.scala 27:72] + wire [3:0] _T_1085 = _T_1084 | _GEN_93; // @[Mux.scala 27:72] + wire _T_1087 = _T_1085 != 4'hf; // @[dma_ctrl.scala 317:66] + wire _T_1088 = _T_1046 & _T_1087; // @[dma_ctrl.scala 310:78] + wire _T_1089 = _T_1043 | _T_1088; // @[dma_ctrl.scala 309:145] + wire _T_1092 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1022; // @[dma_ctrl.scala 318:45] + wire _T_1094 = dma_mem_byteen == 8'hf; // @[dma_ctrl.scala 318:103] + wire _T_1096 = dma_mem_byteen == 8'hf0; // @[dma_ctrl.scala 318:139] + wire _T_1097 = _T_1094 | _T_1096; // @[dma_ctrl.scala 318:116] + wire _T_1099 = dma_mem_byteen == 8'hff; // @[dma_ctrl.scala 318:175] + wire _T_1100 = _T_1097 | _T_1099; // @[dma_ctrl.scala 318:152] + wire _T_1101 = ~_T_1100; // @[dma_ctrl.scala 318:80] + wire _T_1102 = _T_1092 & _T_1101; // @[dma_ctrl.scala 318:78] + wire _T_1103 = _T_1089 | _T_1102; // @[dma_ctrl.scala 317:79] + wire dma_alignment_error = _T_1010 & _T_1103; // @[dma_ctrl.scala 304:87] wire _T_79 = dma_address_error | dma_alignment_error; // @[dma_ctrl.scala 208:258] wire _T_80 = 3'h0 == RdPtr; // @[dma_ctrl.scala 208:288] wire _T_81 = _T_79 & _T_80; // @[dma_ctrl.scala 208:281] @@ -470,12 +485,12 @@ module dma_ctrl( wire _T_184 = _T_167 & _T_134; // @[dma_ctrl.scala 210:174] wire _T_189 = _T_167 & _T_152; // @[dma_ctrl.scala 210:174] wire [4:0] fifo_pend_en = {_T_189,_T_184,_T_179,_T_174,_T_169}; // @[Cat.scala 29:58] - wire _T_1107 = _T_995 & _T_996[0]; // @[dma_ctrl.scala 324:66] - wire _T_1109 = _T_1000 | dma_mem_addr_in_pic; // @[dma_ctrl.scala 324:134] - wire _T_1110 = ~_T_1109; // @[dma_ctrl.scala 324:88] - wire _T_1113 = dma_mem_sz_int[1:0] != 2'h2; // @[dma_ctrl.scala 324:191] - wire _T_1114 = _T_1110 | _T_1113; // @[dma_ctrl.scala 324:167] - wire dma_dbg_cmd_error = _T_1107 & _T_1114; // @[dma_ctrl.scala 324:84] + wire _T_1127 = _T_995 & _T_996[0]; // @[dma_ctrl.scala 328:66] + wire _T_1129 = _T_1000 | dma_mem_addr_in_pic; // @[dma_ctrl.scala 328:134] + wire _T_1130 = ~_T_1129; // @[dma_ctrl.scala 328:88] + wire _T_1133 = dma_mem_sz_int[1:0] != 2'h2; // @[dma_ctrl.scala 328:191] + wire _T_1134 = _T_1130 | _T_1133; // @[dma_ctrl.scala 328:167] + wire dma_dbg_cmd_error = _T_1127 & _T_1134; // @[dma_ctrl.scala 328:84] wire _T_197 = _T_79 | dma_dbg_cmd_error; // @[dma_ctrl.scala 212:114] wire _T_199 = _T_197 & _T_80; // @[dma_ctrl.scala 212:135] wire _T_200 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[dma_ctrl.scala 212:198] @@ -571,9 +586,9 @@ module dma_ctrl( wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75] wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58] - wire _T_1265 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 498:61] - wire _T_1266 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 498:105] - wire bus_rsp_sent = _T_1265 | _T_1266; // @[dma_ctrl.scala 498:83] + wire _T_1285 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 502:61] + wire _T_1286 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 502:105] + wire bus_rsp_sent = _T_1285 | _T_1286; // @[dma_ctrl.scala 502:83] wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99] wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120] reg [2:0] RspPtr; // @[Reg.scala 27:20] @@ -658,7 +673,7 @@ module dma_ctrl( reg fifo_tag_0; // @[Reg.scala 27:20] reg wrbuf_tag; // @[Reg.scala 27:20] reg rdbuf_tag; // @[Reg.scala 27:20] - wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 463:43] + wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 467:43] reg fifo_tag_1; // @[Reg.scala 27:20] reg fifo_tag_2; // @[Reg.scala 27:20] reg fifo_tag_3; // @[Reg.scala 27:20] @@ -672,6 +687,9 @@ module dma_ctrl( wire WrPtrEn = |fifo_cmd_en; // @[dma_ctrl.scala 266:30] wire RdPtrEn = _T_165 | _T_197; // @[dma_ctrl.scala 268:93] wire RspPtrEn = io_dma_dbg_cmd_done | _T_406; // @[dma_ctrl.scala 270:39] + wire [3:0] _T_959 = {3'h0,axi_mstr_prty_en}; // @[Cat.scala 29:58] + wire [3:0] _T_961 = {3'h0,bus_rsp_sent}; // @[Cat.scala 29:58] + wire [3:0] num_fifo_vld_tmp = _T_959 - _T_961; // @[dma_ctrl.scala 291:62] wire [3:0] _T_966 = {3'h0,fifo_valid[0]}; // @[Cat.scala 29:58] wire [3:0] _T_969 = {3'h0,fifo_valid[1]}; // @[Cat.scala 29:58] wire [3:0] _T_972 = {3'h0,fifo_valid[2]}; // @[Cat.scala 29:58] @@ -681,91 +699,92 @@ module dma_ctrl( wire [3:0] _T_982 = _T_980 + _T_972; // @[dma_ctrl.scala 293:102] wire [3:0] _T_984 = _T_982 + _T_975; // @[dma_ctrl.scala 293:102] wire [3:0] num_fifo_vld_tmp2 = _T_984 + _T_978; // @[dma_ctrl.scala 293:102] - wire _T_1123 = |fifo_valid; // @[dma_ctrl.scala 334:30] - wire fifo_empty = ~_T_1123; // @[dma_ctrl.scala 334:17] - wire [4:0] _T_1086 = fifo_valid >> RspPtr; // @[dma_ctrl.scala 320:39] - wire [4:0] _T_1088 = fifo_dbg >> RspPtr; // @[dma_ctrl.scala 320:58] - wire _T_1090 = _T_1086[0] & _T_1088[0]; // @[dma_ctrl.scala 320:48] - wire [4:0] _T_1091 = fifo_done >> RspPtr; // @[dma_ctrl.scala 320:78] - wire [31:0] _GEN_44 = 3'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 321:49] - wire [31:0] _GEN_45 = 3'h2 == RspPtr ? fifo_addr_2 : _GEN_44; // @[dma_ctrl.scala 321:49] - wire [31:0] _GEN_46 = 3'h3 == RspPtr ? fifo_addr_3 : _GEN_45; // @[dma_ctrl.scala 321:49] - wire [31:0] _GEN_47 = 3'h4 == RspPtr ? fifo_addr_4 : _GEN_46; // @[dma_ctrl.scala 321:49] - wire [63:0] _GEN_49 = 3'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 321:71] - wire [63:0] _GEN_50 = 3'h2 == RspPtr ? fifo_data_2 : _GEN_49; // @[dma_ctrl.scala 321:71] - wire [63:0] _GEN_51 = 3'h3 == RspPtr ? fifo_data_3 : _GEN_50; // @[dma_ctrl.scala 321:71] - wire [63:0] _GEN_52 = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 321:71] - wire [1:0] _GEN_54 = 3'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[dma_ctrl.scala 322:47] - wire [1:0] _GEN_55 = 3'h2 == RspPtr ? fifo_error_2 : _GEN_54; // @[dma_ctrl.scala 322:47] - wire [1:0] _GEN_56 = 3'h3 == RspPtr ? fifo_error_3 : _GEN_55; // @[dma_ctrl.scala 322:47] - wire [1:0] _GEN_57 = 3'h4 == RspPtr ? fifo_error_4 : _GEN_56; // @[dma_ctrl.scala 322:47] - wire _T_1116 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[dma_ctrl.scala 328:80] - wire [4:0] _T_1145 = fifo_rpend >> RdPtr; // @[dma_ctrl.scala 347:54] - wire _T_1147 = ~_T_1145[0]; // @[dma_ctrl.scala 347:43] - wire _T_1148 = _T_990[0] & _T_1147; // @[dma_ctrl.scala 347:41] - wire _T_1152 = _T_1148 & _T_994; // @[dma_ctrl.scala 347:62] - wire _T_1155 = ~_T_197; // @[dma_ctrl.scala 347:84] - wire dma_mem_req = _T_1152 & _T_1155; // @[dma_ctrl.scala 347:82] - wire _T_1117 = dma_mem_req & _T_1116; // @[dma_ctrl.scala 328:56] + wire [3:0] num_fifo_vld = num_fifo_vld_tmp + num_fifo_vld_tmp2; // @[dma_ctrl.scala 295:45] + wire _T_1143 = |fifo_valid; // @[dma_ctrl.scala 338:30] + wire fifo_empty = ~_T_1143; // @[dma_ctrl.scala 338:17] + wire [4:0] _T_1106 = fifo_valid >> RspPtr; // @[dma_ctrl.scala 324:39] + wire [4:0] _T_1108 = fifo_dbg >> RspPtr; // @[dma_ctrl.scala 324:58] + wire _T_1110 = _T_1106[0] & _T_1108[0]; // @[dma_ctrl.scala 324:48] + wire [4:0] _T_1111 = fifo_done >> RspPtr; // @[dma_ctrl.scala 324:78] + wire [31:0] _GEN_44 = 3'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 325:49] + wire [31:0] _GEN_45 = 3'h2 == RspPtr ? fifo_addr_2 : _GEN_44; // @[dma_ctrl.scala 325:49] + wire [31:0] _GEN_46 = 3'h3 == RspPtr ? fifo_addr_3 : _GEN_45; // @[dma_ctrl.scala 325:49] + wire [31:0] _GEN_47 = 3'h4 == RspPtr ? fifo_addr_4 : _GEN_46; // @[dma_ctrl.scala 325:49] + wire [63:0] _GEN_49 = 3'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 325:71] + wire [63:0] _GEN_50 = 3'h2 == RspPtr ? fifo_data_2 : _GEN_49; // @[dma_ctrl.scala 325:71] + wire [63:0] _GEN_51 = 3'h3 == RspPtr ? fifo_data_3 : _GEN_50; // @[dma_ctrl.scala 325:71] + wire [63:0] _GEN_52 = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 325:71] + wire [1:0] _GEN_54 = 3'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[dma_ctrl.scala 326:47] + wire [1:0] _GEN_55 = 3'h2 == RspPtr ? fifo_error_2 : _GEN_54; // @[dma_ctrl.scala 326:47] + wire [1:0] _GEN_56 = 3'h3 == RspPtr ? fifo_error_3 : _GEN_55; // @[dma_ctrl.scala 326:47] + wire [1:0] _GEN_57 = 3'h4 == RspPtr ? fifo_error_4 : _GEN_56; // @[dma_ctrl.scala 326:47] + wire _T_1136 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[dma_ctrl.scala 332:80] + wire [4:0] _T_1165 = fifo_rpend >> RdPtr; // @[dma_ctrl.scala 351:54] + wire _T_1167 = ~_T_1165[0]; // @[dma_ctrl.scala 351:43] + wire _T_1168 = _T_990[0] & _T_1167; // @[dma_ctrl.scala 351:41] + wire _T_1172 = _T_1168 & _T_994; // @[dma_ctrl.scala 351:62] + wire _T_1175 = ~_T_197; // @[dma_ctrl.scala 351:84] + wire dma_mem_req = _T_1172 & _T_1175; // @[dma_ctrl.scala 351:82] + wire _T_1137 = dma_mem_req & _T_1136; // @[dma_ctrl.scala 332:56] reg [2:0] dma_nack_count; // @[Reg.scala 27:20] - wire _T_1118 = dma_nack_count >= io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[dma_ctrl.scala 328:121] - wire _T_1120 = dma_mem_req & dma_mem_addr_in_iccm; // @[dma_ctrl.scala 329:56] - wire _T_1127 = ~_T_165; // @[dma_ctrl.scala 339:77] - wire [2:0] _T_1129 = _T_1127 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_1131 = _T_1129 & dma_nack_count; // @[dma_ctrl.scala 339:155] - wire _T_1135 = dma_mem_req & _T_1127; // @[dma_ctrl.scala 339:203] - wire [2:0] _T_1138 = dma_nack_count + 3'h1; // @[dma_ctrl.scala 339:304] - wire _T_1164 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1076; // @[dma_ctrl.scala 353:84] - wire [31:0] _T_1168 = {dma_mem_addr_int[31:3],1'h1,dma_mem_addr_int[1:0]}; // @[Cat.scala 29:58] - wire _T_1176 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1077; // @[dma_ctrl.scala 354:84] - wire [4:0] _T_1179 = fifo_write >> RdPtr; // @[dma_ctrl.scala 356:53] - wire [63:0] _GEN_75 = 3'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 357:40] - wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 357:40] - wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 357:40] - reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 377:12] - wire _T_1192 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 382:44] - wire _T_1193 = _T_1192 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 382:65] - wire bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 497:60] - wire _T_1194 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 383:44] - wire _T_1195 = _T_1194 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 383:60] - wire _T_1196 = _T_1195 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 383:94] - wire _T_1197 = _T_1196 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 383:116] - wire _T_1199 = _T_1197 | _T_1123; // @[dma_ctrl.scala 383:137] - wire wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 405:47] - wire wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 406:46] - wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 407:40] - wire _T_1201 = ~wrbuf_en; // @[dma_ctrl.scala 408:51] - wire wrbuf_rst = wrbuf_cmd_sent & _T_1201; // @[dma_ctrl.scala 408:49] - wire _T_1203 = ~wrbuf_data_en; // @[dma_ctrl.scala 409:51] - wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1203; // @[dma_ctrl.scala 409:49] - wire _T_1204 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 411:63] - wire _T_1205 = ~wrbuf_rst; // @[dma_ctrl.scala 411:92] - wire _T_1208 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 413:63] - wire _T_1209 = ~wrbuf_data_rst; // @[dma_ctrl.scala 413:102] - wire rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 433:59] - wire _T_1214 = ~axi_mstr_sel; // @[dma_ctrl.scala 434:44] - wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1214; // @[dma_ctrl.scala 434:42] - wire _T_1216 = ~rdbuf_en; // @[dma_ctrl.scala 435:63] - wire rdbuf_rst = rdbuf_cmd_sent & _T_1216; // @[dma_ctrl.scala 435:61] - wire _T_1217 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 437:51] - wire _T_1218 = ~rdbuf_rst; // @[dma_ctrl.scala 437:80] - wire _T_1222 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 449:44] - wire _T_1223 = wrbuf_vld & _T_1222; // @[dma_ctrl.scala 449:42] - wire _T_1226 = wrbuf_data_vld & _T_1222; // @[dma_ctrl.scala 450:47] - wire _T_1228 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 451:44] - wire _T_1229 = rdbuf_vld & _T_1228; // @[dma_ctrl.scala 451:42] - wire axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 470:27] - wire _T_1251 = ~_T_1088[0]; // @[dma_ctrl.scala 477:50] - wire _T_1252 = _T_1086[0] & _T_1251; // @[dma_ctrl.scala 477:48] - wire [4:0] _T_1253 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 477:83] - wire axi_rsp_valid = _T_1252 & _T_1253[0]; // @[dma_ctrl.scala 477:68] - wire [4:0] _T_1255 = fifo_write >> RspPtr; // @[dma_ctrl.scala 479:39] - wire axi_rsp_write = _T_1255[0]; // @[dma_ctrl.scala 479:39] - wire [1:0] _T_1258 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 480:64] - wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 488:33] - wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 488:33] - wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 488:33] - wire _T_1261 = ~axi_rsp_write; // @[dma_ctrl.scala 490:46] + wire _T_1138 = dma_nack_count >= io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[dma_ctrl.scala 332:121] + wire _T_1140 = dma_mem_req & dma_mem_addr_in_iccm; // @[dma_ctrl.scala 333:56] + wire _T_1147 = ~_T_165; // @[dma_ctrl.scala 343:77] + wire [2:0] _T_1149 = _T_1147 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_1151 = _T_1149 & dma_nack_count; // @[dma_ctrl.scala 343:155] + wire _T_1155 = dma_mem_req & _T_1147; // @[dma_ctrl.scala 343:203] + wire [2:0] _T_1158 = dma_nack_count + 3'h1; // @[dma_ctrl.scala 343:304] + wire _T_1184 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1096; // @[dma_ctrl.scala 357:84] + wire [31:0] _T_1188 = {dma_mem_addr_int[31:3],1'h1,dma_mem_addr_int[1:0]}; // @[Cat.scala 29:58] + wire _T_1196 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1097; // @[dma_ctrl.scala 358:84] + wire [4:0] _T_1199 = fifo_write >> RdPtr; // @[dma_ctrl.scala 360:53] + wire [63:0] _GEN_75 = 3'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 361:40] + wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 361:40] + wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 361:40] + reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 381:12] + wire _T_1212 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 386:44] + wire _T_1213 = _T_1212 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 386:65] + wire bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 501:60] + wire _T_1214 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 387:44] + wire _T_1215 = _T_1214 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:60] + wire _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94] + wire _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116] + wire _T_1219 = _T_1217 | _T_1143; // @[dma_ctrl.scala 387:137] + wire wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 409:47] + wire wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 410:46] + wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 411:40] + wire _T_1221 = ~wrbuf_en; // @[dma_ctrl.scala 412:51] + wire wrbuf_rst = wrbuf_cmd_sent & _T_1221; // @[dma_ctrl.scala 412:49] + wire _T_1223 = ~wrbuf_data_en; // @[dma_ctrl.scala 413:51] + wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1223; // @[dma_ctrl.scala 413:49] + wire _T_1224 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 415:63] + wire _T_1225 = ~wrbuf_rst; // @[dma_ctrl.scala 415:92] + wire _T_1228 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 417:63] + wire _T_1229 = ~wrbuf_data_rst; // @[dma_ctrl.scala 417:102] + wire rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 437:59] + wire _T_1234 = ~axi_mstr_sel; // @[dma_ctrl.scala 438:44] + wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1234; // @[dma_ctrl.scala 438:42] + wire _T_1236 = ~rdbuf_en; // @[dma_ctrl.scala 439:63] + wire rdbuf_rst = rdbuf_cmd_sent & _T_1236; // @[dma_ctrl.scala 439:61] + wire _T_1237 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 441:51] + wire _T_1238 = ~rdbuf_rst; // @[dma_ctrl.scala 441:80] + wire _T_1242 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 453:44] + wire _T_1243 = wrbuf_vld & _T_1242; // @[dma_ctrl.scala 453:42] + wire _T_1246 = wrbuf_data_vld & _T_1242; // @[dma_ctrl.scala 454:47] + wire _T_1248 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 455:44] + wire _T_1249 = rdbuf_vld & _T_1248; // @[dma_ctrl.scala 455:42] + wire axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 474:27] + wire _T_1271 = ~_T_1108[0]; // @[dma_ctrl.scala 481:50] + wire _T_1272 = _T_1106[0] & _T_1271; // @[dma_ctrl.scala 481:48] + wire [4:0] _T_1273 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 481:83] + wire axi_rsp_valid = _T_1272 & _T_1273[0]; // @[dma_ctrl.scala 481:68] + wire [4:0] _T_1275 = fifo_write >> RspPtr; // @[dma_ctrl.scala 483:39] + wire axi_rsp_write = _T_1275[0]; // @[dma_ctrl.scala 483:39] + wire [1:0] _T_1278 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 484:64] + wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 492:33] + wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 492:33] + wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 492:33] + wire _T_1281 = ~axi_rsp_write; // @[dma_ctrl.scala 494:46] rvclkhdr rvclkhdr ( // @[lib.scala 352:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -826,19 +845,19 @@ module dma_ctrl( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr dma_buffer_c1cgc ( // @[dma_ctrl.scala 385:32] + rvclkhdr dma_buffer_c1cgc ( // @[dma_ctrl.scala 389:32] .io_l1clk(dma_buffer_c1cgc_io_l1clk), .io_clk(dma_buffer_c1cgc_io_clk), .io_en(dma_buffer_c1cgc_io_en), .io_scan_mode(dma_buffer_c1cgc_io_scan_mode) ); - rvclkhdr dma_free_cgc ( // @[dma_ctrl.scala 391:28] + rvclkhdr dma_free_cgc ( // @[dma_ctrl.scala 395:28] .io_l1clk(dma_free_cgc_io_l1clk), .io_clk(dma_free_cgc_io_clk), .io_en(dma_free_cgc_io_en), .io_scan_mode(dma_free_cgc_io_scan_mode) ); - rvclkhdr dma_bus_cgc ( // @[dma_ctrl.scala 397:27] + rvclkhdr dma_bus_cgc ( // @[dma_ctrl.scala 401:27] .io_l1clk(dma_bus_cgc_io_l1clk), .io_clk(dma_bus_cgc_io_clk), .io_en(dma_bus_cgc_io_en), @@ -862,43 +881,43 @@ module dma_ctrl( .io_en(rvclkhdr_12_io_en), .io_scan_mode(rvclkhdr_12_io_scan_mode) ); - assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[dma_ctrl.scala 321:25] - assign io_dma_dbg_cmd_done = _T_1090 & _T_1091[0]; // @[dma_ctrl.scala 320:25] - assign io_dma_dbg_cmd_fail = |_GEN_57; // @[dma_ctrl.scala 322:25] - assign io_dbg_dma_io_dma_dbg_ready = fifo_empty & dbg_dma_bubble_bus; // @[dma_ctrl.scala 319:36] - assign io_dec_dma_dctl_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dma_ctrl.scala 331:42] - assign io_dec_dma_tlu_dma_dma_pmu_dccm_read = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & _T_166; // @[dma_ctrl.scala 361:42] - assign io_dec_dma_tlu_dma_dma_pmu_dccm_write = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 362:42] - assign io_dec_dma_tlu_dma_dma_pmu_any_read = _T_165 & _T_166; // @[dma_ctrl.scala 363:42] - assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 364:42] - assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1117 & _T_1118; // @[dma_ctrl.scala 328:41] - assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 330:41] - assign io_dma_axi_aw_ready = ~_T_1223; // @[dma_ctrl.scala 449:27] - assign io_dma_axi_w_ready = ~_T_1226; // @[dma_ctrl.scala 450:27] - assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 486:27] - assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1258; // @[dma_ctrl.scala 487:41] - assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 488:33] - assign io_dma_axi_ar_ready = ~_T_1229; // @[dma_ctrl.scala 451:27] - assign io_dma_axi_r_valid = axi_rsp_valid & _T_1261; // @[dma_ctrl.scala 490:27] - assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 494:37] - assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 492:43] - assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1258; // @[dma_ctrl.scala 491:41] - assign io_dma_axi_r_bits_last = 1'h1; // @[dma_ctrl.scala 493:41] - assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1117 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 348:40] - assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1164 ? _T_1168 : dma_mem_addr_int; // @[dma_ctrl.scala 353:40] - assign io_lsu_dma_dma_lsc_ctl_dma_mem_sz = _T_1176 ? 3'h2 : dma_mem_sz_int; // @[dma_ctrl.scala 354:40] - assign io_lsu_dma_dma_lsc_ctl_dma_mem_write = _T_1179[0]; // @[dma_ctrl.scala 356:40] - assign io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[dma_ctrl.scala 357:40] - assign io_lsu_dma_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 499:40] - assign io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 500:41] - assign io_lsu_dma_dma_mem_tag = RdPtr; // @[dma_ctrl.scala 350:28] - assign io_ifu_dma_dma_ifc_dma_iccm_stall_any = _T_1120 & _T_1118; // @[dma_ctrl.scala 329:41] - assign io_ifu_dma_dma_mem_ctl_dma_iccm_req = _T_1120 & io_iccm_ready; // @[dma_ctrl.scala 349:40] - assign io_ifu_dma_dma_mem_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 502:39] - assign io_ifu_dma_dma_mem_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[dma_ctrl.scala 501:37] - assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 504:40] - assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 503:40] - assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 505:38] + assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[dma_ctrl.scala 325:25] + assign io_dma_dbg_cmd_done = _T_1110 & _T_1111[0]; // @[dma_ctrl.scala 324:25] + assign io_dma_dbg_cmd_fail = |_GEN_57; // @[dma_ctrl.scala 326:25] + assign io_dbg_dma_io_dma_dbg_ready = fifo_empty & dbg_dma_bubble_bus; // @[dma_ctrl.scala 323:36] + assign io_dec_dma_dctl_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dma_ctrl.scala 335:42] + assign io_dec_dma_tlu_dma_dma_pmu_dccm_read = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & _T_166; // @[dma_ctrl.scala 365:42] + assign io_dec_dma_tlu_dma_dma_pmu_dccm_write = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 366:42] + assign io_dec_dma_tlu_dma_dma_pmu_any_read = _T_165 & _T_166; // @[dma_ctrl.scala 367:42] + assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 368:42] + assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1137 & _T_1138; // @[dma_ctrl.scala 332:41] + assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 334:41] + assign io_dma_axi_aw_ready = ~_T_1243; // @[dma_ctrl.scala 453:27] + assign io_dma_axi_w_ready = ~_T_1246; // @[dma_ctrl.scala 454:27] + assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 490:27] + assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 491:41] + assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 492:33] + assign io_dma_axi_ar_ready = ~_T_1249; // @[dma_ctrl.scala 455:27] + assign io_dma_axi_r_valid = axi_rsp_valid & _T_1281; // @[dma_ctrl.scala 494:27] + assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 498:37] + assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 496:43] + assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 495:41] + assign io_dma_axi_r_bits_last = 1'h1; // @[dma_ctrl.scala 497:41] + assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40] + assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1184 ? _T_1188 : dma_mem_addr_int; // @[dma_ctrl.scala 357:40] + assign io_lsu_dma_dma_lsc_ctl_dma_mem_sz = _T_1196 ? 3'h2 : dma_mem_sz_int; // @[dma_ctrl.scala 358:40] + assign io_lsu_dma_dma_lsc_ctl_dma_mem_write = _T_1199[0]; // @[dma_ctrl.scala 360:40] + assign io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[dma_ctrl.scala 361:40] + assign io_lsu_dma_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 503:40] + assign io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 504:41] + assign io_lsu_dma_dma_mem_tag = RdPtr; // @[dma_ctrl.scala 354:28] + assign io_ifu_dma_dma_ifc_dma_iccm_stall_any = _T_1140 & _T_1138; // @[dma_ctrl.scala 333:41] + assign io_ifu_dma_dma_mem_ctl_dma_iccm_req = _T_1140 & io_iccm_ready; // @[dma_ctrl.scala 353:40] + assign io_ifu_dma_dma_mem_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 506:39] + assign io_ifu_dma_dma_mem_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[dma_ctrl.scala 505:37] + assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 508:40] + assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 507:40] + assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 509:38] assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[lib.scala 355:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] @@ -929,15 +948,15 @@ module dma_ctrl( assign rvclkhdr_9_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[lib.scala 355:17] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] - assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 388:33] - assign dma_buffer_c1cgc_io_en = _T_1193 | io_clk_override; // @[dma_ctrl.scala 386:33] - assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 387:33] - assign dma_free_cgc_io_clk = clock; // @[dma_ctrl.scala 394:29] - assign dma_free_cgc_io_en = _T_1199 | io_clk_override; // @[dma_ctrl.scala 392:29] - assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 393:29] - assign dma_bus_cgc_io_clk = clock; // @[dma_ctrl.scala 400:28] - assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 398:28] - assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 399:28] + assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 392:33] + assign dma_buffer_c1cgc_io_en = _T_1213 | io_clk_override; // @[dma_ctrl.scala 390:33] + assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 391:33] + assign dma_free_cgc_io_clk = clock; // @[dma_ctrl.scala 398:29] + assign dma_free_cgc_io_en = _T_1219 | io_clk_override; // @[dma_ctrl.scala 396:29] + assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 397:29] + assign dma_bus_cgc_io_clk = clock; // @[dma_ctrl.scala 404:28] + assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 402:28] + assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 403:28] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 355:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] @@ -1452,21 +1471,21 @@ end // initial if (reset) begin wrbuf_vld <= 1'h0; end else begin - wrbuf_vld <= _T_1204 & _T_1205; + wrbuf_vld <= _T_1224 & _T_1225; end end always @(posedge dma_bus_clk or posedge reset) begin if (reset) begin wrbuf_data_vld <= 1'h0; end else begin - wrbuf_data_vld <= _T_1208 & _T_1209; + wrbuf_data_vld <= _T_1228 & _T_1229; end end always @(posedge dma_bus_clk or posedge reset) begin if (reset) begin rdbuf_vld <= 1'h0; end else begin - rdbuf_vld <= _T_1217 & _T_1218; + rdbuf_vld <= _T_1237 & _T_1238; end end always @(posedge dma_bus_clk or posedge reset) begin @@ -1515,7 +1534,7 @@ end // initial if (reset) begin fifo_full <= 1'h0; end else begin - fifo_full <= num_fifo_vld_tmp2 >= 4'h5; + fifo_full <= num_fifo_vld >= 4'h5; end end always @(posedge dma_bus_clk or posedge reset) begin @@ -1864,10 +1883,10 @@ end // initial end else if (fifo_cmd_en[0]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin _T_850 <= io_dbg_dma_dbg_ib_dbg_cmd_write; - end else if (_T_1241) begin + end else if (_T_1261) begin _T_850 <= axi_mstr_priority; end else begin - _T_850 <= _T_1240; + _T_850 <= _T_1260; end end end @@ -1877,10 +1896,10 @@ end // initial end else if (fifo_cmd_en[1]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin _T_852 <= io_dbg_dma_dbg_ib_dbg_cmd_write; - end else if (_T_1241) begin + end else if (_T_1261) begin _T_852 <= axi_mstr_priority; end else begin - _T_852 <= _T_1240; + _T_852 <= _T_1260; end end end @@ -1890,10 +1909,10 @@ end // initial end else if (fifo_cmd_en[2]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin _T_854 <= io_dbg_dma_dbg_ib_dbg_cmd_write; - end else if (_T_1241) begin + end else if (_T_1261) begin _T_854 <= axi_mstr_priority; end else begin - _T_854 <= _T_1240; + _T_854 <= _T_1260; end end end @@ -1903,10 +1922,10 @@ end // initial end else if (fifo_cmd_en[3]) begin if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin _T_856 <= io_dbg_dma_dbg_ib_dbg_cmd_write; - end else if (_T_1241) begin + end else if (_T_1261) begin _T_856 <= axi_mstr_priority; end else begin - _T_856 <= _T_1240; + _T_856 <= _T_1260; end end end @@ -2059,10 +2078,10 @@ end // initial if (reset) begin dma_nack_count <= 3'h0; end else if (dma_mem_req) begin - if (_T_1118) begin - dma_nack_count <= _T_1131; - end else if (_T_1135) begin - dma_nack_count <= _T_1138; + if (_T_1138) begin + dma_nack_count <= _T_1151; + end else if (_T_1155) begin + dma_nack_count <= _T_1158; end else begin dma_nack_count <= 3'h0; end diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 67bd698b..622b991f 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -2324,26 +2324,6 @@ circuit quasar_wrapper : input reset : AsyncReset output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip ifu_bus_clk_en : UInt<1>, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, flip ifu_fetch_val : UInt<2>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, ifu_async_error_start : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, flip scan_mode : UInt<1>} - io.ifu_axi.w.valid <= UInt<1>("h00") @[ifu_mem_ctl.scala 57:22] - io.ifu_axi.w.bits.data <= UInt<1>("h00") @[ifu_mem_ctl.scala 58:26] - io.ifu_axi.aw.bits.qos <= UInt<1>("h00") @[ifu_mem_ctl.scala 59:26] - io.ifu_axi.aw.bits.addr <= UInt<1>("h00") @[ifu_mem_ctl.scala 60:27] - io.ifu_axi.aw.bits.prot <= UInt<1>("h00") @[ifu_mem_ctl.scala 61:27] - io.ifu_axi.aw.bits.len <= UInt<1>("h00") @[ifu_mem_ctl.scala 62:26] - io.ifu_axi.ar.bits.lock <= UInt<1>("h00") @[ifu_mem_ctl.scala 63:27] - io.ifu_axi.aw.bits.region <= UInt<1>("h00") @[ifu_mem_ctl.scala 64:29] - io.ifu_axi.aw.bits.id <= UInt<1>("h00") @[ifu_mem_ctl.scala 65:25] - io.ifu_axi.aw.valid <= UInt<1>("h00") @[ifu_mem_ctl.scala 66:23] - io.ifu_axi.w.bits.strb <= UInt<1>("h00") @[ifu_mem_ctl.scala 67:26] - io.ifu_axi.aw.bits.cache <= UInt<1>("h00") @[ifu_mem_ctl.scala 68:28] - io.ifu_axi.ar.bits.qos <= UInt<1>("h00") @[ifu_mem_ctl.scala 69:26] - io.ifu_axi.aw.bits.lock <= UInt<1>("h00") @[ifu_mem_ctl.scala 70:27] - io.ifu_axi.b.ready <= UInt<1>("h00") @[ifu_mem_ctl.scala 71:22] - io.ifu_axi.ar.bits.len <= UInt<1>("h00") @[ifu_mem_ctl.scala 72:26] - io.ifu_axi.aw.bits.size <= UInt<1>("h00") @[ifu_mem_ctl.scala 73:27] - io.ifu_axi.ar.bits.prot <= UInt<1>("h00") @[ifu_mem_ctl.scala 74:27] - io.ifu_axi.aw.bits.burst <= UInt<1>("h00") @[ifu_mem_ctl.scala 75:28] - io.ifu_axi.w.bits.last <= UInt<1>("h00") @[ifu_mem_ctl.scala 76:26] wire iccm_single_ecc_error : UInt<2> iccm_single_ecc_error <= UInt<1>("h00") wire ifc_fetch_req_f : UInt<1> @@ -2402,13 +2382,13 @@ circuit quasar_wrapper : rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= ic_debug_rd_en_ff @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - reg flush_final_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 108:53] - flush_final_f <= io.exu_flush_final @[ifu_mem_ctl.scala 108:53] - node _T = or(io.ifc_fetch_req_bf_raw, ifc_fetch_req_f) @[ifu_mem_ctl.scala 109:53] - node _T_1 = or(_T, miss_pending) @[ifu_mem_ctl.scala 109:71] - node _T_2 = or(_T_1, io.exu_flush_final) @[ifu_mem_ctl.scala 109:86] - node fetch_bf_f_c1_clken = or(_T_2, scnd_miss_req) @[ifu_mem_ctl.scala 109:107] - node debug_c1_clken = or(io.ic.debug_rd_en, io.ic.debug_wr_en) @[ifu_mem_ctl.scala 110:42] + reg flush_final_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 90:53] + flush_final_f <= io.exu_flush_final @[ifu_mem_ctl.scala 90:53] + node _T = or(io.ifc_fetch_req_bf_raw, ifc_fetch_req_f) @[ifu_mem_ctl.scala 91:53] + node _T_1 = or(_T, miss_pending) @[ifu_mem_ctl.scala 91:71] + node _T_2 = or(_T_1, io.exu_flush_final) @[ifu_mem_ctl.scala 91:86] + node fetch_bf_f_c1_clken = or(_T_2, scnd_miss_req) @[ifu_mem_ctl.scala 91:107] + node debug_c1_clken = or(io.ic.debug_rd_en, io.ic.debug_wr_en) @[ifu_mem_ctl.scala 92:42] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -2421,222 +2401,222 @@ circuit quasar_wrapper : rvclkhdr_2.io.clk <= clock @[lib.scala 328:17] rvclkhdr_2.io.en <= fetch_bf_f_c1_clken @[lib.scala 329:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_3 = orr(iccm_single_ecc_error) @[ifu_mem_ctl.scala 113:52] - node _T_4 = bits(dma_iccm_req_f, 0, 0) @[ifu_mem_ctl.scala 113:78] - node _T_5 = and(_T_3, _T_4) @[ifu_mem_ctl.scala 113:55] - io.iccm_dma_sb_error <= _T_5 @[ifu_mem_ctl.scala 113:24] - node _T_6 = or(io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err, io.dec_mem_ctrl.ifu_ic_error_start) @[ifu_mem_ctl.scala 114:74] - io.ifu_async_error_start <= _T_6 @[ifu_mem_ctl.scala 114:28] - node _T_7 = eq(perr_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 115:54] - node _T_8 = or(iccm_correct_ecc, _T_7) @[ifu_mem_ctl.scala 115:40] - node _T_9 = eq(err_stop_state, UInt<2>("h03")) @[ifu_mem_ctl.scala 115:90] - node _T_10 = or(_T_8, _T_9) @[ifu_mem_ctl.scala 115:72] - node _T_11 = or(_T_10, err_stop_fetch) @[ifu_mem_ctl.scala 115:112] - node _T_12 = or(_T_11, io.dec_mem_ctrl.dec_tlu_flush_err_wb) @[ifu_mem_ctl.scala 115:129] - io.ic_dma_active <= _T_12 @[ifu_mem_ctl.scala 115:20] - node _T_13 = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[ifu_mem_ctl.scala 117:44] - node _T_14 = and(_T_13, ifu_bus_rsp_ready) @[ifu_mem_ctl.scala 117:65] - node _T_15 = andr(bus_new_data_beat_count) @[ifu_mem_ctl.scala 117:112] - node _T_16 = and(_T_14, _T_15) @[ifu_mem_ctl.scala 117:85] - node _T_17 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 118:5] - node _T_18 = and(_T_16, _T_17) @[ifu_mem_ctl.scala 117:118] - node _T_19 = eq(miss_state, UInt<3>("h05")) @[ifu_mem_ctl.scala 118:41] - node _T_20 = eq(miss_nxtstate, UInt<3>("h05")) @[ifu_mem_ctl.scala 118:73] - node _T_21 = or(_T_19, _T_20) @[ifu_mem_ctl.scala 118:57] - node _T_22 = and(_T_18, _T_21) @[ifu_mem_ctl.scala 118:26] - node _T_23 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 118:93] - node scnd_miss_req_in = and(_T_22, _T_23) @[ifu_mem_ctl.scala 118:91] - node ifu_bp_hit_taken_q_f = and(io.ifu_bp_hit_taken_f, io.ic_hit_f) @[ifu_mem_ctl.scala 120:52] + node _T_3 = orr(iccm_single_ecc_error) @[ifu_mem_ctl.scala 95:52] + node _T_4 = bits(dma_iccm_req_f, 0, 0) @[ifu_mem_ctl.scala 95:78] + node _T_5 = and(_T_3, _T_4) @[ifu_mem_ctl.scala 95:55] + io.iccm_dma_sb_error <= _T_5 @[ifu_mem_ctl.scala 95:24] + node _T_6 = or(io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err, io.dec_mem_ctrl.ifu_ic_error_start) @[ifu_mem_ctl.scala 96:74] + io.ifu_async_error_start <= _T_6 @[ifu_mem_ctl.scala 96:28] + node _T_7 = eq(perr_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 97:54] + node _T_8 = or(iccm_correct_ecc, _T_7) @[ifu_mem_ctl.scala 97:40] + node _T_9 = eq(err_stop_state, UInt<2>("h03")) @[ifu_mem_ctl.scala 97:90] + node _T_10 = or(_T_8, _T_9) @[ifu_mem_ctl.scala 97:72] + node _T_11 = or(_T_10, err_stop_fetch) @[ifu_mem_ctl.scala 97:112] + node _T_12 = or(_T_11, io.dec_mem_ctrl.dec_tlu_flush_err_wb) @[ifu_mem_ctl.scala 97:129] + io.ic_dma_active <= _T_12 @[ifu_mem_ctl.scala 97:20] + node _T_13 = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[ifu_mem_ctl.scala 99:44] + node _T_14 = and(_T_13, ifu_bus_rsp_ready) @[ifu_mem_ctl.scala 99:65] + node _T_15 = andr(bus_new_data_beat_count) @[ifu_mem_ctl.scala 99:112] + node _T_16 = and(_T_14, _T_15) @[ifu_mem_ctl.scala 99:85] + node _T_17 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 100:5] + node _T_18 = and(_T_16, _T_17) @[ifu_mem_ctl.scala 99:118] + node _T_19 = eq(miss_state, UInt<3>("h05")) @[ifu_mem_ctl.scala 100:41] + node _T_20 = eq(miss_nxtstate, UInt<3>("h05")) @[ifu_mem_ctl.scala 100:73] + node _T_21 = or(_T_19, _T_20) @[ifu_mem_ctl.scala 100:57] + node _T_22 = and(_T_18, _T_21) @[ifu_mem_ctl.scala 100:26] + node _T_23 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 100:93] + node scnd_miss_req_in = and(_T_22, _T_23) @[ifu_mem_ctl.scala 100:91] + node ifu_bp_hit_taken_q_f = and(io.ifu_bp_hit_taken_f, io.ic_hit_f) @[ifu_mem_ctl.scala 102:52] node _T_24 = eq(UInt<3>("h00"), miss_state) @[Conditional.scala 37:30] when _T_24 : @[Conditional.scala 40:58] - node _T_25 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 124:45] - node _T_26 = and(ic_act_miss_f, _T_25) @[ifu_mem_ctl.scala 124:43] - node _T_27 = bits(_T_26, 0, 0) @[ifu_mem_ctl.scala 124:66] - node _T_28 = mux(_T_27, UInt<3>("h01"), UInt<3>("h02")) @[ifu_mem_ctl.scala 124:27] - miss_nxtstate <= _T_28 @[ifu_mem_ctl.scala 124:21] - node _T_29 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 125:40] - node _T_30 = and(ic_act_miss_f, _T_29) @[ifu_mem_ctl.scala 125:38] - miss_state_en <= _T_30 @[ifu_mem_ctl.scala 125:21] + node _T_25 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 106:45] + node _T_26 = and(ic_act_miss_f, _T_25) @[ifu_mem_ctl.scala 106:43] + node _T_27 = bits(_T_26, 0, 0) @[ifu_mem_ctl.scala 106:66] + node _T_28 = mux(_T_27, UInt<3>("h01"), UInt<3>("h02")) @[ifu_mem_ctl.scala 106:27] + miss_nxtstate <= _T_28 @[ifu_mem_ctl.scala 106:21] + node _T_29 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 107:40] + node _T_30 = and(ic_act_miss_f, _T_29) @[ifu_mem_ctl.scala 107:38] + miss_state_en <= _T_30 @[ifu_mem_ctl.scala 107:21] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_31 = eq(UInt<3>("h01"), miss_state) @[Conditional.scala 37:30] when _T_31 : @[Conditional.scala 39:67] - node _T_32 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 128:126] - node _T_33 = or(last_data_recieved_ff, _T_32) @[ifu_mem_ctl.scala 128:106] - node _T_34 = and(ic_byp_hit_f, _T_33) @[ifu_mem_ctl.scala 128:80] - node _T_35 = and(_T_34, uncacheable_miss_ff) @[ifu_mem_ctl.scala 128:140] - node _T_36 = or(io.dec_mem_ctrl.dec_tlu_force_halt, _T_35) @[ifu_mem_ctl.scala 128:64] - node _T_37 = bits(_T_36, 0, 0) @[ifu_mem_ctl.scala 128:165] - node _T_38 = eq(last_data_recieved_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 129:30] - node _T_39 = and(ic_byp_hit_f, _T_38) @[ifu_mem_ctl.scala 129:27] - node _T_40 = and(_T_39, uncacheable_miss_ff) @[ifu_mem_ctl.scala 129:53] - node _T_41 = bits(_T_40, 0, 0) @[ifu_mem_ctl.scala 129:77] - node _T_42 = eq(ic_byp_hit_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 130:16] - node _T_43 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 130:32] - node _T_44 = and(_T_42, _T_43) @[ifu_mem_ctl.scala 130:30] - node _T_45 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 130:72] - node _T_46 = and(_T_44, _T_45) @[ifu_mem_ctl.scala 130:52] - node _T_47 = and(_T_46, uncacheable_miss_ff) @[ifu_mem_ctl.scala 130:85] - node _T_48 = bits(_T_47, 0, 0) @[ifu_mem_ctl.scala 130:109] - node _T_49 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 131:36] - node _T_50 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 131:51] - node _T_51 = and(_T_49, _T_50) @[ifu_mem_ctl.scala 131:49] - node _T_52 = bits(_T_51, 0, 0) @[ifu_mem_ctl.scala 131:73] - node _T_53 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 132:35] - node _T_54 = and(ic_byp_hit_f, _T_53) @[ifu_mem_ctl.scala 132:33] - node _T_55 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 132:76] - node _T_56 = eq(_T_55, UInt<1>("h00")) @[ifu_mem_ctl.scala 132:57] - node _T_57 = and(_T_54, _T_56) @[ifu_mem_ctl.scala 132:55] - node _T_58 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 132:91] - node _T_59 = and(_T_57, _T_58) @[ifu_mem_ctl.scala 132:89] - node _T_60 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 132:115] - node _T_61 = and(_T_59, _T_60) @[ifu_mem_ctl.scala 132:113] - node _T_62 = bits(_T_61, 0, 0) @[ifu_mem_ctl.scala 132:137] - node _T_63 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 133:41] - node _T_64 = and(bus_ifu_wr_en_ff, _T_63) @[ifu_mem_ctl.scala 133:39] - node _T_65 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 133:82] - node _T_66 = eq(_T_65, UInt<1>("h00")) @[ifu_mem_ctl.scala 133:63] - node _T_67 = and(_T_64, _T_66) @[ifu_mem_ctl.scala 133:61] - node _T_68 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 133:97] - node _T_69 = and(_T_67, _T_68) @[ifu_mem_ctl.scala 133:95] - node _T_70 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 133:121] - node _T_71 = and(_T_69, _T_70) @[ifu_mem_ctl.scala 133:119] - node _T_72 = bits(_T_71, 0, 0) @[ifu_mem_ctl.scala 133:143] - node _T_73 = eq(ic_byp_hit_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 134:22] - node _T_74 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 134:40] - node _T_75 = and(_T_73, _T_74) @[ifu_mem_ctl.scala 134:37] - node _T_76 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 134:81] - node _T_77 = and(_T_75, _T_76) @[ifu_mem_ctl.scala 134:60] - node _T_78 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 134:102] - node _T_79 = and(_T_77, _T_78) @[ifu_mem_ctl.scala 134:100] - node _T_80 = bits(_T_79, 0, 0) @[ifu_mem_ctl.scala 134:124] - node _T_81 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 135:44] - node _T_82 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 135:89] - node _T_83 = eq(_T_82, UInt<1>("h00")) @[ifu_mem_ctl.scala 135:70] - node _T_84 = and(_T_81, _T_83) @[ifu_mem_ctl.scala 135:68] - node _T_85 = bits(_T_84, 0, 0) @[ifu_mem_ctl.scala 135:103] - node _T_86 = mux(_T_85, UInt<3>("h02"), UInt<3>("h00")) @[ifu_mem_ctl.scala 135:22] - node _T_87 = mux(_T_80, UInt<3>("h00"), _T_86) @[ifu_mem_ctl.scala 134:20] - node _T_88 = mux(_T_72, UInt<3>("h06"), _T_87) @[ifu_mem_ctl.scala 133:20] - node _T_89 = mux(_T_62, UInt<3>("h06"), _T_88) @[ifu_mem_ctl.scala 132:18] - node _T_90 = mux(_T_52, UInt<3>("h00"), _T_89) @[ifu_mem_ctl.scala 131:16] - node _T_91 = mux(_T_48, UInt<3>("h04"), _T_90) @[ifu_mem_ctl.scala 130:14] - node _T_92 = mux(_T_41, UInt<3>("h03"), _T_91) @[ifu_mem_ctl.scala 129:12] - node _T_93 = mux(_T_37, UInt<3>("h00"), _T_92) @[ifu_mem_ctl.scala 128:27] - miss_nxtstate <= _T_93 @[ifu_mem_ctl.scala 128:21] - node _T_94 = or(io.dec_mem_ctrl.dec_tlu_force_halt, io.exu_flush_final) @[ifu_mem_ctl.scala 136:59] - node _T_95 = or(_T_94, ic_byp_hit_f) @[ifu_mem_ctl.scala 136:80] - node _T_96 = or(_T_95, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 136:95] - node _T_97 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 136:138] - node _T_98 = or(_T_96, _T_97) @[ifu_mem_ctl.scala 136:118] - node _T_99 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 136:173] - node _T_100 = and(bus_ifu_wr_en_ff, _T_99) @[ifu_mem_ctl.scala 136:171] - node _T_101 = or(_T_98, _T_100) @[ifu_mem_ctl.scala 136:151] - miss_state_en <= _T_101 @[ifu_mem_ctl.scala 136:21] + node _T_32 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 110:126] + node _T_33 = or(last_data_recieved_ff, _T_32) @[ifu_mem_ctl.scala 110:106] + node _T_34 = and(ic_byp_hit_f, _T_33) @[ifu_mem_ctl.scala 110:80] + node _T_35 = and(_T_34, uncacheable_miss_ff) @[ifu_mem_ctl.scala 110:140] + node _T_36 = or(io.dec_mem_ctrl.dec_tlu_force_halt, _T_35) @[ifu_mem_ctl.scala 110:64] + node _T_37 = bits(_T_36, 0, 0) @[ifu_mem_ctl.scala 110:165] + node _T_38 = eq(last_data_recieved_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 111:30] + node _T_39 = and(ic_byp_hit_f, _T_38) @[ifu_mem_ctl.scala 111:27] + node _T_40 = and(_T_39, uncacheable_miss_ff) @[ifu_mem_ctl.scala 111:53] + node _T_41 = bits(_T_40, 0, 0) @[ifu_mem_ctl.scala 111:77] + node _T_42 = eq(ic_byp_hit_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 112:16] + node _T_43 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 112:32] + node _T_44 = and(_T_42, _T_43) @[ifu_mem_ctl.scala 112:30] + node _T_45 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 112:72] + node _T_46 = and(_T_44, _T_45) @[ifu_mem_ctl.scala 112:52] + node _T_47 = and(_T_46, uncacheable_miss_ff) @[ifu_mem_ctl.scala 112:85] + node _T_48 = bits(_T_47, 0, 0) @[ifu_mem_ctl.scala 112:109] + node _T_49 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 113:36] + node _T_50 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 113:51] + node _T_51 = and(_T_49, _T_50) @[ifu_mem_ctl.scala 113:49] + node _T_52 = bits(_T_51, 0, 0) @[ifu_mem_ctl.scala 113:73] + node _T_53 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 114:35] + node _T_54 = and(ic_byp_hit_f, _T_53) @[ifu_mem_ctl.scala 114:33] + node _T_55 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 114:76] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[ifu_mem_ctl.scala 114:57] + node _T_57 = and(_T_54, _T_56) @[ifu_mem_ctl.scala 114:55] + node _T_58 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 114:91] + node _T_59 = and(_T_57, _T_58) @[ifu_mem_ctl.scala 114:89] + node _T_60 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 114:115] + node _T_61 = and(_T_59, _T_60) @[ifu_mem_ctl.scala 114:113] + node _T_62 = bits(_T_61, 0, 0) @[ifu_mem_ctl.scala 114:137] + node _T_63 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 115:41] + node _T_64 = and(bus_ifu_wr_en_ff, _T_63) @[ifu_mem_ctl.scala 115:39] + node _T_65 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 115:82] + node _T_66 = eq(_T_65, UInt<1>("h00")) @[ifu_mem_ctl.scala 115:63] + node _T_67 = and(_T_64, _T_66) @[ifu_mem_ctl.scala 115:61] + node _T_68 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 115:97] + node _T_69 = and(_T_67, _T_68) @[ifu_mem_ctl.scala 115:95] + node _T_70 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 115:121] + node _T_71 = and(_T_69, _T_70) @[ifu_mem_ctl.scala 115:119] + node _T_72 = bits(_T_71, 0, 0) @[ifu_mem_ctl.scala 115:143] + node _T_73 = eq(ic_byp_hit_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 116:22] + node _T_74 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 116:40] + node _T_75 = and(_T_73, _T_74) @[ifu_mem_ctl.scala 116:37] + node _T_76 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 116:81] + node _T_77 = and(_T_75, _T_76) @[ifu_mem_ctl.scala 116:60] + node _T_78 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 116:102] + node _T_79 = and(_T_77, _T_78) @[ifu_mem_ctl.scala 116:100] + node _T_80 = bits(_T_79, 0, 0) @[ifu_mem_ctl.scala 116:124] + node _T_81 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 117:44] + node _T_82 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 117:89] + node _T_83 = eq(_T_82, UInt<1>("h00")) @[ifu_mem_ctl.scala 117:70] + node _T_84 = and(_T_81, _T_83) @[ifu_mem_ctl.scala 117:68] + node _T_85 = bits(_T_84, 0, 0) @[ifu_mem_ctl.scala 117:103] + node _T_86 = mux(_T_85, UInt<3>("h02"), UInt<3>("h00")) @[ifu_mem_ctl.scala 117:22] + node _T_87 = mux(_T_80, UInt<3>("h00"), _T_86) @[ifu_mem_ctl.scala 116:20] + node _T_88 = mux(_T_72, UInt<3>("h06"), _T_87) @[ifu_mem_ctl.scala 115:20] + node _T_89 = mux(_T_62, UInt<3>("h06"), _T_88) @[ifu_mem_ctl.scala 114:18] + node _T_90 = mux(_T_52, UInt<3>("h00"), _T_89) @[ifu_mem_ctl.scala 113:16] + node _T_91 = mux(_T_48, UInt<3>("h04"), _T_90) @[ifu_mem_ctl.scala 112:14] + node _T_92 = mux(_T_41, UInt<3>("h03"), _T_91) @[ifu_mem_ctl.scala 111:12] + node _T_93 = mux(_T_37, UInt<3>("h00"), _T_92) @[ifu_mem_ctl.scala 110:27] + miss_nxtstate <= _T_93 @[ifu_mem_ctl.scala 110:21] + node _T_94 = or(io.dec_mem_ctrl.dec_tlu_force_halt, io.exu_flush_final) @[ifu_mem_ctl.scala 118:59] + node _T_95 = or(_T_94, ic_byp_hit_f) @[ifu_mem_ctl.scala 118:80] + node _T_96 = or(_T_95, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 118:95] + node _T_97 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 118:138] + node _T_98 = or(_T_96, _T_97) @[ifu_mem_ctl.scala 118:118] + node _T_99 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 118:173] + node _T_100 = and(bus_ifu_wr_en_ff, _T_99) @[ifu_mem_ctl.scala 118:171] + node _T_101 = or(_T_98, _T_100) @[ifu_mem_ctl.scala 118:151] + miss_state_en <= _T_101 @[ifu_mem_ctl.scala 118:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_102 = eq(UInt<3>("h04"), miss_state) @[Conditional.scala 37:30] when _T_102 : @[Conditional.scala 39:67] - miss_nxtstate <= UInt<3>("h00") @[ifu_mem_ctl.scala 139:21] - node _T_103 = or(io.exu_flush_final, flush_final_f) @[ifu_mem_ctl.scala 140:43] - node _T_104 = or(_T_103, ic_byp_hit_f) @[ifu_mem_ctl.scala 140:59] - node _T_105 = or(_T_104, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 140:74] - miss_state_en <= _T_105 @[ifu_mem_ctl.scala 140:21] + miss_nxtstate <= UInt<3>("h00") @[ifu_mem_ctl.scala 121:21] + node _T_103 = or(io.exu_flush_final, flush_final_f) @[ifu_mem_ctl.scala 122:43] + node _T_104 = or(_T_103, ic_byp_hit_f) @[ifu_mem_ctl.scala 122:59] + node _T_105 = or(_T_104, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 122:74] + miss_state_en <= _T_105 @[ifu_mem_ctl.scala 122:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_106 = eq(UInt<3>("h06"), miss_state) @[Conditional.scala 37:30] when _T_106 : @[Conditional.scala 39:67] - node _T_107 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 143:49] - node _T_108 = or(_T_107, stream_eol_f) @[ifu_mem_ctl.scala 143:72] - node _T_109 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 143:108] - node _T_110 = eq(_T_109, UInt<1>("h00")) @[ifu_mem_ctl.scala 143:89] - node _T_111 = and(_T_108, _T_110) @[ifu_mem_ctl.scala 143:87] - node _T_112 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 143:124] - node _T_113 = and(_T_111, _T_112) @[ifu_mem_ctl.scala 143:122] - node _T_114 = bits(_T_113, 0, 0) @[ifu_mem_ctl.scala 143:161] - node _T_115 = mux(_T_114, UInt<3>("h02"), UInt<3>("h00")) @[ifu_mem_ctl.scala 143:27] - miss_nxtstate <= _T_115 @[ifu_mem_ctl.scala 143:21] - node _T_116 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 144:43] - node _T_117 = or(_T_116, stream_eol_f) @[ifu_mem_ctl.scala 144:67] - node _T_118 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 144:105] - node _T_119 = or(_T_117, _T_118) @[ifu_mem_ctl.scala 144:84] - node _T_120 = or(_T_119, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 144:118] - miss_state_en <= _T_120 @[ifu_mem_ctl.scala 144:21] + node _T_107 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 125:49] + node _T_108 = or(_T_107, stream_eol_f) @[ifu_mem_ctl.scala 125:72] + node _T_109 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 125:108] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[ifu_mem_ctl.scala 125:89] + node _T_111 = and(_T_108, _T_110) @[ifu_mem_ctl.scala 125:87] + node _T_112 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 125:124] + node _T_113 = and(_T_111, _T_112) @[ifu_mem_ctl.scala 125:122] + node _T_114 = bits(_T_113, 0, 0) @[ifu_mem_ctl.scala 125:161] + node _T_115 = mux(_T_114, UInt<3>("h02"), UInt<3>("h00")) @[ifu_mem_ctl.scala 125:27] + miss_nxtstate <= _T_115 @[ifu_mem_ctl.scala 125:21] + node _T_116 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 126:43] + node _T_117 = or(_T_116, stream_eol_f) @[ifu_mem_ctl.scala 126:67] + node _T_118 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 126:105] + node _T_119 = or(_T_117, _T_118) @[ifu_mem_ctl.scala 126:84] + node _T_120 = or(_T_119, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 126:118] + miss_state_en <= _T_120 @[ifu_mem_ctl.scala 126:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_121 = eq(UInt<3>("h03"), miss_state) @[Conditional.scala 37:30] when _T_121 : @[Conditional.scala 39:67] - node _T_122 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 147:69] - node _T_123 = eq(_T_122, UInt<1>("h00")) @[ifu_mem_ctl.scala 147:50] - node _T_124 = and(io.exu_flush_final, _T_123) @[ifu_mem_ctl.scala 147:48] - node _T_125 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 147:84] - node _T_126 = and(_T_124, _T_125) @[ifu_mem_ctl.scala 147:82] - node _T_127 = bits(_T_126, 0, 0) @[ifu_mem_ctl.scala 147:121] - node _T_128 = mux(_T_127, UInt<3>("h02"), UInt<3>("h00")) @[ifu_mem_ctl.scala 147:27] - miss_nxtstate <= _T_128 @[ifu_mem_ctl.scala 147:21] - node _T_129 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 148:63] - node _T_130 = or(io.exu_flush_final, _T_129) @[ifu_mem_ctl.scala 148:43] - node _T_131 = or(_T_130, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 148:76] - miss_state_en <= _T_131 @[ifu_mem_ctl.scala 148:21] + node _T_122 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 129:69] + node _T_123 = eq(_T_122, UInt<1>("h00")) @[ifu_mem_ctl.scala 129:50] + node _T_124 = and(io.exu_flush_final, _T_123) @[ifu_mem_ctl.scala 129:48] + node _T_125 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 129:84] + node _T_126 = and(_T_124, _T_125) @[ifu_mem_ctl.scala 129:82] + node _T_127 = bits(_T_126, 0, 0) @[ifu_mem_ctl.scala 129:121] + node _T_128 = mux(_T_127, UInt<3>("h02"), UInt<3>("h00")) @[ifu_mem_ctl.scala 129:27] + miss_nxtstate <= _T_128 @[ifu_mem_ctl.scala 129:21] + node _T_129 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 130:63] + node _T_130 = or(io.exu_flush_final, _T_129) @[ifu_mem_ctl.scala 130:43] + node _T_131 = or(_T_130, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 130:76] + miss_state_en <= _T_131 @[ifu_mem_ctl.scala 130:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_132 = eq(UInt<3>("h02"), miss_state) @[Conditional.scala 37:30] when _T_132 : @[Conditional.scala 39:67] - node _T_133 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 151:71] - node _T_134 = eq(_T_133, UInt<1>("h00")) @[ifu_mem_ctl.scala 151:52] - node _T_135 = and(ic_miss_under_miss_f, _T_134) @[ifu_mem_ctl.scala 151:50] - node _T_136 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 151:86] - node _T_137 = and(_T_135, _T_136) @[ifu_mem_ctl.scala 151:84] - node _T_138 = bits(_T_137, 0, 0) @[ifu_mem_ctl.scala 151:123] - node _T_139 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 152:56] - node _T_140 = eq(_T_139, UInt<1>("h00")) @[ifu_mem_ctl.scala 152:37] - node _T_141 = and(ic_ignore_2nd_miss_f, _T_140) @[ifu_mem_ctl.scala 152:35] - node _T_142 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 152:71] - node _T_143 = and(_T_141, _T_142) @[ifu_mem_ctl.scala 152:69] - node _T_144 = bits(_T_143, 0, 0) @[ifu_mem_ctl.scala 152:108] - node _T_145 = mux(_T_144, UInt<3>("h07"), UInt<3>("h00")) @[ifu_mem_ctl.scala 152:12] - node _T_146 = mux(_T_138, UInt<3>("h05"), _T_145) @[ifu_mem_ctl.scala 151:27] - miss_nxtstate <= _T_146 @[ifu_mem_ctl.scala 151:21] - node _T_147 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 153:42] - node _T_148 = or(_T_147, ic_miss_under_miss_f) @[ifu_mem_ctl.scala 153:55] - node _T_149 = or(_T_148, ic_ignore_2nd_miss_f) @[ifu_mem_ctl.scala 153:78] - node _T_150 = or(_T_149, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 153:101] - miss_state_en <= _T_150 @[ifu_mem_ctl.scala 153:21] + node _T_133 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 133:71] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[ifu_mem_ctl.scala 133:52] + node _T_135 = and(ic_miss_under_miss_f, _T_134) @[ifu_mem_ctl.scala 133:50] + node _T_136 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 133:86] + node _T_137 = and(_T_135, _T_136) @[ifu_mem_ctl.scala 133:84] + node _T_138 = bits(_T_137, 0, 0) @[ifu_mem_ctl.scala 133:123] + node _T_139 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 134:56] + node _T_140 = eq(_T_139, UInt<1>("h00")) @[ifu_mem_ctl.scala 134:37] + node _T_141 = and(ic_ignore_2nd_miss_f, _T_140) @[ifu_mem_ctl.scala 134:35] + node _T_142 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 134:71] + node _T_143 = and(_T_141, _T_142) @[ifu_mem_ctl.scala 134:69] + node _T_144 = bits(_T_143, 0, 0) @[ifu_mem_ctl.scala 134:108] + node _T_145 = mux(_T_144, UInt<3>("h07"), UInt<3>("h00")) @[ifu_mem_ctl.scala 134:12] + node _T_146 = mux(_T_138, UInt<3>("h05"), _T_145) @[ifu_mem_ctl.scala 133:27] + miss_nxtstate <= _T_146 @[ifu_mem_ctl.scala 133:21] + node _T_147 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 135:42] + node _T_148 = or(_T_147, ic_miss_under_miss_f) @[ifu_mem_ctl.scala 135:55] + node _T_149 = or(_T_148, ic_ignore_2nd_miss_f) @[ifu_mem_ctl.scala 135:78] + node _T_150 = or(_T_149, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 135:101] + miss_state_en <= _T_150 @[ifu_mem_ctl.scala 135:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_151 = eq(UInt<3>("h05"), miss_state) @[Conditional.scala 37:30] when _T_151 : @[Conditional.scala 39:67] - node _T_152 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 157:31] - node _T_153 = bits(_T_152, 0, 0) @[ifu_mem_ctl.scala 157:44] - node _T_154 = mux(_T_153, UInt<3>("h00"), UInt<3>("h02")) @[ifu_mem_ctl.scala 157:12] - node _T_155 = mux(io.exu_flush_final, _T_154, UInt<3>("h01")) @[ifu_mem_ctl.scala 156:75] - node _T_156 = mux(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<3>("h00"), _T_155) @[ifu_mem_ctl.scala 156:27] - miss_nxtstate <= _T_156 @[ifu_mem_ctl.scala 156:21] - node _T_157 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 158:42] - node _T_158 = or(_T_157, io.exu_flush_final) @[ifu_mem_ctl.scala 158:55] - node _T_159 = or(_T_158, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 158:76] - miss_state_en <= _T_159 @[ifu_mem_ctl.scala 158:21] + node _T_152 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 139:31] + node _T_153 = bits(_T_152, 0, 0) @[ifu_mem_ctl.scala 139:44] + node _T_154 = mux(_T_153, UInt<3>("h00"), UInt<3>("h02")) @[ifu_mem_ctl.scala 139:12] + node _T_155 = mux(io.exu_flush_final, _T_154, UInt<3>("h01")) @[ifu_mem_ctl.scala 138:75] + node _T_156 = mux(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<3>("h00"), _T_155) @[ifu_mem_ctl.scala 138:27] + miss_nxtstate <= _T_156 @[ifu_mem_ctl.scala 138:21] + node _T_157 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 140:42] + node _T_158 = or(_T_157, io.exu_flush_final) @[ifu_mem_ctl.scala 140:55] + node _T_159 = or(_T_158, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 140:76] + miss_state_en <= _T_159 @[ifu_mem_ctl.scala 140:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_160 = eq(UInt<3>("h07"), miss_state) @[Conditional.scala 37:30] when _T_160 : @[Conditional.scala 39:67] - node _T_161 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 162:31] - node _T_162 = bits(_T_161, 0, 0) @[ifu_mem_ctl.scala 162:44] - node _T_163 = mux(_T_162, UInt<3>("h00"), UInt<3>("h02")) @[ifu_mem_ctl.scala 162:12] - node _T_164 = mux(io.exu_flush_final, _T_163, UInt<3>("h00")) @[ifu_mem_ctl.scala 161:75] - node _T_165 = mux(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<3>("h00"), _T_164) @[ifu_mem_ctl.scala 161:27] - miss_nxtstate <= _T_165 @[ifu_mem_ctl.scala 161:21] - node _T_166 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 163:42] - node _T_167 = or(_T_166, io.exu_flush_final) @[ifu_mem_ctl.scala 163:55] - node _T_168 = or(_T_167, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 163:76] - miss_state_en <= _T_168 @[ifu_mem_ctl.scala 163:21] + node _T_161 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 144:31] + node _T_162 = bits(_T_161, 0, 0) @[ifu_mem_ctl.scala 144:44] + node _T_163 = mux(_T_162, UInt<3>("h00"), UInt<3>("h02")) @[ifu_mem_ctl.scala 144:12] + node _T_164 = mux(io.exu_flush_final, _T_163, UInt<3>("h00")) @[ifu_mem_ctl.scala 143:75] + node _T_165 = mux(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<3>("h00"), _T_164) @[ifu_mem_ctl.scala 143:27] + miss_nxtstate <= _T_165 @[ifu_mem_ctl.scala 143:21] + node _T_166 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 145:42] + node _T_167 = or(_T_166, io.exu_flush_final) @[ifu_mem_ctl.scala 145:55] + node _T_168 = or(_T_167, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 145:76] + miss_state_en <= _T_168 @[ifu_mem_ctl.scala 145:21] skip @[Conditional.scala 39:67] - node _T_169 = bits(miss_state_en, 0, 0) @[ifu_mem_ctl.scala 166:84] + node _T_169 = bits(miss_state_en, 0, 0) @[ifu_mem_ctl.scala 148:84] reg _T_170 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_169 : @[Reg.scala 28:19] _T_170 <= miss_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - miss_state <= _T_170 @[ifu_mem_ctl.scala 166:14] + miss_state <= _T_170 @[ifu_mem_ctl.scala 148:14] wire crit_byp_hit_f : UInt<1> crit_byp_hit_f <= UInt<1>("h00") wire way_status_mb_scnd_ff : UInt<1> @@ -2655,280 +2635,280 @@ circuit quasar_wrapper : bus_rd_addr_count <= UInt<1>("h00") wire ifu_bus_rid_ff : UInt<3> ifu_bus_rid_ff <= UInt<1>("h00") - node _T_171 = neq(miss_state, UInt<3>("h00")) @[ifu_mem_ctl.scala 176:30] - miss_pending <= _T_171 @[ifu_mem_ctl.scala 176:16] - node _T_172 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 177:39] - node _T_173 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 177:73] - node _T_174 = eq(flush_final_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 177:95] - node _T_175 = and(_T_173, _T_174) @[ifu_mem_ctl.scala 177:93] - node crit_wd_byp_ok_ff = or(_T_172, _T_175) @[ifu_mem_ctl.scala 177:58] - node _T_176 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 178:57] - node _T_177 = eq(_T_176, UInt<1>("h00")) @[ifu_mem_ctl.scala 178:38] - node _T_178 = and(miss_pending, _T_177) @[ifu_mem_ctl.scala 178:36] - node _T_179 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 178:86] - node _T_180 = and(_T_179, io.exu_flush_final) @[ifu_mem_ctl.scala 178:106] - node _T_181 = eq(_T_180, UInt<1>("h00")) @[ifu_mem_ctl.scala 178:72] - node _T_182 = and(_T_178, _T_181) @[ifu_mem_ctl.scala 178:70] - node _T_183 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 179:37] - node _T_184 = and(_T_183, crit_byp_hit_f) @[ifu_mem_ctl.scala 179:57] - node _T_185 = eq(_T_184, UInt<1>("h00")) @[ifu_mem_ctl.scala 179:23] - node _T_186 = and(_T_182, _T_185) @[ifu_mem_ctl.scala 178:128] - node _T_187 = or(_T_186, ic_act_miss_f) @[ifu_mem_ctl.scala 179:77] - node _T_188 = eq(miss_nxtstate, UInt<3>("h04")) @[ifu_mem_ctl.scala 180:36] - node _T_189 = and(miss_pending, _T_188) @[ifu_mem_ctl.scala 180:19] - node sel_hold_imb = or(_T_187, _T_189) @[ifu_mem_ctl.scala 179:93] - node _T_190 = eq(miss_state, UInt<3>("h05")) @[ifu_mem_ctl.scala 182:40] - node _T_191 = or(_T_190, ic_miss_under_miss_f) @[ifu_mem_ctl.scala 182:57] - node _T_192 = eq(flush_final_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 182:83] - node sel_hold_imb_scnd = and(_T_191, _T_192) @[ifu_mem_ctl.scala 182:81] - node _T_193 = eq(miss_state, UInt<3>("h05")) @[ifu_mem_ctl.scala 183:46] - node way_status_mb_scnd_in = mux(_T_193, way_status_mb_scnd_ff, way_status) @[ifu_mem_ctl.scala 183:34] - node _T_194 = eq(miss_state, UInt<3>("h05")) @[ifu_mem_ctl.scala 185:40] - node _T_195 = eq(reset_all_tags, UInt<1>("h00")) @[ifu_mem_ctl.scala 185:96] + node _T_171 = neq(miss_state, UInt<3>("h00")) @[ifu_mem_ctl.scala 159:30] + miss_pending <= _T_171 @[ifu_mem_ctl.scala 159:16] + node _T_172 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 160:39] + node _T_173 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 160:73] + node _T_174 = eq(flush_final_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 160:95] + node _T_175 = and(_T_173, _T_174) @[ifu_mem_ctl.scala 160:93] + node crit_wd_byp_ok_ff = or(_T_172, _T_175) @[ifu_mem_ctl.scala 160:58] + node _T_176 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 161:57] + node _T_177 = eq(_T_176, UInt<1>("h00")) @[ifu_mem_ctl.scala 161:38] + node _T_178 = and(miss_pending, _T_177) @[ifu_mem_ctl.scala 161:36] + node _T_179 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 161:86] + node _T_180 = and(_T_179, io.exu_flush_final) @[ifu_mem_ctl.scala 161:106] + node _T_181 = eq(_T_180, UInt<1>("h00")) @[ifu_mem_ctl.scala 161:72] + node _T_182 = and(_T_178, _T_181) @[ifu_mem_ctl.scala 161:70] + node _T_183 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 162:37] + node _T_184 = and(_T_183, crit_byp_hit_f) @[ifu_mem_ctl.scala 162:57] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[ifu_mem_ctl.scala 162:23] + node _T_186 = and(_T_182, _T_185) @[ifu_mem_ctl.scala 161:128] + node _T_187 = or(_T_186, ic_act_miss_f) @[ifu_mem_ctl.scala 162:77] + node _T_188 = eq(miss_nxtstate, UInt<3>("h04")) @[ifu_mem_ctl.scala 163:36] + node _T_189 = and(miss_pending, _T_188) @[ifu_mem_ctl.scala 163:19] + node sel_hold_imb = or(_T_187, _T_189) @[ifu_mem_ctl.scala 162:93] + node _T_190 = eq(miss_state, UInt<3>("h05")) @[ifu_mem_ctl.scala 165:40] + node _T_191 = or(_T_190, ic_miss_under_miss_f) @[ifu_mem_ctl.scala 165:57] + node _T_192 = eq(flush_final_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 165:83] + node sel_hold_imb_scnd = and(_T_191, _T_192) @[ifu_mem_ctl.scala 165:81] + node _T_193 = eq(miss_state, UInt<3>("h05")) @[ifu_mem_ctl.scala 166:46] + node way_status_mb_scnd_in = mux(_T_193, way_status_mb_scnd_ff, way_status) @[ifu_mem_ctl.scala 166:34] + node _T_194 = eq(miss_state, UInt<3>("h05")) @[ifu_mem_ctl.scala 168:40] + node _T_195 = eq(reset_all_tags, UInt<1>("h00")) @[ifu_mem_ctl.scala 168:96] node _T_196 = bits(_T_195, 0, 0) @[Bitwise.scala 72:15] node _T_197 = mux(_T_196, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_198 = and(_T_197, io.ic.tag_valid) @[ifu_mem_ctl.scala 185:113] - node tagv_mb_scnd_in = mux(_T_194, tagv_mb_scnd_ff, _T_198) @[ifu_mem_ctl.scala 185:28] - node _T_199 = bits(sel_hold_imb_scnd, 0, 0) @[ifu_mem_ctl.scala 186:56] - node uncacheable_miss_scnd_in = mux(_T_199, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[ifu_mem_ctl.scala 186:37] - reg _T_200 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 187:67] - _T_200 <= uncacheable_miss_scnd_in @[ifu_mem_ctl.scala 187:67] - uncacheable_miss_scnd_ff <= _T_200 @[ifu_mem_ctl.scala 187:28] - node _T_201 = bits(sel_hold_imb_scnd, 0, 0) @[ifu_mem_ctl.scala 188:43] - node imb_scnd_in = mux(_T_201, imb_scnd_ff, io.ifc_fetch_addr_bf) @[ifu_mem_ctl.scala 188:24] - reg _T_202 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 189:54] - _T_202 <= imb_scnd_in @[ifu_mem_ctl.scala 189:54] - imb_scnd_ff <= _T_202 @[ifu_mem_ctl.scala 189:15] - reg _T_203 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 190:64] - _T_203 <= way_status_mb_scnd_in @[ifu_mem_ctl.scala 190:64] - way_status_mb_scnd_ff <= _T_203 @[ifu_mem_ctl.scala 190:25] - reg _T_204 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 191:58] - _T_204 <= tagv_mb_scnd_in @[ifu_mem_ctl.scala 191:58] - tagv_mb_scnd_ff <= _T_204 @[ifu_mem_ctl.scala 191:19] + node _T_198 = and(_T_197, io.ic.tag_valid) @[ifu_mem_ctl.scala 168:113] + node tagv_mb_scnd_in = mux(_T_194, tagv_mb_scnd_ff, _T_198) @[ifu_mem_ctl.scala 168:28] + node _T_199 = bits(sel_hold_imb_scnd, 0, 0) @[ifu_mem_ctl.scala 169:56] + node uncacheable_miss_scnd_in = mux(_T_199, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[ifu_mem_ctl.scala 169:37] + reg _T_200 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 170:67] + _T_200 <= uncacheable_miss_scnd_in @[ifu_mem_ctl.scala 170:67] + uncacheable_miss_scnd_ff <= _T_200 @[ifu_mem_ctl.scala 170:28] + node _T_201 = bits(sel_hold_imb_scnd, 0, 0) @[ifu_mem_ctl.scala 171:43] + node imb_scnd_in = mux(_T_201, imb_scnd_ff, io.ifc_fetch_addr_bf) @[ifu_mem_ctl.scala 171:24] + reg _T_202 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 172:54] + _T_202 <= imb_scnd_in @[ifu_mem_ctl.scala 172:54] + imb_scnd_ff <= _T_202 @[ifu_mem_ctl.scala 172:15] + reg _T_203 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 173:64] + _T_203 <= way_status_mb_scnd_in @[ifu_mem_ctl.scala 173:64] + way_status_mb_scnd_ff <= _T_203 @[ifu_mem_ctl.scala 173:25] + reg _T_204 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 174:58] + _T_204 <= tagv_mb_scnd_in @[ifu_mem_ctl.scala 174:58] + tagv_mb_scnd_ff <= _T_204 @[ifu_mem_ctl.scala 174:19] node _T_205 = bits(bus_ifu_wr_en_ff, 0, 0) @[Bitwise.scala 72:15] node _T_206 = mux(_T_205, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node ic_wr_addr_bits_hi_3 = and(ifu_bus_rid_ff, _T_206) @[ifu_mem_ctl.scala 194:45] + node ic_wr_addr_bits_hi_3 = and(ifu_bus_rid_ff, _T_206) @[ifu_mem_ctl.scala 177:45] wire ifc_iccm_access_f : UInt<1> ifc_iccm_access_f <= UInt<1>("h00") wire ifc_region_acc_fault_final_f : UInt<1> ifc_region_acc_fault_final_f <= UInt<1>("h00") - node _T_207 = eq(ifc_iccm_access_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 197:48] - node _T_208 = and(ifc_fetch_req_f, _T_207) @[ifu_mem_ctl.scala 197:46] - node _T_209 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 197:69] - node fetch_req_icache_f = and(_T_208, _T_209) @[ifu_mem_ctl.scala 197:67] - node fetch_req_iccm_f = and(ifc_fetch_req_f, ifc_iccm_access_f) @[ifu_mem_ctl.scala 198:46] - node _T_210 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 199:45] - node _T_211 = eq(miss_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 199:73] - node _T_212 = or(_T_210, _T_211) @[ifu_mem_ctl.scala 199:59] - node _T_213 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 199:105] - node _T_214 = or(_T_212, _T_213) @[ifu_mem_ctl.scala 199:91] - node ic_iccm_hit_f = and(fetch_req_iccm_f, _T_214) @[ifu_mem_ctl.scala 199:41] + node _T_207 = eq(ifc_iccm_access_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 180:48] + node _T_208 = and(ifc_fetch_req_f, _T_207) @[ifu_mem_ctl.scala 180:46] + node _T_209 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 180:69] + node fetch_req_icache_f = and(_T_208, _T_209) @[ifu_mem_ctl.scala 180:67] + node fetch_req_iccm_f = and(ifc_fetch_req_f, ifc_iccm_access_f) @[ifu_mem_ctl.scala 181:46] + node _T_210 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 182:45] + node _T_211 = eq(miss_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 182:73] + node _T_212 = or(_T_210, _T_211) @[ifu_mem_ctl.scala 182:59] + node _T_213 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 182:105] + node _T_214 = or(_T_212, _T_213) @[ifu_mem_ctl.scala 182:91] + node ic_iccm_hit_f = and(fetch_req_iccm_f, _T_214) @[ifu_mem_ctl.scala 182:41] wire stream_hit_f : UInt<1> stream_hit_f <= UInt<1>("h00") - node _T_215 = or(crit_byp_hit_f, stream_hit_f) @[ifu_mem_ctl.scala 201:35] - node _T_216 = and(_T_215, fetch_req_icache_f) @[ifu_mem_ctl.scala 201:52] - node _T_217 = and(_T_216, miss_pending) @[ifu_mem_ctl.scala 201:73] - ic_byp_hit_f <= _T_217 @[ifu_mem_ctl.scala 201:16] + node _T_215 = or(crit_byp_hit_f, stream_hit_f) @[ifu_mem_ctl.scala 184:35] + node _T_216 = and(_T_215, fetch_req_icache_f) @[ifu_mem_ctl.scala 184:52] + node _T_217 = and(_T_216, miss_pending) @[ifu_mem_ctl.scala 184:73] + ic_byp_hit_f <= _T_217 @[ifu_mem_ctl.scala 184:16] wire sel_mb_addr_ff : UInt<1> sel_mb_addr_ff <= UInt<1>("h00") wire imb_ff : UInt<31> imb_ff <= UInt<1>("h00") wire ifu_fetch_addr_int_f : UInt<31> ifu_fetch_addr_int_f <= UInt<1>("h00") - node _T_218 = orr(io.ic.rd_hit) @[ifu_mem_ctl.scala 205:35] - node _T_219 = and(_T_218, fetch_req_icache_f) @[ifu_mem_ctl.scala 205:39] - node _T_220 = eq(reset_all_tags, UInt<1>("h00")) @[ifu_mem_ctl.scala 205:62] - node _T_221 = and(_T_219, _T_220) @[ifu_mem_ctl.scala 205:60] - node _T_222 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 205:81] - node _T_223 = eq(miss_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 205:108] - node _T_224 = or(_T_222, _T_223) @[ifu_mem_ctl.scala 205:95] - node _T_225 = and(_T_221, _T_224) @[ifu_mem_ctl.scala 205:78] - node _T_226 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 205:128] - node ic_act_hit_f = and(_T_225, _T_226) @[ifu_mem_ctl.scala 205:126] - node _T_227 = orr(io.ic.rd_hit) @[ifu_mem_ctl.scala 206:37] - node _T_228 = eq(_T_227, UInt<1>("h00")) @[ifu_mem_ctl.scala 206:23] - node _T_229 = or(_T_228, reset_all_tags) @[ifu_mem_ctl.scala 206:41] - node _T_230 = and(_T_229, fetch_req_icache_f) @[ifu_mem_ctl.scala 206:59] - node _T_231 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 206:82] - node _T_232 = and(_T_230, _T_231) @[ifu_mem_ctl.scala 206:80] - node _T_233 = or(_T_232, scnd_miss_req) @[ifu_mem_ctl.scala 206:97] - node _T_234 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 206:116] - node _T_235 = and(_T_233, _T_234) @[ifu_mem_ctl.scala 206:114] - ic_act_miss_f <= _T_235 @[ifu_mem_ctl.scala 206:17] - node _T_236 = eq(io.ic.rd_hit, UInt<1>("h00")) @[ifu_mem_ctl.scala 207:28] - node _T_237 = or(_T_236, reset_all_tags) @[ifu_mem_ctl.scala 207:42] - node _T_238 = and(_T_237, fetch_req_icache_f) @[ifu_mem_ctl.scala 207:60] - node _T_239 = eq(miss_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 207:94] - node _T_240 = and(_T_238, _T_239) @[ifu_mem_ctl.scala 207:81] - node _T_241 = bits(imb_ff, 30, 5) @[ifu_mem_ctl.scala 208:12] - node _T_242 = bits(ifu_fetch_addr_int_f, 30, 5) @[ifu_mem_ctl.scala 208:63] - node _T_243 = neq(_T_241, _T_242) @[ifu_mem_ctl.scala 208:39] - node _T_244 = and(_T_240, _T_243) @[ifu_mem_ctl.scala 207:111] - node _T_245 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 208:93] - node _T_246 = and(_T_244, _T_245) @[ifu_mem_ctl.scala 208:91] - node _T_247 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 208:116] - node _T_248 = and(_T_246, _T_247) @[ifu_mem_ctl.scala 208:114] - node _T_249 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 208:134] - node _T_250 = and(_T_248, _T_249) @[ifu_mem_ctl.scala 208:132] - ic_miss_under_miss_f <= _T_250 @[ifu_mem_ctl.scala 207:24] - node _T_251 = orr(io.ic.rd_hit) @[ifu_mem_ctl.scala 209:42] - node _T_252 = eq(_T_251, UInt<1>("h00")) @[ifu_mem_ctl.scala 209:28] - node _T_253 = or(_T_252, reset_all_tags) @[ifu_mem_ctl.scala 209:46] - node _T_254 = and(_T_253, fetch_req_icache_f) @[ifu_mem_ctl.scala 209:64] - node _T_255 = eq(miss_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 209:99] - node _T_256 = and(_T_254, _T_255) @[ifu_mem_ctl.scala 209:85] - node _T_257 = bits(imb_ff, 30, 5) @[ifu_mem_ctl.scala 210:13] - node _T_258 = bits(ifu_fetch_addr_int_f, 30, 5) @[ifu_mem_ctl.scala 210:62] - node _T_259 = eq(_T_257, _T_258) @[ifu_mem_ctl.scala 210:39] - node _T_260 = or(_T_259, uncacheable_miss_ff) @[ifu_mem_ctl.scala 210:91] - node _T_261 = and(_T_256, _T_260) @[ifu_mem_ctl.scala 209:117] - ic_ignore_2nd_miss_f <= _T_261 @[ifu_mem_ctl.scala 209:24] - node _T_262 = or(ic_act_hit_f, ic_byp_hit_f) @[ifu_mem_ctl.scala 212:31] - node _T_263 = or(_T_262, ic_iccm_hit_f) @[ifu_mem_ctl.scala 212:46] - node _T_264 = and(ifc_region_acc_fault_final_f, ifc_fetch_req_f) @[ifu_mem_ctl.scala 212:94] - node _T_265 = or(_T_263, _T_264) @[ifu_mem_ctl.scala 212:62] - io.ic_hit_f <= _T_265 @[ifu_mem_ctl.scala 212:15] - node _T_266 = bits(scnd_miss_req, 0, 0) @[ifu_mem_ctl.scala 213:47] - node _T_267 = bits(sel_hold_imb, 0, 0) @[ifu_mem_ctl.scala 213:98] - node _T_268 = mux(_T_267, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf) @[ifu_mem_ctl.scala 213:84] - node uncacheable_miss_in = mux(_T_266, uncacheable_miss_scnd_ff, _T_268) @[ifu_mem_ctl.scala 213:32] - node _T_269 = bits(scnd_miss_req, 0, 0) @[ifu_mem_ctl.scala 214:34] - node _T_270 = bits(sel_hold_imb, 0, 0) @[ifu_mem_ctl.scala 214:72] - node _T_271 = mux(_T_270, imb_ff, io.ifc_fetch_addr_bf) @[ifu_mem_ctl.scala 214:58] - node imb_in = mux(_T_269, imb_scnd_ff, _T_271) @[ifu_mem_ctl.scala 214:19] + node _T_218 = orr(io.ic.rd_hit) @[ifu_mem_ctl.scala 188:35] + node _T_219 = and(_T_218, fetch_req_icache_f) @[ifu_mem_ctl.scala 188:39] + node _T_220 = eq(reset_all_tags, UInt<1>("h00")) @[ifu_mem_ctl.scala 188:62] + node _T_221 = and(_T_219, _T_220) @[ifu_mem_ctl.scala 188:60] + node _T_222 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 188:81] + node _T_223 = eq(miss_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 188:108] + node _T_224 = or(_T_222, _T_223) @[ifu_mem_ctl.scala 188:95] + node _T_225 = and(_T_221, _T_224) @[ifu_mem_ctl.scala 188:78] + node _T_226 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 188:128] + node ic_act_hit_f = and(_T_225, _T_226) @[ifu_mem_ctl.scala 188:126] + node _T_227 = orr(io.ic.rd_hit) @[ifu_mem_ctl.scala 189:37] + node _T_228 = eq(_T_227, UInt<1>("h00")) @[ifu_mem_ctl.scala 189:23] + node _T_229 = or(_T_228, reset_all_tags) @[ifu_mem_ctl.scala 189:41] + node _T_230 = and(_T_229, fetch_req_icache_f) @[ifu_mem_ctl.scala 189:59] + node _T_231 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 189:82] + node _T_232 = and(_T_230, _T_231) @[ifu_mem_ctl.scala 189:80] + node _T_233 = or(_T_232, scnd_miss_req) @[ifu_mem_ctl.scala 189:97] + node _T_234 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 189:116] + node _T_235 = and(_T_233, _T_234) @[ifu_mem_ctl.scala 189:114] + ic_act_miss_f <= _T_235 @[ifu_mem_ctl.scala 189:17] + node _T_236 = eq(io.ic.rd_hit, UInt<1>("h00")) @[ifu_mem_ctl.scala 190:28] + node _T_237 = or(_T_236, reset_all_tags) @[ifu_mem_ctl.scala 190:42] + node _T_238 = and(_T_237, fetch_req_icache_f) @[ifu_mem_ctl.scala 190:60] + node _T_239 = eq(miss_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 190:94] + node _T_240 = and(_T_238, _T_239) @[ifu_mem_ctl.scala 190:81] + node _T_241 = bits(imb_ff, 30, 5) @[ifu_mem_ctl.scala 191:12] + node _T_242 = bits(ifu_fetch_addr_int_f, 30, 5) @[ifu_mem_ctl.scala 191:63] + node _T_243 = neq(_T_241, _T_242) @[ifu_mem_ctl.scala 191:39] + node _T_244 = and(_T_240, _T_243) @[ifu_mem_ctl.scala 190:111] + node _T_245 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 191:93] + node _T_246 = and(_T_244, _T_245) @[ifu_mem_ctl.scala 191:91] + node _T_247 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 191:116] + node _T_248 = and(_T_246, _T_247) @[ifu_mem_ctl.scala 191:114] + node _T_249 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 191:134] + node _T_250 = and(_T_248, _T_249) @[ifu_mem_ctl.scala 191:132] + ic_miss_under_miss_f <= _T_250 @[ifu_mem_ctl.scala 190:24] + node _T_251 = orr(io.ic.rd_hit) @[ifu_mem_ctl.scala 192:42] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[ifu_mem_ctl.scala 192:28] + node _T_253 = or(_T_252, reset_all_tags) @[ifu_mem_ctl.scala 192:46] + node _T_254 = and(_T_253, fetch_req_icache_f) @[ifu_mem_ctl.scala 192:64] + node _T_255 = eq(miss_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 192:99] + node _T_256 = and(_T_254, _T_255) @[ifu_mem_ctl.scala 192:85] + node _T_257 = bits(imb_ff, 30, 5) @[ifu_mem_ctl.scala 193:13] + node _T_258 = bits(ifu_fetch_addr_int_f, 30, 5) @[ifu_mem_ctl.scala 193:62] + node _T_259 = eq(_T_257, _T_258) @[ifu_mem_ctl.scala 193:39] + node _T_260 = or(_T_259, uncacheable_miss_ff) @[ifu_mem_ctl.scala 193:91] + node _T_261 = and(_T_256, _T_260) @[ifu_mem_ctl.scala 192:117] + ic_ignore_2nd_miss_f <= _T_261 @[ifu_mem_ctl.scala 192:24] + node _T_262 = or(ic_act_hit_f, ic_byp_hit_f) @[ifu_mem_ctl.scala 195:31] + node _T_263 = or(_T_262, ic_iccm_hit_f) @[ifu_mem_ctl.scala 195:46] + node _T_264 = and(ifc_region_acc_fault_final_f, ifc_fetch_req_f) @[ifu_mem_ctl.scala 195:94] + node _T_265 = or(_T_263, _T_264) @[ifu_mem_ctl.scala 195:62] + io.ic_hit_f <= _T_265 @[ifu_mem_ctl.scala 195:15] + node _T_266 = bits(scnd_miss_req, 0, 0) @[ifu_mem_ctl.scala 196:47] + node _T_267 = bits(sel_hold_imb, 0, 0) @[ifu_mem_ctl.scala 196:98] + node _T_268 = mux(_T_267, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf) @[ifu_mem_ctl.scala 196:84] + node uncacheable_miss_in = mux(_T_266, uncacheable_miss_scnd_ff, _T_268) @[ifu_mem_ctl.scala 196:32] + node _T_269 = bits(scnd_miss_req, 0, 0) @[ifu_mem_ctl.scala 197:34] + node _T_270 = bits(sel_hold_imb, 0, 0) @[ifu_mem_ctl.scala 197:72] + node _T_271 = mux(_T_270, imb_ff, io.ifc_fetch_addr_bf) @[ifu_mem_ctl.scala 197:58] + node imb_in = mux(_T_269, imb_scnd_ff, _T_271) @[ifu_mem_ctl.scala 197:19] wire ifu_wr_cumulative_err_data : UInt<1> ifu_wr_cumulative_err_data <= UInt<1>("h00") - node _T_272 = bits(imb_ff, 11, 5) @[ifu_mem_ctl.scala 216:38] - node _T_273 = bits(imb_scnd_ff, 11, 5) @[ifu_mem_ctl.scala 216:93] - node _T_274 = eq(_T_272, _T_273) @[ifu_mem_ctl.scala 216:79] - node _T_275 = and(_T_274, scnd_miss_req) @[ifu_mem_ctl.scala 216:135] - node _T_276 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[ifu_mem_ctl.scala 216:153] - node scnd_miss_index_match = and(_T_275, _T_276) @[ifu_mem_ctl.scala 216:151] + node _T_272 = bits(imb_ff, 11, 5) @[ifu_mem_ctl.scala 199:38] + node _T_273 = bits(imb_scnd_ff, 11, 5) @[ifu_mem_ctl.scala 199:93] + node _T_274 = eq(_T_272, _T_273) @[ifu_mem_ctl.scala 199:79] + node _T_275 = and(_T_274, scnd_miss_req) @[ifu_mem_ctl.scala 199:135] + node _T_276 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[ifu_mem_ctl.scala 199:153] + node scnd_miss_index_match = and(_T_275, _T_276) @[ifu_mem_ctl.scala 199:151] wire way_status_mb_ff : UInt<1> way_status_mb_ff <= UInt<1>("h00") wire way_status_rep_new : UInt<1> way_status_rep_new <= UInt<1>("h00") - node _T_277 = eq(scnd_miss_index_match, UInt<1>("h00")) @[ifu_mem_ctl.scala 219:47] - node _T_278 = and(scnd_miss_req, _T_277) @[ifu_mem_ctl.scala 219:45] - node _T_279 = bits(_T_278, 0, 0) @[ifu_mem_ctl.scala 219:71] - node _T_280 = and(scnd_miss_req, scnd_miss_index_match) @[ifu_mem_ctl.scala 220:26] - node _T_281 = bits(_T_280, 0, 0) @[ifu_mem_ctl.scala 220:52] - node _T_282 = bits(miss_pending, 0, 0) @[ifu_mem_ctl.scala 221:26] - node _T_283 = mux(_T_282, way_status_mb_ff, way_status) @[ifu_mem_ctl.scala 221:12] - node _T_284 = mux(_T_281, way_status_rep_new, _T_283) @[ifu_mem_ctl.scala 220:10] - node way_status_mb_in = mux(_T_279, way_status_mb_scnd_ff, _T_284) @[ifu_mem_ctl.scala 219:29] - wire replace_way_mb_any : UInt<1>[2] @[ifu_mem_ctl.scala 222:32] + node _T_277 = eq(scnd_miss_index_match, UInt<1>("h00")) @[ifu_mem_ctl.scala 202:47] + node _T_278 = and(scnd_miss_req, _T_277) @[ifu_mem_ctl.scala 202:45] + node _T_279 = bits(_T_278, 0, 0) @[ifu_mem_ctl.scala 202:71] + node _T_280 = and(scnd_miss_req, scnd_miss_index_match) @[ifu_mem_ctl.scala 203:26] + node _T_281 = bits(_T_280, 0, 0) @[ifu_mem_ctl.scala 203:52] + node _T_282 = bits(miss_pending, 0, 0) @[ifu_mem_ctl.scala 204:26] + node _T_283 = mux(_T_282, way_status_mb_ff, way_status) @[ifu_mem_ctl.scala 204:12] + node _T_284 = mux(_T_281, way_status_rep_new, _T_283) @[ifu_mem_ctl.scala 203:10] + node way_status_mb_in = mux(_T_279, way_status_mb_scnd_ff, _T_284) @[ifu_mem_ctl.scala 202:29] + wire replace_way_mb_any : UInt<1>[2] @[ifu_mem_ctl.scala 205:32] wire tagv_mb_ff : UInt<2> tagv_mb_ff <= UInt<1>("h00") - node _T_285 = bits(scnd_miss_req, 0, 0) @[ifu_mem_ctl.scala 224:38] + node _T_285 = bits(scnd_miss_req, 0, 0) @[ifu_mem_ctl.scala 207:38] node _T_286 = bits(scnd_miss_index_match, 0, 0) @[Bitwise.scala 72:15] node _T_287 = mux(_T_286, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_288 = cat(replace_way_mb_any[1], replace_way_mb_any[0]) @[Cat.scala 29:58] - node _T_289 = and(_T_287, _T_288) @[ifu_mem_ctl.scala 224:110] - node _T_290 = or(tagv_mb_scnd_ff, _T_289) @[ifu_mem_ctl.scala 224:62] - node _T_291 = bits(miss_pending, 0, 0) @[ifu_mem_ctl.scala 225:20] - node _T_292 = eq(reset_all_tags, UInt<1>("h00")) @[ifu_mem_ctl.scala 225:80] + node _T_289 = and(_T_287, _T_288) @[ifu_mem_ctl.scala 207:110] + node _T_290 = or(tagv_mb_scnd_ff, _T_289) @[ifu_mem_ctl.scala 207:62] + node _T_291 = bits(miss_pending, 0, 0) @[ifu_mem_ctl.scala 208:20] + node _T_292 = eq(reset_all_tags, UInt<1>("h00")) @[ifu_mem_ctl.scala 208:80] node _T_293 = bits(_T_292, 0, 0) @[Bitwise.scala 72:15] node _T_294 = mux(_T_293, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_295 = and(io.ic.tag_valid, _T_294) @[ifu_mem_ctl.scala 225:56] - node _T_296 = mux(_T_291, tagv_mb_ff, _T_295) @[ifu_mem_ctl.scala 225:6] - node tagv_mb_in = mux(_T_285, _T_290, _T_296) @[ifu_mem_ctl.scala 224:23] + node _T_295 = and(io.ic.tag_valid, _T_294) @[ifu_mem_ctl.scala 208:56] + node _T_296 = mux(_T_291, tagv_mb_ff, _T_295) @[ifu_mem_ctl.scala 208:6] + node tagv_mb_in = mux(_T_285, _T_290, _T_296) @[ifu_mem_ctl.scala 207:23] wire scnd_miss_req_q : UInt<1> scnd_miss_req_q <= UInt<1>("h00") wire reset_ic_ff : UInt<1> reset_ic_ff <= UInt<1>("h00") - node _T_297 = eq(scnd_miss_req_q, UInt<1>("h00")) @[ifu_mem_ctl.scala 228:36] - node _T_298 = and(miss_pending, _T_297) @[ifu_mem_ctl.scala 228:34] - node _T_299 = or(reset_all_tags, reset_ic_ff) @[ifu_mem_ctl.scala 228:72] - node reset_ic_in = and(_T_298, _T_299) @[ifu_mem_ctl.scala 228:53] - reg _T_300 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 229:48] - _T_300 <= reset_ic_in @[ifu_mem_ctl.scala 229:48] - reset_ic_ff <= _T_300 @[ifu_mem_ctl.scala 229:15] - reg fetch_uncacheable_ff : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 230:62] - fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[ifu_mem_ctl.scala 230:62] - reg _T_301 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 231:63] - _T_301 <= io.ifc_fetch_addr_bf @[ifu_mem_ctl.scala 231:63] - ifu_fetch_addr_int_f <= _T_301 @[ifu_mem_ctl.scala 231:24] - node vaddr_f = bits(ifu_fetch_addr_int_f, 4, 0) @[ifu_mem_ctl.scala 232:37] - reg _T_302 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 233:62] - _T_302 <= uncacheable_miss_in @[ifu_mem_ctl.scala 233:62] - uncacheable_miss_ff <= _T_302 @[ifu_mem_ctl.scala 233:23] - reg _T_303 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 234:49] - _T_303 <= imb_in @[ifu_mem_ctl.scala 234:49] - imb_ff <= _T_303 @[ifu_mem_ctl.scala 234:10] + node _T_297 = eq(scnd_miss_req_q, UInt<1>("h00")) @[ifu_mem_ctl.scala 211:36] + node _T_298 = and(miss_pending, _T_297) @[ifu_mem_ctl.scala 211:34] + node _T_299 = or(reset_all_tags, reset_ic_ff) @[ifu_mem_ctl.scala 211:72] + node reset_ic_in = and(_T_298, _T_299) @[ifu_mem_ctl.scala 211:53] + reg _T_300 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 212:48] + _T_300 <= reset_ic_in @[ifu_mem_ctl.scala 212:48] + reset_ic_ff <= _T_300 @[ifu_mem_ctl.scala 212:15] + reg fetch_uncacheable_ff : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 213:62] + fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[ifu_mem_ctl.scala 213:62] + reg _T_301 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 214:63] + _T_301 <= io.ifc_fetch_addr_bf @[ifu_mem_ctl.scala 214:63] + ifu_fetch_addr_int_f <= _T_301 @[ifu_mem_ctl.scala 214:24] + node vaddr_f = bits(ifu_fetch_addr_int_f, 4, 0) @[ifu_mem_ctl.scala 215:37] + reg _T_302 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 216:62] + _T_302 <= uncacheable_miss_in @[ifu_mem_ctl.scala 216:62] + uncacheable_miss_ff <= _T_302 @[ifu_mem_ctl.scala 216:23] + reg _T_303 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 217:49] + _T_303 <= imb_in @[ifu_mem_ctl.scala 217:49] + imb_ff <= _T_303 @[ifu_mem_ctl.scala 217:10] wire miss_addr : UInt<26> miss_addr <= UInt<1>("h00") - node _T_304 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 236:26] - node _T_305 = bits(imb_ff, 30, 5) @[ifu_mem_ctl.scala 236:47] - node _T_306 = bits(scnd_miss_req_q, 0, 0) @[ifu_mem_ctl.scala 237:25] - node _T_307 = bits(imb_scnd_ff, 30, 5) @[ifu_mem_ctl.scala 237:44] - node _T_308 = mux(_T_306, _T_307, miss_addr) @[ifu_mem_ctl.scala 237:8] - node miss_addr_in = mux(_T_304, _T_305, _T_308) @[ifu_mem_ctl.scala 236:25] - node _T_309 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[ifu_mem_ctl.scala 238:57] - node _T_310 = or(_T_309, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 238:73] + node _T_304 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 219:26] + node _T_305 = bits(imb_ff, 30, 5) @[ifu_mem_ctl.scala 219:47] + node _T_306 = bits(scnd_miss_req_q, 0, 0) @[ifu_mem_ctl.scala 220:25] + node _T_307 = bits(imb_scnd_ff, 30, 5) @[ifu_mem_ctl.scala 220:44] + node _T_308 = mux(_T_306, _T_307, miss_addr) @[ifu_mem_ctl.scala 220:8] + node miss_addr_in = mux(_T_304, _T_305, _T_308) @[ifu_mem_ctl.scala 219:25] + node _T_309 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[ifu_mem_ctl.scala 221:57] + node _T_310 = or(_T_309, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 221:73] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 327:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 328:17] rvclkhdr_3.io.en <= _T_310 @[lib.scala 329:16] rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - reg _T_311 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 239:48] - _T_311 <= miss_addr_in @[ifu_mem_ctl.scala 239:48] - miss_addr <= _T_311 @[ifu_mem_ctl.scala 239:13] - reg _T_312 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 240:59] - _T_312 <= way_status_mb_in @[ifu_mem_ctl.scala 240:59] - way_status_mb_ff <= _T_312 @[ifu_mem_ctl.scala 240:20] - reg _T_313 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 241:53] - _T_313 <= tagv_mb_in @[ifu_mem_ctl.scala 241:53] - tagv_mb_ff <= _T_313 @[ifu_mem_ctl.scala 241:14] + reg _T_311 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 222:48] + _T_311 <= miss_addr_in @[ifu_mem_ctl.scala 222:48] + miss_addr <= _T_311 @[ifu_mem_ctl.scala 222:13] + reg _T_312 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 223:59] + _T_312 <= way_status_mb_in @[ifu_mem_ctl.scala 223:59] + way_status_mb_ff <= _T_312 @[ifu_mem_ctl.scala 223:20] + reg _T_313 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 224:53] + _T_313 <= tagv_mb_in @[ifu_mem_ctl.scala 224:53] + tagv_mb_ff <= _T_313 @[ifu_mem_ctl.scala 224:14] wire stream_miss_f : UInt<1> stream_miss_f <= UInt<1>("h00") - node _T_314 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 243:68] - node _T_315 = and(_T_314, flush_final_f) @[ifu_mem_ctl.scala 243:87] - node _T_316 = eq(_T_315, UInt<1>("h00")) @[ifu_mem_ctl.scala 243:55] - node _T_317 = and(io.ifc_fetch_req_bf, _T_316) @[ifu_mem_ctl.scala 243:53] - node _T_318 = eq(stream_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 243:106] - node ifc_fetch_req_qual_bf = and(_T_317, _T_318) @[ifu_mem_ctl.scala 243:104] - reg ifc_fetch_req_f_raw : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 244:61] - ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf @[ifu_mem_ctl.scala 244:61] - node _T_319 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 245:44] - node _T_320 = and(ifc_fetch_req_f_raw, _T_319) @[ifu_mem_ctl.scala 245:42] - ifc_fetch_req_f <= _T_320 @[ifu_mem_ctl.scala 245:19] - reg _T_321 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 246:60] - _T_321 <= io.ifc_iccm_access_bf @[ifu_mem_ctl.scala 246:60] - ifc_iccm_access_f <= _T_321 @[ifu_mem_ctl.scala 246:21] + node _T_314 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 226:68] + node _T_315 = and(_T_314, flush_final_f) @[ifu_mem_ctl.scala 226:87] + node _T_316 = eq(_T_315, UInt<1>("h00")) @[ifu_mem_ctl.scala 226:55] + node _T_317 = and(io.ifc_fetch_req_bf, _T_316) @[ifu_mem_ctl.scala 226:53] + node _T_318 = eq(stream_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 226:106] + node ifc_fetch_req_qual_bf = and(_T_317, _T_318) @[ifu_mem_ctl.scala 226:104] + reg ifc_fetch_req_f_raw : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 227:61] + ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf @[ifu_mem_ctl.scala 227:61] + node _T_319 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 228:44] + node _T_320 = and(ifc_fetch_req_f_raw, _T_319) @[ifu_mem_ctl.scala 228:42] + ifc_fetch_req_f <= _T_320 @[ifu_mem_ctl.scala 228:19] + reg _T_321 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 229:60] + _T_321 <= io.ifc_iccm_access_bf @[ifu_mem_ctl.scala 229:60] + ifc_iccm_access_f <= _T_321 @[ifu_mem_ctl.scala 229:21] wire ifc_region_acc_fault_final_bf : UInt<1> ifc_region_acc_fault_final_bf <= UInt<1>("h00") - reg _T_322 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 248:71] - _T_322 <= ifc_region_acc_fault_final_bf @[ifu_mem_ctl.scala 248:71] - ifc_region_acc_fault_final_f <= _T_322 @[ifu_mem_ctl.scala 248:32] - reg ifc_region_acc_fault_f : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 249:68] - ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[ifu_mem_ctl.scala 249:68] + reg _T_322 : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 231:71] + _T_322 <= ifc_region_acc_fault_final_bf @[ifu_mem_ctl.scala 231:71] + ifc_region_acc_fault_final_f <= _T_322 @[ifu_mem_ctl.scala 231:32] + reg ifc_region_acc_fault_f : UInt<1>, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 232:68] + ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[ifu_mem_ctl.scala 232:68] node ifu_ic_req_addr_f = cat(miss_addr, bus_rd_addr_count) @[Cat.scala 29:58] - node _T_323 = eq(miss_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 251:38] - node _T_324 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 251:68] - node _T_325 = or(_T_323, _T_324) @[ifu_mem_ctl.scala 251:55] - node _T_326 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 251:103] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[ifu_mem_ctl.scala 251:84] - node _T_328 = and(_T_325, _T_327) @[ifu_mem_ctl.scala 251:82] - node _T_329 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 251:119] - node _T_330 = or(_T_328, _T_329) @[ifu_mem_ctl.scala 251:117] - io.ifu_ic_mb_empty <= _T_330 @[ifu_mem_ctl.scala 251:22] - node _T_331 = eq(miss_state, UInt<3>("h00")) @[ifu_mem_ctl.scala 252:53] - io.dec_mem_ctrl.ifu_miss_state_idle <= _T_331 @[ifu_mem_ctl.scala 252:39] + node _T_323 = eq(miss_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 234:38] + node _T_324 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 234:68] + node _T_325 = or(_T_323, _T_324) @[ifu_mem_ctl.scala 234:55] + node _T_326 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 234:103] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[ifu_mem_ctl.scala 234:84] + node _T_328 = and(_T_325, _T_327) @[ifu_mem_ctl.scala 234:82] + node _T_329 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 234:119] + node _T_330 = or(_T_328, _T_329) @[ifu_mem_ctl.scala 234:117] + io.ifu_ic_mb_empty <= _T_330 @[ifu_mem_ctl.scala 234:22] + node _T_331 = eq(miss_state, UInt<3>("h00")) @[ifu_mem_ctl.scala 235:53] + io.dec_mem_ctrl.ifu_miss_state_idle <= _T_331 @[ifu_mem_ctl.scala 235:39] wire write_ic_16_bytes : UInt<1> write_ic_16_bytes <= UInt<1>("h00") wire reset_tag_valid_for_miss : UInt<1> reset_tag_valid_for_miss <= UInt<1>("h00") - node _T_332 = and(miss_pending, write_ic_16_bytes) @[ifu_mem_ctl.scala 255:35] - node _T_333 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 255:57] - node _T_334 = and(_T_332, _T_333) @[ifu_mem_ctl.scala 255:55] - node sel_mb_addr = or(_T_334, reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 255:79] - node _T_335 = bits(imb_ff, 30, 5) @[ifu_mem_ctl.scala 256:63] - node _T_336 = bits(imb_ff, 1, 0) @[ifu_mem_ctl.scala 256:119] + node _T_332 = and(miss_pending, write_ic_16_bytes) @[ifu_mem_ctl.scala 238:35] + node _T_333 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 238:57] + node _T_334 = and(_T_332, _T_333) @[ifu_mem_ctl.scala 238:55] + node sel_mb_addr = or(_T_334, reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 238:79] + node _T_335 = bits(imb_ff, 30, 5) @[ifu_mem_ctl.scala 239:63] + node _T_336 = bits(imb_ff, 1, 0) @[ifu_mem_ctl.scala 239:119] node _T_337 = cat(_T_335, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58] node _T_338 = cat(_T_337, _T_336) @[Cat.scala 29:58] - node _T_339 = eq(sel_mb_addr, UInt<1>("h00")) @[ifu_mem_ctl.scala 257:37] + node _T_339 = eq(sel_mb_addr, UInt<1>("h00")) @[ifu_mem_ctl.scala 240:37] node _T_340 = mux(sel_mb_addr, _T_338, UInt<1>("h00")) @[Mux.scala 27:72] node _T_341 = mux(_T_339, io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Mux.scala 27:72] node _T_342 = or(_T_340, _T_341) @[Mux.scala 27:72] @@ -2936,21 +2916,21 @@ circuit quasar_wrapper : ifu_ic_rw_int_addr <= _T_342 @[Mux.scala 27:72] wire bus_ifu_wr_en_ff_q : UInt<1> bus_ifu_wr_en_ff_q <= UInt<1>("h00") - node _T_343 = and(miss_pending, write_ic_16_bytes) @[ifu_mem_ctl.scala 259:42] - node _T_344 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 259:64] - node _T_345 = and(_T_343, _T_344) @[ifu_mem_ctl.scala 259:62] - node _T_346 = and(_T_345, last_beat) @[ifu_mem_ctl.scala 259:85] - node _T_347 = and(_T_346, bus_ifu_wr_en_ff_q) @[ifu_mem_ctl.scala 259:97] - node sel_mb_status_addr = or(_T_347, reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 259:119] - node _T_348 = bits(imb_ff, 30, 5) @[ifu_mem_ctl.scala 260:62] - node _T_349 = bits(imb_ff, 1, 0) @[ifu_mem_ctl.scala 260:116] + node _T_343 = and(miss_pending, write_ic_16_bytes) @[ifu_mem_ctl.scala 242:42] + node _T_344 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 242:64] + node _T_345 = and(_T_343, _T_344) @[ifu_mem_ctl.scala 242:62] + node _T_346 = and(_T_345, last_beat) @[ifu_mem_ctl.scala 242:85] + node _T_347 = and(_T_346, bus_ifu_wr_en_ff_q) @[ifu_mem_ctl.scala 242:97] + node sel_mb_status_addr = or(_T_347, reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 242:119] + node _T_348 = bits(imb_ff, 30, 5) @[ifu_mem_ctl.scala 243:62] + node _T_349 = bits(imb_ff, 1, 0) @[ifu_mem_ctl.scala 243:116] node _T_350 = cat(_T_348, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58] node _T_351 = cat(_T_350, _T_349) @[Cat.scala 29:58] - node ifu_status_wr_addr = mux(sel_mb_status_addr, _T_351, ifu_fetch_addr_int_f) @[ifu_mem_ctl.scala 260:31] - io.ic.rw_addr <= ifu_ic_rw_int_addr @[ifu_mem_ctl.scala 261:17] - reg _T_352 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 262:51] - _T_352 <= sel_mb_addr @[ifu_mem_ctl.scala 262:51] - sel_mb_addr_ff <= _T_352 @[ifu_mem_ctl.scala 262:18] + node ifu_status_wr_addr = mux(sel_mb_status_addr, _T_351, ifu_fetch_addr_int_f) @[ifu_mem_ctl.scala 243:31] + io.ic.rw_addr <= ifu_ic_rw_int_addr @[ifu_mem_ctl.scala 244:17] + reg _T_352 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 245:51] + _T_352 <= sel_mb_addr @[ifu_mem_ctl.scala 245:51] + sel_mb_addr_ff <= _T_352 @[ifu_mem_ctl.scala 245:18] wire ifu_bus_rdata_ff : UInt<64> ifu_bus_rdata_ff <= UInt<1>("h00") wire ic_miss_buff_half : UInt<64> @@ -4213,24 +4193,24 @@ circuit quasar_wrapper : node ic_miss_buff_ecc = cat(_T_1196, _T_1193) @[Cat.scala 29:58] wire ic_wr_16bytes_data : UInt<142> ic_wr_16bytes_data <= UInt<1>("h00") - node _T_1197 = bits(ic_wr_16bytes_data, 70, 0) @[ifu_mem_ctl.scala 268:72] - node _T_1198 = bits(ic_wr_16bytes_data, 141, 71) @[ifu_mem_ctl.scala 268:72] - io.ic.wr_data[0] <= _T_1197 @[ifu_mem_ctl.scala 268:17] - io.ic.wr_data[1] <= _T_1198 @[ifu_mem_ctl.scala 268:17] - io.ic.debug_wr_data <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[ifu_mem_ctl.scala 269:23] + node _T_1197 = bits(ic_wr_16bytes_data, 70, 0) @[ifu_mem_ctl.scala 253:72] + node _T_1198 = bits(ic_wr_16bytes_data, 141, 71) @[ifu_mem_ctl.scala 253:72] + io.ic.wr_data[0] <= _T_1197 @[ifu_mem_ctl.scala 253:17] + io.ic.wr_data[1] <= _T_1198 @[ifu_mem_ctl.scala 253:17] + io.ic.debug_wr_data <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[ifu_mem_ctl.scala 254:23] wire ic_rd_parity_final_err : UInt<1> ic_rd_parity_final_err <= UInt<1>("h00") - node _T_1199 = orr(io.ic.eccerr) @[ifu_mem_ctl.scala 271:73] - node _T_1200 = and(_T_1199, ic_act_hit_f) @[ifu_mem_ctl.scala 271:100] - node _T_1201 = or(_T_1200, ic_rd_parity_final_err) @[ifu_mem_ctl.scala 271:116] - io.dec_mem_ctrl.ifu_ic_error_start <= _T_1201 @[ifu_mem_ctl.scala 271:38] + node _T_1199 = orr(io.ic.eccerr) @[ifu_mem_ctl.scala 256:73] + node _T_1200 = and(_T_1199, ic_act_hit_f) @[ifu_mem_ctl.scala 256:100] + node _T_1201 = or(_T_1200, ic_rd_parity_final_err) @[ifu_mem_ctl.scala 256:116] + io.dec_mem_ctrl.ifu_ic_error_start <= _T_1201 @[ifu_mem_ctl.scala 256:38] wire ic_debug_tag_val_rd_out : UInt<1> ic_debug_tag_val_rd_out <= UInt<1>("h00") wire ic_debug_ict_array_sel_ff : UInt<1> ic_debug_ict_array_sel_ff <= UInt<1>("h00") - node _T_1202 = bits(ic_debug_ict_array_sel_ff, 0, 0) @[ifu_mem_ctl.scala 274:63] - node _T_1203 = bits(io.ic.tag_debug_rd_data, 25, 21) @[ifu_mem_ctl.scala 274:122] - node _T_1204 = bits(io.ic.tag_debug_rd_data, 20, 0) @[ifu_mem_ctl.scala 274:163] + node _T_1202 = bits(ic_debug_ict_array_sel_ff, 0, 0) @[ifu_mem_ctl.scala 260:63] + node _T_1203 = bits(io.ic.tag_debug_rd_data, 25, 21) @[ifu_mem_ctl.scala 260:122] + node _T_1204 = bits(io.ic.tag_debug_rd_data, 20, 0) @[ifu_mem_ctl.scala 260:163] node _T_1205 = cat(UInt<3>("h00"), ic_debug_tag_val_rd_out) @[Cat.scala 29:58] node _T_1206 = cat(UInt<6>("h00"), way_status) @[Cat.scala 29:58] node _T_1207 = cat(_T_1206, _T_1205) @[Cat.scala 29:58] @@ -4238,164 +4218,164 @@ circuit quasar_wrapper : node _T_1209 = cat(UInt<2>("h00"), _T_1203) @[Cat.scala 29:58] node _T_1210 = cat(_T_1209, _T_1208) @[Cat.scala 29:58] node _T_1211 = cat(_T_1210, _T_1207) @[Cat.scala 29:58] - node ifu_ic_debug_rd_data_in = mux(_T_1202, _T_1211, io.ic.debug_rd_data) @[ifu_mem_ctl.scala 274:36] - reg _T_1212 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 277:76] - _T_1212 <= ifu_ic_debug_rd_data_in @[ifu_mem_ctl.scala 277:76] - io.dec_mem_ctrl.ifu_ic_debug_rd_data <= _T_1212 @[ifu_mem_ctl.scala 277:40] - node _T_1213 = bits(ifu_bus_rdata_ff, 15, 0) @[ifu_mem_ctl.scala 278:74] + node ifu_ic_debug_rd_data_in = mux(_T_1202, _T_1211, io.ic.debug_rd_data) @[ifu_mem_ctl.scala 260:36] + reg _T_1212 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 263:76] + _T_1212 <= ifu_ic_debug_rd_data_in @[ifu_mem_ctl.scala 263:76] + io.dec_mem_ctrl.ifu_ic_debug_rd_data <= _T_1212 @[ifu_mem_ctl.scala 263:40] + node _T_1213 = bits(ifu_bus_rdata_ff, 15, 0) @[ifu_mem_ctl.scala 264:74] node _T_1214 = xorr(_T_1213) @[lib.scala 48:13] - node _T_1215 = bits(ifu_bus_rdata_ff, 31, 16) @[ifu_mem_ctl.scala 278:74] + node _T_1215 = bits(ifu_bus_rdata_ff, 31, 16) @[ifu_mem_ctl.scala 264:74] node _T_1216 = xorr(_T_1215) @[lib.scala 48:13] - node _T_1217 = bits(ifu_bus_rdata_ff, 47, 32) @[ifu_mem_ctl.scala 278:74] + node _T_1217 = bits(ifu_bus_rdata_ff, 47, 32) @[ifu_mem_ctl.scala 264:74] node _T_1218 = xorr(_T_1217) @[lib.scala 48:13] - node _T_1219 = bits(ifu_bus_rdata_ff, 63, 48) @[ifu_mem_ctl.scala 278:74] + node _T_1219 = bits(ifu_bus_rdata_ff, 63, 48) @[ifu_mem_ctl.scala 264:74] node _T_1220 = xorr(_T_1219) @[lib.scala 48:13] node _T_1221 = cat(_T_1220, _T_1218) @[Cat.scala 29:58] node _T_1222 = cat(_T_1221, _T_1216) @[Cat.scala 29:58] node ic_wr_parity = cat(_T_1222, _T_1214) @[Cat.scala 29:58] - node _T_1223 = bits(ic_miss_buff_half, 15, 0) @[ifu_mem_ctl.scala 279:82] + node _T_1223 = bits(ic_miss_buff_half, 15, 0) @[ifu_mem_ctl.scala 265:82] node _T_1224 = xorr(_T_1223) @[lib.scala 48:13] - node _T_1225 = bits(ic_miss_buff_half, 31, 16) @[ifu_mem_ctl.scala 279:82] + node _T_1225 = bits(ic_miss_buff_half, 31, 16) @[ifu_mem_ctl.scala 265:82] node _T_1226 = xorr(_T_1225) @[lib.scala 48:13] - node _T_1227 = bits(ic_miss_buff_half, 47, 32) @[ifu_mem_ctl.scala 279:82] + node _T_1227 = bits(ic_miss_buff_half, 47, 32) @[ifu_mem_ctl.scala 265:82] node _T_1228 = xorr(_T_1227) @[lib.scala 48:13] - node _T_1229 = bits(ic_miss_buff_half, 63, 48) @[ifu_mem_ctl.scala 279:82] + node _T_1229 = bits(ic_miss_buff_half, 63, 48) @[ifu_mem_ctl.scala 265:82] node _T_1230 = xorr(_T_1229) @[lib.scala 48:13] node _T_1231 = cat(_T_1230, _T_1228) @[Cat.scala 29:58] node _T_1232 = cat(_T_1231, _T_1226) @[Cat.scala 29:58] node ic_miss_buff_parity = cat(_T_1232, _T_1224) @[Cat.scala 29:58] - node _T_1233 = bits(ifu_bus_rid_ff, 0, 0) @[ifu_mem_ctl.scala 281:43] - node _T_1234 = bits(_T_1233, 0, 0) @[ifu_mem_ctl.scala 281:47] + node _T_1233 = bits(ifu_bus_rid_ff, 0, 0) @[ifu_mem_ctl.scala 267:43] + node _T_1234 = bits(_T_1233, 0, 0) @[ifu_mem_ctl.scala 267:47] node _T_1235 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58] node _T_1236 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58] node _T_1237 = cat(_T_1236, _T_1235) @[Cat.scala 29:58] node _T_1238 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58] node _T_1239 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58] node _T_1240 = cat(_T_1239, _T_1238) @[Cat.scala 29:58] - node _T_1241 = mux(_T_1234, _T_1237, _T_1240) @[ifu_mem_ctl.scala 281:28] - ic_wr_16bytes_data <= _T_1241 @[ifu_mem_ctl.scala 281:22] + node _T_1241 = mux(_T_1234, _T_1237, _T_1240) @[ifu_mem_ctl.scala 267:28] + ic_wr_16bytes_data <= _T_1241 @[ifu_mem_ctl.scala 267:22] wire bus_ifu_wr_data_error_ff : UInt<1> bus_ifu_wr_data_error_ff <= UInt<1>("h00") wire ifu_wr_data_comb_err_ff : UInt<1> ifu_wr_data_comb_err_ff <= UInt<1>("h00") wire reset_beat_cnt : UInt<1> reset_beat_cnt <= UInt<1>("h00") - node _T_1242 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[ifu_mem_ctl.scala 288:53] - node _T_1243 = eq(reset_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 288:82] - node ifu_wr_cumulative_err = and(_T_1242, _T_1243) @[ifu_mem_ctl.scala 288:80] - node _T_1244 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[ifu_mem_ctl.scala 289:55] - ifu_wr_cumulative_err_data <= _T_1244 @[ifu_mem_ctl.scala 289:30] - reg _T_1245 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 290:61] - _T_1245 <= ifu_wr_cumulative_err @[ifu_mem_ctl.scala 290:61] - ifu_wr_data_comb_err_ff <= _T_1245 @[ifu_mem_ctl.scala 290:27] + node _T_1242 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[ifu_mem_ctl.scala 274:53] + node _T_1243 = eq(reset_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 274:82] + node ifu_wr_cumulative_err = and(_T_1242, _T_1243) @[ifu_mem_ctl.scala 274:80] + node _T_1244 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[ifu_mem_ctl.scala 275:55] + ifu_wr_cumulative_err_data <= _T_1244 @[ifu_mem_ctl.scala 275:30] + reg _T_1245 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 276:61] + _T_1245 <= ifu_wr_cumulative_err @[ifu_mem_ctl.scala 276:61] + ifu_wr_data_comb_err_ff <= _T_1245 @[ifu_mem_ctl.scala 276:27] wire ic_crit_wd_rdy : UInt<1> ic_crit_wd_rdy <= UInt<1>("h00") wire ifu_byp_data_err_new : UInt<1> ifu_byp_data_err_new <= UInt<1>("h00") - node _T_1246 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 293:51] - node _T_1247 = or(ic_crit_wd_rdy, _T_1246) @[ifu_mem_ctl.scala 293:38] - node _T_1248 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 293:77] - node _T_1249 = or(_T_1247, _T_1248) @[ifu_mem_ctl.scala 293:64] - node _T_1250 = eq(ifu_byp_data_err_new, UInt<1>("h00")) @[ifu_mem_ctl.scala 293:98] - node sel_byp_data = and(_T_1249, _T_1250) @[ifu_mem_ctl.scala 293:96] - node _T_1251 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 294:51] - node _T_1252 = or(ic_crit_wd_rdy, _T_1251) @[ifu_mem_ctl.scala 294:38] - node _T_1253 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 294:77] - node _T_1254 = or(_T_1252, _T_1253) @[ifu_mem_ctl.scala 294:64] - node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[ifu_mem_ctl.scala 294:21] - node _T_1256 = eq(fetch_req_iccm_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 294:98] - node sel_ic_data = and(_T_1255, _T_1256) @[ifu_mem_ctl.scala 294:96] + node _T_1246 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 279:51] + node _T_1247 = or(ic_crit_wd_rdy, _T_1246) @[ifu_mem_ctl.scala 279:38] + node _T_1248 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 279:77] + node _T_1249 = or(_T_1247, _T_1248) @[ifu_mem_ctl.scala 279:64] + node _T_1250 = eq(ifu_byp_data_err_new, UInt<1>("h00")) @[ifu_mem_ctl.scala 279:98] + node sel_byp_data = and(_T_1249, _T_1250) @[ifu_mem_ctl.scala 279:96] + node _T_1251 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 280:51] + node _T_1252 = or(ic_crit_wd_rdy, _T_1251) @[ifu_mem_ctl.scala 280:38] + node _T_1253 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 280:77] + node _T_1254 = or(_T_1252, _T_1253) @[ifu_mem_ctl.scala 280:64] + node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[ifu_mem_ctl.scala 280:21] + node _T_1256 = eq(fetch_req_iccm_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 280:98] + node sel_ic_data = and(_T_1255, _T_1256) @[ifu_mem_ctl.scala 280:96] wire ic_byp_data_only_new : UInt<80> ic_byp_data_only_new <= UInt<1>("h00") - node _T_1257 = or(sel_byp_data, fetch_req_iccm_f) @[ifu_mem_ctl.scala 298:46] - node _T_1258 = or(_T_1257, sel_ic_data) @[ifu_mem_ctl.scala 298:62] - node _T_1259 = or(sel_byp_data, sel_ic_data) @[ifu_mem_ctl.scala 298:104] - wire final_data_sel1 : UInt<1>[4] @[ifu_mem_ctl.scala 298:32] - final_data_sel1[0] <= _T_1258 @[ifu_mem_ctl.scala 298:32] - final_data_sel1[1] <= sel_byp_data @[ifu_mem_ctl.scala 298:32] - final_data_sel1[2] <= _T_1259 @[ifu_mem_ctl.scala 298:32] - final_data_sel1[3] <= sel_byp_data @[ifu_mem_ctl.scala 298:32] - wire final_data_sel2 : UInt<1>[4] @[ifu_mem_ctl.scala 299:32] - final_data_sel2[0] <= UInt<1>("h01") @[ifu_mem_ctl.scala 299:32] - final_data_sel2[1] <= fetch_req_iccm_f @[ifu_mem_ctl.scala 299:32] - final_data_sel2[2] <= UInt<1>("h01") @[ifu_mem_ctl.scala 299:32] - final_data_sel2[3] <= UInt<1>("h01") @[ifu_mem_ctl.scala 299:32] - wire final_data_out1 : UInt<80>[4] @[ifu_mem_ctl.scala 300:32] - final_data_out1[0] <= io.ic.rd_data @[ifu_mem_ctl.scala 300:32] - final_data_out1[1] <= ic_byp_data_only_new @[ifu_mem_ctl.scala 300:32] - final_data_out1[2] <= io.ic.rd_data @[ifu_mem_ctl.scala 300:32] - final_data_out1[3] <= ic_byp_data_only_new @[ifu_mem_ctl.scala 300:32] - wire final_data_out2 : UInt<64>[4] @[ifu_mem_ctl.scala 301:32] - final_data_out2[0] <= UInt<1>("h01") @[ifu_mem_ctl.scala 301:32] - final_data_out2[1] <= io.iccm.rd_data @[ifu_mem_ctl.scala 301:32] - final_data_out2[2] <= UInt<1>("h01") @[ifu_mem_ctl.scala 301:32] - final_data_out2[3] <= UInt<1>("h01") @[ifu_mem_ctl.scala 301:32] - node _T_1260 = or(sel_byp_data, fetch_req_iccm_f) @[ifu_mem_ctl.scala 302:61] - node _T_1261 = or(_T_1260, sel_ic_data) @[ifu_mem_ctl.scala 302:77] + node _T_1257 = or(sel_byp_data, fetch_req_iccm_f) @[ifu_mem_ctl.scala 284:46] + node _T_1258 = or(_T_1257, sel_ic_data) @[ifu_mem_ctl.scala 284:62] + node _T_1259 = or(sel_byp_data, sel_ic_data) @[ifu_mem_ctl.scala 284:104] + wire final_data_sel1 : UInt<1>[4] @[ifu_mem_ctl.scala 284:32] + final_data_sel1[0] <= _T_1258 @[ifu_mem_ctl.scala 284:32] + final_data_sel1[1] <= sel_byp_data @[ifu_mem_ctl.scala 284:32] + final_data_sel1[2] <= _T_1259 @[ifu_mem_ctl.scala 284:32] + final_data_sel1[3] <= sel_byp_data @[ifu_mem_ctl.scala 284:32] + wire final_data_sel2 : UInt<1>[4] @[ifu_mem_ctl.scala 285:32] + final_data_sel2[0] <= UInt<1>("h01") @[ifu_mem_ctl.scala 285:32] + final_data_sel2[1] <= fetch_req_iccm_f @[ifu_mem_ctl.scala 285:32] + final_data_sel2[2] <= UInt<1>("h01") @[ifu_mem_ctl.scala 285:32] + final_data_sel2[3] <= UInt<1>("h01") @[ifu_mem_ctl.scala 285:32] + wire final_data_out1 : UInt<80>[4] @[ifu_mem_ctl.scala 286:32] + final_data_out1[0] <= io.ic.rd_data @[ifu_mem_ctl.scala 286:32] + final_data_out1[1] <= ic_byp_data_only_new @[ifu_mem_ctl.scala 286:32] + final_data_out1[2] <= io.ic.rd_data @[ifu_mem_ctl.scala 286:32] + final_data_out1[3] <= ic_byp_data_only_new @[ifu_mem_ctl.scala 286:32] + wire final_data_out2 : UInt<64>[4] @[ifu_mem_ctl.scala 287:32] + final_data_out2[0] <= UInt<1>("h01") @[ifu_mem_ctl.scala 287:32] + final_data_out2[1] <= io.iccm.rd_data @[ifu_mem_ctl.scala 287:32] + final_data_out2[2] <= UInt<1>("h01") @[ifu_mem_ctl.scala 287:32] + final_data_out2[3] <= UInt<1>("h01") @[ifu_mem_ctl.scala 287:32] + node _T_1260 = or(sel_byp_data, fetch_req_iccm_f) @[ifu_mem_ctl.scala 288:61] + node _T_1261 = or(_T_1260, sel_ic_data) @[ifu_mem_ctl.scala 288:77] node _T_1262 = bits(_T_1261, 0, 0) @[Bitwise.scala 72:15] node _T_1263 = mux(_T_1262, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node ic_final_data = and(_T_1263, io.ic.rd_data) @[ifu_mem_ctl.scala 302:92] + node ic_final_data = and(_T_1263, io.ic.rd_data) @[ifu_mem_ctl.scala 288:92] node _T_1264 = bits(fetch_req_iccm_f, 0, 0) @[Bitwise.scala 72:15] node _T_1265 = mux(_T_1264, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_1266 = and(_T_1265, io.iccm.rd_data) @[ifu_mem_ctl.scala 306:69] + node _T_1266 = and(_T_1265, io.iccm.rd_data) @[ifu_mem_ctl.scala 292:69] node _T_1267 = bits(sel_byp_data, 0, 0) @[Bitwise.scala 72:15] node _T_1268 = mux(_T_1267, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_1269 = and(_T_1268, ic_byp_data_only_new) @[ifu_mem_ctl.scala 306:114] - node ic_premux_data_temp = or(_T_1266, _T_1269) @[ifu_mem_ctl.scala 306:88] - node ic_sel_premux_data_temp = or(fetch_req_iccm_f, sel_byp_data) @[ifu_mem_ctl.scala 308:63] - io.ic.premux_data <= ic_premux_data_temp @[ifu_mem_ctl.scala 309:21] - io.ic.sel_premux_data <= ic_sel_premux_data_temp @[ifu_mem_ctl.scala 310:25] - node ifc_bus_acc_fault_f = and(ic_byp_hit_f, ifu_byp_data_err_new) @[ifu_mem_ctl.scala 311:42] - io.ic_data_f <= ic_final_data @[ifu_mem_ctl.scala 312:16] - node _T_1270 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 313:40] - node fetch_req_f_qual = and(io.ic_hit_f, _T_1270) @[ifu_mem_ctl.scala 313:38] + node _T_1269 = and(_T_1268, ic_byp_data_only_new) @[ifu_mem_ctl.scala 292:114] + node ic_premux_data_temp = or(_T_1266, _T_1269) @[ifu_mem_ctl.scala 292:88] + node ic_sel_premux_data_temp = or(fetch_req_iccm_f, sel_byp_data) @[ifu_mem_ctl.scala 294:63] + io.ic.premux_data <= ic_premux_data_temp @[ifu_mem_ctl.scala 295:21] + io.ic.sel_premux_data <= ic_sel_premux_data_temp @[ifu_mem_ctl.scala 296:25] + node ifc_bus_acc_fault_f = and(ic_byp_hit_f, ifu_byp_data_err_new) @[ifu_mem_ctl.scala 297:42] + io.ic_data_f <= ic_final_data @[ifu_mem_ctl.scala 298:16] + node _T_1270 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 299:40] + node fetch_req_f_qual = and(io.ic_hit_f, _T_1270) @[ifu_mem_ctl.scala 299:38] wire ifc_region_acc_fault_memory_f : UInt<1> ifc_region_acc_fault_memory_f <= UInt<1>("h00") - node _T_1271 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[ifu_mem_ctl.scala 315:57] - node _T_1272 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 315:82] - node _T_1273 = and(_T_1271, _T_1272) @[ifu_mem_ctl.scala 315:80] - io.ic_access_fault_f <= _T_1273 @[ifu_mem_ctl.scala 315:24] - node _T_1274 = bits(io.iccm_rd_ecc_double_err, 0, 0) @[ifu_mem_ctl.scala 316:62] - node _T_1275 = bits(ifc_region_acc_fault_f, 0, 0) @[ifu_mem_ctl.scala 317:32] - node _T_1276 = bits(ifc_region_acc_fault_memory_f, 0, 0) @[ifu_mem_ctl.scala 318:47] - node _T_1277 = mux(_T_1276, UInt<2>("h03"), UInt<1>("h00")) @[ifu_mem_ctl.scala 318:10] - node _T_1278 = mux(_T_1275, UInt<2>("h02"), _T_1277) @[ifu_mem_ctl.scala 317:8] - node _T_1279 = mux(_T_1274, UInt<1>("h01"), _T_1278) @[ifu_mem_ctl.scala 316:35] - io.ic_access_fault_type_f <= _T_1279 @[ifu_mem_ctl.scala 316:29] - node _T_1280 = and(fetch_req_f_qual, io.ifu_bp_inst_mask_f) @[ifu_mem_ctl.scala 319:45] + node _T_1271 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[ifu_mem_ctl.scala 301:57] + node _T_1272 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 301:82] + node _T_1273 = and(_T_1271, _T_1272) @[ifu_mem_ctl.scala 301:80] + io.ic_access_fault_f <= _T_1273 @[ifu_mem_ctl.scala 301:24] + node _T_1274 = bits(io.iccm_rd_ecc_double_err, 0, 0) @[ifu_mem_ctl.scala 302:62] + node _T_1275 = bits(ifc_region_acc_fault_f, 0, 0) @[ifu_mem_ctl.scala 303:32] + node _T_1276 = bits(ifc_region_acc_fault_memory_f, 0, 0) @[ifu_mem_ctl.scala 304:47] + node _T_1277 = mux(_T_1276, UInt<2>("h03"), UInt<1>("h00")) @[ifu_mem_ctl.scala 304:10] + node _T_1278 = mux(_T_1275, UInt<2>("h02"), _T_1277) @[ifu_mem_ctl.scala 303:8] + node _T_1279 = mux(_T_1274, UInt<1>("h01"), _T_1278) @[ifu_mem_ctl.scala 302:35] + io.ic_access_fault_type_f <= _T_1279 @[ifu_mem_ctl.scala 302:29] + node _T_1280 = and(fetch_req_f_qual, io.ifu_bp_inst_mask_f) @[ifu_mem_ctl.scala 305:45] node _T_1281 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_1282 = eq(vaddr_f, _T_1281) @[ifu_mem_ctl.scala 319:80] - node _T_1283 = eq(_T_1282, UInt<1>("h00")) @[ifu_mem_ctl.scala 319:71] - node _T_1284 = and(_T_1280, _T_1283) @[ifu_mem_ctl.scala 319:69] - node _T_1285 = neq(err_stop_state, UInt<2>("h02")) @[ifu_mem_ctl.scala 319:131] - node _T_1286 = and(_T_1284, _T_1285) @[ifu_mem_ctl.scala 319:114] + node _T_1282 = eq(vaddr_f, _T_1281) @[ifu_mem_ctl.scala 305:80] + node _T_1283 = eq(_T_1282, UInt<1>("h00")) @[ifu_mem_ctl.scala 305:71] + node _T_1284 = and(_T_1280, _T_1283) @[ifu_mem_ctl.scala 305:69] + node _T_1285 = neq(err_stop_state, UInt<2>("h02")) @[ifu_mem_ctl.scala 305:131] + node _T_1286 = and(_T_1284, _T_1285) @[ifu_mem_ctl.scala 305:114] node _T_1287 = cat(_T_1286, fetch_req_f_qual) @[Cat.scala 29:58] - io.ic_fetch_val_f <= _T_1287 @[ifu_mem_ctl.scala 319:21] - node _T_1288 = bits(io.ic_data_f, 1, 0) @[ifu_mem_ctl.scala 320:36] - node two_byte_instr = neq(_T_1288, UInt<2>("h03")) @[ifu_mem_ctl.scala 320:42] + io.ic_fetch_val_f <= _T_1287 @[ifu_mem_ctl.scala 305:21] + node _T_1288 = bits(io.ic_data_f, 1, 0) @[ifu_mem_ctl.scala 306:36] + node two_byte_instr = neq(_T_1288, UInt<2>("h03")) @[ifu_mem_ctl.scala 306:42] wire ic_miss_buff_data_in : UInt<64> ic_miss_buff_data_in <= UInt<1>("h00") wire ifu_bus_rsp_tag : UInt<3> ifu_bus_rsp_tag <= UInt<1>("h00") wire bus_ifu_wr_en : UInt<1> bus_ifu_wr_en <= UInt<1>("h00") - node _T_1289 = eq(ifu_bus_rsp_tag, UInt<1>("h00")) @[ifu_mem_ctl.scala 326:91] - node write_fill_data_0 = and(bus_ifu_wr_en, _T_1289) @[ifu_mem_ctl.scala 326:73] - node _T_1290 = eq(ifu_bus_rsp_tag, UInt<1>("h01")) @[ifu_mem_ctl.scala 326:91] - node write_fill_data_1 = and(bus_ifu_wr_en, _T_1290) @[ifu_mem_ctl.scala 326:73] - node _T_1291 = eq(ifu_bus_rsp_tag, UInt<2>("h02")) @[ifu_mem_ctl.scala 326:91] - node write_fill_data_2 = and(bus_ifu_wr_en, _T_1291) @[ifu_mem_ctl.scala 326:73] - node _T_1292 = eq(ifu_bus_rsp_tag, UInt<2>("h03")) @[ifu_mem_ctl.scala 326:91] - node write_fill_data_3 = and(bus_ifu_wr_en, _T_1292) @[ifu_mem_ctl.scala 326:73] - node _T_1293 = eq(ifu_bus_rsp_tag, UInt<3>("h04")) @[ifu_mem_ctl.scala 326:91] - node write_fill_data_4 = and(bus_ifu_wr_en, _T_1293) @[ifu_mem_ctl.scala 326:73] - node _T_1294 = eq(ifu_bus_rsp_tag, UInt<3>("h05")) @[ifu_mem_ctl.scala 326:91] - node write_fill_data_5 = and(bus_ifu_wr_en, _T_1294) @[ifu_mem_ctl.scala 326:73] - node _T_1295 = eq(ifu_bus_rsp_tag, UInt<3>("h06")) @[ifu_mem_ctl.scala 326:91] - node write_fill_data_6 = and(bus_ifu_wr_en, _T_1295) @[ifu_mem_ctl.scala 326:73] - node _T_1296 = eq(ifu_bus_rsp_tag, UInt<3>("h07")) @[ifu_mem_ctl.scala 326:91] - node write_fill_data_7 = and(bus_ifu_wr_en, _T_1296) @[ifu_mem_ctl.scala 326:73] - wire ic_miss_buff_data : UInt<32>[16] @[ifu_mem_ctl.scala 327:31] + node _T_1289 = eq(ifu_bus_rsp_tag, UInt<1>("h00")) @[ifu_mem_ctl.scala 312:91] + node write_fill_data_0 = and(bus_ifu_wr_en, _T_1289) @[ifu_mem_ctl.scala 312:73] + node _T_1290 = eq(ifu_bus_rsp_tag, UInt<1>("h01")) @[ifu_mem_ctl.scala 312:91] + node write_fill_data_1 = and(bus_ifu_wr_en, _T_1290) @[ifu_mem_ctl.scala 312:73] + node _T_1291 = eq(ifu_bus_rsp_tag, UInt<2>("h02")) @[ifu_mem_ctl.scala 312:91] + node write_fill_data_2 = and(bus_ifu_wr_en, _T_1291) @[ifu_mem_ctl.scala 312:73] + node _T_1292 = eq(ifu_bus_rsp_tag, UInt<2>("h03")) @[ifu_mem_ctl.scala 312:91] + node write_fill_data_3 = and(bus_ifu_wr_en, _T_1292) @[ifu_mem_ctl.scala 312:73] + node _T_1293 = eq(ifu_bus_rsp_tag, UInt<3>("h04")) @[ifu_mem_ctl.scala 312:91] + node write_fill_data_4 = and(bus_ifu_wr_en, _T_1293) @[ifu_mem_ctl.scala 312:73] + node _T_1294 = eq(ifu_bus_rsp_tag, UInt<3>("h05")) @[ifu_mem_ctl.scala 312:91] + node write_fill_data_5 = and(bus_ifu_wr_en, _T_1294) @[ifu_mem_ctl.scala 312:73] + node _T_1295 = eq(ifu_bus_rsp_tag, UInt<3>("h06")) @[ifu_mem_ctl.scala 312:91] + node write_fill_data_6 = and(bus_ifu_wr_en, _T_1295) @[ifu_mem_ctl.scala 312:73] + node _T_1296 = eq(ifu_bus_rsp_tag, UInt<3>("h07")) @[ifu_mem_ctl.scala 312:91] + node write_fill_data_7 = and(bus_ifu_wr_en, _T_1296) @[ifu_mem_ctl.scala 312:73] + wire ic_miss_buff_data : UInt<32>[16] @[ifu_mem_ctl.scala 313:31] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 327:22] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -4444,14 +4424,14 @@ circuit quasar_wrapper : rvclkhdr_11.io.clk <= clock @[lib.scala 328:17] rvclkhdr_11.io.en <= write_fill_data_7 @[lib.scala 329:16] rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_1297 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 330:86] - reg _T_1298 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 330:65] - _T_1298 <= _T_1297 @[ifu_mem_ctl.scala 330:65] - ic_miss_buff_data[0] <= _T_1298 @[ifu_mem_ctl.scala 330:26] - node _T_1299 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 331:88] - reg _T_1300 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 331:67] - _T_1300 <= _T_1299 @[ifu_mem_ctl.scala 331:67] - ic_miss_buff_data[1] <= _T_1300 @[ifu_mem_ctl.scala 331:28] + node _T_1297 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] + reg _T_1298 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] + _T_1298 <= _T_1297 @[ifu_mem_ctl.scala 316:65] + ic_miss_buff_data[0] <= _T_1298 @[ifu_mem_ctl.scala 316:26] + node _T_1299 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 317:88] + reg _T_1300 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] + _T_1300 <= _T_1299 @[ifu_mem_ctl.scala 317:67] + ic_miss_buff_data[1] <= _T_1300 @[ifu_mem_ctl.scala 317:28] inst rvclkhdr_12 of rvclkhdr_12 @[lib.scala 327:22] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset @@ -4500,14 +4480,14 @@ circuit quasar_wrapper : rvclkhdr_19.io.clk <= clock @[lib.scala 328:17] rvclkhdr_19.io.en <= write_fill_data_7 @[lib.scala 329:16] rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_1301 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 330:86] - reg _T_1302 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 330:65] - _T_1302 <= _T_1301 @[ifu_mem_ctl.scala 330:65] - ic_miss_buff_data[2] <= _T_1302 @[ifu_mem_ctl.scala 330:26] - node _T_1303 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 331:88] - reg _T_1304 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 331:67] - _T_1304 <= _T_1303 @[ifu_mem_ctl.scala 331:67] - ic_miss_buff_data[3] <= _T_1304 @[ifu_mem_ctl.scala 331:28] + node _T_1301 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] + reg _T_1302 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] + _T_1302 <= _T_1301 @[ifu_mem_ctl.scala 316:65] + ic_miss_buff_data[2] <= _T_1302 @[ifu_mem_ctl.scala 316:26] + node _T_1303 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 317:88] + reg _T_1304 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] + _T_1304 <= _T_1303 @[ifu_mem_ctl.scala 317:67] + ic_miss_buff_data[3] <= _T_1304 @[ifu_mem_ctl.scala 317:28] inst rvclkhdr_20 of rvclkhdr_20 @[lib.scala 327:22] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset @@ -4556,14 +4536,14 @@ circuit quasar_wrapper : rvclkhdr_27.io.clk <= clock @[lib.scala 328:17] rvclkhdr_27.io.en <= write_fill_data_7 @[lib.scala 329:16] rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_1305 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 330:86] - reg _T_1306 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 330:65] - _T_1306 <= _T_1305 @[ifu_mem_ctl.scala 330:65] - ic_miss_buff_data[4] <= _T_1306 @[ifu_mem_ctl.scala 330:26] - node _T_1307 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 331:88] - reg _T_1308 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 331:67] - _T_1308 <= _T_1307 @[ifu_mem_ctl.scala 331:67] - ic_miss_buff_data[5] <= _T_1308 @[ifu_mem_ctl.scala 331:28] + node _T_1305 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] + reg _T_1306 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] + _T_1306 <= _T_1305 @[ifu_mem_ctl.scala 316:65] + ic_miss_buff_data[4] <= _T_1306 @[ifu_mem_ctl.scala 316:26] + node _T_1307 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 317:88] + reg _T_1308 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] + _T_1308 <= _T_1307 @[ifu_mem_ctl.scala 317:67] + ic_miss_buff_data[5] <= _T_1308 @[ifu_mem_ctl.scala 317:28] inst rvclkhdr_28 of rvclkhdr_28 @[lib.scala 327:22] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset @@ -4612,14 +4592,14 @@ circuit quasar_wrapper : rvclkhdr_35.io.clk <= clock @[lib.scala 328:17] rvclkhdr_35.io.en <= write_fill_data_7 @[lib.scala 329:16] rvclkhdr_35.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_1309 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 330:86] - reg _T_1310 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 330:65] - _T_1310 <= _T_1309 @[ifu_mem_ctl.scala 330:65] - ic_miss_buff_data[6] <= _T_1310 @[ifu_mem_ctl.scala 330:26] - node _T_1311 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 331:88] - reg _T_1312 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 331:67] - _T_1312 <= _T_1311 @[ifu_mem_ctl.scala 331:67] - ic_miss_buff_data[7] <= _T_1312 @[ifu_mem_ctl.scala 331:28] + node _T_1309 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] + reg _T_1310 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] + _T_1310 <= _T_1309 @[ifu_mem_ctl.scala 316:65] + ic_miss_buff_data[6] <= _T_1310 @[ifu_mem_ctl.scala 316:26] + node _T_1311 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 317:88] + reg _T_1312 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] + _T_1312 <= _T_1311 @[ifu_mem_ctl.scala 317:67] + ic_miss_buff_data[7] <= _T_1312 @[ifu_mem_ctl.scala 317:28] inst rvclkhdr_36 of rvclkhdr_36 @[lib.scala 327:22] rvclkhdr_36.clock <= clock rvclkhdr_36.reset <= reset @@ -4668,14 +4648,14 @@ circuit quasar_wrapper : rvclkhdr_43.io.clk <= clock @[lib.scala 328:17] rvclkhdr_43.io.en <= write_fill_data_7 @[lib.scala 329:16] rvclkhdr_43.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_1313 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 330:86] - reg _T_1314 : UInt, rvclkhdr_40.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 330:65] - _T_1314 <= _T_1313 @[ifu_mem_ctl.scala 330:65] - ic_miss_buff_data[8] <= _T_1314 @[ifu_mem_ctl.scala 330:26] - node _T_1315 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 331:88] - reg _T_1316 : UInt, rvclkhdr_40.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 331:67] - _T_1316 <= _T_1315 @[ifu_mem_ctl.scala 331:67] - ic_miss_buff_data[9] <= _T_1316 @[ifu_mem_ctl.scala 331:28] + node _T_1313 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] + reg _T_1314 : UInt, rvclkhdr_40.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] + _T_1314 <= _T_1313 @[ifu_mem_ctl.scala 316:65] + ic_miss_buff_data[8] <= _T_1314 @[ifu_mem_ctl.scala 316:26] + node _T_1315 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 317:88] + reg _T_1316 : UInt, rvclkhdr_40.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] + _T_1316 <= _T_1315 @[ifu_mem_ctl.scala 317:67] + ic_miss_buff_data[9] <= _T_1316 @[ifu_mem_ctl.scala 317:28] inst rvclkhdr_44 of rvclkhdr_44 @[lib.scala 327:22] rvclkhdr_44.clock <= clock rvclkhdr_44.reset <= reset @@ -4724,14 +4704,14 @@ circuit quasar_wrapper : rvclkhdr_51.io.clk <= clock @[lib.scala 328:17] rvclkhdr_51.io.en <= write_fill_data_7 @[lib.scala 329:16] rvclkhdr_51.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_1317 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 330:86] - reg _T_1318 : UInt, rvclkhdr_49.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 330:65] - _T_1318 <= _T_1317 @[ifu_mem_ctl.scala 330:65] - ic_miss_buff_data[10] <= _T_1318 @[ifu_mem_ctl.scala 330:26] - node _T_1319 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 331:88] - reg _T_1320 : UInt, rvclkhdr_49.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 331:67] - _T_1320 <= _T_1319 @[ifu_mem_ctl.scala 331:67] - ic_miss_buff_data[11] <= _T_1320 @[ifu_mem_ctl.scala 331:28] + node _T_1317 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] + reg _T_1318 : UInt, rvclkhdr_49.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] + _T_1318 <= _T_1317 @[ifu_mem_ctl.scala 316:65] + ic_miss_buff_data[10] <= _T_1318 @[ifu_mem_ctl.scala 316:26] + node _T_1319 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 317:88] + reg _T_1320 : UInt, rvclkhdr_49.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] + _T_1320 <= _T_1319 @[ifu_mem_ctl.scala 317:67] + ic_miss_buff_data[11] <= _T_1320 @[ifu_mem_ctl.scala 317:28] inst rvclkhdr_52 of rvclkhdr_52 @[lib.scala 327:22] rvclkhdr_52.clock <= clock rvclkhdr_52.reset <= reset @@ -4780,14 +4760,14 @@ circuit quasar_wrapper : rvclkhdr_59.io.clk <= clock @[lib.scala 328:17] rvclkhdr_59.io.en <= write_fill_data_7 @[lib.scala 329:16] rvclkhdr_59.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_1321 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 330:86] - reg _T_1322 : UInt, rvclkhdr_58.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 330:65] - _T_1322 <= _T_1321 @[ifu_mem_ctl.scala 330:65] - ic_miss_buff_data[12] <= _T_1322 @[ifu_mem_ctl.scala 330:26] - node _T_1323 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 331:88] - reg _T_1324 : UInt, rvclkhdr_58.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 331:67] - _T_1324 <= _T_1323 @[ifu_mem_ctl.scala 331:67] - ic_miss_buff_data[13] <= _T_1324 @[ifu_mem_ctl.scala 331:28] + node _T_1321 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] + reg _T_1322 : UInt, rvclkhdr_58.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] + _T_1322 <= _T_1321 @[ifu_mem_ctl.scala 316:65] + ic_miss_buff_data[12] <= _T_1322 @[ifu_mem_ctl.scala 316:26] + node _T_1323 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 317:88] + reg _T_1324 : UInt, rvclkhdr_58.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] + _T_1324 <= _T_1323 @[ifu_mem_ctl.scala 317:67] + ic_miss_buff_data[13] <= _T_1324 @[ifu_mem_ctl.scala 317:28] inst rvclkhdr_60 of rvclkhdr_60 @[lib.scala 327:22] rvclkhdr_60.clock <= clock rvclkhdr_60.reset <= reset @@ -4836,48 +4816,48 @@ circuit quasar_wrapper : rvclkhdr_67.io.clk <= clock @[lib.scala 328:17] rvclkhdr_67.io.en <= write_fill_data_7 @[lib.scala 329:16] rvclkhdr_67.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_1325 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 330:86] - reg _T_1326 : UInt, rvclkhdr_67.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 330:65] - _T_1326 <= _T_1325 @[ifu_mem_ctl.scala 330:65] - ic_miss_buff_data[14] <= _T_1326 @[ifu_mem_ctl.scala 330:26] - node _T_1327 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 331:88] - reg _T_1328 : UInt, rvclkhdr_67.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 331:67] - _T_1328 <= _T_1327 @[ifu_mem_ctl.scala 331:67] - ic_miss_buff_data[15] <= _T_1328 @[ifu_mem_ctl.scala 331:28] + node _T_1325 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] + reg _T_1326 : UInt, rvclkhdr_67.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] + _T_1326 <= _T_1325 @[ifu_mem_ctl.scala 316:65] + ic_miss_buff_data[14] <= _T_1326 @[ifu_mem_ctl.scala 316:26] + node _T_1327 = bits(ic_miss_buff_data_in, 63, 32) @[ifu_mem_ctl.scala 317:88] + reg _T_1328 : UInt, rvclkhdr_67.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] + _T_1328 <= _T_1327 @[ifu_mem_ctl.scala 317:67] + ic_miss_buff_data[15] <= _T_1328 @[ifu_mem_ctl.scala 317:28] wire ic_miss_buff_data_valid : UInt<8> ic_miss_buff_data_valid <= UInt<1>("h00") - node _T_1329 = bits(ic_miss_buff_data_valid, 0, 0) @[ifu_mem_ctl.scala 333:113] - node _T_1330 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 333:118] - node _T_1331 = and(_T_1329, _T_1330) @[ifu_mem_ctl.scala 333:116] - node ic_miss_buff_data_valid_in_0 = or(write_fill_data_0, _T_1331) @[ifu_mem_ctl.scala 333:88] - node _T_1332 = bits(ic_miss_buff_data_valid, 1, 1) @[ifu_mem_ctl.scala 333:113] - node _T_1333 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 333:118] - node _T_1334 = and(_T_1332, _T_1333) @[ifu_mem_ctl.scala 333:116] - node ic_miss_buff_data_valid_in_1 = or(write_fill_data_1, _T_1334) @[ifu_mem_ctl.scala 333:88] - node _T_1335 = bits(ic_miss_buff_data_valid, 2, 2) @[ifu_mem_ctl.scala 333:113] - node _T_1336 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 333:118] - node _T_1337 = and(_T_1335, _T_1336) @[ifu_mem_ctl.scala 333:116] - node ic_miss_buff_data_valid_in_2 = or(write_fill_data_2, _T_1337) @[ifu_mem_ctl.scala 333:88] - node _T_1338 = bits(ic_miss_buff_data_valid, 3, 3) @[ifu_mem_ctl.scala 333:113] - node _T_1339 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 333:118] - node _T_1340 = and(_T_1338, _T_1339) @[ifu_mem_ctl.scala 333:116] - node ic_miss_buff_data_valid_in_3 = or(write_fill_data_3, _T_1340) @[ifu_mem_ctl.scala 333:88] - node _T_1341 = bits(ic_miss_buff_data_valid, 4, 4) @[ifu_mem_ctl.scala 333:113] - node _T_1342 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 333:118] - node _T_1343 = and(_T_1341, _T_1342) @[ifu_mem_ctl.scala 333:116] - node ic_miss_buff_data_valid_in_4 = or(write_fill_data_4, _T_1343) @[ifu_mem_ctl.scala 333:88] - node _T_1344 = bits(ic_miss_buff_data_valid, 5, 5) @[ifu_mem_ctl.scala 333:113] - node _T_1345 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 333:118] - node _T_1346 = and(_T_1344, _T_1345) @[ifu_mem_ctl.scala 333:116] - node ic_miss_buff_data_valid_in_5 = or(write_fill_data_5, _T_1346) @[ifu_mem_ctl.scala 333:88] - node _T_1347 = bits(ic_miss_buff_data_valid, 6, 6) @[ifu_mem_ctl.scala 333:113] - node _T_1348 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 333:118] - node _T_1349 = and(_T_1347, _T_1348) @[ifu_mem_ctl.scala 333:116] - node ic_miss_buff_data_valid_in_6 = or(write_fill_data_6, _T_1349) @[ifu_mem_ctl.scala 333:88] - node _T_1350 = bits(ic_miss_buff_data_valid, 7, 7) @[ifu_mem_ctl.scala 333:113] - node _T_1351 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 333:118] - node _T_1352 = and(_T_1350, _T_1351) @[ifu_mem_ctl.scala 333:116] - node ic_miss_buff_data_valid_in_7 = or(write_fill_data_7, _T_1352) @[ifu_mem_ctl.scala 333:88] + node _T_1329 = bits(ic_miss_buff_data_valid, 0, 0) @[ifu_mem_ctl.scala 319:113] + node _T_1330 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 319:118] + node _T_1331 = and(_T_1329, _T_1330) @[ifu_mem_ctl.scala 319:116] + node ic_miss_buff_data_valid_in_0 = or(write_fill_data_0, _T_1331) @[ifu_mem_ctl.scala 319:88] + node _T_1332 = bits(ic_miss_buff_data_valid, 1, 1) @[ifu_mem_ctl.scala 319:113] + node _T_1333 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 319:118] + node _T_1334 = and(_T_1332, _T_1333) @[ifu_mem_ctl.scala 319:116] + node ic_miss_buff_data_valid_in_1 = or(write_fill_data_1, _T_1334) @[ifu_mem_ctl.scala 319:88] + node _T_1335 = bits(ic_miss_buff_data_valid, 2, 2) @[ifu_mem_ctl.scala 319:113] + node _T_1336 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 319:118] + node _T_1337 = and(_T_1335, _T_1336) @[ifu_mem_ctl.scala 319:116] + node ic_miss_buff_data_valid_in_2 = or(write_fill_data_2, _T_1337) @[ifu_mem_ctl.scala 319:88] + node _T_1338 = bits(ic_miss_buff_data_valid, 3, 3) @[ifu_mem_ctl.scala 319:113] + node _T_1339 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 319:118] + node _T_1340 = and(_T_1338, _T_1339) @[ifu_mem_ctl.scala 319:116] + node ic_miss_buff_data_valid_in_3 = or(write_fill_data_3, _T_1340) @[ifu_mem_ctl.scala 319:88] + node _T_1341 = bits(ic_miss_buff_data_valid, 4, 4) @[ifu_mem_ctl.scala 319:113] + node _T_1342 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 319:118] + node _T_1343 = and(_T_1341, _T_1342) @[ifu_mem_ctl.scala 319:116] + node ic_miss_buff_data_valid_in_4 = or(write_fill_data_4, _T_1343) @[ifu_mem_ctl.scala 319:88] + node _T_1344 = bits(ic_miss_buff_data_valid, 5, 5) @[ifu_mem_ctl.scala 319:113] + node _T_1345 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 319:118] + node _T_1346 = and(_T_1344, _T_1345) @[ifu_mem_ctl.scala 319:116] + node ic_miss_buff_data_valid_in_5 = or(write_fill_data_5, _T_1346) @[ifu_mem_ctl.scala 319:88] + node _T_1347 = bits(ic_miss_buff_data_valid, 6, 6) @[ifu_mem_ctl.scala 319:113] + node _T_1348 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 319:118] + node _T_1349 = and(_T_1347, _T_1348) @[ifu_mem_ctl.scala 319:116] + node ic_miss_buff_data_valid_in_6 = or(write_fill_data_6, _T_1349) @[ifu_mem_ctl.scala 319:88] + node _T_1350 = bits(ic_miss_buff_data_valid, 7, 7) @[ifu_mem_ctl.scala 319:113] + node _T_1351 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 319:118] + node _T_1352 = and(_T_1350, _T_1351) @[ifu_mem_ctl.scala 319:116] + node ic_miss_buff_data_valid_in_7 = or(write_fill_data_7, _T_1352) @[ifu_mem_ctl.scala 319:88] node _T_1353 = cat(ic_miss_buff_data_valid_in_7, ic_miss_buff_data_valid_in_6) @[Cat.scala 29:58] node _T_1354 = cat(_T_1353, ic_miss_buff_data_valid_in_5) @[Cat.scala 29:58] node _T_1355 = cat(_T_1354, ic_miss_buff_data_valid_in_4) @[Cat.scala 29:58] @@ -4885,53 +4865,53 @@ circuit quasar_wrapper : node _T_1357 = cat(_T_1356, ic_miss_buff_data_valid_in_2) @[Cat.scala 29:58] node _T_1358 = cat(_T_1357, ic_miss_buff_data_valid_in_1) @[Cat.scala 29:58] node _T_1359 = cat(_T_1358, ic_miss_buff_data_valid_in_0) @[Cat.scala 29:58] - reg _T_1360 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 334:60] - _T_1360 <= _T_1359 @[ifu_mem_ctl.scala 334:60] - ic_miss_buff_data_valid <= _T_1360 @[ifu_mem_ctl.scala 334:27] + reg _T_1360 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 320:60] + _T_1360 <= _T_1359 @[ifu_mem_ctl.scala 320:60] + ic_miss_buff_data_valid <= _T_1360 @[ifu_mem_ctl.scala 320:27] wire bus_ifu_wr_data_error : UInt<1> bus_ifu_wr_data_error <= UInt<1>("h00") wire ic_miss_buff_data_error : UInt<8> ic_miss_buff_data_error <= UInt<1>("h00") - node _T_1361 = bits(write_fill_data_0, 0, 0) @[ifu_mem_ctl.scala 337:92] - node _T_1362 = bits(ic_miss_buff_data_error, 0, 0) @[ifu_mem_ctl.scala 338:28] - node _T_1363 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 338:34] - node _T_1364 = and(_T_1362, _T_1363) @[ifu_mem_ctl.scala 338:32] - node ic_miss_buff_data_error_in_0 = mux(_T_1361, bus_ifu_wr_data_error, _T_1364) @[ifu_mem_ctl.scala 337:72] - node _T_1365 = bits(write_fill_data_1, 0, 0) @[ifu_mem_ctl.scala 337:92] - node _T_1366 = bits(ic_miss_buff_data_error, 1, 1) @[ifu_mem_ctl.scala 338:28] - node _T_1367 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 338:34] - node _T_1368 = and(_T_1366, _T_1367) @[ifu_mem_ctl.scala 338:32] - node ic_miss_buff_data_error_in_1 = mux(_T_1365, bus_ifu_wr_data_error, _T_1368) @[ifu_mem_ctl.scala 337:72] - node _T_1369 = bits(write_fill_data_2, 0, 0) @[ifu_mem_ctl.scala 337:92] - node _T_1370 = bits(ic_miss_buff_data_error, 2, 2) @[ifu_mem_ctl.scala 338:28] - node _T_1371 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 338:34] - node _T_1372 = and(_T_1370, _T_1371) @[ifu_mem_ctl.scala 338:32] - node ic_miss_buff_data_error_in_2 = mux(_T_1369, bus_ifu_wr_data_error, _T_1372) @[ifu_mem_ctl.scala 337:72] - node _T_1373 = bits(write_fill_data_3, 0, 0) @[ifu_mem_ctl.scala 337:92] - node _T_1374 = bits(ic_miss_buff_data_error, 3, 3) @[ifu_mem_ctl.scala 338:28] - node _T_1375 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 338:34] - node _T_1376 = and(_T_1374, _T_1375) @[ifu_mem_ctl.scala 338:32] - node ic_miss_buff_data_error_in_3 = mux(_T_1373, bus_ifu_wr_data_error, _T_1376) @[ifu_mem_ctl.scala 337:72] - node _T_1377 = bits(write_fill_data_4, 0, 0) @[ifu_mem_ctl.scala 337:92] - node _T_1378 = bits(ic_miss_buff_data_error, 4, 4) @[ifu_mem_ctl.scala 338:28] - node _T_1379 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 338:34] - node _T_1380 = and(_T_1378, _T_1379) @[ifu_mem_ctl.scala 338:32] - node ic_miss_buff_data_error_in_4 = mux(_T_1377, bus_ifu_wr_data_error, _T_1380) @[ifu_mem_ctl.scala 337:72] - node _T_1381 = bits(write_fill_data_5, 0, 0) @[ifu_mem_ctl.scala 337:92] - node _T_1382 = bits(ic_miss_buff_data_error, 5, 5) @[ifu_mem_ctl.scala 338:28] - node _T_1383 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 338:34] - node _T_1384 = and(_T_1382, _T_1383) @[ifu_mem_ctl.scala 338:32] - node ic_miss_buff_data_error_in_5 = mux(_T_1381, bus_ifu_wr_data_error, _T_1384) @[ifu_mem_ctl.scala 337:72] - node _T_1385 = bits(write_fill_data_6, 0, 0) @[ifu_mem_ctl.scala 337:92] - node _T_1386 = bits(ic_miss_buff_data_error, 6, 6) @[ifu_mem_ctl.scala 338:28] - node _T_1387 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 338:34] - node _T_1388 = and(_T_1386, _T_1387) @[ifu_mem_ctl.scala 338:32] - node ic_miss_buff_data_error_in_6 = mux(_T_1385, bus_ifu_wr_data_error, _T_1388) @[ifu_mem_ctl.scala 337:72] - node _T_1389 = bits(write_fill_data_7, 0, 0) @[ifu_mem_ctl.scala 337:92] - node _T_1390 = bits(ic_miss_buff_data_error, 7, 7) @[ifu_mem_ctl.scala 338:28] - node _T_1391 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 338:34] - node _T_1392 = and(_T_1390, _T_1391) @[ifu_mem_ctl.scala 338:32] - node ic_miss_buff_data_error_in_7 = mux(_T_1389, bus_ifu_wr_data_error, _T_1392) @[ifu_mem_ctl.scala 337:72] + node _T_1361 = bits(write_fill_data_0, 0, 0) @[ifu_mem_ctl.scala 323:92] + node _T_1362 = bits(ic_miss_buff_data_error, 0, 0) @[ifu_mem_ctl.scala 324:28] + node _T_1363 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 324:34] + node _T_1364 = and(_T_1362, _T_1363) @[ifu_mem_ctl.scala 324:32] + node ic_miss_buff_data_error_in_0 = mux(_T_1361, bus_ifu_wr_data_error, _T_1364) @[ifu_mem_ctl.scala 323:72] + node _T_1365 = bits(write_fill_data_1, 0, 0) @[ifu_mem_ctl.scala 323:92] + node _T_1366 = bits(ic_miss_buff_data_error, 1, 1) @[ifu_mem_ctl.scala 324:28] + node _T_1367 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 324:34] + node _T_1368 = and(_T_1366, _T_1367) @[ifu_mem_ctl.scala 324:32] + node ic_miss_buff_data_error_in_1 = mux(_T_1365, bus_ifu_wr_data_error, _T_1368) @[ifu_mem_ctl.scala 323:72] + node _T_1369 = bits(write_fill_data_2, 0, 0) @[ifu_mem_ctl.scala 323:92] + node _T_1370 = bits(ic_miss_buff_data_error, 2, 2) @[ifu_mem_ctl.scala 324:28] + node _T_1371 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 324:34] + node _T_1372 = and(_T_1370, _T_1371) @[ifu_mem_ctl.scala 324:32] + node ic_miss_buff_data_error_in_2 = mux(_T_1369, bus_ifu_wr_data_error, _T_1372) @[ifu_mem_ctl.scala 323:72] + node _T_1373 = bits(write_fill_data_3, 0, 0) @[ifu_mem_ctl.scala 323:92] + node _T_1374 = bits(ic_miss_buff_data_error, 3, 3) @[ifu_mem_ctl.scala 324:28] + node _T_1375 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 324:34] + node _T_1376 = and(_T_1374, _T_1375) @[ifu_mem_ctl.scala 324:32] + node ic_miss_buff_data_error_in_3 = mux(_T_1373, bus_ifu_wr_data_error, _T_1376) @[ifu_mem_ctl.scala 323:72] + node _T_1377 = bits(write_fill_data_4, 0, 0) @[ifu_mem_ctl.scala 323:92] + node _T_1378 = bits(ic_miss_buff_data_error, 4, 4) @[ifu_mem_ctl.scala 324:28] + node _T_1379 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 324:34] + node _T_1380 = and(_T_1378, _T_1379) @[ifu_mem_ctl.scala 324:32] + node ic_miss_buff_data_error_in_4 = mux(_T_1377, bus_ifu_wr_data_error, _T_1380) @[ifu_mem_ctl.scala 323:72] + node _T_1381 = bits(write_fill_data_5, 0, 0) @[ifu_mem_ctl.scala 323:92] + node _T_1382 = bits(ic_miss_buff_data_error, 5, 5) @[ifu_mem_ctl.scala 324:28] + node _T_1383 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 324:34] + node _T_1384 = and(_T_1382, _T_1383) @[ifu_mem_ctl.scala 324:32] + node ic_miss_buff_data_error_in_5 = mux(_T_1381, bus_ifu_wr_data_error, _T_1384) @[ifu_mem_ctl.scala 323:72] + node _T_1385 = bits(write_fill_data_6, 0, 0) @[ifu_mem_ctl.scala 323:92] + node _T_1386 = bits(ic_miss_buff_data_error, 6, 6) @[ifu_mem_ctl.scala 324:28] + node _T_1387 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 324:34] + node _T_1388 = and(_T_1386, _T_1387) @[ifu_mem_ctl.scala 324:32] + node ic_miss_buff_data_error_in_6 = mux(_T_1385, bus_ifu_wr_data_error, _T_1388) @[ifu_mem_ctl.scala 323:72] + node _T_1389 = bits(write_fill_data_7, 0, 0) @[ifu_mem_ctl.scala 323:92] + node _T_1390 = bits(ic_miss_buff_data_error, 7, 7) @[ifu_mem_ctl.scala 324:28] + node _T_1391 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 324:34] + node _T_1392 = and(_T_1390, _T_1391) @[ifu_mem_ctl.scala 324:32] + node ic_miss_buff_data_error_in_7 = mux(_T_1389, bus_ifu_wr_data_error, _T_1392) @[ifu_mem_ctl.scala 323:72] node _T_1393 = cat(ic_miss_buff_data_error_in_7, ic_miss_buff_data_error_in_6) @[Cat.scala 29:58] node _T_1394 = cat(_T_1393, ic_miss_buff_data_error_in_5) @[Cat.scala 29:58] node _T_1395 = cat(_T_1394, ic_miss_buff_data_error_in_4) @[Cat.scala 29:58] @@ -4939,37 +4919,37 @@ circuit quasar_wrapper : node _T_1397 = cat(_T_1396, ic_miss_buff_data_error_in_2) @[Cat.scala 29:58] node _T_1398 = cat(_T_1397, ic_miss_buff_data_error_in_1) @[Cat.scala 29:58] node _T_1399 = cat(_T_1398, ic_miss_buff_data_error_in_0) @[Cat.scala 29:58] - reg _T_1400 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 339:60] - _T_1400 <= _T_1399 @[ifu_mem_ctl.scala 339:60] - ic_miss_buff_data_error <= _T_1400 @[ifu_mem_ctl.scala 339:27] - node bypass_index = bits(imb_ff, 4, 0) @[ifu_mem_ctl.scala 342:28] - node _T_1401 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 343:42] - node _T_1402 = add(_T_1401, UInt<1>("h01")) @[ifu_mem_ctl.scala 343:70] - node bypass_index_5_3_inc = tail(_T_1402, 1) @[ifu_mem_ctl.scala 343:70] - node _T_1403 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 344:87] - node _T_1404 = eq(_T_1403, UInt<1>("h00")) @[ifu_mem_ctl.scala 344:114] - node _T_1405 = bits(_T_1404, 0, 0) @[ifu_mem_ctl.scala 344:122] - node _T_1406 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 344:87] - node _T_1407 = eq(_T_1406, UInt<1>("h01")) @[ifu_mem_ctl.scala 344:114] - node _T_1408 = bits(_T_1407, 0, 0) @[ifu_mem_ctl.scala 344:122] - node _T_1409 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 344:87] - node _T_1410 = eq(_T_1409, UInt<2>("h02")) @[ifu_mem_ctl.scala 344:114] - node _T_1411 = bits(_T_1410, 0, 0) @[ifu_mem_ctl.scala 344:122] - node _T_1412 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 344:87] - node _T_1413 = eq(_T_1412, UInt<2>("h03")) @[ifu_mem_ctl.scala 344:114] - node _T_1414 = bits(_T_1413, 0, 0) @[ifu_mem_ctl.scala 344:122] - node _T_1415 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 344:87] - node _T_1416 = eq(_T_1415, UInt<3>("h04")) @[ifu_mem_ctl.scala 344:114] - node _T_1417 = bits(_T_1416, 0, 0) @[ifu_mem_ctl.scala 344:122] - node _T_1418 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 344:87] - node _T_1419 = eq(_T_1418, UInt<3>("h05")) @[ifu_mem_ctl.scala 344:114] - node _T_1420 = bits(_T_1419, 0, 0) @[ifu_mem_ctl.scala 344:122] - node _T_1421 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 344:87] - node _T_1422 = eq(_T_1421, UInt<3>("h06")) @[ifu_mem_ctl.scala 344:114] - node _T_1423 = bits(_T_1422, 0, 0) @[ifu_mem_ctl.scala 344:122] - node _T_1424 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 344:87] - node _T_1425 = eq(_T_1424, UInt<3>("h07")) @[ifu_mem_ctl.scala 344:114] - node _T_1426 = bits(_T_1425, 0, 0) @[ifu_mem_ctl.scala 344:122] + reg _T_1400 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 325:60] + _T_1400 <= _T_1399 @[ifu_mem_ctl.scala 325:60] + ic_miss_buff_data_error <= _T_1400 @[ifu_mem_ctl.scala 325:27] + node bypass_index = bits(imb_ff, 4, 0) @[ifu_mem_ctl.scala 328:28] + node _T_1401 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 329:42] + node _T_1402 = add(_T_1401, UInt<1>("h01")) @[ifu_mem_ctl.scala 329:70] + node bypass_index_5_3_inc = tail(_T_1402, 1) @[ifu_mem_ctl.scala 329:70] + node _T_1403 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 330:87] + node _T_1404 = eq(_T_1403, UInt<1>("h00")) @[ifu_mem_ctl.scala 330:114] + node _T_1405 = bits(_T_1404, 0, 0) @[ifu_mem_ctl.scala 330:122] + node _T_1406 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 330:87] + node _T_1407 = eq(_T_1406, UInt<1>("h01")) @[ifu_mem_ctl.scala 330:114] + node _T_1408 = bits(_T_1407, 0, 0) @[ifu_mem_ctl.scala 330:122] + node _T_1409 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 330:87] + node _T_1410 = eq(_T_1409, UInt<2>("h02")) @[ifu_mem_ctl.scala 330:114] + node _T_1411 = bits(_T_1410, 0, 0) @[ifu_mem_ctl.scala 330:122] + node _T_1412 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 330:87] + node _T_1413 = eq(_T_1412, UInt<2>("h03")) @[ifu_mem_ctl.scala 330:114] + node _T_1414 = bits(_T_1413, 0, 0) @[ifu_mem_ctl.scala 330:122] + node _T_1415 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 330:87] + node _T_1416 = eq(_T_1415, UInt<3>("h04")) @[ifu_mem_ctl.scala 330:114] + node _T_1417 = bits(_T_1416, 0, 0) @[ifu_mem_ctl.scala 330:122] + node _T_1418 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 330:87] + node _T_1419 = eq(_T_1418, UInt<3>("h05")) @[ifu_mem_ctl.scala 330:114] + node _T_1420 = bits(_T_1419, 0, 0) @[ifu_mem_ctl.scala 330:122] + node _T_1421 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 330:87] + node _T_1422 = eq(_T_1421, UInt<3>("h06")) @[ifu_mem_ctl.scala 330:114] + node _T_1423 = bits(_T_1422, 0, 0) @[ifu_mem_ctl.scala 330:122] + node _T_1424 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 330:87] + node _T_1425 = eq(_T_1424, UInt<3>("h07")) @[ifu_mem_ctl.scala 330:114] + node _T_1426 = bits(_T_1425, 0, 0) @[ifu_mem_ctl.scala 330:122] node _T_1427 = mux(_T_1405, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1428 = mux(_T_1408, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1429 = mux(_T_1411, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72] @@ -4987,44 +4967,44 @@ circuit quasar_wrapper : node _T_1441 = or(_T_1440, _T_1434) @[Mux.scala 27:72] wire bypass_valid_value_check : UInt<1> @[Mux.scala 27:72] bypass_valid_value_check <= _T_1441 @[Mux.scala 27:72] - node _T_1442 = bits(bypass_index, 1, 1) @[ifu_mem_ctl.scala 345:71] - node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[ifu_mem_ctl.scala 345:58] - node _T_1444 = and(bypass_valid_value_check, _T_1443) @[ifu_mem_ctl.scala 345:56] - node _T_1445 = bits(bypass_index, 0, 0) @[ifu_mem_ctl.scala 345:90] - node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[ifu_mem_ctl.scala 345:77] - node _T_1447 = and(_T_1444, _T_1446) @[ifu_mem_ctl.scala 345:75] - node _T_1448 = bits(bypass_index, 1, 1) @[ifu_mem_ctl.scala 346:71] - node _T_1449 = eq(_T_1448, UInt<1>("h00")) @[ifu_mem_ctl.scala 346:58] - node _T_1450 = and(bypass_valid_value_check, _T_1449) @[ifu_mem_ctl.scala 346:56] - node _T_1451 = bits(bypass_index, 0, 0) @[ifu_mem_ctl.scala 346:89] - node _T_1452 = and(_T_1450, _T_1451) @[ifu_mem_ctl.scala 346:75] - node _T_1453 = or(_T_1447, _T_1452) @[ifu_mem_ctl.scala 345:95] - node _T_1454 = bits(bypass_index, 1, 1) @[ifu_mem_ctl.scala 347:70] - node _T_1455 = and(bypass_valid_value_check, _T_1454) @[ifu_mem_ctl.scala 347:56] - node _T_1456 = bits(bypass_index, 0, 0) @[ifu_mem_ctl.scala 347:89] - node _T_1457 = eq(_T_1456, UInt<1>("h00")) @[ifu_mem_ctl.scala 347:76] - node _T_1458 = and(_T_1455, _T_1457) @[ifu_mem_ctl.scala 347:74] - node _T_1459 = or(_T_1453, _T_1458) @[ifu_mem_ctl.scala 346:94] - node _T_1460 = bits(bypass_index, 1, 1) @[ifu_mem_ctl.scala 348:47] - node _T_1461 = and(bypass_valid_value_check, _T_1460) @[ifu_mem_ctl.scala 348:33] - node _T_1462 = bits(bypass_index, 0, 0) @[ifu_mem_ctl.scala 348:65] - node _T_1463 = and(_T_1461, _T_1462) @[ifu_mem_ctl.scala 348:51] - node _T_1464 = eq(bypass_index_5_3_inc, UInt<1>("h00")) @[ifu_mem_ctl.scala 348:132] - node _T_1465 = bits(_T_1464, 0, 0) @[ifu_mem_ctl.scala 348:140] - node _T_1466 = eq(bypass_index_5_3_inc, UInt<1>("h01")) @[ifu_mem_ctl.scala 348:132] - node _T_1467 = bits(_T_1466, 0, 0) @[ifu_mem_ctl.scala 348:140] - node _T_1468 = eq(bypass_index_5_3_inc, UInt<2>("h02")) @[ifu_mem_ctl.scala 348:132] - node _T_1469 = bits(_T_1468, 0, 0) @[ifu_mem_ctl.scala 348:140] - node _T_1470 = eq(bypass_index_5_3_inc, UInt<2>("h03")) @[ifu_mem_ctl.scala 348:132] - node _T_1471 = bits(_T_1470, 0, 0) @[ifu_mem_ctl.scala 348:140] - node _T_1472 = eq(bypass_index_5_3_inc, UInt<3>("h04")) @[ifu_mem_ctl.scala 348:132] - node _T_1473 = bits(_T_1472, 0, 0) @[ifu_mem_ctl.scala 348:140] - node _T_1474 = eq(bypass_index_5_3_inc, UInt<3>("h05")) @[ifu_mem_ctl.scala 348:132] - node _T_1475 = bits(_T_1474, 0, 0) @[ifu_mem_ctl.scala 348:140] - node _T_1476 = eq(bypass_index_5_3_inc, UInt<3>("h06")) @[ifu_mem_ctl.scala 348:132] - node _T_1477 = bits(_T_1476, 0, 0) @[ifu_mem_ctl.scala 348:140] - node _T_1478 = eq(bypass_index_5_3_inc, UInt<3>("h07")) @[ifu_mem_ctl.scala 348:132] - node _T_1479 = bits(_T_1478, 0, 0) @[ifu_mem_ctl.scala 348:140] + node _T_1442 = bits(bypass_index, 1, 1) @[ifu_mem_ctl.scala 331:71] + node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[ifu_mem_ctl.scala 331:58] + node _T_1444 = and(bypass_valid_value_check, _T_1443) @[ifu_mem_ctl.scala 331:56] + node _T_1445 = bits(bypass_index, 0, 0) @[ifu_mem_ctl.scala 331:90] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[ifu_mem_ctl.scala 331:77] + node _T_1447 = and(_T_1444, _T_1446) @[ifu_mem_ctl.scala 331:75] + node _T_1448 = bits(bypass_index, 1, 1) @[ifu_mem_ctl.scala 332:71] + node _T_1449 = eq(_T_1448, UInt<1>("h00")) @[ifu_mem_ctl.scala 332:58] + node _T_1450 = and(bypass_valid_value_check, _T_1449) @[ifu_mem_ctl.scala 332:56] + node _T_1451 = bits(bypass_index, 0, 0) @[ifu_mem_ctl.scala 332:89] + node _T_1452 = and(_T_1450, _T_1451) @[ifu_mem_ctl.scala 332:75] + node _T_1453 = or(_T_1447, _T_1452) @[ifu_mem_ctl.scala 331:95] + node _T_1454 = bits(bypass_index, 1, 1) @[ifu_mem_ctl.scala 333:70] + node _T_1455 = and(bypass_valid_value_check, _T_1454) @[ifu_mem_ctl.scala 333:56] + node _T_1456 = bits(bypass_index, 0, 0) @[ifu_mem_ctl.scala 333:89] + node _T_1457 = eq(_T_1456, UInt<1>("h00")) @[ifu_mem_ctl.scala 333:76] + node _T_1458 = and(_T_1455, _T_1457) @[ifu_mem_ctl.scala 333:74] + node _T_1459 = or(_T_1453, _T_1458) @[ifu_mem_ctl.scala 332:94] + node _T_1460 = bits(bypass_index, 1, 1) @[ifu_mem_ctl.scala 334:47] + node _T_1461 = and(bypass_valid_value_check, _T_1460) @[ifu_mem_ctl.scala 334:33] + node _T_1462 = bits(bypass_index, 0, 0) @[ifu_mem_ctl.scala 334:65] + node _T_1463 = and(_T_1461, _T_1462) @[ifu_mem_ctl.scala 334:51] + node _T_1464 = eq(bypass_index_5_3_inc, UInt<1>("h00")) @[ifu_mem_ctl.scala 334:132] + node _T_1465 = bits(_T_1464, 0, 0) @[ifu_mem_ctl.scala 334:140] + node _T_1466 = eq(bypass_index_5_3_inc, UInt<1>("h01")) @[ifu_mem_ctl.scala 334:132] + node _T_1467 = bits(_T_1466, 0, 0) @[ifu_mem_ctl.scala 334:140] + node _T_1468 = eq(bypass_index_5_3_inc, UInt<2>("h02")) @[ifu_mem_ctl.scala 334:132] + node _T_1469 = bits(_T_1468, 0, 0) @[ifu_mem_ctl.scala 334:140] + node _T_1470 = eq(bypass_index_5_3_inc, UInt<2>("h03")) @[ifu_mem_ctl.scala 334:132] + node _T_1471 = bits(_T_1470, 0, 0) @[ifu_mem_ctl.scala 334:140] + node _T_1472 = eq(bypass_index_5_3_inc, UInt<3>("h04")) @[ifu_mem_ctl.scala 334:132] + node _T_1473 = bits(_T_1472, 0, 0) @[ifu_mem_ctl.scala 334:140] + node _T_1474 = eq(bypass_index_5_3_inc, UInt<3>("h05")) @[ifu_mem_ctl.scala 334:132] + node _T_1475 = bits(_T_1474, 0, 0) @[ifu_mem_ctl.scala 334:140] + node _T_1476 = eq(bypass_index_5_3_inc, UInt<3>("h06")) @[ifu_mem_ctl.scala 334:132] + node _T_1477 = bits(_T_1476, 0, 0) @[ifu_mem_ctl.scala 334:140] + node _T_1478 = eq(bypass_index_5_3_inc, UInt<3>("h07")) @[ifu_mem_ctl.scala 334:132] + node _T_1479 = bits(_T_1478, 0, 0) @[ifu_mem_ctl.scala 334:140] node _T_1480 = mux(_T_1465, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1481 = mux(_T_1467, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1482 = mux(_T_1469, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5042,79 +5022,79 @@ circuit quasar_wrapper : node _T_1494 = or(_T_1493, _T_1487) @[Mux.scala 27:72] wire _T_1495 : UInt<1> @[Mux.scala 27:72] _T_1495 <= _T_1494 @[Mux.scala 27:72] - node _T_1496 = and(_T_1463, _T_1495) @[ifu_mem_ctl.scala 348:69] - node _T_1497 = or(_T_1459, _T_1496) @[ifu_mem_ctl.scala 347:94] - node _T_1498 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 349:70] + node _T_1496 = and(_T_1463, _T_1495) @[ifu_mem_ctl.scala 334:69] + node _T_1497 = or(_T_1459, _T_1496) @[ifu_mem_ctl.scala 333:94] + node _T_1498 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 335:70] node _T_1499 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_1500 = eq(_T_1498, _T_1499) @[ifu_mem_ctl.scala 349:95] - node _T_1501 = and(bypass_valid_value_check, _T_1500) @[ifu_mem_ctl.scala 349:56] - node bypass_data_ready_in = or(_T_1497, _T_1501) @[ifu_mem_ctl.scala 348:181] + node _T_1500 = eq(_T_1498, _T_1499) @[ifu_mem_ctl.scala 335:95] + node _T_1501 = and(bypass_valid_value_check, _T_1500) @[ifu_mem_ctl.scala 335:56] + node bypass_data_ready_in = or(_T_1497, _T_1501) @[ifu_mem_ctl.scala 334:181] wire ic_crit_wd_rdy_new_ff : UInt<1> ic_crit_wd_rdy_new_ff <= UInt<1>("h00") - node _T_1502 = and(bypass_data_ready_in, crit_wd_byp_ok_ff) @[ifu_mem_ctl.scala 353:53] - node _T_1503 = and(_T_1502, uncacheable_miss_ff) @[ifu_mem_ctl.scala 353:73] - node _T_1504 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 353:98] - node _T_1505 = and(_T_1503, _T_1504) @[ifu_mem_ctl.scala 353:96] - node _T_1506 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 353:120] - node _T_1507 = and(_T_1505, _T_1506) @[ifu_mem_ctl.scala 353:118] - node _T_1508 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 354:75] - node _T_1509 = and(crit_wd_byp_ok_ff, _T_1508) @[ifu_mem_ctl.scala 354:73] - node _T_1510 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 354:98] - node _T_1511 = and(_T_1509, _T_1510) @[ifu_mem_ctl.scala 354:96] - node _T_1512 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 354:120] - node _T_1513 = and(_T_1511, _T_1512) @[ifu_mem_ctl.scala 354:118] - node _T_1514 = or(_T_1507, _T_1513) @[ifu_mem_ctl.scala 353:143] - node _T_1515 = and(ic_crit_wd_rdy_new_ff, crit_wd_byp_ok_ff) @[ifu_mem_ctl.scala 355:54] - node _T_1516 = eq(fetch_req_icache_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 355:76] - node _T_1517 = and(_T_1515, _T_1516) @[ifu_mem_ctl.scala 355:74] - node _T_1518 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 355:98] - node _T_1519 = and(_T_1517, _T_1518) @[ifu_mem_ctl.scala 355:96] - node ic_crit_wd_rdy_new_in = or(_T_1514, _T_1519) @[ifu_mem_ctl.scala 354:143] - reg _T_1520 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 356:58] - _T_1520 <= ic_crit_wd_rdy_new_in @[ifu_mem_ctl.scala 356:58] - ic_crit_wd_rdy_new_ff <= _T_1520 @[ifu_mem_ctl.scala 356:25] - node byp_fetch_index = bits(ifu_fetch_addr_int_f, 4, 0) @[ifu_mem_ctl.scala 357:45] - node _T_1521 = bits(ifu_fetch_addr_int_f, 4, 2) @[ifu_mem_ctl.scala 358:51] + node _T_1502 = and(bypass_data_ready_in, crit_wd_byp_ok_ff) @[ifu_mem_ctl.scala 339:53] + node _T_1503 = and(_T_1502, uncacheable_miss_ff) @[ifu_mem_ctl.scala 339:73] + node _T_1504 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 339:98] + node _T_1505 = and(_T_1503, _T_1504) @[ifu_mem_ctl.scala 339:96] + node _T_1506 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 339:120] + node _T_1507 = and(_T_1505, _T_1506) @[ifu_mem_ctl.scala 339:118] + node _T_1508 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 340:75] + node _T_1509 = and(crit_wd_byp_ok_ff, _T_1508) @[ifu_mem_ctl.scala 340:73] + node _T_1510 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 340:98] + node _T_1511 = and(_T_1509, _T_1510) @[ifu_mem_ctl.scala 340:96] + node _T_1512 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 340:120] + node _T_1513 = and(_T_1511, _T_1512) @[ifu_mem_ctl.scala 340:118] + node _T_1514 = or(_T_1507, _T_1513) @[ifu_mem_ctl.scala 339:143] + node _T_1515 = and(ic_crit_wd_rdy_new_ff, crit_wd_byp_ok_ff) @[ifu_mem_ctl.scala 341:54] + node _T_1516 = eq(fetch_req_icache_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 341:76] + node _T_1517 = and(_T_1515, _T_1516) @[ifu_mem_ctl.scala 341:74] + node _T_1518 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 341:98] + node _T_1519 = and(_T_1517, _T_1518) @[ifu_mem_ctl.scala 341:96] + node ic_crit_wd_rdy_new_in = or(_T_1514, _T_1519) @[ifu_mem_ctl.scala 340:143] + reg _T_1520 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 342:58] + _T_1520 <= ic_crit_wd_rdy_new_in @[ifu_mem_ctl.scala 342:58] + ic_crit_wd_rdy_new_ff <= _T_1520 @[ifu_mem_ctl.scala 342:25] + node byp_fetch_index = bits(ifu_fetch_addr_int_f, 4, 0) @[ifu_mem_ctl.scala 343:45] + node _T_1521 = bits(ifu_fetch_addr_int_f, 4, 2) @[ifu_mem_ctl.scala 344:51] node byp_fetch_index_0 = cat(_T_1521, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_1522 = bits(ifu_fetch_addr_int_f, 4, 2) @[ifu_mem_ctl.scala 359:51] + node _T_1522 = bits(ifu_fetch_addr_int_f, 4, 2) @[ifu_mem_ctl.scala 345:51] node byp_fetch_index_1 = cat(_T_1522, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_1523 = bits(ifu_fetch_addr_int_f, 4, 2) @[ifu_mem_ctl.scala 360:49] - node _T_1524 = add(_T_1523, UInt<1>("h01")) @[ifu_mem_ctl.scala 360:75] - node byp_fetch_index_inc = tail(_T_1524, 1) @[ifu_mem_ctl.scala 360:75] + node _T_1523 = bits(ifu_fetch_addr_int_f, 4, 2) @[ifu_mem_ctl.scala 346:49] + node _T_1524 = add(_T_1523, UInt<1>("h01")) @[ifu_mem_ctl.scala 346:75] + node byp_fetch_index_inc = tail(_T_1524, 1) @[ifu_mem_ctl.scala 346:75] node byp_fetch_index_inc_0 = cat(byp_fetch_index_inc, UInt<1>("h00")) @[Cat.scala 29:58] node byp_fetch_index_inc_1 = cat(byp_fetch_index_inc, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_1525 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 363:93] - node _T_1526 = eq(_T_1525, UInt<1>("h00")) @[ifu_mem_ctl.scala 363:118] - node _T_1527 = bits(_T_1526, 0, 0) @[ifu_mem_ctl.scala 363:126] - node _T_1528 = bits(ic_miss_buff_data_error, 0, 0) @[ifu_mem_ctl.scala 363:157] - node _T_1529 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 363:93] - node _T_1530 = eq(_T_1529, UInt<1>("h01")) @[ifu_mem_ctl.scala 363:118] - node _T_1531 = bits(_T_1530, 0, 0) @[ifu_mem_ctl.scala 363:126] - node _T_1532 = bits(ic_miss_buff_data_error, 1, 1) @[ifu_mem_ctl.scala 363:157] - node _T_1533 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 363:93] - node _T_1534 = eq(_T_1533, UInt<2>("h02")) @[ifu_mem_ctl.scala 363:118] - node _T_1535 = bits(_T_1534, 0, 0) @[ifu_mem_ctl.scala 363:126] - node _T_1536 = bits(ic_miss_buff_data_error, 2, 2) @[ifu_mem_ctl.scala 363:157] - node _T_1537 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 363:93] - node _T_1538 = eq(_T_1537, UInt<2>("h03")) @[ifu_mem_ctl.scala 363:118] - node _T_1539 = bits(_T_1538, 0, 0) @[ifu_mem_ctl.scala 363:126] - node _T_1540 = bits(ic_miss_buff_data_error, 3, 3) @[ifu_mem_ctl.scala 363:157] - node _T_1541 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 363:93] - node _T_1542 = eq(_T_1541, UInt<3>("h04")) @[ifu_mem_ctl.scala 363:118] - node _T_1543 = bits(_T_1542, 0, 0) @[ifu_mem_ctl.scala 363:126] - node _T_1544 = bits(ic_miss_buff_data_error, 4, 4) @[ifu_mem_ctl.scala 363:157] - node _T_1545 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 363:93] - node _T_1546 = eq(_T_1545, UInt<3>("h05")) @[ifu_mem_ctl.scala 363:118] - node _T_1547 = bits(_T_1546, 0, 0) @[ifu_mem_ctl.scala 363:126] - node _T_1548 = bits(ic_miss_buff_data_error, 5, 5) @[ifu_mem_ctl.scala 363:157] - node _T_1549 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 363:93] - node _T_1550 = eq(_T_1549, UInt<3>("h06")) @[ifu_mem_ctl.scala 363:118] - node _T_1551 = bits(_T_1550, 0, 0) @[ifu_mem_ctl.scala 363:126] - node _T_1552 = bits(ic_miss_buff_data_error, 6, 6) @[ifu_mem_ctl.scala 363:157] - node _T_1553 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 363:93] - node _T_1554 = eq(_T_1553, UInt<3>("h07")) @[ifu_mem_ctl.scala 363:118] - node _T_1555 = bits(_T_1554, 0, 0) @[ifu_mem_ctl.scala 363:126] - node _T_1556 = bits(ic_miss_buff_data_error, 7, 7) @[ifu_mem_ctl.scala 363:157] + node _T_1525 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 349:93] + node _T_1526 = eq(_T_1525, UInt<1>("h00")) @[ifu_mem_ctl.scala 349:118] + node _T_1527 = bits(_T_1526, 0, 0) @[ifu_mem_ctl.scala 349:126] + node _T_1528 = bits(ic_miss_buff_data_error, 0, 0) @[ifu_mem_ctl.scala 349:157] + node _T_1529 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 349:93] + node _T_1530 = eq(_T_1529, UInt<1>("h01")) @[ifu_mem_ctl.scala 349:118] + node _T_1531 = bits(_T_1530, 0, 0) @[ifu_mem_ctl.scala 349:126] + node _T_1532 = bits(ic_miss_buff_data_error, 1, 1) @[ifu_mem_ctl.scala 349:157] + node _T_1533 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 349:93] + node _T_1534 = eq(_T_1533, UInt<2>("h02")) @[ifu_mem_ctl.scala 349:118] + node _T_1535 = bits(_T_1534, 0, 0) @[ifu_mem_ctl.scala 349:126] + node _T_1536 = bits(ic_miss_buff_data_error, 2, 2) @[ifu_mem_ctl.scala 349:157] + node _T_1537 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 349:93] + node _T_1538 = eq(_T_1537, UInt<2>("h03")) @[ifu_mem_ctl.scala 349:118] + node _T_1539 = bits(_T_1538, 0, 0) @[ifu_mem_ctl.scala 349:126] + node _T_1540 = bits(ic_miss_buff_data_error, 3, 3) @[ifu_mem_ctl.scala 349:157] + node _T_1541 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 349:93] + node _T_1542 = eq(_T_1541, UInt<3>("h04")) @[ifu_mem_ctl.scala 349:118] + node _T_1543 = bits(_T_1542, 0, 0) @[ifu_mem_ctl.scala 349:126] + node _T_1544 = bits(ic_miss_buff_data_error, 4, 4) @[ifu_mem_ctl.scala 349:157] + node _T_1545 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 349:93] + node _T_1546 = eq(_T_1545, UInt<3>("h05")) @[ifu_mem_ctl.scala 349:118] + node _T_1547 = bits(_T_1546, 0, 0) @[ifu_mem_ctl.scala 349:126] + node _T_1548 = bits(ic_miss_buff_data_error, 5, 5) @[ifu_mem_ctl.scala 349:157] + node _T_1549 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 349:93] + node _T_1550 = eq(_T_1549, UInt<3>("h06")) @[ifu_mem_ctl.scala 349:118] + node _T_1551 = bits(_T_1550, 0, 0) @[ifu_mem_ctl.scala 349:126] + node _T_1552 = bits(ic_miss_buff_data_error, 6, 6) @[ifu_mem_ctl.scala 349:157] + node _T_1553 = bits(bypass_index, 4, 2) @[ifu_mem_ctl.scala 349:93] + node _T_1554 = eq(_T_1553, UInt<3>("h07")) @[ifu_mem_ctl.scala 349:118] + node _T_1555 = bits(_T_1554, 0, 0) @[ifu_mem_ctl.scala 349:126] + node _T_1556 = bits(ic_miss_buff_data_error, 7, 7) @[ifu_mem_ctl.scala 349:157] node _T_1557 = mux(_T_1527, _T_1528, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1558 = mux(_T_1531, _T_1532, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1559 = mux(_T_1535, _T_1536, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5132,30 +5112,30 @@ circuit quasar_wrapper : node _T_1571 = or(_T_1570, _T_1564) @[Mux.scala 27:72] wire ic_miss_buff_data_error_bypass : UInt<1> @[Mux.scala 27:72] ic_miss_buff_data_error_bypass <= _T_1571 @[Mux.scala 27:72] - node _T_1572 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[ifu_mem_ctl.scala 364:104] - node _T_1573 = bits(_T_1572, 0, 0) @[ifu_mem_ctl.scala 364:112] - node _T_1574 = bits(ic_miss_buff_data_error, 0, 0) @[ifu_mem_ctl.scala 364:143] - node _T_1575 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[ifu_mem_ctl.scala 364:104] - node _T_1576 = bits(_T_1575, 0, 0) @[ifu_mem_ctl.scala 364:112] - node _T_1577 = bits(ic_miss_buff_data_error, 1, 1) @[ifu_mem_ctl.scala 364:143] - node _T_1578 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[ifu_mem_ctl.scala 364:104] - node _T_1579 = bits(_T_1578, 0, 0) @[ifu_mem_ctl.scala 364:112] - node _T_1580 = bits(ic_miss_buff_data_error, 2, 2) @[ifu_mem_ctl.scala 364:143] - node _T_1581 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[ifu_mem_ctl.scala 364:104] - node _T_1582 = bits(_T_1581, 0, 0) @[ifu_mem_ctl.scala 364:112] - node _T_1583 = bits(ic_miss_buff_data_error, 3, 3) @[ifu_mem_ctl.scala 364:143] - node _T_1584 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[ifu_mem_ctl.scala 364:104] - node _T_1585 = bits(_T_1584, 0, 0) @[ifu_mem_ctl.scala 364:112] - node _T_1586 = bits(ic_miss_buff_data_error, 4, 4) @[ifu_mem_ctl.scala 364:143] - node _T_1587 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[ifu_mem_ctl.scala 364:104] - node _T_1588 = bits(_T_1587, 0, 0) @[ifu_mem_ctl.scala 364:112] - node _T_1589 = bits(ic_miss_buff_data_error, 5, 5) @[ifu_mem_ctl.scala 364:143] - node _T_1590 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[ifu_mem_ctl.scala 364:104] - node _T_1591 = bits(_T_1590, 0, 0) @[ifu_mem_ctl.scala 364:112] - node _T_1592 = bits(ic_miss_buff_data_error, 6, 6) @[ifu_mem_ctl.scala 364:143] - node _T_1593 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[ifu_mem_ctl.scala 364:104] - node _T_1594 = bits(_T_1593, 0, 0) @[ifu_mem_ctl.scala 364:112] - node _T_1595 = bits(ic_miss_buff_data_error, 7, 7) @[ifu_mem_ctl.scala 364:143] + node _T_1572 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[ifu_mem_ctl.scala 350:104] + node _T_1573 = bits(_T_1572, 0, 0) @[ifu_mem_ctl.scala 350:112] + node _T_1574 = bits(ic_miss_buff_data_error, 0, 0) @[ifu_mem_ctl.scala 350:143] + node _T_1575 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[ifu_mem_ctl.scala 350:104] + node _T_1576 = bits(_T_1575, 0, 0) @[ifu_mem_ctl.scala 350:112] + node _T_1577 = bits(ic_miss_buff_data_error, 1, 1) @[ifu_mem_ctl.scala 350:143] + node _T_1578 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[ifu_mem_ctl.scala 350:104] + node _T_1579 = bits(_T_1578, 0, 0) @[ifu_mem_ctl.scala 350:112] + node _T_1580 = bits(ic_miss_buff_data_error, 2, 2) @[ifu_mem_ctl.scala 350:143] + node _T_1581 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[ifu_mem_ctl.scala 350:104] + node _T_1582 = bits(_T_1581, 0, 0) @[ifu_mem_ctl.scala 350:112] + node _T_1583 = bits(ic_miss_buff_data_error, 3, 3) @[ifu_mem_ctl.scala 350:143] + node _T_1584 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[ifu_mem_ctl.scala 350:104] + node _T_1585 = bits(_T_1584, 0, 0) @[ifu_mem_ctl.scala 350:112] + node _T_1586 = bits(ic_miss_buff_data_error, 4, 4) @[ifu_mem_ctl.scala 350:143] + node _T_1587 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[ifu_mem_ctl.scala 350:104] + node _T_1588 = bits(_T_1587, 0, 0) @[ifu_mem_ctl.scala 350:112] + node _T_1589 = bits(ic_miss_buff_data_error, 5, 5) @[ifu_mem_ctl.scala 350:143] + node _T_1590 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[ifu_mem_ctl.scala 350:104] + node _T_1591 = bits(_T_1590, 0, 0) @[ifu_mem_ctl.scala 350:112] + node _T_1592 = bits(ic_miss_buff_data_error, 6, 6) @[ifu_mem_ctl.scala 350:143] + node _T_1593 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[ifu_mem_ctl.scala 350:104] + node _T_1594 = bits(_T_1593, 0, 0) @[ifu_mem_ctl.scala 350:112] + node _T_1595 = bits(ic_miss_buff_data_error, 7, 7) @[ifu_mem_ctl.scala 350:143] node _T_1596 = mux(_T_1573, _T_1574, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1597 = mux(_T_1576, _T_1577, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1598 = mux(_T_1579, _T_1580, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5173,106 +5153,106 @@ circuit quasar_wrapper : node _T_1610 = or(_T_1609, _T_1603) @[Mux.scala 27:72] wire ic_miss_buff_data_error_bypass_inc : UInt<1> @[Mux.scala 27:72] ic_miss_buff_data_error_bypass_inc <= _T_1610 @[Mux.scala 27:72] - node _T_1611 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 365:51] - node _T_1612 = eq(_T_1611, UInt<1>("h00")) @[ifu_mem_ctl.scala 365:30] - node _T_1613 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 365:78] - node _T_1614 = eq(_T_1613, UInt<1>("h00")) @[ifu_mem_ctl.scala 365:57] - node _T_1615 = and(_T_1612, _T_1614) @[ifu_mem_ctl.scala 365:55] - node _T_1616 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 365:123] - node _T_1617 = dshr(ic_miss_buff_data_error, _T_1616) @[ifu_mem_ctl.scala 365:107] - node _T_1618 = bits(_T_1617, 0, 0) @[ifu_mem_ctl.scala 365:107] - node _T_1619 = and(_T_1615, _T_1618) @[ifu_mem_ctl.scala 365:82] - node _T_1620 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 366:29] - node _T_1621 = eq(_T_1620, UInt<1>("h00")) @[ifu_mem_ctl.scala 366:8] - node _T_1622 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 366:56] - node _T_1623 = and(_T_1621, _T_1622) @[ifu_mem_ctl.scala 366:33] - node _T_1624 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 366:101] - node _T_1625 = dshr(ic_miss_buff_data_error, _T_1624) @[ifu_mem_ctl.scala 366:85] - node _T_1626 = bits(_T_1625, 0, 0) @[ifu_mem_ctl.scala 366:85] - node _T_1627 = and(_T_1623, _T_1626) @[ifu_mem_ctl.scala 366:60] - node _T_1628 = or(_T_1619, _T_1627) @[ifu_mem_ctl.scala 365:151] - node _T_1629 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 367:29] - node _T_1630 = eq(_T_1629, UInt<1>("h00")) @[ifu_mem_ctl.scala 367:8] - node _T_1631 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 367:56] - node _T_1632 = and(_T_1630, _T_1631) @[ifu_mem_ctl.scala 367:33] - node _T_1633 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 367:101] - node _T_1634 = dshr(ic_miss_buff_data_error, _T_1633) @[ifu_mem_ctl.scala 367:85] - node _T_1635 = bits(_T_1634, 0, 0) @[ifu_mem_ctl.scala 367:85] - node _T_1636 = and(_T_1632, _T_1635) @[ifu_mem_ctl.scala 367:60] - node _T_1637 = or(_T_1628, _T_1636) @[ifu_mem_ctl.scala 366:129] - node _T_1638 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 368:29] - node _T_1639 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 368:56] - node _T_1640 = eq(_T_1639, UInt<1>("h00")) @[ifu_mem_ctl.scala 368:35] - node _T_1641 = and(_T_1638, _T_1640) @[ifu_mem_ctl.scala 368:33] - node _T_1642 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 368:101] - node _T_1643 = dshr(ic_miss_buff_data_error, _T_1642) @[ifu_mem_ctl.scala 368:85] - node _T_1644 = bits(_T_1643, 0, 0) @[ifu_mem_ctl.scala 368:85] - node _T_1645 = and(_T_1641, _T_1644) @[ifu_mem_ctl.scala 368:60] - node _T_1646 = or(_T_1637, _T_1645) @[ifu_mem_ctl.scala 367:129] - node _T_1647 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 369:28] - node _T_1648 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 369:54] - node _T_1649 = and(_T_1647, _T_1648) @[ifu_mem_ctl.scala 369:32] - node _T_1650 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 369:100] - node _T_1651 = dshr(ic_miss_buff_data_error, _T_1650) @[ifu_mem_ctl.scala 369:84] - node _T_1652 = bits(_T_1651, 0, 0) @[ifu_mem_ctl.scala 369:84] - node _T_1653 = bits(byp_fetch_index_inc, 2, 0) @[ifu_mem_ctl.scala 370:52] - node _T_1654 = dshr(ic_miss_buff_data_error, _T_1653) @[ifu_mem_ctl.scala 370:32] - node _T_1655 = bits(_T_1654, 0, 0) @[ifu_mem_ctl.scala 370:32] - node _T_1656 = or(_T_1652, _T_1655) @[ifu_mem_ctl.scala 369:127] - node _T_1657 = and(_T_1649, _T_1656) @[ifu_mem_ctl.scala 369:58] - node _T_1658 = or(_T_1646, _T_1657) @[ifu_mem_ctl.scala 368:129] - ifu_byp_data_err_new <= _T_1658 @[ifu_mem_ctl.scala 365:26] - node _T_1659 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 371:59] - node _T_1660 = bits(_T_1659, 0, 0) @[ifu_mem_ctl.scala 371:63] - node _T_1661 = eq(_T_1660, UInt<1>("h00")) @[ifu_mem_ctl.scala 371:38] - node _T_1662 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[ifu_mem_ctl.scala 372:73] - node _T_1663 = bits(_T_1662, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1664 = bits(ic_miss_buff_data[0], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1665 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[ifu_mem_ctl.scala 372:73] - node _T_1666 = bits(_T_1665, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1667 = bits(ic_miss_buff_data[1], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1668 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[ifu_mem_ctl.scala 372:73] - node _T_1669 = bits(_T_1668, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1670 = bits(ic_miss_buff_data[2], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1671 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[ifu_mem_ctl.scala 372:73] - node _T_1672 = bits(_T_1671, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1673 = bits(ic_miss_buff_data[3], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1674 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[ifu_mem_ctl.scala 372:73] - node _T_1675 = bits(_T_1674, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1676 = bits(ic_miss_buff_data[4], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1677 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[ifu_mem_ctl.scala 372:73] - node _T_1678 = bits(_T_1677, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1679 = bits(ic_miss_buff_data[5], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1680 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[ifu_mem_ctl.scala 372:73] - node _T_1681 = bits(_T_1680, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1682 = bits(ic_miss_buff_data[6], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1683 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[ifu_mem_ctl.scala 372:73] - node _T_1684 = bits(_T_1683, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1685 = bits(ic_miss_buff_data[7], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1686 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[ifu_mem_ctl.scala 372:73] - node _T_1687 = bits(_T_1686, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1688 = bits(ic_miss_buff_data[8], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1689 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[ifu_mem_ctl.scala 372:73] - node _T_1690 = bits(_T_1689, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1691 = bits(ic_miss_buff_data[9], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1692 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[ifu_mem_ctl.scala 372:73] - node _T_1693 = bits(_T_1692, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1694 = bits(ic_miss_buff_data[10], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1695 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[ifu_mem_ctl.scala 372:73] - node _T_1696 = bits(_T_1695, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1697 = bits(ic_miss_buff_data[11], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1698 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[ifu_mem_ctl.scala 372:73] - node _T_1699 = bits(_T_1698, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1700 = bits(ic_miss_buff_data[12], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1701 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[ifu_mem_ctl.scala 372:73] - node _T_1702 = bits(_T_1701, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1703 = bits(ic_miss_buff_data[13], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1704 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[ifu_mem_ctl.scala 372:73] - node _T_1705 = bits(_T_1704, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1706 = bits(ic_miss_buff_data[14], 15, 0) @[ifu_mem_ctl.scala 372:109] - node _T_1707 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[ifu_mem_ctl.scala 372:73] - node _T_1708 = bits(_T_1707, 0, 0) @[ifu_mem_ctl.scala 372:81] - node _T_1709 = bits(ic_miss_buff_data[15], 15, 0) @[ifu_mem_ctl.scala 372:109] + node _T_1611 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 351:51] + node _T_1612 = eq(_T_1611, UInt<1>("h00")) @[ifu_mem_ctl.scala 351:30] + node _T_1613 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 351:78] + node _T_1614 = eq(_T_1613, UInt<1>("h00")) @[ifu_mem_ctl.scala 351:57] + node _T_1615 = and(_T_1612, _T_1614) @[ifu_mem_ctl.scala 351:55] + node _T_1616 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 351:123] + node _T_1617 = dshr(ic_miss_buff_data_error, _T_1616) @[ifu_mem_ctl.scala 351:107] + node _T_1618 = bits(_T_1617, 0, 0) @[ifu_mem_ctl.scala 351:107] + node _T_1619 = and(_T_1615, _T_1618) @[ifu_mem_ctl.scala 351:82] + node _T_1620 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 352:29] + node _T_1621 = eq(_T_1620, UInt<1>("h00")) @[ifu_mem_ctl.scala 352:8] + node _T_1622 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 352:56] + node _T_1623 = and(_T_1621, _T_1622) @[ifu_mem_ctl.scala 352:33] + node _T_1624 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 352:101] + node _T_1625 = dshr(ic_miss_buff_data_error, _T_1624) @[ifu_mem_ctl.scala 352:85] + node _T_1626 = bits(_T_1625, 0, 0) @[ifu_mem_ctl.scala 352:85] + node _T_1627 = and(_T_1623, _T_1626) @[ifu_mem_ctl.scala 352:60] + node _T_1628 = or(_T_1619, _T_1627) @[ifu_mem_ctl.scala 351:151] + node _T_1629 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 353:29] + node _T_1630 = eq(_T_1629, UInt<1>("h00")) @[ifu_mem_ctl.scala 353:8] + node _T_1631 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 353:56] + node _T_1632 = and(_T_1630, _T_1631) @[ifu_mem_ctl.scala 353:33] + node _T_1633 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 353:101] + node _T_1634 = dshr(ic_miss_buff_data_error, _T_1633) @[ifu_mem_ctl.scala 353:85] + node _T_1635 = bits(_T_1634, 0, 0) @[ifu_mem_ctl.scala 353:85] + node _T_1636 = and(_T_1632, _T_1635) @[ifu_mem_ctl.scala 353:60] + node _T_1637 = or(_T_1628, _T_1636) @[ifu_mem_ctl.scala 352:129] + node _T_1638 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 354:29] + node _T_1639 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 354:56] + node _T_1640 = eq(_T_1639, UInt<1>("h00")) @[ifu_mem_ctl.scala 354:35] + node _T_1641 = and(_T_1638, _T_1640) @[ifu_mem_ctl.scala 354:33] + node _T_1642 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 354:101] + node _T_1643 = dshr(ic_miss_buff_data_error, _T_1642) @[ifu_mem_ctl.scala 354:85] + node _T_1644 = bits(_T_1643, 0, 0) @[ifu_mem_ctl.scala 354:85] + node _T_1645 = and(_T_1641, _T_1644) @[ifu_mem_ctl.scala 354:60] + node _T_1646 = or(_T_1637, _T_1645) @[ifu_mem_ctl.scala 353:129] + node _T_1647 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 355:28] + node _T_1648 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 355:54] + node _T_1649 = and(_T_1647, _T_1648) @[ifu_mem_ctl.scala 355:32] + node _T_1650 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 355:100] + node _T_1651 = dshr(ic_miss_buff_data_error, _T_1650) @[ifu_mem_ctl.scala 355:84] + node _T_1652 = bits(_T_1651, 0, 0) @[ifu_mem_ctl.scala 355:84] + node _T_1653 = bits(byp_fetch_index_inc, 2, 0) @[ifu_mem_ctl.scala 356:52] + node _T_1654 = dshr(ic_miss_buff_data_error, _T_1653) @[ifu_mem_ctl.scala 356:32] + node _T_1655 = bits(_T_1654, 0, 0) @[ifu_mem_ctl.scala 356:32] + node _T_1656 = or(_T_1652, _T_1655) @[ifu_mem_ctl.scala 355:127] + node _T_1657 = and(_T_1649, _T_1656) @[ifu_mem_ctl.scala 355:58] + node _T_1658 = or(_T_1646, _T_1657) @[ifu_mem_ctl.scala 354:129] + ifu_byp_data_err_new <= _T_1658 @[ifu_mem_ctl.scala 351:26] + node _T_1659 = bits(ifu_fetch_addr_int_f, 1, 1) @[ifu_mem_ctl.scala 357:59] + node _T_1660 = bits(_T_1659, 0, 0) @[ifu_mem_ctl.scala 357:63] + node _T_1661 = eq(_T_1660, UInt<1>("h00")) @[ifu_mem_ctl.scala 357:38] + node _T_1662 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[ifu_mem_ctl.scala 358:73] + node _T_1663 = bits(_T_1662, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1664 = bits(ic_miss_buff_data[0], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1665 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[ifu_mem_ctl.scala 358:73] + node _T_1666 = bits(_T_1665, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1667 = bits(ic_miss_buff_data[1], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1668 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[ifu_mem_ctl.scala 358:73] + node _T_1669 = bits(_T_1668, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1670 = bits(ic_miss_buff_data[2], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1671 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[ifu_mem_ctl.scala 358:73] + node _T_1672 = bits(_T_1671, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1673 = bits(ic_miss_buff_data[3], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1674 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[ifu_mem_ctl.scala 358:73] + node _T_1675 = bits(_T_1674, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1676 = bits(ic_miss_buff_data[4], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1677 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[ifu_mem_ctl.scala 358:73] + node _T_1678 = bits(_T_1677, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1679 = bits(ic_miss_buff_data[5], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1680 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[ifu_mem_ctl.scala 358:73] + node _T_1681 = bits(_T_1680, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1682 = bits(ic_miss_buff_data[6], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1683 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[ifu_mem_ctl.scala 358:73] + node _T_1684 = bits(_T_1683, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1685 = bits(ic_miss_buff_data[7], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1686 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[ifu_mem_ctl.scala 358:73] + node _T_1687 = bits(_T_1686, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1688 = bits(ic_miss_buff_data[8], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1689 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[ifu_mem_ctl.scala 358:73] + node _T_1690 = bits(_T_1689, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1691 = bits(ic_miss_buff_data[9], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1692 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[ifu_mem_ctl.scala 358:73] + node _T_1693 = bits(_T_1692, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1694 = bits(ic_miss_buff_data[10], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1695 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[ifu_mem_ctl.scala 358:73] + node _T_1696 = bits(_T_1695, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1697 = bits(ic_miss_buff_data[11], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1698 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[ifu_mem_ctl.scala 358:73] + node _T_1699 = bits(_T_1698, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1700 = bits(ic_miss_buff_data[12], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1701 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[ifu_mem_ctl.scala 358:73] + node _T_1702 = bits(_T_1701, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1703 = bits(ic_miss_buff_data[13], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1704 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[ifu_mem_ctl.scala 358:73] + node _T_1705 = bits(_T_1704, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1706 = bits(ic_miss_buff_data[14], 15, 0) @[ifu_mem_ctl.scala 358:109] + node _T_1707 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[ifu_mem_ctl.scala 358:73] + node _T_1708 = bits(_T_1707, 0, 0) @[ifu_mem_ctl.scala 358:81] + node _T_1709 = bits(ic_miss_buff_data[15], 15, 0) @[ifu_mem_ctl.scala 358:109] node _T_1710 = mux(_T_1663, _T_1664, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1711 = mux(_T_1666, _T_1667, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1712 = mux(_T_1669, _T_1670, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5306,54 +5286,54 @@ circuit quasar_wrapper : node _T_1740 = or(_T_1739, _T_1725) @[Mux.scala 27:72] wire _T_1741 : UInt<16> @[Mux.scala 27:72] _T_1741 <= _T_1740 @[Mux.scala 27:72] - node _T_1742 = eq(byp_fetch_index_1, UInt<1>("h00")) @[ifu_mem_ctl.scala 372:179] - node _T_1743 = bits(_T_1742, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1744 = bits(ic_miss_buff_data[0], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1745 = eq(byp_fetch_index_1, UInt<1>("h01")) @[ifu_mem_ctl.scala 372:179] - node _T_1746 = bits(_T_1745, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1747 = bits(ic_miss_buff_data[1], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1748 = eq(byp_fetch_index_1, UInt<2>("h02")) @[ifu_mem_ctl.scala 372:179] - node _T_1749 = bits(_T_1748, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1750 = bits(ic_miss_buff_data[2], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1751 = eq(byp_fetch_index_1, UInt<2>("h03")) @[ifu_mem_ctl.scala 372:179] - node _T_1752 = bits(_T_1751, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1753 = bits(ic_miss_buff_data[3], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1754 = eq(byp_fetch_index_1, UInt<3>("h04")) @[ifu_mem_ctl.scala 372:179] - node _T_1755 = bits(_T_1754, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1756 = bits(ic_miss_buff_data[4], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1757 = eq(byp_fetch_index_1, UInt<3>("h05")) @[ifu_mem_ctl.scala 372:179] - node _T_1758 = bits(_T_1757, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1759 = bits(ic_miss_buff_data[5], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1760 = eq(byp_fetch_index_1, UInt<3>("h06")) @[ifu_mem_ctl.scala 372:179] - node _T_1761 = bits(_T_1760, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1762 = bits(ic_miss_buff_data[6], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1763 = eq(byp_fetch_index_1, UInt<3>("h07")) @[ifu_mem_ctl.scala 372:179] - node _T_1764 = bits(_T_1763, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1765 = bits(ic_miss_buff_data[7], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1766 = eq(byp_fetch_index_1, UInt<4>("h08")) @[ifu_mem_ctl.scala 372:179] - node _T_1767 = bits(_T_1766, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1768 = bits(ic_miss_buff_data[8], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1769 = eq(byp_fetch_index_1, UInt<4>("h09")) @[ifu_mem_ctl.scala 372:179] - node _T_1770 = bits(_T_1769, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1771 = bits(ic_miss_buff_data[9], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1772 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[ifu_mem_ctl.scala 372:179] - node _T_1773 = bits(_T_1772, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1774 = bits(ic_miss_buff_data[10], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1775 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[ifu_mem_ctl.scala 372:179] - node _T_1776 = bits(_T_1775, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1777 = bits(ic_miss_buff_data[11], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1778 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[ifu_mem_ctl.scala 372:179] - node _T_1779 = bits(_T_1778, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1780 = bits(ic_miss_buff_data[12], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1781 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[ifu_mem_ctl.scala 372:179] - node _T_1782 = bits(_T_1781, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1783 = bits(ic_miss_buff_data[13], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1784 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[ifu_mem_ctl.scala 372:179] - node _T_1785 = bits(_T_1784, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1786 = bits(ic_miss_buff_data[14], 31, 0) @[ifu_mem_ctl.scala 372:215] - node _T_1787 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[ifu_mem_ctl.scala 372:179] - node _T_1788 = bits(_T_1787, 0, 0) @[ifu_mem_ctl.scala 372:187] - node _T_1789 = bits(ic_miss_buff_data[15], 31, 0) @[ifu_mem_ctl.scala 372:215] + node _T_1742 = eq(byp_fetch_index_1, UInt<1>("h00")) @[ifu_mem_ctl.scala 358:179] + node _T_1743 = bits(_T_1742, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1744 = bits(ic_miss_buff_data[0], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1745 = eq(byp_fetch_index_1, UInt<1>("h01")) @[ifu_mem_ctl.scala 358:179] + node _T_1746 = bits(_T_1745, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1747 = bits(ic_miss_buff_data[1], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1748 = eq(byp_fetch_index_1, UInt<2>("h02")) @[ifu_mem_ctl.scala 358:179] + node _T_1749 = bits(_T_1748, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1750 = bits(ic_miss_buff_data[2], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1751 = eq(byp_fetch_index_1, UInt<2>("h03")) @[ifu_mem_ctl.scala 358:179] + node _T_1752 = bits(_T_1751, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1753 = bits(ic_miss_buff_data[3], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1754 = eq(byp_fetch_index_1, UInt<3>("h04")) @[ifu_mem_ctl.scala 358:179] + node _T_1755 = bits(_T_1754, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1756 = bits(ic_miss_buff_data[4], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1757 = eq(byp_fetch_index_1, UInt<3>("h05")) @[ifu_mem_ctl.scala 358:179] + node _T_1758 = bits(_T_1757, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1759 = bits(ic_miss_buff_data[5], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1760 = eq(byp_fetch_index_1, UInt<3>("h06")) @[ifu_mem_ctl.scala 358:179] + node _T_1761 = bits(_T_1760, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1762 = bits(ic_miss_buff_data[6], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1763 = eq(byp_fetch_index_1, UInt<3>("h07")) @[ifu_mem_ctl.scala 358:179] + node _T_1764 = bits(_T_1763, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1765 = bits(ic_miss_buff_data[7], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1766 = eq(byp_fetch_index_1, UInt<4>("h08")) @[ifu_mem_ctl.scala 358:179] + node _T_1767 = bits(_T_1766, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1768 = bits(ic_miss_buff_data[8], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1769 = eq(byp_fetch_index_1, UInt<4>("h09")) @[ifu_mem_ctl.scala 358:179] + node _T_1770 = bits(_T_1769, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1771 = bits(ic_miss_buff_data[9], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1772 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[ifu_mem_ctl.scala 358:179] + node _T_1773 = bits(_T_1772, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1774 = bits(ic_miss_buff_data[10], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1775 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[ifu_mem_ctl.scala 358:179] + node _T_1776 = bits(_T_1775, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1777 = bits(ic_miss_buff_data[11], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1778 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[ifu_mem_ctl.scala 358:179] + node _T_1779 = bits(_T_1778, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1780 = bits(ic_miss_buff_data[12], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1781 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[ifu_mem_ctl.scala 358:179] + node _T_1782 = bits(_T_1781, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1783 = bits(ic_miss_buff_data[13], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1784 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[ifu_mem_ctl.scala 358:179] + node _T_1785 = bits(_T_1784, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1786 = bits(ic_miss_buff_data[14], 31, 0) @[ifu_mem_ctl.scala 358:215] + node _T_1787 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[ifu_mem_ctl.scala 358:179] + node _T_1788 = bits(_T_1787, 0, 0) @[ifu_mem_ctl.scala 358:187] + node _T_1789 = bits(ic_miss_buff_data[15], 31, 0) @[ifu_mem_ctl.scala 358:215] node _T_1790 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1791 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1792 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5387,54 +5367,54 @@ circuit quasar_wrapper : node _T_1820 = or(_T_1819, _T_1805) @[Mux.scala 27:72] wire _T_1821 : UInt<32> @[Mux.scala 27:72] _T_1821 <= _T_1820 @[Mux.scala 27:72] - node _T_1822 = eq(byp_fetch_index_0, UInt<1>("h00")) @[ifu_mem_ctl.scala 372:285] - node _T_1823 = bits(_T_1822, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1824 = bits(ic_miss_buff_data[0], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1825 = eq(byp_fetch_index_0, UInt<1>("h01")) @[ifu_mem_ctl.scala 372:285] - node _T_1826 = bits(_T_1825, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1827 = bits(ic_miss_buff_data[1], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1828 = eq(byp_fetch_index_0, UInt<2>("h02")) @[ifu_mem_ctl.scala 372:285] - node _T_1829 = bits(_T_1828, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1830 = bits(ic_miss_buff_data[2], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1831 = eq(byp_fetch_index_0, UInt<2>("h03")) @[ifu_mem_ctl.scala 372:285] - node _T_1832 = bits(_T_1831, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1833 = bits(ic_miss_buff_data[3], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1834 = eq(byp_fetch_index_0, UInt<3>("h04")) @[ifu_mem_ctl.scala 372:285] - node _T_1835 = bits(_T_1834, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1836 = bits(ic_miss_buff_data[4], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1837 = eq(byp_fetch_index_0, UInt<3>("h05")) @[ifu_mem_ctl.scala 372:285] - node _T_1838 = bits(_T_1837, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1839 = bits(ic_miss_buff_data[5], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1840 = eq(byp_fetch_index_0, UInt<3>("h06")) @[ifu_mem_ctl.scala 372:285] - node _T_1841 = bits(_T_1840, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1842 = bits(ic_miss_buff_data[6], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1843 = eq(byp_fetch_index_0, UInt<3>("h07")) @[ifu_mem_ctl.scala 372:285] - node _T_1844 = bits(_T_1843, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1845 = bits(ic_miss_buff_data[7], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1846 = eq(byp_fetch_index_0, UInt<4>("h08")) @[ifu_mem_ctl.scala 372:285] - node _T_1847 = bits(_T_1846, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1848 = bits(ic_miss_buff_data[8], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1849 = eq(byp_fetch_index_0, UInt<4>("h09")) @[ifu_mem_ctl.scala 372:285] - node _T_1850 = bits(_T_1849, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1851 = bits(ic_miss_buff_data[9], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1852 = eq(byp_fetch_index_0, UInt<4>("h0a")) @[ifu_mem_ctl.scala 372:285] - node _T_1853 = bits(_T_1852, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1854 = bits(ic_miss_buff_data[10], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1855 = eq(byp_fetch_index_0, UInt<4>("h0b")) @[ifu_mem_ctl.scala 372:285] - node _T_1856 = bits(_T_1855, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1857 = bits(ic_miss_buff_data[11], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1858 = eq(byp_fetch_index_0, UInt<4>("h0c")) @[ifu_mem_ctl.scala 372:285] - node _T_1859 = bits(_T_1858, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1860 = bits(ic_miss_buff_data[12], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1861 = eq(byp_fetch_index_0, UInt<4>("h0d")) @[ifu_mem_ctl.scala 372:285] - node _T_1862 = bits(_T_1861, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1863 = bits(ic_miss_buff_data[13], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1864 = eq(byp_fetch_index_0, UInt<4>("h0e")) @[ifu_mem_ctl.scala 372:285] - node _T_1865 = bits(_T_1864, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1866 = bits(ic_miss_buff_data[14], 31, 0) @[ifu_mem_ctl.scala 372:321] - node _T_1867 = eq(byp_fetch_index_0, UInt<4>("h0f")) @[ifu_mem_ctl.scala 372:285] - node _T_1868 = bits(_T_1867, 0, 0) @[ifu_mem_ctl.scala 372:293] - node _T_1869 = bits(ic_miss_buff_data[15], 31, 0) @[ifu_mem_ctl.scala 372:321] + node _T_1822 = eq(byp_fetch_index_0, UInt<1>("h00")) @[ifu_mem_ctl.scala 358:285] + node _T_1823 = bits(_T_1822, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1824 = bits(ic_miss_buff_data[0], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1825 = eq(byp_fetch_index_0, UInt<1>("h01")) @[ifu_mem_ctl.scala 358:285] + node _T_1826 = bits(_T_1825, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1827 = bits(ic_miss_buff_data[1], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1828 = eq(byp_fetch_index_0, UInt<2>("h02")) @[ifu_mem_ctl.scala 358:285] + node _T_1829 = bits(_T_1828, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1830 = bits(ic_miss_buff_data[2], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1831 = eq(byp_fetch_index_0, UInt<2>("h03")) @[ifu_mem_ctl.scala 358:285] + node _T_1832 = bits(_T_1831, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1833 = bits(ic_miss_buff_data[3], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1834 = eq(byp_fetch_index_0, UInt<3>("h04")) @[ifu_mem_ctl.scala 358:285] + node _T_1835 = bits(_T_1834, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1836 = bits(ic_miss_buff_data[4], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1837 = eq(byp_fetch_index_0, UInt<3>("h05")) @[ifu_mem_ctl.scala 358:285] + node _T_1838 = bits(_T_1837, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1839 = bits(ic_miss_buff_data[5], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1840 = eq(byp_fetch_index_0, UInt<3>("h06")) @[ifu_mem_ctl.scala 358:285] + node _T_1841 = bits(_T_1840, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1842 = bits(ic_miss_buff_data[6], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1843 = eq(byp_fetch_index_0, UInt<3>("h07")) @[ifu_mem_ctl.scala 358:285] + node _T_1844 = bits(_T_1843, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1845 = bits(ic_miss_buff_data[7], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1846 = eq(byp_fetch_index_0, UInt<4>("h08")) @[ifu_mem_ctl.scala 358:285] + node _T_1847 = bits(_T_1846, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1848 = bits(ic_miss_buff_data[8], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1849 = eq(byp_fetch_index_0, UInt<4>("h09")) @[ifu_mem_ctl.scala 358:285] + node _T_1850 = bits(_T_1849, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1851 = bits(ic_miss_buff_data[9], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1852 = eq(byp_fetch_index_0, UInt<4>("h0a")) @[ifu_mem_ctl.scala 358:285] + node _T_1853 = bits(_T_1852, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1854 = bits(ic_miss_buff_data[10], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1855 = eq(byp_fetch_index_0, UInt<4>("h0b")) @[ifu_mem_ctl.scala 358:285] + node _T_1856 = bits(_T_1855, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1857 = bits(ic_miss_buff_data[11], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1858 = eq(byp_fetch_index_0, UInt<4>("h0c")) @[ifu_mem_ctl.scala 358:285] + node _T_1859 = bits(_T_1858, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1860 = bits(ic_miss_buff_data[12], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1861 = eq(byp_fetch_index_0, UInt<4>("h0d")) @[ifu_mem_ctl.scala 358:285] + node _T_1862 = bits(_T_1861, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1863 = bits(ic_miss_buff_data[13], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1864 = eq(byp_fetch_index_0, UInt<4>("h0e")) @[ifu_mem_ctl.scala 358:285] + node _T_1865 = bits(_T_1864, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1866 = bits(ic_miss_buff_data[14], 31, 0) @[ifu_mem_ctl.scala 358:321] + node _T_1867 = eq(byp_fetch_index_0, UInt<4>("h0f")) @[ifu_mem_ctl.scala 358:285] + node _T_1868 = bits(_T_1867, 0, 0) @[ifu_mem_ctl.scala 358:293] + node _T_1869 = bits(ic_miss_buff_data[15], 31, 0) @[ifu_mem_ctl.scala 358:321] node _T_1870 = mux(_T_1823, _T_1824, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1871 = mux(_T_1826, _T_1827, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1872 = mux(_T_1829, _T_1830, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5470,54 +5450,54 @@ circuit quasar_wrapper : _T_1901 <= _T_1900 @[Mux.scala 27:72] node _T_1902 = cat(_T_1741, _T_1821) @[Cat.scala 29:58] node _T_1903 = cat(_T_1902, _T_1901) @[Cat.scala 29:58] - node _T_1904 = eq(byp_fetch_index_inc_1, UInt<1>("h00")) @[ifu_mem_ctl.scala 373:73] - node _T_1905 = bits(_T_1904, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1906 = bits(ic_miss_buff_data[0], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1907 = eq(byp_fetch_index_inc_1, UInt<1>("h01")) @[ifu_mem_ctl.scala 373:73] - node _T_1908 = bits(_T_1907, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1909 = bits(ic_miss_buff_data[1], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1910 = eq(byp_fetch_index_inc_1, UInt<2>("h02")) @[ifu_mem_ctl.scala 373:73] - node _T_1911 = bits(_T_1910, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1912 = bits(ic_miss_buff_data[2], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1913 = eq(byp_fetch_index_inc_1, UInt<2>("h03")) @[ifu_mem_ctl.scala 373:73] - node _T_1914 = bits(_T_1913, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1915 = bits(ic_miss_buff_data[3], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1916 = eq(byp_fetch_index_inc_1, UInt<3>("h04")) @[ifu_mem_ctl.scala 373:73] - node _T_1917 = bits(_T_1916, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1918 = bits(ic_miss_buff_data[4], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1919 = eq(byp_fetch_index_inc_1, UInt<3>("h05")) @[ifu_mem_ctl.scala 373:73] - node _T_1920 = bits(_T_1919, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1921 = bits(ic_miss_buff_data[5], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1922 = eq(byp_fetch_index_inc_1, UInt<3>("h06")) @[ifu_mem_ctl.scala 373:73] - node _T_1923 = bits(_T_1922, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1924 = bits(ic_miss_buff_data[6], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1925 = eq(byp_fetch_index_inc_1, UInt<3>("h07")) @[ifu_mem_ctl.scala 373:73] - node _T_1926 = bits(_T_1925, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1927 = bits(ic_miss_buff_data[7], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1928 = eq(byp_fetch_index_inc_1, UInt<4>("h08")) @[ifu_mem_ctl.scala 373:73] - node _T_1929 = bits(_T_1928, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1930 = bits(ic_miss_buff_data[8], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1931 = eq(byp_fetch_index_inc_1, UInt<4>("h09")) @[ifu_mem_ctl.scala 373:73] - node _T_1932 = bits(_T_1931, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1933 = bits(ic_miss_buff_data[9], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1934 = eq(byp_fetch_index_inc_1, UInt<4>("h0a")) @[ifu_mem_ctl.scala 373:73] - node _T_1935 = bits(_T_1934, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1936 = bits(ic_miss_buff_data[10], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1937 = eq(byp_fetch_index_inc_1, UInt<4>("h0b")) @[ifu_mem_ctl.scala 373:73] - node _T_1938 = bits(_T_1937, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1939 = bits(ic_miss_buff_data[11], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1940 = eq(byp_fetch_index_inc_1, UInt<4>("h0c")) @[ifu_mem_ctl.scala 373:73] - node _T_1941 = bits(_T_1940, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1942 = bits(ic_miss_buff_data[12], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1943 = eq(byp_fetch_index_inc_1, UInt<4>("h0d")) @[ifu_mem_ctl.scala 373:73] - node _T_1944 = bits(_T_1943, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1945 = bits(ic_miss_buff_data[13], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1946 = eq(byp_fetch_index_inc_1, UInt<4>("h0e")) @[ifu_mem_ctl.scala 373:73] - node _T_1947 = bits(_T_1946, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1948 = bits(ic_miss_buff_data[14], 15, 0) @[ifu_mem_ctl.scala 373:109] - node _T_1949 = eq(byp_fetch_index_inc_1, UInt<4>("h0f")) @[ifu_mem_ctl.scala 373:73] - node _T_1950 = bits(_T_1949, 0, 0) @[ifu_mem_ctl.scala 373:81] - node _T_1951 = bits(ic_miss_buff_data[15], 15, 0) @[ifu_mem_ctl.scala 373:109] + node _T_1904 = eq(byp_fetch_index_inc_1, UInt<1>("h00")) @[ifu_mem_ctl.scala 359:73] + node _T_1905 = bits(_T_1904, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1906 = bits(ic_miss_buff_data[0], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1907 = eq(byp_fetch_index_inc_1, UInt<1>("h01")) @[ifu_mem_ctl.scala 359:73] + node _T_1908 = bits(_T_1907, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1909 = bits(ic_miss_buff_data[1], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1910 = eq(byp_fetch_index_inc_1, UInt<2>("h02")) @[ifu_mem_ctl.scala 359:73] + node _T_1911 = bits(_T_1910, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1912 = bits(ic_miss_buff_data[2], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1913 = eq(byp_fetch_index_inc_1, UInt<2>("h03")) @[ifu_mem_ctl.scala 359:73] + node _T_1914 = bits(_T_1913, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1915 = bits(ic_miss_buff_data[3], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1916 = eq(byp_fetch_index_inc_1, UInt<3>("h04")) @[ifu_mem_ctl.scala 359:73] + node _T_1917 = bits(_T_1916, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1918 = bits(ic_miss_buff_data[4], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1919 = eq(byp_fetch_index_inc_1, UInt<3>("h05")) @[ifu_mem_ctl.scala 359:73] + node _T_1920 = bits(_T_1919, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1921 = bits(ic_miss_buff_data[5], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1922 = eq(byp_fetch_index_inc_1, UInt<3>("h06")) @[ifu_mem_ctl.scala 359:73] + node _T_1923 = bits(_T_1922, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1924 = bits(ic_miss_buff_data[6], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1925 = eq(byp_fetch_index_inc_1, UInt<3>("h07")) @[ifu_mem_ctl.scala 359:73] + node _T_1926 = bits(_T_1925, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1927 = bits(ic_miss_buff_data[7], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1928 = eq(byp_fetch_index_inc_1, UInt<4>("h08")) @[ifu_mem_ctl.scala 359:73] + node _T_1929 = bits(_T_1928, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1930 = bits(ic_miss_buff_data[8], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1931 = eq(byp_fetch_index_inc_1, UInt<4>("h09")) @[ifu_mem_ctl.scala 359:73] + node _T_1932 = bits(_T_1931, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1933 = bits(ic_miss_buff_data[9], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1934 = eq(byp_fetch_index_inc_1, UInt<4>("h0a")) @[ifu_mem_ctl.scala 359:73] + node _T_1935 = bits(_T_1934, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1936 = bits(ic_miss_buff_data[10], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1937 = eq(byp_fetch_index_inc_1, UInt<4>("h0b")) @[ifu_mem_ctl.scala 359:73] + node _T_1938 = bits(_T_1937, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1939 = bits(ic_miss_buff_data[11], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1940 = eq(byp_fetch_index_inc_1, UInt<4>("h0c")) @[ifu_mem_ctl.scala 359:73] + node _T_1941 = bits(_T_1940, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1942 = bits(ic_miss_buff_data[12], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1943 = eq(byp_fetch_index_inc_1, UInt<4>("h0d")) @[ifu_mem_ctl.scala 359:73] + node _T_1944 = bits(_T_1943, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1945 = bits(ic_miss_buff_data[13], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1946 = eq(byp_fetch_index_inc_1, UInt<4>("h0e")) @[ifu_mem_ctl.scala 359:73] + node _T_1947 = bits(_T_1946, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1948 = bits(ic_miss_buff_data[14], 15, 0) @[ifu_mem_ctl.scala 359:109] + node _T_1949 = eq(byp_fetch_index_inc_1, UInt<4>("h0f")) @[ifu_mem_ctl.scala 359:73] + node _T_1950 = bits(_T_1949, 0, 0) @[ifu_mem_ctl.scala 359:81] + node _T_1951 = bits(ic_miss_buff_data[15], 15, 0) @[ifu_mem_ctl.scala 359:109] node _T_1952 = mux(_T_1905, _T_1906, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1953 = mux(_T_1908, _T_1909, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1954 = mux(_T_1911, _T_1912, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5551,54 +5531,54 @@ circuit quasar_wrapper : node _T_1982 = or(_T_1981, _T_1967) @[Mux.scala 27:72] wire _T_1983 : UInt<16> @[Mux.scala 27:72] _T_1983 <= _T_1982 @[Mux.scala 27:72] - node _T_1984 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[ifu_mem_ctl.scala 373:183] - node _T_1985 = bits(_T_1984, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_1986 = bits(ic_miss_buff_data[0], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_1987 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[ifu_mem_ctl.scala 373:183] - node _T_1988 = bits(_T_1987, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_1989 = bits(ic_miss_buff_data[1], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_1990 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[ifu_mem_ctl.scala 373:183] - node _T_1991 = bits(_T_1990, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_1992 = bits(ic_miss_buff_data[2], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_1993 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[ifu_mem_ctl.scala 373:183] - node _T_1994 = bits(_T_1993, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_1995 = bits(ic_miss_buff_data[3], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_1996 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[ifu_mem_ctl.scala 373:183] - node _T_1997 = bits(_T_1996, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_1998 = bits(ic_miss_buff_data[4], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_1999 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[ifu_mem_ctl.scala 373:183] - node _T_2000 = bits(_T_1999, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_2001 = bits(ic_miss_buff_data[5], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_2002 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[ifu_mem_ctl.scala 373:183] - node _T_2003 = bits(_T_2002, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_2004 = bits(ic_miss_buff_data[6], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_2005 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[ifu_mem_ctl.scala 373:183] - node _T_2006 = bits(_T_2005, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_2007 = bits(ic_miss_buff_data[7], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_2008 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[ifu_mem_ctl.scala 373:183] - node _T_2009 = bits(_T_2008, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_2010 = bits(ic_miss_buff_data[8], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_2011 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[ifu_mem_ctl.scala 373:183] - node _T_2012 = bits(_T_2011, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_2013 = bits(ic_miss_buff_data[9], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_2014 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[ifu_mem_ctl.scala 373:183] - node _T_2015 = bits(_T_2014, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_2016 = bits(ic_miss_buff_data[10], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_2017 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[ifu_mem_ctl.scala 373:183] - node _T_2018 = bits(_T_2017, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_2019 = bits(ic_miss_buff_data[11], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_2020 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[ifu_mem_ctl.scala 373:183] - node _T_2021 = bits(_T_2020, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_2022 = bits(ic_miss_buff_data[12], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_2023 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[ifu_mem_ctl.scala 373:183] - node _T_2024 = bits(_T_2023, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_2025 = bits(ic_miss_buff_data[13], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_2026 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[ifu_mem_ctl.scala 373:183] - node _T_2027 = bits(_T_2026, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_2028 = bits(ic_miss_buff_data[14], 31, 0) @[ifu_mem_ctl.scala 373:219] - node _T_2029 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[ifu_mem_ctl.scala 373:183] - node _T_2030 = bits(_T_2029, 0, 0) @[ifu_mem_ctl.scala 373:191] - node _T_2031 = bits(ic_miss_buff_data[15], 31, 0) @[ifu_mem_ctl.scala 373:219] + node _T_1984 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[ifu_mem_ctl.scala 359:183] + node _T_1985 = bits(_T_1984, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_1986 = bits(ic_miss_buff_data[0], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_1987 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[ifu_mem_ctl.scala 359:183] + node _T_1988 = bits(_T_1987, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_1989 = bits(ic_miss_buff_data[1], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_1990 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[ifu_mem_ctl.scala 359:183] + node _T_1991 = bits(_T_1990, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_1992 = bits(ic_miss_buff_data[2], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_1993 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[ifu_mem_ctl.scala 359:183] + node _T_1994 = bits(_T_1993, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_1995 = bits(ic_miss_buff_data[3], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_1996 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[ifu_mem_ctl.scala 359:183] + node _T_1997 = bits(_T_1996, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_1998 = bits(ic_miss_buff_data[4], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_1999 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[ifu_mem_ctl.scala 359:183] + node _T_2000 = bits(_T_1999, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_2001 = bits(ic_miss_buff_data[5], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_2002 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[ifu_mem_ctl.scala 359:183] + node _T_2003 = bits(_T_2002, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_2004 = bits(ic_miss_buff_data[6], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_2005 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[ifu_mem_ctl.scala 359:183] + node _T_2006 = bits(_T_2005, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_2007 = bits(ic_miss_buff_data[7], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_2008 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[ifu_mem_ctl.scala 359:183] + node _T_2009 = bits(_T_2008, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_2010 = bits(ic_miss_buff_data[8], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_2011 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[ifu_mem_ctl.scala 359:183] + node _T_2012 = bits(_T_2011, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_2013 = bits(ic_miss_buff_data[9], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_2014 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[ifu_mem_ctl.scala 359:183] + node _T_2015 = bits(_T_2014, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_2016 = bits(ic_miss_buff_data[10], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_2017 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[ifu_mem_ctl.scala 359:183] + node _T_2018 = bits(_T_2017, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_2019 = bits(ic_miss_buff_data[11], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_2020 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[ifu_mem_ctl.scala 359:183] + node _T_2021 = bits(_T_2020, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_2022 = bits(ic_miss_buff_data[12], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_2023 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[ifu_mem_ctl.scala 359:183] + node _T_2024 = bits(_T_2023, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_2025 = bits(ic_miss_buff_data[13], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_2026 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[ifu_mem_ctl.scala 359:183] + node _T_2027 = bits(_T_2026, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_2028 = bits(ic_miss_buff_data[14], 31, 0) @[ifu_mem_ctl.scala 359:219] + node _T_2029 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[ifu_mem_ctl.scala 359:183] + node _T_2030 = bits(_T_2029, 0, 0) @[ifu_mem_ctl.scala 359:191] + node _T_2031 = bits(ic_miss_buff_data[15], 31, 0) @[ifu_mem_ctl.scala 359:219] node _T_2032 = mux(_T_1985, _T_1986, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2033 = mux(_T_1988, _T_1989, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2034 = mux(_T_1991, _T_1992, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5632,54 +5612,54 @@ circuit quasar_wrapper : node _T_2062 = or(_T_2061, _T_2047) @[Mux.scala 27:72] wire _T_2063 : UInt<32> @[Mux.scala 27:72] _T_2063 <= _T_2062 @[Mux.scala 27:72] - node _T_2064 = eq(byp_fetch_index_1, UInt<1>("h00")) @[ifu_mem_ctl.scala 373:289] - node _T_2065 = bits(_T_2064, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2066 = bits(ic_miss_buff_data[0], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2067 = eq(byp_fetch_index_1, UInt<1>("h01")) @[ifu_mem_ctl.scala 373:289] - node _T_2068 = bits(_T_2067, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2069 = bits(ic_miss_buff_data[1], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2070 = eq(byp_fetch_index_1, UInt<2>("h02")) @[ifu_mem_ctl.scala 373:289] - node _T_2071 = bits(_T_2070, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2072 = bits(ic_miss_buff_data[2], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2073 = eq(byp_fetch_index_1, UInt<2>("h03")) @[ifu_mem_ctl.scala 373:289] - node _T_2074 = bits(_T_2073, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2075 = bits(ic_miss_buff_data[3], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2076 = eq(byp_fetch_index_1, UInt<3>("h04")) @[ifu_mem_ctl.scala 373:289] - node _T_2077 = bits(_T_2076, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2078 = bits(ic_miss_buff_data[4], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2079 = eq(byp_fetch_index_1, UInt<3>("h05")) @[ifu_mem_ctl.scala 373:289] - node _T_2080 = bits(_T_2079, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2081 = bits(ic_miss_buff_data[5], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2082 = eq(byp_fetch_index_1, UInt<3>("h06")) @[ifu_mem_ctl.scala 373:289] - node _T_2083 = bits(_T_2082, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2084 = bits(ic_miss_buff_data[6], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2085 = eq(byp_fetch_index_1, UInt<3>("h07")) @[ifu_mem_ctl.scala 373:289] - node _T_2086 = bits(_T_2085, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2087 = bits(ic_miss_buff_data[7], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2088 = eq(byp_fetch_index_1, UInt<4>("h08")) @[ifu_mem_ctl.scala 373:289] - node _T_2089 = bits(_T_2088, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2090 = bits(ic_miss_buff_data[8], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2091 = eq(byp_fetch_index_1, UInt<4>("h09")) @[ifu_mem_ctl.scala 373:289] - node _T_2092 = bits(_T_2091, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2093 = bits(ic_miss_buff_data[9], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2094 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[ifu_mem_ctl.scala 373:289] - node _T_2095 = bits(_T_2094, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2096 = bits(ic_miss_buff_data[10], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2097 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[ifu_mem_ctl.scala 373:289] - node _T_2098 = bits(_T_2097, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2099 = bits(ic_miss_buff_data[11], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2100 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[ifu_mem_ctl.scala 373:289] - node _T_2101 = bits(_T_2100, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2102 = bits(ic_miss_buff_data[12], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2103 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[ifu_mem_ctl.scala 373:289] - node _T_2104 = bits(_T_2103, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2105 = bits(ic_miss_buff_data[13], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2106 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[ifu_mem_ctl.scala 373:289] - node _T_2107 = bits(_T_2106, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2108 = bits(ic_miss_buff_data[14], 31, 0) @[ifu_mem_ctl.scala 373:325] - node _T_2109 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[ifu_mem_ctl.scala 373:289] - node _T_2110 = bits(_T_2109, 0, 0) @[ifu_mem_ctl.scala 373:297] - node _T_2111 = bits(ic_miss_buff_data[15], 31, 0) @[ifu_mem_ctl.scala 373:325] + node _T_2064 = eq(byp_fetch_index_1, UInt<1>("h00")) @[ifu_mem_ctl.scala 359:289] + node _T_2065 = bits(_T_2064, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2066 = bits(ic_miss_buff_data[0], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2067 = eq(byp_fetch_index_1, UInt<1>("h01")) @[ifu_mem_ctl.scala 359:289] + node _T_2068 = bits(_T_2067, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2069 = bits(ic_miss_buff_data[1], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2070 = eq(byp_fetch_index_1, UInt<2>("h02")) @[ifu_mem_ctl.scala 359:289] + node _T_2071 = bits(_T_2070, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2072 = bits(ic_miss_buff_data[2], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2073 = eq(byp_fetch_index_1, UInt<2>("h03")) @[ifu_mem_ctl.scala 359:289] + node _T_2074 = bits(_T_2073, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2075 = bits(ic_miss_buff_data[3], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2076 = eq(byp_fetch_index_1, UInt<3>("h04")) @[ifu_mem_ctl.scala 359:289] + node _T_2077 = bits(_T_2076, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2078 = bits(ic_miss_buff_data[4], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2079 = eq(byp_fetch_index_1, UInt<3>("h05")) @[ifu_mem_ctl.scala 359:289] + node _T_2080 = bits(_T_2079, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2081 = bits(ic_miss_buff_data[5], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2082 = eq(byp_fetch_index_1, UInt<3>("h06")) @[ifu_mem_ctl.scala 359:289] + node _T_2083 = bits(_T_2082, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2084 = bits(ic_miss_buff_data[6], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2085 = eq(byp_fetch_index_1, UInt<3>("h07")) @[ifu_mem_ctl.scala 359:289] + node _T_2086 = bits(_T_2085, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2087 = bits(ic_miss_buff_data[7], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2088 = eq(byp_fetch_index_1, UInt<4>("h08")) @[ifu_mem_ctl.scala 359:289] + node _T_2089 = bits(_T_2088, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2090 = bits(ic_miss_buff_data[8], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2091 = eq(byp_fetch_index_1, UInt<4>("h09")) @[ifu_mem_ctl.scala 359:289] + node _T_2092 = bits(_T_2091, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2093 = bits(ic_miss_buff_data[9], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2094 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[ifu_mem_ctl.scala 359:289] + node _T_2095 = bits(_T_2094, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2096 = bits(ic_miss_buff_data[10], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2097 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[ifu_mem_ctl.scala 359:289] + node _T_2098 = bits(_T_2097, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2099 = bits(ic_miss_buff_data[11], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2100 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[ifu_mem_ctl.scala 359:289] + node _T_2101 = bits(_T_2100, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2102 = bits(ic_miss_buff_data[12], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2103 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[ifu_mem_ctl.scala 359:289] + node _T_2104 = bits(_T_2103, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2105 = bits(ic_miss_buff_data[13], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2106 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[ifu_mem_ctl.scala 359:289] + node _T_2107 = bits(_T_2106, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2108 = bits(ic_miss_buff_data[14], 31, 0) @[ifu_mem_ctl.scala 359:325] + node _T_2109 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[ifu_mem_ctl.scala 359:289] + node _T_2110 = bits(_T_2109, 0, 0) @[ifu_mem_ctl.scala 359:297] + node _T_2111 = bits(ic_miss_buff_data[15], 31, 0) @[ifu_mem_ctl.scala 359:325] node _T_2112 = mux(_T_2065, _T_2066, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2113 = mux(_T_2068, _T_2069, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2114 = mux(_T_2071, _T_2072, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5715,49 +5695,49 @@ circuit quasar_wrapper : _T_2143 <= _T_2142 @[Mux.scala 27:72] node _T_2144 = cat(_T_1983, _T_2063) @[Cat.scala 29:58] node _T_2145 = cat(_T_2144, _T_2143) @[Cat.scala 29:58] - node ic_byp_data_only_pre_new = mux(_T_1661, _T_1903, _T_2145) @[ifu_mem_ctl.scala 371:37] - node _T_2146 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 375:52] - node _T_2147 = bits(_T_2146, 0, 0) @[ifu_mem_ctl.scala 375:62] - node _T_2148 = eq(_T_2147, UInt<1>("h00")) @[ifu_mem_ctl.scala 375:31] - node _T_2149 = bits(ic_byp_data_only_pre_new, 79, 16) @[ifu_mem_ctl.scala 375:128] + node ic_byp_data_only_pre_new = mux(_T_1661, _T_1903, _T_2145) @[ifu_mem_ctl.scala 357:37] + node _T_2146 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 361:52] + node _T_2147 = bits(_T_2146, 0, 0) @[ifu_mem_ctl.scala 361:62] + node _T_2148 = eq(_T_2147, UInt<1>("h00")) @[ifu_mem_ctl.scala 361:31] + node _T_2149 = bits(ic_byp_data_only_pre_new, 79, 16) @[ifu_mem_ctl.scala 361:128] node _T_2150 = cat(UInt<16>("h00"), _T_2149) @[Cat.scala 29:58] - node _T_2151 = mux(_T_2148, ic_byp_data_only_pre_new, _T_2150) @[ifu_mem_ctl.scala 375:30] - ic_byp_data_only_new <= _T_2151 @[ifu_mem_ctl.scala 375:24] - node _T_2152 = bits(imb_ff, 5, 5) @[ifu_mem_ctl.scala 377:27] - node _T_2153 = bits(ifu_fetch_addr_int_f, 5, 5) @[ifu_mem_ctl.scala 377:75] - node miss_wrap_f = neq(_T_2152, _T_2153) @[ifu_mem_ctl.scala 377:51] - node _T_2154 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 378:102] - node _T_2155 = eq(_T_2154, UInt<1>("h00")) @[ifu_mem_ctl.scala 378:127] - node _T_2156 = bits(_T_2155, 0, 0) @[ifu_mem_ctl.scala 378:135] - node _T_2157 = bits(ic_miss_buff_data_valid, 0, 0) @[ifu_mem_ctl.scala 378:166] - node _T_2158 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 378:102] - node _T_2159 = eq(_T_2158, UInt<1>("h01")) @[ifu_mem_ctl.scala 378:127] - node _T_2160 = bits(_T_2159, 0, 0) @[ifu_mem_ctl.scala 378:135] - node _T_2161 = bits(ic_miss_buff_data_valid, 1, 1) @[ifu_mem_ctl.scala 378:166] - node _T_2162 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 378:102] - node _T_2163 = eq(_T_2162, UInt<2>("h02")) @[ifu_mem_ctl.scala 378:127] - node _T_2164 = bits(_T_2163, 0, 0) @[ifu_mem_ctl.scala 378:135] - node _T_2165 = bits(ic_miss_buff_data_valid, 2, 2) @[ifu_mem_ctl.scala 378:166] - node _T_2166 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 378:102] - node _T_2167 = eq(_T_2166, UInt<2>("h03")) @[ifu_mem_ctl.scala 378:127] - node _T_2168 = bits(_T_2167, 0, 0) @[ifu_mem_ctl.scala 378:135] - node _T_2169 = bits(ic_miss_buff_data_valid, 3, 3) @[ifu_mem_ctl.scala 378:166] - node _T_2170 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 378:102] - node _T_2171 = eq(_T_2170, UInt<3>("h04")) @[ifu_mem_ctl.scala 378:127] - node _T_2172 = bits(_T_2171, 0, 0) @[ifu_mem_ctl.scala 378:135] - node _T_2173 = bits(ic_miss_buff_data_valid, 4, 4) @[ifu_mem_ctl.scala 378:166] - node _T_2174 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 378:102] - node _T_2175 = eq(_T_2174, UInt<3>("h05")) @[ifu_mem_ctl.scala 378:127] - node _T_2176 = bits(_T_2175, 0, 0) @[ifu_mem_ctl.scala 378:135] - node _T_2177 = bits(ic_miss_buff_data_valid, 5, 5) @[ifu_mem_ctl.scala 378:166] - node _T_2178 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 378:102] - node _T_2179 = eq(_T_2178, UInt<3>("h06")) @[ifu_mem_ctl.scala 378:127] - node _T_2180 = bits(_T_2179, 0, 0) @[ifu_mem_ctl.scala 378:135] - node _T_2181 = bits(ic_miss_buff_data_valid, 6, 6) @[ifu_mem_ctl.scala 378:166] - node _T_2182 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 378:102] - node _T_2183 = eq(_T_2182, UInt<3>("h07")) @[ifu_mem_ctl.scala 378:127] - node _T_2184 = bits(_T_2183, 0, 0) @[ifu_mem_ctl.scala 378:135] - node _T_2185 = bits(ic_miss_buff_data_valid, 7, 7) @[ifu_mem_ctl.scala 378:166] + node _T_2151 = mux(_T_2148, ic_byp_data_only_pre_new, _T_2150) @[ifu_mem_ctl.scala 361:30] + ic_byp_data_only_new <= _T_2151 @[ifu_mem_ctl.scala 361:24] + node _T_2152 = bits(imb_ff, 5, 5) @[ifu_mem_ctl.scala 363:27] + node _T_2153 = bits(ifu_fetch_addr_int_f, 5, 5) @[ifu_mem_ctl.scala 363:75] + node miss_wrap_f = neq(_T_2152, _T_2153) @[ifu_mem_ctl.scala 363:51] + node _T_2154 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 364:102] + node _T_2155 = eq(_T_2154, UInt<1>("h00")) @[ifu_mem_ctl.scala 364:127] + node _T_2156 = bits(_T_2155, 0, 0) @[ifu_mem_ctl.scala 364:135] + node _T_2157 = bits(ic_miss_buff_data_valid, 0, 0) @[ifu_mem_ctl.scala 364:166] + node _T_2158 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 364:102] + node _T_2159 = eq(_T_2158, UInt<1>("h01")) @[ifu_mem_ctl.scala 364:127] + node _T_2160 = bits(_T_2159, 0, 0) @[ifu_mem_ctl.scala 364:135] + node _T_2161 = bits(ic_miss_buff_data_valid, 1, 1) @[ifu_mem_ctl.scala 364:166] + node _T_2162 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 364:102] + node _T_2163 = eq(_T_2162, UInt<2>("h02")) @[ifu_mem_ctl.scala 364:127] + node _T_2164 = bits(_T_2163, 0, 0) @[ifu_mem_ctl.scala 364:135] + node _T_2165 = bits(ic_miss_buff_data_valid, 2, 2) @[ifu_mem_ctl.scala 364:166] + node _T_2166 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 364:102] + node _T_2167 = eq(_T_2166, UInt<2>("h03")) @[ifu_mem_ctl.scala 364:127] + node _T_2168 = bits(_T_2167, 0, 0) @[ifu_mem_ctl.scala 364:135] + node _T_2169 = bits(ic_miss_buff_data_valid, 3, 3) @[ifu_mem_ctl.scala 364:166] + node _T_2170 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 364:102] + node _T_2171 = eq(_T_2170, UInt<3>("h04")) @[ifu_mem_ctl.scala 364:127] + node _T_2172 = bits(_T_2171, 0, 0) @[ifu_mem_ctl.scala 364:135] + node _T_2173 = bits(ic_miss_buff_data_valid, 4, 4) @[ifu_mem_ctl.scala 364:166] + node _T_2174 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 364:102] + node _T_2175 = eq(_T_2174, UInt<3>("h05")) @[ifu_mem_ctl.scala 364:127] + node _T_2176 = bits(_T_2175, 0, 0) @[ifu_mem_ctl.scala 364:135] + node _T_2177 = bits(ic_miss_buff_data_valid, 5, 5) @[ifu_mem_ctl.scala 364:166] + node _T_2178 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 364:102] + node _T_2179 = eq(_T_2178, UInt<3>("h06")) @[ifu_mem_ctl.scala 364:127] + node _T_2180 = bits(_T_2179, 0, 0) @[ifu_mem_ctl.scala 364:135] + node _T_2181 = bits(ic_miss_buff_data_valid, 6, 6) @[ifu_mem_ctl.scala 364:166] + node _T_2182 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 364:102] + node _T_2183 = eq(_T_2182, UInt<3>("h07")) @[ifu_mem_ctl.scala 364:127] + node _T_2184 = bits(_T_2183, 0, 0) @[ifu_mem_ctl.scala 364:135] + node _T_2185 = bits(ic_miss_buff_data_valid, 7, 7) @[ifu_mem_ctl.scala 364:166] node _T_2186 = mux(_T_2156, _T_2157, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2187 = mux(_T_2160, _T_2161, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2188 = mux(_T_2164, _T_2165, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5775,30 +5755,30 @@ circuit quasar_wrapper : node _T_2200 = or(_T_2199, _T_2193) @[Mux.scala 27:72] wire ic_miss_buff_data_valid_bypass_index : UInt<1> @[Mux.scala 27:72] ic_miss_buff_data_valid_bypass_index <= _T_2200 @[Mux.scala 27:72] - node _T_2201 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[ifu_mem_ctl.scala 379:110] - node _T_2202 = bits(_T_2201, 0, 0) @[ifu_mem_ctl.scala 379:118] - node _T_2203 = bits(ic_miss_buff_data_valid, 0, 0) @[ifu_mem_ctl.scala 379:149] - node _T_2204 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[ifu_mem_ctl.scala 379:110] - node _T_2205 = bits(_T_2204, 0, 0) @[ifu_mem_ctl.scala 379:118] - node _T_2206 = bits(ic_miss_buff_data_valid, 1, 1) @[ifu_mem_ctl.scala 379:149] - node _T_2207 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[ifu_mem_ctl.scala 379:110] - node _T_2208 = bits(_T_2207, 0, 0) @[ifu_mem_ctl.scala 379:118] - node _T_2209 = bits(ic_miss_buff_data_valid, 2, 2) @[ifu_mem_ctl.scala 379:149] - node _T_2210 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[ifu_mem_ctl.scala 379:110] - node _T_2211 = bits(_T_2210, 0, 0) @[ifu_mem_ctl.scala 379:118] - node _T_2212 = bits(ic_miss_buff_data_valid, 3, 3) @[ifu_mem_ctl.scala 379:149] - node _T_2213 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[ifu_mem_ctl.scala 379:110] - node _T_2214 = bits(_T_2213, 0, 0) @[ifu_mem_ctl.scala 379:118] - node _T_2215 = bits(ic_miss_buff_data_valid, 4, 4) @[ifu_mem_ctl.scala 379:149] - node _T_2216 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[ifu_mem_ctl.scala 379:110] - node _T_2217 = bits(_T_2216, 0, 0) @[ifu_mem_ctl.scala 379:118] - node _T_2218 = bits(ic_miss_buff_data_valid, 5, 5) @[ifu_mem_ctl.scala 379:149] - node _T_2219 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[ifu_mem_ctl.scala 379:110] - node _T_2220 = bits(_T_2219, 0, 0) @[ifu_mem_ctl.scala 379:118] - node _T_2221 = bits(ic_miss_buff_data_valid, 6, 6) @[ifu_mem_ctl.scala 379:149] - node _T_2222 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[ifu_mem_ctl.scala 379:110] - node _T_2223 = bits(_T_2222, 0, 0) @[ifu_mem_ctl.scala 379:118] - node _T_2224 = bits(ic_miss_buff_data_valid, 7, 7) @[ifu_mem_ctl.scala 379:149] + node _T_2201 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[ifu_mem_ctl.scala 365:110] + node _T_2202 = bits(_T_2201, 0, 0) @[ifu_mem_ctl.scala 365:118] + node _T_2203 = bits(ic_miss_buff_data_valid, 0, 0) @[ifu_mem_ctl.scala 365:149] + node _T_2204 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[ifu_mem_ctl.scala 365:110] + node _T_2205 = bits(_T_2204, 0, 0) @[ifu_mem_ctl.scala 365:118] + node _T_2206 = bits(ic_miss_buff_data_valid, 1, 1) @[ifu_mem_ctl.scala 365:149] + node _T_2207 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[ifu_mem_ctl.scala 365:110] + node _T_2208 = bits(_T_2207, 0, 0) @[ifu_mem_ctl.scala 365:118] + node _T_2209 = bits(ic_miss_buff_data_valid, 2, 2) @[ifu_mem_ctl.scala 365:149] + node _T_2210 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[ifu_mem_ctl.scala 365:110] + node _T_2211 = bits(_T_2210, 0, 0) @[ifu_mem_ctl.scala 365:118] + node _T_2212 = bits(ic_miss_buff_data_valid, 3, 3) @[ifu_mem_ctl.scala 365:149] + node _T_2213 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[ifu_mem_ctl.scala 365:110] + node _T_2214 = bits(_T_2213, 0, 0) @[ifu_mem_ctl.scala 365:118] + node _T_2215 = bits(ic_miss_buff_data_valid, 4, 4) @[ifu_mem_ctl.scala 365:149] + node _T_2216 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[ifu_mem_ctl.scala 365:110] + node _T_2217 = bits(_T_2216, 0, 0) @[ifu_mem_ctl.scala 365:118] + node _T_2218 = bits(ic_miss_buff_data_valid, 5, 5) @[ifu_mem_ctl.scala 365:149] + node _T_2219 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[ifu_mem_ctl.scala 365:110] + node _T_2220 = bits(_T_2219, 0, 0) @[ifu_mem_ctl.scala 365:118] + node _T_2221 = bits(ic_miss_buff_data_valid, 6, 6) @[ifu_mem_ctl.scala 365:149] + node _T_2222 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[ifu_mem_ctl.scala 365:110] + node _T_2223 = bits(_T_2222, 0, 0) @[ifu_mem_ctl.scala 365:118] + node _T_2224 = bits(ic_miss_buff_data_valid, 7, 7) @[ifu_mem_ctl.scala 365:149] node _T_2225 = mux(_T_2202, _T_2203, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2226 = mux(_T_2205, _T_2206, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2227 = mux(_T_2208, _T_2209, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5816,86 +5796,86 @@ circuit quasar_wrapper : node _T_2239 = or(_T_2238, _T_2232) @[Mux.scala 27:72] wire ic_miss_buff_data_valid_inc_bypass_index : UInt<1> @[Mux.scala 27:72] ic_miss_buff_data_valid_inc_bypass_index <= _T_2239 @[Mux.scala 27:72] - node _T_2240 = bits(byp_fetch_index, 1, 1) @[ifu_mem_ctl.scala 380:85] - node _T_2241 = eq(_T_2240, UInt<1>("h00")) @[ifu_mem_ctl.scala 380:69] - node _T_2242 = and(ic_miss_buff_data_valid_bypass_index, _T_2241) @[ifu_mem_ctl.scala 380:67] - node _T_2243 = bits(byp_fetch_index, 0, 0) @[ifu_mem_ctl.scala 380:107] - node _T_2244 = eq(_T_2243, UInt<1>("h00")) @[ifu_mem_ctl.scala 380:91] - node _T_2245 = and(_T_2242, _T_2244) @[ifu_mem_ctl.scala 380:89] - node _T_2246 = bits(byp_fetch_index, 1, 1) @[ifu_mem_ctl.scala 381:61] - node _T_2247 = eq(_T_2246, UInt<1>("h00")) @[ifu_mem_ctl.scala 381:45] - node _T_2248 = and(ic_miss_buff_data_valid_bypass_index, _T_2247) @[ifu_mem_ctl.scala 381:43] - node _T_2249 = bits(byp_fetch_index, 0, 0) @[ifu_mem_ctl.scala 381:83] - node _T_2250 = and(_T_2248, _T_2249) @[ifu_mem_ctl.scala 381:65] - node _T_2251 = or(_T_2245, _T_2250) @[ifu_mem_ctl.scala 380:112] - node _T_2252 = bits(byp_fetch_index, 1, 1) @[ifu_mem_ctl.scala 382:61] - node _T_2253 = and(ic_miss_buff_data_valid_bypass_index, _T_2252) @[ifu_mem_ctl.scala 382:43] - node _T_2254 = bits(byp_fetch_index, 0, 0) @[ifu_mem_ctl.scala 382:83] - node _T_2255 = eq(_T_2254, UInt<1>("h00")) @[ifu_mem_ctl.scala 382:67] - node _T_2256 = and(_T_2253, _T_2255) @[ifu_mem_ctl.scala 382:65] - node _T_2257 = or(_T_2251, _T_2256) @[ifu_mem_ctl.scala 381:88] - node _T_2258 = bits(byp_fetch_index, 1, 1) @[ifu_mem_ctl.scala 383:61] - node _T_2259 = and(ic_miss_buff_data_valid_bypass_index, _T_2258) @[ifu_mem_ctl.scala 383:43] - node _T_2260 = bits(byp_fetch_index, 0, 0) @[ifu_mem_ctl.scala 383:83] - node _T_2261 = and(_T_2259, _T_2260) @[ifu_mem_ctl.scala 383:65] - node _T_2262 = and(_T_2261, ic_miss_buff_data_valid_inc_bypass_index) @[ifu_mem_ctl.scala 383:87] - node _T_2263 = or(_T_2257, _T_2262) @[ifu_mem_ctl.scala 382:88] - node _T_2264 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 384:61] + node _T_2240 = bits(byp_fetch_index, 1, 1) @[ifu_mem_ctl.scala 366:85] + node _T_2241 = eq(_T_2240, UInt<1>("h00")) @[ifu_mem_ctl.scala 366:69] + node _T_2242 = and(ic_miss_buff_data_valid_bypass_index, _T_2241) @[ifu_mem_ctl.scala 366:67] + node _T_2243 = bits(byp_fetch_index, 0, 0) @[ifu_mem_ctl.scala 366:107] + node _T_2244 = eq(_T_2243, UInt<1>("h00")) @[ifu_mem_ctl.scala 366:91] + node _T_2245 = and(_T_2242, _T_2244) @[ifu_mem_ctl.scala 366:89] + node _T_2246 = bits(byp_fetch_index, 1, 1) @[ifu_mem_ctl.scala 367:61] + node _T_2247 = eq(_T_2246, UInt<1>("h00")) @[ifu_mem_ctl.scala 367:45] + node _T_2248 = and(ic_miss_buff_data_valid_bypass_index, _T_2247) @[ifu_mem_ctl.scala 367:43] + node _T_2249 = bits(byp_fetch_index, 0, 0) @[ifu_mem_ctl.scala 367:83] + node _T_2250 = and(_T_2248, _T_2249) @[ifu_mem_ctl.scala 367:65] + node _T_2251 = or(_T_2245, _T_2250) @[ifu_mem_ctl.scala 366:112] + node _T_2252 = bits(byp_fetch_index, 1, 1) @[ifu_mem_ctl.scala 368:61] + node _T_2253 = and(ic_miss_buff_data_valid_bypass_index, _T_2252) @[ifu_mem_ctl.scala 368:43] + node _T_2254 = bits(byp_fetch_index, 0, 0) @[ifu_mem_ctl.scala 368:83] + node _T_2255 = eq(_T_2254, UInt<1>("h00")) @[ifu_mem_ctl.scala 368:67] + node _T_2256 = and(_T_2253, _T_2255) @[ifu_mem_ctl.scala 368:65] + node _T_2257 = or(_T_2251, _T_2256) @[ifu_mem_ctl.scala 367:88] + node _T_2258 = bits(byp_fetch_index, 1, 1) @[ifu_mem_ctl.scala 369:61] + node _T_2259 = and(ic_miss_buff_data_valid_bypass_index, _T_2258) @[ifu_mem_ctl.scala 369:43] + node _T_2260 = bits(byp_fetch_index, 0, 0) @[ifu_mem_ctl.scala 369:83] + node _T_2261 = and(_T_2259, _T_2260) @[ifu_mem_ctl.scala 369:65] + node _T_2262 = and(_T_2261, ic_miss_buff_data_valid_inc_bypass_index) @[ifu_mem_ctl.scala 369:87] + node _T_2263 = or(_T_2257, _T_2262) @[ifu_mem_ctl.scala 368:88] + node _T_2264 = bits(byp_fetch_index, 4, 2) @[ifu_mem_ctl.scala 370:61] node _T_2265 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_2266 = eq(_T_2264, _T_2265) @[ifu_mem_ctl.scala 384:87] - node _T_2267 = and(ic_miss_buff_data_valid_bypass_index, _T_2266) @[ifu_mem_ctl.scala 384:43] - node miss_buff_hit_unq_f = or(_T_2263, _T_2267) @[ifu_mem_ctl.scala 383:131] - node _T_2268 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 386:30] - node _T_2269 = eq(miss_wrap_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 386:68] - node _T_2270 = and(miss_buff_hit_unq_f, _T_2269) @[ifu_mem_ctl.scala 386:66] - node _T_2271 = and(_T_2268, _T_2270) @[ifu_mem_ctl.scala 386:43] - stream_hit_f <= _T_2271 @[ifu_mem_ctl.scala 386:16] - node _T_2272 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 387:31] - node _T_2273 = eq(miss_wrap_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 387:70] - node _T_2274 = and(miss_buff_hit_unq_f, _T_2273) @[ifu_mem_ctl.scala 387:68] - node _T_2275 = eq(_T_2274, UInt<1>("h00")) @[ifu_mem_ctl.scala 387:46] - node _T_2276 = and(_T_2272, _T_2275) @[ifu_mem_ctl.scala 387:44] - node _T_2277 = and(_T_2276, ifc_fetch_req_f) @[ifu_mem_ctl.scala 387:84] - stream_miss_f <= _T_2277 @[ifu_mem_ctl.scala 387:17] - node _T_2278 = bits(byp_fetch_index, 4, 1) @[ifu_mem_ctl.scala 388:35] + node _T_2266 = eq(_T_2264, _T_2265) @[ifu_mem_ctl.scala 370:87] + node _T_2267 = and(ic_miss_buff_data_valid_bypass_index, _T_2266) @[ifu_mem_ctl.scala 370:43] + node miss_buff_hit_unq_f = or(_T_2263, _T_2267) @[ifu_mem_ctl.scala 369:131] + node _T_2268 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 372:30] + node _T_2269 = eq(miss_wrap_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 372:68] + node _T_2270 = and(miss_buff_hit_unq_f, _T_2269) @[ifu_mem_ctl.scala 372:66] + node _T_2271 = and(_T_2268, _T_2270) @[ifu_mem_ctl.scala 372:43] + stream_hit_f <= _T_2271 @[ifu_mem_ctl.scala 372:16] + node _T_2272 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 373:31] + node _T_2273 = eq(miss_wrap_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 373:70] + node _T_2274 = and(miss_buff_hit_unq_f, _T_2273) @[ifu_mem_ctl.scala 373:68] + node _T_2275 = eq(_T_2274, UInt<1>("h00")) @[ifu_mem_ctl.scala 373:46] + node _T_2276 = and(_T_2272, _T_2275) @[ifu_mem_ctl.scala 373:44] + node _T_2277 = and(_T_2276, ifc_fetch_req_f) @[ifu_mem_ctl.scala 373:84] + stream_miss_f <= _T_2277 @[ifu_mem_ctl.scala 373:17] + node _T_2278 = bits(byp_fetch_index, 4, 1) @[ifu_mem_ctl.scala 374:35] node _T_2279 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2280 = eq(_T_2278, _T_2279) @[ifu_mem_ctl.scala 388:60] - node _T_2281 = and(_T_2280, ifc_fetch_req_f) @[ifu_mem_ctl.scala 388:94] - node _T_2282 = and(_T_2281, stream_hit_f) @[ifu_mem_ctl.scala 388:112] - stream_eol_f <= _T_2282 @[ifu_mem_ctl.scala 388:16] - node _T_2283 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 389:55] - node _T_2284 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 389:87] - node _T_2285 = or(_T_2283, _T_2284) @[ifu_mem_ctl.scala 389:74] - node _T_2286 = and(miss_buff_hit_unq_f, _T_2285) @[ifu_mem_ctl.scala 389:41] - crit_byp_hit_f <= _T_2286 @[ifu_mem_ctl.scala 389:18] - node _T_2287 = bits(ifu_bus_rid_ff, 2, 1) @[ifu_mem_ctl.scala 392:37] - node _T_2288 = bits(ifu_bus_rid_ff, 0, 0) @[ifu_mem_ctl.scala 392:70] - node _T_2289 = eq(_T_2288, UInt<1>("h00")) @[ifu_mem_ctl.scala 392:55] + node _T_2280 = eq(_T_2278, _T_2279) @[ifu_mem_ctl.scala 374:60] + node _T_2281 = and(_T_2280, ifc_fetch_req_f) @[ifu_mem_ctl.scala 374:94] + node _T_2282 = and(_T_2281, stream_hit_f) @[ifu_mem_ctl.scala 374:112] + stream_eol_f <= _T_2282 @[ifu_mem_ctl.scala 374:16] + node _T_2283 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 375:55] + node _T_2284 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 375:87] + node _T_2285 = or(_T_2283, _T_2284) @[ifu_mem_ctl.scala 375:74] + node _T_2286 = and(miss_buff_hit_unq_f, _T_2285) @[ifu_mem_ctl.scala 375:41] + crit_byp_hit_f <= _T_2286 @[ifu_mem_ctl.scala 375:18] + node _T_2287 = bits(ifu_bus_rid_ff, 2, 1) @[ifu_mem_ctl.scala 378:37] + node _T_2288 = bits(ifu_bus_rid_ff, 0, 0) @[ifu_mem_ctl.scala 378:70] + node _T_2289 = eq(_T_2288, UInt<1>("h00")) @[ifu_mem_ctl.scala 378:55] node other_tag = cat(_T_2287, _T_2289) @[Cat.scala 29:58] - node _T_2290 = eq(other_tag, UInt<1>("h00")) @[ifu_mem_ctl.scala 393:81] - node _T_2291 = bits(_T_2290, 0, 0) @[ifu_mem_ctl.scala 393:89] - node _T_2292 = bits(ic_miss_buff_data_valid, 0, 0) @[ifu_mem_ctl.scala 393:120] - node _T_2293 = eq(other_tag, UInt<1>("h01")) @[ifu_mem_ctl.scala 393:81] - node _T_2294 = bits(_T_2293, 0, 0) @[ifu_mem_ctl.scala 393:89] - node _T_2295 = bits(ic_miss_buff_data_valid, 1, 1) @[ifu_mem_ctl.scala 393:120] - node _T_2296 = eq(other_tag, UInt<2>("h02")) @[ifu_mem_ctl.scala 393:81] - node _T_2297 = bits(_T_2296, 0, 0) @[ifu_mem_ctl.scala 393:89] - node _T_2298 = bits(ic_miss_buff_data_valid, 2, 2) @[ifu_mem_ctl.scala 393:120] - node _T_2299 = eq(other_tag, UInt<2>("h03")) @[ifu_mem_ctl.scala 393:81] - node _T_2300 = bits(_T_2299, 0, 0) @[ifu_mem_ctl.scala 393:89] - node _T_2301 = bits(ic_miss_buff_data_valid, 3, 3) @[ifu_mem_ctl.scala 393:120] - node _T_2302 = eq(other_tag, UInt<3>("h04")) @[ifu_mem_ctl.scala 393:81] - node _T_2303 = bits(_T_2302, 0, 0) @[ifu_mem_ctl.scala 393:89] - node _T_2304 = bits(ic_miss_buff_data_valid, 4, 4) @[ifu_mem_ctl.scala 393:120] - node _T_2305 = eq(other_tag, UInt<3>("h05")) @[ifu_mem_ctl.scala 393:81] - node _T_2306 = bits(_T_2305, 0, 0) @[ifu_mem_ctl.scala 393:89] - node _T_2307 = bits(ic_miss_buff_data_valid, 5, 5) @[ifu_mem_ctl.scala 393:120] - node _T_2308 = eq(other_tag, UInt<3>("h06")) @[ifu_mem_ctl.scala 393:81] - node _T_2309 = bits(_T_2308, 0, 0) @[ifu_mem_ctl.scala 393:89] - node _T_2310 = bits(ic_miss_buff_data_valid, 6, 6) @[ifu_mem_ctl.scala 393:120] - node _T_2311 = eq(other_tag, UInt<3>("h07")) @[ifu_mem_ctl.scala 393:81] - node _T_2312 = bits(_T_2311, 0, 0) @[ifu_mem_ctl.scala 393:89] - node _T_2313 = bits(ic_miss_buff_data_valid, 7, 7) @[ifu_mem_ctl.scala 393:120] + node _T_2290 = eq(other_tag, UInt<1>("h00")) @[ifu_mem_ctl.scala 379:81] + node _T_2291 = bits(_T_2290, 0, 0) @[ifu_mem_ctl.scala 379:89] + node _T_2292 = bits(ic_miss_buff_data_valid, 0, 0) @[ifu_mem_ctl.scala 379:120] + node _T_2293 = eq(other_tag, UInt<1>("h01")) @[ifu_mem_ctl.scala 379:81] + node _T_2294 = bits(_T_2293, 0, 0) @[ifu_mem_ctl.scala 379:89] + node _T_2295 = bits(ic_miss_buff_data_valid, 1, 1) @[ifu_mem_ctl.scala 379:120] + node _T_2296 = eq(other_tag, UInt<2>("h02")) @[ifu_mem_ctl.scala 379:81] + node _T_2297 = bits(_T_2296, 0, 0) @[ifu_mem_ctl.scala 379:89] + node _T_2298 = bits(ic_miss_buff_data_valid, 2, 2) @[ifu_mem_ctl.scala 379:120] + node _T_2299 = eq(other_tag, UInt<2>("h03")) @[ifu_mem_ctl.scala 379:81] + node _T_2300 = bits(_T_2299, 0, 0) @[ifu_mem_ctl.scala 379:89] + node _T_2301 = bits(ic_miss_buff_data_valid, 3, 3) @[ifu_mem_ctl.scala 379:120] + node _T_2302 = eq(other_tag, UInt<3>("h04")) @[ifu_mem_ctl.scala 379:81] + node _T_2303 = bits(_T_2302, 0, 0) @[ifu_mem_ctl.scala 379:89] + node _T_2304 = bits(ic_miss_buff_data_valid, 4, 4) @[ifu_mem_ctl.scala 379:120] + node _T_2305 = eq(other_tag, UInt<3>("h05")) @[ifu_mem_ctl.scala 379:81] + node _T_2306 = bits(_T_2305, 0, 0) @[ifu_mem_ctl.scala 379:89] + node _T_2307 = bits(ic_miss_buff_data_valid, 5, 5) @[ifu_mem_ctl.scala 379:120] + node _T_2308 = eq(other_tag, UInt<3>("h06")) @[ifu_mem_ctl.scala 379:81] + node _T_2309 = bits(_T_2308, 0, 0) @[ifu_mem_ctl.scala 379:89] + node _T_2310 = bits(ic_miss_buff_data_valid, 6, 6) @[ifu_mem_ctl.scala 379:120] + node _T_2311 = eq(other_tag, UInt<3>("h07")) @[ifu_mem_ctl.scala 379:81] + node _T_2312 = bits(_T_2311, 0, 0) @[ifu_mem_ctl.scala 379:89] + node _T_2313 = bits(ic_miss_buff_data_valid, 7, 7) @[ifu_mem_ctl.scala 379:120] node _T_2314 = mux(_T_2291, _T_2292, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2315 = mux(_T_2294, _T_2295, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2316 = mux(_T_2297, _T_2298, UInt<1>("h00")) @[Mux.scala 27:72] @@ -5913,56 +5893,56 @@ circuit quasar_wrapper : node _T_2328 = or(_T_2327, _T_2321) @[Mux.scala 27:72] wire second_half_available : UInt<1> @[Mux.scala 27:72] second_half_available <= _T_2328 @[Mux.scala 27:72] - node _T_2329 = and(second_half_available, bus_ifu_wr_en_ff) @[ifu_mem_ctl.scala 394:46] - write_ic_16_bytes <= _T_2329 @[ifu_mem_ctl.scala 394:21] + node _T_2329 = and(second_half_available, bus_ifu_wr_en_ff) @[ifu_mem_ctl.scala 380:46] + write_ic_16_bytes <= _T_2329 @[ifu_mem_ctl.scala 380:21] node _T_2330 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2331 = eq(_T_2330, UInt<1>("h00")) @[ifu_mem_ctl.scala 395:89] - node _T_2332 = bits(_T_2331, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2331 = eq(_T_2330, UInt<1>("h00")) @[ifu_mem_ctl.scala 381:89] + node _T_2332 = bits(_T_2331, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2333 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2334 = eq(_T_2333, UInt<1>("h01")) @[ifu_mem_ctl.scala 395:89] - node _T_2335 = bits(_T_2334, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2334 = eq(_T_2333, UInt<1>("h01")) @[ifu_mem_ctl.scala 381:89] + node _T_2335 = bits(_T_2334, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2336 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2337 = eq(_T_2336, UInt<2>("h02")) @[ifu_mem_ctl.scala 395:89] - node _T_2338 = bits(_T_2337, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2337 = eq(_T_2336, UInt<2>("h02")) @[ifu_mem_ctl.scala 381:89] + node _T_2338 = bits(_T_2337, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2339 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2340 = eq(_T_2339, UInt<2>("h03")) @[ifu_mem_ctl.scala 395:89] - node _T_2341 = bits(_T_2340, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2340 = eq(_T_2339, UInt<2>("h03")) @[ifu_mem_ctl.scala 381:89] + node _T_2341 = bits(_T_2340, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2342 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2343 = eq(_T_2342, UInt<3>("h04")) @[ifu_mem_ctl.scala 395:89] - node _T_2344 = bits(_T_2343, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2343 = eq(_T_2342, UInt<3>("h04")) @[ifu_mem_ctl.scala 381:89] + node _T_2344 = bits(_T_2343, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2345 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2346 = eq(_T_2345, UInt<3>("h05")) @[ifu_mem_ctl.scala 395:89] - node _T_2347 = bits(_T_2346, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2346 = eq(_T_2345, UInt<3>("h05")) @[ifu_mem_ctl.scala 381:89] + node _T_2347 = bits(_T_2346, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2348 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2349 = eq(_T_2348, UInt<3>("h06")) @[ifu_mem_ctl.scala 395:89] - node _T_2350 = bits(_T_2349, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2349 = eq(_T_2348, UInt<3>("h06")) @[ifu_mem_ctl.scala 381:89] + node _T_2350 = bits(_T_2349, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2351 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2352 = eq(_T_2351, UInt<3>("h07")) @[ifu_mem_ctl.scala 395:89] - node _T_2353 = bits(_T_2352, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2352 = eq(_T_2351, UInt<3>("h07")) @[ifu_mem_ctl.scala 381:89] + node _T_2353 = bits(_T_2352, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2354 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2355 = eq(_T_2354, UInt<4>("h08")) @[ifu_mem_ctl.scala 395:89] - node _T_2356 = bits(_T_2355, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2355 = eq(_T_2354, UInt<4>("h08")) @[ifu_mem_ctl.scala 381:89] + node _T_2356 = bits(_T_2355, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2357 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2358 = eq(_T_2357, UInt<4>("h09")) @[ifu_mem_ctl.scala 395:89] - node _T_2359 = bits(_T_2358, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2358 = eq(_T_2357, UInt<4>("h09")) @[ifu_mem_ctl.scala 381:89] + node _T_2359 = bits(_T_2358, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2360 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2361 = eq(_T_2360, UInt<4>("h0a")) @[ifu_mem_ctl.scala 395:89] - node _T_2362 = bits(_T_2361, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2361 = eq(_T_2360, UInt<4>("h0a")) @[ifu_mem_ctl.scala 381:89] + node _T_2362 = bits(_T_2361, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2363 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2364 = eq(_T_2363, UInt<4>("h0b")) @[ifu_mem_ctl.scala 395:89] - node _T_2365 = bits(_T_2364, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2364 = eq(_T_2363, UInt<4>("h0b")) @[ifu_mem_ctl.scala 381:89] + node _T_2365 = bits(_T_2364, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2366 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2367 = eq(_T_2366, UInt<4>("h0c")) @[ifu_mem_ctl.scala 395:89] - node _T_2368 = bits(_T_2367, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2367 = eq(_T_2366, UInt<4>("h0c")) @[ifu_mem_ctl.scala 381:89] + node _T_2368 = bits(_T_2367, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2369 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2370 = eq(_T_2369, UInt<4>("h0d")) @[ifu_mem_ctl.scala 395:89] - node _T_2371 = bits(_T_2370, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2370 = eq(_T_2369, UInt<4>("h0d")) @[ifu_mem_ctl.scala 381:89] + node _T_2371 = bits(_T_2370, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2372 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2373 = eq(_T_2372, UInt<4>("h0e")) @[ifu_mem_ctl.scala 395:89] - node _T_2374 = bits(_T_2373, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2373 = eq(_T_2372, UInt<4>("h0e")) @[ifu_mem_ctl.scala 381:89] + node _T_2374 = bits(_T_2373, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2375 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2376 = eq(_T_2375, UInt<4>("h0f")) @[ifu_mem_ctl.scala 395:89] - node _T_2377 = bits(_T_2376, 0, 0) @[ifu_mem_ctl.scala 395:97] + node _T_2376 = eq(_T_2375, UInt<4>("h0f")) @[ifu_mem_ctl.scala 381:89] + node _T_2377 = bits(_T_2376, 0, 0) @[ifu_mem_ctl.scala 381:97] node _T_2378 = mux(_T_2332, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_2379 = mux(_T_2335, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_2380 = mux(_T_2338, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -5997,53 +5977,53 @@ circuit quasar_wrapper : wire _T_2409 : UInt<32> @[Mux.scala 27:72] _T_2409 <= _T_2408 @[Mux.scala 27:72] node _T_2410 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2411 = eq(_T_2410, UInt<1>("h00")) @[ifu_mem_ctl.scala 396:66] - node _T_2412 = bits(_T_2411, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2411 = eq(_T_2410, UInt<1>("h00")) @[ifu_mem_ctl.scala 382:66] + node _T_2412 = bits(_T_2411, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2413 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2414 = eq(_T_2413, UInt<1>("h01")) @[ifu_mem_ctl.scala 396:66] - node _T_2415 = bits(_T_2414, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2414 = eq(_T_2413, UInt<1>("h01")) @[ifu_mem_ctl.scala 382:66] + node _T_2415 = bits(_T_2414, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2416 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2417 = eq(_T_2416, UInt<2>("h02")) @[ifu_mem_ctl.scala 396:66] - node _T_2418 = bits(_T_2417, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2417 = eq(_T_2416, UInt<2>("h02")) @[ifu_mem_ctl.scala 382:66] + node _T_2418 = bits(_T_2417, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2419 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2420 = eq(_T_2419, UInt<2>("h03")) @[ifu_mem_ctl.scala 396:66] - node _T_2421 = bits(_T_2420, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2420 = eq(_T_2419, UInt<2>("h03")) @[ifu_mem_ctl.scala 382:66] + node _T_2421 = bits(_T_2420, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2422 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2423 = eq(_T_2422, UInt<3>("h04")) @[ifu_mem_ctl.scala 396:66] - node _T_2424 = bits(_T_2423, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2423 = eq(_T_2422, UInt<3>("h04")) @[ifu_mem_ctl.scala 382:66] + node _T_2424 = bits(_T_2423, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2425 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2426 = eq(_T_2425, UInt<3>("h05")) @[ifu_mem_ctl.scala 396:66] - node _T_2427 = bits(_T_2426, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2426 = eq(_T_2425, UInt<3>("h05")) @[ifu_mem_ctl.scala 382:66] + node _T_2427 = bits(_T_2426, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2428 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2429 = eq(_T_2428, UInt<3>("h06")) @[ifu_mem_ctl.scala 396:66] - node _T_2430 = bits(_T_2429, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2429 = eq(_T_2428, UInt<3>("h06")) @[ifu_mem_ctl.scala 382:66] + node _T_2430 = bits(_T_2429, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2431 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2432 = eq(_T_2431, UInt<3>("h07")) @[ifu_mem_ctl.scala 396:66] - node _T_2433 = bits(_T_2432, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2432 = eq(_T_2431, UInt<3>("h07")) @[ifu_mem_ctl.scala 382:66] + node _T_2433 = bits(_T_2432, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2434 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2435 = eq(_T_2434, UInt<4>("h08")) @[ifu_mem_ctl.scala 396:66] - node _T_2436 = bits(_T_2435, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2435 = eq(_T_2434, UInt<4>("h08")) @[ifu_mem_ctl.scala 382:66] + node _T_2436 = bits(_T_2435, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2437 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2438 = eq(_T_2437, UInt<4>("h09")) @[ifu_mem_ctl.scala 396:66] - node _T_2439 = bits(_T_2438, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2438 = eq(_T_2437, UInt<4>("h09")) @[ifu_mem_ctl.scala 382:66] + node _T_2439 = bits(_T_2438, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2440 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2441 = eq(_T_2440, UInt<4>("h0a")) @[ifu_mem_ctl.scala 396:66] - node _T_2442 = bits(_T_2441, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2441 = eq(_T_2440, UInt<4>("h0a")) @[ifu_mem_ctl.scala 382:66] + node _T_2442 = bits(_T_2441, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2443 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2444 = eq(_T_2443, UInt<4>("h0b")) @[ifu_mem_ctl.scala 396:66] - node _T_2445 = bits(_T_2444, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2444 = eq(_T_2443, UInt<4>("h0b")) @[ifu_mem_ctl.scala 382:66] + node _T_2445 = bits(_T_2444, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2446 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2447 = eq(_T_2446, UInt<4>("h0c")) @[ifu_mem_ctl.scala 396:66] - node _T_2448 = bits(_T_2447, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2447 = eq(_T_2446, UInt<4>("h0c")) @[ifu_mem_ctl.scala 382:66] + node _T_2448 = bits(_T_2447, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2449 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2450 = eq(_T_2449, UInt<4>("h0d")) @[ifu_mem_ctl.scala 396:66] - node _T_2451 = bits(_T_2450, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2450 = eq(_T_2449, UInt<4>("h0d")) @[ifu_mem_ctl.scala 382:66] + node _T_2451 = bits(_T_2450, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2452 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2453 = eq(_T_2452, UInt<4>("h0e")) @[ifu_mem_ctl.scala 396:66] - node _T_2454 = bits(_T_2453, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2453 = eq(_T_2452, UInt<4>("h0e")) @[ifu_mem_ctl.scala 382:66] + node _T_2454 = bits(_T_2453, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2455 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2456 = eq(_T_2455, UInt<4>("h0f")) @[ifu_mem_ctl.scala 396:66] - node _T_2457 = bits(_T_2456, 0, 0) @[ifu_mem_ctl.scala 396:74] + node _T_2456 = eq(_T_2455, UInt<4>("h0f")) @[ifu_mem_ctl.scala 382:66] + node _T_2457 = bits(_T_2456, 0, 0) @[ifu_mem_ctl.scala 382:74] node _T_2458 = mux(_T_2412, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_2459 = mux(_T_2415, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_2460 = mux(_T_2418, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -6078,12 +6058,12 @@ circuit quasar_wrapper : wire _T_2489 : UInt<32> @[Mux.scala 27:72] _T_2489 <= _T_2488 @[Mux.scala 27:72] node _T_2490 = cat(_T_2409, _T_2489) @[Cat.scala 29:58] - ic_miss_buff_half <= _T_2490 @[ifu_mem_ctl.scala 395:21] - node _T_2491 = and(io.ic.tag_perr, sel_ic_data) @[ifu_mem_ctl.scala 398:44] - node _T_2492 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[ifu_mem_ctl.scala 398:91] - node _T_2493 = eq(_T_2492, UInt<1>("h00")) @[ifu_mem_ctl.scala 398:60] - node _T_2494 = and(_T_2491, _T_2493) @[ifu_mem_ctl.scala 398:58] - ic_rd_parity_final_err <= _T_2494 @[ifu_mem_ctl.scala 398:26] + ic_miss_buff_half <= _T_2490 @[ifu_mem_ctl.scala 381:21] + node _T_2491 = and(io.ic.tag_perr, sel_ic_data) @[ifu_mem_ctl.scala 385:44] + node _T_2492 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[ifu_mem_ctl.scala 385:91] + node _T_2493 = eq(_T_2492, UInt<1>("h00")) @[ifu_mem_ctl.scala 385:60] + node _T_2494 = and(_T_2491, _T_2493) @[ifu_mem_ctl.scala 385:58] + ic_rd_parity_final_err <= _T_2494 @[ifu_mem_ctl.scala 385:26] wire ifu_ic_rw_int_addr_ff : UInt<7> ifu_ic_rw_int_addr_ff <= UInt<1>("h00") wire perr_sb_write_status : UInt<1> @@ -6096,16 +6076,16 @@ circuit quasar_wrapper : perr_sel_invalidate <= UInt<1>("h00") node _T_2495 = bits(perr_sel_invalidate, 0, 0) @[Bitwise.scala 72:15] node perr_err_inv_way = mux(_T_2495, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_2496 = eq(perr_state, UInt<3>("h03")) @[ifu_mem_ctl.scala 405:34] - iccm_correct_ecc <= _T_2496 @[ifu_mem_ctl.scala 405:20] - node dma_sb_err_state = eq(perr_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 406:37] - wire dma_sb_err_state_ff : UInt<1> @[ifu_mem_ctl.scala 407:33] - node _T_2497 = eq(dma_sb_err_state_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 408:49] - node _T_2498 = and(iccm_correct_ecc, _T_2497) @[ifu_mem_ctl.scala 408:47] - io.iccm.buf_correct_ecc <= _T_2498 @[ifu_mem_ctl.scala 408:27] - reg _T_2499 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 409:58] - _T_2499 <= dma_sb_err_state @[ifu_mem_ctl.scala 409:58] - dma_sb_err_state_ff <= _T_2499 @[ifu_mem_ctl.scala 409:23] + node _T_2496 = eq(perr_state, UInt<3>("h03")) @[ifu_mem_ctl.scala 392:34] + iccm_correct_ecc <= _T_2496 @[ifu_mem_ctl.scala 392:20] + node dma_sb_err_state = eq(perr_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 393:37] + wire dma_sb_err_state_ff : UInt<1> @[ifu_mem_ctl.scala 394:33] + node _T_2497 = eq(dma_sb_err_state_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 395:49] + node _T_2498 = and(iccm_correct_ecc, _T_2497) @[ifu_mem_ctl.scala 395:47] + io.iccm.buf_correct_ecc <= _T_2498 @[ifu_mem_ctl.scala 395:27] + reg _T_2499 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 396:58] + _T_2499 <= dma_sb_err_state @[ifu_mem_ctl.scala 396:58] + dma_sb_err_state_ff <= _T_2499 @[ifu_mem_ctl.scala 396:23] wire perr_nxtstate : UInt<3> perr_nxtstate <= UInt<1>("h00") wire perr_state_en : UInt<1> @@ -6114,179 +6094,179 @@ circuit quasar_wrapper : iccm_error_start <= UInt<1>("h00") node _T_2500 = eq(UInt<3>("h00"), perr_state) @[Conditional.scala 37:30] when _T_2500 : @[Conditional.scala 40:58] - node _T_2501 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 417:106] - node _T_2502 = and(io.dec_mem_ctrl.ifu_ic_error_start, _T_2501) @[ifu_mem_ctl.scala 417:104] - node _T_2503 = bits(_T_2502, 0, 0) @[ifu_mem_ctl.scala 417:127] - node _T_2504 = mux(_T_2503, UInt<3>("h01"), UInt<3>("h02")) @[ifu_mem_ctl.scala 417:67] - node _T_2505 = mux(io.iccm_dma_sb_error, UInt<3>("h04"), _T_2504) @[ifu_mem_ctl.scala 417:27] - perr_nxtstate <= _T_2505 @[ifu_mem_ctl.scala 417:21] - node _T_2506 = or(iccm_error_start, io.dec_mem_ctrl.ifu_ic_error_start) @[ifu_mem_ctl.scala 418:44] - node _T_2507 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 418:84] - node _T_2508 = and(_T_2506, _T_2507) @[ifu_mem_ctl.scala 418:82] - node _T_2509 = or(_T_2508, io.iccm_dma_sb_error) @[ifu_mem_ctl.scala 418:105] - node _T_2510 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 418:131] - node _T_2511 = and(_T_2509, _T_2510) @[ifu_mem_ctl.scala 418:129] - perr_state_en <= _T_2511 @[ifu_mem_ctl.scala 418:21] - perr_sb_write_status <= perr_state_en @[ifu_mem_ctl.scala 419:28] + node _T_2501 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 404:106] + node _T_2502 = and(io.dec_mem_ctrl.ifu_ic_error_start, _T_2501) @[ifu_mem_ctl.scala 404:104] + node _T_2503 = bits(_T_2502, 0, 0) @[ifu_mem_ctl.scala 404:127] + node _T_2504 = mux(_T_2503, UInt<3>("h01"), UInt<3>("h02")) @[ifu_mem_ctl.scala 404:67] + node _T_2505 = mux(io.iccm_dma_sb_error, UInt<3>("h04"), _T_2504) @[ifu_mem_ctl.scala 404:27] + perr_nxtstate <= _T_2505 @[ifu_mem_ctl.scala 404:21] + node _T_2506 = or(iccm_error_start, io.dec_mem_ctrl.ifu_ic_error_start) @[ifu_mem_ctl.scala 405:44] + node _T_2507 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 405:84] + node _T_2508 = and(_T_2506, _T_2507) @[ifu_mem_ctl.scala 405:82] + node _T_2509 = or(_T_2508, io.iccm_dma_sb_error) @[ifu_mem_ctl.scala 405:105] + node _T_2510 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 405:131] + node _T_2511 = and(_T_2509, _T_2510) @[ifu_mem_ctl.scala 405:129] + perr_state_en <= _T_2511 @[ifu_mem_ctl.scala 405:21] + perr_sb_write_status <= perr_state_en @[ifu_mem_ctl.scala 406:28] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_2512 = eq(UInt<3>("h01"), perr_state) @[Conditional.scala 37:30] when _T_2512 : @[Conditional.scala 39:67] - perr_nxtstate <= UInt<3>("h00") @[ifu_mem_ctl.scala 422:21] - node _T_2513 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 423:50] - perr_state_en <= _T_2513 @[ifu_mem_ctl.scala 423:21] - node _T_2514 = and(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_flush_err_wb) @[ifu_mem_ctl.scala 424:56] - perr_sel_invalidate <= _T_2514 @[ifu_mem_ctl.scala 424:27] + perr_nxtstate <= UInt<3>("h00") @[ifu_mem_ctl.scala 409:21] + node _T_2513 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 410:50] + perr_state_en <= _T_2513 @[ifu_mem_ctl.scala 410:21] + node _T_2514 = and(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_flush_err_wb) @[ifu_mem_ctl.scala 411:56] + perr_sel_invalidate <= _T_2514 @[ifu_mem_ctl.scala 411:27] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2515 = eq(UInt<3>("h02"), perr_state) @[Conditional.scala 37:30] when _T_2515 : @[Conditional.scala 39:67] - node _T_2516 = eq(io.dec_mem_ctrl.dec_tlu_flush_err_wb, UInt<1>("h00")) @[ifu_mem_ctl.scala 427:30] - node _T_2517 = and(_T_2516, io.dec_tlu_flush_lower_wb) @[ifu_mem_ctl.scala 427:68] - node _T_2518 = or(_T_2517, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 427:98] - node _T_2519 = bits(_T_2518, 0, 0) @[ifu_mem_ctl.scala 427:142] - node _T_2520 = mux(_T_2519, UInt<3>("h00"), UInt<3>("h03")) @[ifu_mem_ctl.scala 427:27] - perr_nxtstate <= _T_2520 @[ifu_mem_ctl.scala 427:21] - node _T_2521 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 428:50] - perr_state_en <= _T_2521 @[ifu_mem_ctl.scala 428:21] + node _T_2516 = eq(io.dec_mem_ctrl.dec_tlu_flush_err_wb, UInt<1>("h00")) @[ifu_mem_ctl.scala 414:30] + node _T_2517 = and(_T_2516, io.dec_tlu_flush_lower_wb) @[ifu_mem_ctl.scala 414:68] + node _T_2518 = or(_T_2517, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 414:98] + node _T_2519 = bits(_T_2518, 0, 0) @[ifu_mem_ctl.scala 414:142] + node _T_2520 = mux(_T_2519, UInt<3>("h00"), UInt<3>("h03")) @[ifu_mem_ctl.scala 414:27] + perr_nxtstate <= _T_2520 @[ifu_mem_ctl.scala 414:21] + node _T_2521 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 415:50] + perr_state_en <= _T_2521 @[ifu_mem_ctl.scala 415:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2522 = eq(UInt<3>("h04"), perr_state) @[Conditional.scala 37:30] when _T_2522 : @[Conditional.scala 39:67] - node _T_2523 = mux(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<3>("h00"), UInt<3>("h03")) @[ifu_mem_ctl.scala 431:27] - perr_nxtstate <= _T_2523 @[ifu_mem_ctl.scala 431:21] - perr_state_en <= UInt<1>("h01") @[ifu_mem_ctl.scala 432:21] + node _T_2523 = mux(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<3>("h00"), UInt<3>("h03")) @[ifu_mem_ctl.scala 418:27] + perr_nxtstate <= _T_2523 @[ifu_mem_ctl.scala 418:21] + perr_state_en <= UInt<1>("h01") @[ifu_mem_ctl.scala 419:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2524 = eq(UInt<3>("h03"), perr_state) @[Conditional.scala 37:30] when _T_2524 : @[Conditional.scala 39:67] - perr_nxtstate <= UInt<3>("h00") @[ifu_mem_ctl.scala 435:21] - perr_state_en <= UInt<1>("h01") @[ifu_mem_ctl.scala 436:21] + perr_nxtstate <= UInt<3>("h00") @[ifu_mem_ctl.scala 422:21] + perr_state_en <= UInt<1>("h01") @[ifu_mem_ctl.scala 423:21] skip @[Conditional.scala 39:67] reg _T_2525 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when perr_state_en : @[Reg.scala 28:19] _T_2525 <= perr_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - perr_state <= _T_2525 @[ifu_mem_ctl.scala 439:14] + perr_state <= _T_2525 @[ifu_mem_ctl.scala 426:14] wire err_stop_nxtstate : UInt<2> err_stop_nxtstate <= UInt<1>("h00") wire err_stop_state_en : UInt<1> err_stop_state_en <= UInt<1>("h00") - io.iccm.correction_state <= UInt<1>("h00") @[ifu_mem_ctl.scala 443:28] + io.iccm.correction_state <= UInt<1>("h00") @[ifu_mem_ctl.scala 430:28] node _T_2526 = eq(UInt<2>("h00"), err_stop_state) @[Conditional.scala 37:30] when _T_2526 : @[Conditional.scala 40:58] - err_stop_nxtstate <= UInt<2>("h01") @[ifu_mem_ctl.scala 446:25] - node _T_2527 = eq(perr_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 447:79] - node _T_2528 = and(io.dec_mem_ctrl.dec_tlu_flush_err_wb, _T_2527) @[ifu_mem_ctl.scala 447:65] - node _T_2529 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 447:96] - node _T_2530 = and(_T_2528, _T_2529) @[ifu_mem_ctl.scala 447:94] - err_stop_state_en <= _T_2530 @[ifu_mem_ctl.scala 447:25] + err_stop_nxtstate <= UInt<2>("h01") @[ifu_mem_ctl.scala 433:25] + node _T_2527 = eq(perr_state, UInt<3>("h02")) @[ifu_mem_ctl.scala 434:79] + node _T_2528 = and(io.dec_mem_ctrl.dec_tlu_flush_err_wb, _T_2527) @[ifu_mem_ctl.scala 434:65] + node _T_2529 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 434:96] + node _T_2530 = and(_T_2528, _T_2529) @[ifu_mem_ctl.scala 434:94] + err_stop_state_en <= _T_2530 @[ifu_mem_ctl.scala 434:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_2531 = eq(UInt<2>("h01"), err_stop_state) @[Conditional.scala 37:30] when _T_2531 : @[Conditional.scala 39:67] - node _T_2532 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 450:59] - node _T_2533 = or(_T_2532, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 450:99] - node _T_2534 = bits(_T_2533, 0, 0) @[ifu_mem_ctl.scala 450:143] - node _T_2535 = eq(io.ifu_fetch_val, UInt<2>("h03")) @[ifu_mem_ctl.scala 451:31] - node _T_2536 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 451:56] - node _T_2537 = and(_T_2536, two_byte_instr) @[ifu_mem_ctl.scala 451:59] - node _T_2538 = or(_T_2535, _T_2537) @[ifu_mem_ctl.scala 451:38] - node _T_2539 = bits(_T_2538, 0, 0) @[ifu_mem_ctl.scala 451:83] - node _T_2540 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 452:31] - node _T_2541 = bits(_T_2540, 0, 0) @[ifu_mem_ctl.scala 452:41] - node _T_2542 = mux(_T_2541, UInt<2>("h02"), UInt<2>("h01")) @[ifu_mem_ctl.scala 452:14] - node _T_2543 = mux(_T_2539, UInt<2>("h03"), _T_2542) @[ifu_mem_ctl.scala 451:12] - node _T_2544 = mux(_T_2534, UInt<2>("h00"), _T_2543) @[ifu_mem_ctl.scala 450:31] - err_stop_nxtstate <= _T_2544 @[ifu_mem_ctl.scala 450:25] - node _T_2545 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 453:54] - node _T_2546 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 453:112] - node _T_2547 = or(_T_2545, _T_2546) @[ifu_mem_ctl.scala 453:94] - node _T_2548 = or(_T_2547, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 453:116] - node _T_2549 = or(_T_2548, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 453:139] - err_stop_state_en <= _T_2549 @[ifu_mem_ctl.scala 453:25] - node _T_2550 = bits(io.ifu_fetch_val, 1, 0) @[ifu_mem_ctl.scala 454:43] - node _T_2551 = eq(_T_2550, UInt<2>("h03")) @[ifu_mem_ctl.scala 454:48] - node _T_2552 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 454:75] - node _T_2553 = and(_T_2552, two_byte_instr) @[ifu_mem_ctl.scala 454:79] - node _T_2554 = or(_T_2551, _T_2553) @[ifu_mem_ctl.scala 454:56] - node _T_2555 = or(io.exu_flush_final, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 454:122] - node _T_2556 = eq(_T_2555, UInt<1>("h00")) @[ifu_mem_ctl.scala 454:101] - node _T_2557 = and(_T_2554, _T_2556) @[ifu_mem_ctl.scala 454:99] - err_stop_fetch <= _T_2557 @[ifu_mem_ctl.scala 454:22] - io.iccm.correction_state <= UInt<1>("h01") @[ifu_mem_ctl.scala 455:32] + node _T_2532 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 437:59] + node _T_2533 = or(_T_2532, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 437:99] + node _T_2534 = bits(_T_2533, 0, 0) @[ifu_mem_ctl.scala 437:143] + node _T_2535 = eq(io.ifu_fetch_val, UInt<2>("h03")) @[ifu_mem_ctl.scala 438:31] + node _T_2536 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 438:56] + node _T_2537 = and(_T_2536, two_byte_instr) @[ifu_mem_ctl.scala 438:59] + node _T_2538 = or(_T_2535, _T_2537) @[ifu_mem_ctl.scala 438:38] + node _T_2539 = bits(_T_2538, 0, 0) @[ifu_mem_ctl.scala 438:83] + node _T_2540 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 439:31] + node _T_2541 = bits(_T_2540, 0, 0) @[ifu_mem_ctl.scala 439:41] + node _T_2542 = mux(_T_2541, UInt<2>("h02"), UInt<2>("h01")) @[ifu_mem_ctl.scala 439:14] + node _T_2543 = mux(_T_2539, UInt<2>("h03"), _T_2542) @[ifu_mem_ctl.scala 438:12] + node _T_2544 = mux(_T_2534, UInt<2>("h00"), _T_2543) @[ifu_mem_ctl.scala 437:31] + err_stop_nxtstate <= _T_2544 @[ifu_mem_ctl.scala 437:25] + node _T_2545 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 440:54] + node _T_2546 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 440:112] + node _T_2547 = or(_T_2545, _T_2546) @[ifu_mem_ctl.scala 440:94] + node _T_2548 = or(_T_2547, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 440:116] + node _T_2549 = or(_T_2548, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 440:139] + err_stop_state_en <= _T_2549 @[ifu_mem_ctl.scala 440:25] + node _T_2550 = bits(io.ifu_fetch_val, 1, 0) @[ifu_mem_ctl.scala 441:43] + node _T_2551 = eq(_T_2550, UInt<2>("h03")) @[ifu_mem_ctl.scala 441:48] + node _T_2552 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 441:75] + node _T_2553 = and(_T_2552, two_byte_instr) @[ifu_mem_ctl.scala 441:79] + node _T_2554 = or(_T_2551, _T_2553) @[ifu_mem_ctl.scala 441:56] + node _T_2555 = or(io.exu_flush_final, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 441:122] + node _T_2556 = eq(_T_2555, UInt<1>("h00")) @[ifu_mem_ctl.scala 441:101] + node _T_2557 = and(_T_2554, _T_2556) @[ifu_mem_ctl.scala 441:99] + err_stop_fetch <= _T_2557 @[ifu_mem_ctl.scala 441:22] + io.iccm.correction_state <= UInt<1>("h01") @[ifu_mem_ctl.scala 442:32] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2558 = eq(UInt<2>("h02"), err_stop_state) @[Conditional.scala 37:30] when _T_2558 : @[Conditional.scala 39:67] - node _T_2559 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 458:59] - node _T_2560 = or(_T_2559, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 458:99] - node _T_2561 = bits(_T_2560, 0, 0) @[ifu_mem_ctl.scala 458:137] - node _T_2562 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 459:46] - node _T_2563 = bits(_T_2562, 0, 0) @[ifu_mem_ctl.scala 459:50] - node _T_2564 = mux(_T_2563, UInt<2>("h03"), UInt<2>("h02")) @[ifu_mem_ctl.scala 459:29] - node _T_2565 = mux(_T_2561, UInt<2>("h00"), _T_2564) @[ifu_mem_ctl.scala 458:31] - err_stop_nxtstate <= _T_2565 @[ifu_mem_ctl.scala 458:25] - node _T_2566 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 460:54] - node _T_2567 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 460:112] - node _T_2568 = or(_T_2566, _T_2567) @[ifu_mem_ctl.scala 460:94] - node _T_2569 = or(_T_2568, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 460:116] - err_stop_state_en <= _T_2569 @[ifu_mem_ctl.scala 460:25] - node _T_2570 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 461:41] - node _T_2571 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 461:47] - node _T_2572 = and(_T_2570, _T_2571) @[ifu_mem_ctl.scala 461:45] - node _T_2573 = eq(io.dec_mem_ctrl.dec_tlu_i0_commit_cmt, UInt<1>("h00")) @[ifu_mem_ctl.scala 461:69] - node _T_2574 = and(_T_2572, _T_2573) @[ifu_mem_ctl.scala 461:67] - err_stop_fetch <= _T_2574 @[ifu_mem_ctl.scala 461:22] - io.iccm.correction_state <= UInt<1>("h01") @[ifu_mem_ctl.scala 462:32] + node _T_2559 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 445:59] + node _T_2560 = or(_T_2559, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 445:99] + node _T_2561 = bits(_T_2560, 0, 0) @[ifu_mem_ctl.scala 445:137] + node _T_2562 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 446:46] + node _T_2563 = bits(_T_2562, 0, 0) @[ifu_mem_ctl.scala 446:50] + node _T_2564 = mux(_T_2563, UInt<2>("h03"), UInt<2>("h02")) @[ifu_mem_ctl.scala 446:29] + node _T_2565 = mux(_T_2561, UInt<2>("h00"), _T_2564) @[ifu_mem_ctl.scala 445:31] + err_stop_nxtstate <= _T_2565 @[ifu_mem_ctl.scala 445:25] + node _T_2566 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 447:54] + node _T_2567 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 447:112] + node _T_2568 = or(_T_2566, _T_2567) @[ifu_mem_ctl.scala 447:94] + node _T_2569 = or(_T_2568, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 447:116] + err_stop_state_en <= _T_2569 @[ifu_mem_ctl.scala 447:25] + node _T_2570 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 448:41] + node _T_2571 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 448:47] + node _T_2572 = and(_T_2570, _T_2571) @[ifu_mem_ctl.scala 448:45] + node _T_2573 = eq(io.dec_mem_ctrl.dec_tlu_i0_commit_cmt, UInt<1>("h00")) @[ifu_mem_ctl.scala 448:69] + node _T_2574 = and(_T_2572, _T_2573) @[ifu_mem_ctl.scala 448:67] + err_stop_fetch <= _T_2574 @[ifu_mem_ctl.scala 448:22] + io.iccm.correction_state <= UInt<1>("h01") @[ifu_mem_ctl.scala 449:32] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2575 = eq(UInt<2>("h03"), err_stop_state) @[Conditional.scala 37:30] when _T_2575 : @[Conditional.scala 39:67] - node _T_2576 = eq(io.dec_mem_ctrl.dec_tlu_flush_err_wb, UInt<1>("h00")) @[ifu_mem_ctl.scala 465:62] - node _T_2577 = and(io.dec_tlu_flush_lower_wb, _T_2576) @[ifu_mem_ctl.scala 465:60] - node _T_2578 = or(_T_2577, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 465:101] - node _T_2579 = or(_T_2578, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 465:141] - node _T_2580 = bits(_T_2579, 0, 0) @[ifu_mem_ctl.scala 465:179] - node _T_2581 = bits(io.dec_mem_ctrl.dec_tlu_flush_err_wb, 0, 0) @[ifu_mem_ctl.scala 466:73] - node _T_2582 = mux(_T_2581, UInt<2>("h01"), UInt<2>("h03")) @[ifu_mem_ctl.scala 466:29] - node _T_2583 = mux(_T_2580, UInt<2>("h00"), _T_2582) @[ifu_mem_ctl.scala 465:31] - err_stop_nxtstate <= _T_2583 @[ifu_mem_ctl.scala 465:25] - node _T_2584 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 467:54] - node _T_2585 = or(_T_2584, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 467:94] - err_stop_state_en <= _T_2585 @[ifu_mem_ctl.scala 467:25] - err_stop_fetch <= UInt<1>("h01") @[ifu_mem_ctl.scala 468:22] - io.iccm.correction_state <= UInt<1>("h01") @[ifu_mem_ctl.scala 469:32] + node _T_2576 = eq(io.dec_mem_ctrl.dec_tlu_flush_err_wb, UInt<1>("h00")) @[ifu_mem_ctl.scala 452:62] + node _T_2577 = and(io.dec_tlu_flush_lower_wb, _T_2576) @[ifu_mem_ctl.scala 452:60] + node _T_2578 = or(_T_2577, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 452:101] + node _T_2579 = or(_T_2578, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 452:141] + node _T_2580 = bits(_T_2579, 0, 0) @[ifu_mem_ctl.scala 452:179] + node _T_2581 = bits(io.dec_mem_ctrl.dec_tlu_flush_err_wb, 0, 0) @[ifu_mem_ctl.scala 453:73] + node _T_2582 = mux(_T_2581, UInt<2>("h01"), UInt<2>("h03")) @[ifu_mem_ctl.scala 453:29] + node _T_2583 = mux(_T_2580, UInt<2>("h00"), _T_2582) @[ifu_mem_ctl.scala 452:31] + err_stop_nxtstate <= _T_2583 @[ifu_mem_ctl.scala 452:25] + node _T_2584 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 454:54] + node _T_2585 = or(_T_2584, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 454:94] + err_stop_state_en <= _T_2585 @[ifu_mem_ctl.scala 454:25] + err_stop_fetch <= UInt<1>("h01") @[ifu_mem_ctl.scala 455:22] + io.iccm.correction_state <= UInt<1>("h01") @[ifu_mem_ctl.scala 456:32] skip @[Conditional.scala 39:67] reg _T_2586 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when err_stop_state_en : @[Reg.scala 28:19] _T_2586 <= err_stop_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - err_stop_state <= _T_2586 @[ifu_mem_ctl.scala 472:18] - bus_ifu_bus_clk_en <= io.ifu_bus_clk_en @[ifu_mem_ctl.scala 473:22] + err_stop_state <= _T_2586 @[ifu_mem_ctl.scala 459:18] + bus_ifu_bus_clk_en <= io.ifu_bus_clk_en @[ifu_mem_ctl.scala 460:22] inst rvclkhdr_68 of rvclkhdr_68 @[lib.scala 327:22] rvclkhdr_68.clock <= clock rvclkhdr_68.reset <= reset rvclkhdr_68.io.clk <= clock @[lib.scala 328:17] rvclkhdr_68.io.en <= bus_ifu_bus_clk_en @[lib.scala 329:16] rvclkhdr_68.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_2587 = or(bus_ifu_bus_clk_en, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 475:59] + node _T_2587 = or(bus_ifu_bus_clk_en, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 462:59] inst rvclkhdr_69 of rvclkhdr_69 @[lib.scala 327:22] rvclkhdr_69.clock <= clock rvclkhdr_69.reset <= reset rvclkhdr_69.io.clk <= clock @[lib.scala 328:17] rvclkhdr_69.io.en <= _T_2587 @[lib.scala 329:16] rvclkhdr_69.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - reg bus_ifu_bus_clk_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 476:61] - bus_ifu_bus_clk_en_ff <= bus_ifu_bus_clk_en @[ifu_mem_ctl.scala 476:61] - reg _T_2588 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 477:52] - _T_2588 <= scnd_miss_req_in @[ifu_mem_ctl.scala 477:52] - scnd_miss_req_q <= _T_2588 @[ifu_mem_ctl.scala 477:19] - reg scnd_miss_req_ff2 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 478:57] - scnd_miss_req_ff2 <= scnd_miss_req @[ifu_mem_ctl.scala 478:57] - node _T_2589 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 479:39] - node _T_2590 = and(scnd_miss_req_q, _T_2589) @[ifu_mem_ctl.scala 479:36] - scnd_miss_req <= _T_2590 @[ifu_mem_ctl.scala 479:17] + reg bus_ifu_bus_clk_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 463:61] + bus_ifu_bus_clk_en_ff <= bus_ifu_bus_clk_en @[ifu_mem_ctl.scala 463:61] + reg _T_2588 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 464:52] + _T_2588 <= scnd_miss_req_in @[ifu_mem_ctl.scala 464:52] + scnd_miss_req_q <= _T_2588 @[ifu_mem_ctl.scala 464:19] + reg scnd_miss_req_ff2 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 465:57] + scnd_miss_req_ff2 <= scnd_miss_req @[ifu_mem_ctl.scala 465:57] + node _T_2589 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 466:39] + node _T_2590 = and(scnd_miss_req_q, _T_2589) @[ifu_mem_ctl.scala 466:36] + scnd_miss_req <= _T_2590 @[ifu_mem_ctl.scala 466:17] wire bus_cmd_req_hold : UInt<1> bus_cmd_req_hold <= UInt<1>("h00") wire ifu_bus_cmd_valid : UInt<1> @@ -6295,90 +6275,110 @@ circuit quasar_wrapper : bus_cmd_beat_count <= UInt<1>("h00") wire ifu_bus_cmd_ready : UInt<1> ifu_bus_cmd_ready <= UInt<1>("h00") - node _T_2591 = or(ic_act_miss_f, bus_cmd_req_hold) @[ifu_mem_ctl.scala 484:45] - node _T_2592 = or(_T_2591, ifu_bus_cmd_valid) @[ifu_mem_ctl.scala 484:64] - node _T_2593 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 484:87] - node _T_2594 = and(_T_2592, _T_2593) @[ifu_mem_ctl.scala 484:85] + node _T_2591 = or(ic_act_miss_f, bus_cmd_req_hold) @[ifu_mem_ctl.scala 471:45] + node _T_2592 = or(_T_2591, ifu_bus_cmd_valid) @[ifu_mem_ctl.scala 471:64] + node _T_2593 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 471:87] + node _T_2594 = and(_T_2592, _T_2593) @[ifu_mem_ctl.scala 471:85] node _T_2595 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_2596 = eq(bus_cmd_beat_count, _T_2595) @[ifu_mem_ctl.scala 484:146] - node _T_2597 = and(_T_2596, ifu_bus_cmd_valid) @[ifu_mem_ctl.scala 484:177] - node _T_2598 = and(_T_2597, ifu_bus_cmd_ready) @[ifu_mem_ctl.scala 484:197] - node _T_2599 = and(_T_2598, miss_pending) @[ifu_mem_ctl.scala 484:217] - node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[ifu_mem_ctl.scala 484:125] - node ifc_bus_ic_req_ff_in = and(_T_2594, _T_2600) @[ifu_mem_ctl.scala 484:123] - reg _T_2601 : UInt<1>, rvclkhdr_69.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 485:55] - _T_2601 <= ifc_bus_ic_req_ff_in @[ifu_mem_ctl.scala 485:55] - ifu_bus_cmd_valid <= _T_2601 @[ifu_mem_ctl.scala 485:21] + node _T_2596 = eq(bus_cmd_beat_count, _T_2595) @[ifu_mem_ctl.scala 471:146] + node _T_2597 = and(_T_2596, ifu_bus_cmd_valid) @[ifu_mem_ctl.scala 471:177] + node _T_2598 = and(_T_2597, ifu_bus_cmd_ready) @[ifu_mem_ctl.scala 471:197] + node _T_2599 = and(_T_2598, miss_pending) @[ifu_mem_ctl.scala 471:217] + node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[ifu_mem_ctl.scala 471:125] + node ifc_bus_ic_req_ff_in = and(_T_2594, _T_2600) @[ifu_mem_ctl.scala 471:123] + reg _T_2601 : UInt<1>, rvclkhdr_69.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 472:55] + _T_2601 <= ifc_bus_ic_req_ff_in @[ifu_mem_ctl.scala 472:55] + ifu_bus_cmd_valid <= _T_2601 @[ifu_mem_ctl.scala 472:21] wire bus_cmd_sent : UInt<1> bus_cmd_sent <= UInt<1>("h00") - node _T_2602 = or(ic_act_miss_f, bus_cmd_req_hold) @[ifu_mem_ctl.scala 487:39] - node _T_2603 = eq(bus_cmd_sent, UInt<1>("h00")) @[ifu_mem_ctl.scala 487:61] - node _T_2604 = and(_T_2602, _T_2603) @[ifu_mem_ctl.scala 487:59] - node _T_2605 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 487:77] - node bus_cmd_req_in = and(_T_2604, _T_2605) @[ifu_mem_ctl.scala 487:75] - reg _T_2606 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 488:53] - _T_2606 <= bus_cmd_req_in @[ifu_mem_ctl.scala 488:53] - bus_cmd_req_hold <= _T_2606 @[ifu_mem_ctl.scala 488:20] - io.ifu_axi.ar.valid <= ifu_bus_cmd_valid @[ifu_mem_ctl.scala 490:23] + node _T_2602 = or(ic_act_miss_f, bus_cmd_req_hold) @[ifu_mem_ctl.scala 474:39] + node _T_2603 = eq(bus_cmd_sent, UInt<1>("h00")) @[ifu_mem_ctl.scala 474:61] + node _T_2604 = and(_T_2602, _T_2603) @[ifu_mem_ctl.scala 474:59] + node _T_2605 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 474:77] + node bus_cmd_req_in = and(_T_2604, _T_2605) @[ifu_mem_ctl.scala 474:75] + reg _T_2606 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 475:53] + _T_2606 <= bus_cmd_req_in @[ifu_mem_ctl.scala 475:53] + bus_cmd_req_hold <= _T_2606 @[ifu_mem_ctl.scala 475:20] + io.ifu_axi.w.valid <= UInt<1>("h00") @[ifu_mem_ctl.scala 477:22] + io.ifu_axi.w.bits.data <= UInt<1>("h00") @[ifu_mem_ctl.scala 478:26] + io.ifu_axi.aw.bits.qos <= UInt<1>("h00") @[ifu_mem_ctl.scala 479:26] + io.ifu_axi.aw.bits.addr <= UInt<1>("h00") @[ifu_mem_ctl.scala 480:27] + io.ifu_axi.aw.bits.prot <= UInt<1>("h00") @[ifu_mem_ctl.scala 481:27] + io.ifu_axi.aw.bits.len <= UInt<1>("h00") @[ifu_mem_ctl.scala 482:26] + io.ifu_axi.ar.bits.lock <= UInt<1>("h00") @[ifu_mem_ctl.scala 483:27] + io.ifu_axi.aw.bits.region <= UInt<1>("h00") @[ifu_mem_ctl.scala 484:29] + io.ifu_axi.aw.bits.id <= UInt<1>("h00") @[ifu_mem_ctl.scala 485:25] + io.ifu_axi.aw.valid <= UInt<1>("h00") @[ifu_mem_ctl.scala 486:23] + io.ifu_axi.w.bits.strb <= UInt<1>("h00") @[ifu_mem_ctl.scala 487:26] + io.ifu_axi.aw.bits.cache <= UInt<1>("h00") @[ifu_mem_ctl.scala 488:28] + io.ifu_axi.ar.bits.qos <= UInt<1>("h00") @[ifu_mem_ctl.scala 489:26] + io.ifu_axi.aw.bits.lock <= UInt<1>("h00") @[ifu_mem_ctl.scala 490:27] + io.ifu_axi.b.ready <= UInt<1>("h00") @[ifu_mem_ctl.scala 491:22] + io.ifu_axi.ar.bits.len <= UInt<1>("h00") @[ifu_mem_ctl.scala 492:26] + io.ifu_axi.aw.bits.size <= UInt<1>("h00") @[ifu_mem_ctl.scala 493:27] + io.ifu_axi.ar.bits.prot <= UInt<1>("h00") @[ifu_mem_ctl.scala 494:27] + io.ifu_axi.aw.bits.burst <= UInt<1>("h00") @[ifu_mem_ctl.scala 495:28] + io.ifu_axi.w.bits.last <= UInt<1>("h00") @[ifu_mem_ctl.scala 496:26] + io.ifu_axi.ar.valid <= ifu_bus_cmd_valid @[ifu_mem_ctl.scala 497:23] node _T_2607 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15] node _T_2608 = mux(_T_2607, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_2609 = and(bus_rd_addr_count, _T_2608) @[ifu_mem_ctl.scala 491:46] - io.ifu_axi.ar.bits.id <= _T_2609 @[ifu_mem_ctl.scala 491:25] + node _T_2609 = and(bus_rd_addr_count, _T_2608) @[ifu_mem_ctl.scala 498:46] + io.ifu_axi.ar.bits.id <= _T_2609 @[ifu_mem_ctl.scala 498:25] node _T_2610 = cat(ifu_ic_req_addr_f, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2611 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15] node _T_2612 = mux(_T_2611, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_2613 = and(_T_2610, _T_2612) @[ifu_mem_ctl.scala 492:63] - io.ifu_axi.ar.bits.addr <= _T_2613 @[ifu_mem_ctl.scala 492:27] - io.ifu_axi.ar.bits.size <= UInt<3>("h03") @[ifu_mem_ctl.scala 493:27] - io.ifu_axi.ar.bits.cache <= UInt<4>("h0f") @[ifu_mem_ctl.scala 494:28] - node _T_2614 = bits(ifu_ic_req_addr_f, 28, 25) @[ifu_mem_ctl.scala 495:49] - io.ifu_axi.ar.bits.region <= _T_2614 @[ifu_mem_ctl.scala 495:29] - io.ifu_axi.ar.bits.burst <= UInt<1>("h01") @[ifu_mem_ctl.scala 496:28] - io.ifu_axi.r.ready <= UInt<1>("h01") @[ifu_mem_ctl.scala 497:22] - reg ifu_bus_arready_unq_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 503:57] - ifu_bus_arready_unq_ff <= io.ifu_axi.ar.ready @[ifu_mem_ctl.scala 503:57] - reg ifu_bus_rvalid_unq_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 504:56] - ifu_bus_rvalid_unq_ff <= io.ifu_axi.r.valid @[ifu_mem_ctl.scala 504:56] - reg ifu_bus_arvalid_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 505:53] - ifu_bus_arvalid_ff <= io.ifu_axi.ar.valid @[ifu_mem_ctl.scala 505:53] - reg ifu_bus_rresp_ff : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 506:51] - ifu_bus_rresp_ff <= io.ifu_axi.r.bits.resp @[ifu_mem_ctl.scala 506:51] - reg _T_2615 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 507:48] - _T_2615 <= io.ifu_axi.r.bits.data @[ifu_mem_ctl.scala 507:48] - ifu_bus_rdata_ff <= _T_2615 @[ifu_mem_ctl.scala 507:20] - reg _T_2616 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 508:46] - _T_2616 <= io.ifu_axi.r.bits.id @[ifu_mem_ctl.scala 508:46] - ifu_bus_rid_ff <= _T_2616 @[ifu_mem_ctl.scala 508:18] - ifu_bus_cmd_ready <= io.ifu_axi.ar.ready @[ifu_mem_ctl.scala 509:21] - ifu_bus_rsp_valid <= io.ifu_axi.r.valid @[ifu_mem_ctl.scala 510:21] - ifu_bus_rsp_ready <= io.ifu_axi.r.ready @[ifu_mem_ctl.scala 511:21] - ifu_bus_rsp_tag <= io.ifu_axi.r.bits.id @[ifu_mem_ctl.scala 512:19] - ic_miss_buff_data_in <= io.ifu_axi.r.bits.data @[ifu_mem_ctl.scala 513:21] - node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[ifu_mem_ctl.scala 515:42] - node ifu_bus_arready = and(io.ifu_axi.ar.ready, bus_ifu_bus_clk_en) @[ifu_mem_ctl.scala 516:45] - node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[ifu_mem_ctl.scala 517:51] - node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[ifu_mem_ctl.scala 518:49] - node _T_2617 = and(io.ifu_axi.ar.valid, ifu_bus_arready) @[ifu_mem_ctl.scala 519:35] - node _T_2618 = and(_T_2617, miss_pending) @[ifu_mem_ctl.scala 519:53] - node _T_2619 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 519:70] - node _T_2620 = and(_T_2618, _T_2619) @[ifu_mem_ctl.scala 519:68] - bus_cmd_sent <= _T_2620 @[ifu_mem_ctl.scala 519:16] + node _T_2613 = and(_T_2610, _T_2612) @[ifu_mem_ctl.scala 499:63] + io.ifu_axi.ar.bits.addr <= _T_2613 @[ifu_mem_ctl.scala 499:27] + io.ifu_axi.ar.bits.size <= UInt<3>("h03") @[ifu_mem_ctl.scala 500:27] + io.ifu_axi.ar.bits.cache <= UInt<4>("h0f") @[ifu_mem_ctl.scala 501:28] + node _T_2614 = bits(ifu_ic_req_addr_f, 28, 25) @[ifu_mem_ctl.scala 502:49] + io.ifu_axi.ar.bits.region <= _T_2614 @[ifu_mem_ctl.scala 502:29] + io.ifu_axi.ar.bits.burst <= UInt<1>("h01") @[ifu_mem_ctl.scala 503:28] + io.ifu_axi.r.ready <= UInt<1>("h01") @[ifu_mem_ctl.scala 504:22] + reg ifu_bus_arready_unq_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 510:57] + ifu_bus_arready_unq_ff <= io.ifu_axi.ar.ready @[ifu_mem_ctl.scala 510:57] + reg ifu_bus_rvalid_unq_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 511:56] + ifu_bus_rvalid_unq_ff <= io.ifu_axi.r.valid @[ifu_mem_ctl.scala 511:56] + reg ifu_bus_arvalid_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 512:53] + ifu_bus_arvalid_ff <= io.ifu_axi.ar.valid @[ifu_mem_ctl.scala 512:53] + reg ifu_bus_rresp_ff : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 513:51] + ifu_bus_rresp_ff <= io.ifu_axi.r.bits.resp @[ifu_mem_ctl.scala 513:51] + reg _T_2615 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 514:48] + _T_2615 <= io.ifu_axi.r.bits.data @[ifu_mem_ctl.scala 514:48] + ifu_bus_rdata_ff <= _T_2615 @[ifu_mem_ctl.scala 514:20] + reg _T_2616 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 515:46] + _T_2616 <= io.ifu_axi.r.bits.id @[ifu_mem_ctl.scala 515:46] + ifu_bus_rid_ff <= _T_2616 @[ifu_mem_ctl.scala 515:18] + ifu_bus_cmd_ready <= io.ifu_axi.ar.ready @[ifu_mem_ctl.scala 516:21] + ifu_bus_rsp_valid <= io.ifu_axi.r.valid @[ifu_mem_ctl.scala 517:21] + ifu_bus_rsp_ready <= io.ifu_axi.r.ready @[ifu_mem_ctl.scala 518:21] + ifu_bus_rsp_tag <= io.ifu_axi.r.bits.id @[ifu_mem_ctl.scala 519:19] + ic_miss_buff_data_in <= io.ifu_axi.r.bits.data @[ifu_mem_ctl.scala 520:21] + node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[ifu_mem_ctl.scala 522:42] + node ifu_bus_arready = and(io.ifu_axi.ar.ready, bus_ifu_bus_clk_en) @[ifu_mem_ctl.scala 523:45] + node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[ifu_mem_ctl.scala 524:51] + node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[ifu_mem_ctl.scala 525:49] + node _T_2617 = and(io.ifu_axi.ar.valid, ifu_bus_arready) @[ifu_mem_ctl.scala 527:35] + node _T_2618 = and(_T_2617, miss_pending) @[ifu_mem_ctl.scala 527:53] + node _T_2619 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 527:70] + node _T_2620 = and(_T_2618, _T_2619) @[ifu_mem_ctl.scala 527:68] + bus_cmd_sent <= _T_2620 @[ifu_mem_ctl.scala 527:16] wire bus_last_data_beat : UInt<1> bus_last_data_beat <= UInt<1>("h00") - node _T_2621 = eq(bus_last_data_beat, UInt<1>("h00")) @[ifu_mem_ctl.scala 521:50] - node _T_2622 = and(bus_ifu_wr_en_ff, _T_2621) @[ifu_mem_ctl.scala 521:48] - node _T_2623 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 521:72] - node bus_inc_data_beat_cnt = and(_T_2622, _T_2623) @[ifu_mem_ctl.scala 521:70] - node _T_2624 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[ifu_mem_ctl.scala 522:68] - node _T_2625 = or(ic_act_miss_f, _T_2624) @[ifu_mem_ctl.scala 522:48] - node bus_reset_data_beat_cnt = or(_T_2625, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 522:91] - node _T_2626 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 523:32] - node _T_2627 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 523:57] - node bus_hold_data_beat_cnt = and(_T_2626, _T_2627) @[ifu_mem_ctl.scala 523:55] + node _T_2621 = eq(bus_last_data_beat, UInt<1>("h00")) @[ifu_mem_ctl.scala 529:50] + node _T_2622 = and(bus_ifu_wr_en_ff, _T_2621) @[ifu_mem_ctl.scala 529:48] + node _T_2623 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 529:72] + node bus_inc_data_beat_cnt = and(_T_2622, _T_2623) @[ifu_mem_ctl.scala 529:70] + node _T_2624 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[ifu_mem_ctl.scala 530:68] + node _T_2625 = or(ic_act_miss_f, _T_2624) @[ifu_mem_ctl.scala 530:48] + node bus_reset_data_beat_cnt = or(_T_2625, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 530:91] + node _T_2626 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 531:32] + node _T_2627 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 531:57] + node bus_hold_data_beat_cnt = and(_T_2626, _T_2627) @[ifu_mem_ctl.scala 531:55] wire bus_data_beat_count : UInt<3> bus_data_beat_count <= UInt<1>("h00") - node _T_2628 = add(bus_data_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 525:115] - node _T_2629 = tail(_T_2628, 1) @[ifu_mem_ctl.scala 525:115] + node _T_2628 = add(bus_data_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 533:115] + node _T_2629 = tail(_T_2628, 1) @[ifu_mem_ctl.scala 533:115] node _T_2630 = mux(bus_reset_data_beat_cnt, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2631 = mux(bus_inc_data_beat_cnt, _T_2629, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2632 = mux(bus_hold_data_beat_cnt, bus_data_beat_count, UInt<1>("h00")) @[Mux.scala 27:72] @@ -6386,48 +6386,48 @@ circuit quasar_wrapper : node _T_2634 = or(_T_2633, _T_2632) @[Mux.scala 27:72] wire _T_2635 : UInt<3> @[Mux.scala 27:72] _T_2635 <= _T_2634 @[Mux.scala 27:72] - bus_new_data_beat_count <= _T_2635 @[ifu_mem_ctl.scala 525:27] - reg _T_2636 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 526:56] - _T_2636 <= bus_new_data_beat_count @[ifu_mem_ctl.scala 526:56] - bus_data_beat_count <= _T_2636 @[ifu_mem_ctl.scala 526:23] - node _T_2637 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[ifu_mem_ctl.scala 527:49] - node _T_2638 = eq(scnd_miss_req, UInt<1>("h00")) @[ifu_mem_ctl.scala 527:73] - node _T_2639 = and(_T_2637, _T_2638) @[ifu_mem_ctl.scala 527:71] - node _T_2640 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 527:116] - node _T_2641 = and(last_data_recieved_ff, _T_2640) @[ifu_mem_ctl.scala 527:114] - node last_data_recieved_in = or(_T_2639, _T_2641) @[ifu_mem_ctl.scala 527:89] - reg _T_2642 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 528:58] - _T_2642 <= last_data_recieved_in @[ifu_mem_ctl.scala 528:58] - last_data_recieved_ff <= _T_2642 @[ifu_mem_ctl.scala 528:25] - node _T_2643 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 530:35] - node _T_2644 = bits(imb_ff, 4, 2) @[ifu_mem_ctl.scala 530:56] - node _T_2645 = bits(imb_scnd_ff, 4, 2) @[ifu_mem_ctl.scala 531:39] - node _T_2646 = add(bus_rd_addr_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 532:45] - node _T_2647 = tail(_T_2646, 1) @[ifu_mem_ctl.scala 532:45] - node _T_2648 = mux(bus_cmd_sent, _T_2647, bus_rd_addr_count) @[ifu_mem_ctl.scala 532:12] - node _T_2649 = mux(scnd_miss_req_q, _T_2645, _T_2648) @[ifu_mem_ctl.scala 531:10] - node bus_new_rd_addr_count = mux(_T_2643, _T_2644, _T_2649) @[ifu_mem_ctl.scala 530:34] - reg _T_2650 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 533:55] - _T_2650 <= bus_new_rd_addr_count @[ifu_mem_ctl.scala 533:55] - bus_rd_addr_count <= _T_2650 @[ifu_mem_ctl.scala 533:21] - node _T_2651 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[ifu_mem_ctl.scala 535:48] - node _T_2652 = and(_T_2651, miss_pending) @[ifu_mem_ctl.scala 535:68] - node _T_2653 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 535:85] - node bus_inc_cmd_beat_cnt = and(_T_2652, _T_2653) @[ifu_mem_ctl.scala 535:83] - node _T_2654 = eq(uncacheable_miss_in, UInt<1>("h00")) @[ifu_mem_ctl.scala 536:51] - node _T_2655 = and(ic_act_miss_f, _T_2654) @[ifu_mem_ctl.scala 536:49] - node bus_reset_cmd_beat_cnt_0 = or(_T_2655, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 536:73] - node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[ifu_mem_ctl.scala 537:57] - node _T_2656 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 538:31] - node _T_2657 = or(ic_act_miss_f, scnd_miss_req) @[ifu_mem_ctl.scala 538:71] - node _T_2658 = or(_T_2657, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 538:87] - node _T_2659 = eq(_T_2658, UInt<1>("h00")) @[ifu_mem_ctl.scala 538:55] - node bus_hold_cmd_beat_cnt = and(_T_2656, _T_2659) @[ifu_mem_ctl.scala 538:53] - node _T_2660 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[ifu_mem_ctl.scala 539:46] - node bus_cmd_beat_en = or(_T_2660, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 539:62] - node _T_2661 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[ifu_mem_ctl.scala 540:107] - node _T_2662 = add(bus_cmd_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 541:46] - node _T_2663 = tail(_T_2662, 1) @[ifu_mem_ctl.scala 541:46] + bus_new_data_beat_count <= _T_2635 @[ifu_mem_ctl.scala 533:27] + reg _T_2636 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 534:56] + _T_2636 <= bus_new_data_beat_count @[ifu_mem_ctl.scala 534:56] + bus_data_beat_count <= _T_2636 @[ifu_mem_ctl.scala 534:23] + node _T_2637 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[ifu_mem_ctl.scala 535:49] + node _T_2638 = eq(scnd_miss_req, UInt<1>("h00")) @[ifu_mem_ctl.scala 535:73] + node _T_2639 = and(_T_2637, _T_2638) @[ifu_mem_ctl.scala 535:71] + node _T_2640 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 535:116] + node _T_2641 = and(last_data_recieved_ff, _T_2640) @[ifu_mem_ctl.scala 535:114] + node last_data_recieved_in = or(_T_2639, _T_2641) @[ifu_mem_ctl.scala 535:89] + reg _T_2642 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 536:58] + _T_2642 <= last_data_recieved_in @[ifu_mem_ctl.scala 536:58] + last_data_recieved_ff <= _T_2642 @[ifu_mem_ctl.scala 536:25] + node _T_2643 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 538:35] + node _T_2644 = bits(imb_ff, 4, 2) @[ifu_mem_ctl.scala 538:56] + node _T_2645 = bits(imb_scnd_ff, 4, 2) @[ifu_mem_ctl.scala 539:39] + node _T_2646 = add(bus_rd_addr_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 540:45] + node _T_2647 = tail(_T_2646, 1) @[ifu_mem_ctl.scala 540:45] + node _T_2648 = mux(bus_cmd_sent, _T_2647, bus_rd_addr_count) @[ifu_mem_ctl.scala 540:12] + node _T_2649 = mux(scnd_miss_req_q, _T_2645, _T_2648) @[ifu_mem_ctl.scala 539:10] + node bus_new_rd_addr_count = mux(_T_2643, _T_2644, _T_2649) @[ifu_mem_ctl.scala 538:34] + reg _T_2650 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 541:55] + _T_2650 <= bus_new_rd_addr_count @[ifu_mem_ctl.scala 541:55] + bus_rd_addr_count <= _T_2650 @[ifu_mem_ctl.scala 541:21] + node _T_2651 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[ifu_mem_ctl.scala 543:48] + node _T_2652 = and(_T_2651, miss_pending) @[ifu_mem_ctl.scala 543:68] + node _T_2653 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 543:85] + node bus_inc_cmd_beat_cnt = and(_T_2652, _T_2653) @[ifu_mem_ctl.scala 543:83] + node _T_2654 = eq(uncacheable_miss_in, UInt<1>("h00")) @[ifu_mem_ctl.scala 544:51] + node _T_2655 = and(ic_act_miss_f, _T_2654) @[ifu_mem_ctl.scala 544:49] + node bus_reset_cmd_beat_cnt_0 = or(_T_2655, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 544:73] + node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[ifu_mem_ctl.scala 545:57] + node _T_2656 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 546:31] + node _T_2657 = or(ic_act_miss_f, scnd_miss_req) @[ifu_mem_ctl.scala 546:71] + node _T_2658 = or(_T_2657, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 546:87] + node _T_2659 = eq(_T_2658, UInt<1>("h00")) @[ifu_mem_ctl.scala 546:55] + node bus_hold_cmd_beat_cnt = and(_T_2656, _T_2659) @[ifu_mem_ctl.scala 546:53] + node _T_2660 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[ifu_mem_ctl.scala 547:46] + node bus_cmd_beat_en = or(_T_2660, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 547:62] + node _T_2661 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[ifu_mem_ctl.scala 548:107] + node _T_2662 = add(bus_cmd_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 549:46] + node _T_2663 = tail(_T_2662, 1) @[ifu_mem_ctl.scala 549:46] node _T_2664 = mux(bus_reset_cmd_beat_cnt_0, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2665 = mux(_T_2661, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2666 = mux(bus_inc_cmd_beat_cnt, _T_2663, UInt<1>("h00")) @[Mux.scala 27:72] @@ -6441,84 +6441,84 @@ circuit quasar_wrapper : when bus_cmd_beat_en : @[Reg.scala 28:19] _T_2671 <= bus_new_cmd_beat_count @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bus_cmd_beat_count <= _T_2671 @[ifu_mem_ctl.scala 542:22] - node _T_2672 = eq(bus_data_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 543:69] - node _T_2673 = andr(bus_data_beat_count) @[ifu_mem_ctl.scala 543:101] - node _T_2674 = mux(uncacheable_miss_ff, _T_2672, _T_2673) @[ifu_mem_ctl.scala 543:28] - bus_last_data_beat <= _T_2674 @[ifu_mem_ctl.scala 543:22] - node _T_2675 = and(ifu_bus_rvalid, miss_pending) @[ifu_mem_ctl.scala 544:35] - bus_ifu_wr_en <= _T_2675 @[ifu_mem_ctl.scala 544:17] - node _T_2676 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 545:41] - bus_ifu_wr_en_ff <= _T_2676 @[ifu_mem_ctl.scala 545:20] - node _T_2677 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 546:44] - node _T_2678 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 546:61] - node _T_2679 = and(_T_2677, _T_2678) @[ifu_mem_ctl.scala 546:59] - node _T_2680 = orr(ifu_bus_rresp_ff) @[ifu_mem_ctl.scala 546:103] - node _T_2681 = eq(_T_2680, UInt<1>("h00")) @[ifu_mem_ctl.scala 546:84] - node _T_2682 = and(_T_2679, _T_2681) @[ifu_mem_ctl.scala 546:82] - node _T_2683 = and(_T_2682, write_ic_16_bytes) @[ifu_mem_ctl.scala 546:108] - bus_ifu_wr_en_ff_q <= _T_2683 @[ifu_mem_ctl.scala 546:22] - node _T_2684 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 547:51] - node _T_2685 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 547:68] - node bus_ifu_wr_en_ff_wo_err = and(_T_2684, _T_2685) @[ifu_mem_ctl.scala 547:66] - reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 548:61] - ic_act_miss_f_delayed <= ic_act_miss_f @[ifu_mem_ctl.scala 548:61] - node _T_2686 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 549:66] - node _T_2687 = and(ic_act_miss_f_delayed, _T_2686) @[ifu_mem_ctl.scala 549:53] - node _T_2688 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 549:86] - node _T_2689 = and(_T_2687, _T_2688) @[ifu_mem_ctl.scala 549:84] - reset_tag_valid_for_miss <= _T_2689 @[ifu_mem_ctl.scala 549:28] - node _T_2690 = orr(io.ifu_axi.r.bits.resp) @[ifu_mem_ctl.scala 550:47] - node _T_2691 = and(_T_2690, ifu_bus_rvalid) @[ifu_mem_ctl.scala 550:50] - node _T_2692 = and(_T_2691, miss_pending) @[ifu_mem_ctl.scala 550:68] - bus_ifu_wr_data_error <= _T_2692 @[ifu_mem_ctl.scala 550:25] - node _T_2693 = orr(ifu_bus_rresp_ff) @[ifu_mem_ctl.scala 551:48] - node _T_2694 = and(_T_2693, ifu_bus_rvalid_ff) @[ifu_mem_ctl.scala 551:52] - node _T_2695 = and(_T_2694, miss_pending) @[ifu_mem_ctl.scala 551:73] - bus_ifu_wr_data_error_ff <= _T_2695 @[ifu_mem_ctl.scala 551:28] + bus_cmd_beat_count <= _T_2671 @[ifu_mem_ctl.scala 550:22] + node _T_2672 = eq(bus_data_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 551:69] + node _T_2673 = andr(bus_data_beat_count) @[ifu_mem_ctl.scala 551:101] + node _T_2674 = mux(uncacheable_miss_ff, _T_2672, _T_2673) @[ifu_mem_ctl.scala 551:28] + bus_last_data_beat <= _T_2674 @[ifu_mem_ctl.scala 551:22] + node _T_2675 = and(ifu_bus_rvalid, miss_pending) @[ifu_mem_ctl.scala 552:35] + bus_ifu_wr_en <= _T_2675 @[ifu_mem_ctl.scala 552:17] + node _T_2676 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 553:41] + bus_ifu_wr_en_ff <= _T_2676 @[ifu_mem_ctl.scala 553:20] + node _T_2677 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 554:44] + node _T_2678 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 554:61] + node _T_2679 = and(_T_2677, _T_2678) @[ifu_mem_ctl.scala 554:59] + node _T_2680 = orr(ifu_bus_rresp_ff) @[ifu_mem_ctl.scala 554:103] + node _T_2681 = eq(_T_2680, UInt<1>("h00")) @[ifu_mem_ctl.scala 554:84] + node _T_2682 = and(_T_2679, _T_2681) @[ifu_mem_ctl.scala 554:82] + node _T_2683 = and(_T_2682, write_ic_16_bytes) @[ifu_mem_ctl.scala 554:108] + bus_ifu_wr_en_ff_q <= _T_2683 @[ifu_mem_ctl.scala 554:22] + node _T_2684 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 555:51] + node _T_2685 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 555:68] + node bus_ifu_wr_en_ff_wo_err = and(_T_2684, _T_2685) @[ifu_mem_ctl.scala 555:66] + reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 556:61] + ic_act_miss_f_delayed <= ic_act_miss_f @[ifu_mem_ctl.scala 556:61] + node _T_2686 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 557:66] + node _T_2687 = and(ic_act_miss_f_delayed, _T_2686) @[ifu_mem_ctl.scala 557:53] + node _T_2688 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 557:86] + node _T_2689 = and(_T_2687, _T_2688) @[ifu_mem_ctl.scala 557:84] + reset_tag_valid_for_miss <= _T_2689 @[ifu_mem_ctl.scala 557:28] + node _T_2690 = orr(io.ifu_axi.r.bits.resp) @[ifu_mem_ctl.scala 558:47] + node _T_2691 = and(_T_2690, ifu_bus_rvalid) @[ifu_mem_ctl.scala 558:50] + node _T_2692 = and(_T_2691, miss_pending) @[ifu_mem_ctl.scala 558:68] + bus_ifu_wr_data_error <= _T_2692 @[ifu_mem_ctl.scala 558:25] + node _T_2693 = orr(ifu_bus_rresp_ff) @[ifu_mem_ctl.scala 559:48] + node _T_2694 = and(_T_2693, ifu_bus_rvalid_ff) @[ifu_mem_ctl.scala 559:52] + node _T_2695 = and(_T_2694, miss_pending) @[ifu_mem_ctl.scala 559:73] + bus_ifu_wr_data_error_ff <= _T_2695 @[ifu_mem_ctl.scala 559:28] wire ifc_dma_access_ok_d : UInt<1> ifc_dma_access_ok_d <= UInt<1>("h00") - reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 553:62] - ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[ifu_mem_ctl.scala 553:62] - node _T_2696 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[ifu_mem_ctl.scala 554:43] - ic_crit_wd_rdy <= _T_2696 @[ifu_mem_ctl.scala 554:18] - node _T_2697 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[ifu_mem_ctl.scala 555:35] - last_beat <= _T_2697 @[ifu_mem_ctl.scala 555:13] - reset_beat_cnt <= bus_reset_data_beat_cnt @[ifu_mem_ctl.scala 556:18] - node _T_2698 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 558:50] - node _T_2699 = and(io.ifc_dma_access_ok, _T_2698) @[ifu_mem_ctl.scala 558:47] - node _T_2700 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[ifu_mem_ctl.scala 558:70] - node _T_2701 = and(_T_2699, _T_2700) @[ifu_mem_ctl.scala 558:68] - ifc_dma_access_ok_d <= _T_2701 @[ifu_mem_ctl.scala 558:23] - node _T_2702 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 559:54] - node _T_2703 = and(io.ifc_dma_access_ok, _T_2702) @[ifu_mem_ctl.scala 559:51] - node _T_2704 = and(_T_2703, ifc_dma_access_ok_prev) @[ifu_mem_ctl.scala 559:72] - node _T_2705 = eq(perr_state, UInt<3>("h00")) @[ifu_mem_ctl.scala 559:111] - node _T_2706 = and(_T_2704, _T_2705) @[ifu_mem_ctl.scala 559:97] - node _T_2707 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[ifu_mem_ctl.scala 559:129] - node ifc_dma_access_q_ok = and(_T_2706, _T_2707) @[ifu_mem_ctl.scala 559:127] - io.iccm_ready <= ifc_dma_access_q_ok @[ifu_mem_ctl.scala 560:17] - reg _T_2708 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 561:51] - _T_2708 <= io.dma_mem_ctl.dma_iccm_req @[ifu_mem_ctl.scala 561:51] - dma_iccm_req_f <= _T_2708 @[ifu_mem_ctl.scala 561:18] - node _T_2709 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 562:40] - node _T_2710 = and(_T_2709, io.dma_mem_ctl.dma_mem_write) @[ifu_mem_ctl.scala 562:70] - node _T_2711 = or(_T_2710, iccm_correct_ecc) @[ifu_mem_ctl.scala 562:103] - io.iccm.wren <= _T_2711 @[ifu_mem_ctl.scala 562:16] - node _T_2712 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 563:40] - node _T_2713 = eq(io.dma_mem_ctl.dma_mem_write, UInt<1>("h00")) @[ifu_mem_ctl.scala 563:72] - node _T_2714 = and(_T_2712, _T_2713) @[ifu_mem_ctl.scala 563:70] - node _T_2715 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[ifu_mem_ctl.scala 563:128] - node _T_2716 = or(_T_2714, _T_2715) @[ifu_mem_ctl.scala 563:103] - io.iccm.rden <= _T_2716 @[ifu_mem_ctl.scala 563:16] - node _T_2717 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 564:43] - node _T_2718 = eq(io.dma_mem_ctl.dma_mem_write, UInt<1>("h00")) @[ifu_mem_ctl.scala 564:75] - node iccm_dma_rden = and(_T_2717, _T_2718) @[ifu_mem_ctl.scala 564:73] + reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 561:62] + ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[ifu_mem_ctl.scala 561:62] + node _T_2696 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[ifu_mem_ctl.scala 562:43] + ic_crit_wd_rdy <= _T_2696 @[ifu_mem_ctl.scala 562:18] + node _T_2697 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[ifu_mem_ctl.scala 563:35] + last_beat <= _T_2697 @[ifu_mem_ctl.scala 563:13] + reset_beat_cnt <= bus_reset_data_beat_cnt @[ifu_mem_ctl.scala 564:18] + node _T_2698 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 566:50] + node _T_2699 = and(io.ifc_dma_access_ok, _T_2698) @[ifu_mem_ctl.scala 566:47] + node _T_2700 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[ifu_mem_ctl.scala 566:70] + node _T_2701 = and(_T_2699, _T_2700) @[ifu_mem_ctl.scala 566:68] + ifc_dma_access_ok_d <= _T_2701 @[ifu_mem_ctl.scala 566:23] + node _T_2702 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 567:54] + node _T_2703 = and(io.ifc_dma_access_ok, _T_2702) @[ifu_mem_ctl.scala 567:51] + node _T_2704 = and(_T_2703, ifc_dma_access_ok_prev) @[ifu_mem_ctl.scala 567:72] + node _T_2705 = eq(perr_state, UInt<3>("h00")) @[ifu_mem_ctl.scala 567:111] + node _T_2706 = and(_T_2704, _T_2705) @[ifu_mem_ctl.scala 567:97] + node _T_2707 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[ifu_mem_ctl.scala 567:129] + node ifc_dma_access_q_ok = and(_T_2706, _T_2707) @[ifu_mem_ctl.scala 567:127] + io.iccm_ready <= ifc_dma_access_q_ok @[ifu_mem_ctl.scala 568:17] + reg _T_2708 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 569:51] + _T_2708 <= io.dma_mem_ctl.dma_iccm_req @[ifu_mem_ctl.scala 569:51] + dma_iccm_req_f <= _T_2708 @[ifu_mem_ctl.scala 569:18] + node _T_2709 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 570:40] + node _T_2710 = and(_T_2709, io.dma_mem_ctl.dma_mem_write) @[ifu_mem_ctl.scala 570:70] + node _T_2711 = or(_T_2710, iccm_correct_ecc) @[ifu_mem_ctl.scala 570:103] + io.iccm.wren <= _T_2711 @[ifu_mem_ctl.scala 570:16] + node _T_2712 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 571:40] + node _T_2713 = eq(io.dma_mem_ctl.dma_mem_write, UInt<1>("h00")) @[ifu_mem_ctl.scala 571:72] + node _T_2714 = and(_T_2712, _T_2713) @[ifu_mem_ctl.scala 571:70] + node _T_2715 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[ifu_mem_ctl.scala 571:128] + node _T_2716 = or(_T_2714, _T_2715) @[ifu_mem_ctl.scala 571:103] + io.iccm.rden <= _T_2716 @[ifu_mem_ctl.scala 571:16] + node _T_2717 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 572:43] + node _T_2718 = eq(io.dma_mem_ctl.dma_mem_write, UInt<1>("h00")) @[ifu_mem_ctl.scala 572:75] + node iccm_dma_rden = and(_T_2717, _T_2718) @[ifu_mem_ctl.scala 572:73] node _T_2719 = bits(io.dma_mem_ctl.dma_iccm_req, 0, 0) @[Bitwise.scala 72:15] node _T_2720 = mux(_T_2719, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_2721 = and(_T_2720, io.dma_mem_ctl.dma_mem_sz) @[ifu_mem_ctl.scala 565:59] - io.iccm.wr_size <= _T_2721 @[ifu_mem_ctl.scala 565:19] - node _T_2722 = bits(io.dma_mem_ctl.dma_mem_wdata, 63, 32) @[ifu_mem_ctl.scala 567:66] + node _T_2721 = and(_T_2720, io.dma_mem_ctl.dma_mem_sz) @[ifu_mem_ctl.scala 573:59] + io.iccm.wr_size <= _T_2721 @[ifu_mem_ctl.scala 573:19] + node _T_2722 = bits(io.dma_mem_ctl.dma_mem_wdata, 63, 32) @[ifu_mem_ctl.scala 575:66] node _T_2723 = bits(_T_2722, 0, 0) @[lib.scala 103:58] node _T_2724 = bits(_T_2722, 1, 1) @[lib.scala 103:58] node _T_2725 = bits(_T_2722, 3, 3) @[lib.scala 103:58] @@ -6702,7 +6702,7 @@ circuit quasar_wrapper : node _T_2903 = xorr(_T_2901) @[lib.scala 111:23] node _T_2904 = xor(_T_2902, _T_2903) @[lib.scala 111:18] node _T_2905 = cat(_T_2904, _T_2901) @[Cat.scala 29:58] - node _T_2906 = bits(io.dma_mem_ctl.dma_mem_wdata, 31, 0) @[ifu_mem_ctl.scala 567:117] + node _T_2906 = bits(io.dma_mem_ctl.dma_mem_wdata, 31, 0) @[ifu_mem_ctl.scala 575:117] node _T_2907 = bits(_T_2906, 0, 0) @[lib.scala 103:58] node _T_2908 = bits(_T_2906, 1, 1) @[lib.scala 103:58] node _T_2909 = bits(_T_2906, 3, 3) @[lib.scala 103:58] @@ -6889,90 +6889,90 @@ circuit quasar_wrapper : node dma_mem_ecc = cat(_T_2905, _T_3089) @[Cat.scala 29:58] wire iccm_ecc_corr_data_ff : UInt<39> iccm_ecc_corr_data_ff <= UInt<1>("h00") - node _T_3090 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 569:67] - node _T_3091 = eq(_T_3090, UInt<1>("h00")) @[ifu_mem_ctl.scala 569:45] - node _T_3092 = and(iccm_correct_ecc, _T_3091) @[ifu_mem_ctl.scala 569:43] + node _T_3090 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 577:67] + node _T_3091 = eq(_T_3090, UInt<1>("h00")) @[ifu_mem_ctl.scala 577:45] + node _T_3092 = and(iccm_correct_ecc, _T_3091) @[ifu_mem_ctl.scala 577:43] node _T_3093 = cat(iccm_ecc_corr_data_ff, iccm_ecc_corr_data_ff) @[Cat.scala 29:58] - node _T_3094 = bits(dma_mem_ecc, 13, 7) @[ifu_mem_ctl.scala 570:20] - node _T_3095 = bits(io.dma_mem_ctl.dma_mem_wdata, 63, 32) @[ifu_mem_ctl.scala 570:55] - node _T_3096 = bits(dma_mem_ecc, 6, 0) @[ifu_mem_ctl.scala 570:75] - node _T_3097 = bits(io.dma_mem_ctl.dma_mem_wdata, 31, 0) @[ifu_mem_ctl.scala 570:110] + node _T_3094 = bits(dma_mem_ecc, 13, 7) @[ifu_mem_ctl.scala 578:20] + node _T_3095 = bits(io.dma_mem_ctl.dma_mem_wdata, 63, 32) @[ifu_mem_ctl.scala 578:55] + node _T_3096 = bits(dma_mem_ecc, 6, 0) @[ifu_mem_ctl.scala 578:75] + node _T_3097 = bits(io.dma_mem_ctl.dma_mem_wdata, 31, 0) @[ifu_mem_ctl.scala 578:110] node _T_3098 = cat(_T_3096, _T_3097) @[Cat.scala 29:58] node _T_3099 = cat(_T_3094, _T_3095) @[Cat.scala 29:58] node _T_3100 = cat(_T_3099, _T_3098) @[Cat.scala 29:58] - node _T_3101 = mux(_T_3092, _T_3093, _T_3100) @[ifu_mem_ctl.scala 569:25] - io.iccm.wr_data <= _T_3101 @[ifu_mem_ctl.scala 569:19] - wire iccm_corrected_data : UInt<32>[2] @[ifu_mem_ctl.scala 571:33] - iccm_corrected_data[0] <= UInt<1>("h00") @[ifu_mem_ctl.scala 572:26] - iccm_corrected_data[1] <= UInt<1>("h00") @[ifu_mem_ctl.scala 573:26] + node _T_3101 = mux(_T_3092, _T_3093, _T_3100) @[ifu_mem_ctl.scala 577:25] + io.iccm.wr_data <= _T_3101 @[ifu_mem_ctl.scala 577:19] + wire iccm_corrected_data : UInt<32>[2] @[ifu_mem_ctl.scala 579:33] + iccm_corrected_data[0] <= UInt<1>("h00") @[ifu_mem_ctl.scala 580:26] + iccm_corrected_data[1] <= UInt<1>("h00") @[ifu_mem_ctl.scala 581:26] wire dma_mem_addr_ff : UInt<2> dma_mem_addr_ff <= UInt<1>("h00") - node _T_3102 = bits(dma_mem_addr_ff, 0, 0) @[ifu_mem_ctl.scala 575:51] - node _T_3103 = bits(_T_3102, 0, 0) @[ifu_mem_ctl.scala 575:55] - node iccm_dma_rdata_1_muxed = mux(_T_3103, iccm_corrected_data[0], iccm_corrected_data[1]) @[ifu_mem_ctl.scala 575:35] + node _T_3102 = bits(dma_mem_addr_ff, 0, 0) @[ifu_mem_ctl.scala 583:51] + node _T_3103 = bits(_T_3102, 0, 0) @[ifu_mem_ctl.scala 583:55] + node iccm_dma_rdata_1_muxed = mux(_T_3103, iccm_corrected_data[0], iccm_corrected_data[1]) @[ifu_mem_ctl.scala 583:35] wire iccm_double_ecc_error : UInt<2> iccm_double_ecc_error <= UInt<1>("h00") - node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[ifu_mem_ctl.scala 577:53] + node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[ifu_mem_ctl.scala 585:53] node _T_3104 = cat(io.dma_mem_ctl.dma_mem_addr, io.dma_mem_ctl.dma_mem_addr) @[Cat.scala 29:58] node _T_3105 = cat(iccm_dma_rdata_1_muxed, iccm_corrected_data[0]) @[Cat.scala 29:58] - node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3104, _T_3105) @[ifu_mem_ctl.scala 578:30] - reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 579:54] - dma_mem_tag_ff <= io.dma_mem_ctl.dma_mem_tag @[ifu_mem_ctl.scala 579:54] - reg iccm_dma_rtag_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 580:74] - iccm_dma_rtag_temp <= dma_mem_tag_ff @[ifu_mem_ctl.scala 580:74] - io.iccm_dma_rtag <= iccm_dma_rtag_temp @[ifu_mem_ctl.scala 581:20] - node _T_3106 = bits(io.dma_mem_ctl.dma_mem_addr, 3, 2) @[ifu_mem_ctl.scala 583:81] - reg _T_3107 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 583:53] - _T_3107 <= _T_3106 @[ifu_mem_ctl.scala 583:53] - dma_mem_addr_ff <= _T_3107 @[ifu_mem_ctl.scala 583:19] - reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 584:59] - iccm_dma_rvalid_in <= iccm_dma_rden @[ifu_mem_ctl.scala 584:59] - reg iccm_dma_rvalid_temp : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 585:76] - iccm_dma_rvalid_temp <= iccm_dma_rvalid_in @[ifu_mem_ctl.scala 585:76] - io.iccm_dma_rvalid <= iccm_dma_rvalid_temp @[ifu_mem_ctl.scala 586:22] - reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 587:74] - iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[ifu_mem_ctl.scala 587:74] - io.iccm_dma_ecc_error <= iccm_dma_ecc_error @[ifu_mem_ctl.scala 588:25] - reg iccm_dma_rdata_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 589:75] - iccm_dma_rdata_temp <= iccm_dma_rdata_in @[ifu_mem_ctl.scala 589:75] - io.iccm_dma_rdata <= iccm_dma_rdata_temp @[ifu_mem_ctl.scala 590:21] + node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3104, _T_3105) @[ifu_mem_ctl.scala 586:30] + reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 587:54] + dma_mem_tag_ff <= io.dma_mem_ctl.dma_mem_tag @[ifu_mem_ctl.scala 587:54] + reg iccm_dma_rtag_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 588:74] + iccm_dma_rtag_temp <= dma_mem_tag_ff @[ifu_mem_ctl.scala 588:74] + io.iccm_dma_rtag <= iccm_dma_rtag_temp @[ifu_mem_ctl.scala 589:20] + node _T_3106 = bits(io.dma_mem_ctl.dma_mem_addr, 3, 2) @[ifu_mem_ctl.scala 591:81] + reg _T_3107 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 591:53] + _T_3107 <= _T_3106 @[ifu_mem_ctl.scala 591:53] + dma_mem_addr_ff <= _T_3107 @[ifu_mem_ctl.scala 591:19] + reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 592:59] + iccm_dma_rvalid_in <= iccm_dma_rden @[ifu_mem_ctl.scala 592:59] + reg iccm_dma_rvalid_temp : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 593:76] + iccm_dma_rvalid_temp <= iccm_dma_rvalid_in @[ifu_mem_ctl.scala 593:76] + io.iccm_dma_rvalid <= iccm_dma_rvalid_temp @[ifu_mem_ctl.scala 594:22] + reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 595:74] + iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[ifu_mem_ctl.scala 595:74] + io.iccm_dma_ecc_error <= iccm_dma_ecc_error @[ifu_mem_ctl.scala 596:25] + reg iccm_dma_rdata_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 597:75] + iccm_dma_rdata_temp <= iccm_dma_rdata_in @[ifu_mem_ctl.scala 597:75] + io.iccm_dma_rdata <= iccm_dma_rdata_temp @[ifu_mem_ctl.scala 598:21] wire iccm_ecc_corr_index_ff : UInt<14> iccm_ecc_corr_index_ff <= UInt<1>("h00") - node _T_3108 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 592:46] - node _T_3109 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 592:79] - node _T_3110 = and(_T_3108, _T_3109) @[ifu_mem_ctl.scala 592:77] - node _T_3111 = bits(io.dma_mem_ctl.dma_mem_addr, 15, 1) @[ifu_mem_ctl.scala 592:125] - node _T_3112 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 593:31] - node _T_3113 = eq(_T_3112, UInt<1>("h00")) @[ifu_mem_ctl.scala 593:9] - node _T_3114 = and(_T_3113, iccm_correct_ecc) @[ifu_mem_ctl.scala 593:62] + node _T_3108 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 600:46] + node _T_3109 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 600:79] + node _T_3110 = and(_T_3108, _T_3109) @[ifu_mem_ctl.scala 600:77] + node _T_3111 = bits(io.dma_mem_ctl.dma_mem_addr, 15, 1) @[ifu_mem_ctl.scala 600:125] + node _T_3112 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 601:31] + node _T_3113 = eq(_T_3112, UInt<1>("h00")) @[ifu_mem_ctl.scala 601:9] + node _T_3114 = and(_T_3113, iccm_correct_ecc) @[ifu_mem_ctl.scala 601:62] node _T_3115 = cat(iccm_ecc_corr_index_ff, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_3116 = bits(io.ifc_fetch_addr_bf, 14, 0) @[ifu_mem_ctl.scala 593:136] - node _T_3117 = mux(_T_3114, _T_3115, _T_3116) @[ifu_mem_ctl.scala 593:8] - node _T_3118 = mux(_T_3110, _T_3111, _T_3117) @[ifu_mem_ctl.scala 592:25] - io.iccm.rw_addr <= _T_3118 @[ifu_mem_ctl.scala 592:19] + node _T_3116 = bits(io.ifc_fetch_addr_bf, 14, 0) @[ifu_mem_ctl.scala 601:136] + node _T_3117 = mux(_T_3114, _T_3115, _T_3116) @[ifu_mem_ctl.scala 601:8] + node _T_3118 = mux(_T_3110, _T_3111, _T_3117) @[ifu_mem_ctl.scala 600:25] + io.iccm.rw_addr <= _T_3118 @[ifu_mem_ctl.scala 600:19] node ic_fetch_val_int_f = cat(UInt<2>("h00"), io.ic_fetch_val_f) @[Cat.scala 29:58] - node _T_3119 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 595:76] - node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3119) @[ifu_mem_ctl.scala 595:53] - node _T_3120 = bits(ic_fetch_val_shift_right, 1, 0) @[ifu_mem_ctl.scala 598:75] - node _T_3121 = orr(_T_3120) @[ifu_mem_ctl.scala 598:91] - node _T_3122 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 598:97] - node _T_3123 = and(_T_3121, _T_3122) @[ifu_mem_ctl.scala 598:95] - node _T_3124 = and(_T_3123, fetch_req_iccm_f) @[ifu_mem_ctl.scala 598:117] - node _T_3125 = or(_T_3124, iccm_dma_rvalid_in) @[ifu_mem_ctl.scala 598:134] - node _T_3126 = eq(io.dec_mem_ctrl.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[ifu_mem_ctl.scala 598:158] - node _T_3127 = and(_T_3125, _T_3126) @[ifu_mem_ctl.scala 598:156] - node _T_3128 = bits(ic_fetch_val_shift_right, 3, 2) @[ifu_mem_ctl.scala 598:75] - node _T_3129 = orr(_T_3128) @[ifu_mem_ctl.scala 598:91] - node _T_3130 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 598:97] - node _T_3131 = and(_T_3129, _T_3130) @[ifu_mem_ctl.scala 598:95] - node _T_3132 = and(_T_3131, fetch_req_iccm_f) @[ifu_mem_ctl.scala 598:117] - node _T_3133 = or(_T_3132, iccm_dma_rvalid_in) @[ifu_mem_ctl.scala 598:134] - node _T_3134 = eq(io.dec_mem_ctrl.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[ifu_mem_ctl.scala 598:158] - node _T_3135 = and(_T_3133, _T_3134) @[ifu_mem_ctl.scala 598:156] + node _T_3119 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 603:76] + node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3119) @[ifu_mem_ctl.scala 603:53] + node _T_3120 = bits(ic_fetch_val_shift_right, 1, 0) @[ifu_mem_ctl.scala 606:75] + node _T_3121 = orr(_T_3120) @[ifu_mem_ctl.scala 606:91] + node _T_3122 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 606:97] + node _T_3123 = and(_T_3121, _T_3122) @[ifu_mem_ctl.scala 606:95] + node _T_3124 = and(_T_3123, fetch_req_iccm_f) @[ifu_mem_ctl.scala 606:117] + node _T_3125 = or(_T_3124, iccm_dma_rvalid_in) @[ifu_mem_ctl.scala 606:134] + node _T_3126 = eq(io.dec_mem_ctrl.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[ifu_mem_ctl.scala 606:158] + node _T_3127 = and(_T_3125, _T_3126) @[ifu_mem_ctl.scala 606:156] + node _T_3128 = bits(ic_fetch_val_shift_right, 3, 2) @[ifu_mem_ctl.scala 606:75] + node _T_3129 = orr(_T_3128) @[ifu_mem_ctl.scala 606:91] + node _T_3130 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 606:97] + node _T_3131 = and(_T_3129, _T_3130) @[ifu_mem_ctl.scala 606:95] + node _T_3132 = and(_T_3131, fetch_req_iccm_f) @[ifu_mem_ctl.scala 606:117] + node _T_3133 = or(_T_3132, iccm_dma_rvalid_in) @[ifu_mem_ctl.scala 606:134] + node _T_3134 = eq(io.dec_mem_ctrl.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[ifu_mem_ctl.scala 606:158] + node _T_3135 = and(_T_3133, _T_3134) @[ifu_mem_ctl.scala 606:156] node iccm_ecc_word_enable = cat(_T_3135, _T_3127) @[Cat.scala 29:58] - node _T_3136 = bits(iccm_ecc_word_enable, 0, 0) @[ifu_mem_ctl.scala 599:73] - node _T_3137 = bits(io.iccm.rd_data_ecc, 31, 0) @[ifu_mem_ctl.scala 599:93] - node _T_3138 = bits(io.iccm.rd_data_ecc, 38, 32) @[ifu_mem_ctl.scala 599:128] + node _T_3136 = bits(iccm_ecc_word_enable, 0, 0) @[ifu_mem_ctl.scala 607:73] + node _T_3137 = bits(io.iccm.rd_data_ecc, 31, 0) @[ifu_mem_ctl.scala 607:93] + node _T_3138 = bits(io.iccm.rd_data_ecc, 38, 32) @[ifu_mem_ctl.scala 607:128] wire _T_3139 : UInt<1>[18] @[lib.scala 157:18] wire _T_3140 : UInt<1>[18] @[lib.scala 158:18] wire _T_3141 : UInt<1>[18] @[lib.scala 159:18] @@ -7484,9 +7484,9 @@ circuit quasar_wrapper : node _T_3518 = cat(_T_3510, _T_3511) @[Cat.scala 29:58] node _T_3519 = cat(_T_3518, _T_3512) @[Cat.scala 29:58] node _T_3520 = cat(_T_3519, _T_3517) @[Cat.scala 29:58] - node _T_3521 = bits(iccm_ecc_word_enable, 1, 1) @[ifu_mem_ctl.scala 599:73] - node _T_3522 = bits(io.iccm.rd_data_ecc, 70, 39) @[ifu_mem_ctl.scala 599:93] - node _T_3523 = bits(io.iccm.rd_data_ecc, 77, 71) @[ifu_mem_ctl.scala 599:128] + node _T_3521 = bits(iccm_ecc_word_enable, 1, 1) @[ifu_mem_ctl.scala 607:73] + node _T_3522 = bits(io.iccm.rd_data_ecc, 70, 39) @[ifu_mem_ctl.scala 607:93] + node _T_3523 = bits(io.iccm.rd_data_ecc, 77, 71) @[ifu_mem_ctl.scala 607:128] wire _T_3524 : UInt<1>[18] @[lib.scala 157:18] wire _T_3525 : UInt<1>[18] @[lib.scala 158:18] wire _T_3526 : UInt<1>[18] @[lib.scala 159:18] @@ -7998,191 +7998,191 @@ circuit quasar_wrapper : node _T_3903 = cat(_T_3895, _T_3896) @[Cat.scala 29:58] node _T_3904 = cat(_T_3903, _T_3897) @[Cat.scala 29:58] node _T_3905 = cat(_T_3904, _T_3902) @[Cat.scala 29:58] - wire iccm_corrected_ecc : UInt<7>[2] @[ifu_mem_ctl.scala 600:32] - wire _T_3906 : UInt<7>[2] @[ifu_mem_ctl.scala 601:32] - _T_3906[0] <= _T_3520 @[ifu_mem_ctl.scala 601:32] - _T_3906[1] <= _T_3905 @[ifu_mem_ctl.scala 601:32] - iccm_corrected_ecc[0] <= _T_3906[0] @[ifu_mem_ctl.scala 601:22] - iccm_corrected_ecc[1] <= _T_3906[1] @[ifu_mem_ctl.scala 601:22] - wire _T_3907 : UInt<32>[2] @[ifu_mem_ctl.scala 602:33] - _T_3907[0] <= _T_3506 @[ifu_mem_ctl.scala 602:33] - _T_3907[1] <= _T_3891 @[ifu_mem_ctl.scala 602:33] - iccm_corrected_data[0] <= _T_3907[0] @[ifu_mem_ctl.scala 602:23] - iccm_corrected_data[1] <= _T_3907[1] @[ifu_mem_ctl.scala 602:23] + wire iccm_corrected_ecc : UInt<7>[2] @[ifu_mem_ctl.scala 608:32] + wire _T_3906 : UInt<7>[2] @[ifu_mem_ctl.scala 609:32] + _T_3906[0] <= _T_3520 @[ifu_mem_ctl.scala 609:32] + _T_3906[1] <= _T_3905 @[ifu_mem_ctl.scala 609:32] + iccm_corrected_ecc[0] <= _T_3906[0] @[ifu_mem_ctl.scala 609:22] + iccm_corrected_ecc[1] <= _T_3906[1] @[ifu_mem_ctl.scala 609:22] + wire _T_3907 : UInt<32>[2] @[ifu_mem_ctl.scala 610:33] + _T_3907[0] <= _T_3506 @[ifu_mem_ctl.scala 610:33] + _T_3907[1] <= _T_3891 @[ifu_mem_ctl.scala 610:33] + iccm_corrected_data[0] <= _T_3907[0] @[ifu_mem_ctl.scala 610:23] + iccm_corrected_data[1] <= _T_3907[1] @[ifu_mem_ctl.scala 610:23] node _T_3908 = cat(_T_3736, _T_3351) @[Cat.scala 29:58] - iccm_single_ecc_error <= _T_3908 @[ifu_mem_ctl.scala 603:25] + iccm_single_ecc_error <= _T_3908 @[ifu_mem_ctl.scala 611:25] node _T_3909 = cat(_T_3741, _T_3356) @[Cat.scala 29:58] - iccm_double_ecc_error <= _T_3909 @[ifu_mem_ctl.scala 604:25] - node _T_3910 = orr(iccm_single_ecc_error) @[ifu_mem_ctl.scala 605:71] - node _T_3911 = and(_T_3910, ifc_iccm_access_f) @[ifu_mem_ctl.scala 605:75] - node _T_3912 = and(_T_3911, ifc_fetch_req_f) @[ifu_mem_ctl.scala 605:95] - io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= _T_3912 @[ifu_mem_ctl.scala 605:46] - node _T_3913 = orr(iccm_double_ecc_error) @[ifu_mem_ctl.scala 606:54] - node _T_3914 = and(_T_3913, ifc_iccm_access_f) @[ifu_mem_ctl.scala 606:58] - io.iccm_rd_ecc_double_err <= _T_3914 @[ifu_mem_ctl.scala 606:29] - node _T_3915 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 607:60] - node _T_3916 = bits(_T_3915, 0, 0) @[ifu_mem_ctl.scala 607:64] - node iccm_corrected_data_f_mux = mux(_T_3916, iccm_corrected_data[0], iccm_corrected_data[1]) @[ifu_mem_ctl.scala 607:38] - node _T_3917 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 608:59] - node _T_3918 = bits(_T_3917, 0, 0) @[ifu_mem_ctl.scala 608:63] - node iccm_corrected_ecc_f_mux = mux(_T_3918, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[ifu_mem_ctl.scala 608:37] + iccm_double_ecc_error <= _T_3909 @[ifu_mem_ctl.scala 612:25] + node _T_3910 = orr(iccm_single_ecc_error) @[ifu_mem_ctl.scala 613:71] + node _T_3911 = and(_T_3910, ifc_iccm_access_f) @[ifu_mem_ctl.scala 613:75] + node _T_3912 = and(_T_3911, ifc_fetch_req_f) @[ifu_mem_ctl.scala 613:95] + io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= _T_3912 @[ifu_mem_ctl.scala 613:46] + node _T_3913 = orr(iccm_double_ecc_error) @[ifu_mem_ctl.scala 614:54] + node _T_3914 = and(_T_3913, ifc_iccm_access_f) @[ifu_mem_ctl.scala 614:58] + io.iccm_rd_ecc_double_err <= _T_3914 @[ifu_mem_ctl.scala 614:29] + node _T_3915 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 615:60] + node _T_3916 = bits(_T_3915, 0, 0) @[ifu_mem_ctl.scala 615:64] + node iccm_corrected_data_f_mux = mux(_T_3916, iccm_corrected_data[0], iccm_corrected_data[1]) @[ifu_mem_ctl.scala 615:38] + node _T_3917 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 616:59] + node _T_3918 = bits(_T_3917, 0, 0) @[ifu_mem_ctl.scala 616:63] + node iccm_corrected_ecc_f_mux = mux(_T_3918, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[ifu_mem_ctl.scala 616:37] wire iccm_rd_ecc_single_err_ff : UInt<1> iccm_rd_ecc_single_err_ff <= UInt<1>("h00") - node _T_3919 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 610:93] - node _T_3920 = and(io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err, _T_3919) @[ifu_mem_ctl.scala 610:91] - node _T_3921 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 610:123] - node _T_3922 = and(_T_3920, _T_3921) @[ifu_mem_ctl.scala 610:121] - node iccm_ecc_write_status = or(_T_3922, io.iccm_dma_sb_error) @[ifu_mem_ctl.scala 610:144] - node _T_3923 = or(io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[ifu_mem_ctl.scala 611:84] - node _T_3924 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 611:115] - node iccm_rd_ecc_single_err_hold_in = and(_T_3923, _T_3924) @[ifu_mem_ctl.scala 611:113] - iccm_error_start <= io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[ifu_mem_ctl.scala 612:20] + node _T_3919 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 618:93] + node _T_3920 = and(io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err, _T_3919) @[ifu_mem_ctl.scala 618:91] + node _T_3921 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 618:123] + node _T_3922 = and(_T_3920, _T_3921) @[ifu_mem_ctl.scala 618:121] + node iccm_ecc_write_status = or(_T_3922, io.iccm_dma_sb_error) @[ifu_mem_ctl.scala 618:144] + node _T_3923 = or(io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[ifu_mem_ctl.scala 619:84] + node _T_3924 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 619:115] + node iccm_rd_ecc_single_err_hold_in = and(_T_3923, _T_3924) @[ifu_mem_ctl.scala 619:113] + iccm_error_start <= io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[ifu_mem_ctl.scala 620:20] wire iccm_rw_addr_f : UInt<14> iccm_rw_addr_f <= UInt<1>("h00") - node _T_3925 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 614:57] - node _T_3926 = bits(_T_3925, 0, 0) @[ifu_mem_ctl.scala 614:67] - node _T_3927 = add(iccm_rw_addr_f, UInt<1>("h01")) @[ifu_mem_ctl.scala 614:102] - node _T_3928 = tail(_T_3927, 1) @[ifu_mem_ctl.scala 614:102] - node iccm_ecc_corr_index_in = mux(_T_3926, iccm_rw_addr_f, _T_3928) @[ifu_mem_ctl.scala 614:35] - node _T_3929 = bits(io.iccm.rw_addr, 14, 1) @[ifu_mem_ctl.scala 615:67] - reg _T_3930 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 615:51] - _T_3930 <= _T_3929 @[ifu_mem_ctl.scala 615:51] - iccm_rw_addr_f <= _T_3930 @[ifu_mem_ctl.scala 615:18] - reg _T_3931 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 616:62] - _T_3931 <= iccm_rd_ecc_single_err_hold_in @[ifu_mem_ctl.scala 616:62] - iccm_rd_ecc_single_err_ff <= _T_3931 @[ifu_mem_ctl.scala 616:29] + node _T_3925 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 622:57] + node _T_3926 = bits(_T_3925, 0, 0) @[ifu_mem_ctl.scala 622:67] + node _T_3927 = add(iccm_rw_addr_f, UInt<1>("h01")) @[ifu_mem_ctl.scala 622:102] + node _T_3928 = tail(_T_3927, 1) @[ifu_mem_ctl.scala 622:102] + node iccm_ecc_corr_index_in = mux(_T_3926, iccm_rw_addr_f, _T_3928) @[ifu_mem_ctl.scala 622:35] + node _T_3929 = bits(io.iccm.rw_addr, 14, 1) @[ifu_mem_ctl.scala 623:67] + reg _T_3930 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 623:51] + _T_3930 <= _T_3929 @[ifu_mem_ctl.scala 623:51] + iccm_rw_addr_f <= _T_3930 @[ifu_mem_ctl.scala 623:18] + reg _T_3931 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 624:62] + _T_3931 <= iccm_rd_ecc_single_err_hold_in @[ifu_mem_ctl.scala 624:62] + iccm_rd_ecc_single_err_ff <= _T_3931 @[ifu_mem_ctl.scala 624:29] node _T_3932 = cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux) @[Cat.scala 29:58] - node _T_3933 = bits(iccm_ecc_write_status, 0, 0) @[ifu_mem_ctl.scala 617:152] + node _T_3933 = bits(iccm_ecc_write_status, 0, 0) @[ifu_mem_ctl.scala 625:152] reg _T_3934 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3933 : @[Reg.scala 28:19] _T_3934 <= _T_3932 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - iccm_ecc_corr_data_ff <= _T_3934 @[ifu_mem_ctl.scala 617:25] - node _T_3935 = bits(iccm_ecc_write_status, 0, 0) @[ifu_mem_ctl.scala 618:119] + iccm_ecc_corr_data_ff <= _T_3934 @[ifu_mem_ctl.scala 625:25] + node _T_3935 = bits(iccm_ecc_write_status, 0, 0) @[ifu_mem_ctl.scala 626:119] reg _T_3936 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3935 : @[Reg.scala 28:19] _T_3936 <= iccm_ecc_corr_index_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - iccm_ecc_corr_index_ff <= _T_3936 @[ifu_mem_ctl.scala 618:26] - node _T_3937 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 619:41] - node _T_3938 = and(io.ifc_fetch_req_bf, _T_3937) @[ifu_mem_ctl.scala 619:39] - node _T_3939 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 619:72] - node _T_3940 = and(_T_3938, _T_3939) @[ifu_mem_ctl.scala 619:70] - node _T_3941 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 620:19] - node _T_3942 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 620:34] - node _T_3943 = and(_T_3941, _T_3942) @[ifu_mem_ctl.scala 620:32] - node _T_3944 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 621:19] - node _T_3945 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 621:39] - node _T_3946 = and(_T_3944, _T_3945) @[ifu_mem_ctl.scala 621:37] - node _T_3947 = or(_T_3943, _T_3946) @[ifu_mem_ctl.scala 620:88] - node _T_3948 = eq(miss_state, UInt<3>("h07")) @[ifu_mem_ctl.scala 622:19] - node _T_3949 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 622:43] - node _T_3950 = and(_T_3948, _T_3949) @[ifu_mem_ctl.scala 622:41] - node _T_3951 = or(_T_3947, _T_3950) @[ifu_mem_ctl.scala 621:88] - node _T_3952 = eq(miss_state, UInt<3>("h03")) @[ifu_mem_ctl.scala 623:19] - node _T_3953 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 623:37] - node _T_3954 = and(_T_3952, _T_3953) @[ifu_mem_ctl.scala 623:35] - node _T_3955 = or(_T_3951, _T_3954) @[ifu_mem_ctl.scala 622:88] - node _T_3956 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 624:19] - node _T_3957 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 624:40] - node _T_3958 = and(_T_3956, _T_3957) @[ifu_mem_ctl.scala 624:38] - node _T_3959 = or(_T_3955, _T_3958) @[ifu_mem_ctl.scala 623:88] - node _T_3960 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 625:19] - node _T_3961 = and(_T_3960, miss_state_en) @[ifu_mem_ctl.scala 625:37] - node _T_3962 = eq(miss_nxtstate, UInt<3>("h03")) @[ifu_mem_ctl.scala 625:71] - node _T_3963 = and(_T_3961, _T_3962) @[ifu_mem_ctl.scala 625:54] - node _T_3964 = or(_T_3959, _T_3963) @[ifu_mem_ctl.scala 624:57] - node _T_3965 = eq(_T_3964, UInt<1>("h00")) @[ifu_mem_ctl.scala 620:5] - node _T_3966 = and(_T_3940, _T_3965) @[ifu_mem_ctl.scala 619:96] - node _T_3967 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[ifu_mem_ctl.scala 626:28] - node _T_3968 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 626:52] - node _T_3969 = and(_T_3967, _T_3968) @[ifu_mem_ctl.scala 626:50] - node _T_3970 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 626:83] - node _T_3971 = and(_T_3969, _T_3970) @[ifu_mem_ctl.scala 626:81] - node _T_3972 = or(_T_3966, _T_3971) @[ifu_mem_ctl.scala 625:93] - io.ic.rd_en <= _T_3972 @[ifu_mem_ctl.scala 619:15] + iccm_ecc_corr_index_ff <= _T_3936 @[ifu_mem_ctl.scala 626:26] + node _T_3937 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 627:41] + node _T_3938 = and(io.ifc_fetch_req_bf, _T_3937) @[ifu_mem_ctl.scala 627:39] + node _T_3939 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 627:72] + node _T_3940 = and(_T_3938, _T_3939) @[ifu_mem_ctl.scala 627:70] + node _T_3941 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 628:19] + node _T_3942 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 628:34] + node _T_3943 = and(_T_3941, _T_3942) @[ifu_mem_ctl.scala 628:32] + node _T_3944 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 629:19] + node _T_3945 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 629:39] + node _T_3946 = and(_T_3944, _T_3945) @[ifu_mem_ctl.scala 629:37] + node _T_3947 = or(_T_3943, _T_3946) @[ifu_mem_ctl.scala 628:88] + node _T_3948 = eq(miss_state, UInt<3>("h07")) @[ifu_mem_ctl.scala 630:19] + node _T_3949 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 630:43] + node _T_3950 = and(_T_3948, _T_3949) @[ifu_mem_ctl.scala 630:41] + node _T_3951 = or(_T_3947, _T_3950) @[ifu_mem_ctl.scala 629:88] + node _T_3952 = eq(miss_state, UInt<3>("h03")) @[ifu_mem_ctl.scala 631:19] + node _T_3953 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 631:37] + node _T_3954 = and(_T_3952, _T_3953) @[ifu_mem_ctl.scala 631:35] + node _T_3955 = or(_T_3951, _T_3954) @[ifu_mem_ctl.scala 630:88] + node _T_3956 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 632:19] + node _T_3957 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 632:40] + node _T_3958 = and(_T_3956, _T_3957) @[ifu_mem_ctl.scala 632:38] + node _T_3959 = or(_T_3955, _T_3958) @[ifu_mem_ctl.scala 631:88] + node _T_3960 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 633:19] + node _T_3961 = and(_T_3960, miss_state_en) @[ifu_mem_ctl.scala 633:37] + node _T_3962 = eq(miss_nxtstate, UInt<3>("h03")) @[ifu_mem_ctl.scala 633:71] + node _T_3963 = and(_T_3961, _T_3962) @[ifu_mem_ctl.scala 633:54] + node _T_3964 = or(_T_3959, _T_3963) @[ifu_mem_ctl.scala 632:57] + node _T_3965 = eq(_T_3964, UInt<1>("h00")) @[ifu_mem_ctl.scala 628:5] + node _T_3966 = and(_T_3940, _T_3965) @[ifu_mem_ctl.scala 627:96] + node _T_3967 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[ifu_mem_ctl.scala 634:28] + node _T_3968 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 634:52] + node _T_3969 = and(_T_3967, _T_3968) @[ifu_mem_ctl.scala 634:50] + node _T_3970 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 634:83] + node _T_3971 = and(_T_3969, _T_3970) @[ifu_mem_ctl.scala 634:81] + node _T_3972 = or(_T_3966, _T_3971) @[ifu_mem_ctl.scala 633:93] + io.ic.rd_en <= _T_3972 @[ifu_mem_ctl.scala 627:15] wire bus_ic_wr_en : UInt<2> bus_ic_wr_en <= UInt<1>("h00") node _T_3973 = bits(write_ic_16_bytes, 0, 0) @[Bitwise.scala 72:15] node _T_3974 = mux(_T_3973, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_3975 = and(bus_ic_wr_en, _T_3974) @[ifu_mem_ctl.scala 628:31] - io.ic.wr_en <= _T_3975 @[ifu_mem_ctl.scala 628:15] - node _T_3976 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 629:59] - node _T_3977 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 629:91] - node _T_3978 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 629:127] - node _T_3979 = or(_T_3978, stream_eol_f) @[ifu_mem_ctl.scala 629:151] - node _T_3980 = eq(_T_3979, UInt<1>("h00")) @[ifu_mem_ctl.scala 629:106] - node _T_3981 = and(_T_3977, _T_3980) @[ifu_mem_ctl.scala 629:104] - node _T_3982 = or(_T_3976, _T_3981) @[ifu_mem_ctl.scala 629:77] - node _T_3983 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 629:191] - node _T_3984 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 629:205] - node _T_3985 = and(_T_3983, _T_3984) @[ifu_mem_ctl.scala 629:203] - node _T_3986 = eq(_T_3985, UInt<1>("h00")) @[ifu_mem_ctl.scala 629:172] - node _T_3987 = and(_T_3982, _T_3986) @[ifu_mem_ctl.scala 629:170] - node _T_3988 = eq(_T_3987, UInt<1>("h00")) @[ifu_mem_ctl.scala 629:44] - node _T_3989 = and(write_ic_16_bytes, _T_3988) @[ifu_mem_ctl.scala 629:42] - io.ic_write_stall <= _T_3989 @[ifu_mem_ctl.scala 629:21] - reg _T_3990 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 630:53] - _T_3990 <= io.dec_mem_ctrl.dec_tlu_fence_i_wb @[ifu_mem_ctl.scala 630:53] - reset_all_tags <= _T_3990 @[ifu_mem_ctl.scala 630:18] - node _T_3991 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[ifu_mem_ctl.scala 632:20] - node _T_3992 = or(reset_ic_in, reset_ic_ff) @[ifu_mem_ctl.scala 632:64] - node _T_3993 = eq(_T_3992, UInt<1>("h00")) @[ifu_mem_ctl.scala 632:50] - node _T_3994 = and(_T_3991, _T_3993) @[ifu_mem_ctl.scala 632:48] - node _T_3995 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[ifu_mem_ctl.scala 632:81] - node ic_valid = and(_T_3994, _T_3995) @[ifu_mem_ctl.scala 632:79] - node _T_3996 = or(io.ic.debug_rd_en, io.ic.debug_wr_en) @[ifu_mem_ctl.scala 633:61] - node _T_3997 = and(_T_3996, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 633:82] - node _T_3998 = bits(io.ic.debug_addr, 9, 3) @[ifu_mem_ctl.scala 633:123] - node _T_3999 = bits(ifu_status_wr_addr, 11, 5) @[ifu_mem_ctl.scala 634:25] - node ifu_status_wr_addr_w_debug = mux(_T_3997, _T_3998, _T_3999) @[ifu_mem_ctl.scala 633:41] - reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 636:14] - ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[ifu_mem_ctl.scala 636:14] + node _T_3975 = and(bus_ic_wr_en, _T_3974) @[ifu_mem_ctl.scala 636:31] + io.ic.wr_en <= _T_3975 @[ifu_mem_ctl.scala 636:15] + node _T_3976 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 637:59] + node _T_3977 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 637:91] + node _T_3978 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 637:127] + node _T_3979 = or(_T_3978, stream_eol_f) @[ifu_mem_ctl.scala 637:151] + node _T_3980 = eq(_T_3979, UInt<1>("h00")) @[ifu_mem_ctl.scala 637:106] + node _T_3981 = and(_T_3977, _T_3980) @[ifu_mem_ctl.scala 637:104] + node _T_3982 = or(_T_3976, _T_3981) @[ifu_mem_ctl.scala 637:77] + node _T_3983 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 637:191] + node _T_3984 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 637:205] + node _T_3985 = and(_T_3983, _T_3984) @[ifu_mem_ctl.scala 637:203] + node _T_3986 = eq(_T_3985, UInt<1>("h00")) @[ifu_mem_ctl.scala 637:172] + node _T_3987 = and(_T_3982, _T_3986) @[ifu_mem_ctl.scala 637:170] + node _T_3988 = eq(_T_3987, UInt<1>("h00")) @[ifu_mem_ctl.scala 637:44] + node _T_3989 = and(write_ic_16_bytes, _T_3988) @[ifu_mem_ctl.scala 637:42] + io.ic_write_stall <= _T_3989 @[ifu_mem_ctl.scala 637:21] + reg _T_3990 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 638:53] + _T_3990 <= io.dec_mem_ctrl.dec_tlu_fence_i_wb @[ifu_mem_ctl.scala 638:53] + reset_all_tags <= _T_3990 @[ifu_mem_ctl.scala 638:18] + node _T_3991 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[ifu_mem_ctl.scala 640:20] + node _T_3992 = or(reset_ic_in, reset_ic_ff) @[ifu_mem_ctl.scala 640:64] + node _T_3993 = eq(_T_3992, UInt<1>("h00")) @[ifu_mem_ctl.scala 640:50] + node _T_3994 = and(_T_3991, _T_3993) @[ifu_mem_ctl.scala 640:48] + node _T_3995 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[ifu_mem_ctl.scala 640:81] + node ic_valid = and(_T_3994, _T_3995) @[ifu_mem_ctl.scala 640:79] + node _T_3996 = or(io.ic.debug_rd_en, io.ic.debug_wr_en) @[ifu_mem_ctl.scala 641:61] + node _T_3997 = and(_T_3996, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 641:82] + node _T_3998 = bits(io.ic.debug_addr, 9, 3) @[ifu_mem_ctl.scala 641:123] + node _T_3999 = bits(ifu_status_wr_addr, 11, 5) @[ifu_mem_ctl.scala 642:25] + node ifu_status_wr_addr_w_debug = mux(_T_3997, _T_3998, _T_3999) @[ifu_mem_ctl.scala 641:41] + reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 644:14] + ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[ifu_mem_ctl.scala 644:14] wire way_status_wr_en : UInt<1> way_status_wr_en <= UInt<1>("h00") - node _T_4000 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 639:74] - node way_status_wr_en_w_debug = or(way_status_wr_en, _T_4000) @[ifu_mem_ctl.scala 639:53] - reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 641:14] - way_status_wr_en_ff <= way_status_wr_en_w_debug @[ifu_mem_ctl.scala 641:14] + node _T_4000 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 647:74] + node way_status_wr_en_w_debug = or(way_status_wr_en, _T_4000) @[ifu_mem_ctl.scala 647:53] + reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 649:14] + way_status_wr_en_ff <= way_status_wr_en_w_debug @[ifu_mem_ctl.scala 649:14] wire way_status_new : UInt<1> way_status_new <= UInt<1>("h00") - node _T_4001 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 644:56] - node _T_4002 = bits(io.ic.debug_wr_data, 4, 4) @[ifu_mem_ctl.scala 645:55] - node way_status_new_w_debug = mux(_T_4001, _T_4002, way_status_new) @[ifu_mem_ctl.scala 644:37] - reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 647:14] - way_status_new_ff <= way_status_new_w_debug @[ifu_mem_ctl.scala 647:14] - node _T_4003 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_0 = eq(_T_4003, UInt<1>("h00")) @[ifu_mem_ctl.scala 649:132] - node _T_4004 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_1 = eq(_T_4004, UInt<1>("h01")) @[ifu_mem_ctl.scala 649:132] - node _T_4005 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_2 = eq(_T_4005, UInt<2>("h02")) @[ifu_mem_ctl.scala 649:132] - node _T_4006 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_3 = eq(_T_4006, UInt<2>("h03")) @[ifu_mem_ctl.scala 649:132] - node _T_4007 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_4 = eq(_T_4007, UInt<3>("h04")) @[ifu_mem_ctl.scala 649:132] - node _T_4008 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_5 = eq(_T_4008, UInt<3>("h05")) @[ifu_mem_ctl.scala 649:132] - node _T_4009 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_6 = eq(_T_4009, UInt<3>("h06")) @[ifu_mem_ctl.scala 649:132] - node _T_4010 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_7 = eq(_T_4010, UInt<3>("h07")) @[ifu_mem_ctl.scala 649:132] - node _T_4011 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_8 = eq(_T_4011, UInt<4>("h08")) @[ifu_mem_ctl.scala 649:132] - node _T_4012 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_9 = eq(_T_4012, UInt<4>("h09")) @[ifu_mem_ctl.scala 649:132] - node _T_4013 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_10 = eq(_T_4013, UInt<4>("h0a")) @[ifu_mem_ctl.scala 649:132] - node _T_4014 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_11 = eq(_T_4014, UInt<4>("h0b")) @[ifu_mem_ctl.scala 649:132] - node _T_4015 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_12 = eq(_T_4015, UInt<4>("h0c")) @[ifu_mem_ctl.scala 649:132] - node _T_4016 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_13 = eq(_T_4016, UInt<4>("h0d")) @[ifu_mem_ctl.scala 649:132] - node _T_4017 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_14 = eq(_T_4017, UInt<4>("h0e")) @[ifu_mem_ctl.scala 649:132] - node _T_4018 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 649:89] - node way_status_clken_15 = eq(_T_4018, UInt<4>("h0f")) @[ifu_mem_ctl.scala 649:132] + node _T_4001 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 652:56] + node _T_4002 = bits(io.ic.debug_wr_data, 4, 4) @[ifu_mem_ctl.scala 653:55] + node way_status_new_w_debug = mux(_T_4001, _T_4002, way_status_new) @[ifu_mem_ctl.scala 652:37] + reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 655:14] + way_status_new_ff <= way_status_new_w_debug @[ifu_mem_ctl.scala 655:14] + node _T_4003 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_0 = eq(_T_4003, UInt<1>("h00")) @[ifu_mem_ctl.scala 657:132] + node _T_4004 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_1 = eq(_T_4004, UInt<1>("h01")) @[ifu_mem_ctl.scala 657:132] + node _T_4005 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_2 = eq(_T_4005, UInt<2>("h02")) @[ifu_mem_ctl.scala 657:132] + node _T_4006 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_3 = eq(_T_4006, UInt<2>("h03")) @[ifu_mem_ctl.scala 657:132] + node _T_4007 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_4 = eq(_T_4007, UInt<3>("h04")) @[ifu_mem_ctl.scala 657:132] + node _T_4008 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_5 = eq(_T_4008, UInt<3>("h05")) @[ifu_mem_ctl.scala 657:132] + node _T_4009 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_6 = eq(_T_4009, UInt<3>("h06")) @[ifu_mem_ctl.scala 657:132] + node _T_4010 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_7 = eq(_T_4010, UInt<3>("h07")) @[ifu_mem_ctl.scala 657:132] + node _T_4011 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_8 = eq(_T_4011, UInt<4>("h08")) @[ifu_mem_ctl.scala 657:132] + node _T_4012 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_9 = eq(_T_4012, UInt<4>("h09")) @[ifu_mem_ctl.scala 657:132] + node _T_4013 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_10 = eq(_T_4013, UInt<4>("h0a")) @[ifu_mem_ctl.scala 657:132] + node _T_4014 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_11 = eq(_T_4014, UInt<4>("h0b")) @[ifu_mem_ctl.scala 657:132] + node _T_4015 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_12 = eq(_T_4015, UInt<4>("h0c")) @[ifu_mem_ctl.scala 657:132] + node _T_4016 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_13 = eq(_T_4016, UInt<4>("h0d")) @[ifu_mem_ctl.scala 657:132] + node _T_4017 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_14 = eq(_T_4017, UInt<4>("h0e")) @[ifu_mem_ctl.scala 657:132] + node _T_4018 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] + node way_status_clken_15 = eq(_T_4018, UInt<4>("h0f")) @[ifu_mem_ctl.scala 657:132] inst rvclkhdr_70 of rvclkhdr_70 @[lib.scala 327:22] rvclkhdr_70.clock <= clock rvclkhdr_70.reset <= reset @@ -8279,1031 +8279,1031 @@ circuit quasar_wrapper : rvclkhdr_85.io.clk <= clock @[lib.scala 328:17] rvclkhdr_85.io.en <= way_status_clken_15 @[lib.scala 329:16] rvclkhdr_85.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - wire way_status_out : UInt<1>[128] @[ifu_mem_ctl.scala 651:30] - node _T_4019 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4020 = eq(_T_4019, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4021 = and(_T_4020, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + wire way_status_out : UInt<1>[128] @[ifu_mem_ctl.scala 659:30] + node _T_4019 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4020 = eq(_T_4019, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4021 = and(_T_4020, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4022 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4021 : @[Reg.scala 28:19] _T_4022 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[0] <= _T_4022 @[ifu_mem_ctl.scala 653:35] - node _T_4023 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4024 = eq(_T_4023, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4025 = and(_T_4024, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[0] <= _T_4022 @[ifu_mem_ctl.scala 661:35] + node _T_4023 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4024 = eq(_T_4023, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4025 = and(_T_4024, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4026 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4025 : @[Reg.scala 28:19] _T_4026 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[1] <= _T_4026 @[ifu_mem_ctl.scala 653:35] - node _T_4027 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4028 = eq(_T_4027, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4029 = and(_T_4028, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[1] <= _T_4026 @[ifu_mem_ctl.scala 661:35] + node _T_4027 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4028 = eq(_T_4027, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4029 = and(_T_4028, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4030 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4029 : @[Reg.scala 28:19] _T_4030 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[2] <= _T_4030 @[ifu_mem_ctl.scala 653:35] - node _T_4031 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4032 = eq(_T_4031, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4033 = and(_T_4032, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[2] <= _T_4030 @[ifu_mem_ctl.scala 661:35] + node _T_4031 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4032 = eq(_T_4031, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4033 = and(_T_4032, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4034 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4033 : @[Reg.scala 28:19] _T_4034 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[3] <= _T_4034 @[ifu_mem_ctl.scala 653:35] - node _T_4035 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4036 = eq(_T_4035, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4037 = and(_T_4036, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[3] <= _T_4034 @[ifu_mem_ctl.scala 661:35] + node _T_4035 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4036 = eq(_T_4035, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4037 = and(_T_4036, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4038 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4037 : @[Reg.scala 28:19] _T_4038 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[4] <= _T_4038 @[ifu_mem_ctl.scala 653:35] - node _T_4039 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4040 = eq(_T_4039, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4041 = and(_T_4040, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[4] <= _T_4038 @[ifu_mem_ctl.scala 661:35] + node _T_4039 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4040 = eq(_T_4039, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4041 = and(_T_4040, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4042 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4041 : @[Reg.scala 28:19] _T_4042 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[5] <= _T_4042 @[ifu_mem_ctl.scala 653:35] - node _T_4043 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4044 = eq(_T_4043, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4045 = and(_T_4044, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[5] <= _T_4042 @[ifu_mem_ctl.scala 661:35] + node _T_4043 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4044 = eq(_T_4043, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4045 = and(_T_4044, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4046 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4045 : @[Reg.scala 28:19] _T_4046 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[6] <= _T_4046 @[ifu_mem_ctl.scala 653:35] - node _T_4047 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4048 = eq(_T_4047, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4049 = and(_T_4048, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[6] <= _T_4046 @[ifu_mem_ctl.scala 661:35] + node _T_4047 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4048 = eq(_T_4047, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4049 = and(_T_4048, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4050 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4049 : @[Reg.scala 28:19] _T_4050 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[7] <= _T_4050 @[ifu_mem_ctl.scala 653:35] - node _T_4051 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4052 = eq(_T_4051, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4053 = and(_T_4052, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[7] <= _T_4050 @[ifu_mem_ctl.scala 661:35] + node _T_4051 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4052 = eq(_T_4051, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4053 = and(_T_4052, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4054 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4053 : @[Reg.scala 28:19] _T_4054 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[8] <= _T_4054 @[ifu_mem_ctl.scala 653:35] - node _T_4055 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4056 = eq(_T_4055, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4057 = and(_T_4056, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[8] <= _T_4054 @[ifu_mem_ctl.scala 661:35] + node _T_4055 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4056 = eq(_T_4055, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4057 = and(_T_4056, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4058 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4057 : @[Reg.scala 28:19] _T_4058 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[9] <= _T_4058 @[ifu_mem_ctl.scala 653:35] - node _T_4059 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4060 = eq(_T_4059, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4061 = and(_T_4060, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[9] <= _T_4058 @[ifu_mem_ctl.scala 661:35] + node _T_4059 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4060 = eq(_T_4059, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4061 = and(_T_4060, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4062 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4061 : @[Reg.scala 28:19] _T_4062 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[10] <= _T_4062 @[ifu_mem_ctl.scala 653:35] - node _T_4063 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4064 = eq(_T_4063, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4065 = and(_T_4064, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[10] <= _T_4062 @[ifu_mem_ctl.scala 661:35] + node _T_4063 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4064 = eq(_T_4063, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4065 = and(_T_4064, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4066 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4065 : @[Reg.scala 28:19] _T_4066 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[11] <= _T_4066 @[ifu_mem_ctl.scala 653:35] - node _T_4067 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4068 = eq(_T_4067, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4069 = and(_T_4068, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[11] <= _T_4066 @[ifu_mem_ctl.scala 661:35] + node _T_4067 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4068 = eq(_T_4067, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4069 = and(_T_4068, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4070 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4069 : @[Reg.scala 28:19] _T_4070 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[12] <= _T_4070 @[ifu_mem_ctl.scala 653:35] - node _T_4071 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4072 = eq(_T_4071, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4073 = and(_T_4072, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[12] <= _T_4070 @[ifu_mem_ctl.scala 661:35] + node _T_4071 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4072 = eq(_T_4071, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4073 = and(_T_4072, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4074 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4073 : @[Reg.scala 28:19] _T_4074 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[13] <= _T_4074 @[ifu_mem_ctl.scala 653:35] - node _T_4075 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4076 = eq(_T_4075, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4077 = and(_T_4076, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[13] <= _T_4074 @[ifu_mem_ctl.scala 661:35] + node _T_4075 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4076 = eq(_T_4075, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4077 = and(_T_4076, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4078 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4077 : @[Reg.scala 28:19] _T_4078 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[14] <= _T_4078 @[ifu_mem_ctl.scala 653:35] - node _T_4079 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4080 = eq(_T_4079, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4081 = and(_T_4080, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[14] <= _T_4078 @[ifu_mem_ctl.scala 661:35] + node _T_4079 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4080 = eq(_T_4079, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4081 = and(_T_4080, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4082 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4081 : @[Reg.scala 28:19] _T_4082 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[15] <= _T_4082 @[ifu_mem_ctl.scala 653:35] - node _T_4083 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4084 = eq(_T_4083, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4085 = and(_T_4084, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[15] <= _T_4082 @[ifu_mem_ctl.scala 661:35] + node _T_4083 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4084 = eq(_T_4083, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4085 = and(_T_4084, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4086 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4085 : @[Reg.scala 28:19] _T_4086 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[16] <= _T_4086 @[ifu_mem_ctl.scala 653:35] - node _T_4087 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4088 = eq(_T_4087, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4089 = and(_T_4088, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[16] <= _T_4086 @[ifu_mem_ctl.scala 661:35] + node _T_4087 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4088 = eq(_T_4087, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4089 = and(_T_4088, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4090 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4089 : @[Reg.scala 28:19] _T_4090 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[17] <= _T_4090 @[ifu_mem_ctl.scala 653:35] - node _T_4091 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4092 = eq(_T_4091, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4093 = and(_T_4092, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[17] <= _T_4090 @[ifu_mem_ctl.scala 661:35] + node _T_4091 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4092 = eq(_T_4091, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4093 = and(_T_4092, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4094 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4093 : @[Reg.scala 28:19] _T_4094 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[18] <= _T_4094 @[ifu_mem_ctl.scala 653:35] - node _T_4095 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4096 = eq(_T_4095, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4097 = and(_T_4096, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[18] <= _T_4094 @[ifu_mem_ctl.scala 661:35] + node _T_4095 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4096 = eq(_T_4095, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4097 = and(_T_4096, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4098 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4097 : @[Reg.scala 28:19] _T_4098 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[19] <= _T_4098 @[ifu_mem_ctl.scala 653:35] - node _T_4099 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4100 = eq(_T_4099, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4101 = and(_T_4100, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[19] <= _T_4098 @[ifu_mem_ctl.scala 661:35] + node _T_4099 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4100 = eq(_T_4099, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4101 = and(_T_4100, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4102 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4101 : @[Reg.scala 28:19] _T_4102 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[20] <= _T_4102 @[ifu_mem_ctl.scala 653:35] - node _T_4103 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4104 = eq(_T_4103, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4105 = and(_T_4104, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[20] <= _T_4102 @[ifu_mem_ctl.scala 661:35] + node _T_4103 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4104 = eq(_T_4103, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4105 = and(_T_4104, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4106 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4105 : @[Reg.scala 28:19] _T_4106 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[21] <= _T_4106 @[ifu_mem_ctl.scala 653:35] - node _T_4107 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4108 = eq(_T_4107, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4109 = and(_T_4108, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[21] <= _T_4106 @[ifu_mem_ctl.scala 661:35] + node _T_4107 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4108 = eq(_T_4107, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4109 = and(_T_4108, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4110 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4109 : @[Reg.scala 28:19] _T_4110 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[22] <= _T_4110 @[ifu_mem_ctl.scala 653:35] - node _T_4111 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4112 = eq(_T_4111, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4113 = and(_T_4112, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[22] <= _T_4110 @[ifu_mem_ctl.scala 661:35] + node _T_4111 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4112 = eq(_T_4111, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4113 = and(_T_4112, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4114 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4113 : @[Reg.scala 28:19] _T_4114 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[23] <= _T_4114 @[ifu_mem_ctl.scala 653:35] - node _T_4115 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4116 = eq(_T_4115, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4117 = and(_T_4116, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[23] <= _T_4114 @[ifu_mem_ctl.scala 661:35] + node _T_4115 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4116 = eq(_T_4115, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4117 = and(_T_4116, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4118 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4117 : @[Reg.scala 28:19] _T_4118 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[24] <= _T_4118 @[ifu_mem_ctl.scala 653:35] - node _T_4119 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4120 = eq(_T_4119, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4121 = and(_T_4120, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[24] <= _T_4118 @[ifu_mem_ctl.scala 661:35] + node _T_4119 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4120 = eq(_T_4119, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4121 = and(_T_4120, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4122 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4121 : @[Reg.scala 28:19] _T_4122 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[25] <= _T_4122 @[ifu_mem_ctl.scala 653:35] - node _T_4123 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4124 = eq(_T_4123, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4125 = and(_T_4124, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[25] <= _T_4122 @[ifu_mem_ctl.scala 661:35] + node _T_4123 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4124 = eq(_T_4123, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4125 = and(_T_4124, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4126 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4125 : @[Reg.scala 28:19] _T_4126 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[26] <= _T_4126 @[ifu_mem_ctl.scala 653:35] - node _T_4127 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4128 = eq(_T_4127, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4129 = and(_T_4128, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[26] <= _T_4126 @[ifu_mem_ctl.scala 661:35] + node _T_4127 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4128 = eq(_T_4127, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4129 = and(_T_4128, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4130 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4129 : @[Reg.scala 28:19] _T_4130 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[27] <= _T_4130 @[ifu_mem_ctl.scala 653:35] - node _T_4131 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4132 = eq(_T_4131, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4133 = and(_T_4132, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[27] <= _T_4130 @[ifu_mem_ctl.scala 661:35] + node _T_4131 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4132 = eq(_T_4131, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4133 = and(_T_4132, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4134 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4133 : @[Reg.scala 28:19] _T_4134 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[28] <= _T_4134 @[ifu_mem_ctl.scala 653:35] - node _T_4135 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4136 = eq(_T_4135, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4137 = and(_T_4136, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[28] <= _T_4134 @[ifu_mem_ctl.scala 661:35] + node _T_4135 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4136 = eq(_T_4135, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4137 = and(_T_4136, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4138 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4137 : @[Reg.scala 28:19] _T_4138 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[29] <= _T_4138 @[ifu_mem_ctl.scala 653:35] - node _T_4139 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4140 = eq(_T_4139, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4141 = and(_T_4140, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[29] <= _T_4138 @[ifu_mem_ctl.scala 661:35] + node _T_4139 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4140 = eq(_T_4139, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4141 = and(_T_4140, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4142 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4141 : @[Reg.scala 28:19] _T_4142 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[30] <= _T_4142 @[ifu_mem_ctl.scala 653:35] - node _T_4143 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4144 = eq(_T_4143, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4145 = and(_T_4144, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[30] <= _T_4142 @[ifu_mem_ctl.scala 661:35] + node _T_4143 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4144 = eq(_T_4143, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4145 = and(_T_4144, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4146 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4145 : @[Reg.scala 28:19] _T_4146 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[31] <= _T_4146 @[ifu_mem_ctl.scala 653:35] - node _T_4147 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4148 = eq(_T_4147, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4149 = and(_T_4148, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[31] <= _T_4146 @[ifu_mem_ctl.scala 661:35] + node _T_4147 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4148 = eq(_T_4147, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4149 = and(_T_4148, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4150 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4149 : @[Reg.scala 28:19] _T_4150 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[32] <= _T_4150 @[ifu_mem_ctl.scala 653:35] - node _T_4151 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4152 = eq(_T_4151, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4153 = and(_T_4152, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[32] <= _T_4150 @[ifu_mem_ctl.scala 661:35] + node _T_4151 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4152 = eq(_T_4151, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4153 = and(_T_4152, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4154 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4153 : @[Reg.scala 28:19] _T_4154 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[33] <= _T_4154 @[ifu_mem_ctl.scala 653:35] - node _T_4155 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4156 = eq(_T_4155, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4157 = and(_T_4156, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[33] <= _T_4154 @[ifu_mem_ctl.scala 661:35] + node _T_4155 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4156 = eq(_T_4155, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4157 = and(_T_4156, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4158 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4157 : @[Reg.scala 28:19] _T_4158 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[34] <= _T_4158 @[ifu_mem_ctl.scala 653:35] - node _T_4159 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4160 = eq(_T_4159, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4161 = and(_T_4160, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[34] <= _T_4158 @[ifu_mem_ctl.scala 661:35] + node _T_4159 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4160 = eq(_T_4159, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4161 = and(_T_4160, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4162 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4161 : @[Reg.scala 28:19] _T_4162 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[35] <= _T_4162 @[ifu_mem_ctl.scala 653:35] - node _T_4163 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4164 = eq(_T_4163, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4165 = and(_T_4164, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[35] <= _T_4162 @[ifu_mem_ctl.scala 661:35] + node _T_4163 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4164 = eq(_T_4163, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4165 = and(_T_4164, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4166 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4165 : @[Reg.scala 28:19] _T_4166 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[36] <= _T_4166 @[ifu_mem_ctl.scala 653:35] - node _T_4167 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4168 = eq(_T_4167, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4169 = and(_T_4168, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[36] <= _T_4166 @[ifu_mem_ctl.scala 661:35] + node _T_4167 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4168 = eq(_T_4167, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4169 = and(_T_4168, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4170 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4169 : @[Reg.scala 28:19] _T_4170 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[37] <= _T_4170 @[ifu_mem_ctl.scala 653:35] - node _T_4171 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4172 = eq(_T_4171, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4173 = and(_T_4172, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[37] <= _T_4170 @[ifu_mem_ctl.scala 661:35] + node _T_4171 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4172 = eq(_T_4171, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4173 = and(_T_4172, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4174 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4173 : @[Reg.scala 28:19] _T_4174 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[38] <= _T_4174 @[ifu_mem_ctl.scala 653:35] - node _T_4175 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4176 = eq(_T_4175, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4177 = and(_T_4176, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[38] <= _T_4174 @[ifu_mem_ctl.scala 661:35] + node _T_4175 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4176 = eq(_T_4175, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4177 = and(_T_4176, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4178 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4177 : @[Reg.scala 28:19] _T_4178 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[39] <= _T_4178 @[ifu_mem_ctl.scala 653:35] - node _T_4179 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4180 = eq(_T_4179, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4181 = and(_T_4180, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[39] <= _T_4178 @[ifu_mem_ctl.scala 661:35] + node _T_4179 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4180 = eq(_T_4179, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4181 = and(_T_4180, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4182 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4181 : @[Reg.scala 28:19] _T_4182 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[40] <= _T_4182 @[ifu_mem_ctl.scala 653:35] - node _T_4183 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4184 = eq(_T_4183, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4185 = and(_T_4184, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[40] <= _T_4182 @[ifu_mem_ctl.scala 661:35] + node _T_4183 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4184 = eq(_T_4183, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4185 = and(_T_4184, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4186 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4185 : @[Reg.scala 28:19] _T_4186 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[41] <= _T_4186 @[ifu_mem_ctl.scala 653:35] - node _T_4187 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4188 = eq(_T_4187, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4189 = and(_T_4188, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[41] <= _T_4186 @[ifu_mem_ctl.scala 661:35] + node _T_4187 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4188 = eq(_T_4187, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4189 = and(_T_4188, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4190 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4189 : @[Reg.scala 28:19] _T_4190 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[42] <= _T_4190 @[ifu_mem_ctl.scala 653:35] - node _T_4191 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4192 = eq(_T_4191, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4193 = and(_T_4192, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[42] <= _T_4190 @[ifu_mem_ctl.scala 661:35] + node _T_4191 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4192 = eq(_T_4191, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4193 = and(_T_4192, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4194 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4193 : @[Reg.scala 28:19] _T_4194 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[43] <= _T_4194 @[ifu_mem_ctl.scala 653:35] - node _T_4195 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4196 = eq(_T_4195, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4197 = and(_T_4196, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[43] <= _T_4194 @[ifu_mem_ctl.scala 661:35] + node _T_4195 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4196 = eq(_T_4195, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4197 = and(_T_4196, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4198 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4197 : @[Reg.scala 28:19] _T_4198 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[44] <= _T_4198 @[ifu_mem_ctl.scala 653:35] - node _T_4199 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4200 = eq(_T_4199, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4201 = and(_T_4200, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[44] <= _T_4198 @[ifu_mem_ctl.scala 661:35] + node _T_4199 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4200 = eq(_T_4199, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4201 = and(_T_4200, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4202 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4201 : @[Reg.scala 28:19] _T_4202 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[45] <= _T_4202 @[ifu_mem_ctl.scala 653:35] - node _T_4203 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4204 = eq(_T_4203, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4205 = and(_T_4204, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[45] <= _T_4202 @[ifu_mem_ctl.scala 661:35] + node _T_4203 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4204 = eq(_T_4203, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4205 = and(_T_4204, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4206 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4205 : @[Reg.scala 28:19] _T_4206 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[46] <= _T_4206 @[ifu_mem_ctl.scala 653:35] - node _T_4207 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4208 = eq(_T_4207, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4209 = and(_T_4208, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[46] <= _T_4206 @[ifu_mem_ctl.scala 661:35] + node _T_4207 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4208 = eq(_T_4207, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4209 = and(_T_4208, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4210 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4209 : @[Reg.scala 28:19] _T_4210 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[47] <= _T_4210 @[ifu_mem_ctl.scala 653:35] - node _T_4211 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4212 = eq(_T_4211, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4213 = and(_T_4212, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[47] <= _T_4210 @[ifu_mem_ctl.scala 661:35] + node _T_4211 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4212 = eq(_T_4211, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4213 = and(_T_4212, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4214 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4213 : @[Reg.scala 28:19] _T_4214 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[48] <= _T_4214 @[ifu_mem_ctl.scala 653:35] - node _T_4215 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4216 = eq(_T_4215, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4217 = and(_T_4216, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[48] <= _T_4214 @[ifu_mem_ctl.scala 661:35] + node _T_4215 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4216 = eq(_T_4215, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4217 = and(_T_4216, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4218 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4217 : @[Reg.scala 28:19] _T_4218 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[49] <= _T_4218 @[ifu_mem_ctl.scala 653:35] - node _T_4219 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4220 = eq(_T_4219, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4221 = and(_T_4220, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[49] <= _T_4218 @[ifu_mem_ctl.scala 661:35] + node _T_4219 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4220 = eq(_T_4219, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4221 = and(_T_4220, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4222 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4221 : @[Reg.scala 28:19] _T_4222 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[50] <= _T_4222 @[ifu_mem_ctl.scala 653:35] - node _T_4223 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4224 = eq(_T_4223, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4225 = and(_T_4224, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[50] <= _T_4222 @[ifu_mem_ctl.scala 661:35] + node _T_4223 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4224 = eq(_T_4223, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4225 = and(_T_4224, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4226 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4225 : @[Reg.scala 28:19] _T_4226 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[51] <= _T_4226 @[ifu_mem_ctl.scala 653:35] - node _T_4227 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4228 = eq(_T_4227, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4229 = and(_T_4228, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[51] <= _T_4226 @[ifu_mem_ctl.scala 661:35] + node _T_4227 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4228 = eq(_T_4227, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4229 = and(_T_4228, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4230 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4229 : @[Reg.scala 28:19] _T_4230 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[52] <= _T_4230 @[ifu_mem_ctl.scala 653:35] - node _T_4231 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4232 = eq(_T_4231, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4233 = and(_T_4232, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[52] <= _T_4230 @[ifu_mem_ctl.scala 661:35] + node _T_4231 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4232 = eq(_T_4231, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4233 = and(_T_4232, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4234 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4233 : @[Reg.scala 28:19] _T_4234 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[53] <= _T_4234 @[ifu_mem_ctl.scala 653:35] - node _T_4235 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4236 = eq(_T_4235, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4237 = and(_T_4236, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[53] <= _T_4234 @[ifu_mem_ctl.scala 661:35] + node _T_4235 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4236 = eq(_T_4235, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4237 = and(_T_4236, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4238 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4237 : @[Reg.scala 28:19] _T_4238 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[54] <= _T_4238 @[ifu_mem_ctl.scala 653:35] - node _T_4239 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4240 = eq(_T_4239, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4241 = and(_T_4240, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[54] <= _T_4238 @[ifu_mem_ctl.scala 661:35] + node _T_4239 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4240 = eq(_T_4239, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4241 = and(_T_4240, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4242 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4241 : @[Reg.scala 28:19] _T_4242 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[55] <= _T_4242 @[ifu_mem_ctl.scala 653:35] - node _T_4243 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4244 = eq(_T_4243, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4245 = and(_T_4244, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[55] <= _T_4242 @[ifu_mem_ctl.scala 661:35] + node _T_4243 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4244 = eq(_T_4243, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4245 = and(_T_4244, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4246 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4245 : @[Reg.scala 28:19] _T_4246 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[56] <= _T_4246 @[ifu_mem_ctl.scala 653:35] - node _T_4247 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4248 = eq(_T_4247, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4249 = and(_T_4248, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[56] <= _T_4246 @[ifu_mem_ctl.scala 661:35] + node _T_4247 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4248 = eq(_T_4247, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4249 = and(_T_4248, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4250 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4249 : @[Reg.scala 28:19] _T_4250 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[57] <= _T_4250 @[ifu_mem_ctl.scala 653:35] - node _T_4251 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4252 = eq(_T_4251, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4253 = and(_T_4252, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[57] <= _T_4250 @[ifu_mem_ctl.scala 661:35] + node _T_4251 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4252 = eq(_T_4251, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4253 = and(_T_4252, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4254 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4253 : @[Reg.scala 28:19] _T_4254 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[58] <= _T_4254 @[ifu_mem_ctl.scala 653:35] - node _T_4255 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4256 = eq(_T_4255, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4257 = and(_T_4256, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[58] <= _T_4254 @[ifu_mem_ctl.scala 661:35] + node _T_4255 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4256 = eq(_T_4255, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4257 = and(_T_4256, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4258 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4257 : @[Reg.scala 28:19] _T_4258 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[59] <= _T_4258 @[ifu_mem_ctl.scala 653:35] - node _T_4259 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4260 = eq(_T_4259, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4261 = and(_T_4260, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[59] <= _T_4258 @[ifu_mem_ctl.scala 661:35] + node _T_4259 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4260 = eq(_T_4259, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4261 = and(_T_4260, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4262 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4261 : @[Reg.scala 28:19] _T_4262 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[60] <= _T_4262 @[ifu_mem_ctl.scala 653:35] - node _T_4263 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4264 = eq(_T_4263, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4265 = and(_T_4264, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[60] <= _T_4262 @[ifu_mem_ctl.scala 661:35] + node _T_4263 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4264 = eq(_T_4263, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4265 = and(_T_4264, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4266 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4265 : @[Reg.scala 28:19] _T_4266 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[61] <= _T_4266 @[ifu_mem_ctl.scala 653:35] - node _T_4267 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4268 = eq(_T_4267, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4269 = and(_T_4268, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[61] <= _T_4266 @[ifu_mem_ctl.scala 661:35] + node _T_4267 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4268 = eq(_T_4267, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4269 = and(_T_4268, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4270 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4269 : @[Reg.scala 28:19] _T_4270 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[62] <= _T_4270 @[ifu_mem_ctl.scala 653:35] - node _T_4271 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4272 = eq(_T_4271, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4273 = and(_T_4272, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[62] <= _T_4270 @[ifu_mem_ctl.scala 661:35] + node _T_4271 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4272 = eq(_T_4271, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4273 = and(_T_4272, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4274 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4273 : @[Reg.scala 28:19] _T_4274 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[63] <= _T_4274 @[ifu_mem_ctl.scala 653:35] - node _T_4275 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4276 = eq(_T_4275, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4277 = and(_T_4276, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[63] <= _T_4274 @[ifu_mem_ctl.scala 661:35] + node _T_4275 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4276 = eq(_T_4275, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4277 = and(_T_4276, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4278 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4277 : @[Reg.scala 28:19] _T_4278 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[64] <= _T_4278 @[ifu_mem_ctl.scala 653:35] - node _T_4279 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4280 = eq(_T_4279, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4281 = and(_T_4280, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[64] <= _T_4278 @[ifu_mem_ctl.scala 661:35] + node _T_4279 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4280 = eq(_T_4279, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4281 = and(_T_4280, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4282 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4281 : @[Reg.scala 28:19] _T_4282 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[65] <= _T_4282 @[ifu_mem_ctl.scala 653:35] - node _T_4283 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4284 = eq(_T_4283, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4285 = and(_T_4284, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[65] <= _T_4282 @[ifu_mem_ctl.scala 661:35] + node _T_4283 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4284 = eq(_T_4283, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4285 = and(_T_4284, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4286 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4285 : @[Reg.scala 28:19] _T_4286 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[66] <= _T_4286 @[ifu_mem_ctl.scala 653:35] - node _T_4287 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4288 = eq(_T_4287, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4289 = and(_T_4288, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[66] <= _T_4286 @[ifu_mem_ctl.scala 661:35] + node _T_4287 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4288 = eq(_T_4287, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4289 = and(_T_4288, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4290 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4289 : @[Reg.scala 28:19] _T_4290 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[67] <= _T_4290 @[ifu_mem_ctl.scala 653:35] - node _T_4291 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4292 = eq(_T_4291, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4293 = and(_T_4292, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[67] <= _T_4290 @[ifu_mem_ctl.scala 661:35] + node _T_4291 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4292 = eq(_T_4291, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4293 = and(_T_4292, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4294 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4293 : @[Reg.scala 28:19] _T_4294 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[68] <= _T_4294 @[ifu_mem_ctl.scala 653:35] - node _T_4295 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4296 = eq(_T_4295, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4297 = and(_T_4296, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[68] <= _T_4294 @[ifu_mem_ctl.scala 661:35] + node _T_4295 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4296 = eq(_T_4295, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4297 = and(_T_4296, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4298 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4297 : @[Reg.scala 28:19] _T_4298 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[69] <= _T_4298 @[ifu_mem_ctl.scala 653:35] - node _T_4299 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4300 = eq(_T_4299, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4301 = and(_T_4300, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[69] <= _T_4298 @[ifu_mem_ctl.scala 661:35] + node _T_4299 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4300 = eq(_T_4299, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4301 = and(_T_4300, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4302 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4301 : @[Reg.scala 28:19] _T_4302 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[70] <= _T_4302 @[ifu_mem_ctl.scala 653:35] - node _T_4303 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4304 = eq(_T_4303, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4305 = and(_T_4304, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[70] <= _T_4302 @[ifu_mem_ctl.scala 661:35] + node _T_4303 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4304 = eq(_T_4303, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4305 = and(_T_4304, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4306 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4305 : @[Reg.scala 28:19] _T_4306 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[71] <= _T_4306 @[ifu_mem_ctl.scala 653:35] - node _T_4307 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4308 = eq(_T_4307, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4309 = and(_T_4308, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[71] <= _T_4306 @[ifu_mem_ctl.scala 661:35] + node _T_4307 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4308 = eq(_T_4307, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4309 = and(_T_4308, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4310 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4309 : @[Reg.scala 28:19] _T_4310 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[72] <= _T_4310 @[ifu_mem_ctl.scala 653:35] - node _T_4311 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4312 = eq(_T_4311, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4313 = and(_T_4312, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[72] <= _T_4310 @[ifu_mem_ctl.scala 661:35] + node _T_4311 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4312 = eq(_T_4311, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4313 = and(_T_4312, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4314 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4313 : @[Reg.scala 28:19] _T_4314 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[73] <= _T_4314 @[ifu_mem_ctl.scala 653:35] - node _T_4315 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4316 = eq(_T_4315, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4317 = and(_T_4316, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[73] <= _T_4314 @[ifu_mem_ctl.scala 661:35] + node _T_4315 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4316 = eq(_T_4315, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4317 = and(_T_4316, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4318 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4317 : @[Reg.scala 28:19] _T_4318 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[74] <= _T_4318 @[ifu_mem_ctl.scala 653:35] - node _T_4319 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4320 = eq(_T_4319, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4321 = and(_T_4320, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[74] <= _T_4318 @[ifu_mem_ctl.scala 661:35] + node _T_4319 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4320 = eq(_T_4319, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4321 = and(_T_4320, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4322 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4321 : @[Reg.scala 28:19] _T_4322 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[75] <= _T_4322 @[ifu_mem_ctl.scala 653:35] - node _T_4323 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4324 = eq(_T_4323, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4325 = and(_T_4324, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[75] <= _T_4322 @[ifu_mem_ctl.scala 661:35] + node _T_4323 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4324 = eq(_T_4323, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4325 = and(_T_4324, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4326 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4325 : @[Reg.scala 28:19] _T_4326 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[76] <= _T_4326 @[ifu_mem_ctl.scala 653:35] - node _T_4327 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4328 = eq(_T_4327, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4329 = and(_T_4328, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[76] <= _T_4326 @[ifu_mem_ctl.scala 661:35] + node _T_4327 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4328 = eq(_T_4327, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4329 = and(_T_4328, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4330 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4329 : @[Reg.scala 28:19] _T_4330 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[77] <= _T_4330 @[ifu_mem_ctl.scala 653:35] - node _T_4331 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4332 = eq(_T_4331, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4333 = and(_T_4332, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[77] <= _T_4330 @[ifu_mem_ctl.scala 661:35] + node _T_4331 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4332 = eq(_T_4331, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4333 = and(_T_4332, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4334 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4333 : @[Reg.scala 28:19] _T_4334 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[78] <= _T_4334 @[ifu_mem_ctl.scala 653:35] - node _T_4335 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4336 = eq(_T_4335, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4337 = and(_T_4336, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[78] <= _T_4334 @[ifu_mem_ctl.scala 661:35] + node _T_4335 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4336 = eq(_T_4335, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4337 = and(_T_4336, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4338 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4337 : @[Reg.scala 28:19] _T_4338 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[79] <= _T_4338 @[ifu_mem_ctl.scala 653:35] - node _T_4339 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4340 = eq(_T_4339, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4341 = and(_T_4340, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[79] <= _T_4338 @[ifu_mem_ctl.scala 661:35] + node _T_4339 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4340 = eq(_T_4339, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4341 = and(_T_4340, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4342 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4341 : @[Reg.scala 28:19] _T_4342 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[80] <= _T_4342 @[ifu_mem_ctl.scala 653:35] - node _T_4343 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4344 = eq(_T_4343, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4345 = and(_T_4344, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[80] <= _T_4342 @[ifu_mem_ctl.scala 661:35] + node _T_4343 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4344 = eq(_T_4343, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4345 = and(_T_4344, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4346 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4345 : @[Reg.scala 28:19] _T_4346 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[81] <= _T_4346 @[ifu_mem_ctl.scala 653:35] - node _T_4347 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4348 = eq(_T_4347, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4349 = and(_T_4348, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[81] <= _T_4346 @[ifu_mem_ctl.scala 661:35] + node _T_4347 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4348 = eq(_T_4347, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4349 = and(_T_4348, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4350 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4349 : @[Reg.scala 28:19] _T_4350 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[82] <= _T_4350 @[ifu_mem_ctl.scala 653:35] - node _T_4351 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4352 = eq(_T_4351, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4353 = and(_T_4352, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[82] <= _T_4350 @[ifu_mem_ctl.scala 661:35] + node _T_4351 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4352 = eq(_T_4351, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4353 = and(_T_4352, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4354 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4353 : @[Reg.scala 28:19] _T_4354 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[83] <= _T_4354 @[ifu_mem_ctl.scala 653:35] - node _T_4355 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4356 = eq(_T_4355, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4357 = and(_T_4356, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[83] <= _T_4354 @[ifu_mem_ctl.scala 661:35] + node _T_4355 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4356 = eq(_T_4355, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4357 = and(_T_4356, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4358 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4357 : @[Reg.scala 28:19] _T_4358 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[84] <= _T_4358 @[ifu_mem_ctl.scala 653:35] - node _T_4359 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4360 = eq(_T_4359, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4361 = and(_T_4360, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[84] <= _T_4358 @[ifu_mem_ctl.scala 661:35] + node _T_4359 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4360 = eq(_T_4359, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4361 = and(_T_4360, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4362 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4361 : @[Reg.scala 28:19] _T_4362 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[85] <= _T_4362 @[ifu_mem_ctl.scala 653:35] - node _T_4363 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4364 = eq(_T_4363, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4365 = and(_T_4364, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[85] <= _T_4362 @[ifu_mem_ctl.scala 661:35] + node _T_4363 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4364 = eq(_T_4363, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4365 = and(_T_4364, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4366 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4365 : @[Reg.scala 28:19] _T_4366 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[86] <= _T_4366 @[ifu_mem_ctl.scala 653:35] - node _T_4367 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4368 = eq(_T_4367, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4369 = and(_T_4368, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[86] <= _T_4366 @[ifu_mem_ctl.scala 661:35] + node _T_4367 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4368 = eq(_T_4367, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4369 = and(_T_4368, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4370 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4369 : @[Reg.scala 28:19] _T_4370 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[87] <= _T_4370 @[ifu_mem_ctl.scala 653:35] - node _T_4371 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4372 = eq(_T_4371, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4373 = and(_T_4372, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[87] <= _T_4370 @[ifu_mem_ctl.scala 661:35] + node _T_4371 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4372 = eq(_T_4371, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4373 = and(_T_4372, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4374 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4373 : @[Reg.scala 28:19] _T_4374 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[88] <= _T_4374 @[ifu_mem_ctl.scala 653:35] - node _T_4375 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4376 = eq(_T_4375, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4377 = and(_T_4376, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[88] <= _T_4374 @[ifu_mem_ctl.scala 661:35] + node _T_4375 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4376 = eq(_T_4375, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4377 = and(_T_4376, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4378 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4377 : @[Reg.scala 28:19] _T_4378 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[89] <= _T_4378 @[ifu_mem_ctl.scala 653:35] - node _T_4379 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4380 = eq(_T_4379, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4381 = and(_T_4380, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[89] <= _T_4378 @[ifu_mem_ctl.scala 661:35] + node _T_4379 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4380 = eq(_T_4379, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4381 = and(_T_4380, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4382 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4381 : @[Reg.scala 28:19] _T_4382 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[90] <= _T_4382 @[ifu_mem_ctl.scala 653:35] - node _T_4383 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4384 = eq(_T_4383, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4385 = and(_T_4384, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[90] <= _T_4382 @[ifu_mem_ctl.scala 661:35] + node _T_4383 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4384 = eq(_T_4383, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4385 = and(_T_4384, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4386 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4385 : @[Reg.scala 28:19] _T_4386 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[91] <= _T_4386 @[ifu_mem_ctl.scala 653:35] - node _T_4387 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4388 = eq(_T_4387, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4389 = and(_T_4388, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[91] <= _T_4386 @[ifu_mem_ctl.scala 661:35] + node _T_4387 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4388 = eq(_T_4387, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4389 = and(_T_4388, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4390 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4389 : @[Reg.scala 28:19] _T_4390 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[92] <= _T_4390 @[ifu_mem_ctl.scala 653:35] - node _T_4391 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4392 = eq(_T_4391, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4393 = and(_T_4392, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[92] <= _T_4390 @[ifu_mem_ctl.scala 661:35] + node _T_4391 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4392 = eq(_T_4391, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4393 = and(_T_4392, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4394 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4393 : @[Reg.scala 28:19] _T_4394 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[93] <= _T_4394 @[ifu_mem_ctl.scala 653:35] - node _T_4395 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4396 = eq(_T_4395, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4397 = and(_T_4396, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[93] <= _T_4394 @[ifu_mem_ctl.scala 661:35] + node _T_4395 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4396 = eq(_T_4395, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4397 = and(_T_4396, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4398 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4397 : @[Reg.scala 28:19] _T_4398 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[94] <= _T_4398 @[ifu_mem_ctl.scala 653:35] - node _T_4399 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4400 = eq(_T_4399, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4401 = and(_T_4400, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[94] <= _T_4398 @[ifu_mem_ctl.scala 661:35] + node _T_4399 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4400 = eq(_T_4399, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4401 = and(_T_4400, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4402 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4401 : @[Reg.scala 28:19] _T_4402 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[95] <= _T_4402 @[ifu_mem_ctl.scala 653:35] - node _T_4403 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4404 = eq(_T_4403, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4405 = and(_T_4404, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[95] <= _T_4402 @[ifu_mem_ctl.scala 661:35] + node _T_4403 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4404 = eq(_T_4403, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4405 = and(_T_4404, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4406 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4405 : @[Reg.scala 28:19] _T_4406 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[96] <= _T_4406 @[ifu_mem_ctl.scala 653:35] - node _T_4407 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4408 = eq(_T_4407, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4409 = and(_T_4408, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[96] <= _T_4406 @[ifu_mem_ctl.scala 661:35] + node _T_4407 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4408 = eq(_T_4407, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4409 = and(_T_4408, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4410 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4409 : @[Reg.scala 28:19] _T_4410 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[97] <= _T_4410 @[ifu_mem_ctl.scala 653:35] - node _T_4411 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4412 = eq(_T_4411, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4413 = and(_T_4412, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[97] <= _T_4410 @[ifu_mem_ctl.scala 661:35] + node _T_4411 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4412 = eq(_T_4411, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4413 = and(_T_4412, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4414 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4413 : @[Reg.scala 28:19] _T_4414 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[98] <= _T_4414 @[ifu_mem_ctl.scala 653:35] - node _T_4415 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4416 = eq(_T_4415, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4417 = and(_T_4416, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[98] <= _T_4414 @[ifu_mem_ctl.scala 661:35] + node _T_4415 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4416 = eq(_T_4415, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4417 = and(_T_4416, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4418 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4417 : @[Reg.scala 28:19] _T_4418 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[99] <= _T_4418 @[ifu_mem_ctl.scala 653:35] - node _T_4419 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4420 = eq(_T_4419, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4421 = and(_T_4420, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[99] <= _T_4418 @[ifu_mem_ctl.scala 661:35] + node _T_4419 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4420 = eq(_T_4419, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4421 = and(_T_4420, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4422 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4421 : @[Reg.scala 28:19] _T_4422 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[100] <= _T_4422 @[ifu_mem_ctl.scala 653:35] - node _T_4423 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4424 = eq(_T_4423, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4425 = and(_T_4424, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[100] <= _T_4422 @[ifu_mem_ctl.scala 661:35] + node _T_4423 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4424 = eq(_T_4423, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4425 = and(_T_4424, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4426 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4425 : @[Reg.scala 28:19] _T_4426 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[101] <= _T_4426 @[ifu_mem_ctl.scala 653:35] - node _T_4427 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4428 = eq(_T_4427, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4429 = and(_T_4428, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[101] <= _T_4426 @[ifu_mem_ctl.scala 661:35] + node _T_4427 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4428 = eq(_T_4427, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4429 = and(_T_4428, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4430 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4429 : @[Reg.scala 28:19] _T_4430 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[102] <= _T_4430 @[ifu_mem_ctl.scala 653:35] - node _T_4431 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4432 = eq(_T_4431, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4433 = and(_T_4432, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[102] <= _T_4430 @[ifu_mem_ctl.scala 661:35] + node _T_4431 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4432 = eq(_T_4431, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4433 = and(_T_4432, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4434 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4433 : @[Reg.scala 28:19] _T_4434 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[103] <= _T_4434 @[ifu_mem_ctl.scala 653:35] - node _T_4435 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4436 = eq(_T_4435, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4437 = and(_T_4436, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[103] <= _T_4434 @[ifu_mem_ctl.scala 661:35] + node _T_4435 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4436 = eq(_T_4435, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4437 = and(_T_4436, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4438 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4437 : @[Reg.scala 28:19] _T_4438 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[104] <= _T_4438 @[ifu_mem_ctl.scala 653:35] - node _T_4439 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4440 = eq(_T_4439, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4441 = and(_T_4440, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[104] <= _T_4438 @[ifu_mem_ctl.scala 661:35] + node _T_4439 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4440 = eq(_T_4439, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4441 = and(_T_4440, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4442 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4441 : @[Reg.scala 28:19] _T_4442 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[105] <= _T_4442 @[ifu_mem_ctl.scala 653:35] - node _T_4443 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4444 = eq(_T_4443, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4445 = and(_T_4444, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[105] <= _T_4442 @[ifu_mem_ctl.scala 661:35] + node _T_4443 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4444 = eq(_T_4443, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4445 = and(_T_4444, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4446 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4445 : @[Reg.scala 28:19] _T_4446 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[106] <= _T_4446 @[ifu_mem_ctl.scala 653:35] - node _T_4447 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4448 = eq(_T_4447, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4449 = and(_T_4448, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[106] <= _T_4446 @[ifu_mem_ctl.scala 661:35] + node _T_4447 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4448 = eq(_T_4447, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4449 = and(_T_4448, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4450 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4449 : @[Reg.scala 28:19] _T_4450 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[107] <= _T_4450 @[ifu_mem_ctl.scala 653:35] - node _T_4451 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4452 = eq(_T_4451, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4453 = and(_T_4452, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[107] <= _T_4450 @[ifu_mem_ctl.scala 661:35] + node _T_4451 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4452 = eq(_T_4451, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4453 = and(_T_4452, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4454 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4453 : @[Reg.scala 28:19] _T_4454 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[108] <= _T_4454 @[ifu_mem_ctl.scala 653:35] - node _T_4455 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4456 = eq(_T_4455, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4457 = and(_T_4456, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[108] <= _T_4454 @[ifu_mem_ctl.scala 661:35] + node _T_4455 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4456 = eq(_T_4455, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4457 = and(_T_4456, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4458 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4457 : @[Reg.scala 28:19] _T_4458 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[109] <= _T_4458 @[ifu_mem_ctl.scala 653:35] - node _T_4459 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4460 = eq(_T_4459, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4461 = and(_T_4460, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[109] <= _T_4458 @[ifu_mem_ctl.scala 661:35] + node _T_4459 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4460 = eq(_T_4459, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4461 = and(_T_4460, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4462 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4461 : @[Reg.scala 28:19] _T_4462 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[110] <= _T_4462 @[ifu_mem_ctl.scala 653:35] - node _T_4463 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4464 = eq(_T_4463, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4465 = and(_T_4464, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[110] <= _T_4462 @[ifu_mem_ctl.scala 661:35] + node _T_4463 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4464 = eq(_T_4463, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4465 = and(_T_4464, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4466 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4465 : @[Reg.scala 28:19] _T_4466 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[111] <= _T_4466 @[ifu_mem_ctl.scala 653:35] - node _T_4467 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4468 = eq(_T_4467, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4469 = and(_T_4468, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[111] <= _T_4466 @[ifu_mem_ctl.scala 661:35] + node _T_4467 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4468 = eq(_T_4467, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4469 = and(_T_4468, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4470 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4469 : @[Reg.scala 28:19] _T_4470 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[112] <= _T_4470 @[ifu_mem_ctl.scala 653:35] - node _T_4471 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4472 = eq(_T_4471, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4473 = and(_T_4472, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[112] <= _T_4470 @[ifu_mem_ctl.scala 661:35] + node _T_4471 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4472 = eq(_T_4471, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4473 = and(_T_4472, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4474 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4473 : @[Reg.scala 28:19] _T_4474 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[113] <= _T_4474 @[ifu_mem_ctl.scala 653:35] - node _T_4475 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4476 = eq(_T_4475, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4477 = and(_T_4476, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[113] <= _T_4474 @[ifu_mem_ctl.scala 661:35] + node _T_4475 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4476 = eq(_T_4475, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4477 = and(_T_4476, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4478 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4477 : @[Reg.scala 28:19] _T_4478 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[114] <= _T_4478 @[ifu_mem_ctl.scala 653:35] - node _T_4479 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4480 = eq(_T_4479, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4481 = and(_T_4480, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[114] <= _T_4478 @[ifu_mem_ctl.scala 661:35] + node _T_4479 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4480 = eq(_T_4479, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4481 = and(_T_4480, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4482 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4481 : @[Reg.scala 28:19] _T_4482 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[115] <= _T_4482 @[ifu_mem_ctl.scala 653:35] - node _T_4483 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4484 = eq(_T_4483, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4485 = and(_T_4484, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[115] <= _T_4482 @[ifu_mem_ctl.scala 661:35] + node _T_4483 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4484 = eq(_T_4483, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4485 = and(_T_4484, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4486 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4485 : @[Reg.scala 28:19] _T_4486 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[116] <= _T_4486 @[ifu_mem_ctl.scala 653:35] - node _T_4487 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4488 = eq(_T_4487, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4489 = and(_T_4488, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[116] <= _T_4486 @[ifu_mem_ctl.scala 661:35] + node _T_4487 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4488 = eq(_T_4487, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4489 = and(_T_4488, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4490 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4489 : @[Reg.scala 28:19] _T_4490 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[117] <= _T_4490 @[ifu_mem_ctl.scala 653:35] - node _T_4491 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4492 = eq(_T_4491, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4493 = and(_T_4492, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[117] <= _T_4490 @[ifu_mem_ctl.scala 661:35] + node _T_4491 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4492 = eq(_T_4491, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4493 = and(_T_4492, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4494 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4493 : @[Reg.scala 28:19] _T_4494 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[118] <= _T_4494 @[ifu_mem_ctl.scala 653:35] - node _T_4495 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4496 = eq(_T_4495, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4497 = and(_T_4496, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[118] <= _T_4494 @[ifu_mem_ctl.scala 661:35] + node _T_4495 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4496 = eq(_T_4495, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4497 = and(_T_4496, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4498 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4497 : @[Reg.scala 28:19] _T_4498 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[119] <= _T_4498 @[ifu_mem_ctl.scala 653:35] - node _T_4499 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4500 = eq(_T_4499, UInt<1>("h00")) @[ifu_mem_ctl.scala 653:128] - node _T_4501 = and(_T_4500, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[119] <= _T_4498 @[ifu_mem_ctl.scala 661:35] + node _T_4499 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4500 = eq(_T_4499, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] + node _T_4501 = and(_T_4500, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4502 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4501 : @[Reg.scala 28:19] _T_4502 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[120] <= _T_4502 @[ifu_mem_ctl.scala 653:35] - node _T_4503 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4504 = eq(_T_4503, UInt<1>("h01")) @[ifu_mem_ctl.scala 653:128] - node _T_4505 = and(_T_4504, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[120] <= _T_4502 @[ifu_mem_ctl.scala 661:35] + node _T_4503 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4504 = eq(_T_4503, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] + node _T_4505 = and(_T_4504, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4506 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4505 : @[Reg.scala 28:19] _T_4506 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[121] <= _T_4506 @[ifu_mem_ctl.scala 653:35] - node _T_4507 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4508 = eq(_T_4507, UInt<2>("h02")) @[ifu_mem_ctl.scala 653:128] - node _T_4509 = and(_T_4508, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[121] <= _T_4506 @[ifu_mem_ctl.scala 661:35] + node _T_4507 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4508 = eq(_T_4507, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] + node _T_4509 = and(_T_4508, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4510 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4509 : @[Reg.scala 28:19] _T_4510 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[122] <= _T_4510 @[ifu_mem_ctl.scala 653:35] - node _T_4511 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4512 = eq(_T_4511, UInt<2>("h03")) @[ifu_mem_ctl.scala 653:128] - node _T_4513 = and(_T_4512, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[122] <= _T_4510 @[ifu_mem_ctl.scala 661:35] + node _T_4511 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4512 = eq(_T_4511, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] + node _T_4513 = and(_T_4512, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4514 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4513 : @[Reg.scala 28:19] _T_4514 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[123] <= _T_4514 @[ifu_mem_ctl.scala 653:35] - node _T_4515 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4516 = eq(_T_4515, UInt<3>("h04")) @[ifu_mem_ctl.scala 653:128] - node _T_4517 = and(_T_4516, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[123] <= _T_4514 @[ifu_mem_ctl.scala 661:35] + node _T_4515 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4516 = eq(_T_4515, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] + node _T_4517 = and(_T_4516, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4518 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4517 : @[Reg.scala 28:19] _T_4518 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[124] <= _T_4518 @[ifu_mem_ctl.scala 653:35] - node _T_4519 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4520 = eq(_T_4519, UInt<3>("h05")) @[ifu_mem_ctl.scala 653:128] - node _T_4521 = and(_T_4520, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[124] <= _T_4518 @[ifu_mem_ctl.scala 661:35] + node _T_4519 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4520 = eq(_T_4519, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] + node _T_4521 = and(_T_4520, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4522 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4521 : @[Reg.scala 28:19] _T_4522 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[125] <= _T_4522 @[ifu_mem_ctl.scala 653:35] - node _T_4523 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4524 = eq(_T_4523, UInt<3>("h06")) @[ifu_mem_ctl.scala 653:128] - node _T_4525 = and(_T_4524, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[125] <= _T_4522 @[ifu_mem_ctl.scala 661:35] + node _T_4523 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4524 = eq(_T_4523, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] + node _T_4525 = and(_T_4524, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4526 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4525 : @[Reg.scala 28:19] _T_4526 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[126] <= _T_4526 @[ifu_mem_ctl.scala 653:35] - node _T_4527 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 653:123] - node _T_4528 = eq(_T_4527, UInt<3>("h07")) @[ifu_mem_ctl.scala 653:128] - node _T_4529 = and(_T_4528, way_status_wr_en_ff) @[ifu_mem_ctl.scala 653:136] + way_status_out[126] <= _T_4526 @[ifu_mem_ctl.scala 661:35] + node _T_4527 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] + node _T_4528 = eq(_T_4527, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] + node _T_4529 = and(_T_4528, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] reg _T_4530 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4529 : @[Reg.scala 28:19] _T_4530 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[127] <= _T_4530 @[ifu_mem_ctl.scala 653:35] + way_status_out[127] <= _T_4530 @[ifu_mem_ctl.scala 661:35] node _T_4531 = cat(way_status_out[127], way_status_out[126]) @[Cat.scala 29:58] node _T_4532 = cat(_T_4531, way_status_out[125]) @[Cat.scala 29:58] node _T_4533 = cat(_T_4532, way_status_out[124]) @[Cat.scala 29:58] @@ -9446,134 +9446,134 @@ circuit quasar_wrapper : node _T_4669 = cat(_T_4668, way_status_clken_2) @[Cat.scala 29:58] node _T_4670 = cat(_T_4669, way_status_clken_1) @[Cat.scala 29:58] node test_way_status_clken = cat(_T_4670, way_status_clken_0) @[Cat.scala 29:58] - node _T_4671 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 658:80] - node _T_4672 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 658:80] - node _T_4673 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 658:80] - node _T_4674 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 658:80] - node _T_4675 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 658:80] - node _T_4676 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 658:80] - node _T_4677 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 658:80] - node _T_4678 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 658:80] - node _T_4679 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 658:80] - node _T_4680 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 658:80] - node _T_4681 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 658:80] - node _T_4682 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 658:80] - node _T_4683 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 658:80] - node _T_4684 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 658:80] - node _T_4685 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 658:80] - node _T_4686 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 658:80] - node _T_4687 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 658:80] - node _T_4688 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 658:80] - node _T_4689 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 658:80] - node _T_4690 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 658:80] - node _T_4691 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 658:80] - node _T_4692 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 658:80] - node _T_4693 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 658:80] - node _T_4694 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 658:80] - node _T_4695 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 658:80] - node _T_4696 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 658:80] - node _T_4697 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 658:80] - node _T_4698 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 658:80] - node _T_4699 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 658:80] - node _T_4700 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 658:80] - node _T_4701 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 658:80] - node _T_4702 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 658:80] - node _T_4703 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 658:80] - node _T_4704 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 658:80] - node _T_4705 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 658:80] - node _T_4706 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 658:80] - node _T_4707 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 658:80] - node _T_4708 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 658:80] - node _T_4709 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 658:80] - node _T_4710 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 658:80] - node _T_4711 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 658:80] - node _T_4712 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 658:80] - node _T_4713 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 658:80] - node _T_4714 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 658:80] - node _T_4715 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 658:80] - node _T_4716 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 658:80] - node _T_4717 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 658:80] - node _T_4718 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 658:80] - node _T_4719 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 658:80] - node _T_4720 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 658:80] - node _T_4721 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 658:80] - node _T_4722 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 658:80] - node _T_4723 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 658:80] - node _T_4724 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 658:80] - node _T_4725 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 658:80] - node _T_4726 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 658:80] - node _T_4727 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 658:80] - node _T_4728 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 658:80] - node _T_4729 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 658:80] - node _T_4730 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 658:80] - node _T_4731 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 658:80] - node _T_4732 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 658:80] - node _T_4733 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 658:80] - node _T_4734 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 658:80] - node _T_4735 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 658:80] - node _T_4736 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 658:80] - node _T_4737 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 658:80] - node _T_4738 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 658:80] - node _T_4739 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 658:80] - node _T_4740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 658:80] - node _T_4741 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 658:80] - node _T_4742 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 658:80] - node _T_4743 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 658:80] - node _T_4744 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 658:80] - node _T_4745 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 658:80] - node _T_4746 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 658:80] - node _T_4747 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 658:80] - node _T_4748 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 658:80] - node _T_4749 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 658:80] - node _T_4750 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 658:80] - node _T_4751 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 658:80] - node _T_4752 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 658:80] - node _T_4753 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 658:80] - node _T_4754 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 658:80] - node _T_4755 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 658:80] - node _T_4756 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 658:80] - node _T_4757 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 658:80] - node _T_4758 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 658:80] - node _T_4759 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 658:80] - node _T_4760 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 658:80] - node _T_4761 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 658:80] - node _T_4762 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 658:80] - node _T_4763 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 658:80] - node _T_4764 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 658:80] - node _T_4765 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 658:80] - node _T_4766 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 658:80] - node _T_4767 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 658:80] - node _T_4768 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 658:80] - node _T_4769 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 658:80] - node _T_4770 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 658:80] - node _T_4771 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 658:80] - node _T_4772 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 658:80] - node _T_4773 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 658:80] - node _T_4774 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 658:80] - node _T_4775 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 658:80] - node _T_4776 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 658:80] - node _T_4777 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 658:80] - node _T_4778 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 658:80] - node _T_4779 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 658:80] - node _T_4780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 658:80] - node _T_4781 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 658:80] - node _T_4782 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 658:80] - node _T_4783 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 658:80] - node _T_4784 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 658:80] - node _T_4785 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 658:80] - node _T_4786 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 658:80] - node _T_4787 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 658:80] - node _T_4788 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 658:80] - node _T_4789 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 658:80] - node _T_4790 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 658:80] - node _T_4791 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 658:80] - node _T_4792 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 658:80] - node _T_4793 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 658:80] - node _T_4794 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 658:80] - node _T_4795 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 658:80] - node _T_4796 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 658:80] - node _T_4797 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 658:80] - node _T_4798 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 658:80] + node _T_4671 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 666:80] + node _T_4672 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 666:80] + node _T_4673 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 666:80] + node _T_4674 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 666:80] + node _T_4675 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 666:80] + node _T_4676 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 666:80] + node _T_4677 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 666:80] + node _T_4678 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 666:80] + node _T_4679 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 666:80] + node _T_4680 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 666:80] + node _T_4681 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 666:80] + node _T_4682 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 666:80] + node _T_4683 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 666:80] + node _T_4684 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 666:80] + node _T_4685 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 666:80] + node _T_4686 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 666:80] + node _T_4687 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 666:80] + node _T_4688 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 666:80] + node _T_4689 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 666:80] + node _T_4690 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 666:80] + node _T_4691 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 666:80] + node _T_4692 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 666:80] + node _T_4693 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 666:80] + node _T_4694 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 666:80] + node _T_4695 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 666:80] + node _T_4696 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 666:80] + node _T_4697 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 666:80] + node _T_4698 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 666:80] + node _T_4699 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 666:80] + node _T_4700 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 666:80] + node _T_4701 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 666:80] + node _T_4702 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 666:80] + node _T_4703 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 666:80] + node _T_4704 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 666:80] + node _T_4705 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 666:80] + node _T_4706 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 666:80] + node _T_4707 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 666:80] + node _T_4708 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 666:80] + node _T_4709 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 666:80] + node _T_4710 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 666:80] + node _T_4711 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 666:80] + node _T_4712 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 666:80] + node _T_4713 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 666:80] + node _T_4714 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 666:80] + node _T_4715 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 666:80] + node _T_4716 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 666:80] + node _T_4717 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 666:80] + node _T_4718 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 666:80] + node _T_4719 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 666:80] + node _T_4720 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 666:80] + node _T_4721 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 666:80] + node _T_4722 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 666:80] + node _T_4723 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 666:80] + node _T_4724 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 666:80] + node _T_4725 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 666:80] + node _T_4726 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 666:80] + node _T_4727 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 666:80] + node _T_4728 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 666:80] + node _T_4729 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 666:80] + node _T_4730 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 666:80] + node _T_4731 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 666:80] + node _T_4732 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 666:80] + node _T_4733 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 666:80] + node _T_4734 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 666:80] + node _T_4735 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 666:80] + node _T_4736 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 666:80] + node _T_4737 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 666:80] + node _T_4738 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 666:80] + node _T_4739 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 666:80] + node _T_4740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 666:80] + node _T_4741 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 666:80] + node _T_4742 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 666:80] + node _T_4743 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 666:80] + node _T_4744 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 666:80] + node _T_4745 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 666:80] + node _T_4746 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 666:80] + node _T_4747 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 666:80] + node _T_4748 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 666:80] + node _T_4749 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 666:80] + node _T_4750 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 666:80] + node _T_4751 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 666:80] + node _T_4752 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 666:80] + node _T_4753 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 666:80] + node _T_4754 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 666:80] + node _T_4755 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 666:80] + node _T_4756 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 666:80] + node _T_4757 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 666:80] + node _T_4758 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 666:80] + node _T_4759 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 666:80] + node _T_4760 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 666:80] + node _T_4761 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 666:80] + node _T_4762 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 666:80] + node _T_4763 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 666:80] + node _T_4764 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 666:80] + node _T_4765 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 666:80] + node _T_4766 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 666:80] + node _T_4767 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 666:80] + node _T_4768 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 666:80] + node _T_4769 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 666:80] + node _T_4770 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 666:80] + node _T_4771 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 666:80] + node _T_4772 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 666:80] + node _T_4773 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 666:80] + node _T_4774 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 666:80] + node _T_4775 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 666:80] + node _T_4776 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 666:80] + node _T_4777 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 666:80] + node _T_4778 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 666:80] + node _T_4779 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 666:80] + node _T_4780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 666:80] + node _T_4781 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 666:80] + node _T_4782 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 666:80] + node _T_4783 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 666:80] + node _T_4784 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 666:80] + node _T_4785 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 666:80] + node _T_4786 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 666:80] + node _T_4787 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 666:80] + node _T_4788 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 666:80] + node _T_4789 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 666:80] + node _T_4790 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 666:80] + node _T_4791 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 666:80] + node _T_4792 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 666:80] + node _T_4793 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 666:80] + node _T_4794 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 666:80] + node _T_4795 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 666:80] + node _T_4796 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 666:80] + node _T_4797 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 666:80] + node _T_4798 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 666:80] node _T_4799 = mux(_T_4671, way_status_out[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4800 = mux(_T_4672, way_status_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4801 = mux(_T_4673, way_status_out[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -9831,5915 +9831,5915 @@ circuit quasar_wrapper : node _T_5053 = or(_T_5052, _T_4926) @[Mux.scala 27:72] wire _T_5054 : UInt<1> @[Mux.scala 27:72] _T_5054 <= _T_5053 @[Mux.scala 27:72] - way_status <= _T_5054 @[ifu_mem_ctl.scala 658:14] - node _T_5055 = or(io.ic.debug_rd_en, io.ic.debug_wr_en) @[ifu_mem_ctl.scala 659:61] - node _T_5056 = and(_T_5055, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 659:82] - node _T_5057 = bits(io.ic.debug_addr, 9, 3) @[ifu_mem_ctl.scala 660:23] - node _T_5058 = bits(ifu_ic_rw_int_addr, 11, 5) @[ifu_mem_ctl.scala 660:89] - node ifu_ic_rw_int_addr_w_debug = mux(_T_5056, _T_5057, _T_5058) @[ifu_mem_ctl.scala 659:41] - reg _T_5059 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 662:14] - _T_5059 <= ifu_ic_rw_int_addr_w_debug @[ifu_mem_ctl.scala 662:14] - ifu_ic_rw_int_addr_ff <= _T_5059 @[ifu_mem_ctl.scala 661:27] + way_status <= _T_5054 @[ifu_mem_ctl.scala 666:14] + node _T_5055 = or(io.ic.debug_rd_en, io.ic.debug_wr_en) @[ifu_mem_ctl.scala 667:61] + node _T_5056 = and(_T_5055, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 667:82] + node _T_5057 = bits(io.ic.debug_addr, 9, 3) @[ifu_mem_ctl.scala 668:23] + node _T_5058 = bits(ifu_ic_rw_int_addr, 11, 5) @[ifu_mem_ctl.scala 668:89] + node ifu_ic_rw_int_addr_w_debug = mux(_T_5056, _T_5057, _T_5058) @[ifu_mem_ctl.scala 667:41] + reg _T_5059 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 670:14] + _T_5059 <= ifu_ic_rw_int_addr_w_debug @[ifu_mem_ctl.scala 670:14] + ifu_ic_rw_int_addr_ff <= _T_5059 @[ifu_mem_ctl.scala 669:27] wire ifu_tag_wren : UInt<2> ifu_tag_wren <= UInt<1>("h00") wire ic_debug_tag_wr_en : UInt<2> ic_debug_tag_wr_en <= UInt<1>("h00") - node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[ifu_mem_ctl.scala 666:45] - reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 668:14] - ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[ifu_mem_ctl.scala 668:14] - node _T_5060 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 670:50] - node _T_5061 = bits(io.ic.debug_wr_data, 0, 0) @[ifu_mem_ctl.scala 670:94] - node ic_valid_w_debug = mux(_T_5060, _T_5061, ic_valid) @[ifu_mem_ctl.scala 670:31] - reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 672:14] - ic_valid_ff <= ic_valid_w_debug @[ifu_mem_ctl.scala 672:14] - node _T_5062 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 676:35] - node _T_5063 = eq(_T_5062, UInt<1>("h00")) @[ifu_mem_ctl.scala 676:78] - node _T_5064 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 676:104] - node _T_5065 = and(_T_5063, _T_5064) @[ifu_mem_ctl.scala 676:87] - node _T_5066 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 677:27] - node _T_5067 = eq(_T_5066, UInt<1>("h00")) @[ifu_mem_ctl.scala 677:70] - node _T_5068 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 677:97] - node _T_5069 = and(_T_5067, _T_5068) @[ifu_mem_ctl.scala 677:79] - node _T_5070 = or(_T_5065, _T_5069) @[ifu_mem_ctl.scala 676:109] - node _T_5071 = or(_T_5070, reset_all_tags) @[ifu_mem_ctl.scala 677:102] - node _T_5072 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 676:35] - node _T_5073 = eq(_T_5072, UInt<1>("h00")) @[ifu_mem_ctl.scala 676:78] - node _T_5074 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 676:104] - node _T_5075 = and(_T_5073, _T_5074) @[ifu_mem_ctl.scala 676:87] - node _T_5076 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 677:27] - node _T_5077 = eq(_T_5076, UInt<1>("h00")) @[ifu_mem_ctl.scala 677:70] - node _T_5078 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 677:97] - node _T_5079 = and(_T_5077, _T_5078) @[ifu_mem_ctl.scala 677:79] - node _T_5080 = or(_T_5075, _T_5079) @[ifu_mem_ctl.scala 676:109] - node _T_5081 = or(_T_5080, reset_all_tags) @[ifu_mem_ctl.scala 677:102] + node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[ifu_mem_ctl.scala 674:45] + reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 676:14] + ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[ifu_mem_ctl.scala 676:14] + node _T_5060 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 678:50] + node _T_5061 = bits(io.ic.debug_wr_data, 0, 0) @[ifu_mem_ctl.scala 678:94] + node ic_valid_w_debug = mux(_T_5060, _T_5061, ic_valid) @[ifu_mem_ctl.scala 678:31] + reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 680:14] + ic_valid_ff <= ic_valid_w_debug @[ifu_mem_ctl.scala 680:14] + node _T_5062 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] + node _T_5063 = eq(_T_5062, UInt<1>("h00")) @[ifu_mem_ctl.scala 684:78] + node _T_5064 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 684:104] + node _T_5065 = and(_T_5063, _T_5064) @[ifu_mem_ctl.scala 684:87] + node _T_5066 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] + node _T_5067 = eq(_T_5066, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:70] + node _T_5068 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 685:97] + node _T_5069 = and(_T_5067, _T_5068) @[ifu_mem_ctl.scala 685:79] + node _T_5070 = or(_T_5065, _T_5069) @[ifu_mem_ctl.scala 684:109] + node _T_5071 = or(_T_5070, reset_all_tags) @[ifu_mem_ctl.scala 685:102] + node _T_5072 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] + node _T_5073 = eq(_T_5072, UInt<1>("h00")) @[ifu_mem_ctl.scala 684:78] + node _T_5074 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 684:104] + node _T_5075 = and(_T_5073, _T_5074) @[ifu_mem_ctl.scala 684:87] + node _T_5076 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] + node _T_5077 = eq(_T_5076, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:70] + node _T_5078 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 685:97] + node _T_5079 = and(_T_5077, _T_5078) @[ifu_mem_ctl.scala 685:79] + node _T_5080 = or(_T_5075, _T_5079) @[ifu_mem_ctl.scala 684:109] + node _T_5081 = or(_T_5080, reset_all_tags) @[ifu_mem_ctl.scala 685:102] node tag_valid_clken_0 = cat(_T_5081, _T_5071) @[Cat.scala 29:58] - node _T_5082 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 676:35] - node _T_5083 = eq(_T_5082, UInt<1>("h01")) @[ifu_mem_ctl.scala 676:78] - node _T_5084 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 676:104] - node _T_5085 = and(_T_5083, _T_5084) @[ifu_mem_ctl.scala 676:87] - node _T_5086 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 677:27] - node _T_5087 = eq(_T_5086, UInt<1>("h01")) @[ifu_mem_ctl.scala 677:70] - node _T_5088 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 677:97] - node _T_5089 = and(_T_5087, _T_5088) @[ifu_mem_ctl.scala 677:79] - node _T_5090 = or(_T_5085, _T_5089) @[ifu_mem_ctl.scala 676:109] - node _T_5091 = or(_T_5090, reset_all_tags) @[ifu_mem_ctl.scala 677:102] - node _T_5092 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 676:35] - node _T_5093 = eq(_T_5092, UInt<1>("h01")) @[ifu_mem_ctl.scala 676:78] - node _T_5094 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 676:104] - node _T_5095 = and(_T_5093, _T_5094) @[ifu_mem_ctl.scala 676:87] - node _T_5096 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 677:27] - node _T_5097 = eq(_T_5096, UInt<1>("h01")) @[ifu_mem_ctl.scala 677:70] - node _T_5098 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 677:97] - node _T_5099 = and(_T_5097, _T_5098) @[ifu_mem_ctl.scala 677:79] - node _T_5100 = or(_T_5095, _T_5099) @[ifu_mem_ctl.scala 676:109] - node _T_5101 = or(_T_5100, reset_all_tags) @[ifu_mem_ctl.scala 677:102] + node _T_5082 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] + node _T_5083 = eq(_T_5082, UInt<1>("h01")) @[ifu_mem_ctl.scala 684:78] + node _T_5084 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 684:104] + node _T_5085 = and(_T_5083, _T_5084) @[ifu_mem_ctl.scala 684:87] + node _T_5086 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] + node _T_5087 = eq(_T_5086, UInt<1>("h01")) @[ifu_mem_ctl.scala 685:70] + node _T_5088 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 685:97] + node _T_5089 = and(_T_5087, _T_5088) @[ifu_mem_ctl.scala 685:79] + node _T_5090 = or(_T_5085, _T_5089) @[ifu_mem_ctl.scala 684:109] + node _T_5091 = or(_T_5090, reset_all_tags) @[ifu_mem_ctl.scala 685:102] + node _T_5092 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] + node _T_5093 = eq(_T_5092, UInt<1>("h01")) @[ifu_mem_ctl.scala 684:78] + node _T_5094 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 684:104] + node _T_5095 = and(_T_5093, _T_5094) @[ifu_mem_ctl.scala 684:87] + node _T_5096 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] + node _T_5097 = eq(_T_5096, UInt<1>("h01")) @[ifu_mem_ctl.scala 685:70] + node _T_5098 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 685:97] + node _T_5099 = and(_T_5097, _T_5098) @[ifu_mem_ctl.scala 685:79] + node _T_5100 = or(_T_5095, _T_5099) @[ifu_mem_ctl.scala 684:109] + node _T_5101 = or(_T_5100, reset_all_tags) @[ifu_mem_ctl.scala 685:102] node tag_valid_clken_1 = cat(_T_5101, _T_5091) @[Cat.scala 29:58] - node _T_5102 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 676:35] - node _T_5103 = eq(_T_5102, UInt<2>("h02")) @[ifu_mem_ctl.scala 676:78] - node _T_5104 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 676:104] - node _T_5105 = and(_T_5103, _T_5104) @[ifu_mem_ctl.scala 676:87] - node _T_5106 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 677:27] - node _T_5107 = eq(_T_5106, UInt<2>("h02")) @[ifu_mem_ctl.scala 677:70] - node _T_5108 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 677:97] - node _T_5109 = and(_T_5107, _T_5108) @[ifu_mem_ctl.scala 677:79] - node _T_5110 = or(_T_5105, _T_5109) @[ifu_mem_ctl.scala 676:109] - node _T_5111 = or(_T_5110, reset_all_tags) @[ifu_mem_ctl.scala 677:102] - node _T_5112 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 676:35] - node _T_5113 = eq(_T_5112, UInt<2>("h02")) @[ifu_mem_ctl.scala 676:78] - node _T_5114 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 676:104] - node _T_5115 = and(_T_5113, _T_5114) @[ifu_mem_ctl.scala 676:87] - node _T_5116 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 677:27] - node _T_5117 = eq(_T_5116, UInt<2>("h02")) @[ifu_mem_ctl.scala 677:70] - node _T_5118 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 677:97] - node _T_5119 = and(_T_5117, _T_5118) @[ifu_mem_ctl.scala 677:79] - node _T_5120 = or(_T_5115, _T_5119) @[ifu_mem_ctl.scala 676:109] - node _T_5121 = or(_T_5120, reset_all_tags) @[ifu_mem_ctl.scala 677:102] + node _T_5102 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] + node _T_5103 = eq(_T_5102, UInt<2>("h02")) @[ifu_mem_ctl.scala 684:78] + node _T_5104 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 684:104] + node _T_5105 = and(_T_5103, _T_5104) @[ifu_mem_ctl.scala 684:87] + node _T_5106 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] + node _T_5107 = eq(_T_5106, UInt<2>("h02")) @[ifu_mem_ctl.scala 685:70] + node _T_5108 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 685:97] + node _T_5109 = and(_T_5107, _T_5108) @[ifu_mem_ctl.scala 685:79] + node _T_5110 = or(_T_5105, _T_5109) @[ifu_mem_ctl.scala 684:109] + node _T_5111 = or(_T_5110, reset_all_tags) @[ifu_mem_ctl.scala 685:102] + node _T_5112 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] + node _T_5113 = eq(_T_5112, UInt<2>("h02")) @[ifu_mem_ctl.scala 684:78] + node _T_5114 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 684:104] + node _T_5115 = and(_T_5113, _T_5114) @[ifu_mem_ctl.scala 684:87] + node _T_5116 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] + node _T_5117 = eq(_T_5116, UInt<2>("h02")) @[ifu_mem_ctl.scala 685:70] + node _T_5118 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 685:97] + node _T_5119 = and(_T_5117, _T_5118) @[ifu_mem_ctl.scala 685:79] + node _T_5120 = or(_T_5115, _T_5119) @[ifu_mem_ctl.scala 684:109] + node _T_5121 = or(_T_5120, reset_all_tags) @[ifu_mem_ctl.scala 685:102] node tag_valid_clken_2 = cat(_T_5121, _T_5111) @[Cat.scala 29:58] - node _T_5122 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 676:35] - node _T_5123 = eq(_T_5122, UInt<2>("h03")) @[ifu_mem_ctl.scala 676:78] - node _T_5124 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 676:104] - node _T_5125 = and(_T_5123, _T_5124) @[ifu_mem_ctl.scala 676:87] - node _T_5126 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 677:27] - node _T_5127 = eq(_T_5126, UInt<2>("h03")) @[ifu_mem_ctl.scala 677:70] - node _T_5128 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 677:97] - node _T_5129 = and(_T_5127, _T_5128) @[ifu_mem_ctl.scala 677:79] - node _T_5130 = or(_T_5125, _T_5129) @[ifu_mem_ctl.scala 676:109] - node _T_5131 = or(_T_5130, reset_all_tags) @[ifu_mem_ctl.scala 677:102] - node _T_5132 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 676:35] - node _T_5133 = eq(_T_5132, UInt<2>("h03")) @[ifu_mem_ctl.scala 676:78] - node _T_5134 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 676:104] - node _T_5135 = and(_T_5133, _T_5134) @[ifu_mem_ctl.scala 676:87] - node _T_5136 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 677:27] - node _T_5137 = eq(_T_5136, UInt<2>("h03")) @[ifu_mem_ctl.scala 677:70] - node _T_5138 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 677:97] - node _T_5139 = and(_T_5137, _T_5138) @[ifu_mem_ctl.scala 677:79] - node _T_5140 = or(_T_5135, _T_5139) @[ifu_mem_ctl.scala 676:109] - node _T_5141 = or(_T_5140, reset_all_tags) @[ifu_mem_ctl.scala 677:102] + node _T_5122 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] + node _T_5123 = eq(_T_5122, UInt<2>("h03")) @[ifu_mem_ctl.scala 684:78] + node _T_5124 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 684:104] + node _T_5125 = and(_T_5123, _T_5124) @[ifu_mem_ctl.scala 684:87] + node _T_5126 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] + node _T_5127 = eq(_T_5126, UInt<2>("h03")) @[ifu_mem_ctl.scala 685:70] + node _T_5128 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 685:97] + node _T_5129 = and(_T_5127, _T_5128) @[ifu_mem_ctl.scala 685:79] + node _T_5130 = or(_T_5125, _T_5129) @[ifu_mem_ctl.scala 684:109] + node _T_5131 = or(_T_5130, reset_all_tags) @[ifu_mem_ctl.scala 685:102] + node _T_5132 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] + node _T_5133 = eq(_T_5132, UInt<2>("h03")) @[ifu_mem_ctl.scala 684:78] + node _T_5134 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 684:104] + node _T_5135 = and(_T_5133, _T_5134) @[ifu_mem_ctl.scala 684:87] + node _T_5136 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] + node _T_5137 = eq(_T_5136, UInt<2>("h03")) @[ifu_mem_ctl.scala 685:70] + node _T_5138 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 685:97] + node _T_5139 = and(_T_5137, _T_5138) @[ifu_mem_ctl.scala 685:79] + node _T_5140 = or(_T_5135, _T_5139) @[ifu_mem_ctl.scala 684:109] + node _T_5141 = or(_T_5140, reset_all_tags) @[ifu_mem_ctl.scala 685:102] node tag_valid_clken_3 = cat(_T_5141, _T_5131) @[Cat.scala 29:58] - node _T_5142 = bits(tag_valid_clken_0, 0, 0) @[ifu_mem_ctl.scala 679:135] + node _T_5142 = bits(tag_valid_clken_0, 0, 0) @[ifu_mem_ctl.scala 687:135] inst rvclkhdr_86 of rvclkhdr_86 @[lib.scala 327:22] rvclkhdr_86.clock <= clock rvclkhdr_86.reset <= reset rvclkhdr_86.io.clk <= clock @[lib.scala 328:17] rvclkhdr_86.io.en <= _T_5142 @[lib.scala 329:16] rvclkhdr_86.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_5143 = bits(tag_valid_clken_0, 1, 1) @[ifu_mem_ctl.scala 679:135] + node _T_5143 = bits(tag_valid_clken_0, 1, 1) @[ifu_mem_ctl.scala 687:135] inst rvclkhdr_87 of rvclkhdr_87 @[lib.scala 327:22] rvclkhdr_87.clock <= clock rvclkhdr_87.reset <= reset rvclkhdr_87.io.clk <= clock @[lib.scala 328:17] rvclkhdr_87.io.en <= _T_5143 @[lib.scala 329:16] rvclkhdr_87.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_5144 = bits(tag_valid_clken_1, 0, 0) @[ifu_mem_ctl.scala 679:135] + node _T_5144 = bits(tag_valid_clken_1, 0, 0) @[ifu_mem_ctl.scala 687:135] inst rvclkhdr_88 of rvclkhdr_88 @[lib.scala 327:22] rvclkhdr_88.clock <= clock rvclkhdr_88.reset <= reset rvclkhdr_88.io.clk <= clock @[lib.scala 328:17] rvclkhdr_88.io.en <= _T_5144 @[lib.scala 329:16] rvclkhdr_88.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_5145 = bits(tag_valid_clken_1, 1, 1) @[ifu_mem_ctl.scala 679:135] + node _T_5145 = bits(tag_valid_clken_1, 1, 1) @[ifu_mem_ctl.scala 687:135] inst rvclkhdr_89 of rvclkhdr_89 @[lib.scala 327:22] rvclkhdr_89.clock <= clock rvclkhdr_89.reset <= reset rvclkhdr_89.io.clk <= clock @[lib.scala 328:17] rvclkhdr_89.io.en <= _T_5145 @[lib.scala 329:16] rvclkhdr_89.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_5146 = bits(tag_valid_clken_2, 0, 0) @[ifu_mem_ctl.scala 679:135] + node _T_5146 = bits(tag_valid_clken_2, 0, 0) @[ifu_mem_ctl.scala 687:135] inst rvclkhdr_90 of rvclkhdr_90 @[lib.scala 327:22] rvclkhdr_90.clock <= clock rvclkhdr_90.reset <= reset rvclkhdr_90.io.clk <= clock @[lib.scala 328:17] rvclkhdr_90.io.en <= _T_5146 @[lib.scala 329:16] rvclkhdr_90.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_5147 = bits(tag_valid_clken_2, 1, 1) @[ifu_mem_ctl.scala 679:135] + node _T_5147 = bits(tag_valid_clken_2, 1, 1) @[ifu_mem_ctl.scala 687:135] inst rvclkhdr_91 of rvclkhdr_91 @[lib.scala 327:22] rvclkhdr_91.clock <= clock rvclkhdr_91.reset <= reset rvclkhdr_91.io.clk <= clock @[lib.scala 328:17] rvclkhdr_91.io.en <= _T_5147 @[lib.scala 329:16] rvclkhdr_91.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_5148 = bits(tag_valid_clken_3, 0, 0) @[ifu_mem_ctl.scala 679:135] + node _T_5148 = bits(tag_valid_clken_3, 0, 0) @[ifu_mem_ctl.scala 687:135] inst rvclkhdr_92 of rvclkhdr_92 @[lib.scala 327:22] rvclkhdr_92.clock <= clock rvclkhdr_92.reset <= reset rvclkhdr_92.io.clk <= clock @[lib.scala 328:17] rvclkhdr_92.io.en <= _T_5148 @[lib.scala 329:16] rvclkhdr_92.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_5149 = bits(tag_valid_clken_3, 1, 1) @[ifu_mem_ctl.scala 679:135] + node _T_5149 = bits(tag_valid_clken_3, 1, 1) @[ifu_mem_ctl.scala 687:135] inst rvclkhdr_93 of rvclkhdr_93 @[lib.scala 327:22] rvclkhdr_93.clock <= clock rvclkhdr_93.reset <= reset rvclkhdr_93.io.clk <= clock @[lib.scala 328:17] rvclkhdr_93.io.en <= _T_5149 @[lib.scala 329:16] rvclkhdr_93.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - wire ic_tag_valid_out : UInt<1>[128][2] @[ifu_mem_ctl.scala 680:32] - node _T_5150 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5151 = eq(_T_5150, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5152 = and(ic_valid_ff, _T_5151) @[ifu_mem_ctl.scala 685:97] - node _T_5153 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5154 = and(_T_5152, _T_5153) @[ifu_mem_ctl.scala 685:122] - node _T_5155 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 686:37] - node _T_5156 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5157 = and(_T_5155, _T_5156) @[ifu_mem_ctl.scala 686:59] - node _T_5158 = eq(perr_ic_index_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 686:102] - node _T_5159 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5160 = and(_T_5158, _T_5159) @[ifu_mem_ctl.scala 686:124] - node _T_5161 = or(_T_5157, _T_5160) @[ifu_mem_ctl.scala 686:81] - node _T_5162 = or(_T_5161, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5163 = bits(_T_5162, 0, 0) @[ifu_mem_ctl.scala 686:166] + wire ic_tag_valid_out : UInt<1>[128][2] @[ifu_mem_ctl.scala 688:32] + node _T_5150 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5151 = eq(_T_5150, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5152 = and(ic_valid_ff, _T_5151) @[ifu_mem_ctl.scala 693:97] + node _T_5153 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5154 = and(_T_5152, _T_5153) @[ifu_mem_ctl.scala 693:122] + node _T_5155 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 694:37] + node _T_5156 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5157 = and(_T_5155, _T_5156) @[ifu_mem_ctl.scala 694:59] + node _T_5158 = eq(perr_ic_index_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 694:102] + node _T_5159 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5160 = and(_T_5158, _T_5159) @[ifu_mem_ctl.scala 694:124] + node _T_5161 = or(_T_5157, _T_5160) @[ifu_mem_ctl.scala 694:81] + node _T_5162 = or(_T_5161, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5163 = bits(_T_5162, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5164 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5163 : @[Reg.scala 28:19] _T_5164 <= _T_5154 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][0] <= _T_5164 @[ifu_mem_ctl.scala 685:41] - node _T_5165 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5166 = eq(_T_5165, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5167 = and(ic_valid_ff, _T_5166) @[ifu_mem_ctl.scala 685:97] - node _T_5168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5169 = and(_T_5167, _T_5168) @[ifu_mem_ctl.scala 685:122] - node _T_5170 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 686:37] - node _T_5171 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5172 = and(_T_5170, _T_5171) @[ifu_mem_ctl.scala 686:59] - node _T_5173 = eq(perr_ic_index_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 686:102] - node _T_5174 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5175 = and(_T_5173, _T_5174) @[ifu_mem_ctl.scala 686:124] - node _T_5176 = or(_T_5172, _T_5175) @[ifu_mem_ctl.scala 686:81] - node _T_5177 = or(_T_5176, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5178 = bits(_T_5177, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][0] <= _T_5164 @[ifu_mem_ctl.scala 693:41] + node _T_5165 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5166 = eq(_T_5165, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5167 = and(ic_valid_ff, _T_5166) @[ifu_mem_ctl.scala 693:97] + node _T_5168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5169 = and(_T_5167, _T_5168) @[ifu_mem_ctl.scala 693:122] + node _T_5170 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 694:37] + node _T_5171 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5172 = and(_T_5170, _T_5171) @[ifu_mem_ctl.scala 694:59] + node _T_5173 = eq(perr_ic_index_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 694:102] + node _T_5174 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5175 = and(_T_5173, _T_5174) @[ifu_mem_ctl.scala 694:124] + node _T_5176 = or(_T_5172, _T_5175) @[ifu_mem_ctl.scala 694:81] + node _T_5177 = or(_T_5176, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5178 = bits(_T_5177, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5179 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5178 : @[Reg.scala 28:19] _T_5179 <= _T_5169 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][1] <= _T_5179 @[ifu_mem_ctl.scala 685:41] - node _T_5180 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5181 = eq(_T_5180, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5182 = and(ic_valid_ff, _T_5181) @[ifu_mem_ctl.scala 685:97] - node _T_5183 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5184 = and(_T_5182, _T_5183) @[ifu_mem_ctl.scala 685:122] - node _T_5185 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 686:37] - node _T_5186 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5187 = and(_T_5185, _T_5186) @[ifu_mem_ctl.scala 686:59] - node _T_5188 = eq(perr_ic_index_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 686:102] - node _T_5189 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5190 = and(_T_5188, _T_5189) @[ifu_mem_ctl.scala 686:124] - node _T_5191 = or(_T_5187, _T_5190) @[ifu_mem_ctl.scala 686:81] - node _T_5192 = or(_T_5191, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5193 = bits(_T_5192, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][1] <= _T_5179 @[ifu_mem_ctl.scala 693:41] + node _T_5180 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5181 = eq(_T_5180, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5182 = and(ic_valid_ff, _T_5181) @[ifu_mem_ctl.scala 693:97] + node _T_5183 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5184 = and(_T_5182, _T_5183) @[ifu_mem_ctl.scala 693:122] + node _T_5185 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 694:37] + node _T_5186 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5187 = and(_T_5185, _T_5186) @[ifu_mem_ctl.scala 694:59] + node _T_5188 = eq(perr_ic_index_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 694:102] + node _T_5189 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5190 = and(_T_5188, _T_5189) @[ifu_mem_ctl.scala 694:124] + node _T_5191 = or(_T_5187, _T_5190) @[ifu_mem_ctl.scala 694:81] + node _T_5192 = or(_T_5191, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5193 = bits(_T_5192, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5194 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5193 : @[Reg.scala 28:19] _T_5194 <= _T_5184 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][2] <= _T_5194 @[ifu_mem_ctl.scala 685:41] - node _T_5195 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5196 = eq(_T_5195, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5197 = and(ic_valid_ff, _T_5196) @[ifu_mem_ctl.scala 685:97] - node _T_5198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5199 = and(_T_5197, _T_5198) @[ifu_mem_ctl.scala 685:122] - node _T_5200 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 686:37] - node _T_5201 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5202 = and(_T_5200, _T_5201) @[ifu_mem_ctl.scala 686:59] - node _T_5203 = eq(perr_ic_index_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 686:102] - node _T_5204 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5205 = and(_T_5203, _T_5204) @[ifu_mem_ctl.scala 686:124] - node _T_5206 = or(_T_5202, _T_5205) @[ifu_mem_ctl.scala 686:81] - node _T_5207 = or(_T_5206, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5208 = bits(_T_5207, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][2] <= _T_5194 @[ifu_mem_ctl.scala 693:41] + node _T_5195 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5196 = eq(_T_5195, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5197 = and(ic_valid_ff, _T_5196) @[ifu_mem_ctl.scala 693:97] + node _T_5198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5199 = and(_T_5197, _T_5198) @[ifu_mem_ctl.scala 693:122] + node _T_5200 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 694:37] + node _T_5201 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5202 = and(_T_5200, _T_5201) @[ifu_mem_ctl.scala 694:59] + node _T_5203 = eq(perr_ic_index_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 694:102] + node _T_5204 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5205 = and(_T_5203, _T_5204) @[ifu_mem_ctl.scala 694:124] + node _T_5206 = or(_T_5202, _T_5205) @[ifu_mem_ctl.scala 694:81] + node _T_5207 = or(_T_5206, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5208 = bits(_T_5207, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5209 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5208 : @[Reg.scala 28:19] _T_5209 <= _T_5199 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][3] <= _T_5209 @[ifu_mem_ctl.scala 685:41] - node _T_5210 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5211 = eq(_T_5210, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5212 = and(ic_valid_ff, _T_5211) @[ifu_mem_ctl.scala 685:97] - node _T_5213 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5214 = and(_T_5212, _T_5213) @[ifu_mem_ctl.scala 685:122] - node _T_5215 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 686:37] - node _T_5216 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5217 = and(_T_5215, _T_5216) @[ifu_mem_ctl.scala 686:59] - node _T_5218 = eq(perr_ic_index_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 686:102] - node _T_5219 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5220 = and(_T_5218, _T_5219) @[ifu_mem_ctl.scala 686:124] - node _T_5221 = or(_T_5217, _T_5220) @[ifu_mem_ctl.scala 686:81] - node _T_5222 = or(_T_5221, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5223 = bits(_T_5222, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][3] <= _T_5209 @[ifu_mem_ctl.scala 693:41] + node _T_5210 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5211 = eq(_T_5210, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5212 = and(ic_valid_ff, _T_5211) @[ifu_mem_ctl.scala 693:97] + node _T_5213 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5214 = and(_T_5212, _T_5213) @[ifu_mem_ctl.scala 693:122] + node _T_5215 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 694:37] + node _T_5216 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5217 = and(_T_5215, _T_5216) @[ifu_mem_ctl.scala 694:59] + node _T_5218 = eq(perr_ic_index_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 694:102] + node _T_5219 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5220 = and(_T_5218, _T_5219) @[ifu_mem_ctl.scala 694:124] + node _T_5221 = or(_T_5217, _T_5220) @[ifu_mem_ctl.scala 694:81] + node _T_5222 = or(_T_5221, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5223 = bits(_T_5222, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5224 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5223 : @[Reg.scala 28:19] _T_5224 <= _T_5214 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][4] <= _T_5224 @[ifu_mem_ctl.scala 685:41] - node _T_5225 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5226 = eq(_T_5225, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5227 = and(ic_valid_ff, _T_5226) @[ifu_mem_ctl.scala 685:97] - node _T_5228 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5229 = and(_T_5227, _T_5228) @[ifu_mem_ctl.scala 685:122] - node _T_5230 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 686:37] - node _T_5231 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5232 = and(_T_5230, _T_5231) @[ifu_mem_ctl.scala 686:59] - node _T_5233 = eq(perr_ic_index_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 686:102] - node _T_5234 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5235 = and(_T_5233, _T_5234) @[ifu_mem_ctl.scala 686:124] - node _T_5236 = or(_T_5232, _T_5235) @[ifu_mem_ctl.scala 686:81] - node _T_5237 = or(_T_5236, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5238 = bits(_T_5237, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][4] <= _T_5224 @[ifu_mem_ctl.scala 693:41] + node _T_5225 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5226 = eq(_T_5225, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5227 = and(ic_valid_ff, _T_5226) @[ifu_mem_ctl.scala 693:97] + node _T_5228 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5229 = and(_T_5227, _T_5228) @[ifu_mem_ctl.scala 693:122] + node _T_5230 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 694:37] + node _T_5231 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5232 = and(_T_5230, _T_5231) @[ifu_mem_ctl.scala 694:59] + node _T_5233 = eq(perr_ic_index_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 694:102] + node _T_5234 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5235 = and(_T_5233, _T_5234) @[ifu_mem_ctl.scala 694:124] + node _T_5236 = or(_T_5232, _T_5235) @[ifu_mem_ctl.scala 694:81] + node _T_5237 = or(_T_5236, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5238 = bits(_T_5237, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5239 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5238 : @[Reg.scala 28:19] _T_5239 <= _T_5229 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][5] <= _T_5239 @[ifu_mem_ctl.scala 685:41] - node _T_5240 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5241 = eq(_T_5240, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5242 = and(ic_valid_ff, _T_5241) @[ifu_mem_ctl.scala 685:97] - node _T_5243 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5244 = and(_T_5242, _T_5243) @[ifu_mem_ctl.scala 685:122] - node _T_5245 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 686:37] - node _T_5246 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5247 = and(_T_5245, _T_5246) @[ifu_mem_ctl.scala 686:59] - node _T_5248 = eq(perr_ic_index_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 686:102] - node _T_5249 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5250 = and(_T_5248, _T_5249) @[ifu_mem_ctl.scala 686:124] - node _T_5251 = or(_T_5247, _T_5250) @[ifu_mem_ctl.scala 686:81] - node _T_5252 = or(_T_5251, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5253 = bits(_T_5252, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][5] <= _T_5239 @[ifu_mem_ctl.scala 693:41] + node _T_5240 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5241 = eq(_T_5240, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5242 = and(ic_valid_ff, _T_5241) @[ifu_mem_ctl.scala 693:97] + node _T_5243 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5244 = and(_T_5242, _T_5243) @[ifu_mem_ctl.scala 693:122] + node _T_5245 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 694:37] + node _T_5246 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5247 = and(_T_5245, _T_5246) @[ifu_mem_ctl.scala 694:59] + node _T_5248 = eq(perr_ic_index_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 694:102] + node _T_5249 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5250 = and(_T_5248, _T_5249) @[ifu_mem_ctl.scala 694:124] + node _T_5251 = or(_T_5247, _T_5250) @[ifu_mem_ctl.scala 694:81] + node _T_5252 = or(_T_5251, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5253 = bits(_T_5252, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5254 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5253 : @[Reg.scala 28:19] _T_5254 <= _T_5244 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][6] <= _T_5254 @[ifu_mem_ctl.scala 685:41] - node _T_5255 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5256 = eq(_T_5255, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5257 = and(ic_valid_ff, _T_5256) @[ifu_mem_ctl.scala 685:97] - node _T_5258 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5259 = and(_T_5257, _T_5258) @[ifu_mem_ctl.scala 685:122] - node _T_5260 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 686:37] - node _T_5261 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5262 = and(_T_5260, _T_5261) @[ifu_mem_ctl.scala 686:59] - node _T_5263 = eq(perr_ic_index_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 686:102] - node _T_5264 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5265 = and(_T_5263, _T_5264) @[ifu_mem_ctl.scala 686:124] - node _T_5266 = or(_T_5262, _T_5265) @[ifu_mem_ctl.scala 686:81] - node _T_5267 = or(_T_5266, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5268 = bits(_T_5267, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][6] <= _T_5254 @[ifu_mem_ctl.scala 693:41] + node _T_5255 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5256 = eq(_T_5255, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5257 = and(ic_valid_ff, _T_5256) @[ifu_mem_ctl.scala 693:97] + node _T_5258 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5259 = and(_T_5257, _T_5258) @[ifu_mem_ctl.scala 693:122] + node _T_5260 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 694:37] + node _T_5261 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5262 = and(_T_5260, _T_5261) @[ifu_mem_ctl.scala 694:59] + node _T_5263 = eq(perr_ic_index_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 694:102] + node _T_5264 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5265 = and(_T_5263, _T_5264) @[ifu_mem_ctl.scala 694:124] + node _T_5266 = or(_T_5262, _T_5265) @[ifu_mem_ctl.scala 694:81] + node _T_5267 = or(_T_5266, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5268 = bits(_T_5267, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5269 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5268 : @[Reg.scala 28:19] _T_5269 <= _T_5259 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][7] <= _T_5269 @[ifu_mem_ctl.scala 685:41] - node _T_5270 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5271 = eq(_T_5270, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5272 = and(ic_valid_ff, _T_5271) @[ifu_mem_ctl.scala 685:97] - node _T_5273 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5274 = and(_T_5272, _T_5273) @[ifu_mem_ctl.scala 685:122] - node _T_5275 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 686:37] - node _T_5276 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5277 = and(_T_5275, _T_5276) @[ifu_mem_ctl.scala 686:59] - node _T_5278 = eq(perr_ic_index_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 686:102] - node _T_5279 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5280 = and(_T_5278, _T_5279) @[ifu_mem_ctl.scala 686:124] - node _T_5281 = or(_T_5277, _T_5280) @[ifu_mem_ctl.scala 686:81] - node _T_5282 = or(_T_5281, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5283 = bits(_T_5282, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][7] <= _T_5269 @[ifu_mem_ctl.scala 693:41] + node _T_5270 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5271 = eq(_T_5270, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5272 = and(ic_valid_ff, _T_5271) @[ifu_mem_ctl.scala 693:97] + node _T_5273 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5274 = and(_T_5272, _T_5273) @[ifu_mem_ctl.scala 693:122] + node _T_5275 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 694:37] + node _T_5276 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5277 = and(_T_5275, _T_5276) @[ifu_mem_ctl.scala 694:59] + node _T_5278 = eq(perr_ic_index_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 694:102] + node _T_5279 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5280 = and(_T_5278, _T_5279) @[ifu_mem_ctl.scala 694:124] + node _T_5281 = or(_T_5277, _T_5280) @[ifu_mem_ctl.scala 694:81] + node _T_5282 = or(_T_5281, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5283 = bits(_T_5282, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5284 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5283 : @[Reg.scala 28:19] _T_5284 <= _T_5274 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][8] <= _T_5284 @[ifu_mem_ctl.scala 685:41] - node _T_5285 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5286 = eq(_T_5285, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5287 = and(ic_valid_ff, _T_5286) @[ifu_mem_ctl.scala 685:97] - node _T_5288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5289 = and(_T_5287, _T_5288) @[ifu_mem_ctl.scala 685:122] - node _T_5290 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 686:37] - node _T_5291 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5292 = and(_T_5290, _T_5291) @[ifu_mem_ctl.scala 686:59] - node _T_5293 = eq(perr_ic_index_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 686:102] - node _T_5294 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5295 = and(_T_5293, _T_5294) @[ifu_mem_ctl.scala 686:124] - node _T_5296 = or(_T_5292, _T_5295) @[ifu_mem_ctl.scala 686:81] - node _T_5297 = or(_T_5296, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5298 = bits(_T_5297, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][8] <= _T_5284 @[ifu_mem_ctl.scala 693:41] + node _T_5285 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5286 = eq(_T_5285, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5287 = and(ic_valid_ff, _T_5286) @[ifu_mem_ctl.scala 693:97] + node _T_5288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5289 = and(_T_5287, _T_5288) @[ifu_mem_ctl.scala 693:122] + node _T_5290 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 694:37] + node _T_5291 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5292 = and(_T_5290, _T_5291) @[ifu_mem_ctl.scala 694:59] + node _T_5293 = eq(perr_ic_index_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 694:102] + node _T_5294 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5295 = and(_T_5293, _T_5294) @[ifu_mem_ctl.scala 694:124] + node _T_5296 = or(_T_5292, _T_5295) @[ifu_mem_ctl.scala 694:81] + node _T_5297 = or(_T_5296, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5298 = bits(_T_5297, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5299 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5298 : @[Reg.scala 28:19] _T_5299 <= _T_5289 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][9] <= _T_5299 @[ifu_mem_ctl.scala 685:41] - node _T_5300 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5301 = eq(_T_5300, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5302 = and(ic_valid_ff, _T_5301) @[ifu_mem_ctl.scala 685:97] - node _T_5303 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5304 = and(_T_5302, _T_5303) @[ifu_mem_ctl.scala 685:122] - node _T_5305 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 686:37] - node _T_5306 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5307 = and(_T_5305, _T_5306) @[ifu_mem_ctl.scala 686:59] - node _T_5308 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 686:102] - node _T_5309 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5310 = and(_T_5308, _T_5309) @[ifu_mem_ctl.scala 686:124] - node _T_5311 = or(_T_5307, _T_5310) @[ifu_mem_ctl.scala 686:81] - node _T_5312 = or(_T_5311, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5313 = bits(_T_5312, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][9] <= _T_5299 @[ifu_mem_ctl.scala 693:41] + node _T_5300 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5301 = eq(_T_5300, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5302 = and(ic_valid_ff, _T_5301) @[ifu_mem_ctl.scala 693:97] + node _T_5303 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5304 = and(_T_5302, _T_5303) @[ifu_mem_ctl.scala 693:122] + node _T_5305 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 694:37] + node _T_5306 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5307 = and(_T_5305, _T_5306) @[ifu_mem_ctl.scala 694:59] + node _T_5308 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 694:102] + node _T_5309 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5310 = and(_T_5308, _T_5309) @[ifu_mem_ctl.scala 694:124] + node _T_5311 = or(_T_5307, _T_5310) @[ifu_mem_ctl.scala 694:81] + node _T_5312 = or(_T_5311, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5313 = bits(_T_5312, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5314 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5313 : @[Reg.scala 28:19] _T_5314 <= _T_5304 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][10] <= _T_5314 @[ifu_mem_ctl.scala 685:41] - node _T_5315 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5316 = eq(_T_5315, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5317 = and(ic_valid_ff, _T_5316) @[ifu_mem_ctl.scala 685:97] - node _T_5318 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5319 = and(_T_5317, _T_5318) @[ifu_mem_ctl.scala 685:122] - node _T_5320 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 686:37] - node _T_5321 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5322 = and(_T_5320, _T_5321) @[ifu_mem_ctl.scala 686:59] - node _T_5323 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 686:102] - node _T_5324 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5325 = and(_T_5323, _T_5324) @[ifu_mem_ctl.scala 686:124] - node _T_5326 = or(_T_5322, _T_5325) @[ifu_mem_ctl.scala 686:81] - node _T_5327 = or(_T_5326, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5328 = bits(_T_5327, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][10] <= _T_5314 @[ifu_mem_ctl.scala 693:41] + node _T_5315 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5316 = eq(_T_5315, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5317 = and(ic_valid_ff, _T_5316) @[ifu_mem_ctl.scala 693:97] + node _T_5318 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5319 = and(_T_5317, _T_5318) @[ifu_mem_ctl.scala 693:122] + node _T_5320 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 694:37] + node _T_5321 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5322 = and(_T_5320, _T_5321) @[ifu_mem_ctl.scala 694:59] + node _T_5323 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 694:102] + node _T_5324 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5325 = and(_T_5323, _T_5324) @[ifu_mem_ctl.scala 694:124] + node _T_5326 = or(_T_5322, _T_5325) @[ifu_mem_ctl.scala 694:81] + node _T_5327 = or(_T_5326, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5328 = bits(_T_5327, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5329 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5328 : @[Reg.scala 28:19] _T_5329 <= _T_5319 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][11] <= _T_5329 @[ifu_mem_ctl.scala 685:41] - node _T_5330 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5331 = eq(_T_5330, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5332 = and(ic_valid_ff, _T_5331) @[ifu_mem_ctl.scala 685:97] - node _T_5333 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5334 = and(_T_5332, _T_5333) @[ifu_mem_ctl.scala 685:122] - node _T_5335 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 686:37] - node _T_5336 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5337 = and(_T_5335, _T_5336) @[ifu_mem_ctl.scala 686:59] - node _T_5338 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 686:102] - node _T_5339 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5340 = and(_T_5338, _T_5339) @[ifu_mem_ctl.scala 686:124] - node _T_5341 = or(_T_5337, _T_5340) @[ifu_mem_ctl.scala 686:81] - node _T_5342 = or(_T_5341, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5343 = bits(_T_5342, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][11] <= _T_5329 @[ifu_mem_ctl.scala 693:41] + node _T_5330 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5331 = eq(_T_5330, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5332 = and(ic_valid_ff, _T_5331) @[ifu_mem_ctl.scala 693:97] + node _T_5333 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5334 = and(_T_5332, _T_5333) @[ifu_mem_ctl.scala 693:122] + node _T_5335 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 694:37] + node _T_5336 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5337 = and(_T_5335, _T_5336) @[ifu_mem_ctl.scala 694:59] + node _T_5338 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 694:102] + node _T_5339 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5340 = and(_T_5338, _T_5339) @[ifu_mem_ctl.scala 694:124] + node _T_5341 = or(_T_5337, _T_5340) @[ifu_mem_ctl.scala 694:81] + node _T_5342 = or(_T_5341, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5343 = bits(_T_5342, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5344 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5343 : @[Reg.scala 28:19] _T_5344 <= _T_5334 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][12] <= _T_5344 @[ifu_mem_ctl.scala 685:41] - node _T_5345 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5346 = eq(_T_5345, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5347 = and(ic_valid_ff, _T_5346) @[ifu_mem_ctl.scala 685:97] - node _T_5348 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5349 = and(_T_5347, _T_5348) @[ifu_mem_ctl.scala 685:122] - node _T_5350 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 686:37] - node _T_5351 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5352 = and(_T_5350, _T_5351) @[ifu_mem_ctl.scala 686:59] - node _T_5353 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 686:102] - node _T_5354 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5355 = and(_T_5353, _T_5354) @[ifu_mem_ctl.scala 686:124] - node _T_5356 = or(_T_5352, _T_5355) @[ifu_mem_ctl.scala 686:81] - node _T_5357 = or(_T_5356, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5358 = bits(_T_5357, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][12] <= _T_5344 @[ifu_mem_ctl.scala 693:41] + node _T_5345 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5346 = eq(_T_5345, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5347 = and(ic_valid_ff, _T_5346) @[ifu_mem_ctl.scala 693:97] + node _T_5348 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5349 = and(_T_5347, _T_5348) @[ifu_mem_ctl.scala 693:122] + node _T_5350 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 694:37] + node _T_5351 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5352 = and(_T_5350, _T_5351) @[ifu_mem_ctl.scala 694:59] + node _T_5353 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 694:102] + node _T_5354 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5355 = and(_T_5353, _T_5354) @[ifu_mem_ctl.scala 694:124] + node _T_5356 = or(_T_5352, _T_5355) @[ifu_mem_ctl.scala 694:81] + node _T_5357 = or(_T_5356, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5358 = bits(_T_5357, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5359 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5358 : @[Reg.scala 28:19] _T_5359 <= _T_5349 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][13] <= _T_5359 @[ifu_mem_ctl.scala 685:41] - node _T_5360 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5361 = eq(_T_5360, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5362 = and(ic_valid_ff, _T_5361) @[ifu_mem_ctl.scala 685:97] - node _T_5363 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5364 = and(_T_5362, _T_5363) @[ifu_mem_ctl.scala 685:122] - node _T_5365 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 686:37] - node _T_5366 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5367 = and(_T_5365, _T_5366) @[ifu_mem_ctl.scala 686:59] - node _T_5368 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 686:102] - node _T_5369 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5370 = and(_T_5368, _T_5369) @[ifu_mem_ctl.scala 686:124] - node _T_5371 = or(_T_5367, _T_5370) @[ifu_mem_ctl.scala 686:81] - node _T_5372 = or(_T_5371, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5373 = bits(_T_5372, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][13] <= _T_5359 @[ifu_mem_ctl.scala 693:41] + node _T_5360 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5361 = eq(_T_5360, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5362 = and(ic_valid_ff, _T_5361) @[ifu_mem_ctl.scala 693:97] + node _T_5363 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5364 = and(_T_5362, _T_5363) @[ifu_mem_ctl.scala 693:122] + node _T_5365 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 694:37] + node _T_5366 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5367 = and(_T_5365, _T_5366) @[ifu_mem_ctl.scala 694:59] + node _T_5368 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 694:102] + node _T_5369 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5370 = and(_T_5368, _T_5369) @[ifu_mem_ctl.scala 694:124] + node _T_5371 = or(_T_5367, _T_5370) @[ifu_mem_ctl.scala 694:81] + node _T_5372 = or(_T_5371, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5373 = bits(_T_5372, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5374 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5373 : @[Reg.scala 28:19] _T_5374 <= _T_5364 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][14] <= _T_5374 @[ifu_mem_ctl.scala 685:41] - node _T_5375 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5376 = eq(_T_5375, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5377 = and(ic_valid_ff, _T_5376) @[ifu_mem_ctl.scala 685:97] - node _T_5378 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5379 = and(_T_5377, _T_5378) @[ifu_mem_ctl.scala 685:122] - node _T_5380 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 686:37] - node _T_5381 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5382 = and(_T_5380, _T_5381) @[ifu_mem_ctl.scala 686:59] - node _T_5383 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 686:102] - node _T_5384 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5385 = and(_T_5383, _T_5384) @[ifu_mem_ctl.scala 686:124] - node _T_5386 = or(_T_5382, _T_5385) @[ifu_mem_ctl.scala 686:81] - node _T_5387 = or(_T_5386, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5388 = bits(_T_5387, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][14] <= _T_5374 @[ifu_mem_ctl.scala 693:41] + node _T_5375 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5376 = eq(_T_5375, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5377 = and(ic_valid_ff, _T_5376) @[ifu_mem_ctl.scala 693:97] + node _T_5378 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5379 = and(_T_5377, _T_5378) @[ifu_mem_ctl.scala 693:122] + node _T_5380 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 694:37] + node _T_5381 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5382 = and(_T_5380, _T_5381) @[ifu_mem_ctl.scala 694:59] + node _T_5383 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 694:102] + node _T_5384 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5385 = and(_T_5383, _T_5384) @[ifu_mem_ctl.scala 694:124] + node _T_5386 = or(_T_5382, _T_5385) @[ifu_mem_ctl.scala 694:81] + node _T_5387 = or(_T_5386, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5388 = bits(_T_5387, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5389 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5388 : @[Reg.scala 28:19] _T_5389 <= _T_5379 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][15] <= _T_5389 @[ifu_mem_ctl.scala 685:41] - node _T_5390 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5391 = eq(_T_5390, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5392 = and(ic_valid_ff, _T_5391) @[ifu_mem_ctl.scala 685:97] - node _T_5393 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5394 = and(_T_5392, _T_5393) @[ifu_mem_ctl.scala 685:122] - node _T_5395 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 686:37] - node _T_5396 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5397 = and(_T_5395, _T_5396) @[ifu_mem_ctl.scala 686:59] - node _T_5398 = eq(perr_ic_index_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 686:102] - node _T_5399 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5400 = and(_T_5398, _T_5399) @[ifu_mem_ctl.scala 686:124] - node _T_5401 = or(_T_5397, _T_5400) @[ifu_mem_ctl.scala 686:81] - node _T_5402 = or(_T_5401, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5403 = bits(_T_5402, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][15] <= _T_5389 @[ifu_mem_ctl.scala 693:41] + node _T_5390 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5391 = eq(_T_5390, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5392 = and(ic_valid_ff, _T_5391) @[ifu_mem_ctl.scala 693:97] + node _T_5393 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5394 = and(_T_5392, _T_5393) @[ifu_mem_ctl.scala 693:122] + node _T_5395 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 694:37] + node _T_5396 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5397 = and(_T_5395, _T_5396) @[ifu_mem_ctl.scala 694:59] + node _T_5398 = eq(perr_ic_index_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 694:102] + node _T_5399 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5400 = and(_T_5398, _T_5399) @[ifu_mem_ctl.scala 694:124] + node _T_5401 = or(_T_5397, _T_5400) @[ifu_mem_ctl.scala 694:81] + node _T_5402 = or(_T_5401, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5403 = bits(_T_5402, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5404 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5403 : @[Reg.scala 28:19] _T_5404 <= _T_5394 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][16] <= _T_5404 @[ifu_mem_ctl.scala 685:41] - node _T_5405 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5406 = eq(_T_5405, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5407 = and(ic_valid_ff, _T_5406) @[ifu_mem_ctl.scala 685:97] - node _T_5408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5409 = and(_T_5407, _T_5408) @[ifu_mem_ctl.scala 685:122] - node _T_5410 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 686:37] - node _T_5411 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5412 = and(_T_5410, _T_5411) @[ifu_mem_ctl.scala 686:59] - node _T_5413 = eq(perr_ic_index_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 686:102] - node _T_5414 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5415 = and(_T_5413, _T_5414) @[ifu_mem_ctl.scala 686:124] - node _T_5416 = or(_T_5412, _T_5415) @[ifu_mem_ctl.scala 686:81] - node _T_5417 = or(_T_5416, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5418 = bits(_T_5417, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][16] <= _T_5404 @[ifu_mem_ctl.scala 693:41] + node _T_5405 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5406 = eq(_T_5405, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5407 = and(ic_valid_ff, _T_5406) @[ifu_mem_ctl.scala 693:97] + node _T_5408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5409 = and(_T_5407, _T_5408) @[ifu_mem_ctl.scala 693:122] + node _T_5410 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 694:37] + node _T_5411 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5412 = and(_T_5410, _T_5411) @[ifu_mem_ctl.scala 694:59] + node _T_5413 = eq(perr_ic_index_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 694:102] + node _T_5414 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5415 = and(_T_5413, _T_5414) @[ifu_mem_ctl.scala 694:124] + node _T_5416 = or(_T_5412, _T_5415) @[ifu_mem_ctl.scala 694:81] + node _T_5417 = or(_T_5416, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5418 = bits(_T_5417, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5419 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5418 : @[Reg.scala 28:19] _T_5419 <= _T_5409 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][17] <= _T_5419 @[ifu_mem_ctl.scala 685:41] - node _T_5420 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5421 = eq(_T_5420, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5422 = and(ic_valid_ff, _T_5421) @[ifu_mem_ctl.scala 685:97] - node _T_5423 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5424 = and(_T_5422, _T_5423) @[ifu_mem_ctl.scala 685:122] - node _T_5425 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 686:37] - node _T_5426 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5427 = and(_T_5425, _T_5426) @[ifu_mem_ctl.scala 686:59] - node _T_5428 = eq(perr_ic_index_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 686:102] - node _T_5429 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5430 = and(_T_5428, _T_5429) @[ifu_mem_ctl.scala 686:124] - node _T_5431 = or(_T_5427, _T_5430) @[ifu_mem_ctl.scala 686:81] - node _T_5432 = or(_T_5431, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5433 = bits(_T_5432, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][17] <= _T_5419 @[ifu_mem_ctl.scala 693:41] + node _T_5420 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5421 = eq(_T_5420, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5422 = and(ic_valid_ff, _T_5421) @[ifu_mem_ctl.scala 693:97] + node _T_5423 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5424 = and(_T_5422, _T_5423) @[ifu_mem_ctl.scala 693:122] + node _T_5425 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 694:37] + node _T_5426 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5427 = and(_T_5425, _T_5426) @[ifu_mem_ctl.scala 694:59] + node _T_5428 = eq(perr_ic_index_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 694:102] + node _T_5429 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5430 = and(_T_5428, _T_5429) @[ifu_mem_ctl.scala 694:124] + node _T_5431 = or(_T_5427, _T_5430) @[ifu_mem_ctl.scala 694:81] + node _T_5432 = or(_T_5431, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5433 = bits(_T_5432, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5434 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5433 : @[Reg.scala 28:19] _T_5434 <= _T_5424 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][18] <= _T_5434 @[ifu_mem_ctl.scala 685:41] - node _T_5435 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5436 = eq(_T_5435, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5437 = and(ic_valid_ff, _T_5436) @[ifu_mem_ctl.scala 685:97] - node _T_5438 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5439 = and(_T_5437, _T_5438) @[ifu_mem_ctl.scala 685:122] - node _T_5440 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 686:37] - node _T_5441 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5442 = and(_T_5440, _T_5441) @[ifu_mem_ctl.scala 686:59] - node _T_5443 = eq(perr_ic_index_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 686:102] - node _T_5444 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5445 = and(_T_5443, _T_5444) @[ifu_mem_ctl.scala 686:124] - node _T_5446 = or(_T_5442, _T_5445) @[ifu_mem_ctl.scala 686:81] - node _T_5447 = or(_T_5446, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5448 = bits(_T_5447, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][18] <= _T_5434 @[ifu_mem_ctl.scala 693:41] + node _T_5435 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5436 = eq(_T_5435, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5437 = and(ic_valid_ff, _T_5436) @[ifu_mem_ctl.scala 693:97] + node _T_5438 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5439 = and(_T_5437, _T_5438) @[ifu_mem_ctl.scala 693:122] + node _T_5440 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 694:37] + node _T_5441 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5442 = and(_T_5440, _T_5441) @[ifu_mem_ctl.scala 694:59] + node _T_5443 = eq(perr_ic_index_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 694:102] + node _T_5444 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5445 = and(_T_5443, _T_5444) @[ifu_mem_ctl.scala 694:124] + node _T_5446 = or(_T_5442, _T_5445) @[ifu_mem_ctl.scala 694:81] + node _T_5447 = or(_T_5446, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5448 = bits(_T_5447, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5449 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5448 : @[Reg.scala 28:19] _T_5449 <= _T_5439 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][19] <= _T_5449 @[ifu_mem_ctl.scala 685:41] - node _T_5450 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5451 = eq(_T_5450, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5452 = and(ic_valid_ff, _T_5451) @[ifu_mem_ctl.scala 685:97] - node _T_5453 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5454 = and(_T_5452, _T_5453) @[ifu_mem_ctl.scala 685:122] - node _T_5455 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 686:37] - node _T_5456 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5457 = and(_T_5455, _T_5456) @[ifu_mem_ctl.scala 686:59] - node _T_5458 = eq(perr_ic_index_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 686:102] - node _T_5459 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5460 = and(_T_5458, _T_5459) @[ifu_mem_ctl.scala 686:124] - node _T_5461 = or(_T_5457, _T_5460) @[ifu_mem_ctl.scala 686:81] - node _T_5462 = or(_T_5461, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5463 = bits(_T_5462, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][19] <= _T_5449 @[ifu_mem_ctl.scala 693:41] + node _T_5450 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5451 = eq(_T_5450, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5452 = and(ic_valid_ff, _T_5451) @[ifu_mem_ctl.scala 693:97] + node _T_5453 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5454 = and(_T_5452, _T_5453) @[ifu_mem_ctl.scala 693:122] + node _T_5455 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 694:37] + node _T_5456 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5457 = and(_T_5455, _T_5456) @[ifu_mem_ctl.scala 694:59] + node _T_5458 = eq(perr_ic_index_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 694:102] + node _T_5459 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5460 = and(_T_5458, _T_5459) @[ifu_mem_ctl.scala 694:124] + node _T_5461 = or(_T_5457, _T_5460) @[ifu_mem_ctl.scala 694:81] + node _T_5462 = or(_T_5461, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5463 = bits(_T_5462, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5464 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5463 : @[Reg.scala 28:19] _T_5464 <= _T_5454 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][20] <= _T_5464 @[ifu_mem_ctl.scala 685:41] - node _T_5465 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5466 = eq(_T_5465, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5467 = and(ic_valid_ff, _T_5466) @[ifu_mem_ctl.scala 685:97] - node _T_5468 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5469 = and(_T_5467, _T_5468) @[ifu_mem_ctl.scala 685:122] - node _T_5470 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 686:37] - node _T_5471 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5472 = and(_T_5470, _T_5471) @[ifu_mem_ctl.scala 686:59] - node _T_5473 = eq(perr_ic_index_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 686:102] - node _T_5474 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5475 = and(_T_5473, _T_5474) @[ifu_mem_ctl.scala 686:124] - node _T_5476 = or(_T_5472, _T_5475) @[ifu_mem_ctl.scala 686:81] - node _T_5477 = or(_T_5476, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5478 = bits(_T_5477, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][20] <= _T_5464 @[ifu_mem_ctl.scala 693:41] + node _T_5465 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5466 = eq(_T_5465, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5467 = and(ic_valid_ff, _T_5466) @[ifu_mem_ctl.scala 693:97] + node _T_5468 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5469 = and(_T_5467, _T_5468) @[ifu_mem_ctl.scala 693:122] + node _T_5470 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 694:37] + node _T_5471 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5472 = and(_T_5470, _T_5471) @[ifu_mem_ctl.scala 694:59] + node _T_5473 = eq(perr_ic_index_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 694:102] + node _T_5474 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5475 = and(_T_5473, _T_5474) @[ifu_mem_ctl.scala 694:124] + node _T_5476 = or(_T_5472, _T_5475) @[ifu_mem_ctl.scala 694:81] + node _T_5477 = or(_T_5476, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5478 = bits(_T_5477, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5479 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5478 : @[Reg.scala 28:19] _T_5479 <= _T_5469 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][21] <= _T_5479 @[ifu_mem_ctl.scala 685:41] - node _T_5480 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5481 = eq(_T_5480, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5482 = and(ic_valid_ff, _T_5481) @[ifu_mem_ctl.scala 685:97] - node _T_5483 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5484 = and(_T_5482, _T_5483) @[ifu_mem_ctl.scala 685:122] - node _T_5485 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 686:37] - node _T_5486 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5487 = and(_T_5485, _T_5486) @[ifu_mem_ctl.scala 686:59] - node _T_5488 = eq(perr_ic_index_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 686:102] - node _T_5489 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5490 = and(_T_5488, _T_5489) @[ifu_mem_ctl.scala 686:124] - node _T_5491 = or(_T_5487, _T_5490) @[ifu_mem_ctl.scala 686:81] - node _T_5492 = or(_T_5491, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5493 = bits(_T_5492, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][21] <= _T_5479 @[ifu_mem_ctl.scala 693:41] + node _T_5480 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5481 = eq(_T_5480, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5482 = and(ic_valid_ff, _T_5481) @[ifu_mem_ctl.scala 693:97] + node _T_5483 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5484 = and(_T_5482, _T_5483) @[ifu_mem_ctl.scala 693:122] + node _T_5485 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 694:37] + node _T_5486 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5487 = and(_T_5485, _T_5486) @[ifu_mem_ctl.scala 694:59] + node _T_5488 = eq(perr_ic_index_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 694:102] + node _T_5489 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5490 = and(_T_5488, _T_5489) @[ifu_mem_ctl.scala 694:124] + node _T_5491 = or(_T_5487, _T_5490) @[ifu_mem_ctl.scala 694:81] + node _T_5492 = or(_T_5491, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5493 = bits(_T_5492, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5494 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5493 : @[Reg.scala 28:19] _T_5494 <= _T_5484 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][22] <= _T_5494 @[ifu_mem_ctl.scala 685:41] - node _T_5495 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5496 = eq(_T_5495, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5497 = and(ic_valid_ff, _T_5496) @[ifu_mem_ctl.scala 685:97] - node _T_5498 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5499 = and(_T_5497, _T_5498) @[ifu_mem_ctl.scala 685:122] - node _T_5500 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 686:37] - node _T_5501 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5502 = and(_T_5500, _T_5501) @[ifu_mem_ctl.scala 686:59] - node _T_5503 = eq(perr_ic_index_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 686:102] - node _T_5504 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5505 = and(_T_5503, _T_5504) @[ifu_mem_ctl.scala 686:124] - node _T_5506 = or(_T_5502, _T_5505) @[ifu_mem_ctl.scala 686:81] - node _T_5507 = or(_T_5506, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5508 = bits(_T_5507, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][22] <= _T_5494 @[ifu_mem_ctl.scala 693:41] + node _T_5495 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5496 = eq(_T_5495, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5497 = and(ic_valid_ff, _T_5496) @[ifu_mem_ctl.scala 693:97] + node _T_5498 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5499 = and(_T_5497, _T_5498) @[ifu_mem_ctl.scala 693:122] + node _T_5500 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 694:37] + node _T_5501 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5502 = and(_T_5500, _T_5501) @[ifu_mem_ctl.scala 694:59] + node _T_5503 = eq(perr_ic_index_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 694:102] + node _T_5504 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5505 = and(_T_5503, _T_5504) @[ifu_mem_ctl.scala 694:124] + node _T_5506 = or(_T_5502, _T_5505) @[ifu_mem_ctl.scala 694:81] + node _T_5507 = or(_T_5506, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5508 = bits(_T_5507, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5509 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5508 : @[Reg.scala 28:19] _T_5509 <= _T_5499 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][23] <= _T_5509 @[ifu_mem_ctl.scala 685:41] - node _T_5510 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5511 = eq(_T_5510, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5512 = and(ic_valid_ff, _T_5511) @[ifu_mem_ctl.scala 685:97] - node _T_5513 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5514 = and(_T_5512, _T_5513) @[ifu_mem_ctl.scala 685:122] - node _T_5515 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 686:37] - node _T_5516 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5517 = and(_T_5515, _T_5516) @[ifu_mem_ctl.scala 686:59] - node _T_5518 = eq(perr_ic_index_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 686:102] - node _T_5519 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5520 = and(_T_5518, _T_5519) @[ifu_mem_ctl.scala 686:124] - node _T_5521 = or(_T_5517, _T_5520) @[ifu_mem_ctl.scala 686:81] - node _T_5522 = or(_T_5521, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5523 = bits(_T_5522, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][23] <= _T_5509 @[ifu_mem_ctl.scala 693:41] + node _T_5510 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5511 = eq(_T_5510, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5512 = and(ic_valid_ff, _T_5511) @[ifu_mem_ctl.scala 693:97] + node _T_5513 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5514 = and(_T_5512, _T_5513) @[ifu_mem_ctl.scala 693:122] + node _T_5515 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 694:37] + node _T_5516 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5517 = and(_T_5515, _T_5516) @[ifu_mem_ctl.scala 694:59] + node _T_5518 = eq(perr_ic_index_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 694:102] + node _T_5519 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5520 = and(_T_5518, _T_5519) @[ifu_mem_ctl.scala 694:124] + node _T_5521 = or(_T_5517, _T_5520) @[ifu_mem_ctl.scala 694:81] + node _T_5522 = or(_T_5521, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5523 = bits(_T_5522, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5524 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5523 : @[Reg.scala 28:19] _T_5524 <= _T_5514 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][24] <= _T_5524 @[ifu_mem_ctl.scala 685:41] - node _T_5525 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5526 = eq(_T_5525, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5527 = and(ic_valid_ff, _T_5526) @[ifu_mem_ctl.scala 685:97] - node _T_5528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5529 = and(_T_5527, _T_5528) @[ifu_mem_ctl.scala 685:122] - node _T_5530 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 686:37] - node _T_5531 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5532 = and(_T_5530, _T_5531) @[ifu_mem_ctl.scala 686:59] - node _T_5533 = eq(perr_ic_index_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 686:102] - node _T_5534 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5535 = and(_T_5533, _T_5534) @[ifu_mem_ctl.scala 686:124] - node _T_5536 = or(_T_5532, _T_5535) @[ifu_mem_ctl.scala 686:81] - node _T_5537 = or(_T_5536, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5538 = bits(_T_5537, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][24] <= _T_5524 @[ifu_mem_ctl.scala 693:41] + node _T_5525 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5526 = eq(_T_5525, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5527 = and(ic_valid_ff, _T_5526) @[ifu_mem_ctl.scala 693:97] + node _T_5528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5529 = and(_T_5527, _T_5528) @[ifu_mem_ctl.scala 693:122] + node _T_5530 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 694:37] + node _T_5531 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5532 = and(_T_5530, _T_5531) @[ifu_mem_ctl.scala 694:59] + node _T_5533 = eq(perr_ic_index_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 694:102] + node _T_5534 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5535 = and(_T_5533, _T_5534) @[ifu_mem_ctl.scala 694:124] + node _T_5536 = or(_T_5532, _T_5535) @[ifu_mem_ctl.scala 694:81] + node _T_5537 = or(_T_5536, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5538 = bits(_T_5537, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5539 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5538 : @[Reg.scala 28:19] _T_5539 <= _T_5529 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][25] <= _T_5539 @[ifu_mem_ctl.scala 685:41] - node _T_5540 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5541 = eq(_T_5540, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5542 = and(ic_valid_ff, _T_5541) @[ifu_mem_ctl.scala 685:97] - node _T_5543 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5544 = and(_T_5542, _T_5543) @[ifu_mem_ctl.scala 685:122] - node _T_5545 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 686:37] - node _T_5546 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5547 = and(_T_5545, _T_5546) @[ifu_mem_ctl.scala 686:59] - node _T_5548 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 686:102] - node _T_5549 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5550 = and(_T_5548, _T_5549) @[ifu_mem_ctl.scala 686:124] - node _T_5551 = or(_T_5547, _T_5550) @[ifu_mem_ctl.scala 686:81] - node _T_5552 = or(_T_5551, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5553 = bits(_T_5552, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][25] <= _T_5539 @[ifu_mem_ctl.scala 693:41] + node _T_5540 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5541 = eq(_T_5540, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5542 = and(ic_valid_ff, _T_5541) @[ifu_mem_ctl.scala 693:97] + node _T_5543 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5544 = and(_T_5542, _T_5543) @[ifu_mem_ctl.scala 693:122] + node _T_5545 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 694:37] + node _T_5546 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5547 = and(_T_5545, _T_5546) @[ifu_mem_ctl.scala 694:59] + node _T_5548 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 694:102] + node _T_5549 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5550 = and(_T_5548, _T_5549) @[ifu_mem_ctl.scala 694:124] + node _T_5551 = or(_T_5547, _T_5550) @[ifu_mem_ctl.scala 694:81] + node _T_5552 = or(_T_5551, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5553 = bits(_T_5552, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5554 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5553 : @[Reg.scala 28:19] _T_5554 <= _T_5544 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][26] <= _T_5554 @[ifu_mem_ctl.scala 685:41] - node _T_5555 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5556 = eq(_T_5555, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5557 = and(ic_valid_ff, _T_5556) @[ifu_mem_ctl.scala 685:97] - node _T_5558 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5559 = and(_T_5557, _T_5558) @[ifu_mem_ctl.scala 685:122] - node _T_5560 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 686:37] - node _T_5561 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5562 = and(_T_5560, _T_5561) @[ifu_mem_ctl.scala 686:59] - node _T_5563 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 686:102] - node _T_5564 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5565 = and(_T_5563, _T_5564) @[ifu_mem_ctl.scala 686:124] - node _T_5566 = or(_T_5562, _T_5565) @[ifu_mem_ctl.scala 686:81] - node _T_5567 = or(_T_5566, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5568 = bits(_T_5567, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][26] <= _T_5554 @[ifu_mem_ctl.scala 693:41] + node _T_5555 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5556 = eq(_T_5555, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5557 = and(ic_valid_ff, _T_5556) @[ifu_mem_ctl.scala 693:97] + node _T_5558 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5559 = and(_T_5557, _T_5558) @[ifu_mem_ctl.scala 693:122] + node _T_5560 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 694:37] + node _T_5561 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5562 = and(_T_5560, _T_5561) @[ifu_mem_ctl.scala 694:59] + node _T_5563 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 694:102] + node _T_5564 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5565 = and(_T_5563, _T_5564) @[ifu_mem_ctl.scala 694:124] + node _T_5566 = or(_T_5562, _T_5565) @[ifu_mem_ctl.scala 694:81] + node _T_5567 = or(_T_5566, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5568 = bits(_T_5567, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5569 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5568 : @[Reg.scala 28:19] _T_5569 <= _T_5559 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][27] <= _T_5569 @[ifu_mem_ctl.scala 685:41] - node _T_5570 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5571 = eq(_T_5570, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5572 = and(ic_valid_ff, _T_5571) @[ifu_mem_ctl.scala 685:97] - node _T_5573 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5574 = and(_T_5572, _T_5573) @[ifu_mem_ctl.scala 685:122] - node _T_5575 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 686:37] - node _T_5576 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5577 = and(_T_5575, _T_5576) @[ifu_mem_ctl.scala 686:59] - node _T_5578 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 686:102] - node _T_5579 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5580 = and(_T_5578, _T_5579) @[ifu_mem_ctl.scala 686:124] - node _T_5581 = or(_T_5577, _T_5580) @[ifu_mem_ctl.scala 686:81] - node _T_5582 = or(_T_5581, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5583 = bits(_T_5582, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][27] <= _T_5569 @[ifu_mem_ctl.scala 693:41] + node _T_5570 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5571 = eq(_T_5570, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5572 = and(ic_valid_ff, _T_5571) @[ifu_mem_ctl.scala 693:97] + node _T_5573 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5574 = and(_T_5572, _T_5573) @[ifu_mem_ctl.scala 693:122] + node _T_5575 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 694:37] + node _T_5576 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5577 = and(_T_5575, _T_5576) @[ifu_mem_ctl.scala 694:59] + node _T_5578 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 694:102] + node _T_5579 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5580 = and(_T_5578, _T_5579) @[ifu_mem_ctl.scala 694:124] + node _T_5581 = or(_T_5577, _T_5580) @[ifu_mem_ctl.scala 694:81] + node _T_5582 = or(_T_5581, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5583 = bits(_T_5582, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5584 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5583 : @[Reg.scala 28:19] _T_5584 <= _T_5574 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][28] <= _T_5584 @[ifu_mem_ctl.scala 685:41] - node _T_5585 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5586 = eq(_T_5585, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5587 = and(ic_valid_ff, _T_5586) @[ifu_mem_ctl.scala 685:97] - node _T_5588 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5589 = and(_T_5587, _T_5588) @[ifu_mem_ctl.scala 685:122] - node _T_5590 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 686:37] - node _T_5591 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5592 = and(_T_5590, _T_5591) @[ifu_mem_ctl.scala 686:59] - node _T_5593 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 686:102] - node _T_5594 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5595 = and(_T_5593, _T_5594) @[ifu_mem_ctl.scala 686:124] - node _T_5596 = or(_T_5592, _T_5595) @[ifu_mem_ctl.scala 686:81] - node _T_5597 = or(_T_5596, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5598 = bits(_T_5597, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][28] <= _T_5584 @[ifu_mem_ctl.scala 693:41] + node _T_5585 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5586 = eq(_T_5585, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5587 = and(ic_valid_ff, _T_5586) @[ifu_mem_ctl.scala 693:97] + node _T_5588 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5589 = and(_T_5587, _T_5588) @[ifu_mem_ctl.scala 693:122] + node _T_5590 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 694:37] + node _T_5591 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5592 = and(_T_5590, _T_5591) @[ifu_mem_ctl.scala 694:59] + node _T_5593 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 694:102] + node _T_5594 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5595 = and(_T_5593, _T_5594) @[ifu_mem_ctl.scala 694:124] + node _T_5596 = or(_T_5592, _T_5595) @[ifu_mem_ctl.scala 694:81] + node _T_5597 = or(_T_5596, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5598 = bits(_T_5597, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5599 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5598 : @[Reg.scala 28:19] _T_5599 <= _T_5589 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][29] <= _T_5599 @[ifu_mem_ctl.scala 685:41] - node _T_5600 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5601 = eq(_T_5600, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5602 = and(ic_valid_ff, _T_5601) @[ifu_mem_ctl.scala 685:97] - node _T_5603 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5604 = and(_T_5602, _T_5603) @[ifu_mem_ctl.scala 685:122] - node _T_5605 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 686:37] - node _T_5606 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5607 = and(_T_5605, _T_5606) @[ifu_mem_ctl.scala 686:59] - node _T_5608 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 686:102] - node _T_5609 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5610 = and(_T_5608, _T_5609) @[ifu_mem_ctl.scala 686:124] - node _T_5611 = or(_T_5607, _T_5610) @[ifu_mem_ctl.scala 686:81] - node _T_5612 = or(_T_5611, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5613 = bits(_T_5612, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][29] <= _T_5599 @[ifu_mem_ctl.scala 693:41] + node _T_5600 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5601 = eq(_T_5600, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5602 = and(ic_valid_ff, _T_5601) @[ifu_mem_ctl.scala 693:97] + node _T_5603 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5604 = and(_T_5602, _T_5603) @[ifu_mem_ctl.scala 693:122] + node _T_5605 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 694:37] + node _T_5606 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5607 = and(_T_5605, _T_5606) @[ifu_mem_ctl.scala 694:59] + node _T_5608 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 694:102] + node _T_5609 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5610 = and(_T_5608, _T_5609) @[ifu_mem_ctl.scala 694:124] + node _T_5611 = or(_T_5607, _T_5610) @[ifu_mem_ctl.scala 694:81] + node _T_5612 = or(_T_5611, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5613 = bits(_T_5612, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5614 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5613 : @[Reg.scala 28:19] _T_5614 <= _T_5604 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][30] <= _T_5614 @[ifu_mem_ctl.scala 685:41] - node _T_5615 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5616 = eq(_T_5615, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5617 = and(ic_valid_ff, _T_5616) @[ifu_mem_ctl.scala 685:97] - node _T_5618 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5619 = and(_T_5617, _T_5618) @[ifu_mem_ctl.scala 685:122] - node _T_5620 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 686:37] - node _T_5621 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_5622 = and(_T_5620, _T_5621) @[ifu_mem_ctl.scala 686:59] - node _T_5623 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 686:102] - node _T_5624 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_5625 = and(_T_5623, _T_5624) @[ifu_mem_ctl.scala 686:124] - node _T_5626 = or(_T_5622, _T_5625) @[ifu_mem_ctl.scala 686:81] - node _T_5627 = or(_T_5626, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5628 = bits(_T_5627, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][30] <= _T_5614 @[ifu_mem_ctl.scala 693:41] + node _T_5615 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5616 = eq(_T_5615, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5617 = and(ic_valid_ff, _T_5616) @[ifu_mem_ctl.scala 693:97] + node _T_5618 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5619 = and(_T_5617, _T_5618) @[ifu_mem_ctl.scala 693:122] + node _T_5620 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 694:37] + node _T_5621 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_5622 = and(_T_5620, _T_5621) @[ifu_mem_ctl.scala 694:59] + node _T_5623 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 694:102] + node _T_5624 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_5625 = and(_T_5623, _T_5624) @[ifu_mem_ctl.scala 694:124] + node _T_5626 = or(_T_5622, _T_5625) @[ifu_mem_ctl.scala 694:81] + node _T_5627 = or(_T_5626, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5628 = bits(_T_5627, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5629 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5628 : @[Reg.scala 28:19] _T_5629 <= _T_5619 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][31] <= _T_5629 @[ifu_mem_ctl.scala 685:41] - node _T_5630 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5631 = eq(_T_5630, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5632 = and(ic_valid_ff, _T_5631) @[ifu_mem_ctl.scala 685:97] - node _T_5633 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5634 = and(_T_5632, _T_5633) @[ifu_mem_ctl.scala 685:122] - node _T_5635 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 686:37] - node _T_5636 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5637 = and(_T_5635, _T_5636) @[ifu_mem_ctl.scala 686:59] - node _T_5638 = eq(perr_ic_index_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 686:102] - node _T_5639 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5640 = and(_T_5638, _T_5639) @[ifu_mem_ctl.scala 686:124] - node _T_5641 = or(_T_5637, _T_5640) @[ifu_mem_ctl.scala 686:81] - node _T_5642 = or(_T_5641, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5643 = bits(_T_5642, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][31] <= _T_5629 @[ifu_mem_ctl.scala 693:41] + node _T_5630 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5631 = eq(_T_5630, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5632 = and(ic_valid_ff, _T_5631) @[ifu_mem_ctl.scala 693:97] + node _T_5633 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5634 = and(_T_5632, _T_5633) @[ifu_mem_ctl.scala 693:122] + node _T_5635 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 694:37] + node _T_5636 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5637 = and(_T_5635, _T_5636) @[ifu_mem_ctl.scala 694:59] + node _T_5638 = eq(perr_ic_index_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 694:102] + node _T_5639 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5640 = and(_T_5638, _T_5639) @[ifu_mem_ctl.scala 694:124] + node _T_5641 = or(_T_5637, _T_5640) @[ifu_mem_ctl.scala 694:81] + node _T_5642 = or(_T_5641, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5643 = bits(_T_5642, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5644 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5643 : @[Reg.scala 28:19] _T_5644 <= _T_5634 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][0] <= _T_5644 @[ifu_mem_ctl.scala 685:41] - node _T_5645 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5646 = eq(_T_5645, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5647 = and(ic_valid_ff, _T_5646) @[ifu_mem_ctl.scala 685:97] - node _T_5648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5649 = and(_T_5647, _T_5648) @[ifu_mem_ctl.scala 685:122] - node _T_5650 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 686:37] - node _T_5651 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5652 = and(_T_5650, _T_5651) @[ifu_mem_ctl.scala 686:59] - node _T_5653 = eq(perr_ic_index_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 686:102] - node _T_5654 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5655 = and(_T_5653, _T_5654) @[ifu_mem_ctl.scala 686:124] - node _T_5656 = or(_T_5652, _T_5655) @[ifu_mem_ctl.scala 686:81] - node _T_5657 = or(_T_5656, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5658 = bits(_T_5657, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][0] <= _T_5644 @[ifu_mem_ctl.scala 693:41] + node _T_5645 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5646 = eq(_T_5645, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5647 = and(ic_valid_ff, _T_5646) @[ifu_mem_ctl.scala 693:97] + node _T_5648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5649 = and(_T_5647, _T_5648) @[ifu_mem_ctl.scala 693:122] + node _T_5650 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 694:37] + node _T_5651 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5652 = and(_T_5650, _T_5651) @[ifu_mem_ctl.scala 694:59] + node _T_5653 = eq(perr_ic_index_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 694:102] + node _T_5654 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5655 = and(_T_5653, _T_5654) @[ifu_mem_ctl.scala 694:124] + node _T_5656 = or(_T_5652, _T_5655) @[ifu_mem_ctl.scala 694:81] + node _T_5657 = or(_T_5656, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5658 = bits(_T_5657, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5659 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5658 : @[Reg.scala 28:19] _T_5659 <= _T_5649 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][1] <= _T_5659 @[ifu_mem_ctl.scala 685:41] - node _T_5660 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5661 = eq(_T_5660, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5662 = and(ic_valid_ff, _T_5661) @[ifu_mem_ctl.scala 685:97] - node _T_5663 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5664 = and(_T_5662, _T_5663) @[ifu_mem_ctl.scala 685:122] - node _T_5665 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 686:37] - node _T_5666 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5667 = and(_T_5665, _T_5666) @[ifu_mem_ctl.scala 686:59] - node _T_5668 = eq(perr_ic_index_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 686:102] - node _T_5669 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5670 = and(_T_5668, _T_5669) @[ifu_mem_ctl.scala 686:124] - node _T_5671 = or(_T_5667, _T_5670) @[ifu_mem_ctl.scala 686:81] - node _T_5672 = or(_T_5671, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5673 = bits(_T_5672, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][1] <= _T_5659 @[ifu_mem_ctl.scala 693:41] + node _T_5660 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5661 = eq(_T_5660, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5662 = and(ic_valid_ff, _T_5661) @[ifu_mem_ctl.scala 693:97] + node _T_5663 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5664 = and(_T_5662, _T_5663) @[ifu_mem_ctl.scala 693:122] + node _T_5665 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 694:37] + node _T_5666 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5667 = and(_T_5665, _T_5666) @[ifu_mem_ctl.scala 694:59] + node _T_5668 = eq(perr_ic_index_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 694:102] + node _T_5669 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5670 = and(_T_5668, _T_5669) @[ifu_mem_ctl.scala 694:124] + node _T_5671 = or(_T_5667, _T_5670) @[ifu_mem_ctl.scala 694:81] + node _T_5672 = or(_T_5671, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5673 = bits(_T_5672, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5674 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5673 : @[Reg.scala 28:19] _T_5674 <= _T_5664 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][2] <= _T_5674 @[ifu_mem_ctl.scala 685:41] - node _T_5675 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5676 = eq(_T_5675, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5677 = and(ic_valid_ff, _T_5676) @[ifu_mem_ctl.scala 685:97] - node _T_5678 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5679 = and(_T_5677, _T_5678) @[ifu_mem_ctl.scala 685:122] - node _T_5680 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 686:37] - node _T_5681 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5682 = and(_T_5680, _T_5681) @[ifu_mem_ctl.scala 686:59] - node _T_5683 = eq(perr_ic_index_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 686:102] - node _T_5684 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5685 = and(_T_5683, _T_5684) @[ifu_mem_ctl.scala 686:124] - node _T_5686 = or(_T_5682, _T_5685) @[ifu_mem_ctl.scala 686:81] - node _T_5687 = or(_T_5686, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5688 = bits(_T_5687, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][2] <= _T_5674 @[ifu_mem_ctl.scala 693:41] + node _T_5675 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5676 = eq(_T_5675, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5677 = and(ic_valid_ff, _T_5676) @[ifu_mem_ctl.scala 693:97] + node _T_5678 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5679 = and(_T_5677, _T_5678) @[ifu_mem_ctl.scala 693:122] + node _T_5680 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 694:37] + node _T_5681 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5682 = and(_T_5680, _T_5681) @[ifu_mem_ctl.scala 694:59] + node _T_5683 = eq(perr_ic_index_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 694:102] + node _T_5684 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5685 = and(_T_5683, _T_5684) @[ifu_mem_ctl.scala 694:124] + node _T_5686 = or(_T_5682, _T_5685) @[ifu_mem_ctl.scala 694:81] + node _T_5687 = or(_T_5686, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5688 = bits(_T_5687, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5689 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5688 : @[Reg.scala 28:19] _T_5689 <= _T_5679 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][3] <= _T_5689 @[ifu_mem_ctl.scala 685:41] - node _T_5690 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5691 = eq(_T_5690, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5692 = and(ic_valid_ff, _T_5691) @[ifu_mem_ctl.scala 685:97] - node _T_5693 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5694 = and(_T_5692, _T_5693) @[ifu_mem_ctl.scala 685:122] - node _T_5695 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 686:37] - node _T_5696 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5697 = and(_T_5695, _T_5696) @[ifu_mem_ctl.scala 686:59] - node _T_5698 = eq(perr_ic_index_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 686:102] - node _T_5699 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5700 = and(_T_5698, _T_5699) @[ifu_mem_ctl.scala 686:124] - node _T_5701 = or(_T_5697, _T_5700) @[ifu_mem_ctl.scala 686:81] - node _T_5702 = or(_T_5701, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5703 = bits(_T_5702, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][3] <= _T_5689 @[ifu_mem_ctl.scala 693:41] + node _T_5690 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5691 = eq(_T_5690, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5692 = and(ic_valid_ff, _T_5691) @[ifu_mem_ctl.scala 693:97] + node _T_5693 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5694 = and(_T_5692, _T_5693) @[ifu_mem_ctl.scala 693:122] + node _T_5695 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 694:37] + node _T_5696 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5697 = and(_T_5695, _T_5696) @[ifu_mem_ctl.scala 694:59] + node _T_5698 = eq(perr_ic_index_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 694:102] + node _T_5699 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5700 = and(_T_5698, _T_5699) @[ifu_mem_ctl.scala 694:124] + node _T_5701 = or(_T_5697, _T_5700) @[ifu_mem_ctl.scala 694:81] + node _T_5702 = or(_T_5701, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5703 = bits(_T_5702, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5704 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5703 : @[Reg.scala 28:19] _T_5704 <= _T_5694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][4] <= _T_5704 @[ifu_mem_ctl.scala 685:41] - node _T_5705 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5706 = eq(_T_5705, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5707 = and(ic_valid_ff, _T_5706) @[ifu_mem_ctl.scala 685:97] - node _T_5708 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5709 = and(_T_5707, _T_5708) @[ifu_mem_ctl.scala 685:122] - node _T_5710 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 686:37] - node _T_5711 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5712 = and(_T_5710, _T_5711) @[ifu_mem_ctl.scala 686:59] - node _T_5713 = eq(perr_ic_index_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 686:102] - node _T_5714 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5715 = and(_T_5713, _T_5714) @[ifu_mem_ctl.scala 686:124] - node _T_5716 = or(_T_5712, _T_5715) @[ifu_mem_ctl.scala 686:81] - node _T_5717 = or(_T_5716, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5718 = bits(_T_5717, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][4] <= _T_5704 @[ifu_mem_ctl.scala 693:41] + node _T_5705 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5706 = eq(_T_5705, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5707 = and(ic_valid_ff, _T_5706) @[ifu_mem_ctl.scala 693:97] + node _T_5708 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5709 = and(_T_5707, _T_5708) @[ifu_mem_ctl.scala 693:122] + node _T_5710 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 694:37] + node _T_5711 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5712 = and(_T_5710, _T_5711) @[ifu_mem_ctl.scala 694:59] + node _T_5713 = eq(perr_ic_index_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 694:102] + node _T_5714 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5715 = and(_T_5713, _T_5714) @[ifu_mem_ctl.scala 694:124] + node _T_5716 = or(_T_5712, _T_5715) @[ifu_mem_ctl.scala 694:81] + node _T_5717 = or(_T_5716, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5718 = bits(_T_5717, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5719 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5718 : @[Reg.scala 28:19] _T_5719 <= _T_5709 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][5] <= _T_5719 @[ifu_mem_ctl.scala 685:41] - node _T_5720 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5721 = eq(_T_5720, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5722 = and(ic_valid_ff, _T_5721) @[ifu_mem_ctl.scala 685:97] - node _T_5723 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5724 = and(_T_5722, _T_5723) @[ifu_mem_ctl.scala 685:122] - node _T_5725 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 686:37] - node _T_5726 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5727 = and(_T_5725, _T_5726) @[ifu_mem_ctl.scala 686:59] - node _T_5728 = eq(perr_ic_index_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 686:102] - node _T_5729 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5730 = and(_T_5728, _T_5729) @[ifu_mem_ctl.scala 686:124] - node _T_5731 = or(_T_5727, _T_5730) @[ifu_mem_ctl.scala 686:81] - node _T_5732 = or(_T_5731, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5733 = bits(_T_5732, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][5] <= _T_5719 @[ifu_mem_ctl.scala 693:41] + node _T_5720 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5721 = eq(_T_5720, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5722 = and(ic_valid_ff, _T_5721) @[ifu_mem_ctl.scala 693:97] + node _T_5723 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5724 = and(_T_5722, _T_5723) @[ifu_mem_ctl.scala 693:122] + node _T_5725 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 694:37] + node _T_5726 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5727 = and(_T_5725, _T_5726) @[ifu_mem_ctl.scala 694:59] + node _T_5728 = eq(perr_ic_index_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 694:102] + node _T_5729 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5730 = and(_T_5728, _T_5729) @[ifu_mem_ctl.scala 694:124] + node _T_5731 = or(_T_5727, _T_5730) @[ifu_mem_ctl.scala 694:81] + node _T_5732 = or(_T_5731, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5733 = bits(_T_5732, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5734 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5733 : @[Reg.scala 28:19] _T_5734 <= _T_5724 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][6] <= _T_5734 @[ifu_mem_ctl.scala 685:41] - node _T_5735 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5736 = eq(_T_5735, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5737 = and(ic_valid_ff, _T_5736) @[ifu_mem_ctl.scala 685:97] - node _T_5738 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5739 = and(_T_5737, _T_5738) @[ifu_mem_ctl.scala 685:122] - node _T_5740 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 686:37] - node _T_5741 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5742 = and(_T_5740, _T_5741) @[ifu_mem_ctl.scala 686:59] - node _T_5743 = eq(perr_ic_index_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 686:102] - node _T_5744 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5745 = and(_T_5743, _T_5744) @[ifu_mem_ctl.scala 686:124] - node _T_5746 = or(_T_5742, _T_5745) @[ifu_mem_ctl.scala 686:81] - node _T_5747 = or(_T_5746, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5748 = bits(_T_5747, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][6] <= _T_5734 @[ifu_mem_ctl.scala 693:41] + node _T_5735 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5736 = eq(_T_5735, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5737 = and(ic_valid_ff, _T_5736) @[ifu_mem_ctl.scala 693:97] + node _T_5738 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5739 = and(_T_5737, _T_5738) @[ifu_mem_ctl.scala 693:122] + node _T_5740 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 694:37] + node _T_5741 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5742 = and(_T_5740, _T_5741) @[ifu_mem_ctl.scala 694:59] + node _T_5743 = eq(perr_ic_index_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 694:102] + node _T_5744 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5745 = and(_T_5743, _T_5744) @[ifu_mem_ctl.scala 694:124] + node _T_5746 = or(_T_5742, _T_5745) @[ifu_mem_ctl.scala 694:81] + node _T_5747 = or(_T_5746, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5748 = bits(_T_5747, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5749 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5748 : @[Reg.scala 28:19] _T_5749 <= _T_5739 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][7] <= _T_5749 @[ifu_mem_ctl.scala 685:41] - node _T_5750 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5751 = eq(_T_5750, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5752 = and(ic_valid_ff, _T_5751) @[ifu_mem_ctl.scala 685:97] - node _T_5753 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5754 = and(_T_5752, _T_5753) @[ifu_mem_ctl.scala 685:122] - node _T_5755 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 686:37] - node _T_5756 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5757 = and(_T_5755, _T_5756) @[ifu_mem_ctl.scala 686:59] - node _T_5758 = eq(perr_ic_index_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 686:102] - node _T_5759 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5760 = and(_T_5758, _T_5759) @[ifu_mem_ctl.scala 686:124] - node _T_5761 = or(_T_5757, _T_5760) @[ifu_mem_ctl.scala 686:81] - node _T_5762 = or(_T_5761, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5763 = bits(_T_5762, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][7] <= _T_5749 @[ifu_mem_ctl.scala 693:41] + node _T_5750 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5751 = eq(_T_5750, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5752 = and(ic_valid_ff, _T_5751) @[ifu_mem_ctl.scala 693:97] + node _T_5753 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5754 = and(_T_5752, _T_5753) @[ifu_mem_ctl.scala 693:122] + node _T_5755 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 694:37] + node _T_5756 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5757 = and(_T_5755, _T_5756) @[ifu_mem_ctl.scala 694:59] + node _T_5758 = eq(perr_ic_index_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 694:102] + node _T_5759 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5760 = and(_T_5758, _T_5759) @[ifu_mem_ctl.scala 694:124] + node _T_5761 = or(_T_5757, _T_5760) @[ifu_mem_ctl.scala 694:81] + node _T_5762 = or(_T_5761, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5763 = bits(_T_5762, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5764 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5763 : @[Reg.scala 28:19] _T_5764 <= _T_5754 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][8] <= _T_5764 @[ifu_mem_ctl.scala 685:41] - node _T_5765 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5766 = eq(_T_5765, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5767 = and(ic_valid_ff, _T_5766) @[ifu_mem_ctl.scala 685:97] - node _T_5768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5769 = and(_T_5767, _T_5768) @[ifu_mem_ctl.scala 685:122] - node _T_5770 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 686:37] - node _T_5771 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5772 = and(_T_5770, _T_5771) @[ifu_mem_ctl.scala 686:59] - node _T_5773 = eq(perr_ic_index_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 686:102] - node _T_5774 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5775 = and(_T_5773, _T_5774) @[ifu_mem_ctl.scala 686:124] - node _T_5776 = or(_T_5772, _T_5775) @[ifu_mem_ctl.scala 686:81] - node _T_5777 = or(_T_5776, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5778 = bits(_T_5777, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][8] <= _T_5764 @[ifu_mem_ctl.scala 693:41] + node _T_5765 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5766 = eq(_T_5765, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5767 = and(ic_valid_ff, _T_5766) @[ifu_mem_ctl.scala 693:97] + node _T_5768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5769 = and(_T_5767, _T_5768) @[ifu_mem_ctl.scala 693:122] + node _T_5770 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 694:37] + node _T_5771 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5772 = and(_T_5770, _T_5771) @[ifu_mem_ctl.scala 694:59] + node _T_5773 = eq(perr_ic_index_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 694:102] + node _T_5774 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5775 = and(_T_5773, _T_5774) @[ifu_mem_ctl.scala 694:124] + node _T_5776 = or(_T_5772, _T_5775) @[ifu_mem_ctl.scala 694:81] + node _T_5777 = or(_T_5776, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5778 = bits(_T_5777, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5779 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5778 : @[Reg.scala 28:19] _T_5779 <= _T_5769 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][9] <= _T_5779 @[ifu_mem_ctl.scala 685:41] - node _T_5780 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5781 = eq(_T_5780, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5782 = and(ic_valid_ff, _T_5781) @[ifu_mem_ctl.scala 685:97] - node _T_5783 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5784 = and(_T_5782, _T_5783) @[ifu_mem_ctl.scala 685:122] - node _T_5785 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 686:37] - node _T_5786 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5787 = and(_T_5785, _T_5786) @[ifu_mem_ctl.scala 686:59] - node _T_5788 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 686:102] - node _T_5789 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5790 = and(_T_5788, _T_5789) @[ifu_mem_ctl.scala 686:124] - node _T_5791 = or(_T_5787, _T_5790) @[ifu_mem_ctl.scala 686:81] - node _T_5792 = or(_T_5791, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5793 = bits(_T_5792, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][9] <= _T_5779 @[ifu_mem_ctl.scala 693:41] + node _T_5780 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5781 = eq(_T_5780, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5782 = and(ic_valid_ff, _T_5781) @[ifu_mem_ctl.scala 693:97] + node _T_5783 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5784 = and(_T_5782, _T_5783) @[ifu_mem_ctl.scala 693:122] + node _T_5785 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 694:37] + node _T_5786 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5787 = and(_T_5785, _T_5786) @[ifu_mem_ctl.scala 694:59] + node _T_5788 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 694:102] + node _T_5789 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5790 = and(_T_5788, _T_5789) @[ifu_mem_ctl.scala 694:124] + node _T_5791 = or(_T_5787, _T_5790) @[ifu_mem_ctl.scala 694:81] + node _T_5792 = or(_T_5791, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5793 = bits(_T_5792, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5794 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5793 : @[Reg.scala 28:19] _T_5794 <= _T_5784 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][10] <= _T_5794 @[ifu_mem_ctl.scala 685:41] - node _T_5795 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5796 = eq(_T_5795, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5797 = and(ic_valid_ff, _T_5796) @[ifu_mem_ctl.scala 685:97] - node _T_5798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5799 = and(_T_5797, _T_5798) @[ifu_mem_ctl.scala 685:122] - node _T_5800 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 686:37] - node _T_5801 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5802 = and(_T_5800, _T_5801) @[ifu_mem_ctl.scala 686:59] - node _T_5803 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 686:102] - node _T_5804 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5805 = and(_T_5803, _T_5804) @[ifu_mem_ctl.scala 686:124] - node _T_5806 = or(_T_5802, _T_5805) @[ifu_mem_ctl.scala 686:81] - node _T_5807 = or(_T_5806, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5808 = bits(_T_5807, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][10] <= _T_5794 @[ifu_mem_ctl.scala 693:41] + node _T_5795 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5796 = eq(_T_5795, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5797 = and(ic_valid_ff, _T_5796) @[ifu_mem_ctl.scala 693:97] + node _T_5798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5799 = and(_T_5797, _T_5798) @[ifu_mem_ctl.scala 693:122] + node _T_5800 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 694:37] + node _T_5801 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5802 = and(_T_5800, _T_5801) @[ifu_mem_ctl.scala 694:59] + node _T_5803 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 694:102] + node _T_5804 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5805 = and(_T_5803, _T_5804) @[ifu_mem_ctl.scala 694:124] + node _T_5806 = or(_T_5802, _T_5805) @[ifu_mem_ctl.scala 694:81] + node _T_5807 = or(_T_5806, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5808 = bits(_T_5807, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5809 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5808 : @[Reg.scala 28:19] _T_5809 <= _T_5799 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][11] <= _T_5809 @[ifu_mem_ctl.scala 685:41] - node _T_5810 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5811 = eq(_T_5810, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5812 = and(ic_valid_ff, _T_5811) @[ifu_mem_ctl.scala 685:97] - node _T_5813 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5814 = and(_T_5812, _T_5813) @[ifu_mem_ctl.scala 685:122] - node _T_5815 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 686:37] - node _T_5816 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5817 = and(_T_5815, _T_5816) @[ifu_mem_ctl.scala 686:59] - node _T_5818 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 686:102] - node _T_5819 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5820 = and(_T_5818, _T_5819) @[ifu_mem_ctl.scala 686:124] - node _T_5821 = or(_T_5817, _T_5820) @[ifu_mem_ctl.scala 686:81] - node _T_5822 = or(_T_5821, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5823 = bits(_T_5822, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][11] <= _T_5809 @[ifu_mem_ctl.scala 693:41] + node _T_5810 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5811 = eq(_T_5810, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5812 = and(ic_valid_ff, _T_5811) @[ifu_mem_ctl.scala 693:97] + node _T_5813 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5814 = and(_T_5812, _T_5813) @[ifu_mem_ctl.scala 693:122] + node _T_5815 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 694:37] + node _T_5816 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5817 = and(_T_5815, _T_5816) @[ifu_mem_ctl.scala 694:59] + node _T_5818 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 694:102] + node _T_5819 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5820 = and(_T_5818, _T_5819) @[ifu_mem_ctl.scala 694:124] + node _T_5821 = or(_T_5817, _T_5820) @[ifu_mem_ctl.scala 694:81] + node _T_5822 = or(_T_5821, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5823 = bits(_T_5822, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5824 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5823 : @[Reg.scala 28:19] _T_5824 <= _T_5814 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][12] <= _T_5824 @[ifu_mem_ctl.scala 685:41] - node _T_5825 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5826 = eq(_T_5825, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5827 = and(ic_valid_ff, _T_5826) @[ifu_mem_ctl.scala 685:97] - node _T_5828 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5829 = and(_T_5827, _T_5828) @[ifu_mem_ctl.scala 685:122] - node _T_5830 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 686:37] - node _T_5831 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5832 = and(_T_5830, _T_5831) @[ifu_mem_ctl.scala 686:59] - node _T_5833 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 686:102] - node _T_5834 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5835 = and(_T_5833, _T_5834) @[ifu_mem_ctl.scala 686:124] - node _T_5836 = or(_T_5832, _T_5835) @[ifu_mem_ctl.scala 686:81] - node _T_5837 = or(_T_5836, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5838 = bits(_T_5837, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][12] <= _T_5824 @[ifu_mem_ctl.scala 693:41] + node _T_5825 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5826 = eq(_T_5825, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5827 = and(ic_valid_ff, _T_5826) @[ifu_mem_ctl.scala 693:97] + node _T_5828 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5829 = and(_T_5827, _T_5828) @[ifu_mem_ctl.scala 693:122] + node _T_5830 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 694:37] + node _T_5831 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5832 = and(_T_5830, _T_5831) @[ifu_mem_ctl.scala 694:59] + node _T_5833 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 694:102] + node _T_5834 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5835 = and(_T_5833, _T_5834) @[ifu_mem_ctl.scala 694:124] + node _T_5836 = or(_T_5832, _T_5835) @[ifu_mem_ctl.scala 694:81] + node _T_5837 = or(_T_5836, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5838 = bits(_T_5837, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5839 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5838 : @[Reg.scala 28:19] _T_5839 <= _T_5829 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][13] <= _T_5839 @[ifu_mem_ctl.scala 685:41] - node _T_5840 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5841 = eq(_T_5840, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5842 = and(ic_valid_ff, _T_5841) @[ifu_mem_ctl.scala 685:97] - node _T_5843 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5844 = and(_T_5842, _T_5843) @[ifu_mem_ctl.scala 685:122] - node _T_5845 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 686:37] - node _T_5846 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5847 = and(_T_5845, _T_5846) @[ifu_mem_ctl.scala 686:59] - node _T_5848 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 686:102] - node _T_5849 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5850 = and(_T_5848, _T_5849) @[ifu_mem_ctl.scala 686:124] - node _T_5851 = or(_T_5847, _T_5850) @[ifu_mem_ctl.scala 686:81] - node _T_5852 = or(_T_5851, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5853 = bits(_T_5852, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][13] <= _T_5839 @[ifu_mem_ctl.scala 693:41] + node _T_5840 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5841 = eq(_T_5840, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5842 = and(ic_valid_ff, _T_5841) @[ifu_mem_ctl.scala 693:97] + node _T_5843 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5844 = and(_T_5842, _T_5843) @[ifu_mem_ctl.scala 693:122] + node _T_5845 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 694:37] + node _T_5846 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5847 = and(_T_5845, _T_5846) @[ifu_mem_ctl.scala 694:59] + node _T_5848 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 694:102] + node _T_5849 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5850 = and(_T_5848, _T_5849) @[ifu_mem_ctl.scala 694:124] + node _T_5851 = or(_T_5847, _T_5850) @[ifu_mem_ctl.scala 694:81] + node _T_5852 = or(_T_5851, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5853 = bits(_T_5852, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5854 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5853 : @[Reg.scala 28:19] _T_5854 <= _T_5844 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][14] <= _T_5854 @[ifu_mem_ctl.scala 685:41] - node _T_5855 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5856 = eq(_T_5855, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5857 = and(ic_valid_ff, _T_5856) @[ifu_mem_ctl.scala 685:97] - node _T_5858 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5859 = and(_T_5857, _T_5858) @[ifu_mem_ctl.scala 685:122] - node _T_5860 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 686:37] - node _T_5861 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5862 = and(_T_5860, _T_5861) @[ifu_mem_ctl.scala 686:59] - node _T_5863 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 686:102] - node _T_5864 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5865 = and(_T_5863, _T_5864) @[ifu_mem_ctl.scala 686:124] - node _T_5866 = or(_T_5862, _T_5865) @[ifu_mem_ctl.scala 686:81] - node _T_5867 = or(_T_5866, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5868 = bits(_T_5867, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][14] <= _T_5854 @[ifu_mem_ctl.scala 693:41] + node _T_5855 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5856 = eq(_T_5855, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5857 = and(ic_valid_ff, _T_5856) @[ifu_mem_ctl.scala 693:97] + node _T_5858 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5859 = and(_T_5857, _T_5858) @[ifu_mem_ctl.scala 693:122] + node _T_5860 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 694:37] + node _T_5861 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5862 = and(_T_5860, _T_5861) @[ifu_mem_ctl.scala 694:59] + node _T_5863 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 694:102] + node _T_5864 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5865 = and(_T_5863, _T_5864) @[ifu_mem_ctl.scala 694:124] + node _T_5866 = or(_T_5862, _T_5865) @[ifu_mem_ctl.scala 694:81] + node _T_5867 = or(_T_5866, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5868 = bits(_T_5867, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5869 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5868 : @[Reg.scala 28:19] _T_5869 <= _T_5859 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][15] <= _T_5869 @[ifu_mem_ctl.scala 685:41] - node _T_5870 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5871 = eq(_T_5870, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5872 = and(ic_valid_ff, _T_5871) @[ifu_mem_ctl.scala 685:97] - node _T_5873 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5874 = and(_T_5872, _T_5873) @[ifu_mem_ctl.scala 685:122] - node _T_5875 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 686:37] - node _T_5876 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5877 = and(_T_5875, _T_5876) @[ifu_mem_ctl.scala 686:59] - node _T_5878 = eq(perr_ic_index_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 686:102] - node _T_5879 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5880 = and(_T_5878, _T_5879) @[ifu_mem_ctl.scala 686:124] - node _T_5881 = or(_T_5877, _T_5880) @[ifu_mem_ctl.scala 686:81] - node _T_5882 = or(_T_5881, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5883 = bits(_T_5882, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][15] <= _T_5869 @[ifu_mem_ctl.scala 693:41] + node _T_5870 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5871 = eq(_T_5870, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5872 = and(ic_valid_ff, _T_5871) @[ifu_mem_ctl.scala 693:97] + node _T_5873 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5874 = and(_T_5872, _T_5873) @[ifu_mem_ctl.scala 693:122] + node _T_5875 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 694:37] + node _T_5876 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5877 = and(_T_5875, _T_5876) @[ifu_mem_ctl.scala 694:59] + node _T_5878 = eq(perr_ic_index_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 694:102] + node _T_5879 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5880 = and(_T_5878, _T_5879) @[ifu_mem_ctl.scala 694:124] + node _T_5881 = or(_T_5877, _T_5880) @[ifu_mem_ctl.scala 694:81] + node _T_5882 = or(_T_5881, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5883 = bits(_T_5882, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5884 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5883 : @[Reg.scala 28:19] _T_5884 <= _T_5874 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][16] <= _T_5884 @[ifu_mem_ctl.scala 685:41] - node _T_5885 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5886 = eq(_T_5885, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5887 = and(ic_valid_ff, _T_5886) @[ifu_mem_ctl.scala 685:97] - node _T_5888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5889 = and(_T_5887, _T_5888) @[ifu_mem_ctl.scala 685:122] - node _T_5890 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 686:37] - node _T_5891 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5892 = and(_T_5890, _T_5891) @[ifu_mem_ctl.scala 686:59] - node _T_5893 = eq(perr_ic_index_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 686:102] - node _T_5894 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5895 = and(_T_5893, _T_5894) @[ifu_mem_ctl.scala 686:124] - node _T_5896 = or(_T_5892, _T_5895) @[ifu_mem_ctl.scala 686:81] - node _T_5897 = or(_T_5896, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5898 = bits(_T_5897, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][16] <= _T_5884 @[ifu_mem_ctl.scala 693:41] + node _T_5885 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5886 = eq(_T_5885, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5887 = and(ic_valid_ff, _T_5886) @[ifu_mem_ctl.scala 693:97] + node _T_5888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5889 = and(_T_5887, _T_5888) @[ifu_mem_ctl.scala 693:122] + node _T_5890 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 694:37] + node _T_5891 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5892 = and(_T_5890, _T_5891) @[ifu_mem_ctl.scala 694:59] + node _T_5893 = eq(perr_ic_index_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 694:102] + node _T_5894 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5895 = and(_T_5893, _T_5894) @[ifu_mem_ctl.scala 694:124] + node _T_5896 = or(_T_5892, _T_5895) @[ifu_mem_ctl.scala 694:81] + node _T_5897 = or(_T_5896, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5898 = bits(_T_5897, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5899 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5898 : @[Reg.scala 28:19] _T_5899 <= _T_5889 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][17] <= _T_5899 @[ifu_mem_ctl.scala 685:41] - node _T_5900 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5901 = eq(_T_5900, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5902 = and(ic_valid_ff, _T_5901) @[ifu_mem_ctl.scala 685:97] - node _T_5903 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5904 = and(_T_5902, _T_5903) @[ifu_mem_ctl.scala 685:122] - node _T_5905 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 686:37] - node _T_5906 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5907 = and(_T_5905, _T_5906) @[ifu_mem_ctl.scala 686:59] - node _T_5908 = eq(perr_ic_index_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 686:102] - node _T_5909 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5910 = and(_T_5908, _T_5909) @[ifu_mem_ctl.scala 686:124] - node _T_5911 = or(_T_5907, _T_5910) @[ifu_mem_ctl.scala 686:81] - node _T_5912 = or(_T_5911, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5913 = bits(_T_5912, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][17] <= _T_5899 @[ifu_mem_ctl.scala 693:41] + node _T_5900 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5901 = eq(_T_5900, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5902 = and(ic_valid_ff, _T_5901) @[ifu_mem_ctl.scala 693:97] + node _T_5903 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5904 = and(_T_5902, _T_5903) @[ifu_mem_ctl.scala 693:122] + node _T_5905 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 694:37] + node _T_5906 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5907 = and(_T_5905, _T_5906) @[ifu_mem_ctl.scala 694:59] + node _T_5908 = eq(perr_ic_index_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 694:102] + node _T_5909 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5910 = and(_T_5908, _T_5909) @[ifu_mem_ctl.scala 694:124] + node _T_5911 = or(_T_5907, _T_5910) @[ifu_mem_ctl.scala 694:81] + node _T_5912 = or(_T_5911, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5913 = bits(_T_5912, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5914 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5913 : @[Reg.scala 28:19] _T_5914 <= _T_5904 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][18] <= _T_5914 @[ifu_mem_ctl.scala 685:41] - node _T_5915 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5916 = eq(_T_5915, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5917 = and(ic_valid_ff, _T_5916) @[ifu_mem_ctl.scala 685:97] - node _T_5918 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5919 = and(_T_5917, _T_5918) @[ifu_mem_ctl.scala 685:122] - node _T_5920 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 686:37] - node _T_5921 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5922 = and(_T_5920, _T_5921) @[ifu_mem_ctl.scala 686:59] - node _T_5923 = eq(perr_ic_index_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 686:102] - node _T_5924 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5925 = and(_T_5923, _T_5924) @[ifu_mem_ctl.scala 686:124] - node _T_5926 = or(_T_5922, _T_5925) @[ifu_mem_ctl.scala 686:81] - node _T_5927 = or(_T_5926, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5928 = bits(_T_5927, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][18] <= _T_5914 @[ifu_mem_ctl.scala 693:41] + node _T_5915 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5916 = eq(_T_5915, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5917 = and(ic_valid_ff, _T_5916) @[ifu_mem_ctl.scala 693:97] + node _T_5918 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5919 = and(_T_5917, _T_5918) @[ifu_mem_ctl.scala 693:122] + node _T_5920 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 694:37] + node _T_5921 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5922 = and(_T_5920, _T_5921) @[ifu_mem_ctl.scala 694:59] + node _T_5923 = eq(perr_ic_index_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 694:102] + node _T_5924 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5925 = and(_T_5923, _T_5924) @[ifu_mem_ctl.scala 694:124] + node _T_5926 = or(_T_5922, _T_5925) @[ifu_mem_ctl.scala 694:81] + node _T_5927 = or(_T_5926, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5928 = bits(_T_5927, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5929 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5928 : @[Reg.scala 28:19] _T_5929 <= _T_5919 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][19] <= _T_5929 @[ifu_mem_ctl.scala 685:41] - node _T_5930 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5931 = eq(_T_5930, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5932 = and(ic_valid_ff, _T_5931) @[ifu_mem_ctl.scala 685:97] - node _T_5933 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5934 = and(_T_5932, _T_5933) @[ifu_mem_ctl.scala 685:122] - node _T_5935 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 686:37] - node _T_5936 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5937 = and(_T_5935, _T_5936) @[ifu_mem_ctl.scala 686:59] - node _T_5938 = eq(perr_ic_index_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 686:102] - node _T_5939 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5940 = and(_T_5938, _T_5939) @[ifu_mem_ctl.scala 686:124] - node _T_5941 = or(_T_5937, _T_5940) @[ifu_mem_ctl.scala 686:81] - node _T_5942 = or(_T_5941, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5943 = bits(_T_5942, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][19] <= _T_5929 @[ifu_mem_ctl.scala 693:41] + node _T_5930 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5931 = eq(_T_5930, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5932 = and(ic_valid_ff, _T_5931) @[ifu_mem_ctl.scala 693:97] + node _T_5933 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5934 = and(_T_5932, _T_5933) @[ifu_mem_ctl.scala 693:122] + node _T_5935 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 694:37] + node _T_5936 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5937 = and(_T_5935, _T_5936) @[ifu_mem_ctl.scala 694:59] + node _T_5938 = eq(perr_ic_index_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 694:102] + node _T_5939 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5940 = and(_T_5938, _T_5939) @[ifu_mem_ctl.scala 694:124] + node _T_5941 = or(_T_5937, _T_5940) @[ifu_mem_ctl.scala 694:81] + node _T_5942 = or(_T_5941, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5943 = bits(_T_5942, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5944 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5943 : @[Reg.scala 28:19] _T_5944 <= _T_5934 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][20] <= _T_5944 @[ifu_mem_ctl.scala 685:41] - node _T_5945 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5946 = eq(_T_5945, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5947 = and(ic_valid_ff, _T_5946) @[ifu_mem_ctl.scala 685:97] - node _T_5948 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5949 = and(_T_5947, _T_5948) @[ifu_mem_ctl.scala 685:122] - node _T_5950 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 686:37] - node _T_5951 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5952 = and(_T_5950, _T_5951) @[ifu_mem_ctl.scala 686:59] - node _T_5953 = eq(perr_ic_index_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 686:102] - node _T_5954 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5955 = and(_T_5953, _T_5954) @[ifu_mem_ctl.scala 686:124] - node _T_5956 = or(_T_5952, _T_5955) @[ifu_mem_ctl.scala 686:81] - node _T_5957 = or(_T_5956, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5958 = bits(_T_5957, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][20] <= _T_5944 @[ifu_mem_ctl.scala 693:41] + node _T_5945 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5946 = eq(_T_5945, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5947 = and(ic_valid_ff, _T_5946) @[ifu_mem_ctl.scala 693:97] + node _T_5948 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5949 = and(_T_5947, _T_5948) @[ifu_mem_ctl.scala 693:122] + node _T_5950 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 694:37] + node _T_5951 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5952 = and(_T_5950, _T_5951) @[ifu_mem_ctl.scala 694:59] + node _T_5953 = eq(perr_ic_index_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 694:102] + node _T_5954 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5955 = and(_T_5953, _T_5954) @[ifu_mem_ctl.scala 694:124] + node _T_5956 = or(_T_5952, _T_5955) @[ifu_mem_ctl.scala 694:81] + node _T_5957 = or(_T_5956, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5958 = bits(_T_5957, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5959 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5958 : @[Reg.scala 28:19] _T_5959 <= _T_5949 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][21] <= _T_5959 @[ifu_mem_ctl.scala 685:41] - node _T_5960 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5961 = eq(_T_5960, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5962 = and(ic_valid_ff, _T_5961) @[ifu_mem_ctl.scala 685:97] - node _T_5963 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5964 = and(_T_5962, _T_5963) @[ifu_mem_ctl.scala 685:122] - node _T_5965 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 686:37] - node _T_5966 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5967 = and(_T_5965, _T_5966) @[ifu_mem_ctl.scala 686:59] - node _T_5968 = eq(perr_ic_index_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 686:102] - node _T_5969 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5970 = and(_T_5968, _T_5969) @[ifu_mem_ctl.scala 686:124] - node _T_5971 = or(_T_5967, _T_5970) @[ifu_mem_ctl.scala 686:81] - node _T_5972 = or(_T_5971, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5973 = bits(_T_5972, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][21] <= _T_5959 @[ifu_mem_ctl.scala 693:41] + node _T_5960 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5961 = eq(_T_5960, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5962 = and(ic_valid_ff, _T_5961) @[ifu_mem_ctl.scala 693:97] + node _T_5963 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5964 = and(_T_5962, _T_5963) @[ifu_mem_ctl.scala 693:122] + node _T_5965 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 694:37] + node _T_5966 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5967 = and(_T_5965, _T_5966) @[ifu_mem_ctl.scala 694:59] + node _T_5968 = eq(perr_ic_index_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 694:102] + node _T_5969 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5970 = and(_T_5968, _T_5969) @[ifu_mem_ctl.scala 694:124] + node _T_5971 = or(_T_5967, _T_5970) @[ifu_mem_ctl.scala 694:81] + node _T_5972 = or(_T_5971, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5973 = bits(_T_5972, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5974 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5973 : @[Reg.scala 28:19] _T_5974 <= _T_5964 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][22] <= _T_5974 @[ifu_mem_ctl.scala 685:41] - node _T_5975 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5976 = eq(_T_5975, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5977 = and(ic_valid_ff, _T_5976) @[ifu_mem_ctl.scala 685:97] - node _T_5978 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5979 = and(_T_5977, _T_5978) @[ifu_mem_ctl.scala 685:122] - node _T_5980 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 686:37] - node _T_5981 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5982 = and(_T_5980, _T_5981) @[ifu_mem_ctl.scala 686:59] - node _T_5983 = eq(perr_ic_index_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 686:102] - node _T_5984 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_5985 = and(_T_5983, _T_5984) @[ifu_mem_ctl.scala 686:124] - node _T_5986 = or(_T_5982, _T_5985) @[ifu_mem_ctl.scala 686:81] - node _T_5987 = or(_T_5986, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_5988 = bits(_T_5987, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][22] <= _T_5974 @[ifu_mem_ctl.scala 693:41] + node _T_5975 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5976 = eq(_T_5975, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5977 = and(ic_valid_ff, _T_5976) @[ifu_mem_ctl.scala 693:97] + node _T_5978 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5979 = and(_T_5977, _T_5978) @[ifu_mem_ctl.scala 693:122] + node _T_5980 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 694:37] + node _T_5981 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5982 = and(_T_5980, _T_5981) @[ifu_mem_ctl.scala 694:59] + node _T_5983 = eq(perr_ic_index_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 694:102] + node _T_5984 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_5985 = and(_T_5983, _T_5984) @[ifu_mem_ctl.scala 694:124] + node _T_5986 = or(_T_5982, _T_5985) @[ifu_mem_ctl.scala 694:81] + node _T_5987 = or(_T_5986, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_5988 = bits(_T_5987, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_5989 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5988 : @[Reg.scala 28:19] _T_5989 <= _T_5979 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][23] <= _T_5989 @[ifu_mem_ctl.scala 685:41] - node _T_5990 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_5991 = eq(_T_5990, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_5992 = and(ic_valid_ff, _T_5991) @[ifu_mem_ctl.scala 685:97] - node _T_5993 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_5994 = and(_T_5992, _T_5993) @[ifu_mem_ctl.scala 685:122] - node _T_5995 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 686:37] - node _T_5996 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_5997 = and(_T_5995, _T_5996) @[ifu_mem_ctl.scala 686:59] - node _T_5998 = eq(perr_ic_index_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 686:102] - node _T_5999 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6000 = and(_T_5998, _T_5999) @[ifu_mem_ctl.scala 686:124] - node _T_6001 = or(_T_5997, _T_6000) @[ifu_mem_ctl.scala 686:81] - node _T_6002 = or(_T_6001, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6003 = bits(_T_6002, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][23] <= _T_5989 @[ifu_mem_ctl.scala 693:41] + node _T_5990 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_5991 = eq(_T_5990, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_5992 = and(ic_valid_ff, _T_5991) @[ifu_mem_ctl.scala 693:97] + node _T_5993 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_5994 = and(_T_5992, _T_5993) @[ifu_mem_ctl.scala 693:122] + node _T_5995 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 694:37] + node _T_5996 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_5997 = and(_T_5995, _T_5996) @[ifu_mem_ctl.scala 694:59] + node _T_5998 = eq(perr_ic_index_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 694:102] + node _T_5999 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6000 = and(_T_5998, _T_5999) @[ifu_mem_ctl.scala 694:124] + node _T_6001 = or(_T_5997, _T_6000) @[ifu_mem_ctl.scala 694:81] + node _T_6002 = or(_T_6001, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6003 = bits(_T_6002, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6004 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6003 : @[Reg.scala 28:19] _T_6004 <= _T_5994 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][24] <= _T_6004 @[ifu_mem_ctl.scala 685:41] - node _T_6005 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6006 = eq(_T_6005, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6007 = and(ic_valid_ff, _T_6006) @[ifu_mem_ctl.scala 685:97] - node _T_6008 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6009 = and(_T_6007, _T_6008) @[ifu_mem_ctl.scala 685:122] - node _T_6010 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 686:37] - node _T_6011 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6012 = and(_T_6010, _T_6011) @[ifu_mem_ctl.scala 686:59] - node _T_6013 = eq(perr_ic_index_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 686:102] - node _T_6014 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6015 = and(_T_6013, _T_6014) @[ifu_mem_ctl.scala 686:124] - node _T_6016 = or(_T_6012, _T_6015) @[ifu_mem_ctl.scala 686:81] - node _T_6017 = or(_T_6016, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6018 = bits(_T_6017, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][24] <= _T_6004 @[ifu_mem_ctl.scala 693:41] + node _T_6005 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6006 = eq(_T_6005, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6007 = and(ic_valid_ff, _T_6006) @[ifu_mem_ctl.scala 693:97] + node _T_6008 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6009 = and(_T_6007, _T_6008) @[ifu_mem_ctl.scala 693:122] + node _T_6010 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 694:37] + node _T_6011 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6012 = and(_T_6010, _T_6011) @[ifu_mem_ctl.scala 694:59] + node _T_6013 = eq(perr_ic_index_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 694:102] + node _T_6014 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6015 = and(_T_6013, _T_6014) @[ifu_mem_ctl.scala 694:124] + node _T_6016 = or(_T_6012, _T_6015) @[ifu_mem_ctl.scala 694:81] + node _T_6017 = or(_T_6016, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6018 = bits(_T_6017, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6019 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6018 : @[Reg.scala 28:19] _T_6019 <= _T_6009 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][25] <= _T_6019 @[ifu_mem_ctl.scala 685:41] - node _T_6020 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6021 = eq(_T_6020, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6022 = and(ic_valid_ff, _T_6021) @[ifu_mem_ctl.scala 685:97] - node _T_6023 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6024 = and(_T_6022, _T_6023) @[ifu_mem_ctl.scala 685:122] - node _T_6025 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 686:37] - node _T_6026 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6027 = and(_T_6025, _T_6026) @[ifu_mem_ctl.scala 686:59] - node _T_6028 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 686:102] - node _T_6029 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6030 = and(_T_6028, _T_6029) @[ifu_mem_ctl.scala 686:124] - node _T_6031 = or(_T_6027, _T_6030) @[ifu_mem_ctl.scala 686:81] - node _T_6032 = or(_T_6031, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6033 = bits(_T_6032, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][25] <= _T_6019 @[ifu_mem_ctl.scala 693:41] + node _T_6020 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6021 = eq(_T_6020, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6022 = and(ic_valid_ff, _T_6021) @[ifu_mem_ctl.scala 693:97] + node _T_6023 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6024 = and(_T_6022, _T_6023) @[ifu_mem_ctl.scala 693:122] + node _T_6025 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 694:37] + node _T_6026 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6027 = and(_T_6025, _T_6026) @[ifu_mem_ctl.scala 694:59] + node _T_6028 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 694:102] + node _T_6029 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6030 = and(_T_6028, _T_6029) @[ifu_mem_ctl.scala 694:124] + node _T_6031 = or(_T_6027, _T_6030) @[ifu_mem_ctl.scala 694:81] + node _T_6032 = or(_T_6031, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6033 = bits(_T_6032, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6034 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6033 : @[Reg.scala 28:19] _T_6034 <= _T_6024 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][26] <= _T_6034 @[ifu_mem_ctl.scala 685:41] - node _T_6035 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6036 = eq(_T_6035, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6037 = and(ic_valid_ff, _T_6036) @[ifu_mem_ctl.scala 685:97] - node _T_6038 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6039 = and(_T_6037, _T_6038) @[ifu_mem_ctl.scala 685:122] - node _T_6040 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 686:37] - node _T_6041 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6042 = and(_T_6040, _T_6041) @[ifu_mem_ctl.scala 686:59] - node _T_6043 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 686:102] - node _T_6044 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6045 = and(_T_6043, _T_6044) @[ifu_mem_ctl.scala 686:124] - node _T_6046 = or(_T_6042, _T_6045) @[ifu_mem_ctl.scala 686:81] - node _T_6047 = or(_T_6046, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6048 = bits(_T_6047, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][26] <= _T_6034 @[ifu_mem_ctl.scala 693:41] + node _T_6035 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6036 = eq(_T_6035, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6037 = and(ic_valid_ff, _T_6036) @[ifu_mem_ctl.scala 693:97] + node _T_6038 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6039 = and(_T_6037, _T_6038) @[ifu_mem_ctl.scala 693:122] + node _T_6040 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 694:37] + node _T_6041 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6042 = and(_T_6040, _T_6041) @[ifu_mem_ctl.scala 694:59] + node _T_6043 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 694:102] + node _T_6044 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6045 = and(_T_6043, _T_6044) @[ifu_mem_ctl.scala 694:124] + node _T_6046 = or(_T_6042, _T_6045) @[ifu_mem_ctl.scala 694:81] + node _T_6047 = or(_T_6046, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6048 = bits(_T_6047, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6049 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6048 : @[Reg.scala 28:19] _T_6049 <= _T_6039 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][27] <= _T_6049 @[ifu_mem_ctl.scala 685:41] - node _T_6050 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6051 = eq(_T_6050, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6052 = and(ic_valid_ff, _T_6051) @[ifu_mem_ctl.scala 685:97] - node _T_6053 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6054 = and(_T_6052, _T_6053) @[ifu_mem_ctl.scala 685:122] - node _T_6055 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 686:37] - node _T_6056 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6057 = and(_T_6055, _T_6056) @[ifu_mem_ctl.scala 686:59] - node _T_6058 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 686:102] - node _T_6059 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6060 = and(_T_6058, _T_6059) @[ifu_mem_ctl.scala 686:124] - node _T_6061 = or(_T_6057, _T_6060) @[ifu_mem_ctl.scala 686:81] - node _T_6062 = or(_T_6061, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6063 = bits(_T_6062, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][27] <= _T_6049 @[ifu_mem_ctl.scala 693:41] + node _T_6050 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6051 = eq(_T_6050, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6052 = and(ic_valid_ff, _T_6051) @[ifu_mem_ctl.scala 693:97] + node _T_6053 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6054 = and(_T_6052, _T_6053) @[ifu_mem_ctl.scala 693:122] + node _T_6055 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 694:37] + node _T_6056 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6057 = and(_T_6055, _T_6056) @[ifu_mem_ctl.scala 694:59] + node _T_6058 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 694:102] + node _T_6059 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6060 = and(_T_6058, _T_6059) @[ifu_mem_ctl.scala 694:124] + node _T_6061 = or(_T_6057, _T_6060) @[ifu_mem_ctl.scala 694:81] + node _T_6062 = or(_T_6061, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6063 = bits(_T_6062, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6064 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6063 : @[Reg.scala 28:19] _T_6064 <= _T_6054 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][28] <= _T_6064 @[ifu_mem_ctl.scala 685:41] - node _T_6065 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6066 = eq(_T_6065, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6067 = and(ic_valid_ff, _T_6066) @[ifu_mem_ctl.scala 685:97] - node _T_6068 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6069 = and(_T_6067, _T_6068) @[ifu_mem_ctl.scala 685:122] - node _T_6070 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 686:37] - node _T_6071 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6072 = and(_T_6070, _T_6071) @[ifu_mem_ctl.scala 686:59] - node _T_6073 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 686:102] - node _T_6074 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6075 = and(_T_6073, _T_6074) @[ifu_mem_ctl.scala 686:124] - node _T_6076 = or(_T_6072, _T_6075) @[ifu_mem_ctl.scala 686:81] - node _T_6077 = or(_T_6076, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6078 = bits(_T_6077, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][28] <= _T_6064 @[ifu_mem_ctl.scala 693:41] + node _T_6065 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6066 = eq(_T_6065, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6067 = and(ic_valid_ff, _T_6066) @[ifu_mem_ctl.scala 693:97] + node _T_6068 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6069 = and(_T_6067, _T_6068) @[ifu_mem_ctl.scala 693:122] + node _T_6070 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 694:37] + node _T_6071 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6072 = and(_T_6070, _T_6071) @[ifu_mem_ctl.scala 694:59] + node _T_6073 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 694:102] + node _T_6074 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6075 = and(_T_6073, _T_6074) @[ifu_mem_ctl.scala 694:124] + node _T_6076 = or(_T_6072, _T_6075) @[ifu_mem_ctl.scala 694:81] + node _T_6077 = or(_T_6076, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6078 = bits(_T_6077, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6079 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6078 : @[Reg.scala 28:19] _T_6079 <= _T_6069 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][29] <= _T_6079 @[ifu_mem_ctl.scala 685:41] - node _T_6080 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6081 = eq(_T_6080, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6082 = and(ic_valid_ff, _T_6081) @[ifu_mem_ctl.scala 685:97] - node _T_6083 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6084 = and(_T_6082, _T_6083) @[ifu_mem_ctl.scala 685:122] - node _T_6085 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 686:37] - node _T_6086 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6087 = and(_T_6085, _T_6086) @[ifu_mem_ctl.scala 686:59] - node _T_6088 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 686:102] - node _T_6089 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6090 = and(_T_6088, _T_6089) @[ifu_mem_ctl.scala 686:124] - node _T_6091 = or(_T_6087, _T_6090) @[ifu_mem_ctl.scala 686:81] - node _T_6092 = or(_T_6091, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6093 = bits(_T_6092, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][29] <= _T_6079 @[ifu_mem_ctl.scala 693:41] + node _T_6080 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6081 = eq(_T_6080, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6082 = and(ic_valid_ff, _T_6081) @[ifu_mem_ctl.scala 693:97] + node _T_6083 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6084 = and(_T_6082, _T_6083) @[ifu_mem_ctl.scala 693:122] + node _T_6085 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 694:37] + node _T_6086 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6087 = and(_T_6085, _T_6086) @[ifu_mem_ctl.scala 694:59] + node _T_6088 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 694:102] + node _T_6089 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6090 = and(_T_6088, _T_6089) @[ifu_mem_ctl.scala 694:124] + node _T_6091 = or(_T_6087, _T_6090) @[ifu_mem_ctl.scala 694:81] + node _T_6092 = or(_T_6091, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6093 = bits(_T_6092, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6094 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6093 : @[Reg.scala 28:19] _T_6094 <= _T_6084 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][30] <= _T_6094 @[ifu_mem_ctl.scala 685:41] - node _T_6095 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6096 = eq(_T_6095, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6097 = and(ic_valid_ff, _T_6096) @[ifu_mem_ctl.scala 685:97] - node _T_6098 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6099 = and(_T_6097, _T_6098) @[ifu_mem_ctl.scala 685:122] - node _T_6100 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 686:37] - node _T_6101 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6102 = and(_T_6100, _T_6101) @[ifu_mem_ctl.scala 686:59] - node _T_6103 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 686:102] - node _T_6104 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6105 = and(_T_6103, _T_6104) @[ifu_mem_ctl.scala 686:124] - node _T_6106 = or(_T_6102, _T_6105) @[ifu_mem_ctl.scala 686:81] - node _T_6107 = or(_T_6106, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6108 = bits(_T_6107, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][30] <= _T_6094 @[ifu_mem_ctl.scala 693:41] + node _T_6095 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6096 = eq(_T_6095, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6097 = and(ic_valid_ff, _T_6096) @[ifu_mem_ctl.scala 693:97] + node _T_6098 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6099 = and(_T_6097, _T_6098) @[ifu_mem_ctl.scala 693:122] + node _T_6100 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 694:37] + node _T_6101 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6102 = and(_T_6100, _T_6101) @[ifu_mem_ctl.scala 694:59] + node _T_6103 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 694:102] + node _T_6104 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6105 = and(_T_6103, _T_6104) @[ifu_mem_ctl.scala 694:124] + node _T_6106 = or(_T_6102, _T_6105) @[ifu_mem_ctl.scala 694:81] + node _T_6107 = or(_T_6106, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6108 = bits(_T_6107, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6109 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6108 : @[Reg.scala 28:19] _T_6109 <= _T_6099 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][31] <= _T_6109 @[ifu_mem_ctl.scala 685:41] - node _T_6110 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6111 = eq(_T_6110, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6112 = and(ic_valid_ff, _T_6111) @[ifu_mem_ctl.scala 685:97] - node _T_6113 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6114 = and(_T_6112, _T_6113) @[ifu_mem_ctl.scala 685:122] - node _T_6115 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 686:37] - node _T_6116 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6117 = and(_T_6115, _T_6116) @[ifu_mem_ctl.scala 686:59] - node _T_6118 = eq(perr_ic_index_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 686:102] - node _T_6119 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6120 = and(_T_6118, _T_6119) @[ifu_mem_ctl.scala 686:124] - node _T_6121 = or(_T_6117, _T_6120) @[ifu_mem_ctl.scala 686:81] - node _T_6122 = or(_T_6121, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6123 = bits(_T_6122, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][31] <= _T_6109 @[ifu_mem_ctl.scala 693:41] + node _T_6110 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6111 = eq(_T_6110, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6112 = and(ic_valid_ff, _T_6111) @[ifu_mem_ctl.scala 693:97] + node _T_6113 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6114 = and(_T_6112, _T_6113) @[ifu_mem_ctl.scala 693:122] + node _T_6115 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 694:37] + node _T_6116 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6117 = and(_T_6115, _T_6116) @[ifu_mem_ctl.scala 694:59] + node _T_6118 = eq(perr_ic_index_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 694:102] + node _T_6119 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6120 = and(_T_6118, _T_6119) @[ifu_mem_ctl.scala 694:124] + node _T_6121 = or(_T_6117, _T_6120) @[ifu_mem_ctl.scala 694:81] + node _T_6122 = or(_T_6121, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6123 = bits(_T_6122, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6124 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6123 : @[Reg.scala 28:19] _T_6124 <= _T_6114 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][32] <= _T_6124 @[ifu_mem_ctl.scala 685:41] - node _T_6125 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6126 = eq(_T_6125, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6127 = and(ic_valid_ff, _T_6126) @[ifu_mem_ctl.scala 685:97] - node _T_6128 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6129 = and(_T_6127, _T_6128) @[ifu_mem_ctl.scala 685:122] - node _T_6130 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 686:37] - node _T_6131 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6132 = and(_T_6130, _T_6131) @[ifu_mem_ctl.scala 686:59] - node _T_6133 = eq(perr_ic_index_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 686:102] - node _T_6134 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6135 = and(_T_6133, _T_6134) @[ifu_mem_ctl.scala 686:124] - node _T_6136 = or(_T_6132, _T_6135) @[ifu_mem_ctl.scala 686:81] - node _T_6137 = or(_T_6136, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6138 = bits(_T_6137, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][32] <= _T_6124 @[ifu_mem_ctl.scala 693:41] + node _T_6125 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6126 = eq(_T_6125, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6127 = and(ic_valid_ff, _T_6126) @[ifu_mem_ctl.scala 693:97] + node _T_6128 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6129 = and(_T_6127, _T_6128) @[ifu_mem_ctl.scala 693:122] + node _T_6130 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 694:37] + node _T_6131 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6132 = and(_T_6130, _T_6131) @[ifu_mem_ctl.scala 694:59] + node _T_6133 = eq(perr_ic_index_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 694:102] + node _T_6134 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6135 = and(_T_6133, _T_6134) @[ifu_mem_ctl.scala 694:124] + node _T_6136 = or(_T_6132, _T_6135) @[ifu_mem_ctl.scala 694:81] + node _T_6137 = or(_T_6136, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6138 = bits(_T_6137, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6139 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6138 : @[Reg.scala 28:19] _T_6139 <= _T_6129 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][33] <= _T_6139 @[ifu_mem_ctl.scala 685:41] - node _T_6140 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6141 = eq(_T_6140, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6142 = and(ic_valid_ff, _T_6141) @[ifu_mem_ctl.scala 685:97] - node _T_6143 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6144 = and(_T_6142, _T_6143) @[ifu_mem_ctl.scala 685:122] - node _T_6145 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 686:37] - node _T_6146 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6147 = and(_T_6145, _T_6146) @[ifu_mem_ctl.scala 686:59] - node _T_6148 = eq(perr_ic_index_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 686:102] - node _T_6149 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6150 = and(_T_6148, _T_6149) @[ifu_mem_ctl.scala 686:124] - node _T_6151 = or(_T_6147, _T_6150) @[ifu_mem_ctl.scala 686:81] - node _T_6152 = or(_T_6151, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6153 = bits(_T_6152, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][33] <= _T_6139 @[ifu_mem_ctl.scala 693:41] + node _T_6140 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6141 = eq(_T_6140, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6142 = and(ic_valid_ff, _T_6141) @[ifu_mem_ctl.scala 693:97] + node _T_6143 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6144 = and(_T_6142, _T_6143) @[ifu_mem_ctl.scala 693:122] + node _T_6145 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 694:37] + node _T_6146 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6147 = and(_T_6145, _T_6146) @[ifu_mem_ctl.scala 694:59] + node _T_6148 = eq(perr_ic_index_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 694:102] + node _T_6149 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6150 = and(_T_6148, _T_6149) @[ifu_mem_ctl.scala 694:124] + node _T_6151 = or(_T_6147, _T_6150) @[ifu_mem_ctl.scala 694:81] + node _T_6152 = or(_T_6151, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6153 = bits(_T_6152, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6154 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6153 : @[Reg.scala 28:19] _T_6154 <= _T_6144 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][34] <= _T_6154 @[ifu_mem_ctl.scala 685:41] - node _T_6155 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6156 = eq(_T_6155, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6157 = and(ic_valid_ff, _T_6156) @[ifu_mem_ctl.scala 685:97] - node _T_6158 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6159 = and(_T_6157, _T_6158) @[ifu_mem_ctl.scala 685:122] - node _T_6160 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 686:37] - node _T_6161 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6162 = and(_T_6160, _T_6161) @[ifu_mem_ctl.scala 686:59] - node _T_6163 = eq(perr_ic_index_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 686:102] - node _T_6164 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6165 = and(_T_6163, _T_6164) @[ifu_mem_ctl.scala 686:124] - node _T_6166 = or(_T_6162, _T_6165) @[ifu_mem_ctl.scala 686:81] - node _T_6167 = or(_T_6166, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6168 = bits(_T_6167, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][34] <= _T_6154 @[ifu_mem_ctl.scala 693:41] + node _T_6155 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6156 = eq(_T_6155, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6157 = and(ic_valid_ff, _T_6156) @[ifu_mem_ctl.scala 693:97] + node _T_6158 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6159 = and(_T_6157, _T_6158) @[ifu_mem_ctl.scala 693:122] + node _T_6160 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 694:37] + node _T_6161 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6162 = and(_T_6160, _T_6161) @[ifu_mem_ctl.scala 694:59] + node _T_6163 = eq(perr_ic_index_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 694:102] + node _T_6164 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6165 = and(_T_6163, _T_6164) @[ifu_mem_ctl.scala 694:124] + node _T_6166 = or(_T_6162, _T_6165) @[ifu_mem_ctl.scala 694:81] + node _T_6167 = or(_T_6166, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6168 = bits(_T_6167, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6169 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6168 : @[Reg.scala 28:19] _T_6169 <= _T_6159 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][35] <= _T_6169 @[ifu_mem_ctl.scala 685:41] - node _T_6170 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6171 = eq(_T_6170, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6172 = and(ic_valid_ff, _T_6171) @[ifu_mem_ctl.scala 685:97] - node _T_6173 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6174 = and(_T_6172, _T_6173) @[ifu_mem_ctl.scala 685:122] - node _T_6175 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 686:37] - node _T_6176 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6177 = and(_T_6175, _T_6176) @[ifu_mem_ctl.scala 686:59] - node _T_6178 = eq(perr_ic_index_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 686:102] - node _T_6179 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6180 = and(_T_6178, _T_6179) @[ifu_mem_ctl.scala 686:124] - node _T_6181 = or(_T_6177, _T_6180) @[ifu_mem_ctl.scala 686:81] - node _T_6182 = or(_T_6181, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6183 = bits(_T_6182, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][35] <= _T_6169 @[ifu_mem_ctl.scala 693:41] + node _T_6170 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6171 = eq(_T_6170, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6172 = and(ic_valid_ff, _T_6171) @[ifu_mem_ctl.scala 693:97] + node _T_6173 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6174 = and(_T_6172, _T_6173) @[ifu_mem_ctl.scala 693:122] + node _T_6175 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 694:37] + node _T_6176 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6177 = and(_T_6175, _T_6176) @[ifu_mem_ctl.scala 694:59] + node _T_6178 = eq(perr_ic_index_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 694:102] + node _T_6179 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6180 = and(_T_6178, _T_6179) @[ifu_mem_ctl.scala 694:124] + node _T_6181 = or(_T_6177, _T_6180) @[ifu_mem_ctl.scala 694:81] + node _T_6182 = or(_T_6181, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6183 = bits(_T_6182, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6184 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6183 : @[Reg.scala 28:19] _T_6184 <= _T_6174 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][36] <= _T_6184 @[ifu_mem_ctl.scala 685:41] - node _T_6185 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6186 = eq(_T_6185, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6187 = and(ic_valid_ff, _T_6186) @[ifu_mem_ctl.scala 685:97] - node _T_6188 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6189 = and(_T_6187, _T_6188) @[ifu_mem_ctl.scala 685:122] - node _T_6190 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 686:37] - node _T_6191 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6192 = and(_T_6190, _T_6191) @[ifu_mem_ctl.scala 686:59] - node _T_6193 = eq(perr_ic_index_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 686:102] - node _T_6194 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6195 = and(_T_6193, _T_6194) @[ifu_mem_ctl.scala 686:124] - node _T_6196 = or(_T_6192, _T_6195) @[ifu_mem_ctl.scala 686:81] - node _T_6197 = or(_T_6196, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6198 = bits(_T_6197, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][36] <= _T_6184 @[ifu_mem_ctl.scala 693:41] + node _T_6185 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6186 = eq(_T_6185, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6187 = and(ic_valid_ff, _T_6186) @[ifu_mem_ctl.scala 693:97] + node _T_6188 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6189 = and(_T_6187, _T_6188) @[ifu_mem_ctl.scala 693:122] + node _T_6190 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 694:37] + node _T_6191 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6192 = and(_T_6190, _T_6191) @[ifu_mem_ctl.scala 694:59] + node _T_6193 = eq(perr_ic_index_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 694:102] + node _T_6194 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6195 = and(_T_6193, _T_6194) @[ifu_mem_ctl.scala 694:124] + node _T_6196 = or(_T_6192, _T_6195) @[ifu_mem_ctl.scala 694:81] + node _T_6197 = or(_T_6196, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6198 = bits(_T_6197, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6199 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6198 : @[Reg.scala 28:19] _T_6199 <= _T_6189 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][37] <= _T_6199 @[ifu_mem_ctl.scala 685:41] - node _T_6200 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6201 = eq(_T_6200, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6202 = and(ic_valid_ff, _T_6201) @[ifu_mem_ctl.scala 685:97] - node _T_6203 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6204 = and(_T_6202, _T_6203) @[ifu_mem_ctl.scala 685:122] - node _T_6205 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 686:37] - node _T_6206 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6207 = and(_T_6205, _T_6206) @[ifu_mem_ctl.scala 686:59] - node _T_6208 = eq(perr_ic_index_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 686:102] - node _T_6209 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6210 = and(_T_6208, _T_6209) @[ifu_mem_ctl.scala 686:124] - node _T_6211 = or(_T_6207, _T_6210) @[ifu_mem_ctl.scala 686:81] - node _T_6212 = or(_T_6211, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6213 = bits(_T_6212, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][37] <= _T_6199 @[ifu_mem_ctl.scala 693:41] + node _T_6200 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6201 = eq(_T_6200, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6202 = and(ic_valid_ff, _T_6201) @[ifu_mem_ctl.scala 693:97] + node _T_6203 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6204 = and(_T_6202, _T_6203) @[ifu_mem_ctl.scala 693:122] + node _T_6205 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 694:37] + node _T_6206 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6207 = and(_T_6205, _T_6206) @[ifu_mem_ctl.scala 694:59] + node _T_6208 = eq(perr_ic_index_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 694:102] + node _T_6209 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6210 = and(_T_6208, _T_6209) @[ifu_mem_ctl.scala 694:124] + node _T_6211 = or(_T_6207, _T_6210) @[ifu_mem_ctl.scala 694:81] + node _T_6212 = or(_T_6211, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6213 = bits(_T_6212, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6214 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6213 : @[Reg.scala 28:19] _T_6214 <= _T_6204 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][38] <= _T_6214 @[ifu_mem_ctl.scala 685:41] - node _T_6215 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6216 = eq(_T_6215, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6217 = and(ic_valid_ff, _T_6216) @[ifu_mem_ctl.scala 685:97] - node _T_6218 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6219 = and(_T_6217, _T_6218) @[ifu_mem_ctl.scala 685:122] - node _T_6220 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 686:37] - node _T_6221 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6222 = and(_T_6220, _T_6221) @[ifu_mem_ctl.scala 686:59] - node _T_6223 = eq(perr_ic_index_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 686:102] - node _T_6224 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6225 = and(_T_6223, _T_6224) @[ifu_mem_ctl.scala 686:124] - node _T_6226 = or(_T_6222, _T_6225) @[ifu_mem_ctl.scala 686:81] - node _T_6227 = or(_T_6226, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6228 = bits(_T_6227, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][38] <= _T_6214 @[ifu_mem_ctl.scala 693:41] + node _T_6215 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6216 = eq(_T_6215, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6217 = and(ic_valid_ff, _T_6216) @[ifu_mem_ctl.scala 693:97] + node _T_6218 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6219 = and(_T_6217, _T_6218) @[ifu_mem_ctl.scala 693:122] + node _T_6220 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 694:37] + node _T_6221 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6222 = and(_T_6220, _T_6221) @[ifu_mem_ctl.scala 694:59] + node _T_6223 = eq(perr_ic_index_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 694:102] + node _T_6224 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6225 = and(_T_6223, _T_6224) @[ifu_mem_ctl.scala 694:124] + node _T_6226 = or(_T_6222, _T_6225) @[ifu_mem_ctl.scala 694:81] + node _T_6227 = or(_T_6226, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6228 = bits(_T_6227, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6229 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6228 : @[Reg.scala 28:19] _T_6229 <= _T_6219 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][39] <= _T_6229 @[ifu_mem_ctl.scala 685:41] - node _T_6230 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6231 = eq(_T_6230, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6232 = and(ic_valid_ff, _T_6231) @[ifu_mem_ctl.scala 685:97] - node _T_6233 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6234 = and(_T_6232, _T_6233) @[ifu_mem_ctl.scala 685:122] - node _T_6235 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 686:37] - node _T_6236 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6237 = and(_T_6235, _T_6236) @[ifu_mem_ctl.scala 686:59] - node _T_6238 = eq(perr_ic_index_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 686:102] - node _T_6239 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6240 = and(_T_6238, _T_6239) @[ifu_mem_ctl.scala 686:124] - node _T_6241 = or(_T_6237, _T_6240) @[ifu_mem_ctl.scala 686:81] - node _T_6242 = or(_T_6241, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6243 = bits(_T_6242, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][39] <= _T_6229 @[ifu_mem_ctl.scala 693:41] + node _T_6230 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6231 = eq(_T_6230, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6232 = and(ic_valid_ff, _T_6231) @[ifu_mem_ctl.scala 693:97] + node _T_6233 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6234 = and(_T_6232, _T_6233) @[ifu_mem_ctl.scala 693:122] + node _T_6235 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 694:37] + node _T_6236 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6237 = and(_T_6235, _T_6236) @[ifu_mem_ctl.scala 694:59] + node _T_6238 = eq(perr_ic_index_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 694:102] + node _T_6239 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6240 = and(_T_6238, _T_6239) @[ifu_mem_ctl.scala 694:124] + node _T_6241 = or(_T_6237, _T_6240) @[ifu_mem_ctl.scala 694:81] + node _T_6242 = or(_T_6241, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6243 = bits(_T_6242, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6244 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6243 : @[Reg.scala 28:19] _T_6244 <= _T_6234 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][40] <= _T_6244 @[ifu_mem_ctl.scala 685:41] - node _T_6245 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6246 = eq(_T_6245, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6247 = and(ic_valid_ff, _T_6246) @[ifu_mem_ctl.scala 685:97] - node _T_6248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6249 = and(_T_6247, _T_6248) @[ifu_mem_ctl.scala 685:122] - node _T_6250 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 686:37] - node _T_6251 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6252 = and(_T_6250, _T_6251) @[ifu_mem_ctl.scala 686:59] - node _T_6253 = eq(perr_ic_index_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 686:102] - node _T_6254 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6255 = and(_T_6253, _T_6254) @[ifu_mem_ctl.scala 686:124] - node _T_6256 = or(_T_6252, _T_6255) @[ifu_mem_ctl.scala 686:81] - node _T_6257 = or(_T_6256, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6258 = bits(_T_6257, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][40] <= _T_6244 @[ifu_mem_ctl.scala 693:41] + node _T_6245 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6246 = eq(_T_6245, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6247 = and(ic_valid_ff, _T_6246) @[ifu_mem_ctl.scala 693:97] + node _T_6248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6249 = and(_T_6247, _T_6248) @[ifu_mem_ctl.scala 693:122] + node _T_6250 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 694:37] + node _T_6251 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6252 = and(_T_6250, _T_6251) @[ifu_mem_ctl.scala 694:59] + node _T_6253 = eq(perr_ic_index_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 694:102] + node _T_6254 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6255 = and(_T_6253, _T_6254) @[ifu_mem_ctl.scala 694:124] + node _T_6256 = or(_T_6252, _T_6255) @[ifu_mem_ctl.scala 694:81] + node _T_6257 = or(_T_6256, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6258 = bits(_T_6257, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6259 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6258 : @[Reg.scala 28:19] _T_6259 <= _T_6249 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][41] <= _T_6259 @[ifu_mem_ctl.scala 685:41] - node _T_6260 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6261 = eq(_T_6260, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6262 = and(ic_valid_ff, _T_6261) @[ifu_mem_ctl.scala 685:97] - node _T_6263 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6264 = and(_T_6262, _T_6263) @[ifu_mem_ctl.scala 685:122] - node _T_6265 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 686:37] - node _T_6266 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6267 = and(_T_6265, _T_6266) @[ifu_mem_ctl.scala 686:59] - node _T_6268 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 686:102] - node _T_6269 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6270 = and(_T_6268, _T_6269) @[ifu_mem_ctl.scala 686:124] - node _T_6271 = or(_T_6267, _T_6270) @[ifu_mem_ctl.scala 686:81] - node _T_6272 = or(_T_6271, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6273 = bits(_T_6272, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][41] <= _T_6259 @[ifu_mem_ctl.scala 693:41] + node _T_6260 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6261 = eq(_T_6260, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6262 = and(ic_valid_ff, _T_6261) @[ifu_mem_ctl.scala 693:97] + node _T_6263 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6264 = and(_T_6262, _T_6263) @[ifu_mem_ctl.scala 693:122] + node _T_6265 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 694:37] + node _T_6266 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6267 = and(_T_6265, _T_6266) @[ifu_mem_ctl.scala 694:59] + node _T_6268 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 694:102] + node _T_6269 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6270 = and(_T_6268, _T_6269) @[ifu_mem_ctl.scala 694:124] + node _T_6271 = or(_T_6267, _T_6270) @[ifu_mem_ctl.scala 694:81] + node _T_6272 = or(_T_6271, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6273 = bits(_T_6272, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6274 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6273 : @[Reg.scala 28:19] _T_6274 <= _T_6264 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][42] <= _T_6274 @[ifu_mem_ctl.scala 685:41] - node _T_6275 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6276 = eq(_T_6275, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6277 = and(ic_valid_ff, _T_6276) @[ifu_mem_ctl.scala 685:97] - node _T_6278 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6279 = and(_T_6277, _T_6278) @[ifu_mem_ctl.scala 685:122] - node _T_6280 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 686:37] - node _T_6281 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6282 = and(_T_6280, _T_6281) @[ifu_mem_ctl.scala 686:59] - node _T_6283 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 686:102] - node _T_6284 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6285 = and(_T_6283, _T_6284) @[ifu_mem_ctl.scala 686:124] - node _T_6286 = or(_T_6282, _T_6285) @[ifu_mem_ctl.scala 686:81] - node _T_6287 = or(_T_6286, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6288 = bits(_T_6287, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][42] <= _T_6274 @[ifu_mem_ctl.scala 693:41] + node _T_6275 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6276 = eq(_T_6275, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6277 = and(ic_valid_ff, _T_6276) @[ifu_mem_ctl.scala 693:97] + node _T_6278 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6279 = and(_T_6277, _T_6278) @[ifu_mem_ctl.scala 693:122] + node _T_6280 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 694:37] + node _T_6281 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6282 = and(_T_6280, _T_6281) @[ifu_mem_ctl.scala 694:59] + node _T_6283 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 694:102] + node _T_6284 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6285 = and(_T_6283, _T_6284) @[ifu_mem_ctl.scala 694:124] + node _T_6286 = or(_T_6282, _T_6285) @[ifu_mem_ctl.scala 694:81] + node _T_6287 = or(_T_6286, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6288 = bits(_T_6287, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6289 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6288 : @[Reg.scala 28:19] _T_6289 <= _T_6279 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][43] <= _T_6289 @[ifu_mem_ctl.scala 685:41] - node _T_6290 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6291 = eq(_T_6290, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6292 = and(ic_valid_ff, _T_6291) @[ifu_mem_ctl.scala 685:97] - node _T_6293 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6294 = and(_T_6292, _T_6293) @[ifu_mem_ctl.scala 685:122] - node _T_6295 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 686:37] - node _T_6296 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6297 = and(_T_6295, _T_6296) @[ifu_mem_ctl.scala 686:59] - node _T_6298 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 686:102] - node _T_6299 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6300 = and(_T_6298, _T_6299) @[ifu_mem_ctl.scala 686:124] - node _T_6301 = or(_T_6297, _T_6300) @[ifu_mem_ctl.scala 686:81] - node _T_6302 = or(_T_6301, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6303 = bits(_T_6302, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][43] <= _T_6289 @[ifu_mem_ctl.scala 693:41] + node _T_6290 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6291 = eq(_T_6290, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6292 = and(ic_valid_ff, _T_6291) @[ifu_mem_ctl.scala 693:97] + node _T_6293 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6294 = and(_T_6292, _T_6293) @[ifu_mem_ctl.scala 693:122] + node _T_6295 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 694:37] + node _T_6296 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6297 = and(_T_6295, _T_6296) @[ifu_mem_ctl.scala 694:59] + node _T_6298 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 694:102] + node _T_6299 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6300 = and(_T_6298, _T_6299) @[ifu_mem_ctl.scala 694:124] + node _T_6301 = or(_T_6297, _T_6300) @[ifu_mem_ctl.scala 694:81] + node _T_6302 = or(_T_6301, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6303 = bits(_T_6302, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6304 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6303 : @[Reg.scala 28:19] _T_6304 <= _T_6294 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][44] <= _T_6304 @[ifu_mem_ctl.scala 685:41] - node _T_6305 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6306 = eq(_T_6305, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6307 = and(ic_valid_ff, _T_6306) @[ifu_mem_ctl.scala 685:97] - node _T_6308 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6309 = and(_T_6307, _T_6308) @[ifu_mem_ctl.scala 685:122] - node _T_6310 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 686:37] - node _T_6311 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6312 = and(_T_6310, _T_6311) @[ifu_mem_ctl.scala 686:59] - node _T_6313 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 686:102] - node _T_6314 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6315 = and(_T_6313, _T_6314) @[ifu_mem_ctl.scala 686:124] - node _T_6316 = or(_T_6312, _T_6315) @[ifu_mem_ctl.scala 686:81] - node _T_6317 = or(_T_6316, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6318 = bits(_T_6317, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][44] <= _T_6304 @[ifu_mem_ctl.scala 693:41] + node _T_6305 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6306 = eq(_T_6305, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6307 = and(ic_valid_ff, _T_6306) @[ifu_mem_ctl.scala 693:97] + node _T_6308 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6309 = and(_T_6307, _T_6308) @[ifu_mem_ctl.scala 693:122] + node _T_6310 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 694:37] + node _T_6311 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6312 = and(_T_6310, _T_6311) @[ifu_mem_ctl.scala 694:59] + node _T_6313 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 694:102] + node _T_6314 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6315 = and(_T_6313, _T_6314) @[ifu_mem_ctl.scala 694:124] + node _T_6316 = or(_T_6312, _T_6315) @[ifu_mem_ctl.scala 694:81] + node _T_6317 = or(_T_6316, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6318 = bits(_T_6317, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6319 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6318 : @[Reg.scala 28:19] _T_6319 <= _T_6309 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][45] <= _T_6319 @[ifu_mem_ctl.scala 685:41] - node _T_6320 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6321 = eq(_T_6320, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6322 = and(ic_valid_ff, _T_6321) @[ifu_mem_ctl.scala 685:97] - node _T_6323 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6324 = and(_T_6322, _T_6323) @[ifu_mem_ctl.scala 685:122] - node _T_6325 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 686:37] - node _T_6326 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6327 = and(_T_6325, _T_6326) @[ifu_mem_ctl.scala 686:59] - node _T_6328 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 686:102] - node _T_6329 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6330 = and(_T_6328, _T_6329) @[ifu_mem_ctl.scala 686:124] - node _T_6331 = or(_T_6327, _T_6330) @[ifu_mem_ctl.scala 686:81] - node _T_6332 = or(_T_6331, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6333 = bits(_T_6332, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][45] <= _T_6319 @[ifu_mem_ctl.scala 693:41] + node _T_6320 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6321 = eq(_T_6320, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6322 = and(ic_valid_ff, _T_6321) @[ifu_mem_ctl.scala 693:97] + node _T_6323 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6324 = and(_T_6322, _T_6323) @[ifu_mem_ctl.scala 693:122] + node _T_6325 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 694:37] + node _T_6326 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6327 = and(_T_6325, _T_6326) @[ifu_mem_ctl.scala 694:59] + node _T_6328 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 694:102] + node _T_6329 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6330 = and(_T_6328, _T_6329) @[ifu_mem_ctl.scala 694:124] + node _T_6331 = or(_T_6327, _T_6330) @[ifu_mem_ctl.scala 694:81] + node _T_6332 = or(_T_6331, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6333 = bits(_T_6332, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6334 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6333 : @[Reg.scala 28:19] _T_6334 <= _T_6324 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][46] <= _T_6334 @[ifu_mem_ctl.scala 685:41] - node _T_6335 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6336 = eq(_T_6335, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6337 = and(ic_valid_ff, _T_6336) @[ifu_mem_ctl.scala 685:97] - node _T_6338 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6339 = and(_T_6337, _T_6338) @[ifu_mem_ctl.scala 685:122] - node _T_6340 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 686:37] - node _T_6341 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6342 = and(_T_6340, _T_6341) @[ifu_mem_ctl.scala 686:59] - node _T_6343 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 686:102] - node _T_6344 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6345 = and(_T_6343, _T_6344) @[ifu_mem_ctl.scala 686:124] - node _T_6346 = or(_T_6342, _T_6345) @[ifu_mem_ctl.scala 686:81] - node _T_6347 = or(_T_6346, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6348 = bits(_T_6347, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][46] <= _T_6334 @[ifu_mem_ctl.scala 693:41] + node _T_6335 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6336 = eq(_T_6335, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6337 = and(ic_valid_ff, _T_6336) @[ifu_mem_ctl.scala 693:97] + node _T_6338 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6339 = and(_T_6337, _T_6338) @[ifu_mem_ctl.scala 693:122] + node _T_6340 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 694:37] + node _T_6341 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6342 = and(_T_6340, _T_6341) @[ifu_mem_ctl.scala 694:59] + node _T_6343 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 694:102] + node _T_6344 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6345 = and(_T_6343, _T_6344) @[ifu_mem_ctl.scala 694:124] + node _T_6346 = or(_T_6342, _T_6345) @[ifu_mem_ctl.scala 694:81] + node _T_6347 = or(_T_6346, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6348 = bits(_T_6347, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6349 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6348 : @[Reg.scala 28:19] _T_6349 <= _T_6339 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][47] <= _T_6349 @[ifu_mem_ctl.scala 685:41] - node _T_6350 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6351 = eq(_T_6350, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6352 = and(ic_valid_ff, _T_6351) @[ifu_mem_ctl.scala 685:97] - node _T_6353 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6354 = and(_T_6352, _T_6353) @[ifu_mem_ctl.scala 685:122] - node _T_6355 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 686:37] - node _T_6356 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6357 = and(_T_6355, _T_6356) @[ifu_mem_ctl.scala 686:59] - node _T_6358 = eq(perr_ic_index_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 686:102] - node _T_6359 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6360 = and(_T_6358, _T_6359) @[ifu_mem_ctl.scala 686:124] - node _T_6361 = or(_T_6357, _T_6360) @[ifu_mem_ctl.scala 686:81] - node _T_6362 = or(_T_6361, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6363 = bits(_T_6362, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][47] <= _T_6349 @[ifu_mem_ctl.scala 693:41] + node _T_6350 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6351 = eq(_T_6350, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6352 = and(ic_valid_ff, _T_6351) @[ifu_mem_ctl.scala 693:97] + node _T_6353 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6354 = and(_T_6352, _T_6353) @[ifu_mem_ctl.scala 693:122] + node _T_6355 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 694:37] + node _T_6356 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6357 = and(_T_6355, _T_6356) @[ifu_mem_ctl.scala 694:59] + node _T_6358 = eq(perr_ic_index_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 694:102] + node _T_6359 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6360 = and(_T_6358, _T_6359) @[ifu_mem_ctl.scala 694:124] + node _T_6361 = or(_T_6357, _T_6360) @[ifu_mem_ctl.scala 694:81] + node _T_6362 = or(_T_6361, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6363 = bits(_T_6362, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6364 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6363 : @[Reg.scala 28:19] _T_6364 <= _T_6354 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][48] <= _T_6364 @[ifu_mem_ctl.scala 685:41] - node _T_6365 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6366 = eq(_T_6365, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6367 = and(ic_valid_ff, _T_6366) @[ifu_mem_ctl.scala 685:97] - node _T_6368 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6369 = and(_T_6367, _T_6368) @[ifu_mem_ctl.scala 685:122] - node _T_6370 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 686:37] - node _T_6371 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6372 = and(_T_6370, _T_6371) @[ifu_mem_ctl.scala 686:59] - node _T_6373 = eq(perr_ic_index_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 686:102] - node _T_6374 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6375 = and(_T_6373, _T_6374) @[ifu_mem_ctl.scala 686:124] - node _T_6376 = or(_T_6372, _T_6375) @[ifu_mem_ctl.scala 686:81] - node _T_6377 = or(_T_6376, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6378 = bits(_T_6377, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][48] <= _T_6364 @[ifu_mem_ctl.scala 693:41] + node _T_6365 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6366 = eq(_T_6365, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6367 = and(ic_valid_ff, _T_6366) @[ifu_mem_ctl.scala 693:97] + node _T_6368 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6369 = and(_T_6367, _T_6368) @[ifu_mem_ctl.scala 693:122] + node _T_6370 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 694:37] + node _T_6371 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6372 = and(_T_6370, _T_6371) @[ifu_mem_ctl.scala 694:59] + node _T_6373 = eq(perr_ic_index_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 694:102] + node _T_6374 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6375 = and(_T_6373, _T_6374) @[ifu_mem_ctl.scala 694:124] + node _T_6376 = or(_T_6372, _T_6375) @[ifu_mem_ctl.scala 694:81] + node _T_6377 = or(_T_6376, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6378 = bits(_T_6377, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6379 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6378 : @[Reg.scala 28:19] _T_6379 <= _T_6369 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][49] <= _T_6379 @[ifu_mem_ctl.scala 685:41] - node _T_6380 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6381 = eq(_T_6380, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6382 = and(ic_valid_ff, _T_6381) @[ifu_mem_ctl.scala 685:97] - node _T_6383 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6384 = and(_T_6382, _T_6383) @[ifu_mem_ctl.scala 685:122] - node _T_6385 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 686:37] - node _T_6386 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6387 = and(_T_6385, _T_6386) @[ifu_mem_ctl.scala 686:59] - node _T_6388 = eq(perr_ic_index_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 686:102] - node _T_6389 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6390 = and(_T_6388, _T_6389) @[ifu_mem_ctl.scala 686:124] - node _T_6391 = or(_T_6387, _T_6390) @[ifu_mem_ctl.scala 686:81] - node _T_6392 = or(_T_6391, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6393 = bits(_T_6392, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][49] <= _T_6379 @[ifu_mem_ctl.scala 693:41] + node _T_6380 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6381 = eq(_T_6380, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6382 = and(ic_valid_ff, _T_6381) @[ifu_mem_ctl.scala 693:97] + node _T_6383 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6384 = and(_T_6382, _T_6383) @[ifu_mem_ctl.scala 693:122] + node _T_6385 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 694:37] + node _T_6386 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6387 = and(_T_6385, _T_6386) @[ifu_mem_ctl.scala 694:59] + node _T_6388 = eq(perr_ic_index_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 694:102] + node _T_6389 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6390 = and(_T_6388, _T_6389) @[ifu_mem_ctl.scala 694:124] + node _T_6391 = or(_T_6387, _T_6390) @[ifu_mem_ctl.scala 694:81] + node _T_6392 = or(_T_6391, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6393 = bits(_T_6392, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6394 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6393 : @[Reg.scala 28:19] _T_6394 <= _T_6384 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][50] <= _T_6394 @[ifu_mem_ctl.scala 685:41] - node _T_6395 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6396 = eq(_T_6395, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6397 = and(ic_valid_ff, _T_6396) @[ifu_mem_ctl.scala 685:97] - node _T_6398 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6399 = and(_T_6397, _T_6398) @[ifu_mem_ctl.scala 685:122] - node _T_6400 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 686:37] - node _T_6401 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6402 = and(_T_6400, _T_6401) @[ifu_mem_ctl.scala 686:59] - node _T_6403 = eq(perr_ic_index_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 686:102] - node _T_6404 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6405 = and(_T_6403, _T_6404) @[ifu_mem_ctl.scala 686:124] - node _T_6406 = or(_T_6402, _T_6405) @[ifu_mem_ctl.scala 686:81] - node _T_6407 = or(_T_6406, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6408 = bits(_T_6407, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][50] <= _T_6394 @[ifu_mem_ctl.scala 693:41] + node _T_6395 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6396 = eq(_T_6395, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6397 = and(ic_valid_ff, _T_6396) @[ifu_mem_ctl.scala 693:97] + node _T_6398 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6399 = and(_T_6397, _T_6398) @[ifu_mem_ctl.scala 693:122] + node _T_6400 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 694:37] + node _T_6401 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6402 = and(_T_6400, _T_6401) @[ifu_mem_ctl.scala 694:59] + node _T_6403 = eq(perr_ic_index_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 694:102] + node _T_6404 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6405 = and(_T_6403, _T_6404) @[ifu_mem_ctl.scala 694:124] + node _T_6406 = or(_T_6402, _T_6405) @[ifu_mem_ctl.scala 694:81] + node _T_6407 = or(_T_6406, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6408 = bits(_T_6407, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6409 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6408 : @[Reg.scala 28:19] _T_6409 <= _T_6399 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][51] <= _T_6409 @[ifu_mem_ctl.scala 685:41] - node _T_6410 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6411 = eq(_T_6410, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6412 = and(ic_valid_ff, _T_6411) @[ifu_mem_ctl.scala 685:97] - node _T_6413 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6414 = and(_T_6412, _T_6413) @[ifu_mem_ctl.scala 685:122] - node _T_6415 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 686:37] - node _T_6416 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6417 = and(_T_6415, _T_6416) @[ifu_mem_ctl.scala 686:59] - node _T_6418 = eq(perr_ic_index_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 686:102] - node _T_6419 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6420 = and(_T_6418, _T_6419) @[ifu_mem_ctl.scala 686:124] - node _T_6421 = or(_T_6417, _T_6420) @[ifu_mem_ctl.scala 686:81] - node _T_6422 = or(_T_6421, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6423 = bits(_T_6422, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][51] <= _T_6409 @[ifu_mem_ctl.scala 693:41] + node _T_6410 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6411 = eq(_T_6410, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6412 = and(ic_valid_ff, _T_6411) @[ifu_mem_ctl.scala 693:97] + node _T_6413 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6414 = and(_T_6412, _T_6413) @[ifu_mem_ctl.scala 693:122] + node _T_6415 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 694:37] + node _T_6416 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6417 = and(_T_6415, _T_6416) @[ifu_mem_ctl.scala 694:59] + node _T_6418 = eq(perr_ic_index_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 694:102] + node _T_6419 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6420 = and(_T_6418, _T_6419) @[ifu_mem_ctl.scala 694:124] + node _T_6421 = or(_T_6417, _T_6420) @[ifu_mem_ctl.scala 694:81] + node _T_6422 = or(_T_6421, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6423 = bits(_T_6422, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6424 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6423 : @[Reg.scala 28:19] _T_6424 <= _T_6414 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][52] <= _T_6424 @[ifu_mem_ctl.scala 685:41] - node _T_6425 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6426 = eq(_T_6425, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6427 = and(ic_valid_ff, _T_6426) @[ifu_mem_ctl.scala 685:97] - node _T_6428 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6429 = and(_T_6427, _T_6428) @[ifu_mem_ctl.scala 685:122] - node _T_6430 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 686:37] - node _T_6431 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6432 = and(_T_6430, _T_6431) @[ifu_mem_ctl.scala 686:59] - node _T_6433 = eq(perr_ic_index_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 686:102] - node _T_6434 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6435 = and(_T_6433, _T_6434) @[ifu_mem_ctl.scala 686:124] - node _T_6436 = or(_T_6432, _T_6435) @[ifu_mem_ctl.scala 686:81] - node _T_6437 = or(_T_6436, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6438 = bits(_T_6437, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][52] <= _T_6424 @[ifu_mem_ctl.scala 693:41] + node _T_6425 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6426 = eq(_T_6425, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6427 = and(ic_valid_ff, _T_6426) @[ifu_mem_ctl.scala 693:97] + node _T_6428 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6429 = and(_T_6427, _T_6428) @[ifu_mem_ctl.scala 693:122] + node _T_6430 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 694:37] + node _T_6431 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6432 = and(_T_6430, _T_6431) @[ifu_mem_ctl.scala 694:59] + node _T_6433 = eq(perr_ic_index_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 694:102] + node _T_6434 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6435 = and(_T_6433, _T_6434) @[ifu_mem_ctl.scala 694:124] + node _T_6436 = or(_T_6432, _T_6435) @[ifu_mem_ctl.scala 694:81] + node _T_6437 = or(_T_6436, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6438 = bits(_T_6437, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6439 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6438 : @[Reg.scala 28:19] _T_6439 <= _T_6429 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][53] <= _T_6439 @[ifu_mem_ctl.scala 685:41] - node _T_6440 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6441 = eq(_T_6440, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6442 = and(ic_valid_ff, _T_6441) @[ifu_mem_ctl.scala 685:97] - node _T_6443 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6444 = and(_T_6442, _T_6443) @[ifu_mem_ctl.scala 685:122] - node _T_6445 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 686:37] - node _T_6446 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6447 = and(_T_6445, _T_6446) @[ifu_mem_ctl.scala 686:59] - node _T_6448 = eq(perr_ic_index_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 686:102] - node _T_6449 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6450 = and(_T_6448, _T_6449) @[ifu_mem_ctl.scala 686:124] - node _T_6451 = or(_T_6447, _T_6450) @[ifu_mem_ctl.scala 686:81] - node _T_6452 = or(_T_6451, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6453 = bits(_T_6452, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][53] <= _T_6439 @[ifu_mem_ctl.scala 693:41] + node _T_6440 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6441 = eq(_T_6440, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6442 = and(ic_valid_ff, _T_6441) @[ifu_mem_ctl.scala 693:97] + node _T_6443 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6444 = and(_T_6442, _T_6443) @[ifu_mem_ctl.scala 693:122] + node _T_6445 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 694:37] + node _T_6446 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6447 = and(_T_6445, _T_6446) @[ifu_mem_ctl.scala 694:59] + node _T_6448 = eq(perr_ic_index_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 694:102] + node _T_6449 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6450 = and(_T_6448, _T_6449) @[ifu_mem_ctl.scala 694:124] + node _T_6451 = or(_T_6447, _T_6450) @[ifu_mem_ctl.scala 694:81] + node _T_6452 = or(_T_6451, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6453 = bits(_T_6452, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6454 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6453 : @[Reg.scala 28:19] _T_6454 <= _T_6444 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][54] <= _T_6454 @[ifu_mem_ctl.scala 685:41] - node _T_6455 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6456 = eq(_T_6455, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6457 = and(ic_valid_ff, _T_6456) @[ifu_mem_ctl.scala 685:97] - node _T_6458 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6459 = and(_T_6457, _T_6458) @[ifu_mem_ctl.scala 685:122] - node _T_6460 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 686:37] - node _T_6461 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6462 = and(_T_6460, _T_6461) @[ifu_mem_ctl.scala 686:59] - node _T_6463 = eq(perr_ic_index_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 686:102] - node _T_6464 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6465 = and(_T_6463, _T_6464) @[ifu_mem_ctl.scala 686:124] - node _T_6466 = or(_T_6462, _T_6465) @[ifu_mem_ctl.scala 686:81] - node _T_6467 = or(_T_6466, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6468 = bits(_T_6467, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][54] <= _T_6454 @[ifu_mem_ctl.scala 693:41] + node _T_6455 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6456 = eq(_T_6455, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6457 = and(ic_valid_ff, _T_6456) @[ifu_mem_ctl.scala 693:97] + node _T_6458 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6459 = and(_T_6457, _T_6458) @[ifu_mem_ctl.scala 693:122] + node _T_6460 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 694:37] + node _T_6461 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6462 = and(_T_6460, _T_6461) @[ifu_mem_ctl.scala 694:59] + node _T_6463 = eq(perr_ic_index_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 694:102] + node _T_6464 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6465 = and(_T_6463, _T_6464) @[ifu_mem_ctl.scala 694:124] + node _T_6466 = or(_T_6462, _T_6465) @[ifu_mem_ctl.scala 694:81] + node _T_6467 = or(_T_6466, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6468 = bits(_T_6467, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6469 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6468 : @[Reg.scala 28:19] _T_6469 <= _T_6459 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][55] <= _T_6469 @[ifu_mem_ctl.scala 685:41] - node _T_6470 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6471 = eq(_T_6470, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6472 = and(ic_valid_ff, _T_6471) @[ifu_mem_ctl.scala 685:97] - node _T_6473 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6474 = and(_T_6472, _T_6473) @[ifu_mem_ctl.scala 685:122] - node _T_6475 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 686:37] - node _T_6476 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6477 = and(_T_6475, _T_6476) @[ifu_mem_ctl.scala 686:59] - node _T_6478 = eq(perr_ic_index_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 686:102] - node _T_6479 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6480 = and(_T_6478, _T_6479) @[ifu_mem_ctl.scala 686:124] - node _T_6481 = or(_T_6477, _T_6480) @[ifu_mem_ctl.scala 686:81] - node _T_6482 = or(_T_6481, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6483 = bits(_T_6482, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][55] <= _T_6469 @[ifu_mem_ctl.scala 693:41] + node _T_6470 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6471 = eq(_T_6470, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6472 = and(ic_valid_ff, _T_6471) @[ifu_mem_ctl.scala 693:97] + node _T_6473 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6474 = and(_T_6472, _T_6473) @[ifu_mem_ctl.scala 693:122] + node _T_6475 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 694:37] + node _T_6476 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6477 = and(_T_6475, _T_6476) @[ifu_mem_ctl.scala 694:59] + node _T_6478 = eq(perr_ic_index_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 694:102] + node _T_6479 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6480 = and(_T_6478, _T_6479) @[ifu_mem_ctl.scala 694:124] + node _T_6481 = or(_T_6477, _T_6480) @[ifu_mem_ctl.scala 694:81] + node _T_6482 = or(_T_6481, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6483 = bits(_T_6482, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6484 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6483 : @[Reg.scala 28:19] _T_6484 <= _T_6474 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][56] <= _T_6484 @[ifu_mem_ctl.scala 685:41] - node _T_6485 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6486 = eq(_T_6485, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6487 = and(ic_valid_ff, _T_6486) @[ifu_mem_ctl.scala 685:97] - node _T_6488 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6489 = and(_T_6487, _T_6488) @[ifu_mem_ctl.scala 685:122] - node _T_6490 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 686:37] - node _T_6491 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6492 = and(_T_6490, _T_6491) @[ifu_mem_ctl.scala 686:59] - node _T_6493 = eq(perr_ic_index_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 686:102] - node _T_6494 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6495 = and(_T_6493, _T_6494) @[ifu_mem_ctl.scala 686:124] - node _T_6496 = or(_T_6492, _T_6495) @[ifu_mem_ctl.scala 686:81] - node _T_6497 = or(_T_6496, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6498 = bits(_T_6497, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][56] <= _T_6484 @[ifu_mem_ctl.scala 693:41] + node _T_6485 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6486 = eq(_T_6485, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6487 = and(ic_valid_ff, _T_6486) @[ifu_mem_ctl.scala 693:97] + node _T_6488 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6489 = and(_T_6487, _T_6488) @[ifu_mem_ctl.scala 693:122] + node _T_6490 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 694:37] + node _T_6491 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6492 = and(_T_6490, _T_6491) @[ifu_mem_ctl.scala 694:59] + node _T_6493 = eq(perr_ic_index_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 694:102] + node _T_6494 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6495 = and(_T_6493, _T_6494) @[ifu_mem_ctl.scala 694:124] + node _T_6496 = or(_T_6492, _T_6495) @[ifu_mem_ctl.scala 694:81] + node _T_6497 = or(_T_6496, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6498 = bits(_T_6497, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6499 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6498 : @[Reg.scala 28:19] _T_6499 <= _T_6489 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][57] <= _T_6499 @[ifu_mem_ctl.scala 685:41] - node _T_6500 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6501 = eq(_T_6500, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6502 = and(ic_valid_ff, _T_6501) @[ifu_mem_ctl.scala 685:97] - node _T_6503 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6504 = and(_T_6502, _T_6503) @[ifu_mem_ctl.scala 685:122] - node _T_6505 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 686:37] - node _T_6506 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6507 = and(_T_6505, _T_6506) @[ifu_mem_ctl.scala 686:59] - node _T_6508 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 686:102] - node _T_6509 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6510 = and(_T_6508, _T_6509) @[ifu_mem_ctl.scala 686:124] - node _T_6511 = or(_T_6507, _T_6510) @[ifu_mem_ctl.scala 686:81] - node _T_6512 = or(_T_6511, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6513 = bits(_T_6512, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][57] <= _T_6499 @[ifu_mem_ctl.scala 693:41] + node _T_6500 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6501 = eq(_T_6500, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6502 = and(ic_valid_ff, _T_6501) @[ifu_mem_ctl.scala 693:97] + node _T_6503 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6504 = and(_T_6502, _T_6503) @[ifu_mem_ctl.scala 693:122] + node _T_6505 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 694:37] + node _T_6506 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6507 = and(_T_6505, _T_6506) @[ifu_mem_ctl.scala 694:59] + node _T_6508 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 694:102] + node _T_6509 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6510 = and(_T_6508, _T_6509) @[ifu_mem_ctl.scala 694:124] + node _T_6511 = or(_T_6507, _T_6510) @[ifu_mem_ctl.scala 694:81] + node _T_6512 = or(_T_6511, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6513 = bits(_T_6512, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6514 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6513 : @[Reg.scala 28:19] _T_6514 <= _T_6504 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][58] <= _T_6514 @[ifu_mem_ctl.scala 685:41] - node _T_6515 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6516 = eq(_T_6515, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6517 = and(ic_valid_ff, _T_6516) @[ifu_mem_ctl.scala 685:97] - node _T_6518 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6519 = and(_T_6517, _T_6518) @[ifu_mem_ctl.scala 685:122] - node _T_6520 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 686:37] - node _T_6521 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6522 = and(_T_6520, _T_6521) @[ifu_mem_ctl.scala 686:59] - node _T_6523 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 686:102] - node _T_6524 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6525 = and(_T_6523, _T_6524) @[ifu_mem_ctl.scala 686:124] - node _T_6526 = or(_T_6522, _T_6525) @[ifu_mem_ctl.scala 686:81] - node _T_6527 = or(_T_6526, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6528 = bits(_T_6527, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][58] <= _T_6514 @[ifu_mem_ctl.scala 693:41] + node _T_6515 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6516 = eq(_T_6515, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6517 = and(ic_valid_ff, _T_6516) @[ifu_mem_ctl.scala 693:97] + node _T_6518 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6519 = and(_T_6517, _T_6518) @[ifu_mem_ctl.scala 693:122] + node _T_6520 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 694:37] + node _T_6521 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6522 = and(_T_6520, _T_6521) @[ifu_mem_ctl.scala 694:59] + node _T_6523 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 694:102] + node _T_6524 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6525 = and(_T_6523, _T_6524) @[ifu_mem_ctl.scala 694:124] + node _T_6526 = or(_T_6522, _T_6525) @[ifu_mem_ctl.scala 694:81] + node _T_6527 = or(_T_6526, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6528 = bits(_T_6527, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6529 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6528 : @[Reg.scala 28:19] _T_6529 <= _T_6519 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][59] <= _T_6529 @[ifu_mem_ctl.scala 685:41] - node _T_6530 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6531 = eq(_T_6530, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6532 = and(ic_valid_ff, _T_6531) @[ifu_mem_ctl.scala 685:97] - node _T_6533 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6534 = and(_T_6532, _T_6533) @[ifu_mem_ctl.scala 685:122] - node _T_6535 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 686:37] - node _T_6536 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6537 = and(_T_6535, _T_6536) @[ifu_mem_ctl.scala 686:59] - node _T_6538 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 686:102] - node _T_6539 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6540 = and(_T_6538, _T_6539) @[ifu_mem_ctl.scala 686:124] - node _T_6541 = or(_T_6537, _T_6540) @[ifu_mem_ctl.scala 686:81] - node _T_6542 = or(_T_6541, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6543 = bits(_T_6542, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][59] <= _T_6529 @[ifu_mem_ctl.scala 693:41] + node _T_6530 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6531 = eq(_T_6530, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6532 = and(ic_valid_ff, _T_6531) @[ifu_mem_ctl.scala 693:97] + node _T_6533 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6534 = and(_T_6532, _T_6533) @[ifu_mem_ctl.scala 693:122] + node _T_6535 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 694:37] + node _T_6536 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6537 = and(_T_6535, _T_6536) @[ifu_mem_ctl.scala 694:59] + node _T_6538 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 694:102] + node _T_6539 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6540 = and(_T_6538, _T_6539) @[ifu_mem_ctl.scala 694:124] + node _T_6541 = or(_T_6537, _T_6540) @[ifu_mem_ctl.scala 694:81] + node _T_6542 = or(_T_6541, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6543 = bits(_T_6542, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6544 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6543 : @[Reg.scala 28:19] _T_6544 <= _T_6534 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][60] <= _T_6544 @[ifu_mem_ctl.scala 685:41] - node _T_6545 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6546 = eq(_T_6545, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6547 = and(ic_valid_ff, _T_6546) @[ifu_mem_ctl.scala 685:97] - node _T_6548 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6549 = and(_T_6547, _T_6548) @[ifu_mem_ctl.scala 685:122] - node _T_6550 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 686:37] - node _T_6551 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6552 = and(_T_6550, _T_6551) @[ifu_mem_ctl.scala 686:59] - node _T_6553 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 686:102] - node _T_6554 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6555 = and(_T_6553, _T_6554) @[ifu_mem_ctl.scala 686:124] - node _T_6556 = or(_T_6552, _T_6555) @[ifu_mem_ctl.scala 686:81] - node _T_6557 = or(_T_6556, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6558 = bits(_T_6557, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][60] <= _T_6544 @[ifu_mem_ctl.scala 693:41] + node _T_6545 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6546 = eq(_T_6545, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6547 = and(ic_valid_ff, _T_6546) @[ifu_mem_ctl.scala 693:97] + node _T_6548 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6549 = and(_T_6547, _T_6548) @[ifu_mem_ctl.scala 693:122] + node _T_6550 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 694:37] + node _T_6551 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6552 = and(_T_6550, _T_6551) @[ifu_mem_ctl.scala 694:59] + node _T_6553 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 694:102] + node _T_6554 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6555 = and(_T_6553, _T_6554) @[ifu_mem_ctl.scala 694:124] + node _T_6556 = or(_T_6552, _T_6555) @[ifu_mem_ctl.scala 694:81] + node _T_6557 = or(_T_6556, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6558 = bits(_T_6557, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6559 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6558 : @[Reg.scala 28:19] _T_6559 <= _T_6549 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][61] <= _T_6559 @[ifu_mem_ctl.scala 685:41] - node _T_6560 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6561 = eq(_T_6560, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6562 = and(ic_valid_ff, _T_6561) @[ifu_mem_ctl.scala 685:97] - node _T_6563 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6564 = and(_T_6562, _T_6563) @[ifu_mem_ctl.scala 685:122] - node _T_6565 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 686:37] - node _T_6566 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6567 = and(_T_6565, _T_6566) @[ifu_mem_ctl.scala 686:59] - node _T_6568 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 686:102] - node _T_6569 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6570 = and(_T_6568, _T_6569) @[ifu_mem_ctl.scala 686:124] - node _T_6571 = or(_T_6567, _T_6570) @[ifu_mem_ctl.scala 686:81] - node _T_6572 = or(_T_6571, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6573 = bits(_T_6572, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][61] <= _T_6559 @[ifu_mem_ctl.scala 693:41] + node _T_6560 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6561 = eq(_T_6560, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6562 = and(ic_valid_ff, _T_6561) @[ifu_mem_ctl.scala 693:97] + node _T_6563 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6564 = and(_T_6562, _T_6563) @[ifu_mem_ctl.scala 693:122] + node _T_6565 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 694:37] + node _T_6566 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6567 = and(_T_6565, _T_6566) @[ifu_mem_ctl.scala 694:59] + node _T_6568 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 694:102] + node _T_6569 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6570 = and(_T_6568, _T_6569) @[ifu_mem_ctl.scala 694:124] + node _T_6571 = or(_T_6567, _T_6570) @[ifu_mem_ctl.scala 694:81] + node _T_6572 = or(_T_6571, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6573 = bits(_T_6572, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6574 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6573 : @[Reg.scala 28:19] _T_6574 <= _T_6564 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][62] <= _T_6574 @[ifu_mem_ctl.scala 685:41] - node _T_6575 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6576 = eq(_T_6575, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6577 = and(ic_valid_ff, _T_6576) @[ifu_mem_ctl.scala 685:97] - node _T_6578 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6579 = and(_T_6577, _T_6578) @[ifu_mem_ctl.scala 685:122] - node _T_6580 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 686:37] - node _T_6581 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_6582 = and(_T_6580, _T_6581) @[ifu_mem_ctl.scala 686:59] - node _T_6583 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 686:102] - node _T_6584 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_6585 = and(_T_6583, _T_6584) @[ifu_mem_ctl.scala 686:124] - node _T_6586 = or(_T_6582, _T_6585) @[ifu_mem_ctl.scala 686:81] - node _T_6587 = or(_T_6586, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6588 = bits(_T_6587, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][62] <= _T_6574 @[ifu_mem_ctl.scala 693:41] + node _T_6575 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6576 = eq(_T_6575, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6577 = and(ic_valid_ff, _T_6576) @[ifu_mem_ctl.scala 693:97] + node _T_6578 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6579 = and(_T_6577, _T_6578) @[ifu_mem_ctl.scala 693:122] + node _T_6580 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 694:37] + node _T_6581 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_6582 = and(_T_6580, _T_6581) @[ifu_mem_ctl.scala 694:59] + node _T_6583 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 694:102] + node _T_6584 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_6585 = and(_T_6583, _T_6584) @[ifu_mem_ctl.scala 694:124] + node _T_6586 = or(_T_6582, _T_6585) @[ifu_mem_ctl.scala 694:81] + node _T_6587 = or(_T_6586, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6588 = bits(_T_6587, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6589 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6588 : @[Reg.scala 28:19] _T_6589 <= _T_6579 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][63] <= _T_6589 @[ifu_mem_ctl.scala 685:41] - node _T_6590 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6591 = eq(_T_6590, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6592 = and(ic_valid_ff, _T_6591) @[ifu_mem_ctl.scala 685:97] - node _T_6593 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6594 = and(_T_6592, _T_6593) @[ifu_mem_ctl.scala 685:122] - node _T_6595 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 686:37] - node _T_6596 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6597 = and(_T_6595, _T_6596) @[ifu_mem_ctl.scala 686:59] - node _T_6598 = eq(perr_ic_index_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 686:102] - node _T_6599 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6600 = and(_T_6598, _T_6599) @[ifu_mem_ctl.scala 686:124] - node _T_6601 = or(_T_6597, _T_6600) @[ifu_mem_ctl.scala 686:81] - node _T_6602 = or(_T_6601, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6603 = bits(_T_6602, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][63] <= _T_6589 @[ifu_mem_ctl.scala 693:41] + node _T_6590 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6591 = eq(_T_6590, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6592 = and(ic_valid_ff, _T_6591) @[ifu_mem_ctl.scala 693:97] + node _T_6593 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6594 = and(_T_6592, _T_6593) @[ifu_mem_ctl.scala 693:122] + node _T_6595 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 694:37] + node _T_6596 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6597 = and(_T_6595, _T_6596) @[ifu_mem_ctl.scala 694:59] + node _T_6598 = eq(perr_ic_index_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 694:102] + node _T_6599 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6600 = and(_T_6598, _T_6599) @[ifu_mem_ctl.scala 694:124] + node _T_6601 = or(_T_6597, _T_6600) @[ifu_mem_ctl.scala 694:81] + node _T_6602 = or(_T_6601, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6603 = bits(_T_6602, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6604 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6603 : @[Reg.scala 28:19] _T_6604 <= _T_6594 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][32] <= _T_6604 @[ifu_mem_ctl.scala 685:41] - node _T_6605 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6606 = eq(_T_6605, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6607 = and(ic_valid_ff, _T_6606) @[ifu_mem_ctl.scala 685:97] - node _T_6608 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6609 = and(_T_6607, _T_6608) @[ifu_mem_ctl.scala 685:122] - node _T_6610 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 686:37] - node _T_6611 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6612 = and(_T_6610, _T_6611) @[ifu_mem_ctl.scala 686:59] - node _T_6613 = eq(perr_ic_index_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 686:102] - node _T_6614 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6615 = and(_T_6613, _T_6614) @[ifu_mem_ctl.scala 686:124] - node _T_6616 = or(_T_6612, _T_6615) @[ifu_mem_ctl.scala 686:81] - node _T_6617 = or(_T_6616, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6618 = bits(_T_6617, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][32] <= _T_6604 @[ifu_mem_ctl.scala 693:41] + node _T_6605 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6606 = eq(_T_6605, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6607 = and(ic_valid_ff, _T_6606) @[ifu_mem_ctl.scala 693:97] + node _T_6608 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6609 = and(_T_6607, _T_6608) @[ifu_mem_ctl.scala 693:122] + node _T_6610 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 694:37] + node _T_6611 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6612 = and(_T_6610, _T_6611) @[ifu_mem_ctl.scala 694:59] + node _T_6613 = eq(perr_ic_index_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 694:102] + node _T_6614 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6615 = and(_T_6613, _T_6614) @[ifu_mem_ctl.scala 694:124] + node _T_6616 = or(_T_6612, _T_6615) @[ifu_mem_ctl.scala 694:81] + node _T_6617 = or(_T_6616, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6618 = bits(_T_6617, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6619 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6618 : @[Reg.scala 28:19] _T_6619 <= _T_6609 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][33] <= _T_6619 @[ifu_mem_ctl.scala 685:41] - node _T_6620 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6621 = eq(_T_6620, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6622 = and(ic_valid_ff, _T_6621) @[ifu_mem_ctl.scala 685:97] - node _T_6623 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6624 = and(_T_6622, _T_6623) @[ifu_mem_ctl.scala 685:122] - node _T_6625 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 686:37] - node _T_6626 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6627 = and(_T_6625, _T_6626) @[ifu_mem_ctl.scala 686:59] - node _T_6628 = eq(perr_ic_index_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 686:102] - node _T_6629 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6630 = and(_T_6628, _T_6629) @[ifu_mem_ctl.scala 686:124] - node _T_6631 = or(_T_6627, _T_6630) @[ifu_mem_ctl.scala 686:81] - node _T_6632 = or(_T_6631, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6633 = bits(_T_6632, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][33] <= _T_6619 @[ifu_mem_ctl.scala 693:41] + node _T_6620 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6621 = eq(_T_6620, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6622 = and(ic_valid_ff, _T_6621) @[ifu_mem_ctl.scala 693:97] + node _T_6623 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6624 = and(_T_6622, _T_6623) @[ifu_mem_ctl.scala 693:122] + node _T_6625 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 694:37] + node _T_6626 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6627 = and(_T_6625, _T_6626) @[ifu_mem_ctl.scala 694:59] + node _T_6628 = eq(perr_ic_index_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 694:102] + node _T_6629 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6630 = and(_T_6628, _T_6629) @[ifu_mem_ctl.scala 694:124] + node _T_6631 = or(_T_6627, _T_6630) @[ifu_mem_ctl.scala 694:81] + node _T_6632 = or(_T_6631, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6633 = bits(_T_6632, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6634 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6633 : @[Reg.scala 28:19] _T_6634 <= _T_6624 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][34] <= _T_6634 @[ifu_mem_ctl.scala 685:41] - node _T_6635 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6636 = eq(_T_6635, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6637 = and(ic_valid_ff, _T_6636) @[ifu_mem_ctl.scala 685:97] - node _T_6638 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6639 = and(_T_6637, _T_6638) @[ifu_mem_ctl.scala 685:122] - node _T_6640 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 686:37] - node _T_6641 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6642 = and(_T_6640, _T_6641) @[ifu_mem_ctl.scala 686:59] - node _T_6643 = eq(perr_ic_index_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 686:102] - node _T_6644 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6645 = and(_T_6643, _T_6644) @[ifu_mem_ctl.scala 686:124] - node _T_6646 = or(_T_6642, _T_6645) @[ifu_mem_ctl.scala 686:81] - node _T_6647 = or(_T_6646, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6648 = bits(_T_6647, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][34] <= _T_6634 @[ifu_mem_ctl.scala 693:41] + node _T_6635 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6636 = eq(_T_6635, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6637 = and(ic_valid_ff, _T_6636) @[ifu_mem_ctl.scala 693:97] + node _T_6638 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6639 = and(_T_6637, _T_6638) @[ifu_mem_ctl.scala 693:122] + node _T_6640 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 694:37] + node _T_6641 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6642 = and(_T_6640, _T_6641) @[ifu_mem_ctl.scala 694:59] + node _T_6643 = eq(perr_ic_index_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 694:102] + node _T_6644 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6645 = and(_T_6643, _T_6644) @[ifu_mem_ctl.scala 694:124] + node _T_6646 = or(_T_6642, _T_6645) @[ifu_mem_ctl.scala 694:81] + node _T_6647 = or(_T_6646, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6648 = bits(_T_6647, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6649 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6648 : @[Reg.scala 28:19] _T_6649 <= _T_6639 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][35] <= _T_6649 @[ifu_mem_ctl.scala 685:41] - node _T_6650 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6651 = eq(_T_6650, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6652 = and(ic_valid_ff, _T_6651) @[ifu_mem_ctl.scala 685:97] - node _T_6653 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6654 = and(_T_6652, _T_6653) @[ifu_mem_ctl.scala 685:122] - node _T_6655 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 686:37] - node _T_6656 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6657 = and(_T_6655, _T_6656) @[ifu_mem_ctl.scala 686:59] - node _T_6658 = eq(perr_ic_index_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 686:102] - node _T_6659 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6660 = and(_T_6658, _T_6659) @[ifu_mem_ctl.scala 686:124] - node _T_6661 = or(_T_6657, _T_6660) @[ifu_mem_ctl.scala 686:81] - node _T_6662 = or(_T_6661, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6663 = bits(_T_6662, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][35] <= _T_6649 @[ifu_mem_ctl.scala 693:41] + node _T_6650 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6651 = eq(_T_6650, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6652 = and(ic_valid_ff, _T_6651) @[ifu_mem_ctl.scala 693:97] + node _T_6653 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6654 = and(_T_6652, _T_6653) @[ifu_mem_ctl.scala 693:122] + node _T_6655 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 694:37] + node _T_6656 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6657 = and(_T_6655, _T_6656) @[ifu_mem_ctl.scala 694:59] + node _T_6658 = eq(perr_ic_index_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 694:102] + node _T_6659 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6660 = and(_T_6658, _T_6659) @[ifu_mem_ctl.scala 694:124] + node _T_6661 = or(_T_6657, _T_6660) @[ifu_mem_ctl.scala 694:81] + node _T_6662 = or(_T_6661, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6663 = bits(_T_6662, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6664 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6663 : @[Reg.scala 28:19] _T_6664 <= _T_6654 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][36] <= _T_6664 @[ifu_mem_ctl.scala 685:41] - node _T_6665 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6666 = eq(_T_6665, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6667 = and(ic_valid_ff, _T_6666) @[ifu_mem_ctl.scala 685:97] - node _T_6668 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6669 = and(_T_6667, _T_6668) @[ifu_mem_ctl.scala 685:122] - node _T_6670 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 686:37] - node _T_6671 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6672 = and(_T_6670, _T_6671) @[ifu_mem_ctl.scala 686:59] - node _T_6673 = eq(perr_ic_index_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 686:102] - node _T_6674 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6675 = and(_T_6673, _T_6674) @[ifu_mem_ctl.scala 686:124] - node _T_6676 = or(_T_6672, _T_6675) @[ifu_mem_ctl.scala 686:81] - node _T_6677 = or(_T_6676, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6678 = bits(_T_6677, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][36] <= _T_6664 @[ifu_mem_ctl.scala 693:41] + node _T_6665 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6666 = eq(_T_6665, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6667 = and(ic_valid_ff, _T_6666) @[ifu_mem_ctl.scala 693:97] + node _T_6668 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6669 = and(_T_6667, _T_6668) @[ifu_mem_ctl.scala 693:122] + node _T_6670 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 694:37] + node _T_6671 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6672 = and(_T_6670, _T_6671) @[ifu_mem_ctl.scala 694:59] + node _T_6673 = eq(perr_ic_index_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 694:102] + node _T_6674 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6675 = and(_T_6673, _T_6674) @[ifu_mem_ctl.scala 694:124] + node _T_6676 = or(_T_6672, _T_6675) @[ifu_mem_ctl.scala 694:81] + node _T_6677 = or(_T_6676, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6678 = bits(_T_6677, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6679 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6678 : @[Reg.scala 28:19] _T_6679 <= _T_6669 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][37] <= _T_6679 @[ifu_mem_ctl.scala 685:41] - node _T_6680 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6681 = eq(_T_6680, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6682 = and(ic_valid_ff, _T_6681) @[ifu_mem_ctl.scala 685:97] - node _T_6683 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6684 = and(_T_6682, _T_6683) @[ifu_mem_ctl.scala 685:122] - node _T_6685 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 686:37] - node _T_6686 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6687 = and(_T_6685, _T_6686) @[ifu_mem_ctl.scala 686:59] - node _T_6688 = eq(perr_ic_index_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 686:102] - node _T_6689 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6690 = and(_T_6688, _T_6689) @[ifu_mem_ctl.scala 686:124] - node _T_6691 = or(_T_6687, _T_6690) @[ifu_mem_ctl.scala 686:81] - node _T_6692 = or(_T_6691, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6693 = bits(_T_6692, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][37] <= _T_6679 @[ifu_mem_ctl.scala 693:41] + node _T_6680 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6681 = eq(_T_6680, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6682 = and(ic_valid_ff, _T_6681) @[ifu_mem_ctl.scala 693:97] + node _T_6683 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6684 = and(_T_6682, _T_6683) @[ifu_mem_ctl.scala 693:122] + node _T_6685 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 694:37] + node _T_6686 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6687 = and(_T_6685, _T_6686) @[ifu_mem_ctl.scala 694:59] + node _T_6688 = eq(perr_ic_index_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 694:102] + node _T_6689 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6690 = and(_T_6688, _T_6689) @[ifu_mem_ctl.scala 694:124] + node _T_6691 = or(_T_6687, _T_6690) @[ifu_mem_ctl.scala 694:81] + node _T_6692 = or(_T_6691, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6693 = bits(_T_6692, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6694 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6693 : @[Reg.scala 28:19] _T_6694 <= _T_6684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][38] <= _T_6694 @[ifu_mem_ctl.scala 685:41] - node _T_6695 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6696 = eq(_T_6695, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6697 = and(ic_valid_ff, _T_6696) @[ifu_mem_ctl.scala 685:97] - node _T_6698 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6699 = and(_T_6697, _T_6698) @[ifu_mem_ctl.scala 685:122] - node _T_6700 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 686:37] - node _T_6701 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6702 = and(_T_6700, _T_6701) @[ifu_mem_ctl.scala 686:59] - node _T_6703 = eq(perr_ic_index_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 686:102] - node _T_6704 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6705 = and(_T_6703, _T_6704) @[ifu_mem_ctl.scala 686:124] - node _T_6706 = or(_T_6702, _T_6705) @[ifu_mem_ctl.scala 686:81] - node _T_6707 = or(_T_6706, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6708 = bits(_T_6707, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][38] <= _T_6694 @[ifu_mem_ctl.scala 693:41] + node _T_6695 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6696 = eq(_T_6695, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6697 = and(ic_valid_ff, _T_6696) @[ifu_mem_ctl.scala 693:97] + node _T_6698 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6699 = and(_T_6697, _T_6698) @[ifu_mem_ctl.scala 693:122] + node _T_6700 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 694:37] + node _T_6701 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6702 = and(_T_6700, _T_6701) @[ifu_mem_ctl.scala 694:59] + node _T_6703 = eq(perr_ic_index_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 694:102] + node _T_6704 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6705 = and(_T_6703, _T_6704) @[ifu_mem_ctl.scala 694:124] + node _T_6706 = or(_T_6702, _T_6705) @[ifu_mem_ctl.scala 694:81] + node _T_6707 = or(_T_6706, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6708 = bits(_T_6707, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6709 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6708 : @[Reg.scala 28:19] _T_6709 <= _T_6699 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][39] <= _T_6709 @[ifu_mem_ctl.scala 685:41] - node _T_6710 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6711 = eq(_T_6710, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6712 = and(ic_valid_ff, _T_6711) @[ifu_mem_ctl.scala 685:97] - node _T_6713 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6714 = and(_T_6712, _T_6713) @[ifu_mem_ctl.scala 685:122] - node _T_6715 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 686:37] - node _T_6716 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6717 = and(_T_6715, _T_6716) @[ifu_mem_ctl.scala 686:59] - node _T_6718 = eq(perr_ic_index_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 686:102] - node _T_6719 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6720 = and(_T_6718, _T_6719) @[ifu_mem_ctl.scala 686:124] - node _T_6721 = or(_T_6717, _T_6720) @[ifu_mem_ctl.scala 686:81] - node _T_6722 = or(_T_6721, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6723 = bits(_T_6722, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][39] <= _T_6709 @[ifu_mem_ctl.scala 693:41] + node _T_6710 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6711 = eq(_T_6710, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6712 = and(ic_valid_ff, _T_6711) @[ifu_mem_ctl.scala 693:97] + node _T_6713 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6714 = and(_T_6712, _T_6713) @[ifu_mem_ctl.scala 693:122] + node _T_6715 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 694:37] + node _T_6716 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6717 = and(_T_6715, _T_6716) @[ifu_mem_ctl.scala 694:59] + node _T_6718 = eq(perr_ic_index_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 694:102] + node _T_6719 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6720 = and(_T_6718, _T_6719) @[ifu_mem_ctl.scala 694:124] + node _T_6721 = or(_T_6717, _T_6720) @[ifu_mem_ctl.scala 694:81] + node _T_6722 = or(_T_6721, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6723 = bits(_T_6722, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6724 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6723 : @[Reg.scala 28:19] _T_6724 <= _T_6714 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][40] <= _T_6724 @[ifu_mem_ctl.scala 685:41] - node _T_6725 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6726 = eq(_T_6725, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6727 = and(ic_valid_ff, _T_6726) @[ifu_mem_ctl.scala 685:97] - node _T_6728 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6729 = and(_T_6727, _T_6728) @[ifu_mem_ctl.scala 685:122] - node _T_6730 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 686:37] - node _T_6731 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6732 = and(_T_6730, _T_6731) @[ifu_mem_ctl.scala 686:59] - node _T_6733 = eq(perr_ic_index_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 686:102] - node _T_6734 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6735 = and(_T_6733, _T_6734) @[ifu_mem_ctl.scala 686:124] - node _T_6736 = or(_T_6732, _T_6735) @[ifu_mem_ctl.scala 686:81] - node _T_6737 = or(_T_6736, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6738 = bits(_T_6737, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][40] <= _T_6724 @[ifu_mem_ctl.scala 693:41] + node _T_6725 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6726 = eq(_T_6725, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6727 = and(ic_valid_ff, _T_6726) @[ifu_mem_ctl.scala 693:97] + node _T_6728 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6729 = and(_T_6727, _T_6728) @[ifu_mem_ctl.scala 693:122] + node _T_6730 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 694:37] + node _T_6731 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6732 = and(_T_6730, _T_6731) @[ifu_mem_ctl.scala 694:59] + node _T_6733 = eq(perr_ic_index_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 694:102] + node _T_6734 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6735 = and(_T_6733, _T_6734) @[ifu_mem_ctl.scala 694:124] + node _T_6736 = or(_T_6732, _T_6735) @[ifu_mem_ctl.scala 694:81] + node _T_6737 = or(_T_6736, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6738 = bits(_T_6737, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6739 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6738 : @[Reg.scala 28:19] _T_6739 <= _T_6729 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][41] <= _T_6739 @[ifu_mem_ctl.scala 685:41] - node _T_6740 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6741 = eq(_T_6740, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6742 = and(ic_valid_ff, _T_6741) @[ifu_mem_ctl.scala 685:97] - node _T_6743 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6744 = and(_T_6742, _T_6743) @[ifu_mem_ctl.scala 685:122] - node _T_6745 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 686:37] - node _T_6746 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6747 = and(_T_6745, _T_6746) @[ifu_mem_ctl.scala 686:59] - node _T_6748 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 686:102] - node _T_6749 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6750 = and(_T_6748, _T_6749) @[ifu_mem_ctl.scala 686:124] - node _T_6751 = or(_T_6747, _T_6750) @[ifu_mem_ctl.scala 686:81] - node _T_6752 = or(_T_6751, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6753 = bits(_T_6752, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][41] <= _T_6739 @[ifu_mem_ctl.scala 693:41] + node _T_6740 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6741 = eq(_T_6740, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6742 = and(ic_valid_ff, _T_6741) @[ifu_mem_ctl.scala 693:97] + node _T_6743 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6744 = and(_T_6742, _T_6743) @[ifu_mem_ctl.scala 693:122] + node _T_6745 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 694:37] + node _T_6746 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6747 = and(_T_6745, _T_6746) @[ifu_mem_ctl.scala 694:59] + node _T_6748 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 694:102] + node _T_6749 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6750 = and(_T_6748, _T_6749) @[ifu_mem_ctl.scala 694:124] + node _T_6751 = or(_T_6747, _T_6750) @[ifu_mem_ctl.scala 694:81] + node _T_6752 = or(_T_6751, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6753 = bits(_T_6752, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6754 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6753 : @[Reg.scala 28:19] _T_6754 <= _T_6744 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][42] <= _T_6754 @[ifu_mem_ctl.scala 685:41] - node _T_6755 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6756 = eq(_T_6755, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6757 = and(ic_valid_ff, _T_6756) @[ifu_mem_ctl.scala 685:97] - node _T_6758 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6759 = and(_T_6757, _T_6758) @[ifu_mem_ctl.scala 685:122] - node _T_6760 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 686:37] - node _T_6761 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6762 = and(_T_6760, _T_6761) @[ifu_mem_ctl.scala 686:59] - node _T_6763 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 686:102] - node _T_6764 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6765 = and(_T_6763, _T_6764) @[ifu_mem_ctl.scala 686:124] - node _T_6766 = or(_T_6762, _T_6765) @[ifu_mem_ctl.scala 686:81] - node _T_6767 = or(_T_6766, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6768 = bits(_T_6767, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][42] <= _T_6754 @[ifu_mem_ctl.scala 693:41] + node _T_6755 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6756 = eq(_T_6755, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6757 = and(ic_valid_ff, _T_6756) @[ifu_mem_ctl.scala 693:97] + node _T_6758 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6759 = and(_T_6757, _T_6758) @[ifu_mem_ctl.scala 693:122] + node _T_6760 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 694:37] + node _T_6761 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6762 = and(_T_6760, _T_6761) @[ifu_mem_ctl.scala 694:59] + node _T_6763 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 694:102] + node _T_6764 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6765 = and(_T_6763, _T_6764) @[ifu_mem_ctl.scala 694:124] + node _T_6766 = or(_T_6762, _T_6765) @[ifu_mem_ctl.scala 694:81] + node _T_6767 = or(_T_6766, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6768 = bits(_T_6767, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6769 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6768 : @[Reg.scala 28:19] _T_6769 <= _T_6759 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][43] <= _T_6769 @[ifu_mem_ctl.scala 685:41] - node _T_6770 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6771 = eq(_T_6770, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6772 = and(ic_valid_ff, _T_6771) @[ifu_mem_ctl.scala 685:97] - node _T_6773 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6774 = and(_T_6772, _T_6773) @[ifu_mem_ctl.scala 685:122] - node _T_6775 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 686:37] - node _T_6776 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6777 = and(_T_6775, _T_6776) @[ifu_mem_ctl.scala 686:59] - node _T_6778 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 686:102] - node _T_6779 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6780 = and(_T_6778, _T_6779) @[ifu_mem_ctl.scala 686:124] - node _T_6781 = or(_T_6777, _T_6780) @[ifu_mem_ctl.scala 686:81] - node _T_6782 = or(_T_6781, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6783 = bits(_T_6782, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][43] <= _T_6769 @[ifu_mem_ctl.scala 693:41] + node _T_6770 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6771 = eq(_T_6770, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6772 = and(ic_valid_ff, _T_6771) @[ifu_mem_ctl.scala 693:97] + node _T_6773 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6774 = and(_T_6772, _T_6773) @[ifu_mem_ctl.scala 693:122] + node _T_6775 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 694:37] + node _T_6776 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6777 = and(_T_6775, _T_6776) @[ifu_mem_ctl.scala 694:59] + node _T_6778 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 694:102] + node _T_6779 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6780 = and(_T_6778, _T_6779) @[ifu_mem_ctl.scala 694:124] + node _T_6781 = or(_T_6777, _T_6780) @[ifu_mem_ctl.scala 694:81] + node _T_6782 = or(_T_6781, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6783 = bits(_T_6782, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6784 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6783 : @[Reg.scala 28:19] _T_6784 <= _T_6774 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][44] <= _T_6784 @[ifu_mem_ctl.scala 685:41] - node _T_6785 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6786 = eq(_T_6785, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6787 = and(ic_valid_ff, _T_6786) @[ifu_mem_ctl.scala 685:97] - node _T_6788 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6789 = and(_T_6787, _T_6788) @[ifu_mem_ctl.scala 685:122] - node _T_6790 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 686:37] - node _T_6791 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6792 = and(_T_6790, _T_6791) @[ifu_mem_ctl.scala 686:59] - node _T_6793 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 686:102] - node _T_6794 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6795 = and(_T_6793, _T_6794) @[ifu_mem_ctl.scala 686:124] - node _T_6796 = or(_T_6792, _T_6795) @[ifu_mem_ctl.scala 686:81] - node _T_6797 = or(_T_6796, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6798 = bits(_T_6797, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][44] <= _T_6784 @[ifu_mem_ctl.scala 693:41] + node _T_6785 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6786 = eq(_T_6785, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6787 = and(ic_valid_ff, _T_6786) @[ifu_mem_ctl.scala 693:97] + node _T_6788 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6789 = and(_T_6787, _T_6788) @[ifu_mem_ctl.scala 693:122] + node _T_6790 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 694:37] + node _T_6791 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6792 = and(_T_6790, _T_6791) @[ifu_mem_ctl.scala 694:59] + node _T_6793 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 694:102] + node _T_6794 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6795 = and(_T_6793, _T_6794) @[ifu_mem_ctl.scala 694:124] + node _T_6796 = or(_T_6792, _T_6795) @[ifu_mem_ctl.scala 694:81] + node _T_6797 = or(_T_6796, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6798 = bits(_T_6797, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6799 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6798 : @[Reg.scala 28:19] _T_6799 <= _T_6789 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][45] <= _T_6799 @[ifu_mem_ctl.scala 685:41] - node _T_6800 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6801 = eq(_T_6800, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6802 = and(ic_valid_ff, _T_6801) @[ifu_mem_ctl.scala 685:97] - node _T_6803 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6804 = and(_T_6802, _T_6803) @[ifu_mem_ctl.scala 685:122] - node _T_6805 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 686:37] - node _T_6806 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6807 = and(_T_6805, _T_6806) @[ifu_mem_ctl.scala 686:59] - node _T_6808 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 686:102] - node _T_6809 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6810 = and(_T_6808, _T_6809) @[ifu_mem_ctl.scala 686:124] - node _T_6811 = or(_T_6807, _T_6810) @[ifu_mem_ctl.scala 686:81] - node _T_6812 = or(_T_6811, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6813 = bits(_T_6812, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][45] <= _T_6799 @[ifu_mem_ctl.scala 693:41] + node _T_6800 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6801 = eq(_T_6800, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6802 = and(ic_valid_ff, _T_6801) @[ifu_mem_ctl.scala 693:97] + node _T_6803 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6804 = and(_T_6802, _T_6803) @[ifu_mem_ctl.scala 693:122] + node _T_6805 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 694:37] + node _T_6806 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6807 = and(_T_6805, _T_6806) @[ifu_mem_ctl.scala 694:59] + node _T_6808 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 694:102] + node _T_6809 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6810 = and(_T_6808, _T_6809) @[ifu_mem_ctl.scala 694:124] + node _T_6811 = or(_T_6807, _T_6810) @[ifu_mem_ctl.scala 694:81] + node _T_6812 = or(_T_6811, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6813 = bits(_T_6812, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6814 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6813 : @[Reg.scala 28:19] _T_6814 <= _T_6804 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][46] <= _T_6814 @[ifu_mem_ctl.scala 685:41] - node _T_6815 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6816 = eq(_T_6815, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6817 = and(ic_valid_ff, _T_6816) @[ifu_mem_ctl.scala 685:97] - node _T_6818 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6819 = and(_T_6817, _T_6818) @[ifu_mem_ctl.scala 685:122] - node _T_6820 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 686:37] - node _T_6821 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6822 = and(_T_6820, _T_6821) @[ifu_mem_ctl.scala 686:59] - node _T_6823 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 686:102] - node _T_6824 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6825 = and(_T_6823, _T_6824) @[ifu_mem_ctl.scala 686:124] - node _T_6826 = or(_T_6822, _T_6825) @[ifu_mem_ctl.scala 686:81] - node _T_6827 = or(_T_6826, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6828 = bits(_T_6827, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][46] <= _T_6814 @[ifu_mem_ctl.scala 693:41] + node _T_6815 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6816 = eq(_T_6815, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6817 = and(ic_valid_ff, _T_6816) @[ifu_mem_ctl.scala 693:97] + node _T_6818 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6819 = and(_T_6817, _T_6818) @[ifu_mem_ctl.scala 693:122] + node _T_6820 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 694:37] + node _T_6821 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6822 = and(_T_6820, _T_6821) @[ifu_mem_ctl.scala 694:59] + node _T_6823 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 694:102] + node _T_6824 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6825 = and(_T_6823, _T_6824) @[ifu_mem_ctl.scala 694:124] + node _T_6826 = or(_T_6822, _T_6825) @[ifu_mem_ctl.scala 694:81] + node _T_6827 = or(_T_6826, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6828 = bits(_T_6827, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6829 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6828 : @[Reg.scala 28:19] _T_6829 <= _T_6819 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][47] <= _T_6829 @[ifu_mem_ctl.scala 685:41] - node _T_6830 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6831 = eq(_T_6830, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6832 = and(ic_valid_ff, _T_6831) @[ifu_mem_ctl.scala 685:97] - node _T_6833 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6834 = and(_T_6832, _T_6833) @[ifu_mem_ctl.scala 685:122] - node _T_6835 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 686:37] - node _T_6836 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6837 = and(_T_6835, _T_6836) @[ifu_mem_ctl.scala 686:59] - node _T_6838 = eq(perr_ic_index_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 686:102] - node _T_6839 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6840 = and(_T_6838, _T_6839) @[ifu_mem_ctl.scala 686:124] - node _T_6841 = or(_T_6837, _T_6840) @[ifu_mem_ctl.scala 686:81] - node _T_6842 = or(_T_6841, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6843 = bits(_T_6842, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][47] <= _T_6829 @[ifu_mem_ctl.scala 693:41] + node _T_6830 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6831 = eq(_T_6830, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6832 = and(ic_valid_ff, _T_6831) @[ifu_mem_ctl.scala 693:97] + node _T_6833 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6834 = and(_T_6832, _T_6833) @[ifu_mem_ctl.scala 693:122] + node _T_6835 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 694:37] + node _T_6836 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6837 = and(_T_6835, _T_6836) @[ifu_mem_ctl.scala 694:59] + node _T_6838 = eq(perr_ic_index_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 694:102] + node _T_6839 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6840 = and(_T_6838, _T_6839) @[ifu_mem_ctl.scala 694:124] + node _T_6841 = or(_T_6837, _T_6840) @[ifu_mem_ctl.scala 694:81] + node _T_6842 = or(_T_6841, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6843 = bits(_T_6842, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6844 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6843 : @[Reg.scala 28:19] _T_6844 <= _T_6834 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][48] <= _T_6844 @[ifu_mem_ctl.scala 685:41] - node _T_6845 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6846 = eq(_T_6845, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6847 = and(ic_valid_ff, _T_6846) @[ifu_mem_ctl.scala 685:97] - node _T_6848 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6849 = and(_T_6847, _T_6848) @[ifu_mem_ctl.scala 685:122] - node _T_6850 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 686:37] - node _T_6851 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6852 = and(_T_6850, _T_6851) @[ifu_mem_ctl.scala 686:59] - node _T_6853 = eq(perr_ic_index_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 686:102] - node _T_6854 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6855 = and(_T_6853, _T_6854) @[ifu_mem_ctl.scala 686:124] - node _T_6856 = or(_T_6852, _T_6855) @[ifu_mem_ctl.scala 686:81] - node _T_6857 = or(_T_6856, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6858 = bits(_T_6857, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][48] <= _T_6844 @[ifu_mem_ctl.scala 693:41] + node _T_6845 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6846 = eq(_T_6845, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6847 = and(ic_valid_ff, _T_6846) @[ifu_mem_ctl.scala 693:97] + node _T_6848 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6849 = and(_T_6847, _T_6848) @[ifu_mem_ctl.scala 693:122] + node _T_6850 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 694:37] + node _T_6851 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6852 = and(_T_6850, _T_6851) @[ifu_mem_ctl.scala 694:59] + node _T_6853 = eq(perr_ic_index_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 694:102] + node _T_6854 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6855 = and(_T_6853, _T_6854) @[ifu_mem_ctl.scala 694:124] + node _T_6856 = or(_T_6852, _T_6855) @[ifu_mem_ctl.scala 694:81] + node _T_6857 = or(_T_6856, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6858 = bits(_T_6857, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6859 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6858 : @[Reg.scala 28:19] _T_6859 <= _T_6849 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][49] <= _T_6859 @[ifu_mem_ctl.scala 685:41] - node _T_6860 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6861 = eq(_T_6860, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6862 = and(ic_valid_ff, _T_6861) @[ifu_mem_ctl.scala 685:97] - node _T_6863 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6864 = and(_T_6862, _T_6863) @[ifu_mem_ctl.scala 685:122] - node _T_6865 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 686:37] - node _T_6866 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6867 = and(_T_6865, _T_6866) @[ifu_mem_ctl.scala 686:59] - node _T_6868 = eq(perr_ic_index_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 686:102] - node _T_6869 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6870 = and(_T_6868, _T_6869) @[ifu_mem_ctl.scala 686:124] - node _T_6871 = or(_T_6867, _T_6870) @[ifu_mem_ctl.scala 686:81] - node _T_6872 = or(_T_6871, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6873 = bits(_T_6872, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][49] <= _T_6859 @[ifu_mem_ctl.scala 693:41] + node _T_6860 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6861 = eq(_T_6860, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6862 = and(ic_valid_ff, _T_6861) @[ifu_mem_ctl.scala 693:97] + node _T_6863 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6864 = and(_T_6862, _T_6863) @[ifu_mem_ctl.scala 693:122] + node _T_6865 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 694:37] + node _T_6866 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6867 = and(_T_6865, _T_6866) @[ifu_mem_ctl.scala 694:59] + node _T_6868 = eq(perr_ic_index_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 694:102] + node _T_6869 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6870 = and(_T_6868, _T_6869) @[ifu_mem_ctl.scala 694:124] + node _T_6871 = or(_T_6867, _T_6870) @[ifu_mem_ctl.scala 694:81] + node _T_6872 = or(_T_6871, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6873 = bits(_T_6872, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6874 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6873 : @[Reg.scala 28:19] _T_6874 <= _T_6864 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][50] <= _T_6874 @[ifu_mem_ctl.scala 685:41] - node _T_6875 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6876 = eq(_T_6875, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6877 = and(ic_valid_ff, _T_6876) @[ifu_mem_ctl.scala 685:97] - node _T_6878 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6879 = and(_T_6877, _T_6878) @[ifu_mem_ctl.scala 685:122] - node _T_6880 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 686:37] - node _T_6881 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6882 = and(_T_6880, _T_6881) @[ifu_mem_ctl.scala 686:59] - node _T_6883 = eq(perr_ic_index_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 686:102] - node _T_6884 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6885 = and(_T_6883, _T_6884) @[ifu_mem_ctl.scala 686:124] - node _T_6886 = or(_T_6882, _T_6885) @[ifu_mem_ctl.scala 686:81] - node _T_6887 = or(_T_6886, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6888 = bits(_T_6887, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][50] <= _T_6874 @[ifu_mem_ctl.scala 693:41] + node _T_6875 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6876 = eq(_T_6875, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6877 = and(ic_valid_ff, _T_6876) @[ifu_mem_ctl.scala 693:97] + node _T_6878 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6879 = and(_T_6877, _T_6878) @[ifu_mem_ctl.scala 693:122] + node _T_6880 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 694:37] + node _T_6881 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6882 = and(_T_6880, _T_6881) @[ifu_mem_ctl.scala 694:59] + node _T_6883 = eq(perr_ic_index_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 694:102] + node _T_6884 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6885 = and(_T_6883, _T_6884) @[ifu_mem_ctl.scala 694:124] + node _T_6886 = or(_T_6882, _T_6885) @[ifu_mem_ctl.scala 694:81] + node _T_6887 = or(_T_6886, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6888 = bits(_T_6887, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6889 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6888 : @[Reg.scala 28:19] _T_6889 <= _T_6879 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][51] <= _T_6889 @[ifu_mem_ctl.scala 685:41] - node _T_6890 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6891 = eq(_T_6890, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6892 = and(ic_valid_ff, _T_6891) @[ifu_mem_ctl.scala 685:97] - node _T_6893 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6894 = and(_T_6892, _T_6893) @[ifu_mem_ctl.scala 685:122] - node _T_6895 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 686:37] - node _T_6896 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6897 = and(_T_6895, _T_6896) @[ifu_mem_ctl.scala 686:59] - node _T_6898 = eq(perr_ic_index_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 686:102] - node _T_6899 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6900 = and(_T_6898, _T_6899) @[ifu_mem_ctl.scala 686:124] - node _T_6901 = or(_T_6897, _T_6900) @[ifu_mem_ctl.scala 686:81] - node _T_6902 = or(_T_6901, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6903 = bits(_T_6902, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][51] <= _T_6889 @[ifu_mem_ctl.scala 693:41] + node _T_6890 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6891 = eq(_T_6890, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6892 = and(ic_valid_ff, _T_6891) @[ifu_mem_ctl.scala 693:97] + node _T_6893 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6894 = and(_T_6892, _T_6893) @[ifu_mem_ctl.scala 693:122] + node _T_6895 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 694:37] + node _T_6896 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6897 = and(_T_6895, _T_6896) @[ifu_mem_ctl.scala 694:59] + node _T_6898 = eq(perr_ic_index_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 694:102] + node _T_6899 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6900 = and(_T_6898, _T_6899) @[ifu_mem_ctl.scala 694:124] + node _T_6901 = or(_T_6897, _T_6900) @[ifu_mem_ctl.scala 694:81] + node _T_6902 = or(_T_6901, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6903 = bits(_T_6902, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6904 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6903 : @[Reg.scala 28:19] _T_6904 <= _T_6894 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][52] <= _T_6904 @[ifu_mem_ctl.scala 685:41] - node _T_6905 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6906 = eq(_T_6905, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6907 = and(ic_valid_ff, _T_6906) @[ifu_mem_ctl.scala 685:97] - node _T_6908 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6909 = and(_T_6907, _T_6908) @[ifu_mem_ctl.scala 685:122] - node _T_6910 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 686:37] - node _T_6911 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6912 = and(_T_6910, _T_6911) @[ifu_mem_ctl.scala 686:59] - node _T_6913 = eq(perr_ic_index_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 686:102] - node _T_6914 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6915 = and(_T_6913, _T_6914) @[ifu_mem_ctl.scala 686:124] - node _T_6916 = or(_T_6912, _T_6915) @[ifu_mem_ctl.scala 686:81] - node _T_6917 = or(_T_6916, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6918 = bits(_T_6917, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][52] <= _T_6904 @[ifu_mem_ctl.scala 693:41] + node _T_6905 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6906 = eq(_T_6905, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6907 = and(ic_valid_ff, _T_6906) @[ifu_mem_ctl.scala 693:97] + node _T_6908 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6909 = and(_T_6907, _T_6908) @[ifu_mem_ctl.scala 693:122] + node _T_6910 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 694:37] + node _T_6911 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6912 = and(_T_6910, _T_6911) @[ifu_mem_ctl.scala 694:59] + node _T_6913 = eq(perr_ic_index_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 694:102] + node _T_6914 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6915 = and(_T_6913, _T_6914) @[ifu_mem_ctl.scala 694:124] + node _T_6916 = or(_T_6912, _T_6915) @[ifu_mem_ctl.scala 694:81] + node _T_6917 = or(_T_6916, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6918 = bits(_T_6917, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6919 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6918 : @[Reg.scala 28:19] _T_6919 <= _T_6909 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][53] <= _T_6919 @[ifu_mem_ctl.scala 685:41] - node _T_6920 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6921 = eq(_T_6920, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6922 = and(ic_valid_ff, _T_6921) @[ifu_mem_ctl.scala 685:97] - node _T_6923 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6924 = and(_T_6922, _T_6923) @[ifu_mem_ctl.scala 685:122] - node _T_6925 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 686:37] - node _T_6926 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6927 = and(_T_6925, _T_6926) @[ifu_mem_ctl.scala 686:59] - node _T_6928 = eq(perr_ic_index_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 686:102] - node _T_6929 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6930 = and(_T_6928, _T_6929) @[ifu_mem_ctl.scala 686:124] - node _T_6931 = or(_T_6927, _T_6930) @[ifu_mem_ctl.scala 686:81] - node _T_6932 = or(_T_6931, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6933 = bits(_T_6932, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][53] <= _T_6919 @[ifu_mem_ctl.scala 693:41] + node _T_6920 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6921 = eq(_T_6920, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6922 = and(ic_valid_ff, _T_6921) @[ifu_mem_ctl.scala 693:97] + node _T_6923 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6924 = and(_T_6922, _T_6923) @[ifu_mem_ctl.scala 693:122] + node _T_6925 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 694:37] + node _T_6926 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6927 = and(_T_6925, _T_6926) @[ifu_mem_ctl.scala 694:59] + node _T_6928 = eq(perr_ic_index_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 694:102] + node _T_6929 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6930 = and(_T_6928, _T_6929) @[ifu_mem_ctl.scala 694:124] + node _T_6931 = or(_T_6927, _T_6930) @[ifu_mem_ctl.scala 694:81] + node _T_6932 = or(_T_6931, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6933 = bits(_T_6932, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6934 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6933 : @[Reg.scala 28:19] _T_6934 <= _T_6924 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][54] <= _T_6934 @[ifu_mem_ctl.scala 685:41] - node _T_6935 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6936 = eq(_T_6935, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6937 = and(ic_valid_ff, _T_6936) @[ifu_mem_ctl.scala 685:97] - node _T_6938 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6939 = and(_T_6937, _T_6938) @[ifu_mem_ctl.scala 685:122] - node _T_6940 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 686:37] - node _T_6941 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6942 = and(_T_6940, _T_6941) @[ifu_mem_ctl.scala 686:59] - node _T_6943 = eq(perr_ic_index_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 686:102] - node _T_6944 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6945 = and(_T_6943, _T_6944) @[ifu_mem_ctl.scala 686:124] - node _T_6946 = or(_T_6942, _T_6945) @[ifu_mem_ctl.scala 686:81] - node _T_6947 = or(_T_6946, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6948 = bits(_T_6947, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][54] <= _T_6934 @[ifu_mem_ctl.scala 693:41] + node _T_6935 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6936 = eq(_T_6935, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6937 = and(ic_valid_ff, _T_6936) @[ifu_mem_ctl.scala 693:97] + node _T_6938 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6939 = and(_T_6937, _T_6938) @[ifu_mem_ctl.scala 693:122] + node _T_6940 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 694:37] + node _T_6941 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6942 = and(_T_6940, _T_6941) @[ifu_mem_ctl.scala 694:59] + node _T_6943 = eq(perr_ic_index_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 694:102] + node _T_6944 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6945 = and(_T_6943, _T_6944) @[ifu_mem_ctl.scala 694:124] + node _T_6946 = or(_T_6942, _T_6945) @[ifu_mem_ctl.scala 694:81] + node _T_6947 = or(_T_6946, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6948 = bits(_T_6947, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6949 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6948 : @[Reg.scala 28:19] _T_6949 <= _T_6939 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][55] <= _T_6949 @[ifu_mem_ctl.scala 685:41] - node _T_6950 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6951 = eq(_T_6950, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6952 = and(ic_valid_ff, _T_6951) @[ifu_mem_ctl.scala 685:97] - node _T_6953 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6954 = and(_T_6952, _T_6953) @[ifu_mem_ctl.scala 685:122] - node _T_6955 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 686:37] - node _T_6956 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6957 = and(_T_6955, _T_6956) @[ifu_mem_ctl.scala 686:59] - node _T_6958 = eq(perr_ic_index_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 686:102] - node _T_6959 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6960 = and(_T_6958, _T_6959) @[ifu_mem_ctl.scala 686:124] - node _T_6961 = or(_T_6957, _T_6960) @[ifu_mem_ctl.scala 686:81] - node _T_6962 = or(_T_6961, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6963 = bits(_T_6962, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][55] <= _T_6949 @[ifu_mem_ctl.scala 693:41] + node _T_6950 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6951 = eq(_T_6950, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6952 = and(ic_valid_ff, _T_6951) @[ifu_mem_ctl.scala 693:97] + node _T_6953 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6954 = and(_T_6952, _T_6953) @[ifu_mem_ctl.scala 693:122] + node _T_6955 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 694:37] + node _T_6956 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6957 = and(_T_6955, _T_6956) @[ifu_mem_ctl.scala 694:59] + node _T_6958 = eq(perr_ic_index_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 694:102] + node _T_6959 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6960 = and(_T_6958, _T_6959) @[ifu_mem_ctl.scala 694:124] + node _T_6961 = or(_T_6957, _T_6960) @[ifu_mem_ctl.scala 694:81] + node _T_6962 = or(_T_6961, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6963 = bits(_T_6962, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6964 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6963 : @[Reg.scala 28:19] _T_6964 <= _T_6954 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][56] <= _T_6964 @[ifu_mem_ctl.scala 685:41] - node _T_6965 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6966 = eq(_T_6965, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6967 = and(ic_valid_ff, _T_6966) @[ifu_mem_ctl.scala 685:97] - node _T_6968 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6969 = and(_T_6967, _T_6968) @[ifu_mem_ctl.scala 685:122] - node _T_6970 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 686:37] - node _T_6971 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6972 = and(_T_6970, _T_6971) @[ifu_mem_ctl.scala 686:59] - node _T_6973 = eq(perr_ic_index_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 686:102] - node _T_6974 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6975 = and(_T_6973, _T_6974) @[ifu_mem_ctl.scala 686:124] - node _T_6976 = or(_T_6972, _T_6975) @[ifu_mem_ctl.scala 686:81] - node _T_6977 = or(_T_6976, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6978 = bits(_T_6977, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][56] <= _T_6964 @[ifu_mem_ctl.scala 693:41] + node _T_6965 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6966 = eq(_T_6965, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6967 = and(ic_valid_ff, _T_6966) @[ifu_mem_ctl.scala 693:97] + node _T_6968 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6969 = and(_T_6967, _T_6968) @[ifu_mem_ctl.scala 693:122] + node _T_6970 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 694:37] + node _T_6971 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6972 = and(_T_6970, _T_6971) @[ifu_mem_ctl.scala 694:59] + node _T_6973 = eq(perr_ic_index_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 694:102] + node _T_6974 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6975 = and(_T_6973, _T_6974) @[ifu_mem_ctl.scala 694:124] + node _T_6976 = or(_T_6972, _T_6975) @[ifu_mem_ctl.scala 694:81] + node _T_6977 = or(_T_6976, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6978 = bits(_T_6977, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6979 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6978 : @[Reg.scala 28:19] _T_6979 <= _T_6969 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][57] <= _T_6979 @[ifu_mem_ctl.scala 685:41] - node _T_6980 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6981 = eq(_T_6980, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6982 = and(ic_valid_ff, _T_6981) @[ifu_mem_ctl.scala 685:97] - node _T_6983 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6984 = and(_T_6982, _T_6983) @[ifu_mem_ctl.scala 685:122] - node _T_6985 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 686:37] - node _T_6986 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_6987 = and(_T_6985, _T_6986) @[ifu_mem_ctl.scala 686:59] - node _T_6988 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 686:102] - node _T_6989 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_6990 = and(_T_6988, _T_6989) @[ifu_mem_ctl.scala 686:124] - node _T_6991 = or(_T_6987, _T_6990) @[ifu_mem_ctl.scala 686:81] - node _T_6992 = or(_T_6991, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_6993 = bits(_T_6992, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][57] <= _T_6979 @[ifu_mem_ctl.scala 693:41] + node _T_6980 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6981 = eq(_T_6980, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6982 = and(ic_valid_ff, _T_6981) @[ifu_mem_ctl.scala 693:97] + node _T_6983 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6984 = and(_T_6982, _T_6983) @[ifu_mem_ctl.scala 693:122] + node _T_6985 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 694:37] + node _T_6986 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_6987 = and(_T_6985, _T_6986) @[ifu_mem_ctl.scala 694:59] + node _T_6988 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 694:102] + node _T_6989 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_6990 = and(_T_6988, _T_6989) @[ifu_mem_ctl.scala 694:124] + node _T_6991 = or(_T_6987, _T_6990) @[ifu_mem_ctl.scala 694:81] + node _T_6992 = or(_T_6991, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_6993 = bits(_T_6992, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_6994 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6993 : @[Reg.scala 28:19] _T_6994 <= _T_6984 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][58] <= _T_6994 @[ifu_mem_ctl.scala 685:41] - node _T_6995 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_6996 = eq(_T_6995, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_6997 = and(ic_valid_ff, _T_6996) @[ifu_mem_ctl.scala 685:97] - node _T_6998 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_6999 = and(_T_6997, _T_6998) @[ifu_mem_ctl.scala 685:122] - node _T_7000 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 686:37] - node _T_7001 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7002 = and(_T_7000, _T_7001) @[ifu_mem_ctl.scala 686:59] - node _T_7003 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 686:102] - node _T_7004 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7005 = and(_T_7003, _T_7004) @[ifu_mem_ctl.scala 686:124] - node _T_7006 = or(_T_7002, _T_7005) @[ifu_mem_ctl.scala 686:81] - node _T_7007 = or(_T_7006, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7008 = bits(_T_7007, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][58] <= _T_6994 @[ifu_mem_ctl.scala 693:41] + node _T_6995 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_6996 = eq(_T_6995, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_6997 = and(ic_valid_ff, _T_6996) @[ifu_mem_ctl.scala 693:97] + node _T_6998 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_6999 = and(_T_6997, _T_6998) @[ifu_mem_ctl.scala 693:122] + node _T_7000 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 694:37] + node _T_7001 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7002 = and(_T_7000, _T_7001) @[ifu_mem_ctl.scala 694:59] + node _T_7003 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 694:102] + node _T_7004 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7005 = and(_T_7003, _T_7004) @[ifu_mem_ctl.scala 694:124] + node _T_7006 = or(_T_7002, _T_7005) @[ifu_mem_ctl.scala 694:81] + node _T_7007 = or(_T_7006, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7008 = bits(_T_7007, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7009 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7008 : @[Reg.scala 28:19] _T_7009 <= _T_6999 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][59] <= _T_7009 @[ifu_mem_ctl.scala 685:41] - node _T_7010 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7011 = eq(_T_7010, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7012 = and(ic_valid_ff, _T_7011) @[ifu_mem_ctl.scala 685:97] - node _T_7013 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7014 = and(_T_7012, _T_7013) @[ifu_mem_ctl.scala 685:122] - node _T_7015 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 686:37] - node _T_7016 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7017 = and(_T_7015, _T_7016) @[ifu_mem_ctl.scala 686:59] - node _T_7018 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 686:102] - node _T_7019 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7020 = and(_T_7018, _T_7019) @[ifu_mem_ctl.scala 686:124] - node _T_7021 = or(_T_7017, _T_7020) @[ifu_mem_ctl.scala 686:81] - node _T_7022 = or(_T_7021, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7023 = bits(_T_7022, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][59] <= _T_7009 @[ifu_mem_ctl.scala 693:41] + node _T_7010 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7011 = eq(_T_7010, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7012 = and(ic_valid_ff, _T_7011) @[ifu_mem_ctl.scala 693:97] + node _T_7013 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7014 = and(_T_7012, _T_7013) @[ifu_mem_ctl.scala 693:122] + node _T_7015 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 694:37] + node _T_7016 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7017 = and(_T_7015, _T_7016) @[ifu_mem_ctl.scala 694:59] + node _T_7018 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 694:102] + node _T_7019 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7020 = and(_T_7018, _T_7019) @[ifu_mem_ctl.scala 694:124] + node _T_7021 = or(_T_7017, _T_7020) @[ifu_mem_ctl.scala 694:81] + node _T_7022 = or(_T_7021, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7023 = bits(_T_7022, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7024 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7023 : @[Reg.scala 28:19] _T_7024 <= _T_7014 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][60] <= _T_7024 @[ifu_mem_ctl.scala 685:41] - node _T_7025 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7026 = eq(_T_7025, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7027 = and(ic_valid_ff, _T_7026) @[ifu_mem_ctl.scala 685:97] - node _T_7028 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7029 = and(_T_7027, _T_7028) @[ifu_mem_ctl.scala 685:122] - node _T_7030 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 686:37] - node _T_7031 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7032 = and(_T_7030, _T_7031) @[ifu_mem_ctl.scala 686:59] - node _T_7033 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 686:102] - node _T_7034 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7035 = and(_T_7033, _T_7034) @[ifu_mem_ctl.scala 686:124] - node _T_7036 = or(_T_7032, _T_7035) @[ifu_mem_ctl.scala 686:81] - node _T_7037 = or(_T_7036, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7038 = bits(_T_7037, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][60] <= _T_7024 @[ifu_mem_ctl.scala 693:41] + node _T_7025 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7026 = eq(_T_7025, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7027 = and(ic_valid_ff, _T_7026) @[ifu_mem_ctl.scala 693:97] + node _T_7028 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7029 = and(_T_7027, _T_7028) @[ifu_mem_ctl.scala 693:122] + node _T_7030 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 694:37] + node _T_7031 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7032 = and(_T_7030, _T_7031) @[ifu_mem_ctl.scala 694:59] + node _T_7033 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 694:102] + node _T_7034 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7035 = and(_T_7033, _T_7034) @[ifu_mem_ctl.scala 694:124] + node _T_7036 = or(_T_7032, _T_7035) @[ifu_mem_ctl.scala 694:81] + node _T_7037 = or(_T_7036, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7038 = bits(_T_7037, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7039 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7038 : @[Reg.scala 28:19] _T_7039 <= _T_7029 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][61] <= _T_7039 @[ifu_mem_ctl.scala 685:41] - node _T_7040 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7041 = eq(_T_7040, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7042 = and(ic_valid_ff, _T_7041) @[ifu_mem_ctl.scala 685:97] - node _T_7043 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7044 = and(_T_7042, _T_7043) @[ifu_mem_ctl.scala 685:122] - node _T_7045 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 686:37] - node _T_7046 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7047 = and(_T_7045, _T_7046) @[ifu_mem_ctl.scala 686:59] - node _T_7048 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 686:102] - node _T_7049 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7050 = and(_T_7048, _T_7049) @[ifu_mem_ctl.scala 686:124] - node _T_7051 = or(_T_7047, _T_7050) @[ifu_mem_ctl.scala 686:81] - node _T_7052 = or(_T_7051, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7053 = bits(_T_7052, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][61] <= _T_7039 @[ifu_mem_ctl.scala 693:41] + node _T_7040 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7041 = eq(_T_7040, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7042 = and(ic_valid_ff, _T_7041) @[ifu_mem_ctl.scala 693:97] + node _T_7043 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7044 = and(_T_7042, _T_7043) @[ifu_mem_ctl.scala 693:122] + node _T_7045 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 694:37] + node _T_7046 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7047 = and(_T_7045, _T_7046) @[ifu_mem_ctl.scala 694:59] + node _T_7048 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 694:102] + node _T_7049 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7050 = and(_T_7048, _T_7049) @[ifu_mem_ctl.scala 694:124] + node _T_7051 = or(_T_7047, _T_7050) @[ifu_mem_ctl.scala 694:81] + node _T_7052 = or(_T_7051, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7053 = bits(_T_7052, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7054 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7053 : @[Reg.scala 28:19] _T_7054 <= _T_7044 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][62] <= _T_7054 @[ifu_mem_ctl.scala 685:41] - node _T_7055 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7056 = eq(_T_7055, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7057 = and(ic_valid_ff, _T_7056) @[ifu_mem_ctl.scala 685:97] - node _T_7058 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7059 = and(_T_7057, _T_7058) @[ifu_mem_ctl.scala 685:122] - node _T_7060 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 686:37] - node _T_7061 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7062 = and(_T_7060, _T_7061) @[ifu_mem_ctl.scala 686:59] - node _T_7063 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 686:102] - node _T_7064 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7065 = and(_T_7063, _T_7064) @[ifu_mem_ctl.scala 686:124] - node _T_7066 = or(_T_7062, _T_7065) @[ifu_mem_ctl.scala 686:81] - node _T_7067 = or(_T_7066, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7068 = bits(_T_7067, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][62] <= _T_7054 @[ifu_mem_ctl.scala 693:41] + node _T_7055 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7056 = eq(_T_7055, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7057 = and(ic_valid_ff, _T_7056) @[ifu_mem_ctl.scala 693:97] + node _T_7058 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7059 = and(_T_7057, _T_7058) @[ifu_mem_ctl.scala 693:122] + node _T_7060 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 694:37] + node _T_7061 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7062 = and(_T_7060, _T_7061) @[ifu_mem_ctl.scala 694:59] + node _T_7063 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 694:102] + node _T_7064 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7065 = and(_T_7063, _T_7064) @[ifu_mem_ctl.scala 694:124] + node _T_7066 = or(_T_7062, _T_7065) @[ifu_mem_ctl.scala 694:81] + node _T_7067 = or(_T_7066, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7068 = bits(_T_7067, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7069 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7068 : @[Reg.scala 28:19] _T_7069 <= _T_7059 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][63] <= _T_7069 @[ifu_mem_ctl.scala 685:41] - node _T_7070 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7071 = eq(_T_7070, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7072 = and(ic_valid_ff, _T_7071) @[ifu_mem_ctl.scala 685:97] - node _T_7073 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7074 = and(_T_7072, _T_7073) @[ifu_mem_ctl.scala 685:122] - node _T_7075 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 686:37] - node _T_7076 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7077 = and(_T_7075, _T_7076) @[ifu_mem_ctl.scala 686:59] - node _T_7078 = eq(perr_ic_index_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 686:102] - node _T_7079 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7080 = and(_T_7078, _T_7079) @[ifu_mem_ctl.scala 686:124] - node _T_7081 = or(_T_7077, _T_7080) @[ifu_mem_ctl.scala 686:81] - node _T_7082 = or(_T_7081, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7083 = bits(_T_7082, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][63] <= _T_7069 @[ifu_mem_ctl.scala 693:41] + node _T_7070 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7071 = eq(_T_7070, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7072 = and(ic_valid_ff, _T_7071) @[ifu_mem_ctl.scala 693:97] + node _T_7073 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7074 = and(_T_7072, _T_7073) @[ifu_mem_ctl.scala 693:122] + node _T_7075 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 694:37] + node _T_7076 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7077 = and(_T_7075, _T_7076) @[ifu_mem_ctl.scala 694:59] + node _T_7078 = eq(perr_ic_index_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 694:102] + node _T_7079 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7080 = and(_T_7078, _T_7079) @[ifu_mem_ctl.scala 694:124] + node _T_7081 = or(_T_7077, _T_7080) @[ifu_mem_ctl.scala 694:81] + node _T_7082 = or(_T_7081, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7083 = bits(_T_7082, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7084 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7083 : @[Reg.scala 28:19] _T_7084 <= _T_7074 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][64] <= _T_7084 @[ifu_mem_ctl.scala 685:41] - node _T_7085 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7086 = eq(_T_7085, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7087 = and(ic_valid_ff, _T_7086) @[ifu_mem_ctl.scala 685:97] - node _T_7088 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7089 = and(_T_7087, _T_7088) @[ifu_mem_ctl.scala 685:122] - node _T_7090 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 686:37] - node _T_7091 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7092 = and(_T_7090, _T_7091) @[ifu_mem_ctl.scala 686:59] - node _T_7093 = eq(perr_ic_index_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 686:102] - node _T_7094 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7095 = and(_T_7093, _T_7094) @[ifu_mem_ctl.scala 686:124] - node _T_7096 = or(_T_7092, _T_7095) @[ifu_mem_ctl.scala 686:81] - node _T_7097 = or(_T_7096, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7098 = bits(_T_7097, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][64] <= _T_7084 @[ifu_mem_ctl.scala 693:41] + node _T_7085 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7086 = eq(_T_7085, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7087 = and(ic_valid_ff, _T_7086) @[ifu_mem_ctl.scala 693:97] + node _T_7088 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7089 = and(_T_7087, _T_7088) @[ifu_mem_ctl.scala 693:122] + node _T_7090 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 694:37] + node _T_7091 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7092 = and(_T_7090, _T_7091) @[ifu_mem_ctl.scala 694:59] + node _T_7093 = eq(perr_ic_index_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 694:102] + node _T_7094 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7095 = and(_T_7093, _T_7094) @[ifu_mem_ctl.scala 694:124] + node _T_7096 = or(_T_7092, _T_7095) @[ifu_mem_ctl.scala 694:81] + node _T_7097 = or(_T_7096, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7098 = bits(_T_7097, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7099 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7098 : @[Reg.scala 28:19] _T_7099 <= _T_7089 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][65] <= _T_7099 @[ifu_mem_ctl.scala 685:41] - node _T_7100 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7101 = eq(_T_7100, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7102 = and(ic_valid_ff, _T_7101) @[ifu_mem_ctl.scala 685:97] - node _T_7103 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7104 = and(_T_7102, _T_7103) @[ifu_mem_ctl.scala 685:122] - node _T_7105 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 686:37] - node _T_7106 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7107 = and(_T_7105, _T_7106) @[ifu_mem_ctl.scala 686:59] - node _T_7108 = eq(perr_ic_index_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 686:102] - node _T_7109 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7110 = and(_T_7108, _T_7109) @[ifu_mem_ctl.scala 686:124] - node _T_7111 = or(_T_7107, _T_7110) @[ifu_mem_ctl.scala 686:81] - node _T_7112 = or(_T_7111, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7113 = bits(_T_7112, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][65] <= _T_7099 @[ifu_mem_ctl.scala 693:41] + node _T_7100 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7101 = eq(_T_7100, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7102 = and(ic_valid_ff, _T_7101) @[ifu_mem_ctl.scala 693:97] + node _T_7103 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7104 = and(_T_7102, _T_7103) @[ifu_mem_ctl.scala 693:122] + node _T_7105 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 694:37] + node _T_7106 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7107 = and(_T_7105, _T_7106) @[ifu_mem_ctl.scala 694:59] + node _T_7108 = eq(perr_ic_index_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 694:102] + node _T_7109 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7110 = and(_T_7108, _T_7109) @[ifu_mem_ctl.scala 694:124] + node _T_7111 = or(_T_7107, _T_7110) @[ifu_mem_ctl.scala 694:81] + node _T_7112 = or(_T_7111, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7113 = bits(_T_7112, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7114 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7113 : @[Reg.scala 28:19] _T_7114 <= _T_7104 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][66] <= _T_7114 @[ifu_mem_ctl.scala 685:41] - node _T_7115 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7116 = eq(_T_7115, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7117 = and(ic_valid_ff, _T_7116) @[ifu_mem_ctl.scala 685:97] - node _T_7118 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7119 = and(_T_7117, _T_7118) @[ifu_mem_ctl.scala 685:122] - node _T_7120 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 686:37] - node _T_7121 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7122 = and(_T_7120, _T_7121) @[ifu_mem_ctl.scala 686:59] - node _T_7123 = eq(perr_ic_index_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 686:102] - node _T_7124 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7125 = and(_T_7123, _T_7124) @[ifu_mem_ctl.scala 686:124] - node _T_7126 = or(_T_7122, _T_7125) @[ifu_mem_ctl.scala 686:81] - node _T_7127 = or(_T_7126, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7128 = bits(_T_7127, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][66] <= _T_7114 @[ifu_mem_ctl.scala 693:41] + node _T_7115 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7116 = eq(_T_7115, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7117 = and(ic_valid_ff, _T_7116) @[ifu_mem_ctl.scala 693:97] + node _T_7118 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7119 = and(_T_7117, _T_7118) @[ifu_mem_ctl.scala 693:122] + node _T_7120 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 694:37] + node _T_7121 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7122 = and(_T_7120, _T_7121) @[ifu_mem_ctl.scala 694:59] + node _T_7123 = eq(perr_ic_index_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 694:102] + node _T_7124 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7125 = and(_T_7123, _T_7124) @[ifu_mem_ctl.scala 694:124] + node _T_7126 = or(_T_7122, _T_7125) @[ifu_mem_ctl.scala 694:81] + node _T_7127 = or(_T_7126, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7128 = bits(_T_7127, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7129 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7128 : @[Reg.scala 28:19] _T_7129 <= _T_7119 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][67] <= _T_7129 @[ifu_mem_ctl.scala 685:41] - node _T_7130 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7131 = eq(_T_7130, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7132 = and(ic_valid_ff, _T_7131) @[ifu_mem_ctl.scala 685:97] - node _T_7133 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7134 = and(_T_7132, _T_7133) @[ifu_mem_ctl.scala 685:122] - node _T_7135 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 686:37] - node _T_7136 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7137 = and(_T_7135, _T_7136) @[ifu_mem_ctl.scala 686:59] - node _T_7138 = eq(perr_ic_index_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 686:102] - node _T_7139 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7140 = and(_T_7138, _T_7139) @[ifu_mem_ctl.scala 686:124] - node _T_7141 = or(_T_7137, _T_7140) @[ifu_mem_ctl.scala 686:81] - node _T_7142 = or(_T_7141, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7143 = bits(_T_7142, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][67] <= _T_7129 @[ifu_mem_ctl.scala 693:41] + node _T_7130 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7131 = eq(_T_7130, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7132 = and(ic_valid_ff, _T_7131) @[ifu_mem_ctl.scala 693:97] + node _T_7133 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7134 = and(_T_7132, _T_7133) @[ifu_mem_ctl.scala 693:122] + node _T_7135 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 694:37] + node _T_7136 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7137 = and(_T_7135, _T_7136) @[ifu_mem_ctl.scala 694:59] + node _T_7138 = eq(perr_ic_index_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 694:102] + node _T_7139 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7140 = and(_T_7138, _T_7139) @[ifu_mem_ctl.scala 694:124] + node _T_7141 = or(_T_7137, _T_7140) @[ifu_mem_ctl.scala 694:81] + node _T_7142 = or(_T_7141, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7143 = bits(_T_7142, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7144 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7143 : @[Reg.scala 28:19] _T_7144 <= _T_7134 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][68] <= _T_7144 @[ifu_mem_ctl.scala 685:41] - node _T_7145 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7146 = eq(_T_7145, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7147 = and(ic_valid_ff, _T_7146) @[ifu_mem_ctl.scala 685:97] - node _T_7148 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7149 = and(_T_7147, _T_7148) @[ifu_mem_ctl.scala 685:122] - node _T_7150 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 686:37] - node _T_7151 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7152 = and(_T_7150, _T_7151) @[ifu_mem_ctl.scala 686:59] - node _T_7153 = eq(perr_ic_index_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 686:102] - node _T_7154 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7155 = and(_T_7153, _T_7154) @[ifu_mem_ctl.scala 686:124] - node _T_7156 = or(_T_7152, _T_7155) @[ifu_mem_ctl.scala 686:81] - node _T_7157 = or(_T_7156, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7158 = bits(_T_7157, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][68] <= _T_7144 @[ifu_mem_ctl.scala 693:41] + node _T_7145 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7146 = eq(_T_7145, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7147 = and(ic_valid_ff, _T_7146) @[ifu_mem_ctl.scala 693:97] + node _T_7148 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7149 = and(_T_7147, _T_7148) @[ifu_mem_ctl.scala 693:122] + node _T_7150 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 694:37] + node _T_7151 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7152 = and(_T_7150, _T_7151) @[ifu_mem_ctl.scala 694:59] + node _T_7153 = eq(perr_ic_index_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 694:102] + node _T_7154 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7155 = and(_T_7153, _T_7154) @[ifu_mem_ctl.scala 694:124] + node _T_7156 = or(_T_7152, _T_7155) @[ifu_mem_ctl.scala 694:81] + node _T_7157 = or(_T_7156, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7158 = bits(_T_7157, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7159 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7158 : @[Reg.scala 28:19] _T_7159 <= _T_7149 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][69] <= _T_7159 @[ifu_mem_ctl.scala 685:41] - node _T_7160 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7161 = eq(_T_7160, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7162 = and(ic_valid_ff, _T_7161) @[ifu_mem_ctl.scala 685:97] - node _T_7163 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7164 = and(_T_7162, _T_7163) @[ifu_mem_ctl.scala 685:122] - node _T_7165 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 686:37] - node _T_7166 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7167 = and(_T_7165, _T_7166) @[ifu_mem_ctl.scala 686:59] - node _T_7168 = eq(perr_ic_index_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 686:102] - node _T_7169 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7170 = and(_T_7168, _T_7169) @[ifu_mem_ctl.scala 686:124] - node _T_7171 = or(_T_7167, _T_7170) @[ifu_mem_ctl.scala 686:81] - node _T_7172 = or(_T_7171, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7173 = bits(_T_7172, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][69] <= _T_7159 @[ifu_mem_ctl.scala 693:41] + node _T_7160 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7161 = eq(_T_7160, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7162 = and(ic_valid_ff, _T_7161) @[ifu_mem_ctl.scala 693:97] + node _T_7163 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7164 = and(_T_7162, _T_7163) @[ifu_mem_ctl.scala 693:122] + node _T_7165 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 694:37] + node _T_7166 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7167 = and(_T_7165, _T_7166) @[ifu_mem_ctl.scala 694:59] + node _T_7168 = eq(perr_ic_index_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 694:102] + node _T_7169 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7170 = and(_T_7168, _T_7169) @[ifu_mem_ctl.scala 694:124] + node _T_7171 = or(_T_7167, _T_7170) @[ifu_mem_ctl.scala 694:81] + node _T_7172 = or(_T_7171, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7173 = bits(_T_7172, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7174 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7173 : @[Reg.scala 28:19] _T_7174 <= _T_7164 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][70] <= _T_7174 @[ifu_mem_ctl.scala 685:41] - node _T_7175 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7176 = eq(_T_7175, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7177 = and(ic_valid_ff, _T_7176) @[ifu_mem_ctl.scala 685:97] - node _T_7178 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7179 = and(_T_7177, _T_7178) @[ifu_mem_ctl.scala 685:122] - node _T_7180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 686:37] - node _T_7181 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7182 = and(_T_7180, _T_7181) @[ifu_mem_ctl.scala 686:59] - node _T_7183 = eq(perr_ic_index_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 686:102] - node _T_7184 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7185 = and(_T_7183, _T_7184) @[ifu_mem_ctl.scala 686:124] - node _T_7186 = or(_T_7182, _T_7185) @[ifu_mem_ctl.scala 686:81] - node _T_7187 = or(_T_7186, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7188 = bits(_T_7187, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][70] <= _T_7174 @[ifu_mem_ctl.scala 693:41] + node _T_7175 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7176 = eq(_T_7175, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7177 = and(ic_valid_ff, _T_7176) @[ifu_mem_ctl.scala 693:97] + node _T_7178 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7179 = and(_T_7177, _T_7178) @[ifu_mem_ctl.scala 693:122] + node _T_7180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 694:37] + node _T_7181 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7182 = and(_T_7180, _T_7181) @[ifu_mem_ctl.scala 694:59] + node _T_7183 = eq(perr_ic_index_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 694:102] + node _T_7184 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7185 = and(_T_7183, _T_7184) @[ifu_mem_ctl.scala 694:124] + node _T_7186 = or(_T_7182, _T_7185) @[ifu_mem_ctl.scala 694:81] + node _T_7187 = or(_T_7186, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7188 = bits(_T_7187, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7189 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7188 : @[Reg.scala 28:19] _T_7189 <= _T_7179 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][71] <= _T_7189 @[ifu_mem_ctl.scala 685:41] - node _T_7190 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7191 = eq(_T_7190, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7192 = and(ic_valid_ff, _T_7191) @[ifu_mem_ctl.scala 685:97] - node _T_7193 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7194 = and(_T_7192, _T_7193) @[ifu_mem_ctl.scala 685:122] - node _T_7195 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 686:37] - node _T_7196 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7197 = and(_T_7195, _T_7196) @[ifu_mem_ctl.scala 686:59] - node _T_7198 = eq(perr_ic_index_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 686:102] - node _T_7199 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7200 = and(_T_7198, _T_7199) @[ifu_mem_ctl.scala 686:124] - node _T_7201 = or(_T_7197, _T_7200) @[ifu_mem_ctl.scala 686:81] - node _T_7202 = or(_T_7201, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7203 = bits(_T_7202, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][71] <= _T_7189 @[ifu_mem_ctl.scala 693:41] + node _T_7190 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7191 = eq(_T_7190, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7192 = and(ic_valid_ff, _T_7191) @[ifu_mem_ctl.scala 693:97] + node _T_7193 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7194 = and(_T_7192, _T_7193) @[ifu_mem_ctl.scala 693:122] + node _T_7195 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 694:37] + node _T_7196 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7197 = and(_T_7195, _T_7196) @[ifu_mem_ctl.scala 694:59] + node _T_7198 = eq(perr_ic_index_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 694:102] + node _T_7199 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7200 = and(_T_7198, _T_7199) @[ifu_mem_ctl.scala 694:124] + node _T_7201 = or(_T_7197, _T_7200) @[ifu_mem_ctl.scala 694:81] + node _T_7202 = or(_T_7201, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7203 = bits(_T_7202, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7204 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7203 : @[Reg.scala 28:19] _T_7204 <= _T_7194 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][72] <= _T_7204 @[ifu_mem_ctl.scala 685:41] - node _T_7205 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7206 = eq(_T_7205, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7207 = and(ic_valid_ff, _T_7206) @[ifu_mem_ctl.scala 685:97] - node _T_7208 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7209 = and(_T_7207, _T_7208) @[ifu_mem_ctl.scala 685:122] - node _T_7210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 686:37] - node _T_7211 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7212 = and(_T_7210, _T_7211) @[ifu_mem_ctl.scala 686:59] - node _T_7213 = eq(perr_ic_index_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 686:102] - node _T_7214 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7215 = and(_T_7213, _T_7214) @[ifu_mem_ctl.scala 686:124] - node _T_7216 = or(_T_7212, _T_7215) @[ifu_mem_ctl.scala 686:81] - node _T_7217 = or(_T_7216, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7218 = bits(_T_7217, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][72] <= _T_7204 @[ifu_mem_ctl.scala 693:41] + node _T_7205 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7206 = eq(_T_7205, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7207 = and(ic_valid_ff, _T_7206) @[ifu_mem_ctl.scala 693:97] + node _T_7208 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7209 = and(_T_7207, _T_7208) @[ifu_mem_ctl.scala 693:122] + node _T_7210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 694:37] + node _T_7211 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7212 = and(_T_7210, _T_7211) @[ifu_mem_ctl.scala 694:59] + node _T_7213 = eq(perr_ic_index_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 694:102] + node _T_7214 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7215 = and(_T_7213, _T_7214) @[ifu_mem_ctl.scala 694:124] + node _T_7216 = or(_T_7212, _T_7215) @[ifu_mem_ctl.scala 694:81] + node _T_7217 = or(_T_7216, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7218 = bits(_T_7217, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7219 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7218 : @[Reg.scala 28:19] _T_7219 <= _T_7209 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][73] <= _T_7219 @[ifu_mem_ctl.scala 685:41] - node _T_7220 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7221 = eq(_T_7220, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7222 = and(ic_valid_ff, _T_7221) @[ifu_mem_ctl.scala 685:97] - node _T_7223 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7224 = and(_T_7222, _T_7223) @[ifu_mem_ctl.scala 685:122] - node _T_7225 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 686:37] - node _T_7226 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7227 = and(_T_7225, _T_7226) @[ifu_mem_ctl.scala 686:59] - node _T_7228 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 686:102] - node _T_7229 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7230 = and(_T_7228, _T_7229) @[ifu_mem_ctl.scala 686:124] - node _T_7231 = or(_T_7227, _T_7230) @[ifu_mem_ctl.scala 686:81] - node _T_7232 = or(_T_7231, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7233 = bits(_T_7232, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][73] <= _T_7219 @[ifu_mem_ctl.scala 693:41] + node _T_7220 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7221 = eq(_T_7220, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7222 = and(ic_valid_ff, _T_7221) @[ifu_mem_ctl.scala 693:97] + node _T_7223 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7224 = and(_T_7222, _T_7223) @[ifu_mem_ctl.scala 693:122] + node _T_7225 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 694:37] + node _T_7226 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7227 = and(_T_7225, _T_7226) @[ifu_mem_ctl.scala 694:59] + node _T_7228 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 694:102] + node _T_7229 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7230 = and(_T_7228, _T_7229) @[ifu_mem_ctl.scala 694:124] + node _T_7231 = or(_T_7227, _T_7230) @[ifu_mem_ctl.scala 694:81] + node _T_7232 = or(_T_7231, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7233 = bits(_T_7232, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7234 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7233 : @[Reg.scala 28:19] _T_7234 <= _T_7224 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][74] <= _T_7234 @[ifu_mem_ctl.scala 685:41] - node _T_7235 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7236 = eq(_T_7235, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7237 = and(ic_valid_ff, _T_7236) @[ifu_mem_ctl.scala 685:97] - node _T_7238 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7239 = and(_T_7237, _T_7238) @[ifu_mem_ctl.scala 685:122] - node _T_7240 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 686:37] - node _T_7241 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7242 = and(_T_7240, _T_7241) @[ifu_mem_ctl.scala 686:59] - node _T_7243 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 686:102] - node _T_7244 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7245 = and(_T_7243, _T_7244) @[ifu_mem_ctl.scala 686:124] - node _T_7246 = or(_T_7242, _T_7245) @[ifu_mem_ctl.scala 686:81] - node _T_7247 = or(_T_7246, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7248 = bits(_T_7247, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][74] <= _T_7234 @[ifu_mem_ctl.scala 693:41] + node _T_7235 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7236 = eq(_T_7235, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7237 = and(ic_valid_ff, _T_7236) @[ifu_mem_ctl.scala 693:97] + node _T_7238 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7239 = and(_T_7237, _T_7238) @[ifu_mem_ctl.scala 693:122] + node _T_7240 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 694:37] + node _T_7241 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7242 = and(_T_7240, _T_7241) @[ifu_mem_ctl.scala 694:59] + node _T_7243 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 694:102] + node _T_7244 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7245 = and(_T_7243, _T_7244) @[ifu_mem_ctl.scala 694:124] + node _T_7246 = or(_T_7242, _T_7245) @[ifu_mem_ctl.scala 694:81] + node _T_7247 = or(_T_7246, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7248 = bits(_T_7247, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7249 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7248 : @[Reg.scala 28:19] _T_7249 <= _T_7239 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][75] <= _T_7249 @[ifu_mem_ctl.scala 685:41] - node _T_7250 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7251 = eq(_T_7250, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7252 = and(ic_valid_ff, _T_7251) @[ifu_mem_ctl.scala 685:97] - node _T_7253 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7254 = and(_T_7252, _T_7253) @[ifu_mem_ctl.scala 685:122] - node _T_7255 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 686:37] - node _T_7256 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7257 = and(_T_7255, _T_7256) @[ifu_mem_ctl.scala 686:59] - node _T_7258 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 686:102] - node _T_7259 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7260 = and(_T_7258, _T_7259) @[ifu_mem_ctl.scala 686:124] - node _T_7261 = or(_T_7257, _T_7260) @[ifu_mem_ctl.scala 686:81] - node _T_7262 = or(_T_7261, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7263 = bits(_T_7262, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][75] <= _T_7249 @[ifu_mem_ctl.scala 693:41] + node _T_7250 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7251 = eq(_T_7250, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7252 = and(ic_valid_ff, _T_7251) @[ifu_mem_ctl.scala 693:97] + node _T_7253 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7254 = and(_T_7252, _T_7253) @[ifu_mem_ctl.scala 693:122] + node _T_7255 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 694:37] + node _T_7256 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7257 = and(_T_7255, _T_7256) @[ifu_mem_ctl.scala 694:59] + node _T_7258 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 694:102] + node _T_7259 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7260 = and(_T_7258, _T_7259) @[ifu_mem_ctl.scala 694:124] + node _T_7261 = or(_T_7257, _T_7260) @[ifu_mem_ctl.scala 694:81] + node _T_7262 = or(_T_7261, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7263 = bits(_T_7262, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7264 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7263 : @[Reg.scala 28:19] _T_7264 <= _T_7254 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][76] <= _T_7264 @[ifu_mem_ctl.scala 685:41] - node _T_7265 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7266 = eq(_T_7265, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7267 = and(ic_valid_ff, _T_7266) @[ifu_mem_ctl.scala 685:97] - node _T_7268 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7269 = and(_T_7267, _T_7268) @[ifu_mem_ctl.scala 685:122] - node _T_7270 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 686:37] - node _T_7271 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7272 = and(_T_7270, _T_7271) @[ifu_mem_ctl.scala 686:59] - node _T_7273 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 686:102] - node _T_7274 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7275 = and(_T_7273, _T_7274) @[ifu_mem_ctl.scala 686:124] - node _T_7276 = or(_T_7272, _T_7275) @[ifu_mem_ctl.scala 686:81] - node _T_7277 = or(_T_7276, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7278 = bits(_T_7277, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][76] <= _T_7264 @[ifu_mem_ctl.scala 693:41] + node _T_7265 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7266 = eq(_T_7265, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7267 = and(ic_valid_ff, _T_7266) @[ifu_mem_ctl.scala 693:97] + node _T_7268 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7269 = and(_T_7267, _T_7268) @[ifu_mem_ctl.scala 693:122] + node _T_7270 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 694:37] + node _T_7271 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7272 = and(_T_7270, _T_7271) @[ifu_mem_ctl.scala 694:59] + node _T_7273 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 694:102] + node _T_7274 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7275 = and(_T_7273, _T_7274) @[ifu_mem_ctl.scala 694:124] + node _T_7276 = or(_T_7272, _T_7275) @[ifu_mem_ctl.scala 694:81] + node _T_7277 = or(_T_7276, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7278 = bits(_T_7277, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7279 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7278 : @[Reg.scala 28:19] _T_7279 <= _T_7269 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][77] <= _T_7279 @[ifu_mem_ctl.scala 685:41] - node _T_7280 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7281 = eq(_T_7280, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7282 = and(ic_valid_ff, _T_7281) @[ifu_mem_ctl.scala 685:97] - node _T_7283 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7284 = and(_T_7282, _T_7283) @[ifu_mem_ctl.scala 685:122] - node _T_7285 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 686:37] - node _T_7286 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7287 = and(_T_7285, _T_7286) @[ifu_mem_ctl.scala 686:59] - node _T_7288 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 686:102] - node _T_7289 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7290 = and(_T_7288, _T_7289) @[ifu_mem_ctl.scala 686:124] - node _T_7291 = or(_T_7287, _T_7290) @[ifu_mem_ctl.scala 686:81] - node _T_7292 = or(_T_7291, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7293 = bits(_T_7292, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][77] <= _T_7279 @[ifu_mem_ctl.scala 693:41] + node _T_7280 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7281 = eq(_T_7280, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7282 = and(ic_valid_ff, _T_7281) @[ifu_mem_ctl.scala 693:97] + node _T_7283 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7284 = and(_T_7282, _T_7283) @[ifu_mem_ctl.scala 693:122] + node _T_7285 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 694:37] + node _T_7286 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7287 = and(_T_7285, _T_7286) @[ifu_mem_ctl.scala 694:59] + node _T_7288 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 694:102] + node _T_7289 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7290 = and(_T_7288, _T_7289) @[ifu_mem_ctl.scala 694:124] + node _T_7291 = or(_T_7287, _T_7290) @[ifu_mem_ctl.scala 694:81] + node _T_7292 = or(_T_7291, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7293 = bits(_T_7292, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7294 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7293 : @[Reg.scala 28:19] _T_7294 <= _T_7284 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][78] <= _T_7294 @[ifu_mem_ctl.scala 685:41] - node _T_7295 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7296 = eq(_T_7295, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7297 = and(ic_valid_ff, _T_7296) @[ifu_mem_ctl.scala 685:97] - node _T_7298 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7299 = and(_T_7297, _T_7298) @[ifu_mem_ctl.scala 685:122] - node _T_7300 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 686:37] - node _T_7301 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7302 = and(_T_7300, _T_7301) @[ifu_mem_ctl.scala 686:59] - node _T_7303 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 686:102] - node _T_7304 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7305 = and(_T_7303, _T_7304) @[ifu_mem_ctl.scala 686:124] - node _T_7306 = or(_T_7302, _T_7305) @[ifu_mem_ctl.scala 686:81] - node _T_7307 = or(_T_7306, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7308 = bits(_T_7307, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][78] <= _T_7294 @[ifu_mem_ctl.scala 693:41] + node _T_7295 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7296 = eq(_T_7295, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7297 = and(ic_valid_ff, _T_7296) @[ifu_mem_ctl.scala 693:97] + node _T_7298 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7299 = and(_T_7297, _T_7298) @[ifu_mem_ctl.scala 693:122] + node _T_7300 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 694:37] + node _T_7301 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7302 = and(_T_7300, _T_7301) @[ifu_mem_ctl.scala 694:59] + node _T_7303 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 694:102] + node _T_7304 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7305 = and(_T_7303, _T_7304) @[ifu_mem_ctl.scala 694:124] + node _T_7306 = or(_T_7302, _T_7305) @[ifu_mem_ctl.scala 694:81] + node _T_7307 = or(_T_7306, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7308 = bits(_T_7307, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7309 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7308 : @[Reg.scala 28:19] _T_7309 <= _T_7299 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][79] <= _T_7309 @[ifu_mem_ctl.scala 685:41] - node _T_7310 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7311 = eq(_T_7310, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7312 = and(ic_valid_ff, _T_7311) @[ifu_mem_ctl.scala 685:97] - node _T_7313 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7314 = and(_T_7312, _T_7313) @[ifu_mem_ctl.scala 685:122] - node _T_7315 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 686:37] - node _T_7316 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7317 = and(_T_7315, _T_7316) @[ifu_mem_ctl.scala 686:59] - node _T_7318 = eq(perr_ic_index_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 686:102] - node _T_7319 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7320 = and(_T_7318, _T_7319) @[ifu_mem_ctl.scala 686:124] - node _T_7321 = or(_T_7317, _T_7320) @[ifu_mem_ctl.scala 686:81] - node _T_7322 = or(_T_7321, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7323 = bits(_T_7322, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][79] <= _T_7309 @[ifu_mem_ctl.scala 693:41] + node _T_7310 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7311 = eq(_T_7310, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7312 = and(ic_valid_ff, _T_7311) @[ifu_mem_ctl.scala 693:97] + node _T_7313 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7314 = and(_T_7312, _T_7313) @[ifu_mem_ctl.scala 693:122] + node _T_7315 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 694:37] + node _T_7316 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7317 = and(_T_7315, _T_7316) @[ifu_mem_ctl.scala 694:59] + node _T_7318 = eq(perr_ic_index_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 694:102] + node _T_7319 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7320 = and(_T_7318, _T_7319) @[ifu_mem_ctl.scala 694:124] + node _T_7321 = or(_T_7317, _T_7320) @[ifu_mem_ctl.scala 694:81] + node _T_7322 = or(_T_7321, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7323 = bits(_T_7322, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7324 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7323 : @[Reg.scala 28:19] _T_7324 <= _T_7314 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][80] <= _T_7324 @[ifu_mem_ctl.scala 685:41] - node _T_7325 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7326 = eq(_T_7325, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7327 = and(ic_valid_ff, _T_7326) @[ifu_mem_ctl.scala 685:97] - node _T_7328 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7329 = and(_T_7327, _T_7328) @[ifu_mem_ctl.scala 685:122] - node _T_7330 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 686:37] - node _T_7331 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7332 = and(_T_7330, _T_7331) @[ifu_mem_ctl.scala 686:59] - node _T_7333 = eq(perr_ic_index_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 686:102] - node _T_7334 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7335 = and(_T_7333, _T_7334) @[ifu_mem_ctl.scala 686:124] - node _T_7336 = or(_T_7332, _T_7335) @[ifu_mem_ctl.scala 686:81] - node _T_7337 = or(_T_7336, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7338 = bits(_T_7337, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][80] <= _T_7324 @[ifu_mem_ctl.scala 693:41] + node _T_7325 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7326 = eq(_T_7325, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7327 = and(ic_valid_ff, _T_7326) @[ifu_mem_ctl.scala 693:97] + node _T_7328 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7329 = and(_T_7327, _T_7328) @[ifu_mem_ctl.scala 693:122] + node _T_7330 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 694:37] + node _T_7331 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7332 = and(_T_7330, _T_7331) @[ifu_mem_ctl.scala 694:59] + node _T_7333 = eq(perr_ic_index_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 694:102] + node _T_7334 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7335 = and(_T_7333, _T_7334) @[ifu_mem_ctl.scala 694:124] + node _T_7336 = or(_T_7332, _T_7335) @[ifu_mem_ctl.scala 694:81] + node _T_7337 = or(_T_7336, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7338 = bits(_T_7337, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7339 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7338 : @[Reg.scala 28:19] _T_7339 <= _T_7329 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][81] <= _T_7339 @[ifu_mem_ctl.scala 685:41] - node _T_7340 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7341 = eq(_T_7340, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7342 = and(ic_valid_ff, _T_7341) @[ifu_mem_ctl.scala 685:97] - node _T_7343 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7344 = and(_T_7342, _T_7343) @[ifu_mem_ctl.scala 685:122] - node _T_7345 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 686:37] - node _T_7346 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7347 = and(_T_7345, _T_7346) @[ifu_mem_ctl.scala 686:59] - node _T_7348 = eq(perr_ic_index_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 686:102] - node _T_7349 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7350 = and(_T_7348, _T_7349) @[ifu_mem_ctl.scala 686:124] - node _T_7351 = or(_T_7347, _T_7350) @[ifu_mem_ctl.scala 686:81] - node _T_7352 = or(_T_7351, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7353 = bits(_T_7352, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][81] <= _T_7339 @[ifu_mem_ctl.scala 693:41] + node _T_7340 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7341 = eq(_T_7340, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7342 = and(ic_valid_ff, _T_7341) @[ifu_mem_ctl.scala 693:97] + node _T_7343 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7344 = and(_T_7342, _T_7343) @[ifu_mem_ctl.scala 693:122] + node _T_7345 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 694:37] + node _T_7346 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7347 = and(_T_7345, _T_7346) @[ifu_mem_ctl.scala 694:59] + node _T_7348 = eq(perr_ic_index_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 694:102] + node _T_7349 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7350 = and(_T_7348, _T_7349) @[ifu_mem_ctl.scala 694:124] + node _T_7351 = or(_T_7347, _T_7350) @[ifu_mem_ctl.scala 694:81] + node _T_7352 = or(_T_7351, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7353 = bits(_T_7352, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7354 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7353 : @[Reg.scala 28:19] _T_7354 <= _T_7344 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][82] <= _T_7354 @[ifu_mem_ctl.scala 685:41] - node _T_7355 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7356 = eq(_T_7355, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7357 = and(ic_valid_ff, _T_7356) @[ifu_mem_ctl.scala 685:97] - node _T_7358 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7359 = and(_T_7357, _T_7358) @[ifu_mem_ctl.scala 685:122] - node _T_7360 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 686:37] - node _T_7361 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7362 = and(_T_7360, _T_7361) @[ifu_mem_ctl.scala 686:59] - node _T_7363 = eq(perr_ic_index_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 686:102] - node _T_7364 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7365 = and(_T_7363, _T_7364) @[ifu_mem_ctl.scala 686:124] - node _T_7366 = or(_T_7362, _T_7365) @[ifu_mem_ctl.scala 686:81] - node _T_7367 = or(_T_7366, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7368 = bits(_T_7367, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][82] <= _T_7354 @[ifu_mem_ctl.scala 693:41] + node _T_7355 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7356 = eq(_T_7355, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7357 = and(ic_valid_ff, _T_7356) @[ifu_mem_ctl.scala 693:97] + node _T_7358 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7359 = and(_T_7357, _T_7358) @[ifu_mem_ctl.scala 693:122] + node _T_7360 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 694:37] + node _T_7361 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7362 = and(_T_7360, _T_7361) @[ifu_mem_ctl.scala 694:59] + node _T_7363 = eq(perr_ic_index_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 694:102] + node _T_7364 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7365 = and(_T_7363, _T_7364) @[ifu_mem_ctl.scala 694:124] + node _T_7366 = or(_T_7362, _T_7365) @[ifu_mem_ctl.scala 694:81] + node _T_7367 = or(_T_7366, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7368 = bits(_T_7367, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7369 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7368 : @[Reg.scala 28:19] _T_7369 <= _T_7359 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][83] <= _T_7369 @[ifu_mem_ctl.scala 685:41] - node _T_7370 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7371 = eq(_T_7370, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7372 = and(ic_valid_ff, _T_7371) @[ifu_mem_ctl.scala 685:97] - node _T_7373 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7374 = and(_T_7372, _T_7373) @[ifu_mem_ctl.scala 685:122] - node _T_7375 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 686:37] - node _T_7376 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7377 = and(_T_7375, _T_7376) @[ifu_mem_ctl.scala 686:59] - node _T_7378 = eq(perr_ic_index_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 686:102] - node _T_7379 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7380 = and(_T_7378, _T_7379) @[ifu_mem_ctl.scala 686:124] - node _T_7381 = or(_T_7377, _T_7380) @[ifu_mem_ctl.scala 686:81] - node _T_7382 = or(_T_7381, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7383 = bits(_T_7382, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][83] <= _T_7369 @[ifu_mem_ctl.scala 693:41] + node _T_7370 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7371 = eq(_T_7370, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7372 = and(ic_valid_ff, _T_7371) @[ifu_mem_ctl.scala 693:97] + node _T_7373 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7374 = and(_T_7372, _T_7373) @[ifu_mem_ctl.scala 693:122] + node _T_7375 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 694:37] + node _T_7376 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7377 = and(_T_7375, _T_7376) @[ifu_mem_ctl.scala 694:59] + node _T_7378 = eq(perr_ic_index_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 694:102] + node _T_7379 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7380 = and(_T_7378, _T_7379) @[ifu_mem_ctl.scala 694:124] + node _T_7381 = or(_T_7377, _T_7380) @[ifu_mem_ctl.scala 694:81] + node _T_7382 = or(_T_7381, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7383 = bits(_T_7382, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7384 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7383 : @[Reg.scala 28:19] _T_7384 <= _T_7374 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][84] <= _T_7384 @[ifu_mem_ctl.scala 685:41] - node _T_7385 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7386 = eq(_T_7385, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7387 = and(ic_valid_ff, _T_7386) @[ifu_mem_ctl.scala 685:97] - node _T_7388 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7389 = and(_T_7387, _T_7388) @[ifu_mem_ctl.scala 685:122] - node _T_7390 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 686:37] - node _T_7391 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7392 = and(_T_7390, _T_7391) @[ifu_mem_ctl.scala 686:59] - node _T_7393 = eq(perr_ic_index_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 686:102] - node _T_7394 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7395 = and(_T_7393, _T_7394) @[ifu_mem_ctl.scala 686:124] - node _T_7396 = or(_T_7392, _T_7395) @[ifu_mem_ctl.scala 686:81] - node _T_7397 = or(_T_7396, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7398 = bits(_T_7397, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][84] <= _T_7384 @[ifu_mem_ctl.scala 693:41] + node _T_7385 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7386 = eq(_T_7385, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7387 = and(ic_valid_ff, _T_7386) @[ifu_mem_ctl.scala 693:97] + node _T_7388 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7389 = and(_T_7387, _T_7388) @[ifu_mem_ctl.scala 693:122] + node _T_7390 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 694:37] + node _T_7391 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7392 = and(_T_7390, _T_7391) @[ifu_mem_ctl.scala 694:59] + node _T_7393 = eq(perr_ic_index_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 694:102] + node _T_7394 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7395 = and(_T_7393, _T_7394) @[ifu_mem_ctl.scala 694:124] + node _T_7396 = or(_T_7392, _T_7395) @[ifu_mem_ctl.scala 694:81] + node _T_7397 = or(_T_7396, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7398 = bits(_T_7397, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7399 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7398 : @[Reg.scala 28:19] _T_7399 <= _T_7389 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][85] <= _T_7399 @[ifu_mem_ctl.scala 685:41] - node _T_7400 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7401 = eq(_T_7400, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7402 = and(ic_valid_ff, _T_7401) @[ifu_mem_ctl.scala 685:97] - node _T_7403 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7404 = and(_T_7402, _T_7403) @[ifu_mem_ctl.scala 685:122] - node _T_7405 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 686:37] - node _T_7406 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7407 = and(_T_7405, _T_7406) @[ifu_mem_ctl.scala 686:59] - node _T_7408 = eq(perr_ic_index_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 686:102] - node _T_7409 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7410 = and(_T_7408, _T_7409) @[ifu_mem_ctl.scala 686:124] - node _T_7411 = or(_T_7407, _T_7410) @[ifu_mem_ctl.scala 686:81] - node _T_7412 = or(_T_7411, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7413 = bits(_T_7412, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][85] <= _T_7399 @[ifu_mem_ctl.scala 693:41] + node _T_7400 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7401 = eq(_T_7400, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7402 = and(ic_valid_ff, _T_7401) @[ifu_mem_ctl.scala 693:97] + node _T_7403 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7404 = and(_T_7402, _T_7403) @[ifu_mem_ctl.scala 693:122] + node _T_7405 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 694:37] + node _T_7406 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7407 = and(_T_7405, _T_7406) @[ifu_mem_ctl.scala 694:59] + node _T_7408 = eq(perr_ic_index_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 694:102] + node _T_7409 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7410 = and(_T_7408, _T_7409) @[ifu_mem_ctl.scala 694:124] + node _T_7411 = or(_T_7407, _T_7410) @[ifu_mem_ctl.scala 694:81] + node _T_7412 = or(_T_7411, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7413 = bits(_T_7412, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7414 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7413 : @[Reg.scala 28:19] _T_7414 <= _T_7404 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][86] <= _T_7414 @[ifu_mem_ctl.scala 685:41] - node _T_7415 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7416 = eq(_T_7415, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7417 = and(ic_valid_ff, _T_7416) @[ifu_mem_ctl.scala 685:97] - node _T_7418 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7419 = and(_T_7417, _T_7418) @[ifu_mem_ctl.scala 685:122] - node _T_7420 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 686:37] - node _T_7421 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7422 = and(_T_7420, _T_7421) @[ifu_mem_ctl.scala 686:59] - node _T_7423 = eq(perr_ic_index_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 686:102] - node _T_7424 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7425 = and(_T_7423, _T_7424) @[ifu_mem_ctl.scala 686:124] - node _T_7426 = or(_T_7422, _T_7425) @[ifu_mem_ctl.scala 686:81] - node _T_7427 = or(_T_7426, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7428 = bits(_T_7427, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][86] <= _T_7414 @[ifu_mem_ctl.scala 693:41] + node _T_7415 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7416 = eq(_T_7415, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7417 = and(ic_valid_ff, _T_7416) @[ifu_mem_ctl.scala 693:97] + node _T_7418 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7419 = and(_T_7417, _T_7418) @[ifu_mem_ctl.scala 693:122] + node _T_7420 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 694:37] + node _T_7421 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7422 = and(_T_7420, _T_7421) @[ifu_mem_ctl.scala 694:59] + node _T_7423 = eq(perr_ic_index_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 694:102] + node _T_7424 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7425 = and(_T_7423, _T_7424) @[ifu_mem_ctl.scala 694:124] + node _T_7426 = or(_T_7422, _T_7425) @[ifu_mem_ctl.scala 694:81] + node _T_7427 = or(_T_7426, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7428 = bits(_T_7427, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7429 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7428 : @[Reg.scala 28:19] _T_7429 <= _T_7419 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][87] <= _T_7429 @[ifu_mem_ctl.scala 685:41] - node _T_7430 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7431 = eq(_T_7430, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7432 = and(ic_valid_ff, _T_7431) @[ifu_mem_ctl.scala 685:97] - node _T_7433 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7434 = and(_T_7432, _T_7433) @[ifu_mem_ctl.scala 685:122] - node _T_7435 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 686:37] - node _T_7436 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7437 = and(_T_7435, _T_7436) @[ifu_mem_ctl.scala 686:59] - node _T_7438 = eq(perr_ic_index_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 686:102] - node _T_7439 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7440 = and(_T_7438, _T_7439) @[ifu_mem_ctl.scala 686:124] - node _T_7441 = or(_T_7437, _T_7440) @[ifu_mem_ctl.scala 686:81] - node _T_7442 = or(_T_7441, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7443 = bits(_T_7442, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][87] <= _T_7429 @[ifu_mem_ctl.scala 693:41] + node _T_7430 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7431 = eq(_T_7430, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7432 = and(ic_valid_ff, _T_7431) @[ifu_mem_ctl.scala 693:97] + node _T_7433 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7434 = and(_T_7432, _T_7433) @[ifu_mem_ctl.scala 693:122] + node _T_7435 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 694:37] + node _T_7436 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7437 = and(_T_7435, _T_7436) @[ifu_mem_ctl.scala 694:59] + node _T_7438 = eq(perr_ic_index_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 694:102] + node _T_7439 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7440 = and(_T_7438, _T_7439) @[ifu_mem_ctl.scala 694:124] + node _T_7441 = or(_T_7437, _T_7440) @[ifu_mem_ctl.scala 694:81] + node _T_7442 = or(_T_7441, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7443 = bits(_T_7442, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7444 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7443 : @[Reg.scala 28:19] _T_7444 <= _T_7434 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][88] <= _T_7444 @[ifu_mem_ctl.scala 685:41] - node _T_7445 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7446 = eq(_T_7445, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7447 = and(ic_valid_ff, _T_7446) @[ifu_mem_ctl.scala 685:97] - node _T_7448 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7449 = and(_T_7447, _T_7448) @[ifu_mem_ctl.scala 685:122] - node _T_7450 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 686:37] - node _T_7451 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7452 = and(_T_7450, _T_7451) @[ifu_mem_ctl.scala 686:59] - node _T_7453 = eq(perr_ic_index_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 686:102] - node _T_7454 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7455 = and(_T_7453, _T_7454) @[ifu_mem_ctl.scala 686:124] - node _T_7456 = or(_T_7452, _T_7455) @[ifu_mem_ctl.scala 686:81] - node _T_7457 = or(_T_7456, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7458 = bits(_T_7457, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][88] <= _T_7444 @[ifu_mem_ctl.scala 693:41] + node _T_7445 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7446 = eq(_T_7445, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7447 = and(ic_valid_ff, _T_7446) @[ifu_mem_ctl.scala 693:97] + node _T_7448 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7449 = and(_T_7447, _T_7448) @[ifu_mem_ctl.scala 693:122] + node _T_7450 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 694:37] + node _T_7451 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7452 = and(_T_7450, _T_7451) @[ifu_mem_ctl.scala 694:59] + node _T_7453 = eq(perr_ic_index_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 694:102] + node _T_7454 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7455 = and(_T_7453, _T_7454) @[ifu_mem_ctl.scala 694:124] + node _T_7456 = or(_T_7452, _T_7455) @[ifu_mem_ctl.scala 694:81] + node _T_7457 = or(_T_7456, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7458 = bits(_T_7457, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7459 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7458 : @[Reg.scala 28:19] _T_7459 <= _T_7449 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][89] <= _T_7459 @[ifu_mem_ctl.scala 685:41] - node _T_7460 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7461 = eq(_T_7460, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7462 = and(ic_valid_ff, _T_7461) @[ifu_mem_ctl.scala 685:97] - node _T_7463 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7464 = and(_T_7462, _T_7463) @[ifu_mem_ctl.scala 685:122] - node _T_7465 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 686:37] - node _T_7466 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7467 = and(_T_7465, _T_7466) @[ifu_mem_ctl.scala 686:59] - node _T_7468 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 686:102] - node _T_7469 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7470 = and(_T_7468, _T_7469) @[ifu_mem_ctl.scala 686:124] - node _T_7471 = or(_T_7467, _T_7470) @[ifu_mem_ctl.scala 686:81] - node _T_7472 = or(_T_7471, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7473 = bits(_T_7472, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][89] <= _T_7459 @[ifu_mem_ctl.scala 693:41] + node _T_7460 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7461 = eq(_T_7460, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7462 = and(ic_valid_ff, _T_7461) @[ifu_mem_ctl.scala 693:97] + node _T_7463 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7464 = and(_T_7462, _T_7463) @[ifu_mem_ctl.scala 693:122] + node _T_7465 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 694:37] + node _T_7466 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7467 = and(_T_7465, _T_7466) @[ifu_mem_ctl.scala 694:59] + node _T_7468 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 694:102] + node _T_7469 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7470 = and(_T_7468, _T_7469) @[ifu_mem_ctl.scala 694:124] + node _T_7471 = or(_T_7467, _T_7470) @[ifu_mem_ctl.scala 694:81] + node _T_7472 = or(_T_7471, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7473 = bits(_T_7472, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7474 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7473 : @[Reg.scala 28:19] _T_7474 <= _T_7464 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][90] <= _T_7474 @[ifu_mem_ctl.scala 685:41] - node _T_7475 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7476 = eq(_T_7475, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7477 = and(ic_valid_ff, _T_7476) @[ifu_mem_ctl.scala 685:97] - node _T_7478 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7479 = and(_T_7477, _T_7478) @[ifu_mem_ctl.scala 685:122] - node _T_7480 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 686:37] - node _T_7481 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7482 = and(_T_7480, _T_7481) @[ifu_mem_ctl.scala 686:59] - node _T_7483 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 686:102] - node _T_7484 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7485 = and(_T_7483, _T_7484) @[ifu_mem_ctl.scala 686:124] - node _T_7486 = or(_T_7482, _T_7485) @[ifu_mem_ctl.scala 686:81] - node _T_7487 = or(_T_7486, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7488 = bits(_T_7487, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][90] <= _T_7474 @[ifu_mem_ctl.scala 693:41] + node _T_7475 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7476 = eq(_T_7475, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7477 = and(ic_valid_ff, _T_7476) @[ifu_mem_ctl.scala 693:97] + node _T_7478 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7479 = and(_T_7477, _T_7478) @[ifu_mem_ctl.scala 693:122] + node _T_7480 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 694:37] + node _T_7481 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7482 = and(_T_7480, _T_7481) @[ifu_mem_ctl.scala 694:59] + node _T_7483 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 694:102] + node _T_7484 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7485 = and(_T_7483, _T_7484) @[ifu_mem_ctl.scala 694:124] + node _T_7486 = or(_T_7482, _T_7485) @[ifu_mem_ctl.scala 694:81] + node _T_7487 = or(_T_7486, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7488 = bits(_T_7487, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7489 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7488 : @[Reg.scala 28:19] _T_7489 <= _T_7479 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][91] <= _T_7489 @[ifu_mem_ctl.scala 685:41] - node _T_7490 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7491 = eq(_T_7490, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7492 = and(ic_valid_ff, _T_7491) @[ifu_mem_ctl.scala 685:97] - node _T_7493 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7494 = and(_T_7492, _T_7493) @[ifu_mem_ctl.scala 685:122] - node _T_7495 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 686:37] - node _T_7496 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7497 = and(_T_7495, _T_7496) @[ifu_mem_ctl.scala 686:59] - node _T_7498 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 686:102] - node _T_7499 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7500 = and(_T_7498, _T_7499) @[ifu_mem_ctl.scala 686:124] - node _T_7501 = or(_T_7497, _T_7500) @[ifu_mem_ctl.scala 686:81] - node _T_7502 = or(_T_7501, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7503 = bits(_T_7502, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][91] <= _T_7489 @[ifu_mem_ctl.scala 693:41] + node _T_7490 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7491 = eq(_T_7490, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7492 = and(ic_valid_ff, _T_7491) @[ifu_mem_ctl.scala 693:97] + node _T_7493 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7494 = and(_T_7492, _T_7493) @[ifu_mem_ctl.scala 693:122] + node _T_7495 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 694:37] + node _T_7496 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7497 = and(_T_7495, _T_7496) @[ifu_mem_ctl.scala 694:59] + node _T_7498 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 694:102] + node _T_7499 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7500 = and(_T_7498, _T_7499) @[ifu_mem_ctl.scala 694:124] + node _T_7501 = or(_T_7497, _T_7500) @[ifu_mem_ctl.scala 694:81] + node _T_7502 = or(_T_7501, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7503 = bits(_T_7502, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7504 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7503 : @[Reg.scala 28:19] _T_7504 <= _T_7494 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][92] <= _T_7504 @[ifu_mem_ctl.scala 685:41] - node _T_7505 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7506 = eq(_T_7505, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7507 = and(ic_valid_ff, _T_7506) @[ifu_mem_ctl.scala 685:97] - node _T_7508 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7509 = and(_T_7507, _T_7508) @[ifu_mem_ctl.scala 685:122] - node _T_7510 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 686:37] - node _T_7511 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7512 = and(_T_7510, _T_7511) @[ifu_mem_ctl.scala 686:59] - node _T_7513 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 686:102] - node _T_7514 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7515 = and(_T_7513, _T_7514) @[ifu_mem_ctl.scala 686:124] - node _T_7516 = or(_T_7512, _T_7515) @[ifu_mem_ctl.scala 686:81] - node _T_7517 = or(_T_7516, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7518 = bits(_T_7517, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][92] <= _T_7504 @[ifu_mem_ctl.scala 693:41] + node _T_7505 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7506 = eq(_T_7505, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7507 = and(ic_valid_ff, _T_7506) @[ifu_mem_ctl.scala 693:97] + node _T_7508 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7509 = and(_T_7507, _T_7508) @[ifu_mem_ctl.scala 693:122] + node _T_7510 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 694:37] + node _T_7511 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7512 = and(_T_7510, _T_7511) @[ifu_mem_ctl.scala 694:59] + node _T_7513 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 694:102] + node _T_7514 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7515 = and(_T_7513, _T_7514) @[ifu_mem_ctl.scala 694:124] + node _T_7516 = or(_T_7512, _T_7515) @[ifu_mem_ctl.scala 694:81] + node _T_7517 = or(_T_7516, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7518 = bits(_T_7517, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7519 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7518 : @[Reg.scala 28:19] _T_7519 <= _T_7509 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][93] <= _T_7519 @[ifu_mem_ctl.scala 685:41] - node _T_7520 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7521 = eq(_T_7520, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7522 = and(ic_valid_ff, _T_7521) @[ifu_mem_ctl.scala 685:97] - node _T_7523 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7524 = and(_T_7522, _T_7523) @[ifu_mem_ctl.scala 685:122] - node _T_7525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 686:37] - node _T_7526 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7527 = and(_T_7525, _T_7526) @[ifu_mem_ctl.scala 686:59] - node _T_7528 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 686:102] - node _T_7529 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7530 = and(_T_7528, _T_7529) @[ifu_mem_ctl.scala 686:124] - node _T_7531 = or(_T_7527, _T_7530) @[ifu_mem_ctl.scala 686:81] - node _T_7532 = or(_T_7531, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7533 = bits(_T_7532, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][93] <= _T_7519 @[ifu_mem_ctl.scala 693:41] + node _T_7520 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7521 = eq(_T_7520, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7522 = and(ic_valid_ff, _T_7521) @[ifu_mem_ctl.scala 693:97] + node _T_7523 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7524 = and(_T_7522, _T_7523) @[ifu_mem_ctl.scala 693:122] + node _T_7525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 694:37] + node _T_7526 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7527 = and(_T_7525, _T_7526) @[ifu_mem_ctl.scala 694:59] + node _T_7528 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 694:102] + node _T_7529 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7530 = and(_T_7528, _T_7529) @[ifu_mem_ctl.scala 694:124] + node _T_7531 = or(_T_7527, _T_7530) @[ifu_mem_ctl.scala 694:81] + node _T_7532 = or(_T_7531, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7533 = bits(_T_7532, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7534 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7533 : @[Reg.scala 28:19] _T_7534 <= _T_7524 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][94] <= _T_7534 @[ifu_mem_ctl.scala 685:41] - node _T_7535 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7536 = eq(_T_7535, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7537 = and(ic_valid_ff, _T_7536) @[ifu_mem_ctl.scala 685:97] - node _T_7538 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7539 = and(_T_7537, _T_7538) @[ifu_mem_ctl.scala 685:122] - node _T_7540 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 686:37] - node _T_7541 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_7542 = and(_T_7540, _T_7541) @[ifu_mem_ctl.scala 686:59] - node _T_7543 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 686:102] - node _T_7544 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_7545 = and(_T_7543, _T_7544) @[ifu_mem_ctl.scala 686:124] - node _T_7546 = or(_T_7542, _T_7545) @[ifu_mem_ctl.scala 686:81] - node _T_7547 = or(_T_7546, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7548 = bits(_T_7547, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][94] <= _T_7534 @[ifu_mem_ctl.scala 693:41] + node _T_7535 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7536 = eq(_T_7535, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7537 = and(ic_valid_ff, _T_7536) @[ifu_mem_ctl.scala 693:97] + node _T_7538 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7539 = and(_T_7537, _T_7538) @[ifu_mem_ctl.scala 693:122] + node _T_7540 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 694:37] + node _T_7541 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_7542 = and(_T_7540, _T_7541) @[ifu_mem_ctl.scala 694:59] + node _T_7543 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 694:102] + node _T_7544 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_7545 = and(_T_7543, _T_7544) @[ifu_mem_ctl.scala 694:124] + node _T_7546 = or(_T_7542, _T_7545) @[ifu_mem_ctl.scala 694:81] + node _T_7547 = or(_T_7546, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7548 = bits(_T_7547, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7549 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7548 : @[Reg.scala 28:19] _T_7549 <= _T_7539 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][95] <= _T_7549 @[ifu_mem_ctl.scala 685:41] - node _T_7550 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7551 = eq(_T_7550, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7552 = and(ic_valid_ff, _T_7551) @[ifu_mem_ctl.scala 685:97] - node _T_7553 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7554 = and(_T_7552, _T_7553) @[ifu_mem_ctl.scala 685:122] - node _T_7555 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 686:37] - node _T_7556 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7557 = and(_T_7555, _T_7556) @[ifu_mem_ctl.scala 686:59] - node _T_7558 = eq(perr_ic_index_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 686:102] - node _T_7559 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7560 = and(_T_7558, _T_7559) @[ifu_mem_ctl.scala 686:124] - node _T_7561 = or(_T_7557, _T_7560) @[ifu_mem_ctl.scala 686:81] - node _T_7562 = or(_T_7561, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7563 = bits(_T_7562, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][95] <= _T_7549 @[ifu_mem_ctl.scala 693:41] + node _T_7550 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7551 = eq(_T_7550, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7552 = and(ic_valid_ff, _T_7551) @[ifu_mem_ctl.scala 693:97] + node _T_7553 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7554 = and(_T_7552, _T_7553) @[ifu_mem_ctl.scala 693:122] + node _T_7555 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 694:37] + node _T_7556 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7557 = and(_T_7555, _T_7556) @[ifu_mem_ctl.scala 694:59] + node _T_7558 = eq(perr_ic_index_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 694:102] + node _T_7559 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7560 = and(_T_7558, _T_7559) @[ifu_mem_ctl.scala 694:124] + node _T_7561 = or(_T_7557, _T_7560) @[ifu_mem_ctl.scala 694:81] + node _T_7562 = or(_T_7561, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7563 = bits(_T_7562, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7564 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7563 : @[Reg.scala 28:19] _T_7564 <= _T_7554 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][64] <= _T_7564 @[ifu_mem_ctl.scala 685:41] - node _T_7565 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7566 = eq(_T_7565, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7567 = and(ic_valid_ff, _T_7566) @[ifu_mem_ctl.scala 685:97] - node _T_7568 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7569 = and(_T_7567, _T_7568) @[ifu_mem_ctl.scala 685:122] - node _T_7570 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 686:37] - node _T_7571 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7572 = and(_T_7570, _T_7571) @[ifu_mem_ctl.scala 686:59] - node _T_7573 = eq(perr_ic_index_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 686:102] - node _T_7574 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7575 = and(_T_7573, _T_7574) @[ifu_mem_ctl.scala 686:124] - node _T_7576 = or(_T_7572, _T_7575) @[ifu_mem_ctl.scala 686:81] - node _T_7577 = or(_T_7576, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7578 = bits(_T_7577, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][64] <= _T_7564 @[ifu_mem_ctl.scala 693:41] + node _T_7565 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7566 = eq(_T_7565, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7567 = and(ic_valid_ff, _T_7566) @[ifu_mem_ctl.scala 693:97] + node _T_7568 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7569 = and(_T_7567, _T_7568) @[ifu_mem_ctl.scala 693:122] + node _T_7570 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 694:37] + node _T_7571 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7572 = and(_T_7570, _T_7571) @[ifu_mem_ctl.scala 694:59] + node _T_7573 = eq(perr_ic_index_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 694:102] + node _T_7574 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7575 = and(_T_7573, _T_7574) @[ifu_mem_ctl.scala 694:124] + node _T_7576 = or(_T_7572, _T_7575) @[ifu_mem_ctl.scala 694:81] + node _T_7577 = or(_T_7576, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7578 = bits(_T_7577, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7579 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7578 : @[Reg.scala 28:19] _T_7579 <= _T_7569 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][65] <= _T_7579 @[ifu_mem_ctl.scala 685:41] - node _T_7580 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7581 = eq(_T_7580, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7582 = and(ic_valid_ff, _T_7581) @[ifu_mem_ctl.scala 685:97] - node _T_7583 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7584 = and(_T_7582, _T_7583) @[ifu_mem_ctl.scala 685:122] - node _T_7585 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 686:37] - node _T_7586 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7587 = and(_T_7585, _T_7586) @[ifu_mem_ctl.scala 686:59] - node _T_7588 = eq(perr_ic_index_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 686:102] - node _T_7589 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7590 = and(_T_7588, _T_7589) @[ifu_mem_ctl.scala 686:124] - node _T_7591 = or(_T_7587, _T_7590) @[ifu_mem_ctl.scala 686:81] - node _T_7592 = or(_T_7591, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7593 = bits(_T_7592, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][65] <= _T_7579 @[ifu_mem_ctl.scala 693:41] + node _T_7580 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7581 = eq(_T_7580, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7582 = and(ic_valid_ff, _T_7581) @[ifu_mem_ctl.scala 693:97] + node _T_7583 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7584 = and(_T_7582, _T_7583) @[ifu_mem_ctl.scala 693:122] + node _T_7585 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 694:37] + node _T_7586 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7587 = and(_T_7585, _T_7586) @[ifu_mem_ctl.scala 694:59] + node _T_7588 = eq(perr_ic_index_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 694:102] + node _T_7589 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7590 = and(_T_7588, _T_7589) @[ifu_mem_ctl.scala 694:124] + node _T_7591 = or(_T_7587, _T_7590) @[ifu_mem_ctl.scala 694:81] + node _T_7592 = or(_T_7591, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7593 = bits(_T_7592, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7594 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7593 : @[Reg.scala 28:19] _T_7594 <= _T_7584 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][66] <= _T_7594 @[ifu_mem_ctl.scala 685:41] - node _T_7595 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7596 = eq(_T_7595, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7597 = and(ic_valid_ff, _T_7596) @[ifu_mem_ctl.scala 685:97] - node _T_7598 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7599 = and(_T_7597, _T_7598) @[ifu_mem_ctl.scala 685:122] - node _T_7600 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 686:37] - node _T_7601 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7602 = and(_T_7600, _T_7601) @[ifu_mem_ctl.scala 686:59] - node _T_7603 = eq(perr_ic_index_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 686:102] - node _T_7604 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7605 = and(_T_7603, _T_7604) @[ifu_mem_ctl.scala 686:124] - node _T_7606 = or(_T_7602, _T_7605) @[ifu_mem_ctl.scala 686:81] - node _T_7607 = or(_T_7606, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7608 = bits(_T_7607, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][66] <= _T_7594 @[ifu_mem_ctl.scala 693:41] + node _T_7595 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7596 = eq(_T_7595, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7597 = and(ic_valid_ff, _T_7596) @[ifu_mem_ctl.scala 693:97] + node _T_7598 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7599 = and(_T_7597, _T_7598) @[ifu_mem_ctl.scala 693:122] + node _T_7600 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 694:37] + node _T_7601 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7602 = and(_T_7600, _T_7601) @[ifu_mem_ctl.scala 694:59] + node _T_7603 = eq(perr_ic_index_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 694:102] + node _T_7604 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7605 = and(_T_7603, _T_7604) @[ifu_mem_ctl.scala 694:124] + node _T_7606 = or(_T_7602, _T_7605) @[ifu_mem_ctl.scala 694:81] + node _T_7607 = or(_T_7606, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7608 = bits(_T_7607, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7609 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7608 : @[Reg.scala 28:19] _T_7609 <= _T_7599 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][67] <= _T_7609 @[ifu_mem_ctl.scala 685:41] - node _T_7610 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7611 = eq(_T_7610, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7612 = and(ic_valid_ff, _T_7611) @[ifu_mem_ctl.scala 685:97] - node _T_7613 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7614 = and(_T_7612, _T_7613) @[ifu_mem_ctl.scala 685:122] - node _T_7615 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 686:37] - node _T_7616 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7617 = and(_T_7615, _T_7616) @[ifu_mem_ctl.scala 686:59] - node _T_7618 = eq(perr_ic_index_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 686:102] - node _T_7619 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7620 = and(_T_7618, _T_7619) @[ifu_mem_ctl.scala 686:124] - node _T_7621 = or(_T_7617, _T_7620) @[ifu_mem_ctl.scala 686:81] - node _T_7622 = or(_T_7621, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7623 = bits(_T_7622, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][67] <= _T_7609 @[ifu_mem_ctl.scala 693:41] + node _T_7610 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7611 = eq(_T_7610, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7612 = and(ic_valid_ff, _T_7611) @[ifu_mem_ctl.scala 693:97] + node _T_7613 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7614 = and(_T_7612, _T_7613) @[ifu_mem_ctl.scala 693:122] + node _T_7615 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 694:37] + node _T_7616 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7617 = and(_T_7615, _T_7616) @[ifu_mem_ctl.scala 694:59] + node _T_7618 = eq(perr_ic_index_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 694:102] + node _T_7619 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7620 = and(_T_7618, _T_7619) @[ifu_mem_ctl.scala 694:124] + node _T_7621 = or(_T_7617, _T_7620) @[ifu_mem_ctl.scala 694:81] + node _T_7622 = or(_T_7621, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7623 = bits(_T_7622, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7624 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7623 : @[Reg.scala 28:19] _T_7624 <= _T_7614 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][68] <= _T_7624 @[ifu_mem_ctl.scala 685:41] - node _T_7625 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7626 = eq(_T_7625, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7627 = and(ic_valid_ff, _T_7626) @[ifu_mem_ctl.scala 685:97] - node _T_7628 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7629 = and(_T_7627, _T_7628) @[ifu_mem_ctl.scala 685:122] - node _T_7630 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 686:37] - node _T_7631 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7632 = and(_T_7630, _T_7631) @[ifu_mem_ctl.scala 686:59] - node _T_7633 = eq(perr_ic_index_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 686:102] - node _T_7634 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7635 = and(_T_7633, _T_7634) @[ifu_mem_ctl.scala 686:124] - node _T_7636 = or(_T_7632, _T_7635) @[ifu_mem_ctl.scala 686:81] - node _T_7637 = or(_T_7636, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7638 = bits(_T_7637, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][68] <= _T_7624 @[ifu_mem_ctl.scala 693:41] + node _T_7625 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7626 = eq(_T_7625, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7627 = and(ic_valid_ff, _T_7626) @[ifu_mem_ctl.scala 693:97] + node _T_7628 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7629 = and(_T_7627, _T_7628) @[ifu_mem_ctl.scala 693:122] + node _T_7630 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 694:37] + node _T_7631 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7632 = and(_T_7630, _T_7631) @[ifu_mem_ctl.scala 694:59] + node _T_7633 = eq(perr_ic_index_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 694:102] + node _T_7634 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7635 = and(_T_7633, _T_7634) @[ifu_mem_ctl.scala 694:124] + node _T_7636 = or(_T_7632, _T_7635) @[ifu_mem_ctl.scala 694:81] + node _T_7637 = or(_T_7636, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7638 = bits(_T_7637, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7639 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7638 : @[Reg.scala 28:19] _T_7639 <= _T_7629 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][69] <= _T_7639 @[ifu_mem_ctl.scala 685:41] - node _T_7640 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7641 = eq(_T_7640, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7642 = and(ic_valid_ff, _T_7641) @[ifu_mem_ctl.scala 685:97] - node _T_7643 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7644 = and(_T_7642, _T_7643) @[ifu_mem_ctl.scala 685:122] - node _T_7645 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 686:37] - node _T_7646 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7647 = and(_T_7645, _T_7646) @[ifu_mem_ctl.scala 686:59] - node _T_7648 = eq(perr_ic_index_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 686:102] - node _T_7649 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7650 = and(_T_7648, _T_7649) @[ifu_mem_ctl.scala 686:124] - node _T_7651 = or(_T_7647, _T_7650) @[ifu_mem_ctl.scala 686:81] - node _T_7652 = or(_T_7651, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7653 = bits(_T_7652, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][69] <= _T_7639 @[ifu_mem_ctl.scala 693:41] + node _T_7640 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7641 = eq(_T_7640, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7642 = and(ic_valid_ff, _T_7641) @[ifu_mem_ctl.scala 693:97] + node _T_7643 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7644 = and(_T_7642, _T_7643) @[ifu_mem_ctl.scala 693:122] + node _T_7645 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 694:37] + node _T_7646 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7647 = and(_T_7645, _T_7646) @[ifu_mem_ctl.scala 694:59] + node _T_7648 = eq(perr_ic_index_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 694:102] + node _T_7649 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7650 = and(_T_7648, _T_7649) @[ifu_mem_ctl.scala 694:124] + node _T_7651 = or(_T_7647, _T_7650) @[ifu_mem_ctl.scala 694:81] + node _T_7652 = or(_T_7651, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7653 = bits(_T_7652, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7654 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7653 : @[Reg.scala 28:19] _T_7654 <= _T_7644 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][70] <= _T_7654 @[ifu_mem_ctl.scala 685:41] - node _T_7655 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7656 = eq(_T_7655, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7657 = and(ic_valid_ff, _T_7656) @[ifu_mem_ctl.scala 685:97] - node _T_7658 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7659 = and(_T_7657, _T_7658) @[ifu_mem_ctl.scala 685:122] - node _T_7660 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 686:37] - node _T_7661 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7662 = and(_T_7660, _T_7661) @[ifu_mem_ctl.scala 686:59] - node _T_7663 = eq(perr_ic_index_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 686:102] - node _T_7664 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7665 = and(_T_7663, _T_7664) @[ifu_mem_ctl.scala 686:124] - node _T_7666 = or(_T_7662, _T_7665) @[ifu_mem_ctl.scala 686:81] - node _T_7667 = or(_T_7666, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7668 = bits(_T_7667, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][70] <= _T_7654 @[ifu_mem_ctl.scala 693:41] + node _T_7655 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7656 = eq(_T_7655, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7657 = and(ic_valid_ff, _T_7656) @[ifu_mem_ctl.scala 693:97] + node _T_7658 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7659 = and(_T_7657, _T_7658) @[ifu_mem_ctl.scala 693:122] + node _T_7660 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 694:37] + node _T_7661 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7662 = and(_T_7660, _T_7661) @[ifu_mem_ctl.scala 694:59] + node _T_7663 = eq(perr_ic_index_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 694:102] + node _T_7664 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7665 = and(_T_7663, _T_7664) @[ifu_mem_ctl.scala 694:124] + node _T_7666 = or(_T_7662, _T_7665) @[ifu_mem_ctl.scala 694:81] + node _T_7667 = or(_T_7666, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7668 = bits(_T_7667, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7669 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7668 : @[Reg.scala 28:19] _T_7669 <= _T_7659 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][71] <= _T_7669 @[ifu_mem_ctl.scala 685:41] - node _T_7670 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7671 = eq(_T_7670, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7672 = and(ic_valid_ff, _T_7671) @[ifu_mem_ctl.scala 685:97] - node _T_7673 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7674 = and(_T_7672, _T_7673) @[ifu_mem_ctl.scala 685:122] - node _T_7675 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 686:37] - node _T_7676 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7677 = and(_T_7675, _T_7676) @[ifu_mem_ctl.scala 686:59] - node _T_7678 = eq(perr_ic_index_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 686:102] - node _T_7679 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7680 = and(_T_7678, _T_7679) @[ifu_mem_ctl.scala 686:124] - node _T_7681 = or(_T_7677, _T_7680) @[ifu_mem_ctl.scala 686:81] - node _T_7682 = or(_T_7681, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7683 = bits(_T_7682, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][71] <= _T_7669 @[ifu_mem_ctl.scala 693:41] + node _T_7670 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7671 = eq(_T_7670, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7672 = and(ic_valid_ff, _T_7671) @[ifu_mem_ctl.scala 693:97] + node _T_7673 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7674 = and(_T_7672, _T_7673) @[ifu_mem_ctl.scala 693:122] + node _T_7675 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 694:37] + node _T_7676 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7677 = and(_T_7675, _T_7676) @[ifu_mem_ctl.scala 694:59] + node _T_7678 = eq(perr_ic_index_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 694:102] + node _T_7679 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7680 = and(_T_7678, _T_7679) @[ifu_mem_ctl.scala 694:124] + node _T_7681 = or(_T_7677, _T_7680) @[ifu_mem_ctl.scala 694:81] + node _T_7682 = or(_T_7681, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7683 = bits(_T_7682, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7684 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7683 : @[Reg.scala 28:19] _T_7684 <= _T_7674 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][72] <= _T_7684 @[ifu_mem_ctl.scala 685:41] - node _T_7685 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7686 = eq(_T_7685, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7687 = and(ic_valid_ff, _T_7686) @[ifu_mem_ctl.scala 685:97] - node _T_7688 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7689 = and(_T_7687, _T_7688) @[ifu_mem_ctl.scala 685:122] - node _T_7690 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 686:37] - node _T_7691 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7692 = and(_T_7690, _T_7691) @[ifu_mem_ctl.scala 686:59] - node _T_7693 = eq(perr_ic_index_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 686:102] - node _T_7694 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7695 = and(_T_7693, _T_7694) @[ifu_mem_ctl.scala 686:124] - node _T_7696 = or(_T_7692, _T_7695) @[ifu_mem_ctl.scala 686:81] - node _T_7697 = or(_T_7696, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7698 = bits(_T_7697, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][72] <= _T_7684 @[ifu_mem_ctl.scala 693:41] + node _T_7685 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7686 = eq(_T_7685, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7687 = and(ic_valid_ff, _T_7686) @[ifu_mem_ctl.scala 693:97] + node _T_7688 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7689 = and(_T_7687, _T_7688) @[ifu_mem_ctl.scala 693:122] + node _T_7690 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 694:37] + node _T_7691 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7692 = and(_T_7690, _T_7691) @[ifu_mem_ctl.scala 694:59] + node _T_7693 = eq(perr_ic_index_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 694:102] + node _T_7694 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7695 = and(_T_7693, _T_7694) @[ifu_mem_ctl.scala 694:124] + node _T_7696 = or(_T_7692, _T_7695) @[ifu_mem_ctl.scala 694:81] + node _T_7697 = or(_T_7696, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7698 = bits(_T_7697, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7699 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7698 : @[Reg.scala 28:19] _T_7699 <= _T_7689 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][73] <= _T_7699 @[ifu_mem_ctl.scala 685:41] - node _T_7700 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7701 = eq(_T_7700, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7702 = and(ic_valid_ff, _T_7701) @[ifu_mem_ctl.scala 685:97] - node _T_7703 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7704 = and(_T_7702, _T_7703) @[ifu_mem_ctl.scala 685:122] - node _T_7705 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 686:37] - node _T_7706 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7707 = and(_T_7705, _T_7706) @[ifu_mem_ctl.scala 686:59] - node _T_7708 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 686:102] - node _T_7709 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7710 = and(_T_7708, _T_7709) @[ifu_mem_ctl.scala 686:124] - node _T_7711 = or(_T_7707, _T_7710) @[ifu_mem_ctl.scala 686:81] - node _T_7712 = or(_T_7711, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7713 = bits(_T_7712, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][73] <= _T_7699 @[ifu_mem_ctl.scala 693:41] + node _T_7700 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7701 = eq(_T_7700, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7702 = and(ic_valid_ff, _T_7701) @[ifu_mem_ctl.scala 693:97] + node _T_7703 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7704 = and(_T_7702, _T_7703) @[ifu_mem_ctl.scala 693:122] + node _T_7705 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 694:37] + node _T_7706 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7707 = and(_T_7705, _T_7706) @[ifu_mem_ctl.scala 694:59] + node _T_7708 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 694:102] + node _T_7709 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7710 = and(_T_7708, _T_7709) @[ifu_mem_ctl.scala 694:124] + node _T_7711 = or(_T_7707, _T_7710) @[ifu_mem_ctl.scala 694:81] + node _T_7712 = or(_T_7711, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7713 = bits(_T_7712, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7714 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7713 : @[Reg.scala 28:19] _T_7714 <= _T_7704 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][74] <= _T_7714 @[ifu_mem_ctl.scala 685:41] - node _T_7715 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7716 = eq(_T_7715, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7717 = and(ic_valid_ff, _T_7716) @[ifu_mem_ctl.scala 685:97] - node _T_7718 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7719 = and(_T_7717, _T_7718) @[ifu_mem_ctl.scala 685:122] - node _T_7720 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 686:37] - node _T_7721 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7722 = and(_T_7720, _T_7721) @[ifu_mem_ctl.scala 686:59] - node _T_7723 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 686:102] - node _T_7724 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7725 = and(_T_7723, _T_7724) @[ifu_mem_ctl.scala 686:124] - node _T_7726 = or(_T_7722, _T_7725) @[ifu_mem_ctl.scala 686:81] - node _T_7727 = or(_T_7726, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7728 = bits(_T_7727, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][74] <= _T_7714 @[ifu_mem_ctl.scala 693:41] + node _T_7715 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7716 = eq(_T_7715, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7717 = and(ic_valid_ff, _T_7716) @[ifu_mem_ctl.scala 693:97] + node _T_7718 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7719 = and(_T_7717, _T_7718) @[ifu_mem_ctl.scala 693:122] + node _T_7720 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 694:37] + node _T_7721 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7722 = and(_T_7720, _T_7721) @[ifu_mem_ctl.scala 694:59] + node _T_7723 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 694:102] + node _T_7724 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7725 = and(_T_7723, _T_7724) @[ifu_mem_ctl.scala 694:124] + node _T_7726 = or(_T_7722, _T_7725) @[ifu_mem_ctl.scala 694:81] + node _T_7727 = or(_T_7726, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7728 = bits(_T_7727, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7729 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7728 : @[Reg.scala 28:19] _T_7729 <= _T_7719 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][75] <= _T_7729 @[ifu_mem_ctl.scala 685:41] - node _T_7730 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7731 = eq(_T_7730, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7732 = and(ic_valid_ff, _T_7731) @[ifu_mem_ctl.scala 685:97] - node _T_7733 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7734 = and(_T_7732, _T_7733) @[ifu_mem_ctl.scala 685:122] - node _T_7735 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 686:37] - node _T_7736 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7737 = and(_T_7735, _T_7736) @[ifu_mem_ctl.scala 686:59] - node _T_7738 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 686:102] - node _T_7739 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7740 = and(_T_7738, _T_7739) @[ifu_mem_ctl.scala 686:124] - node _T_7741 = or(_T_7737, _T_7740) @[ifu_mem_ctl.scala 686:81] - node _T_7742 = or(_T_7741, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7743 = bits(_T_7742, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][75] <= _T_7729 @[ifu_mem_ctl.scala 693:41] + node _T_7730 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7731 = eq(_T_7730, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7732 = and(ic_valid_ff, _T_7731) @[ifu_mem_ctl.scala 693:97] + node _T_7733 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7734 = and(_T_7732, _T_7733) @[ifu_mem_ctl.scala 693:122] + node _T_7735 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 694:37] + node _T_7736 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7737 = and(_T_7735, _T_7736) @[ifu_mem_ctl.scala 694:59] + node _T_7738 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 694:102] + node _T_7739 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7740 = and(_T_7738, _T_7739) @[ifu_mem_ctl.scala 694:124] + node _T_7741 = or(_T_7737, _T_7740) @[ifu_mem_ctl.scala 694:81] + node _T_7742 = or(_T_7741, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7743 = bits(_T_7742, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7744 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7743 : @[Reg.scala 28:19] _T_7744 <= _T_7734 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][76] <= _T_7744 @[ifu_mem_ctl.scala 685:41] - node _T_7745 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7746 = eq(_T_7745, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7747 = and(ic_valid_ff, _T_7746) @[ifu_mem_ctl.scala 685:97] - node _T_7748 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7749 = and(_T_7747, _T_7748) @[ifu_mem_ctl.scala 685:122] - node _T_7750 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 686:37] - node _T_7751 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7752 = and(_T_7750, _T_7751) @[ifu_mem_ctl.scala 686:59] - node _T_7753 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 686:102] - node _T_7754 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7755 = and(_T_7753, _T_7754) @[ifu_mem_ctl.scala 686:124] - node _T_7756 = or(_T_7752, _T_7755) @[ifu_mem_ctl.scala 686:81] - node _T_7757 = or(_T_7756, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7758 = bits(_T_7757, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][76] <= _T_7744 @[ifu_mem_ctl.scala 693:41] + node _T_7745 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7746 = eq(_T_7745, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7747 = and(ic_valid_ff, _T_7746) @[ifu_mem_ctl.scala 693:97] + node _T_7748 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7749 = and(_T_7747, _T_7748) @[ifu_mem_ctl.scala 693:122] + node _T_7750 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 694:37] + node _T_7751 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7752 = and(_T_7750, _T_7751) @[ifu_mem_ctl.scala 694:59] + node _T_7753 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 694:102] + node _T_7754 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7755 = and(_T_7753, _T_7754) @[ifu_mem_ctl.scala 694:124] + node _T_7756 = or(_T_7752, _T_7755) @[ifu_mem_ctl.scala 694:81] + node _T_7757 = or(_T_7756, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7758 = bits(_T_7757, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7759 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7758 : @[Reg.scala 28:19] _T_7759 <= _T_7749 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][77] <= _T_7759 @[ifu_mem_ctl.scala 685:41] - node _T_7760 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7761 = eq(_T_7760, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7762 = and(ic_valid_ff, _T_7761) @[ifu_mem_ctl.scala 685:97] - node _T_7763 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7764 = and(_T_7762, _T_7763) @[ifu_mem_ctl.scala 685:122] - node _T_7765 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 686:37] - node _T_7766 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7767 = and(_T_7765, _T_7766) @[ifu_mem_ctl.scala 686:59] - node _T_7768 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 686:102] - node _T_7769 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7770 = and(_T_7768, _T_7769) @[ifu_mem_ctl.scala 686:124] - node _T_7771 = or(_T_7767, _T_7770) @[ifu_mem_ctl.scala 686:81] - node _T_7772 = or(_T_7771, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7773 = bits(_T_7772, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][77] <= _T_7759 @[ifu_mem_ctl.scala 693:41] + node _T_7760 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7761 = eq(_T_7760, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7762 = and(ic_valid_ff, _T_7761) @[ifu_mem_ctl.scala 693:97] + node _T_7763 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7764 = and(_T_7762, _T_7763) @[ifu_mem_ctl.scala 693:122] + node _T_7765 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 694:37] + node _T_7766 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7767 = and(_T_7765, _T_7766) @[ifu_mem_ctl.scala 694:59] + node _T_7768 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 694:102] + node _T_7769 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7770 = and(_T_7768, _T_7769) @[ifu_mem_ctl.scala 694:124] + node _T_7771 = or(_T_7767, _T_7770) @[ifu_mem_ctl.scala 694:81] + node _T_7772 = or(_T_7771, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7773 = bits(_T_7772, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7774 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7773 : @[Reg.scala 28:19] _T_7774 <= _T_7764 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][78] <= _T_7774 @[ifu_mem_ctl.scala 685:41] - node _T_7775 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7776 = eq(_T_7775, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7777 = and(ic_valid_ff, _T_7776) @[ifu_mem_ctl.scala 685:97] - node _T_7778 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7779 = and(_T_7777, _T_7778) @[ifu_mem_ctl.scala 685:122] - node _T_7780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 686:37] - node _T_7781 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7782 = and(_T_7780, _T_7781) @[ifu_mem_ctl.scala 686:59] - node _T_7783 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 686:102] - node _T_7784 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7785 = and(_T_7783, _T_7784) @[ifu_mem_ctl.scala 686:124] - node _T_7786 = or(_T_7782, _T_7785) @[ifu_mem_ctl.scala 686:81] - node _T_7787 = or(_T_7786, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7788 = bits(_T_7787, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][78] <= _T_7774 @[ifu_mem_ctl.scala 693:41] + node _T_7775 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7776 = eq(_T_7775, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7777 = and(ic_valid_ff, _T_7776) @[ifu_mem_ctl.scala 693:97] + node _T_7778 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7779 = and(_T_7777, _T_7778) @[ifu_mem_ctl.scala 693:122] + node _T_7780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 694:37] + node _T_7781 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7782 = and(_T_7780, _T_7781) @[ifu_mem_ctl.scala 694:59] + node _T_7783 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 694:102] + node _T_7784 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7785 = and(_T_7783, _T_7784) @[ifu_mem_ctl.scala 694:124] + node _T_7786 = or(_T_7782, _T_7785) @[ifu_mem_ctl.scala 694:81] + node _T_7787 = or(_T_7786, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7788 = bits(_T_7787, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7789 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7788 : @[Reg.scala 28:19] _T_7789 <= _T_7779 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][79] <= _T_7789 @[ifu_mem_ctl.scala 685:41] - node _T_7790 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7791 = eq(_T_7790, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7792 = and(ic_valid_ff, _T_7791) @[ifu_mem_ctl.scala 685:97] - node _T_7793 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7794 = and(_T_7792, _T_7793) @[ifu_mem_ctl.scala 685:122] - node _T_7795 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 686:37] - node _T_7796 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7797 = and(_T_7795, _T_7796) @[ifu_mem_ctl.scala 686:59] - node _T_7798 = eq(perr_ic_index_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 686:102] - node _T_7799 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7800 = and(_T_7798, _T_7799) @[ifu_mem_ctl.scala 686:124] - node _T_7801 = or(_T_7797, _T_7800) @[ifu_mem_ctl.scala 686:81] - node _T_7802 = or(_T_7801, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7803 = bits(_T_7802, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][79] <= _T_7789 @[ifu_mem_ctl.scala 693:41] + node _T_7790 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7791 = eq(_T_7790, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7792 = and(ic_valid_ff, _T_7791) @[ifu_mem_ctl.scala 693:97] + node _T_7793 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7794 = and(_T_7792, _T_7793) @[ifu_mem_ctl.scala 693:122] + node _T_7795 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 694:37] + node _T_7796 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7797 = and(_T_7795, _T_7796) @[ifu_mem_ctl.scala 694:59] + node _T_7798 = eq(perr_ic_index_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 694:102] + node _T_7799 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7800 = and(_T_7798, _T_7799) @[ifu_mem_ctl.scala 694:124] + node _T_7801 = or(_T_7797, _T_7800) @[ifu_mem_ctl.scala 694:81] + node _T_7802 = or(_T_7801, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7803 = bits(_T_7802, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7804 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7803 : @[Reg.scala 28:19] _T_7804 <= _T_7794 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][80] <= _T_7804 @[ifu_mem_ctl.scala 685:41] - node _T_7805 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7806 = eq(_T_7805, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7807 = and(ic_valid_ff, _T_7806) @[ifu_mem_ctl.scala 685:97] - node _T_7808 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7809 = and(_T_7807, _T_7808) @[ifu_mem_ctl.scala 685:122] - node _T_7810 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 686:37] - node _T_7811 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7812 = and(_T_7810, _T_7811) @[ifu_mem_ctl.scala 686:59] - node _T_7813 = eq(perr_ic_index_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 686:102] - node _T_7814 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7815 = and(_T_7813, _T_7814) @[ifu_mem_ctl.scala 686:124] - node _T_7816 = or(_T_7812, _T_7815) @[ifu_mem_ctl.scala 686:81] - node _T_7817 = or(_T_7816, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7818 = bits(_T_7817, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][80] <= _T_7804 @[ifu_mem_ctl.scala 693:41] + node _T_7805 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7806 = eq(_T_7805, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7807 = and(ic_valid_ff, _T_7806) @[ifu_mem_ctl.scala 693:97] + node _T_7808 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7809 = and(_T_7807, _T_7808) @[ifu_mem_ctl.scala 693:122] + node _T_7810 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 694:37] + node _T_7811 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7812 = and(_T_7810, _T_7811) @[ifu_mem_ctl.scala 694:59] + node _T_7813 = eq(perr_ic_index_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 694:102] + node _T_7814 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7815 = and(_T_7813, _T_7814) @[ifu_mem_ctl.scala 694:124] + node _T_7816 = or(_T_7812, _T_7815) @[ifu_mem_ctl.scala 694:81] + node _T_7817 = or(_T_7816, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7818 = bits(_T_7817, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7819 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7818 : @[Reg.scala 28:19] _T_7819 <= _T_7809 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][81] <= _T_7819 @[ifu_mem_ctl.scala 685:41] - node _T_7820 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7821 = eq(_T_7820, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7822 = and(ic_valid_ff, _T_7821) @[ifu_mem_ctl.scala 685:97] - node _T_7823 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7824 = and(_T_7822, _T_7823) @[ifu_mem_ctl.scala 685:122] - node _T_7825 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 686:37] - node _T_7826 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7827 = and(_T_7825, _T_7826) @[ifu_mem_ctl.scala 686:59] - node _T_7828 = eq(perr_ic_index_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 686:102] - node _T_7829 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7830 = and(_T_7828, _T_7829) @[ifu_mem_ctl.scala 686:124] - node _T_7831 = or(_T_7827, _T_7830) @[ifu_mem_ctl.scala 686:81] - node _T_7832 = or(_T_7831, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7833 = bits(_T_7832, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][81] <= _T_7819 @[ifu_mem_ctl.scala 693:41] + node _T_7820 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7821 = eq(_T_7820, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7822 = and(ic_valid_ff, _T_7821) @[ifu_mem_ctl.scala 693:97] + node _T_7823 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7824 = and(_T_7822, _T_7823) @[ifu_mem_ctl.scala 693:122] + node _T_7825 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 694:37] + node _T_7826 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7827 = and(_T_7825, _T_7826) @[ifu_mem_ctl.scala 694:59] + node _T_7828 = eq(perr_ic_index_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 694:102] + node _T_7829 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7830 = and(_T_7828, _T_7829) @[ifu_mem_ctl.scala 694:124] + node _T_7831 = or(_T_7827, _T_7830) @[ifu_mem_ctl.scala 694:81] + node _T_7832 = or(_T_7831, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7833 = bits(_T_7832, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7834 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7833 : @[Reg.scala 28:19] _T_7834 <= _T_7824 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][82] <= _T_7834 @[ifu_mem_ctl.scala 685:41] - node _T_7835 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7836 = eq(_T_7835, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7837 = and(ic_valid_ff, _T_7836) @[ifu_mem_ctl.scala 685:97] - node _T_7838 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7839 = and(_T_7837, _T_7838) @[ifu_mem_ctl.scala 685:122] - node _T_7840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 686:37] - node _T_7841 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7842 = and(_T_7840, _T_7841) @[ifu_mem_ctl.scala 686:59] - node _T_7843 = eq(perr_ic_index_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 686:102] - node _T_7844 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7845 = and(_T_7843, _T_7844) @[ifu_mem_ctl.scala 686:124] - node _T_7846 = or(_T_7842, _T_7845) @[ifu_mem_ctl.scala 686:81] - node _T_7847 = or(_T_7846, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7848 = bits(_T_7847, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][82] <= _T_7834 @[ifu_mem_ctl.scala 693:41] + node _T_7835 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7836 = eq(_T_7835, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7837 = and(ic_valid_ff, _T_7836) @[ifu_mem_ctl.scala 693:97] + node _T_7838 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7839 = and(_T_7837, _T_7838) @[ifu_mem_ctl.scala 693:122] + node _T_7840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 694:37] + node _T_7841 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7842 = and(_T_7840, _T_7841) @[ifu_mem_ctl.scala 694:59] + node _T_7843 = eq(perr_ic_index_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 694:102] + node _T_7844 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7845 = and(_T_7843, _T_7844) @[ifu_mem_ctl.scala 694:124] + node _T_7846 = or(_T_7842, _T_7845) @[ifu_mem_ctl.scala 694:81] + node _T_7847 = or(_T_7846, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7848 = bits(_T_7847, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7849 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7848 : @[Reg.scala 28:19] _T_7849 <= _T_7839 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][83] <= _T_7849 @[ifu_mem_ctl.scala 685:41] - node _T_7850 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7851 = eq(_T_7850, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7852 = and(ic_valid_ff, _T_7851) @[ifu_mem_ctl.scala 685:97] - node _T_7853 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7854 = and(_T_7852, _T_7853) @[ifu_mem_ctl.scala 685:122] - node _T_7855 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 686:37] - node _T_7856 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7857 = and(_T_7855, _T_7856) @[ifu_mem_ctl.scala 686:59] - node _T_7858 = eq(perr_ic_index_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 686:102] - node _T_7859 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7860 = and(_T_7858, _T_7859) @[ifu_mem_ctl.scala 686:124] - node _T_7861 = or(_T_7857, _T_7860) @[ifu_mem_ctl.scala 686:81] - node _T_7862 = or(_T_7861, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7863 = bits(_T_7862, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][83] <= _T_7849 @[ifu_mem_ctl.scala 693:41] + node _T_7850 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7851 = eq(_T_7850, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7852 = and(ic_valid_ff, _T_7851) @[ifu_mem_ctl.scala 693:97] + node _T_7853 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7854 = and(_T_7852, _T_7853) @[ifu_mem_ctl.scala 693:122] + node _T_7855 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 694:37] + node _T_7856 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7857 = and(_T_7855, _T_7856) @[ifu_mem_ctl.scala 694:59] + node _T_7858 = eq(perr_ic_index_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 694:102] + node _T_7859 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7860 = and(_T_7858, _T_7859) @[ifu_mem_ctl.scala 694:124] + node _T_7861 = or(_T_7857, _T_7860) @[ifu_mem_ctl.scala 694:81] + node _T_7862 = or(_T_7861, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7863 = bits(_T_7862, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7864 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7863 : @[Reg.scala 28:19] _T_7864 <= _T_7854 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][84] <= _T_7864 @[ifu_mem_ctl.scala 685:41] - node _T_7865 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7866 = eq(_T_7865, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7867 = and(ic_valid_ff, _T_7866) @[ifu_mem_ctl.scala 685:97] - node _T_7868 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7869 = and(_T_7867, _T_7868) @[ifu_mem_ctl.scala 685:122] - node _T_7870 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 686:37] - node _T_7871 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7872 = and(_T_7870, _T_7871) @[ifu_mem_ctl.scala 686:59] - node _T_7873 = eq(perr_ic_index_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 686:102] - node _T_7874 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7875 = and(_T_7873, _T_7874) @[ifu_mem_ctl.scala 686:124] - node _T_7876 = or(_T_7872, _T_7875) @[ifu_mem_ctl.scala 686:81] - node _T_7877 = or(_T_7876, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7878 = bits(_T_7877, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][84] <= _T_7864 @[ifu_mem_ctl.scala 693:41] + node _T_7865 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7866 = eq(_T_7865, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7867 = and(ic_valid_ff, _T_7866) @[ifu_mem_ctl.scala 693:97] + node _T_7868 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7869 = and(_T_7867, _T_7868) @[ifu_mem_ctl.scala 693:122] + node _T_7870 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 694:37] + node _T_7871 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7872 = and(_T_7870, _T_7871) @[ifu_mem_ctl.scala 694:59] + node _T_7873 = eq(perr_ic_index_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 694:102] + node _T_7874 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7875 = and(_T_7873, _T_7874) @[ifu_mem_ctl.scala 694:124] + node _T_7876 = or(_T_7872, _T_7875) @[ifu_mem_ctl.scala 694:81] + node _T_7877 = or(_T_7876, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7878 = bits(_T_7877, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7879 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7878 : @[Reg.scala 28:19] _T_7879 <= _T_7869 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][85] <= _T_7879 @[ifu_mem_ctl.scala 685:41] - node _T_7880 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7881 = eq(_T_7880, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7882 = and(ic_valid_ff, _T_7881) @[ifu_mem_ctl.scala 685:97] - node _T_7883 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7884 = and(_T_7882, _T_7883) @[ifu_mem_ctl.scala 685:122] - node _T_7885 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 686:37] - node _T_7886 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7887 = and(_T_7885, _T_7886) @[ifu_mem_ctl.scala 686:59] - node _T_7888 = eq(perr_ic_index_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 686:102] - node _T_7889 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7890 = and(_T_7888, _T_7889) @[ifu_mem_ctl.scala 686:124] - node _T_7891 = or(_T_7887, _T_7890) @[ifu_mem_ctl.scala 686:81] - node _T_7892 = or(_T_7891, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7893 = bits(_T_7892, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][85] <= _T_7879 @[ifu_mem_ctl.scala 693:41] + node _T_7880 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7881 = eq(_T_7880, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7882 = and(ic_valid_ff, _T_7881) @[ifu_mem_ctl.scala 693:97] + node _T_7883 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7884 = and(_T_7882, _T_7883) @[ifu_mem_ctl.scala 693:122] + node _T_7885 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 694:37] + node _T_7886 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7887 = and(_T_7885, _T_7886) @[ifu_mem_ctl.scala 694:59] + node _T_7888 = eq(perr_ic_index_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 694:102] + node _T_7889 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7890 = and(_T_7888, _T_7889) @[ifu_mem_ctl.scala 694:124] + node _T_7891 = or(_T_7887, _T_7890) @[ifu_mem_ctl.scala 694:81] + node _T_7892 = or(_T_7891, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7893 = bits(_T_7892, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7894 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7893 : @[Reg.scala 28:19] _T_7894 <= _T_7884 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][86] <= _T_7894 @[ifu_mem_ctl.scala 685:41] - node _T_7895 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7896 = eq(_T_7895, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7897 = and(ic_valid_ff, _T_7896) @[ifu_mem_ctl.scala 685:97] - node _T_7898 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7899 = and(_T_7897, _T_7898) @[ifu_mem_ctl.scala 685:122] - node _T_7900 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 686:37] - node _T_7901 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7902 = and(_T_7900, _T_7901) @[ifu_mem_ctl.scala 686:59] - node _T_7903 = eq(perr_ic_index_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 686:102] - node _T_7904 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7905 = and(_T_7903, _T_7904) @[ifu_mem_ctl.scala 686:124] - node _T_7906 = or(_T_7902, _T_7905) @[ifu_mem_ctl.scala 686:81] - node _T_7907 = or(_T_7906, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7908 = bits(_T_7907, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][86] <= _T_7894 @[ifu_mem_ctl.scala 693:41] + node _T_7895 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7896 = eq(_T_7895, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7897 = and(ic_valid_ff, _T_7896) @[ifu_mem_ctl.scala 693:97] + node _T_7898 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7899 = and(_T_7897, _T_7898) @[ifu_mem_ctl.scala 693:122] + node _T_7900 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 694:37] + node _T_7901 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7902 = and(_T_7900, _T_7901) @[ifu_mem_ctl.scala 694:59] + node _T_7903 = eq(perr_ic_index_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 694:102] + node _T_7904 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7905 = and(_T_7903, _T_7904) @[ifu_mem_ctl.scala 694:124] + node _T_7906 = or(_T_7902, _T_7905) @[ifu_mem_ctl.scala 694:81] + node _T_7907 = or(_T_7906, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7908 = bits(_T_7907, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7909 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7908 : @[Reg.scala 28:19] _T_7909 <= _T_7899 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][87] <= _T_7909 @[ifu_mem_ctl.scala 685:41] - node _T_7910 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7911 = eq(_T_7910, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7912 = and(ic_valid_ff, _T_7911) @[ifu_mem_ctl.scala 685:97] - node _T_7913 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7914 = and(_T_7912, _T_7913) @[ifu_mem_ctl.scala 685:122] - node _T_7915 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 686:37] - node _T_7916 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7917 = and(_T_7915, _T_7916) @[ifu_mem_ctl.scala 686:59] - node _T_7918 = eq(perr_ic_index_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 686:102] - node _T_7919 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7920 = and(_T_7918, _T_7919) @[ifu_mem_ctl.scala 686:124] - node _T_7921 = or(_T_7917, _T_7920) @[ifu_mem_ctl.scala 686:81] - node _T_7922 = or(_T_7921, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7923 = bits(_T_7922, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][87] <= _T_7909 @[ifu_mem_ctl.scala 693:41] + node _T_7910 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7911 = eq(_T_7910, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7912 = and(ic_valid_ff, _T_7911) @[ifu_mem_ctl.scala 693:97] + node _T_7913 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7914 = and(_T_7912, _T_7913) @[ifu_mem_ctl.scala 693:122] + node _T_7915 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 694:37] + node _T_7916 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7917 = and(_T_7915, _T_7916) @[ifu_mem_ctl.scala 694:59] + node _T_7918 = eq(perr_ic_index_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 694:102] + node _T_7919 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7920 = and(_T_7918, _T_7919) @[ifu_mem_ctl.scala 694:124] + node _T_7921 = or(_T_7917, _T_7920) @[ifu_mem_ctl.scala 694:81] + node _T_7922 = or(_T_7921, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7923 = bits(_T_7922, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7924 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7923 : @[Reg.scala 28:19] _T_7924 <= _T_7914 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][88] <= _T_7924 @[ifu_mem_ctl.scala 685:41] - node _T_7925 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7926 = eq(_T_7925, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7927 = and(ic_valid_ff, _T_7926) @[ifu_mem_ctl.scala 685:97] - node _T_7928 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7929 = and(_T_7927, _T_7928) @[ifu_mem_ctl.scala 685:122] - node _T_7930 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 686:37] - node _T_7931 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7932 = and(_T_7930, _T_7931) @[ifu_mem_ctl.scala 686:59] - node _T_7933 = eq(perr_ic_index_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 686:102] - node _T_7934 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7935 = and(_T_7933, _T_7934) @[ifu_mem_ctl.scala 686:124] - node _T_7936 = or(_T_7932, _T_7935) @[ifu_mem_ctl.scala 686:81] - node _T_7937 = or(_T_7936, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7938 = bits(_T_7937, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][88] <= _T_7924 @[ifu_mem_ctl.scala 693:41] + node _T_7925 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7926 = eq(_T_7925, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7927 = and(ic_valid_ff, _T_7926) @[ifu_mem_ctl.scala 693:97] + node _T_7928 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7929 = and(_T_7927, _T_7928) @[ifu_mem_ctl.scala 693:122] + node _T_7930 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 694:37] + node _T_7931 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7932 = and(_T_7930, _T_7931) @[ifu_mem_ctl.scala 694:59] + node _T_7933 = eq(perr_ic_index_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 694:102] + node _T_7934 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7935 = and(_T_7933, _T_7934) @[ifu_mem_ctl.scala 694:124] + node _T_7936 = or(_T_7932, _T_7935) @[ifu_mem_ctl.scala 694:81] + node _T_7937 = or(_T_7936, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7938 = bits(_T_7937, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7939 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7938 : @[Reg.scala 28:19] _T_7939 <= _T_7929 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][89] <= _T_7939 @[ifu_mem_ctl.scala 685:41] - node _T_7940 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7941 = eq(_T_7940, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7942 = and(ic_valid_ff, _T_7941) @[ifu_mem_ctl.scala 685:97] - node _T_7943 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7944 = and(_T_7942, _T_7943) @[ifu_mem_ctl.scala 685:122] - node _T_7945 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 686:37] - node _T_7946 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7947 = and(_T_7945, _T_7946) @[ifu_mem_ctl.scala 686:59] - node _T_7948 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 686:102] - node _T_7949 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7950 = and(_T_7948, _T_7949) @[ifu_mem_ctl.scala 686:124] - node _T_7951 = or(_T_7947, _T_7950) @[ifu_mem_ctl.scala 686:81] - node _T_7952 = or(_T_7951, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7953 = bits(_T_7952, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][89] <= _T_7939 @[ifu_mem_ctl.scala 693:41] + node _T_7940 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7941 = eq(_T_7940, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7942 = and(ic_valid_ff, _T_7941) @[ifu_mem_ctl.scala 693:97] + node _T_7943 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7944 = and(_T_7942, _T_7943) @[ifu_mem_ctl.scala 693:122] + node _T_7945 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 694:37] + node _T_7946 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7947 = and(_T_7945, _T_7946) @[ifu_mem_ctl.scala 694:59] + node _T_7948 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 694:102] + node _T_7949 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7950 = and(_T_7948, _T_7949) @[ifu_mem_ctl.scala 694:124] + node _T_7951 = or(_T_7947, _T_7950) @[ifu_mem_ctl.scala 694:81] + node _T_7952 = or(_T_7951, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7953 = bits(_T_7952, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7954 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7953 : @[Reg.scala 28:19] _T_7954 <= _T_7944 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][90] <= _T_7954 @[ifu_mem_ctl.scala 685:41] - node _T_7955 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7956 = eq(_T_7955, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7957 = and(ic_valid_ff, _T_7956) @[ifu_mem_ctl.scala 685:97] - node _T_7958 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7959 = and(_T_7957, _T_7958) @[ifu_mem_ctl.scala 685:122] - node _T_7960 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 686:37] - node _T_7961 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7962 = and(_T_7960, _T_7961) @[ifu_mem_ctl.scala 686:59] - node _T_7963 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 686:102] - node _T_7964 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7965 = and(_T_7963, _T_7964) @[ifu_mem_ctl.scala 686:124] - node _T_7966 = or(_T_7962, _T_7965) @[ifu_mem_ctl.scala 686:81] - node _T_7967 = or(_T_7966, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7968 = bits(_T_7967, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][90] <= _T_7954 @[ifu_mem_ctl.scala 693:41] + node _T_7955 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7956 = eq(_T_7955, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7957 = and(ic_valid_ff, _T_7956) @[ifu_mem_ctl.scala 693:97] + node _T_7958 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7959 = and(_T_7957, _T_7958) @[ifu_mem_ctl.scala 693:122] + node _T_7960 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 694:37] + node _T_7961 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7962 = and(_T_7960, _T_7961) @[ifu_mem_ctl.scala 694:59] + node _T_7963 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 694:102] + node _T_7964 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7965 = and(_T_7963, _T_7964) @[ifu_mem_ctl.scala 694:124] + node _T_7966 = or(_T_7962, _T_7965) @[ifu_mem_ctl.scala 694:81] + node _T_7967 = or(_T_7966, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7968 = bits(_T_7967, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7969 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7968 : @[Reg.scala 28:19] _T_7969 <= _T_7959 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][91] <= _T_7969 @[ifu_mem_ctl.scala 685:41] - node _T_7970 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7971 = eq(_T_7970, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7972 = and(ic_valid_ff, _T_7971) @[ifu_mem_ctl.scala 685:97] - node _T_7973 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7974 = and(_T_7972, _T_7973) @[ifu_mem_ctl.scala 685:122] - node _T_7975 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 686:37] - node _T_7976 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7977 = and(_T_7975, _T_7976) @[ifu_mem_ctl.scala 686:59] - node _T_7978 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 686:102] - node _T_7979 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7980 = and(_T_7978, _T_7979) @[ifu_mem_ctl.scala 686:124] - node _T_7981 = or(_T_7977, _T_7980) @[ifu_mem_ctl.scala 686:81] - node _T_7982 = or(_T_7981, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7983 = bits(_T_7982, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][91] <= _T_7969 @[ifu_mem_ctl.scala 693:41] + node _T_7970 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7971 = eq(_T_7970, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7972 = and(ic_valid_ff, _T_7971) @[ifu_mem_ctl.scala 693:97] + node _T_7973 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7974 = and(_T_7972, _T_7973) @[ifu_mem_ctl.scala 693:122] + node _T_7975 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 694:37] + node _T_7976 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7977 = and(_T_7975, _T_7976) @[ifu_mem_ctl.scala 694:59] + node _T_7978 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 694:102] + node _T_7979 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7980 = and(_T_7978, _T_7979) @[ifu_mem_ctl.scala 694:124] + node _T_7981 = or(_T_7977, _T_7980) @[ifu_mem_ctl.scala 694:81] + node _T_7982 = or(_T_7981, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7983 = bits(_T_7982, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7984 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7983 : @[Reg.scala 28:19] _T_7984 <= _T_7974 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][92] <= _T_7984 @[ifu_mem_ctl.scala 685:41] - node _T_7985 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_7986 = eq(_T_7985, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_7987 = and(ic_valid_ff, _T_7986) @[ifu_mem_ctl.scala 685:97] - node _T_7988 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_7989 = and(_T_7987, _T_7988) @[ifu_mem_ctl.scala 685:122] - node _T_7990 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 686:37] - node _T_7991 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_7992 = and(_T_7990, _T_7991) @[ifu_mem_ctl.scala 686:59] - node _T_7993 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 686:102] - node _T_7994 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_7995 = and(_T_7993, _T_7994) @[ifu_mem_ctl.scala 686:124] - node _T_7996 = or(_T_7992, _T_7995) @[ifu_mem_ctl.scala 686:81] - node _T_7997 = or(_T_7996, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_7998 = bits(_T_7997, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][92] <= _T_7984 @[ifu_mem_ctl.scala 693:41] + node _T_7985 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_7986 = eq(_T_7985, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_7987 = and(ic_valid_ff, _T_7986) @[ifu_mem_ctl.scala 693:97] + node _T_7988 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_7989 = and(_T_7987, _T_7988) @[ifu_mem_ctl.scala 693:122] + node _T_7990 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 694:37] + node _T_7991 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_7992 = and(_T_7990, _T_7991) @[ifu_mem_ctl.scala 694:59] + node _T_7993 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 694:102] + node _T_7994 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_7995 = and(_T_7993, _T_7994) @[ifu_mem_ctl.scala 694:124] + node _T_7996 = or(_T_7992, _T_7995) @[ifu_mem_ctl.scala 694:81] + node _T_7997 = or(_T_7996, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_7998 = bits(_T_7997, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_7999 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7998 : @[Reg.scala 28:19] _T_7999 <= _T_7989 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][93] <= _T_7999 @[ifu_mem_ctl.scala 685:41] - node _T_8000 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8001 = eq(_T_8000, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8002 = and(ic_valid_ff, _T_8001) @[ifu_mem_ctl.scala 685:97] - node _T_8003 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8004 = and(_T_8002, _T_8003) @[ifu_mem_ctl.scala 685:122] - node _T_8005 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 686:37] - node _T_8006 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8007 = and(_T_8005, _T_8006) @[ifu_mem_ctl.scala 686:59] - node _T_8008 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 686:102] - node _T_8009 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8010 = and(_T_8008, _T_8009) @[ifu_mem_ctl.scala 686:124] - node _T_8011 = or(_T_8007, _T_8010) @[ifu_mem_ctl.scala 686:81] - node _T_8012 = or(_T_8011, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8013 = bits(_T_8012, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][93] <= _T_7999 @[ifu_mem_ctl.scala 693:41] + node _T_8000 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8001 = eq(_T_8000, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8002 = and(ic_valid_ff, _T_8001) @[ifu_mem_ctl.scala 693:97] + node _T_8003 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8004 = and(_T_8002, _T_8003) @[ifu_mem_ctl.scala 693:122] + node _T_8005 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 694:37] + node _T_8006 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8007 = and(_T_8005, _T_8006) @[ifu_mem_ctl.scala 694:59] + node _T_8008 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 694:102] + node _T_8009 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8010 = and(_T_8008, _T_8009) @[ifu_mem_ctl.scala 694:124] + node _T_8011 = or(_T_8007, _T_8010) @[ifu_mem_ctl.scala 694:81] + node _T_8012 = or(_T_8011, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8013 = bits(_T_8012, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8014 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8013 : @[Reg.scala 28:19] _T_8014 <= _T_8004 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][94] <= _T_8014 @[ifu_mem_ctl.scala 685:41] - node _T_8015 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8016 = eq(_T_8015, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8017 = and(ic_valid_ff, _T_8016) @[ifu_mem_ctl.scala 685:97] - node _T_8018 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8019 = and(_T_8017, _T_8018) @[ifu_mem_ctl.scala 685:122] - node _T_8020 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 686:37] - node _T_8021 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8022 = and(_T_8020, _T_8021) @[ifu_mem_ctl.scala 686:59] - node _T_8023 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 686:102] - node _T_8024 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8025 = and(_T_8023, _T_8024) @[ifu_mem_ctl.scala 686:124] - node _T_8026 = or(_T_8022, _T_8025) @[ifu_mem_ctl.scala 686:81] - node _T_8027 = or(_T_8026, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8028 = bits(_T_8027, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][94] <= _T_8014 @[ifu_mem_ctl.scala 693:41] + node _T_8015 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8016 = eq(_T_8015, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8017 = and(ic_valid_ff, _T_8016) @[ifu_mem_ctl.scala 693:97] + node _T_8018 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8019 = and(_T_8017, _T_8018) @[ifu_mem_ctl.scala 693:122] + node _T_8020 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 694:37] + node _T_8021 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8022 = and(_T_8020, _T_8021) @[ifu_mem_ctl.scala 694:59] + node _T_8023 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 694:102] + node _T_8024 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8025 = and(_T_8023, _T_8024) @[ifu_mem_ctl.scala 694:124] + node _T_8026 = or(_T_8022, _T_8025) @[ifu_mem_ctl.scala 694:81] + node _T_8027 = or(_T_8026, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8028 = bits(_T_8027, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8029 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8028 : @[Reg.scala 28:19] _T_8029 <= _T_8019 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][95] <= _T_8029 @[ifu_mem_ctl.scala 685:41] - node _T_8030 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8031 = eq(_T_8030, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8032 = and(ic_valid_ff, _T_8031) @[ifu_mem_ctl.scala 685:97] - node _T_8033 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8034 = and(_T_8032, _T_8033) @[ifu_mem_ctl.scala 685:122] - node _T_8035 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 686:37] - node _T_8036 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8037 = and(_T_8035, _T_8036) @[ifu_mem_ctl.scala 686:59] - node _T_8038 = eq(perr_ic_index_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 686:102] - node _T_8039 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8040 = and(_T_8038, _T_8039) @[ifu_mem_ctl.scala 686:124] - node _T_8041 = or(_T_8037, _T_8040) @[ifu_mem_ctl.scala 686:81] - node _T_8042 = or(_T_8041, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8043 = bits(_T_8042, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][95] <= _T_8029 @[ifu_mem_ctl.scala 693:41] + node _T_8030 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8031 = eq(_T_8030, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8032 = and(ic_valid_ff, _T_8031) @[ifu_mem_ctl.scala 693:97] + node _T_8033 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8034 = and(_T_8032, _T_8033) @[ifu_mem_ctl.scala 693:122] + node _T_8035 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 694:37] + node _T_8036 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8037 = and(_T_8035, _T_8036) @[ifu_mem_ctl.scala 694:59] + node _T_8038 = eq(perr_ic_index_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 694:102] + node _T_8039 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8040 = and(_T_8038, _T_8039) @[ifu_mem_ctl.scala 694:124] + node _T_8041 = or(_T_8037, _T_8040) @[ifu_mem_ctl.scala 694:81] + node _T_8042 = or(_T_8041, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8043 = bits(_T_8042, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8044 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8043 : @[Reg.scala 28:19] _T_8044 <= _T_8034 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][96] <= _T_8044 @[ifu_mem_ctl.scala 685:41] - node _T_8045 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8046 = eq(_T_8045, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8047 = and(ic_valid_ff, _T_8046) @[ifu_mem_ctl.scala 685:97] - node _T_8048 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8049 = and(_T_8047, _T_8048) @[ifu_mem_ctl.scala 685:122] - node _T_8050 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 686:37] - node _T_8051 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8052 = and(_T_8050, _T_8051) @[ifu_mem_ctl.scala 686:59] - node _T_8053 = eq(perr_ic_index_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 686:102] - node _T_8054 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8055 = and(_T_8053, _T_8054) @[ifu_mem_ctl.scala 686:124] - node _T_8056 = or(_T_8052, _T_8055) @[ifu_mem_ctl.scala 686:81] - node _T_8057 = or(_T_8056, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8058 = bits(_T_8057, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][96] <= _T_8044 @[ifu_mem_ctl.scala 693:41] + node _T_8045 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8046 = eq(_T_8045, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8047 = and(ic_valid_ff, _T_8046) @[ifu_mem_ctl.scala 693:97] + node _T_8048 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8049 = and(_T_8047, _T_8048) @[ifu_mem_ctl.scala 693:122] + node _T_8050 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 694:37] + node _T_8051 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8052 = and(_T_8050, _T_8051) @[ifu_mem_ctl.scala 694:59] + node _T_8053 = eq(perr_ic_index_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 694:102] + node _T_8054 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8055 = and(_T_8053, _T_8054) @[ifu_mem_ctl.scala 694:124] + node _T_8056 = or(_T_8052, _T_8055) @[ifu_mem_ctl.scala 694:81] + node _T_8057 = or(_T_8056, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8058 = bits(_T_8057, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8059 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8058 : @[Reg.scala 28:19] _T_8059 <= _T_8049 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][97] <= _T_8059 @[ifu_mem_ctl.scala 685:41] - node _T_8060 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8061 = eq(_T_8060, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8062 = and(ic_valid_ff, _T_8061) @[ifu_mem_ctl.scala 685:97] - node _T_8063 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8064 = and(_T_8062, _T_8063) @[ifu_mem_ctl.scala 685:122] - node _T_8065 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 686:37] - node _T_8066 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8067 = and(_T_8065, _T_8066) @[ifu_mem_ctl.scala 686:59] - node _T_8068 = eq(perr_ic_index_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 686:102] - node _T_8069 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8070 = and(_T_8068, _T_8069) @[ifu_mem_ctl.scala 686:124] - node _T_8071 = or(_T_8067, _T_8070) @[ifu_mem_ctl.scala 686:81] - node _T_8072 = or(_T_8071, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8073 = bits(_T_8072, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][97] <= _T_8059 @[ifu_mem_ctl.scala 693:41] + node _T_8060 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8061 = eq(_T_8060, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8062 = and(ic_valid_ff, _T_8061) @[ifu_mem_ctl.scala 693:97] + node _T_8063 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8064 = and(_T_8062, _T_8063) @[ifu_mem_ctl.scala 693:122] + node _T_8065 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 694:37] + node _T_8066 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8067 = and(_T_8065, _T_8066) @[ifu_mem_ctl.scala 694:59] + node _T_8068 = eq(perr_ic_index_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 694:102] + node _T_8069 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8070 = and(_T_8068, _T_8069) @[ifu_mem_ctl.scala 694:124] + node _T_8071 = or(_T_8067, _T_8070) @[ifu_mem_ctl.scala 694:81] + node _T_8072 = or(_T_8071, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8073 = bits(_T_8072, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8074 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8073 : @[Reg.scala 28:19] _T_8074 <= _T_8064 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][98] <= _T_8074 @[ifu_mem_ctl.scala 685:41] - node _T_8075 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8076 = eq(_T_8075, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8077 = and(ic_valid_ff, _T_8076) @[ifu_mem_ctl.scala 685:97] - node _T_8078 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8079 = and(_T_8077, _T_8078) @[ifu_mem_ctl.scala 685:122] - node _T_8080 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 686:37] - node _T_8081 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8082 = and(_T_8080, _T_8081) @[ifu_mem_ctl.scala 686:59] - node _T_8083 = eq(perr_ic_index_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 686:102] - node _T_8084 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8085 = and(_T_8083, _T_8084) @[ifu_mem_ctl.scala 686:124] - node _T_8086 = or(_T_8082, _T_8085) @[ifu_mem_ctl.scala 686:81] - node _T_8087 = or(_T_8086, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8088 = bits(_T_8087, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][98] <= _T_8074 @[ifu_mem_ctl.scala 693:41] + node _T_8075 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8076 = eq(_T_8075, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8077 = and(ic_valid_ff, _T_8076) @[ifu_mem_ctl.scala 693:97] + node _T_8078 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8079 = and(_T_8077, _T_8078) @[ifu_mem_ctl.scala 693:122] + node _T_8080 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 694:37] + node _T_8081 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8082 = and(_T_8080, _T_8081) @[ifu_mem_ctl.scala 694:59] + node _T_8083 = eq(perr_ic_index_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 694:102] + node _T_8084 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8085 = and(_T_8083, _T_8084) @[ifu_mem_ctl.scala 694:124] + node _T_8086 = or(_T_8082, _T_8085) @[ifu_mem_ctl.scala 694:81] + node _T_8087 = or(_T_8086, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8088 = bits(_T_8087, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8089 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8088 : @[Reg.scala 28:19] _T_8089 <= _T_8079 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][99] <= _T_8089 @[ifu_mem_ctl.scala 685:41] - node _T_8090 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8091 = eq(_T_8090, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8092 = and(ic_valid_ff, _T_8091) @[ifu_mem_ctl.scala 685:97] - node _T_8093 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8094 = and(_T_8092, _T_8093) @[ifu_mem_ctl.scala 685:122] - node _T_8095 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 686:37] - node _T_8096 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8097 = and(_T_8095, _T_8096) @[ifu_mem_ctl.scala 686:59] - node _T_8098 = eq(perr_ic_index_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 686:102] - node _T_8099 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8100 = and(_T_8098, _T_8099) @[ifu_mem_ctl.scala 686:124] - node _T_8101 = or(_T_8097, _T_8100) @[ifu_mem_ctl.scala 686:81] - node _T_8102 = or(_T_8101, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8103 = bits(_T_8102, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][99] <= _T_8089 @[ifu_mem_ctl.scala 693:41] + node _T_8090 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8091 = eq(_T_8090, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8092 = and(ic_valid_ff, _T_8091) @[ifu_mem_ctl.scala 693:97] + node _T_8093 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8094 = and(_T_8092, _T_8093) @[ifu_mem_ctl.scala 693:122] + node _T_8095 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 694:37] + node _T_8096 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8097 = and(_T_8095, _T_8096) @[ifu_mem_ctl.scala 694:59] + node _T_8098 = eq(perr_ic_index_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 694:102] + node _T_8099 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8100 = and(_T_8098, _T_8099) @[ifu_mem_ctl.scala 694:124] + node _T_8101 = or(_T_8097, _T_8100) @[ifu_mem_ctl.scala 694:81] + node _T_8102 = or(_T_8101, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8103 = bits(_T_8102, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8104 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8103 : @[Reg.scala 28:19] _T_8104 <= _T_8094 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][100] <= _T_8104 @[ifu_mem_ctl.scala 685:41] - node _T_8105 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8106 = eq(_T_8105, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8107 = and(ic_valid_ff, _T_8106) @[ifu_mem_ctl.scala 685:97] - node _T_8108 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8109 = and(_T_8107, _T_8108) @[ifu_mem_ctl.scala 685:122] - node _T_8110 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 686:37] - node _T_8111 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8112 = and(_T_8110, _T_8111) @[ifu_mem_ctl.scala 686:59] - node _T_8113 = eq(perr_ic_index_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 686:102] - node _T_8114 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8115 = and(_T_8113, _T_8114) @[ifu_mem_ctl.scala 686:124] - node _T_8116 = or(_T_8112, _T_8115) @[ifu_mem_ctl.scala 686:81] - node _T_8117 = or(_T_8116, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8118 = bits(_T_8117, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][100] <= _T_8104 @[ifu_mem_ctl.scala 693:41] + node _T_8105 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8106 = eq(_T_8105, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8107 = and(ic_valid_ff, _T_8106) @[ifu_mem_ctl.scala 693:97] + node _T_8108 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8109 = and(_T_8107, _T_8108) @[ifu_mem_ctl.scala 693:122] + node _T_8110 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 694:37] + node _T_8111 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8112 = and(_T_8110, _T_8111) @[ifu_mem_ctl.scala 694:59] + node _T_8113 = eq(perr_ic_index_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 694:102] + node _T_8114 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8115 = and(_T_8113, _T_8114) @[ifu_mem_ctl.scala 694:124] + node _T_8116 = or(_T_8112, _T_8115) @[ifu_mem_ctl.scala 694:81] + node _T_8117 = or(_T_8116, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8118 = bits(_T_8117, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8119 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8118 : @[Reg.scala 28:19] _T_8119 <= _T_8109 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][101] <= _T_8119 @[ifu_mem_ctl.scala 685:41] - node _T_8120 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8121 = eq(_T_8120, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8122 = and(ic_valid_ff, _T_8121) @[ifu_mem_ctl.scala 685:97] - node _T_8123 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8124 = and(_T_8122, _T_8123) @[ifu_mem_ctl.scala 685:122] - node _T_8125 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 686:37] - node _T_8126 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8127 = and(_T_8125, _T_8126) @[ifu_mem_ctl.scala 686:59] - node _T_8128 = eq(perr_ic_index_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 686:102] - node _T_8129 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8130 = and(_T_8128, _T_8129) @[ifu_mem_ctl.scala 686:124] - node _T_8131 = or(_T_8127, _T_8130) @[ifu_mem_ctl.scala 686:81] - node _T_8132 = or(_T_8131, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8133 = bits(_T_8132, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][101] <= _T_8119 @[ifu_mem_ctl.scala 693:41] + node _T_8120 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8121 = eq(_T_8120, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8122 = and(ic_valid_ff, _T_8121) @[ifu_mem_ctl.scala 693:97] + node _T_8123 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8124 = and(_T_8122, _T_8123) @[ifu_mem_ctl.scala 693:122] + node _T_8125 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 694:37] + node _T_8126 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8127 = and(_T_8125, _T_8126) @[ifu_mem_ctl.scala 694:59] + node _T_8128 = eq(perr_ic_index_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 694:102] + node _T_8129 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8130 = and(_T_8128, _T_8129) @[ifu_mem_ctl.scala 694:124] + node _T_8131 = or(_T_8127, _T_8130) @[ifu_mem_ctl.scala 694:81] + node _T_8132 = or(_T_8131, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8133 = bits(_T_8132, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8134 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8133 : @[Reg.scala 28:19] _T_8134 <= _T_8124 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][102] <= _T_8134 @[ifu_mem_ctl.scala 685:41] - node _T_8135 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8136 = eq(_T_8135, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8137 = and(ic_valid_ff, _T_8136) @[ifu_mem_ctl.scala 685:97] - node _T_8138 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8139 = and(_T_8137, _T_8138) @[ifu_mem_ctl.scala 685:122] - node _T_8140 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 686:37] - node _T_8141 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8142 = and(_T_8140, _T_8141) @[ifu_mem_ctl.scala 686:59] - node _T_8143 = eq(perr_ic_index_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 686:102] - node _T_8144 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8145 = and(_T_8143, _T_8144) @[ifu_mem_ctl.scala 686:124] - node _T_8146 = or(_T_8142, _T_8145) @[ifu_mem_ctl.scala 686:81] - node _T_8147 = or(_T_8146, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8148 = bits(_T_8147, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][102] <= _T_8134 @[ifu_mem_ctl.scala 693:41] + node _T_8135 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8136 = eq(_T_8135, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8137 = and(ic_valid_ff, _T_8136) @[ifu_mem_ctl.scala 693:97] + node _T_8138 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8139 = and(_T_8137, _T_8138) @[ifu_mem_ctl.scala 693:122] + node _T_8140 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 694:37] + node _T_8141 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8142 = and(_T_8140, _T_8141) @[ifu_mem_ctl.scala 694:59] + node _T_8143 = eq(perr_ic_index_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 694:102] + node _T_8144 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8145 = and(_T_8143, _T_8144) @[ifu_mem_ctl.scala 694:124] + node _T_8146 = or(_T_8142, _T_8145) @[ifu_mem_ctl.scala 694:81] + node _T_8147 = or(_T_8146, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8148 = bits(_T_8147, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8149 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8148 : @[Reg.scala 28:19] _T_8149 <= _T_8139 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][103] <= _T_8149 @[ifu_mem_ctl.scala 685:41] - node _T_8150 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8151 = eq(_T_8150, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8152 = and(ic_valid_ff, _T_8151) @[ifu_mem_ctl.scala 685:97] - node _T_8153 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8154 = and(_T_8152, _T_8153) @[ifu_mem_ctl.scala 685:122] - node _T_8155 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 686:37] - node _T_8156 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8157 = and(_T_8155, _T_8156) @[ifu_mem_ctl.scala 686:59] - node _T_8158 = eq(perr_ic_index_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 686:102] - node _T_8159 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8160 = and(_T_8158, _T_8159) @[ifu_mem_ctl.scala 686:124] - node _T_8161 = or(_T_8157, _T_8160) @[ifu_mem_ctl.scala 686:81] - node _T_8162 = or(_T_8161, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8163 = bits(_T_8162, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][103] <= _T_8149 @[ifu_mem_ctl.scala 693:41] + node _T_8150 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8151 = eq(_T_8150, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8152 = and(ic_valid_ff, _T_8151) @[ifu_mem_ctl.scala 693:97] + node _T_8153 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8154 = and(_T_8152, _T_8153) @[ifu_mem_ctl.scala 693:122] + node _T_8155 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 694:37] + node _T_8156 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8157 = and(_T_8155, _T_8156) @[ifu_mem_ctl.scala 694:59] + node _T_8158 = eq(perr_ic_index_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 694:102] + node _T_8159 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8160 = and(_T_8158, _T_8159) @[ifu_mem_ctl.scala 694:124] + node _T_8161 = or(_T_8157, _T_8160) @[ifu_mem_ctl.scala 694:81] + node _T_8162 = or(_T_8161, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8163 = bits(_T_8162, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8164 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8163 : @[Reg.scala 28:19] _T_8164 <= _T_8154 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][104] <= _T_8164 @[ifu_mem_ctl.scala 685:41] - node _T_8165 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8166 = eq(_T_8165, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8167 = and(ic_valid_ff, _T_8166) @[ifu_mem_ctl.scala 685:97] - node _T_8168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8169 = and(_T_8167, _T_8168) @[ifu_mem_ctl.scala 685:122] - node _T_8170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 686:37] - node _T_8171 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8172 = and(_T_8170, _T_8171) @[ifu_mem_ctl.scala 686:59] - node _T_8173 = eq(perr_ic_index_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 686:102] - node _T_8174 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8175 = and(_T_8173, _T_8174) @[ifu_mem_ctl.scala 686:124] - node _T_8176 = or(_T_8172, _T_8175) @[ifu_mem_ctl.scala 686:81] - node _T_8177 = or(_T_8176, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8178 = bits(_T_8177, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][104] <= _T_8164 @[ifu_mem_ctl.scala 693:41] + node _T_8165 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8166 = eq(_T_8165, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8167 = and(ic_valid_ff, _T_8166) @[ifu_mem_ctl.scala 693:97] + node _T_8168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8169 = and(_T_8167, _T_8168) @[ifu_mem_ctl.scala 693:122] + node _T_8170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 694:37] + node _T_8171 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8172 = and(_T_8170, _T_8171) @[ifu_mem_ctl.scala 694:59] + node _T_8173 = eq(perr_ic_index_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 694:102] + node _T_8174 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8175 = and(_T_8173, _T_8174) @[ifu_mem_ctl.scala 694:124] + node _T_8176 = or(_T_8172, _T_8175) @[ifu_mem_ctl.scala 694:81] + node _T_8177 = or(_T_8176, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8178 = bits(_T_8177, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8179 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8178 : @[Reg.scala 28:19] _T_8179 <= _T_8169 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][105] <= _T_8179 @[ifu_mem_ctl.scala 685:41] - node _T_8180 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8181 = eq(_T_8180, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8182 = and(ic_valid_ff, _T_8181) @[ifu_mem_ctl.scala 685:97] - node _T_8183 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8184 = and(_T_8182, _T_8183) @[ifu_mem_ctl.scala 685:122] - node _T_8185 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 686:37] - node _T_8186 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8187 = and(_T_8185, _T_8186) @[ifu_mem_ctl.scala 686:59] - node _T_8188 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 686:102] - node _T_8189 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8190 = and(_T_8188, _T_8189) @[ifu_mem_ctl.scala 686:124] - node _T_8191 = or(_T_8187, _T_8190) @[ifu_mem_ctl.scala 686:81] - node _T_8192 = or(_T_8191, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8193 = bits(_T_8192, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][105] <= _T_8179 @[ifu_mem_ctl.scala 693:41] + node _T_8180 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8181 = eq(_T_8180, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8182 = and(ic_valid_ff, _T_8181) @[ifu_mem_ctl.scala 693:97] + node _T_8183 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8184 = and(_T_8182, _T_8183) @[ifu_mem_ctl.scala 693:122] + node _T_8185 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 694:37] + node _T_8186 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8187 = and(_T_8185, _T_8186) @[ifu_mem_ctl.scala 694:59] + node _T_8188 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 694:102] + node _T_8189 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8190 = and(_T_8188, _T_8189) @[ifu_mem_ctl.scala 694:124] + node _T_8191 = or(_T_8187, _T_8190) @[ifu_mem_ctl.scala 694:81] + node _T_8192 = or(_T_8191, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8193 = bits(_T_8192, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8194 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8193 : @[Reg.scala 28:19] _T_8194 <= _T_8184 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][106] <= _T_8194 @[ifu_mem_ctl.scala 685:41] - node _T_8195 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8196 = eq(_T_8195, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8197 = and(ic_valid_ff, _T_8196) @[ifu_mem_ctl.scala 685:97] - node _T_8198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8199 = and(_T_8197, _T_8198) @[ifu_mem_ctl.scala 685:122] - node _T_8200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 686:37] - node _T_8201 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8202 = and(_T_8200, _T_8201) @[ifu_mem_ctl.scala 686:59] - node _T_8203 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 686:102] - node _T_8204 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8205 = and(_T_8203, _T_8204) @[ifu_mem_ctl.scala 686:124] - node _T_8206 = or(_T_8202, _T_8205) @[ifu_mem_ctl.scala 686:81] - node _T_8207 = or(_T_8206, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8208 = bits(_T_8207, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][106] <= _T_8194 @[ifu_mem_ctl.scala 693:41] + node _T_8195 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8196 = eq(_T_8195, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8197 = and(ic_valid_ff, _T_8196) @[ifu_mem_ctl.scala 693:97] + node _T_8198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8199 = and(_T_8197, _T_8198) @[ifu_mem_ctl.scala 693:122] + node _T_8200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 694:37] + node _T_8201 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8202 = and(_T_8200, _T_8201) @[ifu_mem_ctl.scala 694:59] + node _T_8203 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 694:102] + node _T_8204 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8205 = and(_T_8203, _T_8204) @[ifu_mem_ctl.scala 694:124] + node _T_8206 = or(_T_8202, _T_8205) @[ifu_mem_ctl.scala 694:81] + node _T_8207 = or(_T_8206, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8208 = bits(_T_8207, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8209 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8208 : @[Reg.scala 28:19] _T_8209 <= _T_8199 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][107] <= _T_8209 @[ifu_mem_ctl.scala 685:41] - node _T_8210 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8211 = eq(_T_8210, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8212 = and(ic_valid_ff, _T_8211) @[ifu_mem_ctl.scala 685:97] - node _T_8213 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8214 = and(_T_8212, _T_8213) @[ifu_mem_ctl.scala 685:122] - node _T_8215 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 686:37] - node _T_8216 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8217 = and(_T_8215, _T_8216) @[ifu_mem_ctl.scala 686:59] - node _T_8218 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 686:102] - node _T_8219 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8220 = and(_T_8218, _T_8219) @[ifu_mem_ctl.scala 686:124] - node _T_8221 = or(_T_8217, _T_8220) @[ifu_mem_ctl.scala 686:81] - node _T_8222 = or(_T_8221, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8223 = bits(_T_8222, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][107] <= _T_8209 @[ifu_mem_ctl.scala 693:41] + node _T_8210 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8211 = eq(_T_8210, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8212 = and(ic_valid_ff, _T_8211) @[ifu_mem_ctl.scala 693:97] + node _T_8213 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8214 = and(_T_8212, _T_8213) @[ifu_mem_ctl.scala 693:122] + node _T_8215 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 694:37] + node _T_8216 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8217 = and(_T_8215, _T_8216) @[ifu_mem_ctl.scala 694:59] + node _T_8218 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 694:102] + node _T_8219 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8220 = and(_T_8218, _T_8219) @[ifu_mem_ctl.scala 694:124] + node _T_8221 = or(_T_8217, _T_8220) @[ifu_mem_ctl.scala 694:81] + node _T_8222 = or(_T_8221, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8223 = bits(_T_8222, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8224 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8223 : @[Reg.scala 28:19] _T_8224 <= _T_8214 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][108] <= _T_8224 @[ifu_mem_ctl.scala 685:41] - node _T_8225 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8226 = eq(_T_8225, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8227 = and(ic_valid_ff, _T_8226) @[ifu_mem_ctl.scala 685:97] - node _T_8228 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8229 = and(_T_8227, _T_8228) @[ifu_mem_ctl.scala 685:122] - node _T_8230 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 686:37] - node _T_8231 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8232 = and(_T_8230, _T_8231) @[ifu_mem_ctl.scala 686:59] - node _T_8233 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 686:102] - node _T_8234 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8235 = and(_T_8233, _T_8234) @[ifu_mem_ctl.scala 686:124] - node _T_8236 = or(_T_8232, _T_8235) @[ifu_mem_ctl.scala 686:81] - node _T_8237 = or(_T_8236, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8238 = bits(_T_8237, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][108] <= _T_8224 @[ifu_mem_ctl.scala 693:41] + node _T_8225 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8226 = eq(_T_8225, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8227 = and(ic_valid_ff, _T_8226) @[ifu_mem_ctl.scala 693:97] + node _T_8228 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8229 = and(_T_8227, _T_8228) @[ifu_mem_ctl.scala 693:122] + node _T_8230 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 694:37] + node _T_8231 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8232 = and(_T_8230, _T_8231) @[ifu_mem_ctl.scala 694:59] + node _T_8233 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 694:102] + node _T_8234 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8235 = and(_T_8233, _T_8234) @[ifu_mem_ctl.scala 694:124] + node _T_8236 = or(_T_8232, _T_8235) @[ifu_mem_ctl.scala 694:81] + node _T_8237 = or(_T_8236, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8238 = bits(_T_8237, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8239 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8238 : @[Reg.scala 28:19] _T_8239 <= _T_8229 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][109] <= _T_8239 @[ifu_mem_ctl.scala 685:41] - node _T_8240 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8241 = eq(_T_8240, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8242 = and(ic_valid_ff, _T_8241) @[ifu_mem_ctl.scala 685:97] - node _T_8243 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8244 = and(_T_8242, _T_8243) @[ifu_mem_ctl.scala 685:122] - node _T_8245 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 686:37] - node _T_8246 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8247 = and(_T_8245, _T_8246) @[ifu_mem_ctl.scala 686:59] - node _T_8248 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 686:102] - node _T_8249 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8250 = and(_T_8248, _T_8249) @[ifu_mem_ctl.scala 686:124] - node _T_8251 = or(_T_8247, _T_8250) @[ifu_mem_ctl.scala 686:81] - node _T_8252 = or(_T_8251, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8253 = bits(_T_8252, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][109] <= _T_8239 @[ifu_mem_ctl.scala 693:41] + node _T_8240 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8241 = eq(_T_8240, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8242 = and(ic_valid_ff, _T_8241) @[ifu_mem_ctl.scala 693:97] + node _T_8243 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8244 = and(_T_8242, _T_8243) @[ifu_mem_ctl.scala 693:122] + node _T_8245 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 694:37] + node _T_8246 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8247 = and(_T_8245, _T_8246) @[ifu_mem_ctl.scala 694:59] + node _T_8248 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 694:102] + node _T_8249 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8250 = and(_T_8248, _T_8249) @[ifu_mem_ctl.scala 694:124] + node _T_8251 = or(_T_8247, _T_8250) @[ifu_mem_ctl.scala 694:81] + node _T_8252 = or(_T_8251, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8253 = bits(_T_8252, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8254 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8253 : @[Reg.scala 28:19] _T_8254 <= _T_8244 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][110] <= _T_8254 @[ifu_mem_ctl.scala 685:41] - node _T_8255 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8256 = eq(_T_8255, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8257 = and(ic_valid_ff, _T_8256) @[ifu_mem_ctl.scala 685:97] - node _T_8258 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8259 = and(_T_8257, _T_8258) @[ifu_mem_ctl.scala 685:122] - node _T_8260 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 686:37] - node _T_8261 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8262 = and(_T_8260, _T_8261) @[ifu_mem_ctl.scala 686:59] - node _T_8263 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 686:102] - node _T_8264 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8265 = and(_T_8263, _T_8264) @[ifu_mem_ctl.scala 686:124] - node _T_8266 = or(_T_8262, _T_8265) @[ifu_mem_ctl.scala 686:81] - node _T_8267 = or(_T_8266, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8268 = bits(_T_8267, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][110] <= _T_8254 @[ifu_mem_ctl.scala 693:41] + node _T_8255 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8256 = eq(_T_8255, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8257 = and(ic_valid_ff, _T_8256) @[ifu_mem_ctl.scala 693:97] + node _T_8258 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8259 = and(_T_8257, _T_8258) @[ifu_mem_ctl.scala 693:122] + node _T_8260 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 694:37] + node _T_8261 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8262 = and(_T_8260, _T_8261) @[ifu_mem_ctl.scala 694:59] + node _T_8263 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 694:102] + node _T_8264 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8265 = and(_T_8263, _T_8264) @[ifu_mem_ctl.scala 694:124] + node _T_8266 = or(_T_8262, _T_8265) @[ifu_mem_ctl.scala 694:81] + node _T_8267 = or(_T_8266, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8268 = bits(_T_8267, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8269 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8268 : @[Reg.scala 28:19] _T_8269 <= _T_8259 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][111] <= _T_8269 @[ifu_mem_ctl.scala 685:41] - node _T_8270 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8271 = eq(_T_8270, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8272 = and(ic_valid_ff, _T_8271) @[ifu_mem_ctl.scala 685:97] - node _T_8273 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8274 = and(_T_8272, _T_8273) @[ifu_mem_ctl.scala 685:122] - node _T_8275 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 686:37] - node _T_8276 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8277 = and(_T_8275, _T_8276) @[ifu_mem_ctl.scala 686:59] - node _T_8278 = eq(perr_ic_index_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 686:102] - node _T_8279 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8280 = and(_T_8278, _T_8279) @[ifu_mem_ctl.scala 686:124] - node _T_8281 = or(_T_8277, _T_8280) @[ifu_mem_ctl.scala 686:81] - node _T_8282 = or(_T_8281, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8283 = bits(_T_8282, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][111] <= _T_8269 @[ifu_mem_ctl.scala 693:41] + node _T_8270 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8271 = eq(_T_8270, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8272 = and(ic_valid_ff, _T_8271) @[ifu_mem_ctl.scala 693:97] + node _T_8273 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8274 = and(_T_8272, _T_8273) @[ifu_mem_ctl.scala 693:122] + node _T_8275 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 694:37] + node _T_8276 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8277 = and(_T_8275, _T_8276) @[ifu_mem_ctl.scala 694:59] + node _T_8278 = eq(perr_ic_index_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 694:102] + node _T_8279 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8280 = and(_T_8278, _T_8279) @[ifu_mem_ctl.scala 694:124] + node _T_8281 = or(_T_8277, _T_8280) @[ifu_mem_ctl.scala 694:81] + node _T_8282 = or(_T_8281, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8283 = bits(_T_8282, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8284 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8283 : @[Reg.scala 28:19] _T_8284 <= _T_8274 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][112] <= _T_8284 @[ifu_mem_ctl.scala 685:41] - node _T_8285 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8286 = eq(_T_8285, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8287 = and(ic_valid_ff, _T_8286) @[ifu_mem_ctl.scala 685:97] - node _T_8288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8289 = and(_T_8287, _T_8288) @[ifu_mem_ctl.scala 685:122] - node _T_8290 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 686:37] - node _T_8291 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8292 = and(_T_8290, _T_8291) @[ifu_mem_ctl.scala 686:59] - node _T_8293 = eq(perr_ic_index_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 686:102] - node _T_8294 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8295 = and(_T_8293, _T_8294) @[ifu_mem_ctl.scala 686:124] - node _T_8296 = or(_T_8292, _T_8295) @[ifu_mem_ctl.scala 686:81] - node _T_8297 = or(_T_8296, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8298 = bits(_T_8297, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][112] <= _T_8284 @[ifu_mem_ctl.scala 693:41] + node _T_8285 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8286 = eq(_T_8285, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8287 = and(ic_valid_ff, _T_8286) @[ifu_mem_ctl.scala 693:97] + node _T_8288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8289 = and(_T_8287, _T_8288) @[ifu_mem_ctl.scala 693:122] + node _T_8290 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 694:37] + node _T_8291 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8292 = and(_T_8290, _T_8291) @[ifu_mem_ctl.scala 694:59] + node _T_8293 = eq(perr_ic_index_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 694:102] + node _T_8294 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8295 = and(_T_8293, _T_8294) @[ifu_mem_ctl.scala 694:124] + node _T_8296 = or(_T_8292, _T_8295) @[ifu_mem_ctl.scala 694:81] + node _T_8297 = or(_T_8296, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8298 = bits(_T_8297, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8299 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8298 : @[Reg.scala 28:19] _T_8299 <= _T_8289 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][113] <= _T_8299 @[ifu_mem_ctl.scala 685:41] - node _T_8300 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8301 = eq(_T_8300, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8302 = and(ic_valid_ff, _T_8301) @[ifu_mem_ctl.scala 685:97] - node _T_8303 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8304 = and(_T_8302, _T_8303) @[ifu_mem_ctl.scala 685:122] - node _T_8305 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 686:37] - node _T_8306 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8307 = and(_T_8305, _T_8306) @[ifu_mem_ctl.scala 686:59] - node _T_8308 = eq(perr_ic_index_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 686:102] - node _T_8309 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8310 = and(_T_8308, _T_8309) @[ifu_mem_ctl.scala 686:124] - node _T_8311 = or(_T_8307, _T_8310) @[ifu_mem_ctl.scala 686:81] - node _T_8312 = or(_T_8311, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8313 = bits(_T_8312, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][113] <= _T_8299 @[ifu_mem_ctl.scala 693:41] + node _T_8300 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8301 = eq(_T_8300, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8302 = and(ic_valid_ff, _T_8301) @[ifu_mem_ctl.scala 693:97] + node _T_8303 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8304 = and(_T_8302, _T_8303) @[ifu_mem_ctl.scala 693:122] + node _T_8305 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 694:37] + node _T_8306 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8307 = and(_T_8305, _T_8306) @[ifu_mem_ctl.scala 694:59] + node _T_8308 = eq(perr_ic_index_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 694:102] + node _T_8309 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8310 = and(_T_8308, _T_8309) @[ifu_mem_ctl.scala 694:124] + node _T_8311 = or(_T_8307, _T_8310) @[ifu_mem_ctl.scala 694:81] + node _T_8312 = or(_T_8311, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8313 = bits(_T_8312, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8314 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8313 : @[Reg.scala 28:19] _T_8314 <= _T_8304 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][114] <= _T_8314 @[ifu_mem_ctl.scala 685:41] - node _T_8315 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8316 = eq(_T_8315, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8317 = and(ic_valid_ff, _T_8316) @[ifu_mem_ctl.scala 685:97] - node _T_8318 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8319 = and(_T_8317, _T_8318) @[ifu_mem_ctl.scala 685:122] - node _T_8320 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 686:37] - node _T_8321 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8322 = and(_T_8320, _T_8321) @[ifu_mem_ctl.scala 686:59] - node _T_8323 = eq(perr_ic_index_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 686:102] - node _T_8324 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8325 = and(_T_8323, _T_8324) @[ifu_mem_ctl.scala 686:124] - node _T_8326 = or(_T_8322, _T_8325) @[ifu_mem_ctl.scala 686:81] - node _T_8327 = or(_T_8326, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8328 = bits(_T_8327, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][114] <= _T_8314 @[ifu_mem_ctl.scala 693:41] + node _T_8315 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8316 = eq(_T_8315, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8317 = and(ic_valid_ff, _T_8316) @[ifu_mem_ctl.scala 693:97] + node _T_8318 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8319 = and(_T_8317, _T_8318) @[ifu_mem_ctl.scala 693:122] + node _T_8320 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 694:37] + node _T_8321 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8322 = and(_T_8320, _T_8321) @[ifu_mem_ctl.scala 694:59] + node _T_8323 = eq(perr_ic_index_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 694:102] + node _T_8324 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8325 = and(_T_8323, _T_8324) @[ifu_mem_ctl.scala 694:124] + node _T_8326 = or(_T_8322, _T_8325) @[ifu_mem_ctl.scala 694:81] + node _T_8327 = or(_T_8326, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8328 = bits(_T_8327, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8329 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8328 : @[Reg.scala 28:19] _T_8329 <= _T_8319 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][115] <= _T_8329 @[ifu_mem_ctl.scala 685:41] - node _T_8330 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8331 = eq(_T_8330, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8332 = and(ic_valid_ff, _T_8331) @[ifu_mem_ctl.scala 685:97] - node _T_8333 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8334 = and(_T_8332, _T_8333) @[ifu_mem_ctl.scala 685:122] - node _T_8335 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 686:37] - node _T_8336 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8337 = and(_T_8335, _T_8336) @[ifu_mem_ctl.scala 686:59] - node _T_8338 = eq(perr_ic_index_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 686:102] - node _T_8339 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8340 = and(_T_8338, _T_8339) @[ifu_mem_ctl.scala 686:124] - node _T_8341 = or(_T_8337, _T_8340) @[ifu_mem_ctl.scala 686:81] - node _T_8342 = or(_T_8341, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8343 = bits(_T_8342, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][115] <= _T_8329 @[ifu_mem_ctl.scala 693:41] + node _T_8330 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8331 = eq(_T_8330, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8332 = and(ic_valid_ff, _T_8331) @[ifu_mem_ctl.scala 693:97] + node _T_8333 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8334 = and(_T_8332, _T_8333) @[ifu_mem_ctl.scala 693:122] + node _T_8335 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 694:37] + node _T_8336 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8337 = and(_T_8335, _T_8336) @[ifu_mem_ctl.scala 694:59] + node _T_8338 = eq(perr_ic_index_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 694:102] + node _T_8339 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8340 = and(_T_8338, _T_8339) @[ifu_mem_ctl.scala 694:124] + node _T_8341 = or(_T_8337, _T_8340) @[ifu_mem_ctl.scala 694:81] + node _T_8342 = or(_T_8341, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8343 = bits(_T_8342, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8344 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8343 : @[Reg.scala 28:19] _T_8344 <= _T_8334 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][116] <= _T_8344 @[ifu_mem_ctl.scala 685:41] - node _T_8345 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8346 = eq(_T_8345, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8347 = and(ic_valid_ff, _T_8346) @[ifu_mem_ctl.scala 685:97] - node _T_8348 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8349 = and(_T_8347, _T_8348) @[ifu_mem_ctl.scala 685:122] - node _T_8350 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 686:37] - node _T_8351 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8352 = and(_T_8350, _T_8351) @[ifu_mem_ctl.scala 686:59] - node _T_8353 = eq(perr_ic_index_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 686:102] - node _T_8354 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8355 = and(_T_8353, _T_8354) @[ifu_mem_ctl.scala 686:124] - node _T_8356 = or(_T_8352, _T_8355) @[ifu_mem_ctl.scala 686:81] - node _T_8357 = or(_T_8356, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8358 = bits(_T_8357, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][116] <= _T_8344 @[ifu_mem_ctl.scala 693:41] + node _T_8345 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8346 = eq(_T_8345, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8347 = and(ic_valid_ff, _T_8346) @[ifu_mem_ctl.scala 693:97] + node _T_8348 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8349 = and(_T_8347, _T_8348) @[ifu_mem_ctl.scala 693:122] + node _T_8350 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 694:37] + node _T_8351 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8352 = and(_T_8350, _T_8351) @[ifu_mem_ctl.scala 694:59] + node _T_8353 = eq(perr_ic_index_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 694:102] + node _T_8354 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8355 = and(_T_8353, _T_8354) @[ifu_mem_ctl.scala 694:124] + node _T_8356 = or(_T_8352, _T_8355) @[ifu_mem_ctl.scala 694:81] + node _T_8357 = or(_T_8356, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8358 = bits(_T_8357, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8359 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8358 : @[Reg.scala 28:19] _T_8359 <= _T_8349 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][117] <= _T_8359 @[ifu_mem_ctl.scala 685:41] - node _T_8360 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8361 = eq(_T_8360, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8362 = and(ic_valid_ff, _T_8361) @[ifu_mem_ctl.scala 685:97] - node _T_8363 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8364 = and(_T_8362, _T_8363) @[ifu_mem_ctl.scala 685:122] - node _T_8365 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 686:37] - node _T_8366 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8367 = and(_T_8365, _T_8366) @[ifu_mem_ctl.scala 686:59] - node _T_8368 = eq(perr_ic_index_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 686:102] - node _T_8369 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8370 = and(_T_8368, _T_8369) @[ifu_mem_ctl.scala 686:124] - node _T_8371 = or(_T_8367, _T_8370) @[ifu_mem_ctl.scala 686:81] - node _T_8372 = or(_T_8371, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8373 = bits(_T_8372, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][117] <= _T_8359 @[ifu_mem_ctl.scala 693:41] + node _T_8360 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8361 = eq(_T_8360, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8362 = and(ic_valid_ff, _T_8361) @[ifu_mem_ctl.scala 693:97] + node _T_8363 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8364 = and(_T_8362, _T_8363) @[ifu_mem_ctl.scala 693:122] + node _T_8365 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 694:37] + node _T_8366 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8367 = and(_T_8365, _T_8366) @[ifu_mem_ctl.scala 694:59] + node _T_8368 = eq(perr_ic_index_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 694:102] + node _T_8369 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8370 = and(_T_8368, _T_8369) @[ifu_mem_ctl.scala 694:124] + node _T_8371 = or(_T_8367, _T_8370) @[ifu_mem_ctl.scala 694:81] + node _T_8372 = or(_T_8371, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8373 = bits(_T_8372, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8374 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8373 : @[Reg.scala 28:19] _T_8374 <= _T_8364 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][118] <= _T_8374 @[ifu_mem_ctl.scala 685:41] - node _T_8375 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8376 = eq(_T_8375, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8377 = and(ic_valid_ff, _T_8376) @[ifu_mem_ctl.scala 685:97] - node _T_8378 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8379 = and(_T_8377, _T_8378) @[ifu_mem_ctl.scala 685:122] - node _T_8380 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 686:37] - node _T_8381 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8382 = and(_T_8380, _T_8381) @[ifu_mem_ctl.scala 686:59] - node _T_8383 = eq(perr_ic_index_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 686:102] - node _T_8384 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8385 = and(_T_8383, _T_8384) @[ifu_mem_ctl.scala 686:124] - node _T_8386 = or(_T_8382, _T_8385) @[ifu_mem_ctl.scala 686:81] - node _T_8387 = or(_T_8386, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8388 = bits(_T_8387, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][118] <= _T_8374 @[ifu_mem_ctl.scala 693:41] + node _T_8375 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8376 = eq(_T_8375, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8377 = and(ic_valid_ff, _T_8376) @[ifu_mem_ctl.scala 693:97] + node _T_8378 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8379 = and(_T_8377, _T_8378) @[ifu_mem_ctl.scala 693:122] + node _T_8380 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 694:37] + node _T_8381 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8382 = and(_T_8380, _T_8381) @[ifu_mem_ctl.scala 694:59] + node _T_8383 = eq(perr_ic_index_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 694:102] + node _T_8384 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8385 = and(_T_8383, _T_8384) @[ifu_mem_ctl.scala 694:124] + node _T_8386 = or(_T_8382, _T_8385) @[ifu_mem_ctl.scala 694:81] + node _T_8387 = or(_T_8386, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8388 = bits(_T_8387, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8389 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8388 : @[Reg.scala 28:19] _T_8389 <= _T_8379 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][119] <= _T_8389 @[ifu_mem_ctl.scala 685:41] - node _T_8390 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8391 = eq(_T_8390, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8392 = and(ic_valid_ff, _T_8391) @[ifu_mem_ctl.scala 685:97] - node _T_8393 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8394 = and(_T_8392, _T_8393) @[ifu_mem_ctl.scala 685:122] - node _T_8395 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 686:37] - node _T_8396 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8397 = and(_T_8395, _T_8396) @[ifu_mem_ctl.scala 686:59] - node _T_8398 = eq(perr_ic_index_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 686:102] - node _T_8399 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8400 = and(_T_8398, _T_8399) @[ifu_mem_ctl.scala 686:124] - node _T_8401 = or(_T_8397, _T_8400) @[ifu_mem_ctl.scala 686:81] - node _T_8402 = or(_T_8401, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8403 = bits(_T_8402, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][119] <= _T_8389 @[ifu_mem_ctl.scala 693:41] + node _T_8390 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8391 = eq(_T_8390, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8392 = and(ic_valid_ff, _T_8391) @[ifu_mem_ctl.scala 693:97] + node _T_8393 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8394 = and(_T_8392, _T_8393) @[ifu_mem_ctl.scala 693:122] + node _T_8395 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 694:37] + node _T_8396 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8397 = and(_T_8395, _T_8396) @[ifu_mem_ctl.scala 694:59] + node _T_8398 = eq(perr_ic_index_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 694:102] + node _T_8399 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8400 = and(_T_8398, _T_8399) @[ifu_mem_ctl.scala 694:124] + node _T_8401 = or(_T_8397, _T_8400) @[ifu_mem_ctl.scala 694:81] + node _T_8402 = or(_T_8401, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8403 = bits(_T_8402, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8404 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8403 : @[Reg.scala 28:19] _T_8404 <= _T_8394 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][120] <= _T_8404 @[ifu_mem_ctl.scala 685:41] - node _T_8405 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8406 = eq(_T_8405, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8407 = and(ic_valid_ff, _T_8406) @[ifu_mem_ctl.scala 685:97] - node _T_8408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8409 = and(_T_8407, _T_8408) @[ifu_mem_ctl.scala 685:122] - node _T_8410 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 686:37] - node _T_8411 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8412 = and(_T_8410, _T_8411) @[ifu_mem_ctl.scala 686:59] - node _T_8413 = eq(perr_ic_index_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 686:102] - node _T_8414 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8415 = and(_T_8413, _T_8414) @[ifu_mem_ctl.scala 686:124] - node _T_8416 = or(_T_8412, _T_8415) @[ifu_mem_ctl.scala 686:81] - node _T_8417 = or(_T_8416, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8418 = bits(_T_8417, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][120] <= _T_8404 @[ifu_mem_ctl.scala 693:41] + node _T_8405 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8406 = eq(_T_8405, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8407 = and(ic_valid_ff, _T_8406) @[ifu_mem_ctl.scala 693:97] + node _T_8408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8409 = and(_T_8407, _T_8408) @[ifu_mem_ctl.scala 693:122] + node _T_8410 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 694:37] + node _T_8411 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8412 = and(_T_8410, _T_8411) @[ifu_mem_ctl.scala 694:59] + node _T_8413 = eq(perr_ic_index_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 694:102] + node _T_8414 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8415 = and(_T_8413, _T_8414) @[ifu_mem_ctl.scala 694:124] + node _T_8416 = or(_T_8412, _T_8415) @[ifu_mem_ctl.scala 694:81] + node _T_8417 = or(_T_8416, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8418 = bits(_T_8417, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8419 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8418 : @[Reg.scala 28:19] _T_8419 <= _T_8409 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][121] <= _T_8419 @[ifu_mem_ctl.scala 685:41] - node _T_8420 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8421 = eq(_T_8420, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8422 = and(ic_valid_ff, _T_8421) @[ifu_mem_ctl.scala 685:97] - node _T_8423 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8424 = and(_T_8422, _T_8423) @[ifu_mem_ctl.scala 685:122] - node _T_8425 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 686:37] - node _T_8426 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8427 = and(_T_8425, _T_8426) @[ifu_mem_ctl.scala 686:59] - node _T_8428 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 686:102] - node _T_8429 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8430 = and(_T_8428, _T_8429) @[ifu_mem_ctl.scala 686:124] - node _T_8431 = or(_T_8427, _T_8430) @[ifu_mem_ctl.scala 686:81] - node _T_8432 = or(_T_8431, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8433 = bits(_T_8432, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][121] <= _T_8419 @[ifu_mem_ctl.scala 693:41] + node _T_8420 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8421 = eq(_T_8420, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8422 = and(ic_valid_ff, _T_8421) @[ifu_mem_ctl.scala 693:97] + node _T_8423 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8424 = and(_T_8422, _T_8423) @[ifu_mem_ctl.scala 693:122] + node _T_8425 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 694:37] + node _T_8426 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8427 = and(_T_8425, _T_8426) @[ifu_mem_ctl.scala 694:59] + node _T_8428 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 694:102] + node _T_8429 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8430 = and(_T_8428, _T_8429) @[ifu_mem_ctl.scala 694:124] + node _T_8431 = or(_T_8427, _T_8430) @[ifu_mem_ctl.scala 694:81] + node _T_8432 = or(_T_8431, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8433 = bits(_T_8432, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8434 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8433 : @[Reg.scala 28:19] _T_8434 <= _T_8424 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][122] <= _T_8434 @[ifu_mem_ctl.scala 685:41] - node _T_8435 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8436 = eq(_T_8435, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8437 = and(ic_valid_ff, _T_8436) @[ifu_mem_ctl.scala 685:97] - node _T_8438 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8439 = and(_T_8437, _T_8438) @[ifu_mem_ctl.scala 685:122] - node _T_8440 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 686:37] - node _T_8441 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8442 = and(_T_8440, _T_8441) @[ifu_mem_ctl.scala 686:59] - node _T_8443 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 686:102] - node _T_8444 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8445 = and(_T_8443, _T_8444) @[ifu_mem_ctl.scala 686:124] - node _T_8446 = or(_T_8442, _T_8445) @[ifu_mem_ctl.scala 686:81] - node _T_8447 = or(_T_8446, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8448 = bits(_T_8447, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][122] <= _T_8434 @[ifu_mem_ctl.scala 693:41] + node _T_8435 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8436 = eq(_T_8435, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8437 = and(ic_valid_ff, _T_8436) @[ifu_mem_ctl.scala 693:97] + node _T_8438 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8439 = and(_T_8437, _T_8438) @[ifu_mem_ctl.scala 693:122] + node _T_8440 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 694:37] + node _T_8441 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8442 = and(_T_8440, _T_8441) @[ifu_mem_ctl.scala 694:59] + node _T_8443 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 694:102] + node _T_8444 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8445 = and(_T_8443, _T_8444) @[ifu_mem_ctl.scala 694:124] + node _T_8446 = or(_T_8442, _T_8445) @[ifu_mem_ctl.scala 694:81] + node _T_8447 = or(_T_8446, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8448 = bits(_T_8447, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8449 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8448 : @[Reg.scala 28:19] _T_8449 <= _T_8439 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][123] <= _T_8449 @[ifu_mem_ctl.scala 685:41] - node _T_8450 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8451 = eq(_T_8450, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8452 = and(ic_valid_ff, _T_8451) @[ifu_mem_ctl.scala 685:97] - node _T_8453 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8454 = and(_T_8452, _T_8453) @[ifu_mem_ctl.scala 685:122] - node _T_8455 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 686:37] - node _T_8456 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8457 = and(_T_8455, _T_8456) @[ifu_mem_ctl.scala 686:59] - node _T_8458 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 686:102] - node _T_8459 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8460 = and(_T_8458, _T_8459) @[ifu_mem_ctl.scala 686:124] - node _T_8461 = or(_T_8457, _T_8460) @[ifu_mem_ctl.scala 686:81] - node _T_8462 = or(_T_8461, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8463 = bits(_T_8462, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][123] <= _T_8449 @[ifu_mem_ctl.scala 693:41] + node _T_8450 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8451 = eq(_T_8450, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8452 = and(ic_valid_ff, _T_8451) @[ifu_mem_ctl.scala 693:97] + node _T_8453 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8454 = and(_T_8452, _T_8453) @[ifu_mem_ctl.scala 693:122] + node _T_8455 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 694:37] + node _T_8456 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8457 = and(_T_8455, _T_8456) @[ifu_mem_ctl.scala 694:59] + node _T_8458 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 694:102] + node _T_8459 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8460 = and(_T_8458, _T_8459) @[ifu_mem_ctl.scala 694:124] + node _T_8461 = or(_T_8457, _T_8460) @[ifu_mem_ctl.scala 694:81] + node _T_8462 = or(_T_8461, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8463 = bits(_T_8462, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8464 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8463 : @[Reg.scala 28:19] _T_8464 <= _T_8454 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][124] <= _T_8464 @[ifu_mem_ctl.scala 685:41] - node _T_8465 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8466 = eq(_T_8465, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8467 = and(ic_valid_ff, _T_8466) @[ifu_mem_ctl.scala 685:97] - node _T_8468 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8469 = and(_T_8467, _T_8468) @[ifu_mem_ctl.scala 685:122] - node _T_8470 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 686:37] - node _T_8471 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8472 = and(_T_8470, _T_8471) @[ifu_mem_ctl.scala 686:59] - node _T_8473 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 686:102] - node _T_8474 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8475 = and(_T_8473, _T_8474) @[ifu_mem_ctl.scala 686:124] - node _T_8476 = or(_T_8472, _T_8475) @[ifu_mem_ctl.scala 686:81] - node _T_8477 = or(_T_8476, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8478 = bits(_T_8477, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][124] <= _T_8464 @[ifu_mem_ctl.scala 693:41] + node _T_8465 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8466 = eq(_T_8465, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8467 = and(ic_valid_ff, _T_8466) @[ifu_mem_ctl.scala 693:97] + node _T_8468 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8469 = and(_T_8467, _T_8468) @[ifu_mem_ctl.scala 693:122] + node _T_8470 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 694:37] + node _T_8471 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8472 = and(_T_8470, _T_8471) @[ifu_mem_ctl.scala 694:59] + node _T_8473 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 694:102] + node _T_8474 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8475 = and(_T_8473, _T_8474) @[ifu_mem_ctl.scala 694:124] + node _T_8476 = or(_T_8472, _T_8475) @[ifu_mem_ctl.scala 694:81] + node _T_8477 = or(_T_8476, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8478 = bits(_T_8477, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8479 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8478 : @[Reg.scala 28:19] _T_8479 <= _T_8469 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][125] <= _T_8479 @[ifu_mem_ctl.scala 685:41] - node _T_8480 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8481 = eq(_T_8480, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8482 = and(ic_valid_ff, _T_8481) @[ifu_mem_ctl.scala 685:97] - node _T_8483 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8484 = and(_T_8482, _T_8483) @[ifu_mem_ctl.scala 685:122] - node _T_8485 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 686:37] - node _T_8486 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8487 = and(_T_8485, _T_8486) @[ifu_mem_ctl.scala 686:59] - node _T_8488 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 686:102] - node _T_8489 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8490 = and(_T_8488, _T_8489) @[ifu_mem_ctl.scala 686:124] - node _T_8491 = or(_T_8487, _T_8490) @[ifu_mem_ctl.scala 686:81] - node _T_8492 = or(_T_8491, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8493 = bits(_T_8492, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][125] <= _T_8479 @[ifu_mem_ctl.scala 693:41] + node _T_8480 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8481 = eq(_T_8480, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8482 = and(ic_valid_ff, _T_8481) @[ifu_mem_ctl.scala 693:97] + node _T_8483 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8484 = and(_T_8482, _T_8483) @[ifu_mem_ctl.scala 693:122] + node _T_8485 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 694:37] + node _T_8486 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8487 = and(_T_8485, _T_8486) @[ifu_mem_ctl.scala 694:59] + node _T_8488 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 694:102] + node _T_8489 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8490 = and(_T_8488, _T_8489) @[ifu_mem_ctl.scala 694:124] + node _T_8491 = or(_T_8487, _T_8490) @[ifu_mem_ctl.scala 694:81] + node _T_8492 = or(_T_8491, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8493 = bits(_T_8492, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8494 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8493 : @[Reg.scala 28:19] _T_8494 <= _T_8484 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][126] <= _T_8494 @[ifu_mem_ctl.scala 685:41] - node _T_8495 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8496 = eq(_T_8495, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8497 = and(ic_valid_ff, _T_8496) @[ifu_mem_ctl.scala 685:97] - node _T_8498 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8499 = and(_T_8497, _T_8498) @[ifu_mem_ctl.scala 685:122] - node _T_8500 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 686:37] - node _T_8501 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 686:76] - node _T_8502 = and(_T_8500, _T_8501) @[ifu_mem_ctl.scala 686:59] - node _T_8503 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 686:102] - node _T_8504 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 686:142] - node _T_8505 = and(_T_8503, _T_8504) @[ifu_mem_ctl.scala 686:124] - node _T_8506 = or(_T_8502, _T_8505) @[ifu_mem_ctl.scala 686:81] - node _T_8507 = or(_T_8506, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8508 = bits(_T_8507, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][126] <= _T_8494 @[ifu_mem_ctl.scala 693:41] + node _T_8495 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8496 = eq(_T_8495, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8497 = and(ic_valid_ff, _T_8496) @[ifu_mem_ctl.scala 693:97] + node _T_8498 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8499 = and(_T_8497, _T_8498) @[ifu_mem_ctl.scala 693:122] + node _T_8500 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 694:37] + node _T_8501 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] + node _T_8502 = and(_T_8500, _T_8501) @[ifu_mem_ctl.scala 694:59] + node _T_8503 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 694:102] + node _T_8504 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] + node _T_8505 = and(_T_8503, _T_8504) @[ifu_mem_ctl.scala 694:124] + node _T_8506 = or(_T_8502, _T_8505) @[ifu_mem_ctl.scala 694:81] + node _T_8507 = or(_T_8506, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8508 = bits(_T_8507, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8509 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8508 : @[Reg.scala 28:19] _T_8509 <= _T_8499 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][127] <= _T_8509 @[ifu_mem_ctl.scala 685:41] - node _T_8510 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8511 = eq(_T_8510, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8512 = and(ic_valid_ff, _T_8511) @[ifu_mem_ctl.scala 685:97] - node _T_8513 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8514 = and(_T_8512, _T_8513) @[ifu_mem_ctl.scala 685:122] - node _T_8515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 686:37] - node _T_8516 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8517 = and(_T_8515, _T_8516) @[ifu_mem_ctl.scala 686:59] - node _T_8518 = eq(perr_ic_index_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 686:102] - node _T_8519 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8520 = and(_T_8518, _T_8519) @[ifu_mem_ctl.scala 686:124] - node _T_8521 = or(_T_8517, _T_8520) @[ifu_mem_ctl.scala 686:81] - node _T_8522 = or(_T_8521, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8523 = bits(_T_8522, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[0][127] <= _T_8509 @[ifu_mem_ctl.scala 693:41] + node _T_8510 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8511 = eq(_T_8510, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8512 = and(ic_valid_ff, _T_8511) @[ifu_mem_ctl.scala 693:97] + node _T_8513 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8514 = and(_T_8512, _T_8513) @[ifu_mem_ctl.scala 693:122] + node _T_8515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 694:37] + node _T_8516 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8517 = and(_T_8515, _T_8516) @[ifu_mem_ctl.scala 694:59] + node _T_8518 = eq(perr_ic_index_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 694:102] + node _T_8519 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8520 = and(_T_8518, _T_8519) @[ifu_mem_ctl.scala 694:124] + node _T_8521 = or(_T_8517, _T_8520) @[ifu_mem_ctl.scala 694:81] + node _T_8522 = or(_T_8521, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8523 = bits(_T_8522, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8524 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8523 : @[Reg.scala 28:19] _T_8524 <= _T_8514 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][96] <= _T_8524 @[ifu_mem_ctl.scala 685:41] - node _T_8525 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8526 = eq(_T_8525, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8527 = and(ic_valid_ff, _T_8526) @[ifu_mem_ctl.scala 685:97] - node _T_8528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8529 = and(_T_8527, _T_8528) @[ifu_mem_ctl.scala 685:122] - node _T_8530 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 686:37] - node _T_8531 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8532 = and(_T_8530, _T_8531) @[ifu_mem_ctl.scala 686:59] - node _T_8533 = eq(perr_ic_index_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 686:102] - node _T_8534 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8535 = and(_T_8533, _T_8534) @[ifu_mem_ctl.scala 686:124] - node _T_8536 = or(_T_8532, _T_8535) @[ifu_mem_ctl.scala 686:81] - node _T_8537 = or(_T_8536, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8538 = bits(_T_8537, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][96] <= _T_8524 @[ifu_mem_ctl.scala 693:41] + node _T_8525 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8526 = eq(_T_8525, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8527 = and(ic_valid_ff, _T_8526) @[ifu_mem_ctl.scala 693:97] + node _T_8528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8529 = and(_T_8527, _T_8528) @[ifu_mem_ctl.scala 693:122] + node _T_8530 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 694:37] + node _T_8531 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8532 = and(_T_8530, _T_8531) @[ifu_mem_ctl.scala 694:59] + node _T_8533 = eq(perr_ic_index_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 694:102] + node _T_8534 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8535 = and(_T_8533, _T_8534) @[ifu_mem_ctl.scala 694:124] + node _T_8536 = or(_T_8532, _T_8535) @[ifu_mem_ctl.scala 694:81] + node _T_8537 = or(_T_8536, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8538 = bits(_T_8537, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8539 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8538 : @[Reg.scala 28:19] _T_8539 <= _T_8529 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][97] <= _T_8539 @[ifu_mem_ctl.scala 685:41] - node _T_8540 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8541 = eq(_T_8540, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8542 = and(ic_valid_ff, _T_8541) @[ifu_mem_ctl.scala 685:97] - node _T_8543 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8544 = and(_T_8542, _T_8543) @[ifu_mem_ctl.scala 685:122] - node _T_8545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 686:37] - node _T_8546 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8547 = and(_T_8545, _T_8546) @[ifu_mem_ctl.scala 686:59] - node _T_8548 = eq(perr_ic_index_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 686:102] - node _T_8549 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8550 = and(_T_8548, _T_8549) @[ifu_mem_ctl.scala 686:124] - node _T_8551 = or(_T_8547, _T_8550) @[ifu_mem_ctl.scala 686:81] - node _T_8552 = or(_T_8551, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8553 = bits(_T_8552, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][97] <= _T_8539 @[ifu_mem_ctl.scala 693:41] + node _T_8540 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8541 = eq(_T_8540, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8542 = and(ic_valid_ff, _T_8541) @[ifu_mem_ctl.scala 693:97] + node _T_8543 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8544 = and(_T_8542, _T_8543) @[ifu_mem_ctl.scala 693:122] + node _T_8545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 694:37] + node _T_8546 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8547 = and(_T_8545, _T_8546) @[ifu_mem_ctl.scala 694:59] + node _T_8548 = eq(perr_ic_index_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 694:102] + node _T_8549 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8550 = and(_T_8548, _T_8549) @[ifu_mem_ctl.scala 694:124] + node _T_8551 = or(_T_8547, _T_8550) @[ifu_mem_ctl.scala 694:81] + node _T_8552 = or(_T_8551, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8553 = bits(_T_8552, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8554 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8553 : @[Reg.scala 28:19] _T_8554 <= _T_8544 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][98] <= _T_8554 @[ifu_mem_ctl.scala 685:41] - node _T_8555 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8556 = eq(_T_8555, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8557 = and(ic_valid_ff, _T_8556) @[ifu_mem_ctl.scala 685:97] - node _T_8558 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8559 = and(_T_8557, _T_8558) @[ifu_mem_ctl.scala 685:122] - node _T_8560 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 686:37] - node _T_8561 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8562 = and(_T_8560, _T_8561) @[ifu_mem_ctl.scala 686:59] - node _T_8563 = eq(perr_ic_index_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 686:102] - node _T_8564 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8565 = and(_T_8563, _T_8564) @[ifu_mem_ctl.scala 686:124] - node _T_8566 = or(_T_8562, _T_8565) @[ifu_mem_ctl.scala 686:81] - node _T_8567 = or(_T_8566, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8568 = bits(_T_8567, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][98] <= _T_8554 @[ifu_mem_ctl.scala 693:41] + node _T_8555 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8556 = eq(_T_8555, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8557 = and(ic_valid_ff, _T_8556) @[ifu_mem_ctl.scala 693:97] + node _T_8558 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8559 = and(_T_8557, _T_8558) @[ifu_mem_ctl.scala 693:122] + node _T_8560 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 694:37] + node _T_8561 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8562 = and(_T_8560, _T_8561) @[ifu_mem_ctl.scala 694:59] + node _T_8563 = eq(perr_ic_index_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 694:102] + node _T_8564 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8565 = and(_T_8563, _T_8564) @[ifu_mem_ctl.scala 694:124] + node _T_8566 = or(_T_8562, _T_8565) @[ifu_mem_ctl.scala 694:81] + node _T_8567 = or(_T_8566, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8568 = bits(_T_8567, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8569 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8568 : @[Reg.scala 28:19] _T_8569 <= _T_8559 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][99] <= _T_8569 @[ifu_mem_ctl.scala 685:41] - node _T_8570 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8571 = eq(_T_8570, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8572 = and(ic_valid_ff, _T_8571) @[ifu_mem_ctl.scala 685:97] - node _T_8573 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8574 = and(_T_8572, _T_8573) @[ifu_mem_ctl.scala 685:122] - node _T_8575 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 686:37] - node _T_8576 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8577 = and(_T_8575, _T_8576) @[ifu_mem_ctl.scala 686:59] - node _T_8578 = eq(perr_ic_index_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 686:102] - node _T_8579 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8580 = and(_T_8578, _T_8579) @[ifu_mem_ctl.scala 686:124] - node _T_8581 = or(_T_8577, _T_8580) @[ifu_mem_ctl.scala 686:81] - node _T_8582 = or(_T_8581, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8583 = bits(_T_8582, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][99] <= _T_8569 @[ifu_mem_ctl.scala 693:41] + node _T_8570 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8571 = eq(_T_8570, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8572 = and(ic_valid_ff, _T_8571) @[ifu_mem_ctl.scala 693:97] + node _T_8573 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8574 = and(_T_8572, _T_8573) @[ifu_mem_ctl.scala 693:122] + node _T_8575 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 694:37] + node _T_8576 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8577 = and(_T_8575, _T_8576) @[ifu_mem_ctl.scala 694:59] + node _T_8578 = eq(perr_ic_index_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 694:102] + node _T_8579 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8580 = and(_T_8578, _T_8579) @[ifu_mem_ctl.scala 694:124] + node _T_8581 = or(_T_8577, _T_8580) @[ifu_mem_ctl.scala 694:81] + node _T_8582 = or(_T_8581, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8583 = bits(_T_8582, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8584 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8583 : @[Reg.scala 28:19] _T_8584 <= _T_8574 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][100] <= _T_8584 @[ifu_mem_ctl.scala 685:41] - node _T_8585 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8586 = eq(_T_8585, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8587 = and(ic_valid_ff, _T_8586) @[ifu_mem_ctl.scala 685:97] - node _T_8588 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8589 = and(_T_8587, _T_8588) @[ifu_mem_ctl.scala 685:122] - node _T_8590 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 686:37] - node _T_8591 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8592 = and(_T_8590, _T_8591) @[ifu_mem_ctl.scala 686:59] - node _T_8593 = eq(perr_ic_index_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 686:102] - node _T_8594 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8595 = and(_T_8593, _T_8594) @[ifu_mem_ctl.scala 686:124] - node _T_8596 = or(_T_8592, _T_8595) @[ifu_mem_ctl.scala 686:81] - node _T_8597 = or(_T_8596, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8598 = bits(_T_8597, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][100] <= _T_8584 @[ifu_mem_ctl.scala 693:41] + node _T_8585 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8586 = eq(_T_8585, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8587 = and(ic_valid_ff, _T_8586) @[ifu_mem_ctl.scala 693:97] + node _T_8588 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8589 = and(_T_8587, _T_8588) @[ifu_mem_ctl.scala 693:122] + node _T_8590 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 694:37] + node _T_8591 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8592 = and(_T_8590, _T_8591) @[ifu_mem_ctl.scala 694:59] + node _T_8593 = eq(perr_ic_index_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 694:102] + node _T_8594 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8595 = and(_T_8593, _T_8594) @[ifu_mem_ctl.scala 694:124] + node _T_8596 = or(_T_8592, _T_8595) @[ifu_mem_ctl.scala 694:81] + node _T_8597 = or(_T_8596, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8598 = bits(_T_8597, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8599 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8598 : @[Reg.scala 28:19] _T_8599 <= _T_8589 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][101] <= _T_8599 @[ifu_mem_ctl.scala 685:41] - node _T_8600 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8601 = eq(_T_8600, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8602 = and(ic_valid_ff, _T_8601) @[ifu_mem_ctl.scala 685:97] - node _T_8603 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8604 = and(_T_8602, _T_8603) @[ifu_mem_ctl.scala 685:122] - node _T_8605 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 686:37] - node _T_8606 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8607 = and(_T_8605, _T_8606) @[ifu_mem_ctl.scala 686:59] - node _T_8608 = eq(perr_ic_index_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 686:102] - node _T_8609 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8610 = and(_T_8608, _T_8609) @[ifu_mem_ctl.scala 686:124] - node _T_8611 = or(_T_8607, _T_8610) @[ifu_mem_ctl.scala 686:81] - node _T_8612 = or(_T_8611, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8613 = bits(_T_8612, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][101] <= _T_8599 @[ifu_mem_ctl.scala 693:41] + node _T_8600 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8601 = eq(_T_8600, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8602 = and(ic_valid_ff, _T_8601) @[ifu_mem_ctl.scala 693:97] + node _T_8603 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8604 = and(_T_8602, _T_8603) @[ifu_mem_ctl.scala 693:122] + node _T_8605 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 694:37] + node _T_8606 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8607 = and(_T_8605, _T_8606) @[ifu_mem_ctl.scala 694:59] + node _T_8608 = eq(perr_ic_index_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 694:102] + node _T_8609 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8610 = and(_T_8608, _T_8609) @[ifu_mem_ctl.scala 694:124] + node _T_8611 = or(_T_8607, _T_8610) @[ifu_mem_ctl.scala 694:81] + node _T_8612 = or(_T_8611, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8613 = bits(_T_8612, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8614 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8613 : @[Reg.scala 28:19] _T_8614 <= _T_8604 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][102] <= _T_8614 @[ifu_mem_ctl.scala 685:41] - node _T_8615 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8616 = eq(_T_8615, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8617 = and(ic_valid_ff, _T_8616) @[ifu_mem_ctl.scala 685:97] - node _T_8618 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8619 = and(_T_8617, _T_8618) @[ifu_mem_ctl.scala 685:122] - node _T_8620 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 686:37] - node _T_8621 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8622 = and(_T_8620, _T_8621) @[ifu_mem_ctl.scala 686:59] - node _T_8623 = eq(perr_ic_index_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 686:102] - node _T_8624 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8625 = and(_T_8623, _T_8624) @[ifu_mem_ctl.scala 686:124] - node _T_8626 = or(_T_8622, _T_8625) @[ifu_mem_ctl.scala 686:81] - node _T_8627 = or(_T_8626, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8628 = bits(_T_8627, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][102] <= _T_8614 @[ifu_mem_ctl.scala 693:41] + node _T_8615 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8616 = eq(_T_8615, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8617 = and(ic_valid_ff, _T_8616) @[ifu_mem_ctl.scala 693:97] + node _T_8618 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8619 = and(_T_8617, _T_8618) @[ifu_mem_ctl.scala 693:122] + node _T_8620 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 694:37] + node _T_8621 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8622 = and(_T_8620, _T_8621) @[ifu_mem_ctl.scala 694:59] + node _T_8623 = eq(perr_ic_index_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 694:102] + node _T_8624 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8625 = and(_T_8623, _T_8624) @[ifu_mem_ctl.scala 694:124] + node _T_8626 = or(_T_8622, _T_8625) @[ifu_mem_ctl.scala 694:81] + node _T_8627 = or(_T_8626, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8628 = bits(_T_8627, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8629 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8628 : @[Reg.scala 28:19] _T_8629 <= _T_8619 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][103] <= _T_8629 @[ifu_mem_ctl.scala 685:41] - node _T_8630 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8631 = eq(_T_8630, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8632 = and(ic_valid_ff, _T_8631) @[ifu_mem_ctl.scala 685:97] - node _T_8633 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8634 = and(_T_8632, _T_8633) @[ifu_mem_ctl.scala 685:122] - node _T_8635 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 686:37] - node _T_8636 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8637 = and(_T_8635, _T_8636) @[ifu_mem_ctl.scala 686:59] - node _T_8638 = eq(perr_ic_index_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 686:102] - node _T_8639 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8640 = and(_T_8638, _T_8639) @[ifu_mem_ctl.scala 686:124] - node _T_8641 = or(_T_8637, _T_8640) @[ifu_mem_ctl.scala 686:81] - node _T_8642 = or(_T_8641, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8643 = bits(_T_8642, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][103] <= _T_8629 @[ifu_mem_ctl.scala 693:41] + node _T_8630 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8631 = eq(_T_8630, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8632 = and(ic_valid_ff, _T_8631) @[ifu_mem_ctl.scala 693:97] + node _T_8633 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8634 = and(_T_8632, _T_8633) @[ifu_mem_ctl.scala 693:122] + node _T_8635 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 694:37] + node _T_8636 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8637 = and(_T_8635, _T_8636) @[ifu_mem_ctl.scala 694:59] + node _T_8638 = eq(perr_ic_index_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 694:102] + node _T_8639 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8640 = and(_T_8638, _T_8639) @[ifu_mem_ctl.scala 694:124] + node _T_8641 = or(_T_8637, _T_8640) @[ifu_mem_ctl.scala 694:81] + node _T_8642 = or(_T_8641, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8643 = bits(_T_8642, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8644 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8643 : @[Reg.scala 28:19] _T_8644 <= _T_8634 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][104] <= _T_8644 @[ifu_mem_ctl.scala 685:41] - node _T_8645 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8646 = eq(_T_8645, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8647 = and(ic_valid_ff, _T_8646) @[ifu_mem_ctl.scala 685:97] - node _T_8648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8649 = and(_T_8647, _T_8648) @[ifu_mem_ctl.scala 685:122] - node _T_8650 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 686:37] - node _T_8651 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8652 = and(_T_8650, _T_8651) @[ifu_mem_ctl.scala 686:59] - node _T_8653 = eq(perr_ic_index_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 686:102] - node _T_8654 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8655 = and(_T_8653, _T_8654) @[ifu_mem_ctl.scala 686:124] - node _T_8656 = or(_T_8652, _T_8655) @[ifu_mem_ctl.scala 686:81] - node _T_8657 = or(_T_8656, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8658 = bits(_T_8657, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][104] <= _T_8644 @[ifu_mem_ctl.scala 693:41] + node _T_8645 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8646 = eq(_T_8645, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8647 = and(ic_valid_ff, _T_8646) @[ifu_mem_ctl.scala 693:97] + node _T_8648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8649 = and(_T_8647, _T_8648) @[ifu_mem_ctl.scala 693:122] + node _T_8650 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 694:37] + node _T_8651 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8652 = and(_T_8650, _T_8651) @[ifu_mem_ctl.scala 694:59] + node _T_8653 = eq(perr_ic_index_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 694:102] + node _T_8654 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8655 = and(_T_8653, _T_8654) @[ifu_mem_ctl.scala 694:124] + node _T_8656 = or(_T_8652, _T_8655) @[ifu_mem_ctl.scala 694:81] + node _T_8657 = or(_T_8656, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8658 = bits(_T_8657, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8659 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8658 : @[Reg.scala 28:19] _T_8659 <= _T_8649 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][105] <= _T_8659 @[ifu_mem_ctl.scala 685:41] - node _T_8660 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8661 = eq(_T_8660, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8662 = and(ic_valid_ff, _T_8661) @[ifu_mem_ctl.scala 685:97] - node _T_8663 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8664 = and(_T_8662, _T_8663) @[ifu_mem_ctl.scala 685:122] - node _T_8665 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 686:37] - node _T_8666 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8667 = and(_T_8665, _T_8666) @[ifu_mem_ctl.scala 686:59] - node _T_8668 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 686:102] - node _T_8669 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8670 = and(_T_8668, _T_8669) @[ifu_mem_ctl.scala 686:124] - node _T_8671 = or(_T_8667, _T_8670) @[ifu_mem_ctl.scala 686:81] - node _T_8672 = or(_T_8671, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8673 = bits(_T_8672, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][105] <= _T_8659 @[ifu_mem_ctl.scala 693:41] + node _T_8660 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8661 = eq(_T_8660, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8662 = and(ic_valid_ff, _T_8661) @[ifu_mem_ctl.scala 693:97] + node _T_8663 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8664 = and(_T_8662, _T_8663) @[ifu_mem_ctl.scala 693:122] + node _T_8665 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 694:37] + node _T_8666 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8667 = and(_T_8665, _T_8666) @[ifu_mem_ctl.scala 694:59] + node _T_8668 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 694:102] + node _T_8669 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8670 = and(_T_8668, _T_8669) @[ifu_mem_ctl.scala 694:124] + node _T_8671 = or(_T_8667, _T_8670) @[ifu_mem_ctl.scala 694:81] + node _T_8672 = or(_T_8671, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8673 = bits(_T_8672, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8674 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8673 : @[Reg.scala 28:19] _T_8674 <= _T_8664 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][106] <= _T_8674 @[ifu_mem_ctl.scala 685:41] - node _T_8675 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8676 = eq(_T_8675, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8677 = and(ic_valid_ff, _T_8676) @[ifu_mem_ctl.scala 685:97] - node _T_8678 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8679 = and(_T_8677, _T_8678) @[ifu_mem_ctl.scala 685:122] - node _T_8680 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 686:37] - node _T_8681 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8682 = and(_T_8680, _T_8681) @[ifu_mem_ctl.scala 686:59] - node _T_8683 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 686:102] - node _T_8684 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8685 = and(_T_8683, _T_8684) @[ifu_mem_ctl.scala 686:124] - node _T_8686 = or(_T_8682, _T_8685) @[ifu_mem_ctl.scala 686:81] - node _T_8687 = or(_T_8686, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8688 = bits(_T_8687, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][106] <= _T_8674 @[ifu_mem_ctl.scala 693:41] + node _T_8675 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8676 = eq(_T_8675, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8677 = and(ic_valid_ff, _T_8676) @[ifu_mem_ctl.scala 693:97] + node _T_8678 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8679 = and(_T_8677, _T_8678) @[ifu_mem_ctl.scala 693:122] + node _T_8680 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 694:37] + node _T_8681 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8682 = and(_T_8680, _T_8681) @[ifu_mem_ctl.scala 694:59] + node _T_8683 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 694:102] + node _T_8684 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8685 = and(_T_8683, _T_8684) @[ifu_mem_ctl.scala 694:124] + node _T_8686 = or(_T_8682, _T_8685) @[ifu_mem_ctl.scala 694:81] + node _T_8687 = or(_T_8686, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8688 = bits(_T_8687, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8689 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8688 : @[Reg.scala 28:19] _T_8689 <= _T_8679 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][107] <= _T_8689 @[ifu_mem_ctl.scala 685:41] - node _T_8690 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8691 = eq(_T_8690, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8692 = and(ic_valid_ff, _T_8691) @[ifu_mem_ctl.scala 685:97] - node _T_8693 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8694 = and(_T_8692, _T_8693) @[ifu_mem_ctl.scala 685:122] - node _T_8695 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 686:37] - node _T_8696 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8697 = and(_T_8695, _T_8696) @[ifu_mem_ctl.scala 686:59] - node _T_8698 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 686:102] - node _T_8699 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8700 = and(_T_8698, _T_8699) @[ifu_mem_ctl.scala 686:124] - node _T_8701 = or(_T_8697, _T_8700) @[ifu_mem_ctl.scala 686:81] - node _T_8702 = or(_T_8701, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8703 = bits(_T_8702, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][107] <= _T_8689 @[ifu_mem_ctl.scala 693:41] + node _T_8690 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8691 = eq(_T_8690, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8692 = and(ic_valid_ff, _T_8691) @[ifu_mem_ctl.scala 693:97] + node _T_8693 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8694 = and(_T_8692, _T_8693) @[ifu_mem_ctl.scala 693:122] + node _T_8695 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 694:37] + node _T_8696 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8697 = and(_T_8695, _T_8696) @[ifu_mem_ctl.scala 694:59] + node _T_8698 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 694:102] + node _T_8699 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8700 = and(_T_8698, _T_8699) @[ifu_mem_ctl.scala 694:124] + node _T_8701 = or(_T_8697, _T_8700) @[ifu_mem_ctl.scala 694:81] + node _T_8702 = or(_T_8701, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8703 = bits(_T_8702, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8704 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8703 : @[Reg.scala 28:19] _T_8704 <= _T_8694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][108] <= _T_8704 @[ifu_mem_ctl.scala 685:41] - node _T_8705 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8706 = eq(_T_8705, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8707 = and(ic_valid_ff, _T_8706) @[ifu_mem_ctl.scala 685:97] - node _T_8708 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8709 = and(_T_8707, _T_8708) @[ifu_mem_ctl.scala 685:122] - node _T_8710 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 686:37] - node _T_8711 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8712 = and(_T_8710, _T_8711) @[ifu_mem_ctl.scala 686:59] - node _T_8713 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 686:102] - node _T_8714 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8715 = and(_T_8713, _T_8714) @[ifu_mem_ctl.scala 686:124] - node _T_8716 = or(_T_8712, _T_8715) @[ifu_mem_ctl.scala 686:81] - node _T_8717 = or(_T_8716, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8718 = bits(_T_8717, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][108] <= _T_8704 @[ifu_mem_ctl.scala 693:41] + node _T_8705 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8706 = eq(_T_8705, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8707 = and(ic_valid_ff, _T_8706) @[ifu_mem_ctl.scala 693:97] + node _T_8708 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8709 = and(_T_8707, _T_8708) @[ifu_mem_ctl.scala 693:122] + node _T_8710 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 694:37] + node _T_8711 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8712 = and(_T_8710, _T_8711) @[ifu_mem_ctl.scala 694:59] + node _T_8713 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 694:102] + node _T_8714 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8715 = and(_T_8713, _T_8714) @[ifu_mem_ctl.scala 694:124] + node _T_8716 = or(_T_8712, _T_8715) @[ifu_mem_ctl.scala 694:81] + node _T_8717 = or(_T_8716, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8718 = bits(_T_8717, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8719 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8718 : @[Reg.scala 28:19] _T_8719 <= _T_8709 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][109] <= _T_8719 @[ifu_mem_ctl.scala 685:41] - node _T_8720 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8721 = eq(_T_8720, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8722 = and(ic_valid_ff, _T_8721) @[ifu_mem_ctl.scala 685:97] - node _T_8723 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8724 = and(_T_8722, _T_8723) @[ifu_mem_ctl.scala 685:122] - node _T_8725 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 686:37] - node _T_8726 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8727 = and(_T_8725, _T_8726) @[ifu_mem_ctl.scala 686:59] - node _T_8728 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 686:102] - node _T_8729 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8730 = and(_T_8728, _T_8729) @[ifu_mem_ctl.scala 686:124] - node _T_8731 = or(_T_8727, _T_8730) @[ifu_mem_ctl.scala 686:81] - node _T_8732 = or(_T_8731, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8733 = bits(_T_8732, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][109] <= _T_8719 @[ifu_mem_ctl.scala 693:41] + node _T_8720 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8721 = eq(_T_8720, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8722 = and(ic_valid_ff, _T_8721) @[ifu_mem_ctl.scala 693:97] + node _T_8723 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8724 = and(_T_8722, _T_8723) @[ifu_mem_ctl.scala 693:122] + node _T_8725 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 694:37] + node _T_8726 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8727 = and(_T_8725, _T_8726) @[ifu_mem_ctl.scala 694:59] + node _T_8728 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 694:102] + node _T_8729 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8730 = and(_T_8728, _T_8729) @[ifu_mem_ctl.scala 694:124] + node _T_8731 = or(_T_8727, _T_8730) @[ifu_mem_ctl.scala 694:81] + node _T_8732 = or(_T_8731, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8733 = bits(_T_8732, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8734 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8733 : @[Reg.scala 28:19] _T_8734 <= _T_8724 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][110] <= _T_8734 @[ifu_mem_ctl.scala 685:41] - node _T_8735 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8736 = eq(_T_8735, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8737 = and(ic_valid_ff, _T_8736) @[ifu_mem_ctl.scala 685:97] - node _T_8738 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8739 = and(_T_8737, _T_8738) @[ifu_mem_ctl.scala 685:122] - node _T_8740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 686:37] - node _T_8741 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8742 = and(_T_8740, _T_8741) @[ifu_mem_ctl.scala 686:59] - node _T_8743 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 686:102] - node _T_8744 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8745 = and(_T_8743, _T_8744) @[ifu_mem_ctl.scala 686:124] - node _T_8746 = or(_T_8742, _T_8745) @[ifu_mem_ctl.scala 686:81] - node _T_8747 = or(_T_8746, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8748 = bits(_T_8747, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][110] <= _T_8734 @[ifu_mem_ctl.scala 693:41] + node _T_8735 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8736 = eq(_T_8735, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8737 = and(ic_valid_ff, _T_8736) @[ifu_mem_ctl.scala 693:97] + node _T_8738 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8739 = and(_T_8737, _T_8738) @[ifu_mem_ctl.scala 693:122] + node _T_8740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 694:37] + node _T_8741 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8742 = and(_T_8740, _T_8741) @[ifu_mem_ctl.scala 694:59] + node _T_8743 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 694:102] + node _T_8744 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8745 = and(_T_8743, _T_8744) @[ifu_mem_ctl.scala 694:124] + node _T_8746 = or(_T_8742, _T_8745) @[ifu_mem_ctl.scala 694:81] + node _T_8747 = or(_T_8746, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8748 = bits(_T_8747, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8749 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8748 : @[Reg.scala 28:19] _T_8749 <= _T_8739 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][111] <= _T_8749 @[ifu_mem_ctl.scala 685:41] - node _T_8750 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8751 = eq(_T_8750, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8752 = and(ic_valid_ff, _T_8751) @[ifu_mem_ctl.scala 685:97] - node _T_8753 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8754 = and(_T_8752, _T_8753) @[ifu_mem_ctl.scala 685:122] - node _T_8755 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 686:37] - node _T_8756 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8757 = and(_T_8755, _T_8756) @[ifu_mem_ctl.scala 686:59] - node _T_8758 = eq(perr_ic_index_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 686:102] - node _T_8759 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8760 = and(_T_8758, _T_8759) @[ifu_mem_ctl.scala 686:124] - node _T_8761 = or(_T_8757, _T_8760) @[ifu_mem_ctl.scala 686:81] - node _T_8762 = or(_T_8761, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8763 = bits(_T_8762, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][111] <= _T_8749 @[ifu_mem_ctl.scala 693:41] + node _T_8750 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8751 = eq(_T_8750, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8752 = and(ic_valid_ff, _T_8751) @[ifu_mem_ctl.scala 693:97] + node _T_8753 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8754 = and(_T_8752, _T_8753) @[ifu_mem_ctl.scala 693:122] + node _T_8755 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 694:37] + node _T_8756 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8757 = and(_T_8755, _T_8756) @[ifu_mem_ctl.scala 694:59] + node _T_8758 = eq(perr_ic_index_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 694:102] + node _T_8759 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8760 = and(_T_8758, _T_8759) @[ifu_mem_ctl.scala 694:124] + node _T_8761 = or(_T_8757, _T_8760) @[ifu_mem_ctl.scala 694:81] + node _T_8762 = or(_T_8761, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8763 = bits(_T_8762, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8764 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8763 : @[Reg.scala 28:19] _T_8764 <= _T_8754 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][112] <= _T_8764 @[ifu_mem_ctl.scala 685:41] - node _T_8765 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8766 = eq(_T_8765, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8767 = and(ic_valid_ff, _T_8766) @[ifu_mem_ctl.scala 685:97] - node _T_8768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8769 = and(_T_8767, _T_8768) @[ifu_mem_ctl.scala 685:122] - node _T_8770 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 686:37] - node _T_8771 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8772 = and(_T_8770, _T_8771) @[ifu_mem_ctl.scala 686:59] - node _T_8773 = eq(perr_ic_index_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 686:102] - node _T_8774 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8775 = and(_T_8773, _T_8774) @[ifu_mem_ctl.scala 686:124] - node _T_8776 = or(_T_8772, _T_8775) @[ifu_mem_ctl.scala 686:81] - node _T_8777 = or(_T_8776, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8778 = bits(_T_8777, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][112] <= _T_8764 @[ifu_mem_ctl.scala 693:41] + node _T_8765 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8766 = eq(_T_8765, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8767 = and(ic_valid_ff, _T_8766) @[ifu_mem_ctl.scala 693:97] + node _T_8768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8769 = and(_T_8767, _T_8768) @[ifu_mem_ctl.scala 693:122] + node _T_8770 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 694:37] + node _T_8771 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8772 = and(_T_8770, _T_8771) @[ifu_mem_ctl.scala 694:59] + node _T_8773 = eq(perr_ic_index_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 694:102] + node _T_8774 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8775 = and(_T_8773, _T_8774) @[ifu_mem_ctl.scala 694:124] + node _T_8776 = or(_T_8772, _T_8775) @[ifu_mem_ctl.scala 694:81] + node _T_8777 = or(_T_8776, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8778 = bits(_T_8777, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8779 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8778 : @[Reg.scala 28:19] _T_8779 <= _T_8769 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][113] <= _T_8779 @[ifu_mem_ctl.scala 685:41] - node _T_8780 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8781 = eq(_T_8780, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8782 = and(ic_valid_ff, _T_8781) @[ifu_mem_ctl.scala 685:97] - node _T_8783 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8784 = and(_T_8782, _T_8783) @[ifu_mem_ctl.scala 685:122] - node _T_8785 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 686:37] - node _T_8786 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8787 = and(_T_8785, _T_8786) @[ifu_mem_ctl.scala 686:59] - node _T_8788 = eq(perr_ic_index_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 686:102] - node _T_8789 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8790 = and(_T_8788, _T_8789) @[ifu_mem_ctl.scala 686:124] - node _T_8791 = or(_T_8787, _T_8790) @[ifu_mem_ctl.scala 686:81] - node _T_8792 = or(_T_8791, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8793 = bits(_T_8792, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][113] <= _T_8779 @[ifu_mem_ctl.scala 693:41] + node _T_8780 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8781 = eq(_T_8780, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8782 = and(ic_valid_ff, _T_8781) @[ifu_mem_ctl.scala 693:97] + node _T_8783 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8784 = and(_T_8782, _T_8783) @[ifu_mem_ctl.scala 693:122] + node _T_8785 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 694:37] + node _T_8786 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8787 = and(_T_8785, _T_8786) @[ifu_mem_ctl.scala 694:59] + node _T_8788 = eq(perr_ic_index_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 694:102] + node _T_8789 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8790 = and(_T_8788, _T_8789) @[ifu_mem_ctl.scala 694:124] + node _T_8791 = or(_T_8787, _T_8790) @[ifu_mem_ctl.scala 694:81] + node _T_8792 = or(_T_8791, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8793 = bits(_T_8792, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8794 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8793 : @[Reg.scala 28:19] _T_8794 <= _T_8784 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][114] <= _T_8794 @[ifu_mem_ctl.scala 685:41] - node _T_8795 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8796 = eq(_T_8795, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8797 = and(ic_valid_ff, _T_8796) @[ifu_mem_ctl.scala 685:97] - node _T_8798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8799 = and(_T_8797, _T_8798) @[ifu_mem_ctl.scala 685:122] - node _T_8800 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 686:37] - node _T_8801 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8802 = and(_T_8800, _T_8801) @[ifu_mem_ctl.scala 686:59] - node _T_8803 = eq(perr_ic_index_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 686:102] - node _T_8804 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8805 = and(_T_8803, _T_8804) @[ifu_mem_ctl.scala 686:124] - node _T_8806 = or(_T_8802, _T_8805) @[ifu_mem_ctl.scala 686:81] - node _T_8807 = or(_T_8806, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8808 = bits(_T_8807, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][114] <= _T_8794 @[ifu_mem_ctl.scala 693:41] + node _T_8795 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8796 = eq(_T_8795, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8797 = and(ic_valid_ff, _T_8796) @[ifu_mem_ctl.scala 693:97] + node _T_8798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8799 = and(_T_8797, _T_8798) @[ifu_mem_ctl.scala 693:122] + node _T_8800 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 694:37] + node _T_8801 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8802 = and(_T_8800, _T_8801) @[ifu_mem_ctl.scala 694:59] + node _T_8803 = eq(perr_ic_index_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 694:102] + node _T_8804 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8805 = and(_T_8803, _T_8804) @[ifu_mem_ctl.scala 694:124] + node _T_8806 = or(_T_8802, _T_8805) @[ifu_mem_ctl.scala 694:81] + node _T_8807 = or(_T_8806, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8808 = bits(_T_8807, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8809 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8808 : @[Reg.scala 28:19] _T_8809 <= _T_8799 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][115] <= _T_8809 @[ifu_mem_ctl.scala 685:41] - node _T_8810 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8811 = eq(_T_8810, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8812 = and(ic_valid_ff, _T_8811) @[ifu_mem_ctl.scala 685:97] - node _T_8813 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8814 = and(_T_8812, _T_8813) @[ifu_mem_ctl.scala 685:122] - node _T_8815 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 686:37] - node _T_8816 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8817 = and(_T_8815, _T_8816) @[ifu_mem_ctl.scala 686:59] - node _T_8818 = eq(perr_ic_index_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 686:102] - node _T_8819 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8820 = and(_T_8818, _T_8819) @[ifu_mem_ctl.scala 686:124] - node _T_8821 = or(_T_8817, _T_8820) @[ifu_mem_ctl.scala 686:81] - node _T_8822 = or(_T_8821, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8823 = bits(_T_8822, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][115] <= _T_8809 @[ifu_mem_ctl.scala 693:41] + node _T_8810 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8811 = eq(_T_8810, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8812 = and(ic_valid_ff, _T_8811) @[ifu_mem_ctl.scala 693:97] + node _T_8813 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8814 = and(_T_8812, _T_8813) @[ifu_mem_ctl.scala 693:122] + node _T_8815 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 694:37] + node _T_8816 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8817 = and(_T_8815, _T_8816) @[ifu_mem_ctl.scala 694:59] + node _T_8818 = eq(perr_ic_index_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 694:102] + node _T_8819 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8820 = and(_T_8818, _T_8819) @[ifu_mem_ctl.scala 694:124] + node _T_8821 = or(_T_8817, _T_8820) @[ifu_mem_ctl.scala 694:81] + node _T_8822 = or(_T_8821, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8823 = bits(_T_8822, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8824 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8823 : @[Reg.scala 28:19] _T_8824 <= _T_8814 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][116] <= _T_8824 @[ifu_mem_ctl.scala 685:41] - node _T_8825 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8826 = eq(_T_8825, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8827 = and(ic_valid_ff, _T_8826) @[ifu_mem_ctl.scala 685:97] - node _T_8828 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8829 = and(_T_8827, _T_8828) @[ifu_mem_ctl.scala 685:122] - node _T_8830 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 686:37] - node _T_8831 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8832 = and(_T_8830, _T_8831) @[ifu_mem_ctl.scala 686:59] - node _T_8833 = eq(perr_ic_index_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 686:102] - node _T_8834 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8835 = and(_T_8833, _T_8834) @[ifu_mem_ctl.scala 686:124] - node _T_8836 = or(_T_8832, _T_8835) @[ifu_mem_ctl.scala 686:81] - node _T_8837 = or(_T_8836, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8838 = bits(_T_8837, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][116] <= _T_8824 @[ifu_mem_ctl.scala 693:41] + node _T_8825 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8826 = eq(_T_8825, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8827 = and(ic_valid_ff, _T_8826) @[ifu_mem_ctl.scala 693:97] + node _T_8828 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8829 = and(_T_8827, _T_8828) @[ifu_mem_ctl.scala 693:122] + node _T_8830 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 694:37] + node _T_8831 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8832 = and(_T_8830, _T_8831) @[ifu_mem_ctl.scala 694:59] + node _T_8833 = eq(perr_ic_index_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 694:102] + node _T_8834 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8835 = and(_T_8833, _T_8834) @[ifu_mem_ctl.scala 694:124] + node _T_8836 = or(_T_8832, _T_8835) @[ifu_mem_ctl.scala 694:81] + node _T_8837 = or(_T_8836, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8838 = bits(_T_8837, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8839 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8838 : @[Reg.scala 28:19] _T_8839 <= _T_8829 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][117] <= _T_8839 @[ifu_mem_ctl.scala 685:41] - node _T_8840 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8841 = eq(_T_8840, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8842 = and(ic_valid_ff, _T_8841) @[ifu_mem_ctl.scala 685:97] - node _T_8843 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8844 = and(_T_8842, _T_8843) @[ifu_mem_ctl.scala 685:122] - node _T_8845 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 686:37] - node _T_8846 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8847 = and(_T_8845, _T_8846) @[ifu_mem_ctl.scala 686:59] - node _T_8848 = eq(perr_ic_index_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 686:102] - node _T_8849 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8850 = and(_T_8848, _T_8849) @[ifu_mem_ctl.scala 686:124] - node _T_8851 = or(_T_8847, _T_8850) @[ifu_mem_ctl.scala 686:81] - node _T_8852 = or(_T_8851, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8853 = bits(_T_8852, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][117] <= _T_8839 @[ifu_mem_ctl.scala 693:41] + node _T_8840 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8841 = eq(_T_8840, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8842 = and(ic_valid_ff, _T_8841) @[ifu_mem_ctl.scala 693:97] + node _T_8843 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8844 = and(_T_8842, _T_8843) @[ifu_mem_ctl.scala 693:122] + node _T_8845 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 694:37] + node _T_8846 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8847 = and(_T_8845, _T_8846) @[ifu_mem_ctl.scala 694:59] + node _T_8848 = eq(perr_ic_index_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 694:102] + node _T_8849 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8850 = and(_T_8848, _T_8849) @[ifu_mem_ctl.scala 694:124] + node _T_8851 = or(_T_8847, _T_8850) @[ifu_mem_ctl.scala 694:81] + node _T_8852 = or(_T_8851, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8853 = bits(_T_8852, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8854 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8853 : @[Reg.scala 28:19] _T_8854 <= _T_8844 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][118] <= _T_8854 @[ifu_mem_ctl.scala 685:41] - node _T_8855 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8856 = eq(_T_8855, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8857 = and(ic_valid_ff, _T_8856) @[ifu_mem_ctl.scala 685:97] - node _T_8858 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8859 = and(_T_8857, _T_8858) @[ifu_mem_ctl.scala 685:122] - node _T_8860 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 686:37] - node _T_8861 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8862 = and(_T_8860, _T_8861) @[ifu_mem_ctl.scala 686:59] - node _T_8863 = eq(perr_ic_index_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 686:102] - node _T_8864 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8865 = and(_T_8863, _T_8864) @[ifu_mem_ctl.scala 686:124] - node _T_8866 = or(_T_8862, _T_8865) @[ifu_mem_ctl.scala 686:81] - node _T_8867 = or(_T_8866, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8868 = bits(_T_8867, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][118] <= _T_8854 @[ifu_mem_ctl.scala 693:41] + node _T_8855 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8856 = eq(_T_8855, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8857 = and(ic_valid_ff, _T_8856) @[ifu_mem_ctl.scala 693:97] + node _T_8858 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8859 = and(_T_8857, _T_8858) @[ifu_mem_ctl.scala 693:122] + node _T_8860 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 694:37] + node _T_8861 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8862 = and(_T_8860, _T_8861) @[ifu_mem_ctl.scala 694:59] + node _T_8863 = eq(perr_ic_index_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 694:102] + node _T_8864 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8865 = and(_T_8863, _T_8864) @[ifu_mem_ctl.scala 694:124] + node _T_8866 = or(_T_8862, _T_8865) @[ifu_mem_ctl.scala 694:81] + node _T_8867 = or(_T_8866, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8868 = bits(_T_8867, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8869 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8868 : @[Reg.scala 28:19] _T_8869 <= _T_8859 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][119] <= _T_8869 @[ifu_mem_ctl.scala 685:41] - node _T_8870 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8871 = eq(_T_8870, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8872 = and(ic_valid_ff, _T_8871) @[ifu_mem_ctl.scala 685:97] - node _T_8873 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8874 = and(_T_8872, _T_8873) @[ifu_mem_ctl.scala 685:122] - node _T_8875 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 686:37] - node _T_8876 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8877 = and(_T_8875, _T_8876) @[ifu_mem_ctl.scala 686:59] - node _T_8878 = eq(perr_ic_index_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 686:102] - node _T_8879 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8880 = and(_T_8878, _T_8879) @[ifu_mem_ctl.scala 686:124] - node _T_8881 = or(_T_8877, _T_8880) @[ifu_mem_ctl.scala 686:81] - node _T_8882 = or(_T_8881, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8883 = bits(_T_8882, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][119] <= _T_8869 @[ifu_mem_ctl.scala 693:41] + node _T_8870 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8871 = eq(_T_8870, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8872 = and(ic_valid_ff, _T_8871) @[ifu_mem_ctl.scala 693:97] + node _T_8873 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8874 = and(_T_8872, _T_8873) @[ifu_mem_ctl.scala 693:122] + node _T_8875 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 694:37] + node _T_8876 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8877 = and(_T_8875, _T_8876) @[ifu_mem_ctl.scala 694:59] + node _T_8878 = eq(perr_ic_index_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 694:102] + node _T_8879 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8880 = and(_T_8878, _T_8879) @[ifu_mem_ctl.scala 694:124] + node _T_8881 = or(_T_8877, _T_8880) @[ifu_mem_ctl.scala 694:81] + node _T_8882 = or(_T_8881, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8883 = bits(_T_8882, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8884 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8883 : @[Reg.scala 28:19] _T_8884 <= _T_8874 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][120] <= _T_8884 @[ifu_mem_ctl.scala 685:41] - node _T_8885 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8886 = eq(_T_8885, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8887 = and(ic_valid_ff, _T_8886) @[ifu_mem_ctl.scala 685:97] - node _T_8888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8889 = and(_T_8887, _T_8888) @[ifu_mem_ctl.scala 685:122] - node _T_8890 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 686:37] - node _T_8891 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8892 = and(_T_8890, _T_8891) @[ifu_mem_ctl.scala 686:59] - node _T_8893 = eq(perr_ic_index_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 686:102] - node _T_8894 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8895 = and(_T_8893, _T_8894) @[ifu_mem_ctl.scala 686:124] - node _T_8896 = or(_T_8892, _T_8895) @[ifu_mem_ctl.scala 686:81] - node _T_8897 = or(_T_8896, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8898 = bits(_T_8897, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][120] <= _T_8884 @[ifu_mem_ctl.scala 693:41] + node _T_8885 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8886 = eq(_T_8885, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8887 = and(ic_valid_ff, _T_8886) @[ifu_mem_ctl.scala 693:97] + node _T_8888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8889 = and(_T_8887, _T_8888) @[ifu_mem_ctl.scala 693:122] + node _T_8890 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 694:37] + node _T_8891 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8892 = and(_T_8890, _T_8891) @[ifu_mem_ctl.scala 694:59] + node _T_8893 = eq(perr_ic_index_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 694:102] + node _T_8894 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8895 = and(_T_8893, _T_8894) @[ifu_mem_ctl.scala 694:124] + node _T_8896 = or(_T_8892, _T_8895) @[ifu_mem_ctl.scala 694:81] + node _T_8897 = or(_T_8896, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8898 = bits(_T_8897, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8899 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8898 : @[Reg.scala 28:19] _T_8899 <= _T_8889 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][121] <= _T_8899 @[ifu_mem_ctl.scala 685:41] - node _T_8900 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8901 = eq(_T_8900, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8902 = and(ic_valid_ff, _T_8901) @[ifu_mem_ctl.scala 685:97] - node _T_8903 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8904 = and(_T_8902, _T_8903) @[ifu_mem_ctl.scala 685:122] - node _T_8905 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 686:37] - node _T_8906 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8907 = and(_T_8905, _T_8906) @[ifu_mem_ctl.scala 686:59] - node _T_8908 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 686:102] - node _T_8909 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8910 = and(_T_8908, _T_8909) @[ifu_mem_ctl.scala 686:124] - node _T_8911 = or(_T_8907, _T_8910) @[ifu_mem_ctl.scala 686:81] - node _T_8912 = or(_T_8911, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8913 = bits(_T_8912, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][121] <= _T_8899 @[ifu_mem_ctl.scala 693:41] + node _T_8900 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8901 = eq(_T_8900, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8902 = and(ic_valid_ff, _T_8901) @[ifu_mem_ctl.scala 693:97] + node _T_8903 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8904 = and(_T_8902, _T_8903) @[ifu_mem_ctl.scala 693:122] + node _T_8905 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 694:37] + node _T_8906 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8907 = and(_T_8905, _T_8906) @[ifu_mem_ctl.scala 694:59] + node _T_8908 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 694:102] + node _T_8909 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8910 = and(_T_8908, _T_8909) @[ifu_mem_ctl.scala 694:124] + node _T_8911 = or(_T_8907, _T_8910) @[ifu_mem_ctl.scala 694:81] + node _T_8912 = or(_T_8911, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8913 = bits(_T_8912, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8914 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8913 : @[Reg.scala 28:19] _T_8914 <= _T_8904 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][122] <= _T_8914 @[ifu_mem_ctl.scala 685:41] - node _T_8915 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8916 = eq(_T_8915, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8917 = and(ic_valid_ff, _T_8916) @[ifu_mem_ctl.scala 685:97] - node _T_8918 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8919 = and(_T_8917, _T_8918) @[ifu_mem_ctl.scala 685:122] - node _T_8920 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 686:37] - node _T_8921 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8922 = and(_T_8920, _T_8921) @[ifu_mem_ctl.scala 686:59] - node _T_8923 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 686:102] - node _T_8924 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8925 = and(_T_8923, _T_8924) @[ifu_mem_ctl.scala 686:124] - node _T_8926 = or(_T_8922, _T_8925) @[ifu_mem_ctl.scala 686:81] - node _T_8927 = or(_T_8926, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8928 = bits(_T_8927, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][122] <= _T_8914 @[ifu_mem_ctl.scala 693:41] + node _T_8915 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8916 = eq(_T_8915, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8917 = and(ic_valid_ff, _T_8916) @[ifu_mem_ctl.scala 693:97] + node _T_8918 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8919 = and(_T_8917, _T_8918) @[ifu_mem_ctl.scala 693:122] + node _T_8920 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 694:37] + node _T_8921 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8922 = and(_T_8920, _T_8921) @[ifu_mem_ctl.scala 694:59] + node _T_8923 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 694:102] + node _T_8924 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8925 = and(_T_8923, _T_8924) @[ifu_mem_ctl.scala 694:124] + node _T_8926 = or(_T_8922, _T_8925) @[ifu_mem_ctl.scala 694:81] + node _T_8927 = or(_T_8926, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8928 = bits(_T_8927, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8929 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8928 : @[Reg.scala 28:19] _T_8929 <= _T_8919 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][123] <= _T_8929 @[ifu_mem_ctl.scala 685:41] - node _T_8930 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8931 = eq(_T_8930, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8932 = and(ic_valid_ff, _T_8931) @[ifu_mem_ctl.scala 685:97] - node _T_8933 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8934 = and(_T_8932, _T_8933) @[ifu_mem_ctl.scala 685:122] - node _T_8935 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 686:37] - node _T_8936 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8937 = and(_T_8935, _T_8936) @[ifu_mem_ctl.scala 686:59] - node _T_8938 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 686:102] - node _T_8939 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8940 = and(_T_8938, _T_8939) @[ifu_mem_ctl.scala 686:124] - node _T_8941 = or(_T_8937, _T_8940) @[ifu_mem_ctl.scala 686:81] - node _T_8942 = or(_T_8941, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8943 = bits(_T_8942, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][123] <= _T_8929 @[ifu_mem_ctl.scala 693:41] + node _T_8930 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8931 = eq(_T_8930, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8932 = and(ic_valid_ff, _T_8931) @[ifu_mem_ctl.scala 693:97] + node _T_8933 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8934 = and(_T_8932, _T_8933) @[ifu_mem_ctl.scala 693:122] + node _T_8935 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 694:37] + node _T_8936 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8937 = and(_T_8935, _T_8936) @[ifu_mem_ctl.scala 694:59] + node _T_8938 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 694:102] + node _T_8939 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8940 = and(_T_8938, _T_8939) @[ifu_mem_ctl.scala 694:124] + node _T_8941 = or(_T_8937, _T_8940) @[ifu_mem_ctl.scala 694:81] + node _T_8942 = or(_T_8941, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8943 = bits(_T_8942, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8944 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8943 : @[Reg.scala 28:19] _T_8944 <= _T_8934 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][124] <= _T_8944 @[ifu_mem_ctl.scala 685:41] - node _T_8945 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8946 = eq(_T_8945, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8947 = and(ic_valid_ff, _T_8946) @[ifu_mem_ctl.scala 685:97] - node _T_8948 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8949 = and(_T_8947, _T_8948) @[ifu_mem_ctl.scala 685:122] - node _T_8950 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 686:37] - node _T_8951 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8952 = and(_T_8950, _T_8951) @[ifu_mem_ctl.scala 686:59] - node _T_8953 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 686:102] - node _T_8954 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8955 = and(_T_8953, _T_8954) @[ifu_mem_ctl.scala 686:124] - node _T_8956 = or(_T_8952, _T_8955) @[ifu_mem_ctl.scala 686:81] - node _T_8957 = or(_T_8956, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8958 = bits(_T_8957, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][124] <= _T_8944 @[ifu_mem_ctl.scala 693:41] + node _T_8945 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8946 = eq(_T_8945, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8947 = and(ic_valid_ff, _T_8946) @[ifu_mem_ctl.scala 693:97] + node _T_8948 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8949 = and(_T_8947, _T_8948) @[ifu_mem_ctl.scala 693:122] + node _T_8950 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 694:37] + node _T_8951 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8952 = and(_T_8950, _T_8951) @[ifu_mem_ctl.scala 694:59] + node _T_8953 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 694:102] + node _T_8954 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8955 = and(_T_8953, _T_8954) @[ifu_mem_ctl.scala 694:124] + node _T_8956 = or(_T_8952, _T_8955) @[ifu_mem_ctl.scala 694:81] + node _T_8957 = or(_T_8956, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8958 = bits(_T_8957, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8959 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8958 : @[Reg.scala 28:19] _T_8959 <= _T_8949 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][125] <= _T_8959 @[ifu_mem_ctl.scala 685:41] - node _T_8960 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8961 = eq(_T_8960, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8962 = and(ic_valid_ff, _T_8961) @[ifu_mem_ctl.scala 685:97] - node _T_8963 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8964 = and(_T_8962, _T_8963) @[ifu_mem_ctl.scala 685:122] - node _T_8965 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 686:37] - node _T_8966 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8967 = and(_T_8965, _T_8966) @[ifu_mem_ctl.scala 686:59] - node _T_8968 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 686:102] - node _T_8969 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8970 = and(_T_8968, _T_8969) @[ifu_mem_ctl.scala 686:124] - node _T_8971 = or(_T_8967, _T_8970) @[ifu_mem_ctl.scala 686:81] - node _T_8972 = or(_T_8971, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8973 = bits(_T_8972, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][125] <= _T_8959 @[ifu_mem_ctl.scala 693:41] + node _T_8960 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8961 = eq(_T_8960, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8962 = and(ic_valid_ff, _T_8961) @[ifu_mem_ctl.scala 693:97] + node _T_8963 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8964 = and(_T_8962, _T_8963) @[ifu_mem_ctl.scala 693:122] + node _T_8965 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 694:37] + node _T_8966 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8967 = and(_T_8965, _T_8966) @[ifu_mem_ctl.scala 694:59] + node _T_8968 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 694:102] + node _T_8969 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8970 = and(_T_8968, _T_8969) @[ifu_mem_ctl.scala 694:124] + node _T_8971 = or(_T_8967, _T_8970) @[ifu_mem_ctl.scala 694:81] + node _T_8972 = or(_T_8971, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8973 = bits(_T_8972, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8974 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8973 : @[Reg.scala 28:19] _T_8974 <= _T_8964 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][126] <= _T_8974 @[ifu_mem_ctl.scala 685:41] - node _T_8975 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 685:115] - node _T_8976 = eq(_T_8975, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:99] - node _T_8977 = and(ic_valid_ff, _T_8976) @[ifu_mem_ctl.scala 685:97] - node _T_8978 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:124] - node _T_8979 = and(_T_8977, _T_8978) @[ifu_mem_ctl.scala 685:122] - node _T_8980 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 686:37] - node _T_8981 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 686:76] - node _T_8982 = and(_T_8980, _T_8981) @[ifu_mem_ctl.scala 686:59] - node _T_8983 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 686:102] - node _T_8984 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 686:142] - node _T_8985 = and(_T_8983, _T_8984) @[ifu_mem_ctl.scala 686:124] - node _T_8986 = or(_T_8982, _T_8985) @[ifu_mem_ctl.scala 686:81] - node _T_8987 = or(_T_8986, reset_all_tags) @[ifu_mem_ctl.scala 686:147] - node _T_8988 = bits(_T_8987, 0, 0) @[ifu_mem_ctl.scala 686:166] + ic_tag_valid_out[1][126] <= _T_8974 @[ifu_mem_ctl.scala 693:41] + node _T_8975 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] + node _T_8976 = eq(_T_8975, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] + node _T_8977 = and(ic_valid_ff, _T_8976) @[ifu_mem_ctl.scala 693:97] + node _T_8978 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] + node _T_8979 = and(_T_8977, _T_8978) @[ifu_mem_ctl.scala 693:122] + node _T_8980 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 694:37] + node _T_8981 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] + node _T_8982 = and(_T_8980, _T_8981) @[ifu_mem_ctl.scala 694:59] + node _T_8983 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 694:102] + node _T_8984 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] + node _T_8985 = and(_T_8983, _T_8984) @[ifu_mem_ctl.scala 694:124] + node _T_8986 = or(_T_8982, _T_8985) @[ifu_mem_ctl.scala 694:81] + node _T_8987 = or(_T_8986, reset_all_tags) @[ifu_mem_ctl.scala 694:147] + node _T_8988 = bits(_T_8987, 0, 0) @[ifu_mem_ctl.scala 694:166] reg _T_8989 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8988 : @[Reg.scala 28:19] _T_8989 <= _T_8979 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][127] <= _T_8989 @[ifu_mem_ctl.scala 685:41] - node _T_8990 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 689:33] - node _T_8991 = mux(_T_8990, ic_tag_valid_out[0][0], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_8992 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 689:33] - node _T_8993 = mux(_T_8992, ic_tag_valid_out[0][1], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_8994 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 689:33] - node _T_8995 = mux(_T_8994, ic_tag_valid_out[0][2], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_8996 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 689:33] - node _T_8997 = mux(_T_8996, ic_tag_valid_out[0][3], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_8998 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 689:33] - node _T_8999 = mux(_T_8998, ic_tag_valid_out[0][4], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9000 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 689:33] - node _T_9001 = mux(_T_9000, ic_tag_valid_out[0][5], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9002 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 689:33] - node _T_9003 = mux(_T_9002, ic_tag_valid_out[0][6], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9004 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 689:33] - node _T_9005 = mux(_T_9004, ic_tag_valid_out[0][7], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9006 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 689:33] - node _T_9007 = mux(_T_9006, ic_tag_valid_out[0][8], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9008 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 689:33] - node _T_9009 = mux(_T_9008, ic_tag_valid_out[0][9], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9010 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 689:33] - node _T_9011 = mux(_T_9010, ic_tag_valid_out[0][10], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9012 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 689:33] - node _T_9013 = mux(_T_9012, ic_tag_valid_out[0][11], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9014 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 689:33] - node _T_9015 = mux(_T_9014, ic_tag_valid_out[0][12], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9016 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 689:33] - node _T_9017 = mux(_T_9016, ic_tag_valid_out[0][13], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9018 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 689:33] - node _T_9019 = mux(_T_9018, ic_tag_valid_out[0][14], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9020 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 689:33] - node _T_9021 = mux(_T_9020, ic_tag_valid_out[0][15], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9022 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 689:33] - node _T_9023 = mux(_T_9022, ic_tag_valid_out[0][16], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9024 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 689:33] - node _T_9025 = mux(_T_9024, ic_tag_valid_out[0][17], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9026 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 689:33] - node _T_9027 = mux(_T_9026, ic_tag_valid_out[0][18], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9028 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 689:33] - node _T_9029 = mux(_T_9028, ic_tag_valid_out[0][19], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9030 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 689:33] - node _T_9031 = mux(_T_9030, ic_tag_valid_out[0][20], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9032 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 689:33] - node _T_9033 = mux(_T_9032, ic_tag_valid_out[0][21], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9034 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 689:33] - node _T_9035 = mux(_T_9034, ic_tag_valid_out[0][22], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9036 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 689:33] - node _T_9037 = mux(_T_9036, ic_tag_valid_out[0][23], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9038 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 689:33] - node _T_9039 = mux(_T_9038, ic_tag_valid_out[0][24], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9040 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 689:33] - node _T_9041 = mux(_T_9040, ic_tag_valid_out[0][25], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9042 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 689:33] - node _T_9043 = mux(_T_9042, ic_tag_valid_out[0][26], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9044 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 689:33] - node _T_9045 = mux(_T_9044, ic_tag_valid_out[0][27], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9046 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 689:33] - node _T_9047 = mux(_T_9046, ic_tag_valid_out[0][28], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9048 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 689:33] - node _T_9049 = mux(_T_9048, ic_tag_valid_out[0][29], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9050 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 689:33] - node _T_9051 = mux(_T_9050, ic_tag_valid_out[0][30], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9052 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 689:33] - node _T_9053 = mux(_T_9052, ic_tag_valid_out[0][31], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9054 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 689:33] - node _T_9055 = mux(_T_9054, ic_tag_valid_out[0][32], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9056 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 689:33] - node _T_9057 = mux(_T_9056, ic_tag_valid_out[0][33], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9058 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 689:33] - node _T_9059 = mux(_T_9058, ic_tag_valid_out[0][34], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9060 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 689:33] - node _T_9061 = mux(_T_9060, ic_tag_valid_out[0][35], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9062 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 689:33] - node _T_9063 = mux(_T_9062, ic_tag_valid_out[0][36], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9064 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 689:33] - node _T_9065 = mux(_T_9064, ic_tag_valid_out[0][37], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9066 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 689:33] - node _T_9067 = mux(_T_9066, ic_tag_valid_out[0][38], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9068 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 689:33] - node _T_9069 = mux(_T_9068, ic_tag_valid_out[0][39], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9070 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 689:33] - node _T_9071 = mux(_T_9070, ic_tag_valid_out[0][40], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9072 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 689:33] - node _T_9073 = mux(_T_9072, ic_tag_valid_out[0][41], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9074 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 689:33] - node _T_9075 = mux(_T_9074, ic_tag_valid_out[0][42], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9076 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 689:33] - node _T_9077 = mux(_T_9076, ic_tag_valid_out[0][43], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9078 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 689:33] - node _T_9079 = mux(_T_9078, ic_tag_valid_out[0][44], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9080 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 689:33] - node _T_9081 = mux(_T_9080, ic_tag_valid_out[0][45], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9082 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 689:33] - node _T_9083 = mux(_T_9082, ic_tag_valid_out[0][46], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9084 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 689:33] - node _T_9085 = mux(_T_9084, ic_tag_valid_out[0][47], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9086 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 689:33] - node _T_9087 = mux(_T_9086, ic_tag_valid_out[0][48], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9088 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 689:33] - node _T_9089 = mux(_T_9088, ic_tag_valid_out[0][49], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9090 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 689:33] - node _T_9091 = mux(_T_9090, ic_tag_valid_out[0][50], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9092 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 689:33] - node _T_9093 = mux(_T_9092, ic_tag_valid_out[0][51], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9094 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 689:33] - node _T_9095 = mux(_T_9094, ic_tag_valid_out[0][52], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9096 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 689:33] - node _T_9097 = mux(_T_9096, ic_tag_valid_out[0][53], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9098 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 689:33] - node _T_9099 = mux(_T_9098, ic_tag_valid_out[0][54], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9100 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 689:33] - node _T_9101 = mux(_T_9100, ic_tag_valid_out[0][55], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9102 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 689:33] - node _T_9103 = mux(_T_9102, ic_tag_valid_out[0][56], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9104 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 689:33] - node _T_9105 = mux(_T_9104, ic_tag_valid_out[0][57], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9106 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 689:33] - node _T_9107 = mux(_T_9106, ic_tag_valid_out[0][58], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9108 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 689:33] - node _T_9109 = mux(_T_9108, ic_tag_valid_out[0][59], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9110 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 689:33] - node _T_9111 = mux(_T_9110, ic_tag_valid_out[0][60], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9112 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 689:33] - node _T_9113 = mux(_T_9112, ic_tag_valid_out[0][61], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9114 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 689:33] - node _T_9115 = mux(_T_9114, ic_tag_valid_out[0][62], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9116 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 689:33] - node _T_9117 = mux(_T_9116, ic_tag_valid_out[0][63], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9118 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 689:33] - node _T_9119 = mux(_T_9118, ic_tag_valid_out[0][64], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9120 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 689:33] - node _T_9121 = mux(_T_9120, ic_tag_valid_out[0][65], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9122 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 689:33] - node _T_9123 = mux(_T_9122, ic_tag_valid_out[0][66], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9124 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 689:33] - node _T_9125 = mux(_T_9124, ic_tag_valid_out[0][67], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9126 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 689:33] - node _T_9127 = mux(_T_9126, ic_tag_valid_out[0][68], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9128 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 689:33] - node _T_9129 = mux(_T_9128, ic_tag_valid_out[0][69], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9130 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 689:33] - node _T_9131 = mux(_T_9130, ic_tag_valid_out[0][70], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9132 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 689:33] - node _T_9133 = mux(_T_9132, ic_tag_valid_out[0][71], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9134 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 689:33] - node _T_9135 = mux(_T_9134, ic_tag_valid_out[0][72], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9136 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 689:33] - node _T_9137 = mux(_T_9136, ic_tag_valid_out[0][73], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9138 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 689:33] - node _T_9139 = mux(_T_9138, ic_tag_valid_out[0][74], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9140 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 689:33] - node _T_9141 = mux(_T_9140, ic_tag_valid_out[0][75], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9142 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 689:33] - node _T_9143 = mux(_T_9142, ic_tag_valid_out[0][76], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9144 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 689:33] - node _T_9145 = mux(_T_9144, ic_tag_valid_out[0][77], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9146 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 689:33] - node _T_9147 = mux(_T_9146, ic_tag_valid_out[0][78], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9148 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 689:33] - node _T_9149 = mux(_T_9148, ic_tag_valid_out[0][79], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9150 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 689:33] - node _T_9151 = mux(_T_9150, ic_tag_valid_out[0][80], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9152 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 689:33] - node _T_9153 = mux(_T_9152, ic_tag_valid_out[0][81], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9154 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 689:33] - node _T_9155 = mux(_T_9154, ic_tag_valid_out[0][82], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9156 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 689:33] - node _T_9157 = mux(_T_9156, ic_tag_valid_out[0][83], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9158 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 689:33] - node _T_9159 = mux(_T_9158, ic_tag_valid_out[0][84], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9160 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 689:33] - node _T_9161 = mux(_T_9160, ic_tag_valid_out[0][85], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9162 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 689:33] - node _T_9163 = mux(_T_9162, ic_tag_valid_out[0][86], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9164 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 689:33] - node _T_9165 = mux(_T_9164, ic_tag_valid_out[0][87], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9166 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 689:33] - node _T_9167 = mux(_T_9166, ic_tag_valid_out[0][88], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9168 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 689:33] - node _T_9169 = mux(_T_9168, ic_tag_valid_out[0][89], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 689:33] - node _T_9171 = mux(_T_9170, ic_tag_valid_out[0][90], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9172 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 689:33] - node _T_9173 = mux(_T_9172, ic_tag_valid_out[0][91], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9174 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 689:33] - node _T_9175 = mux(_T_9174, ic_tag_valid_out[0][92], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9176 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 689:33] - node _T_9177 = mux(_T_9176, ic_tag_valid_out[0][93], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9178 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 689:33] - node _T_9179 = mux(_T_9178, ic_tag_valid_out[0][94], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 689:33] - node _T_9181 = mux(_T_9180, ic_tag_valid_out[0][95], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9182 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 689:33] - node _T_9183 = mux(_T_9182, ic_tag_valid_out[0][96], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9184 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 689:33] - node _T_9185 = mux(_T_9184, ic_tag_valid_out[0][97], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9186 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 689:33] - node _T_9187 = mux(_T_9186, ic_tag_valid_out[0][98], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9188 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 689:33] - node _T_9189 = mux(_T_9188, ic_tag_valid_out[0][99], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9190 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 689:33] - node _T_9191 = mux(_T_9190, ic_tag_valid_out[0][100], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9192 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 689:33] - node _T_9193 = mux(_T_9192, ic_tag_valid_out[0][101], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9194 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 689:33] - node _T_9195 = mux(_T_9194, ic_tag_valid_out[0][102], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9196 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 689:33] - node _T_9197 = mux(_T_9196, ic_tag_valid_out[0][103], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9198 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 689:33] - node _T_9199 = mux(_T_9198, ic_tag_valid_out[0][104], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 689:33] - node _T_9201 = mux(_T_9200, ic_tag_valid_out[0][105], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9202 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 689:33] - node _T_9203 = mux(_T_9202, ic_tag_valid_out[0][106], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9204 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 689:33] - node _T_9205 = mux(_T_9204, ic_tag_valid_out[0][107], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9206 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 689:33] - node _T_9207 = mux(_T_9206, ic_tag_valid_out[0][108], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9208 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 689:33] - node _T_9209 = mux(_T_9208, ic_tag_valid_out[0][109], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 689:33] - node _T_9211 = mux(_T_9210, ic_tag_valid_out[0][110], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9212 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 689:33] - node _T_9213 = mux(_T_9212, ic_tag_valid_out[0][111], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9214 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 689:33] - node _T_9215 = mux(_T_9214, ic_tag_valid_out[0][112], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9216 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 689:33] - node _T_9217 = mux(_T_9216, ic_tag_valid_out[0][113], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9218 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 689:33] - node _T_9219 = mux(_T_9218, ic_tag_valid_out[0][114], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9220 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 689:33] - node _T_9221 = mux(_T_9220, ic_tag_valid_out[0][115], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9222 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 689:33] - node _T_9223 = mux(_T_9222, ic_tag_valid_out[0][116], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9224 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 689:33] - node _T_9225 = mux(_T_9224, ic_tag_valid_out[0][117], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9226 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 689:33] - node _T_9227 = mux(_T_9226, ic_tag_valid_out[0][118], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9228 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 689:33] - node _T_9229 = mux(_T_9228, ic_tag_valid_out[0][119], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9230 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 689:33] - node _T_9231 = mux(_T_9230, ic_tag_valid_out[0][120], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9232 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 689:33] - node _T_9233 = mux(_T_9232, ic_tag_valid_out[0][121], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9234 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 689:33] - node _T_9235 = mux(_T_9234, ic_tag_valid_out[0][122], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9236 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 689:33] - node _T_9237 = mux(_T_9236, ic_tag_valid_out[0][123], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9238 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 689:33] - node _T_9239 = mux(_T_9238, ic_tag_valid_out[0][124], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9240 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 689:33] - node _T_9241 = mux(_T_9240, ic_tag_valid_out[0][125], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9242 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 689:33] - node _T_9243 = mux(_T_9242, ic_tag_valid_out[0][126], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9244 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 689:33] - node _T_9245 = mux(_T_9244, ic_tag_valid_out[0][127], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9246 = or(_T_8991, _T_8993) @[ifu_mem_ctl.scala 689:91] - node _T_9247 = or(_T_9246, _T_8995) @[ifu_mem_ctl.scala 689:91] - node _T_9248 = or(_T_9247, _T_8997) @[ifu_mem_ctl.scala 689:91] - node _T_9249 = or(_T_9248, _T_8999) @[ifu_mem_ctl.scala 689:91] - node _T_9250 = or(_T_9249, _T_9001) @[ifu_mem_ctl.scala 689:91] - node _T_9251 = or(_T_9250, _T_9003) @[ifu_mem_ctl.scala 689:91] - node _T_9252 = or(_T_9251, _T_9005) @[ifu_mem_ctl.scala 689:91] - node _T_9253 = or(_T_9252, _T_9007) @[ifu_mem_ctl.scala 689:91] - node _T_9254 = or(_T_9253, _T_9009) @[ifu_mem_ctl.scala 689:91] - node _T_9255 = or(_T_9254, _T_9011) @[ifu_mem_ctl.scala 689:91] - node _T_9256 = or(_T_9255, _T_9013) @[ifu_mem_ctl.scala 689:91] - node _T_9257 = or(_T_9256, _T_9015) @[ifu_mem_ctl.scala 689:91] - node _T_9258 = or(_T_9257, _T_9017) @[ifu_mem_ctl.scala 689:91] - node _T_9259 = or(_T_9258, _T_9019) @[ifu_mem_ctl.scala 689:91] - node _T_9260 = or(_T_9259, _T_9021) @[ifu_mem_ctl.scala 689:91] - node _T_9261 = or(_T_9260, _T_9023) @[ifu_mem_ctl.scala 689:91] - node _T_9262 = or(_T_9261, _T_9025) @[ifu_mem_ctl.scala 689:91] - node _T_9263 = or(_T_9262, _T_9027) @[ifu_mem_ctl.scala 689:91] - node _T_9264 = or(_T_9263, _T_9029) @[ifu_mem_ctl.scala 689:91] - node _T_9265 = or(_T_9264, _T_9031) @[ifu_mem_ctl.scala 689:91] - node _T_9266 = or(_T_9265, _T_9033) @[ifu_mem_ctl.scala 689:91] - node _T_9267 = or(_T_9266, _T_9035) @[ifu_mem_ctl.scala 689:91] - node _T_9268 = or(_T_9267, _T_9037) @[ifu_mem_ctl.scala 689:91] - node _T_9269 = or(_T_9268, _T_9039) @[ifu_mem_ctl.scala 689:91] - node _T_9270 = or(_T_9269, _T_9041) @[ifu_mem_ctl.scala 689:91] - node _T_9271 = or(_T_9270, _T_9043) @[ifu_mem_ctl.scala 689:91] - node _T_9272 = or(_T_9271, _T_9045) @[ifu_mem_ctl.scala 689:91] - node _T_9273 = or(_T_9272, _T_9047) @[ifu_mem_ctl.scala 689:91] - node _T_9274 = or(_T_9273, _T_9049) @[ifu_mem_ctl.scala 689:91] - node _T_9275 = or(_T_9274, _T_9051) @[ifu_mem_ctl.scala 689:91] - node _T_9276 = or(_T_9275, _T_9053) @[ifu_mem_ctl.scala 689:91] - node _T_9277 = or(_T_9276, _T_9055) @[ifu_mem_ctl.scala 689:91] - node _T_9278 = or(_T_9277, _T_9057) @[ifu_mem_ctl.scala 689:91] - node _T_9279 = or(_T_9278, _T_9059) @[ifu_mem_ctl.scala 689:91] - node _T_9280 = or(_T_9279, _T_9061) @[ifu_mem_ctl.scala 689:91] - node _T_9281 = or(_T_9280, _T_9063) @[ifu_mem_ctl.scala 689:91] - node _T_9282 = or(_T_9281, _T_9065) @[ifu_mem_ctl.scala 689:91] - node _T_9283 = or(_T_9282, _T_9067) @[ifu_mem_ctl.scala 689:91] - node _T_9284 = or(_T_9283, _T_9069) @[ifu_mem_ctl.scala 689:91] - node _T_9285 = or(_T_9284, _T_9071) @[ifu_mem_ctl.scala 689:91] - node _T_9286 = or(_T_9285, _T_9073) @[ifu_mem_ctl.scala 689:91] - node _T_9287 = or(_T_9286, _T_9075) @[ifu_mem_ctl.scala 689:91] - node _T_9288 = or(_T_9287, _T_9077) @[ifu_mem_ctl.scala 689:91] - node _T_9289 = or(_T_9288, _T_9079) @[ifu_mem_ctl.scala 689:91] - node _T_9290 = or(_T_9289, _T_9081) @[ifu_mem_ctl.scala 689:91] - node _T_9291 = or(_T_9290, _T_9083) @[ifu_mem_ctl.scala 689:91] - node _T_9292 = or(_T_9291, _T_9085) @[ifu_mem_ctl.scala 689:91] - node _T_9293 = or(_T_9292, _T_9087) @[ifu_mem_ctl.scala 689:91] - node _T_9294 = or(_T_9293, _T_9089) @[ifu_mem_ctl.scala 689:91] - node _T_9295 = or(_T_9294, _T_9091) @[ifu_mem_ctl.scala 689:91] - node _T_9296 = or(_T_9295, _T_9093) @[ifu_mem_ctl.scala 689:91] - node _T_9297 = or(_T_9296, _T_9095) @[ifu_mem_ctl.scala 689:91] - node _T_9298 = or(_T_9297, _T_9097) @[ifu_mem_ctl.scala 689:91] - node _T_9299 = or(_T_9298, _T_9099) @[ifu_mem_ctl.scala 689:91] - node _T_9300 = or(_T_9299, _T_9101) @[ifu_mem_ctl.scala 689:91] - node _T_9301 = or(_T_9300, _T_9103) @[ifu_mem_ctl.scala 689:91] - node _T_9302 = or(_T_9301, _T_9105) @[ifu_mem_ctl.scala 689:91] - node _T_9303 = or(_T_9302, _T_9107) @[ifu_mem_ctl.scala 689:91] - node _T_9304 = or(_T_9303, _T_9109) @[ifu_mem_ctl.scala 689:91] - node _T_9305 = or(_T_9304, _T_9111) @[ifu_mem_ctl.scala 689:91] - node _T_9306 = or(_T_9305, _T_9113) @[ifu_mem_ctl.scala 689:91] - node _T_9307 = or(_T_9306, _T_9115) @[ifu_mem_ctl.scala 689:91] - node _T_9308 = or(_T_9307, _T_9117) @[ifu_mem_ctl.scala 689:91] - node _T_9309 = or(_T_9308, _T_9119) @[ifu_mem_ctl.scala 689:91] - node _T_9310 = or(_T_9309, _T_9121) @[ifu_mem_ctl.scala 689:91] - node _T_9311 = or(_T_9310, _T_9123) @[ifu_mem_ctl.scala 689:91] - node _T_9312 = or(_T_9311, _T_9125) @[ifu_mem_ctl.scala 689:91] - node _T_9313 = or(_T_9312, _T_9127) @[ifu_mem_ctl.scala 689:91] - node _T_9314 = or(_T_9313, _T_9129) @[ifu_mem_ctl.scala 689:91] - node _T_9315 = or(_T_9314, _T_9131) @[ifu_mem_ctl.scala 689:91] - node _T_9316 = or(_T_9315, _T_9133) @[ifu_mem_ctl.scala 689:91] - node _T_9317 = or(_T_9316, _T_9135) @[ifu_mem_ctl.scala 689:91] - node _T_9318 = or(_T_9317, _T_9137) @[ifu_mem_ctl.scala 689:91] - node _T_9319 = or(_T_9318, _T_9139) @[ifu_mem_ctl.scala 689:91] - node _T_9320 = or(_T_9319, _T_9141) @[ifu_mem_ctl.scala 689:91] - node _T_9321 = or(_T_9320, _T_9143) @[ifu_mem_ctl.scala 689:91] - node _T_9322 = or(_T_9321, _T_9145) @[ifu_mem_ctl.scala 689:91] - node _T_9323 = or(_T_9322, _T_9147) @[ifu_mem_ctl.scala 689:91] - node _T_9324 = or(_T_9323, _T_9149) @[ifu_mem_ctl.scala 689:91] - node _T_9325 = or(_T_9324, _T_9151) @[ifu_mem_ctl.scala 689:91] - node _T_9326 = or(_T_9325, _T_9153) @[ifu_mem_ctl.scala 689:91] - node _T_9327 = or(_T_9326, _T_9155) @[ifu_mem_ctl.scala 689:91] - node _T_9328 = or(_T_9327, _T_9157) @[ifu_mem_ctl.scala 689:91] - node _T_9329 = or(_T_9328, _T_9159) @[ifu_mem_ctl.scala 689:91] - node _T_9330 = or(_T_9329, _T_9161) @[ifu_mem_ctl.scala 689:91] - node _T_9331 = or(_T_9330, _T_9163) @[ifu_mem_ctl.scala 689:91] - node _T_9332 = or(_T_9331, _T_9165) @[ifu_mem_ctl.scala 689:91] - node _T_9333 = or(_T_9332, _T_9167) @[ifu_mem_ctl.scala 689:91] - node _T_9334 = or(_T_9333, _T_9169) @[ifu_mem_ctl.scala 689:91] - node _T_9335 = or(_T_9334, _T_9171) @[ifu_mem_ctl.scala 689:91] - node _T_9336 = or(_T_9335, _T_9173) @[ifu_mem_ctl.scala 689:91] - node _T_9337 = or(_T_9336, _T_9175) @[ifu_mem_ctl.scala 689:91] - node _T_9338 = or(_T_9337, _T_9177) @[ifu_mem_ctl.scala 689:91] - node _T_9339 = or(_T_9338, _T_9179) @[ifu_mem_ctl.scala 689:91] - node _T_9340 = or(_T_9339, _T_9181) @[ifu_mem_ctl.scala 689:91] - node _T_9341 = or(_T_9340, _T_9183) @[ifu_mem_ctl.scala 689:91] - node _T_9342 = or(_T_9341, _T_9185) @[ifu_mem_ctl.scala 689:91] - node _T_9343 = or(_T_9342, _T_9187) @[ifu_mem_ctl.scala 689:91] - node _T_9344 = or(_T_9343, _T_9189) @[ifu_mem_ctl.scala 689:91] - node _T_9345 = or(_T_9344, _T_9191) @[ifu_mem_ctl.scala 689:91] - node _T_9346 = or(_T_9345, _T_9193) @[ifu_mem_ctl.scala 689:91] - node _T_9347 = or(_T_9346, _T_9195) @[ifu_mem_ctl.scala 689:91] - node _T_9348 = or(_T_9347, _T_9197) @[ifu_mem_ctl.scala 689:91] - node _T_9349 = or(_T_9348, _T_9199) @[ifu_mem_ctl.scala 689:91] - node _T_9350 = or(_T_9349, _T_9201) @[ifu_mem_ctl.scala 689:91] - node _T_9351 = or(_T_9350, _T_9203) @[ifu_mem_ctl.scala 689:91] - node _T_9352 = or(_T_9351, _T_9205) @[ifu_mem_ctl.scala 689:91] - node _T_9353 = or(_T_9352, _T_9207) @[ifu_mem_ctl.scala 689:91] - node _T_9354 = or(_T_9353, _T_9209) @[ifu_mem_ctl.scala 689:91] - node _T_9355 = or(_T_9354, _T_9211) @[ifu_mem_ctl.scala 689:91] - node _T_9356 = or(_T_9355, _T_9213) @[ifu_mem_ctl.scala 689:91] - node _T_9357 = or(_T_9356, _T_9215) @[ifu_mem_ctl.scala 689:91] - node _T_9358 = or(_T_9357, _T_9217) @[ifu_mem_ctl.scala 689:91] - node _T_9359 = or(_T_9358, _T_9219) @[ifu_mem_ctl.scala 689:91] - node _T_9360 = or(_T_9359, _T_9221) @[ifu_mem_ctl.scala 689:91] - node _T_9361 = or(_T_9360, _T_9223) @[ifu_mem_ctl.scala 689:91] - node _T_9362 = or(_T_9361, _T_9225) @[ifu_mem_ctl.scala 689:91] - node _T_9363 = or(_T_9362, _T_9227) @[ifu_mem_ctl.scala 689:91] - node _T_9364 = or(_T_9363, _T_9229) @[ifu_mem_ctl.scala 689:91] - node _T_9365 = or(_T_9364, _T_9231) @[ifu_mem_ctl.scala 689:91] - node _T_9366 = or(_T_9365, _T_9233) @[ifu_mem_ctl.scala 689:91] - node _T_9367 = or(_T_9366, _T_9235) @[ifu_mem_ctl.scala 689:91] - node _T_9368 = or(_T_9367, _T_9237) @[ifu_mem_ctl.scala 689:91] - node _T_9369 = or(_T_9368, _T_9239) @[ifu_mem_ctl.scala 689:91] - node _T_9370 = or(_T_9369, _T_9241) @[ifu_mem_ctl.scala 689:91] - node _T_9371 = or(_T_9370, _T_9243) @[ifu_mem_ctl.scala 689:91] - node _T_9372 = or(_T_9371, _T_9245) @[ifu_mem_ctl.scala 689:91] - node _T_9373 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 689:33] - node _T_9374 = mux(_T_9373, ic_tag_valid_out[1][0], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9375 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 689:33] - node _T_9376 = mux(_T_9375, ic_tag_valid_out[1][1], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9377 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 689:33] - node _T_9378 = mux(_T_9377, ic_tag_valid_out[1][2], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9379 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 689:33] - node _T_9380 = mux(_T_9379, ic_tag_valid_out[1][3], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9381 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 689:33] - node _T_9382 = mux(_T_9381, ic_tag_valid_out[1][4], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9383 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 689:33] - node _T_9384 = mux(_T_9383, ic_tag_valid_out[1][5], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9385 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 689:33] - node _T_9386 = mux(_T_9385, ic_tag_valid_out[1][6], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9387 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 689:33] - node _T_9388 = mux(_T_9387, ic_tag_valid_out[1][7], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9389 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 689:33] - node _T_9390 = mux(_T_9389, ic_tag_valid_out[1][8], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9391 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 689:33] - node _T_9392 = mux(_T_9391, ic_tag_valid_out[1][9], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9393 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 689:33] - node _T_9394 = mux(_T_9393, ic_tag_valid_out[1][10], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9395 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 689:33] - node _T_9396 = mux(_T_9395, ic_tag_valid_out[1][11], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9397 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 689:33] - node _T_9398 = mux(_T_9397, ic_tag_valid_out[1][12], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9399 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 689:33] - node _T_9400 = mux(_T_9399, ic_tag_valid_out[1][13], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9401 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 689:33] - node _T_9402 = mux(_T_9401, ic_tag_valid_out[1][14], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9403 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 689:33] - node _T_9404 = mux(_T_9403, ic_tag_valid_out[1][15], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9405 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 689:33] - node _T_9406 = mux(_T_9405, ic_tag_valid_out[1][16], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9407 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 689:33] - node _T_9408 = mux(_T_9407, ic_tag_valid_out[1][17], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9409 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 689:33] - node _T_9410 = mux(_T_9409, ic_tag_valid_out[1][18], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9411 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 689:33] - node _T_9412 = mux(_T_9411, ic_tag_valid_out[1][19], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9413 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 689:33] - node _T_9414 = mux(_T_9413, ic_tag_valid_out[1][20], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9415 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 689:33] - node _T_9416 = mux(_T_9415, ic_tag_valid_out[1][21], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9417 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 689:33] - node _T_9418 = mux(_T_9417, ic_tag_valid_out[1][22], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9419 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 689:33] - node _T_9420 = mux(_T_9419, ic_tag_valid_out[1][23], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9421 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 689:33] - node _T_9422 = mux(_T_9421, ic_tag_valid_out[1][24], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9423 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 689:33] - node _T_9424 = mux(_T_9423, ic_tag_valid_out[1][25], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9425 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 689:33] - node _T_9426 = mux(_T_9425, ic_tag_valid_out[1][26], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9427 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 689:33] - node _T_9428 = mux(_T_9427, ic_tag_valid_out[1][27], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9429 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 689:33] - node _T_9430 = mux(_T_9429, ic_tag_valid_out[1][28], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9431 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 689:33] - node _T_9432 = mux(_T_9431, ic_tag_valid_out[1][29], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9433 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 689:33] - node _T_9434 = mux(_T_9433, ic_tag_valid_out[1][30], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9435 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 689:33] - node _T_9436 = mux(_T_9435, ic_tag_valid_out[1][31], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9437 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 689:33] - node _T_9438 = mux(_T_9437, ic_tag_valid_out[1][32], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9439 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 689:33] - node _T_9440 = mux(_T_9439, ic_tag_valid_out[1][33], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9441 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 689:33] - node _T_9442 = mux(_T_9441, ic_tag_valid_out[1][34], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9443 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 689:33] - node _T_9444 = mux(_T_9443, ic_tag_valid_out[1][35], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9445 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 689:33] - node _T_9446 = mux(_T_9445, ic_tag_valid_out[1][36], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9447 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 689:33] - node _T_9448 = mux(_T_9447, ic_tag_valid_out[1][37], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9449 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 689:33] - node _T_9450 = mux(_T_9449, ic_tag_valid_out[1][38], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9451 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 689:33] - node _T_9452 = mux(_T_9451, ic_tag_valid_out[1][39], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9453 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 689:33] - node _T_9454 = mux(_T_9453, ic_tag_valid_out[1][40], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9455 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 689:33] - node _T_9456 = mux(_T_9455, ic_tag_valid_out[1][41], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9457 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 689:33] - node _T_9458 = mux(_T_9457, ic_tag_valid_out[1][42], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9459 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 689:33] - node _T_9460 = mux(_T_9459, ic_tag_valid_out[1][43], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9461 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 689:33] - node _T_9462 = mux(_T_9461, ic_tag_valid_out[1][44], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9463 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 689:33] - node _T_9464 = mux(_T_9463, ic_tag_valid_out[1][45], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9465 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 689:33] - node _T_9466 = mux(_T_9465, ic_tag_valid_out[1][46], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9467 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 689:33] - node _T_9468 = mux(_T_9467, ic_tag_valid_out[1][47], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9469 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 689:33] - node _T_9470 = mux(_T_9469, ic_tag_valid_out[1][48], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9471 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 689:33] - node _T_9472 = mux(_T_9471, ic_tag_valid_out[1][49], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9473 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 689:33] - node _T_9474 = mux(_T_9473, ic_tag_valid_out[1][50], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9475 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 689:33] - node _T_9476 = mux(_T_9475, ic_tag_valid_out[1][51], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9477 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 689:33] - node _T_9478 = mux(_T_9477, ic_tag_valid_out[1][52], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9479 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 689:33] - node _T_9480 = mux(_T_9479, ic_tag_valid_out[1][53], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9481 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 689:33] - node _T_9482 = mux(_T_9481, ic_tag_valid_out[1][54], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9483 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 689:33] - node _T_9484 = mux(_T_9483, ic_tag_valid_out[1][55], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9485 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 689:33] - node _T_9486 = mux(_T_9485, ic_tag_valid_out[1][56], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9487 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 689:33] - node _T_9488 = mux(_T_9487, ic_tag_valid_out[1][57], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9489 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 689:33] - node _T_9490 = mux(_T_9489, ic_tag_valid_out[1][58], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9491 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 689:33] - node _T_9492 = mux(_T_9491, ic_tag_valid_out[1][59], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9493 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 689:33] - node _T_9494 = mux(_T_9493, ic_tag_valid_out[1][60], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9495 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 689:33] - node _T_9496 = mux(_T_9495, ic_tag_valid_out[1][61], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9497 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 689:33] - node _T_9498 = mux(_T_9497, ic_tag_valid_out[1][62], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9499 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 689:33] - node _T_9500 = mux(_T_9499, ic_tag_valid_out[1][63], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9501 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 689:33] - node _T_9502 = mux(_T_9501, ic_tag_valid_out[1][64], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9503 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 689:33] - node _T_9504 = mux(_T_9503, ic_tag_valid_out[1][65], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9505 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 689:33] - node _T_9506 = mux(_T_9505, ic_tag_valid_out[1][66], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9507 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 689:33] - node _T_9508 = mux(_T_9507, ic_tag_valid_out[1][67], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9509 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 689:33] - node _T_9510 = mux(_T_9509, ic_tag_valid_out[1][68], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9511 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 689:33] - node _T_9512 = mux(_T_9511, ic_tag_valid_out[1][69], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9513 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 689:33] - node _T_9514 = mux(_T_9513, ic_tag_valid_out[1][70], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 689:33] - node _T_9516 = mux(_T_9515, ic_tag_valid_out[1][71], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9517 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 689:33] - node _T_9518 = mux(_T_9517, ic_tag_valid_out[1][72], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9519 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 689:33] - node _T_9520 = mux(_T_9519, ic_tag_valid_out[1][73], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9521 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 689:33] - node _T_9522 = mux(_T_9521, ic_tag_valid_out[1][74], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9523 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 689:33] - node _T_9524 = mux(_T_9523, ic_tag_valid_out[1][75], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 689:33] - node _T_9526 = mux(_T_9525, ic_tag_valid_out[1][76], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9527 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 689:33] - node _T_9528 = mux(_T_9527, ic_tag_valid_out[1][77], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9529 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 689:33] - node _T_9530 = mux(_T_9529, ic_tag_valid_out[1][78], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9531 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 689:33] - node _T_9532 = mux(_T_9531, ic_tag_valid_out[1][79], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9533 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 689:33] - node _T_9534 = mux(_T_9533, ic_tag_valid_out[1][80], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9535 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 689:33] - node _T_9536 = mux(_T_9535, ic_tag_valid_out[1][81], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9537 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 689:33] - node _T_9538 = mux(_T_9537, ic_tag_valid_out[1][82], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9539 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 689:33] - node _T_9540 = mux(_T_9539, ic_tag_valid_out[1][83], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9541 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 689:33] - node _T_9542 = mux(_T_9541, ic_tag_valid_out[1][84], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9543 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 689:33] - node _T_9544 = mux(_T_9543, ic_tag_valid_out[1][85], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 689:33] - node _T_9546 = mux(_T_9545, ic_tag_valid_out[1][86], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9547 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 689:33] - node _T_9548 = mux(_T_9547, ic_tag_valid_out[1][87], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9549 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 689:33] - node _T_9550 = mux(_T_9549, ic_tag_valid_out[1][88], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9551 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 689:33] - node _T_9552 = mux(_T_9551, ic_tag_valid_out[1][89], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9553 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 689:33] - node _T_9554 = mux(_T_9553, ic_tag_valid_out[1][90], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9555 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 689:33] - node _T_9556 = mux(_T_9555, ic_tag_valid_out[1][91], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9557 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 689:33] - node _T_9558 = mux(_T_9557, ic_tag_valid_out[1][92], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9559 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 689:33] - node _T_9560 = mux(_T_9559, ic_tag_valid_out[1][93], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9561 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 689:33] - node _T_9562 = mux(_T_9561, ic_tag_valid_out[1][94], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9563 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 689:33] - node _T_9564 = mux(_T_9563, ic_tag_valid_out[1][95], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9565 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 689:33] - node _T_9566 = mux(_T_9565, ic_tag_valid_out[1][96], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9567 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 689:33] - node _T_9568 = mux(_T_9567, ic_tag_valid_out[1][97], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9569 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 689:33] - node _T_9570 = mux(_T_9569, ic_tag_valid_out[1][98], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9571 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 689:33] - node _T_9572 = mux(_T_9571, ic_tag_valid_out[1][99], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9573 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 689:33] - node _T_9574 = mux(_T_9573, ic_tag_valid_out[1][100], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9575 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 689:33] - node _T_9576 = mux(_T_9575, ic_tag_valid_out[1][101], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9577 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 689:33] - node _T_9578 = mux(_T_9577, ic_tag_valid_out[1][102], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9579 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 689:33] - node _T_9580 = mux(_T_9579, ic_tag_valid_out[1][103], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9581 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 689:33] - node _T_9582 = mux(_T_9581, ic_tag_valid_out[1][104], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9583 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 689:33] - node _T_9584 = mux(_T_9583, ic_tag_valid_out[1][105], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9585 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 689:33] - node _T_9586 = mux(_T_9585, ic_tag_valid_out[1][106], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9587 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 689:33] - node _T_9588 = mux(_T_9587, ic_tag_valid_out[1][107], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9589 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 689:33] - node _T_9590 = mux(_T_9589, ic_tag_valid_out[1][108], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9591 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 689:33] - node _T_9592 = mux(_T_9591, ic_tag_valid_out[1][109], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9593 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 689:33] - node _T_9594 = mux(_T_9593, ic_tag_valid_out[1][110], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9595 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 689:33] - node _T_9596 = mux(_T_9595, ic_tag_valid_out[1][111], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9597 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 689:33] - node _T_9598 = mux(_T_9597, ic_tag_valid_out[1][112], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9599 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 689:33] - node _T_9600 = mux(_T_9599, ic_tag_valid_out[1][113], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9601 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 689:33] - node _T_9602 = mux(_T_9601, ic_tag_valid_out[1][114], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9603 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 689:33] - node _T_9604 = mux(_T_9603, ic_tag_valid_out[1][115], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9605 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 689:33] - node _T_9606 = mux(_T_9605, ic_tag_valid_out[1][116], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9607 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 689:33] - node _T_9608 = mux(_T_9607, ic_tag_valid_out[1][117], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9609 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 689:33] - node _T_9610 = mux(_T_9609, ic_tag_valid_out[1][118], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9611 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 689:33] - node _T_9612 = mux(_T_9611, ic_tag_valid_out[1][119], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9613 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 689:33] - node _T_9614 = mux(_T_9613, ic_tag_valid_out[1][120], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9615 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 689:33] - node _T_9616 = mux(_T_9615, ic_tag_valid_out[1][121], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9617 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 689:33] - node _T_9618 = mux(_T_9617, ic_tag_valid_out[1][122], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9619 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 689:33] - node _T_9620 = mux(_T_9619, ic_tag_valid_out[1][123], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9621 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 689:33] - node _T_9622 = mux(_T_9621, ic_tag_valid_out[1][124], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9623 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 689:33] - node _T_9624 = mux(_T_9623, ic_tag_valid_out[1][125], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9625 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 689:33] - node _T_9626 = mux(_T_9625, ic_tag_valid_out[1][126], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9627 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 689:33] - node _T_9628 = mux(_T_9627, ic_tag_valid_out[1][127], UInt<1>("h00")) @[ifu_mem_ctl.scala 689:10] - node _T_9629 = or(_T_9374, _T_9376) @[ifu_mem_ctl.scala 689:91] - node _T_9630 = or(_T_9629, _T_9378) @[ifu_mem_ctl.scala 689:91] - node _T_9631 = or(_T_9630, _T_9380) @[ifu_mem_ctl.scala 689:91] - node _T_9632 = or(_T_9631, _T_9382) @[ifu_mem_ctl.scala 689:91] - node _T_9633 = or(_T_9632, _T_9384) @[ifu_mem_ctl.scala 689:91] - node _T_9634 = or(_T_9633, _T_9386) @[ifu_mem_ctl.scala 689:91] - node _T_9635 = or(_T_9634, _T_9388) @[ifu_mem_ctl.scala 689:91] - node _T_9636 = or(_T_9635, _T_9390) @[ifu_mem_ctl.scala 689:91] - node _T_9637 = or(_T_9636, _T_9392) @[ifu_mem_ctl.scala 689:91] - node _T_9638 = or(_T_9637, _T_9394) @[ifu_mem_ctl.scala 689:91] - node _T_9639 = or(_T_9638, _T_9396) @[ifu_mem_ctl.scala 689:91] - node _T_9640 = or(_T_9639, _T_9398) @[ifu_mem_ctl.scala 689:91] - node _T_9641 = or(_T_9640, _T_9400) @[ifu_mem_ctl.scala 689:91] - node _T_9642 = or(_T_9641, _T_9402) @[ifu_mem_ctl.scala 689:91] - node _T_9643 = or(_T_9642, _T_9404) @[ifu_mem_ctl.scala 689:91] - node _T_9644 = or(_T_9643, _T_9406) @[ifu_mem_ctl.scala 689:91] - node _T_9645 = or(_T_9644, _T_9408) @[ifu_mem_ctl.scala 689:91] - node _T_9646 = or(_T_9645, _T_9410) @[ifu_mem_ctl.scala 689:91] - node _T_9647 = or(_T_9646, _T_9412) @[ifu_mem_ctl.scala 689:91] - node _T_9648 = or(_T_9647, _T_9414) @[ifu_mem_ctl.scala 689:91] - node _T_9649 = or(_T_9648, _T_9416) @[ifu_mem_ctl.scala 689:91] - node _T_9650 = or(_T_9649, _T_9418) @[ifu_mem_ctl.scala 689:91] - node _T_9651 = or(_T_9650, _T_9420) @[ifu_mem_ctl.scala 689:91] - node _T_9652 = or(_T_9651, _T_9422) @[ifu_mem_ctl.scala 689:91] - node _T_9653 = or(_T_9652, _T_9424) @[ifu_mem_ctl.scala 689:91] - node _T_9654 = or(_T_9653, _T_9426) @[ifu_mem_ctl.scala 689:91] - node _T_9655 = or(_T_9654, _T_9428) @[ifu_mem_ctl.scala 689:91] - node _T_9656 = or(_T_9655, _T_9430) @[ifu_mem_ctl.scala 689:91] - node _T_9657 = or(_T_9656, _T_9432) @[ifu_mem_ctl.scala 689:91] - node _T_9658 = or(_T_9657, _T_9434) @[ifu_mem_ctl.scala 689:91] - node _T_9659 = or(_T_9658, _T_9436) @[ifu_mem_ctl.scala 689:91] - node _T_9660 = or(_T_9659, _T_9438) @[ifu_mem_ctl.scala 689:91] - node _T_9661 = or(_T_9660, _T_9440) @[ifu_mem_ctl.scala 689:91] - node _T_9662 = or(_T_9661, _T_9442) @[ifu_mem_ctl.scala 689:91] - node _T_9663 = or(_T_9662, _T_9444) @[ifu_mem_ctl.scala 689:91] - node _T_9664 = or(_T_9663, _T_9446) @[ifu_mem_ctl.scala 689:91] - node _T_9665 = or(_T_9664, _T_9448) @[ifu_mem_ctl.scala 689:91] - node _T_9666 = or(_T_9665, _T_9450) @[ifu_mem_ctl.scala 689:91] - node _T_9667 = or(_T_9666, _T_9452) @[ifu_mem_ctl.scala 689:91] - node _T_9668 = or(_T_9667, _T_9454) @[ifu_mem_ctl.scala 689:91] - node _T_9669 = or(_T_9668, _T_9456) @[ifu_mem_ctl.scala 689:91] - node _T_9670 = or(_T_9669, _T_9458) @[ifu_mem_ctl.scala 689:91] - node _T_9671 = or(_T_9670, _T_9460) @[ifu_mem_ctl.scala 689:91] - node _T_9672 = or(_T_9671, _T_9462) @[ifu_mem_ctl.scala 689:91] - node _T_9673 = or(_T_9672, _T_9464) @[ifu_mem_ctl.scala 689:91] - node _T_9674 = or(_T_9673, _T_9466) @[ifu_mem_ctl.scala 689:91] - node _T_9675 = or(_T_9674, _T_9468) @[ifu_mem_ctl.scala 689:91] - node _T_9676 = or(_T_9675, _T_9470) @[ifu_mem_ctl.scala 689:91] - node _T_9677 = or(_T_9676, _T_9472) @[ifu_mem_ctl.scala 689:91] - node _T_9678 = or(_T_9677, _T_9474) @[ifu_mem_ctl.scala 689:91] - node _T_9679 = or(_T_9678, _T_9476) @[ifu_mem_ctl.scala 689:91] - node _T_9680 = or(_T_9679, _T_9478) @[ifu_mem_ctl.scala 689:91] - node _T_9681 = or(_T_9680, _T_9480) @[ifu_mem_ctl.scala 689:91] - node _T_9682 = or(_T_9681, _T_9482) @[ifu_mem_ctl.scala 689:91] - node _T_9683 = or(_T_9682, _T_9484) @[ifu_mem_ctl.scala 689:91] - node _T_9684 = or(_T_9683, _T_9486) @[ifu_mem_ctl.scala 689:91] - node _T_9685 = or(_T_9684, _T_9488) @[ifu_mem_ctl.scala 689:91] - node _T_9686 = or(_T_9685, _T_9490) @[ifu_mem_ctl.scala 689:91] - node _T_9687 = or(_T_9686, _T_9492) @[ifu_mem_ctl.scala 689:91] - node _T_9688 = or(_T_9687, _T_9494) @[ifu_mem_ctl.scala 689:91] - node _T_9689 = or(_T_9688, _T_9496) @[ifu_mem_ctl.scala 689:91] - node _T_9690 = or(_T_9689, _T_9498) @[ifu_mem_ctl.scala 689:91] - node _T_9691 = or(_T_9690, _T_9500) @[ifu_mem_ctl.scala 689:91] - node _T_9692 = or(_T_9691, _T_9502) @[ifu_mem_ctl.scala 689:91] - node _T_9693 = or(_T_9692, _T_9504) @[ifu_mem_ctl.scala 689:91] - node _T_9694 = or(_T_9693, _T_9506) @[ifu_mem_ctl.scala 689:91] - node _T_9695 = or(_T_9694, _T_9508) @[ifu_mem_ctl.scala 689:91] - node _T_9696 = or(_T_9695, _T_9510) @[ifu_mem_ctl.scala 689:91] - node _T_9697 = or(_T_9696, _T_9512) @[ifu_mem_ctl.scala 689:91] - node _T_9698 = or(_T_9697, _T_9514) @[ifu_mem_ctl.scala 689:91] - node _T_9699 = or(_T_9698, _T_9516) @[ifu_mem_ctl.scala 689:91] - node _T_9700 = or(_T_9699, _T_9518) @[ifu_mem_ctl.scala 689:91] - node _T_9701 = or(_T_9700, _T_9520) @[ifu_mem_ctl.scala 689:91] - node _T_9702 = or(_T_9701, _T_9522) @[ifu_mem_ctl.scala 689:91] - node _T_9703 = or(_T_9702, _T_9524) @[ifu_mem_ctl.scala 689:91] - node _T_9704 = or(_T_9703, _T_9526) @[ifu_mem_ctl.scala 689:91] - node _T_9705 = or(_T_9704, _T_9528) @[ifu_mem_ctl.scala 689:91] - node _T_9706 = or(_T_9705, _T_9530) @[ifu_mem_ctl.scala 689:91] - node _T_9707 = or(_T_9706, _T_9532) @[ifu_mem_ctl.scala 689:91] - node _T_9708 = or(_T_9707, _T_9534) @[ifu_mem_ctl.scala 689:91] - node _T_9709 = or(_T_9708, _T_9536) @[ifu_mem_ctl.scala 689:91] - node _T_9710 = or(_T_9709, _T_9538) @[ifu_mem_ctl.scala 689:91] - node _T_9711 = or(_T_9710, _T_9540) @[ifu_mem_ctl.scala 689:91] - node _T_9712 = or(_T_9711, _T_9542) @[ifu_mem_ctl.scala 689:91] - node _T_9713 = or(_T_9712, _T_9544) @[ifu_mem_ctl.scala 689:91] - node _T_9714 = or(_T_9713, _T_9546) @[ifu_mem_ctl.scala 689:91] - node _T_9715 = or(_T_9714, _T_9548) @[ifu_mem_ctl.scala 689:91] - node _T_9716 = or(_T_9715, _T_9550) @[ifu_mem_ctl.scala 689:91] - node _T_9717 = or(_T_9716, _T_9552) @[ifu_mem_ctl.scala 689:91] - node _T_9718 = or(_T_9717, _T_9554) @[ifu_mem_ctl.scala 689:91] - node _T_9719 = or(_T_9718, _T_9556) @[ifu_mem_ctl.scala 689:91] - node _T_9720 = or(_T_9719, _T_9558) @[ifu_mem_ctl.scala 689:91] - node _T_9721 = or(_T_9720, _T_9560) @[ifu_mem_ctl.scala 689:91] - node _T_9722 = or(_T_9721, _T_9562) @[ifu_mem_ctl.scala 689:91] - node _T_9723 = or(_T_9722, _T_9564) @[ifu_mem_ctl.scala 689:91] - node _T_9724 = or(_T_9723, _T_9566) @[ifu_mem_ctl.scala 689:91] - node _T_9725 = or(_T_9724, _T_9568) @[ifu_mem_ctl.scala 689:91] - node _T_9726 = or(_T_9725, _T_9570) @[ifu_mem_ctl.scala 689:91] - node _T_9727 = or(_T_9726, _T_9572) @[ifu_mem_ctl.scala 689:91] - node _T_9728 = or(_T_9727, _T_9574) @[ifu_mem_ctl.scala 689:91] - node _T_9729 = or(_T_9728, _T_9576) @[ifu_mem_ctl.scala 689:91] - node _T_9730 = or(_T_9729, _T_9578) @[ifu_mem_ctl.scala 689:91] - node _T_9731 = or(_T_9730, _T_9580) @[ifu_mem_ctl.scala 689:91] - node _T_9732 = or(_T_9731, _T_9582) @[ifu_mem_ctl.scala 689:91] - node _T_9733 = or(_T_9732, _T_9584) @[ifu_mem_ctl.scala 689:91] - node _T_9734 = or(_T_9733, _T_9586) @[ifu_mem_ctl.scala 689:91] - node _T_9735 = or(_T_9734, _T_9588) @[ifu_mem_ctl.scala 689:91] - node _T_9736 = or(_T_9735, _T_9590) @[ifu_mem_ctl.scala 689:91] - node _T_9737 = or(_T_9736, _T_9592) @[ifu_mem_ctl.scala 689:91] - node _T_9738 = or(_T_9737, _T_9594) @[ifu_mem_ctl.scala 689:91] - node _T_9739 = or(_T_9738, _T_9596) @[ifu_mem_ctl.scala 689:91] - node _T_9740 = or(_T_9739, _T_9598) @[ifu_mem_ctl.scala 689:91] - node _T_9741 = or(_T_9740, _T_9600) @[ifu_mem_ctl.scala 689:91] - node _T_9742 = or(_T_9741, _T_9602) @[ifu_mem_ctl.scala 689:91] - node _T_9743 = or(_T_9742, _T_9604) @[ifu_mem_ctl.scala 689:91] - node _T_9744 = or(_T_9743, _T_9606) @[ifu_mem_ctl.scala 689:91] - node _T_9745 = or(_T_9744, _T_9608) @[ifu_mem_ctl.scala 689:91] - node _T_9746 = or(_T_9745, _T_9610) @[ifu_mem_ctl.scala 689:91] - node _T_9747 = or(_T_9746, _T_9612) @[ifu_mem_ctl.scala 689:91] - node _T_9748 = or(_T_9747, _T_9614) @[ifu_mem_ctl.scala 689:91] - node _T_9749 = or(_T_9748, _T_9616) @[ifu_mem_ctl.scala 689:91] - node _T_9750 = or(_T_9749, _T_9618) @[ifu_mem_ctl.scala 689:91] - node _T_9751 = or(_T_9750, _T_9620) @[ifu_mem_ctl.scala 689:91] - node _T_9752 = or(_T_9751, _T_9622) @[ifu_mem_ctl.scala 689:91] - node _T_9753 = or(_T_9752, _T_9624) @[ifu_mem_ctl.scala 689:91] - node _T_9754 = or(_T_9753, _T_9626) @[ifu_mem_ctl.scala 689:91] - node _T_9755 = or(_T_9754, _T_9628) @[ifu_mem_ctl.scala 689:91] + ic_tag_valid_out[1][127] <= _T_8989 @[ifu_mem_ctl.scala 693:41] + node _T_8990 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 697:33] + node _T_8991 = mux(_T_8990, ic_tag_valid_out[0][0], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_8992 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 697:33] + node _T_8993 = mux(_T_8992, ic_tag_valid_out[0][1], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_8994 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 697:33] + node _T_8995 = mux(_T_8994, ic_tag_valid_out[0][2], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_8996 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 697:33] + node _T_8997 = mux(_T_8996, ic_tag_valid_out[0][3], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_8998 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 697:33] + node _T_8999 = mux(_T_8998, ic_tag_valid_out[0][4], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9000 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 697:33] + node _T_9001 = mux(_T_9000, ic_tag_valid_out[0][5], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9002 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 697:33] + node _T_9003 = mux(_T_9002, ic_tag_valid_out[0][6], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9004 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 697:33] + node _T_9005 = mux(_T_9004, ic_tag_valid_out[0][7], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9006 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 697:33] + node _T_9007 = mux(_T_9006, ic_tag_valid_out[0][8], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9008 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 697:33] + node _T_9009 = mux(_T_9008, ic_tag_valid_out[0][9], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9010 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 697:33] + node _T_9011 = mux(_T_9010, ic_tag_valid_out[0][10], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9012 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 697:33] + node _T_9013 = mux(_T_9012, ic_tag_valid_out[0][11], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9014 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 697:33] + node _T_9015 = mux(_T_9014, ic_tag_valid_out[0][12], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9016 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 697:33] + node _T_9017 = mux(_T_9016, ic_tag_valid_out[0][13], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9018 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 697:33] + node _T_9019 = mux(_T_9018, ic_tag_valid_out[0][14], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9020 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 697:33] + node _T_9021 = mux(_T_9020, ic_tag_valid_out[0][15], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9022 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 697:33] + node _T_9023 = mux(_T_9022, ic_tag_valid_out[0][16], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9024 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 697:33] + node _T_9025 = mux(_T_9024, ic_tag_valid_out[0][17], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9026 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 697:33] + node _T_9027 = mux(_T_9026, ic_tag_valid_out[0][18], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9028 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 697:33] + node _T_9029 = mux(_T_9028, ic_tag_valid_out[0][19], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9030 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 697:33] + node _T_9031 = mux(_T_9030, ic_tag_valid_out[0][20], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9032 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 697:33] + node _T_9033 = mux(_T_9032, ic_tag_valid_out[0][21], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9034 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 697:33] + node _T_9035 = mux(_T_9034, ic_tag_valid_out[0][22], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9036 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 697:33] + node _T_9037 = mux(_T_9036, ic_tag_valid_out[0][23], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9038 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 697:33] + node _T_9039 = mux(_T_9038, ic_tag_valid_out[0][24], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9040 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 697:33] + node _T_9041 = mux(_T_9040, ic_tag_valid_out[0][25], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9042 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 697:33] + node _T_9043 = mux(_T_9042, ic_tag_valid_out[0][26], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9044 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 697:33] + node _T_9045 = mux(_T_9044, ic_tag_valid_out[0][27], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9046 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 697:33] + node _T_9047 = mux(_T_9046, ic_tag_valid_out[0][28], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9048 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 697:33] + node _T_9049 = mux(_T_9048, ic_tag_valid_out[0][29], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9050 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 697:33] + node _T_9051 = mux(_T_9050, ic_tag_valid_out[0][30], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9052 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 697:33] + node _T_9053 = mux(_T_9052, ic_tag_valid_out[0][31], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9054 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 697:33] + node _T_9055 = mux(_T_9054, ic_tag_valid_out[0][32], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9056 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 697:33] + node _T_9057 = mux(_T_9056, ic_tag_valid_out[0][33], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9058 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 697:33] + node _T_9059 = mux(_T_9058, ic_tag_valid_out[0][34], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9060 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 697:33] + node _T_9061 = mux(_T_9060, ic_tag_valid_out[0][35], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9062 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 697:33] + node _T_9063 = mux(_T_9062, ic_tag_valid_out[0][36], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9064 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 697:33] + node _T_9065 = mux(_T_9064, ic_tag_valid_out[0][37], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9066 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 697:33] + node _T_9067 = mux(_T_9066, ic_tag_valid_out[0][38], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9068 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 697:33] + node _T_9069 = mux(_T_9068, ic_tag_valid_out[0][39], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9070 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 697:33] + node _T_9071 = mux(_T_9070, ic_tag_valid_out[0][40], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9072 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 697:33] + node _T_9073 = mux(_T_9072, ic_tag_valid_out[0][41], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9074 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 697:33] + node _T_9075 = mux(_T_9074, ic_tag_valid_out[0][42], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9076 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 697:33] + node _T_9077 = mux(_T_9076, ic_tag_valid_out[0][43], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9078 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 697:33] + node _T_9079 = mux(_T_9078, ic_tag_valid_out[0][44], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9080 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 697:33] + node _T_9081 = mux(_T_9080, ic_tag_valid_out[0][45], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9082 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 697:33] + node _T_9083 = mux(_T_9082, ic_tag_valid_out[0][46], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9084 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 697:33] + node _T_9085 = mux(_T_9084, ic_tag_valid_out[0][47], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9086 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 697:33] + node _T_9087 = mux(_T_9086, ic_tag_valid_out[0][48], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9088 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 697:33] + node _T_9089 = mux(_T_9088, ic_tag_valid_out[0][49], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9090 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 697:33] + node _T_9091 = mux(_T_9090, ic_tag_valid_out[0][50], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9092 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 697:33] + node _T_9093 = mux(_T_9092, ic_tag_valid_out[0][51], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9094 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 697:33] + node _T_9095 = mux(_T_9094, ic_tag_valid_out[0][52], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9096 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 697:33] + node _T_9097 = mux(_T_9096, ic_tag_valid_out[0][53], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9098 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 697:33] + node _T_9099 = mux(_T_9098, ic_tag_valid_out[0][54], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9100 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 697:33] + node _T_9101 = mux(_T_9100, ic_tag_valid_out[0][55], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9102 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 697:33] + node _T_9103 = mux(_T_9102, ic_tag_valid_out[0][56], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9104 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 697:33] + node _T_9105 = mux(_T_9104, ic_tag_valid_out[0][57], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9106 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 697:33] + node _T_9107 = mux(_T_9106, ic_tag_valid_out[0][58], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9108 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 697:33] + node _T_9109 = mux(_T_9108, ic_tag_valid_out[0][59], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9110 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 697:33] + node _T_9111 = mux(_T_9110, ic_tag_valid_out[0][60], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9112 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 697:33] + node _T_9113 = mux(_T_9112, ic_tag_valid_out[0][61], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9114 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 697:33] + node _T_9115 = mux(_T_9114, ic_tag_valid_out[0][62], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9116 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 697:33] + node _T_9117 = mux(_T_9116, ic_tag_valid_out[0][63], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9118 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 697:33] + node _T_9119 = mux(_T_9118, ic_tag_valid_out[0][64], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9120 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 697:33] + node _T_9121 = mux(_T_9120, ic_tag_valid_out[0][65], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9122 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 697:33] + node _T_9123 = mux(_T_9122, ic_tag_valid_out[0][66], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9124 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 697:33] + node _T_9125 = mux(_T_9124, ic_tag_valid_out[0][67], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9126 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 697:33] + node _T_9127 = mux(_T_9126, ic_tag_valid_out[0][68], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9128 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 697:33] + node _T_9129 = mux(_T_9128, ic_tag_valid_out[0][69], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9130 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 697:33] + node _T_9131 = mux(_T_9130, ic_tag_valid_out[0][70], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9132 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 697:33] + node _T_9133 = mux(_T_9132, ic_tag_valid_out[0][71], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9134 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 697:33] + node _T_9135 = mux(_T_9134, ic_tag_valid_out[0][72], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9136 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 697:33] + node _T_9137 = mux(_T_9136, ic_tag_valid_out[0][73], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9138 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 697:33] + node _T_9139 = mux(_T_9138, ic_tag_valid_out[0][74], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9140 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 697:33] + node _T_9141 = mux(_T_9140, ic_tag_valid_out[0][75], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9142 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 697:33] + node _T_9143 = mux(_T_9142, ic_tag_valid_out[0][76], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9144 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 697:33] + node _T_9145 = mux(_T_9144, ic_tag_valid_out[0][77], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9146 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 697:33] + node _T_9147 = mux(_T_9146, ic_tag_valid_out[0][78], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9148 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 697:33] + node _T_9149 = mux(_T_9148, ic_tag_valid_out[0][79], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9150 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 697:33] + node _T_9151 = mux(_T_9150, ic_tag_valid_out[0][80], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9152 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 697:33] + node _T_9153 = mux(_T_9152, ic_tag_valid_out[0][81], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9154 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 697:33] + node _T_9155 = mux(_T_9154, ic_tag_valid_out[0][82], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9156 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 697:33] + node _T_9157 = mux(_T_9156, ic_tag_valid_out[0][83], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9158 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 697:33] + node _T_9159 = mux(_T_9158, ic_tag_valid_out[0][84], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9160 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 697:33] + node _T_9161 = mux(_T_9160, ic_tag_valid_out[0][85], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9162 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 697:33] + node _T_9163 = mux(_T_9162, ic_tag_valid_out[0][86], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9164 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 697:33] + node _T_9165 = mux(_T_9164, ic_tag_valid_out[0][87], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9166 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 697:33] + node _T_9167 = mux(_T_9166, ic_tag_valid_out[0][88], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9168 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 697:33] + node _T_9169 = mux(_T_9168, ic_tag_valid_out[0][89], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 697:33] + node _T_9171 = mux(_T_9170, ic_tag_valid_out[0][90], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9172 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 697:33] + node _T_9173 = mux(_T_9172, ic_tag_valid_out[0][91], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9174 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 697:33] + node _T_9175 = mux(_T_9174, ic_tag_valid_out[0][92], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9176 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 697:33] + node _T_9177 = mux(_T_9176, ic_tag_valid_out[0][93], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9178 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 697:33] + node _T_9179 = mux(_T_9178, ic_tag_valid_out[0][94], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 697:33] + node _T_9181 = mux(_T_9180, ic_tag_valid_out[0][95], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9182 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 697:33] + node _T_9183 = mux(_T_9182, ic_tag_valid_out[0][96], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9184 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 697:33] + node _T_9185 = mux(_T_9184, ic_tag_valid_out[0][97], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9186 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 697:33] + node _T_9187 = mux(_T_9186, ic_tag_valid_out[0][98], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9188 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 697:33] + node _T_9189 = mux(_T_9188, ic_tag_valid_out[0][99], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9190 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 697:33] + node _T_9191 = mux(_T_9190, ic_tag_valid_out[0][100], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9192 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 697:33] + node _T_9193 = mux(_T_9192, ic_tag_valid_out[0][101], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9194 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 697:33] + node _T_9195 = mux(_T_9194, ic_tag_valid_out[0][102], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9196 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 697:33] + node _T_9197 = mux(_T_9196, ic_tag_valid_out[0][103], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9198 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 697:33] + node _T_9199 = mux(_T_9198, ic_tag_valid_out[0][104], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 697:33] + node _T_9201 = mux(_T_9200, ic_tag_valid_out[0][105], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9202 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 697:33] + node _T_9203 = mux(_T_9202, ic_tag_valid_out[0][106], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9204 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 697:33] + node _T_9205 = mux(_T_9204, ic_tag_valid_out[0][107], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9206 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 697:33] + node _T_9207 = mux(_T_9206, ic_tag_valid_out[0][108], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9208 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 697:33] + node _T_9209 = mux(_T_9208, ic_tag_valid_out[0][109], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 697:33] + node _T_9211 = mux(_T_9210, ic_tag_valid_out[0][110], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9212 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 697:33] + node _T_9213 = mux(_T_9212, ic_tag_valid_out[0][111], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9214 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 697:33] + node _T_9215 = mux(_T_9214, ic_tag_valid_out[0][112], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9216 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 697:33] + node _T_9217 = mux(_T_9216, ic_tag_valid_out[0][113], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9218 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 697:33] + node _T_9219 = mux(_T_9218, ic_tag_valid_out[0][114], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9220 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 697:33] + node _T_9221 = mux(_T_9220, ic_tag_valid_out[0][115], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9222 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 697:33] + node _T_9223 = mux(_T_9222, ic_tag_valid_out[0][116], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9224 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 697:33] + node _T_9225 = mux(_T_9224, ic_tag_valid_out[0][117], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9226 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 697:33] + node _T_9227 = mux(_T_9226, ic_tag_valid_out[0][118], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9228 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 697:33] + node _T_9229 = mux(_T_9228, ic_tag_valid_out[0][119], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9230 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 697:33] + node _T_9231 = mux(_T_9230, ic_tag_valid_out[0][120], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9232 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 697:33] + node _T_9233 = mux(_T_9232, ic_tag_valid_out[0][121], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9234 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 697:33] + node _T_9235 = mux(_T_9234, ic_tag_valid_out[0][122], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9236 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 697:33] + node _T_9237 = mux(_T_9236, ic_tag_valid_out[0][123], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9238 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 697:33] + node _T_9239 = mux(_T_9238, ic_tag_valid_out[0][124], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9240 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 697:33] + node _T_9241 = mux(_T_9240, ic_tag_valid_out[0][125], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9242 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 697:33] + node _T_9243 = mux(_T_9242, ic_tag_valid_out[0][126], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9244 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 697:33] + node _T_9245 = mux(_T_9244, ic_tag_valid_out[0][127], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9246 = or(_T_8991, _T_8993) @[ifu_mem_ctl.scala 697:91] + node _T_9247 = or(_T_9246, _T_8995) @[ifu_mem_ctl.scala 697:91] + node _T_9248 = or(_T_9247, _T_8997) @[ifu_mem_ctl.scala 697:91] + node _T_9249 = or(_T_9248, _T_8999) @[ifu_mem_ctl.scala 697:91] + node _T_9250 = or(_T_9249, _T_9001) @[ifu_mem_ctl.scala 697:91] + node _T_9251 = or(_T_9250, _T_9003) @[ifu_mem_ctl.scala 697:91] + node _T_9252 = or(_T_9251, _T_9005) @[ifu_mem_ctl.scala 697:91] + node _T_9253 = or(_T_9252, _T_9007) @[ifu_mem_ctl.scala 697:91] + node _T_9254 = or(_T_9253, _T_9009) @[ifu_mem_ctl.scala 697:91] + node _T_9255 = or(_T_9254, _T_9011) @[ifu_mem_ctl.scala 697:91] + node _T_9256 = or(_T_9255, _T_9013) @[ifu_mem_ctl.scala 697:91] + node _T_9257 = or(_T_9256, _T_9015) @[ifu_mem_ctl.scala 697:91] + node _T_9258 = or(_T_9257, _T_9017) @[ifu_mem_ctl.scala 697:91] + node _T_9259 = or(_T_9258, _T_9019) @[ifu_mem_ctl.scala 697:91] + node _T_9260 = or(_T_9259, _T_9021) @[ifu_mem_ctl.scala 697:91] + node _T_9261 = or(_T_9260, _T_9023) @[ifu_mem_ctl.scala 697:91] + node _T_9262 = or(_T_9261, _T_9025) @[ifu_mem_ctl.scala 697:91] + node _T_9263 = or(_T_9262, _T_9027) @[ifu_mem_ctl.scala 697:91] + node _T_9264 = or(_T_9263, _T_9029) @[ifu_mem_ctl.scala 697:91] + node _T_9265 = or(_T_9264, _T_9031) @[ifu_mem_ctl.scala 697:91] + node _T_9266 = or(_T_9265, _T_9033) @[ifu_mem_ctl.scala 697:91] + node _T_9267 = or(_T_9266, _T_9035) @[ifu_mem_ctl.scala 697:91] + node _T_9268 = or(_T_9267, _T_9037) @[ifu_mem_ctl.scala 697:91] + node _T_9269 = or(_T_9268, _T_9039) @[ifu_mem_ctl.scala 697:91] + node _T_9270 = or(_T_9269, _T_9041) @[ifu_mem_ctl.scala 697:91] + node _T_9271 = or(_T_9270, _T_9043) @[ifu_mem_ctl.scala 697:91] + node _T_9272 = or(_T_9271, _T_9045) @[ifu_mem_ctl.scala 697:91] + node _T_9273 = or(_T_9272, _T_9047) @[ifu_mem_ctl.scala 697:91] + node _T_9274 = or(_T_9273, _T_9049) @[ifu_mem_ctl.scala 697:91] + node _T_9275 = or(_T_9274, _T_9051) @[ifu_mem_ctl.scala 697:91] + node _T_9276 = or(_T_9275, _T_9053) @[ifu_mem_ctl.scala 697:91] + node _T_9277 = or(_T_9276, _T_9055) @[ifu_mem_ctl.scala 697:91] + node _T_9278 = or(_T_9277, _T_9057) @[ifu_mem_ctl.scala 697:91] + node _T_9279 = or(_T_9278, _T_9059) @[ifu_mem_ctl.scala 697:91] + node _T_9280 = or(_T_9279, _T_9061) @[ifu_mem_ctl.scala 697:91] + node _T_9281 = or(_T_9280, _T_9063) @[ifu_mem_ctl.scala 697:91] + node _T_9282 = or(_T_9281, _T_9065) @[ifu_mem_ctl.scala 697:91] + node _T_9283 = or(_T_9282, _T_9067) @[ifu_mem_ctl.scala 697:91] + node _T_9284 = or(_T_9283, _T_9069) @[ifu_mem_ctl.scala 697:91] + node _T_9285 = or(_T_9284, _T_9071) @[ifu_mem_ctl.scala 697:91] + node _T_9286 = or(_T_9285, _T_9073) @[ifu_mem_ctl.scala 697:91] + node _T_9287 = or(_T_9286, _T_9075) @[ifu_mem_ctl.scala 697:91] + node _T_9288 = or(_T_9287, _T_9077) @[ifu_mem_ctl.scala 697:91] + node _T_9289 = or(_T_9288, _T_9079) @[ifu_mem_ctl.scala 697:91] + node _T_9290 = or(_T_9289, _T_9081) @[ifu_mem_ctl.scala 697:91] + node _T_9291 = or(_T_9290, _T_9083) @[ifu_mem_ctl.scala 697:91] + node _T_9292 = or(_T_9291, _T_9085) @[ifu_mem_ctl.scala 697:91] + node _T_9293 = or(_T_9292, _T_9087) @[ifu_mem_ctl.scala 697:91] + node _T_9294 = or(_T_9293, _T_9089) @[ifu_mem_ctl.scala 697:91] + node _T_9295 = or(_T_9294, _T_9091) @[ifu_mem_ctl.scala 697:91] + node _T_9296 = or(_T_9295, _T_9093) @[ifu_mem_ctl.scala 697:91] + node _T_9297 = or(_T_9296, _T_9095) @[ifu_mem_ctl.scala 697:91] + node _T_9298 = or(_T_9297, _T_9097) @[ifu_mem_ctl.scala 697:91] + node _T_9299 = or(_T_9298, _T_9099) @[ifu_mem_ctl.scala 697:91] + node _T_9300 = or(_T_9299, _T_9101) @[ifu_mem_ctl.scala 697:91] + node _T_9301 = or(_T_9300, _T_9103) @[ifu_mem_ctl.scala 697:91] + node _T_9302 = or(_T_9301, _T_9105) @[ifu_mem_ctl.scala 697:91] + node _T_9303 = or(_T_9302, _T_9107) @[ifu_mem_ctl.scala 697:91] + node _T_9304 = or(_T_9303, _T_9109) @[ifu_mem_ctl.scala 697:91] + node _T_9305 = or(_T_9304, _T_9111) @[ifu_mem_ctl.scala 697:91] + node _T_9306 = or(_T_9305, _T_9113) @[ifu_mem_ctl.scala 697:91] + node _T_9307 = or(_T_9306, _T_9115) @[ifu_mem_ctl.scala 697:91] + node _T_9308 = or(_T_9307, _T_9117) @[ifu_mem_ctl.scala 697:91] + node _T_9309 = or(_T_9308, _T_9119) @[ifu_mem_ctl.scala 697:91] + node _T_9310 = or(_T_9309, _T_9121) @[ifu_mem_ctl.scala 697:91] + node _T_9311 = or(_T_9310, _T_9123) @[ifu_mem_ctl.scala 697:91] + node _T_9312 = or(_T_9311, _T_9125) @[ifu_mem_ctl.scala 697:91] + node _T_9313 = or(_T_9312, _T_9127) @[ifu_mem_ctl.scala 697:91] + node _T_9314 = or(_T_9313, _T_9129) @[ifu_mem_ctl.scala 697:91] + node _T_9315 = or(_T_9314, _T_9131) @[ifu_mem_ctl.scala 697:91] + node _T_9316 = or(_T_9315, _T_9133) @[ifu_mem_ctl.scala 697:91] + node _T_9317 = or(_T_9316, _T_9135) @[ifu_mem_ctl.scala 697:91] + node _T_9318 = or(_T_9317, _T_9137) @[ifu_mem_ctl.scala 697:91] + node _T_9319 = or(_T_9318, _T_9139) @[ifu_mem_ctl.scala 697:91] + node _T_9320 = or(_T_9319, _T_9141) @[ifu_mem_ctl.scala 697:91] + node _T_9321 = or(_T_9320, _T_9143) @[ifu_mem_ctl.scala 697:91] + node _T_9322 = or(_T_9321, _T_9145) @[ifu_mem_ctl.scala 697:91] + node _T_9323 = or(_T_9322, _T_9147) @[ifu_mem_ctl.scala 697:91] + node _T_9324 = or(_T_9323, _T_9149) @[ifu_mem_ctl.scala 697:91] + node _T_9325 = or(_T_9324, _T_9151) @[ifu_mem_ctl.scala 697:91] + node _T_9326 = or(_T_9325, _T_9153) @[ifu_mem_ctl.scala 697:91] + node _T_9327 = or(_T_9326, _T_9155) @[ifu_mem_ctl.scala 697:91] + node _T_9328 = or(_T_9327, _T_9157) @[ifu_mem_ctl.scala 697:91] + node _T_9329 = or(_T_9328, _T_9159) @[ifu_mem_ctl.scala 697:91] + node _T_9330 = or(_T_9329, _T_9161) @[ifu_mem_ctl.scala 697:91] + node _T_9331 = or(_T_9330, _T_9163) @[ifu_mem_ctl.scala 697:91] + node _T_9332 = or(_T_9331, _T_9165) @[ifu_mem_ctl.scala 697:91] + node _T_9333 = or(_T_9332, _T_9167) @[ifu_mem_ctl.scala 697:91] + node _T_9334 = or(_T_9333, _T_9169) @[ifu_mem_ctl.scala 697:91] + node _T_9335 = or(_T_9334, _T_9171) @[ifu_mem_ctl.scala 697:91] + node _T_9336 = or(_T_9335, _T_9173) @[ifu_mem_ctl.scala 697:91] + node _T_9337 = or(_T_9336, _T_9175) @[ifu_mem_ctl.scala 697:91] + node _T_9338 = or(_T_9337, _T_9177) @[ifu_mem_ctl.scala 697:91] + node _T_9339 = or(_T_9338, _T_9179) @[ifu_mem_ctl.scala 697:91] + node _T_9340 = or(_T_9339, _T_9181) @[ifu_mem_ctl.scala 697:91] + node _T_9341 = or(_T_9340, _T_9183) @[ifu_mem_ctl.scala 697:91] + node _T_9342 = or(_T_9341, _T_9185) @[ifu_mem_ctl.scala 697:91] + node _T_9343 = or(_T_9342, _T_9187) @[ifu_mem_ctl.scala 697:91] + node _T_9344 = or(_T_9343, _T_9189) @[ifu_mem_ctl.scala 697:91] + node _T_9345 = or(_T_9344, _T_9191) @[ifu_mem_ctl.scala 697:91] + node _T_9346 = or(_T_9345, _T_9193) @[ifu_mem_ctl.scala 697:91] + node _T_9347 = or(_T_9346, _T_9195) @[ifu_mem_ctl.scala 697:91] + node _T_9348 = or(_T_9347, _T_9197) @[ifu_mem_ctl.scala 697:91] + node _T_9349 = or(_T_9348, _T_9199) @[ifu_mem_ctl.scala 697:91] + node _T_9350 = or(_T_9349, _T_9201) @[ifu_mem_ctl.scala 697:91] + node _T_9351 = or(_T_9350, _T_9203) @[ifu_mem_ctl.scala 697:91] + node _T_9352 = or(_T_9351, _T_9205) @[ifu_mem_ctl.scala 697:91] + node _T_9353 = or(_T_9352, _T_9207) @[ifu_mem_ctl.scala 697:91] + node _T_9354 = or(_T_9353, _T_9209) @[ifu_mem_ctl.scala 697:91] + node _T_9355 = or(_T_9354, _T_9211) @[ifu_mem_ctl.scala 697:91] + node _T_9356 = or(_T_9355, _T_9213) @[ifu_mem_ctl.scala 697:91] + node _T_9357 = or(_T_9356, _T_9215) @[ifu_mem_ctl.scala 697:91] + node _T_9358 = or(_T_9357, _T_9217) @[ifu_mem_ctl.scala 697:91] + node _T_9359 = or(_T_9358, _T_9219) @[ifu_mem_ctl.scala 697:91] + node _T_9360 = or(_T_9359, _T_9221) @[ifu_mem_ctl.scala 697:91] + node _T_9361 = or(_T_9360, _T_9223) @[ifu_mem_ctl.scala 697:91] + node _T_9362 = or(_T_9361, _T_9225) @[ifu_mem_ctl.scala 697:91] + node _T_9363 = or(_T_9362, _T_9227) @[ifu_mem_ctl.scala 697:91] + node _T_9364 = or(_T_9363, _T_9229) @[ifu_mem_ctl.scala 697:91] + node _T_9365 = or(_T_9364, _T_9231) @[ifu_mem_ctl.scala 697:91] + node _T_9366 = or(_T_9365, _T_9233) @[ifu_mem_ctl.scala 697:91] + node _T_9367 = or(_T_9366, _T_9235) @[ifu_mem_ctl.scala 697:91] + node _T_9368 = or(_T_9367, _T_9237) @[ifu_mem_ctl.scala 697:91] + node _T_9369 = or(_T_9368, _T_9239) @[ifu_mem_ctl.scala 697:91] + node _T_9370 = or(_T_9369, _T_9241) @[ifu_mem_ctl.scala 697:91] + node _T_9371 = or(_T_9370, _T_9243) @[ifu_mem_ctl.scala 697:91] + node _T_9372 = or(_T_9371, _T_9245) @[ifu_mem_ctl.scala 697:91] + node _T_9373 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 697:33] + node _T_9374 = mux(_T_9373, ic_tag_valid_out[1][0], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9375 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 697:33] + node _T_9376 = mux(_T_9375, ic_tag_valid_out[1][1], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9377 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 697:33] + node _T_9378 = mux(_T_9377, ic_tag_valid_out[1][2], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9379 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 697:33] + node _T_9380 = mux(_T_9379, ic_tag_valid_out[1][3], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9381 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 697:33] + node _T_9382 = mux(_T_9381, ic_tag_valid_out[1][4], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9383 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 697:33] + node _T_9384 = mux(_T_9383, ic_tag_valid_out[1][5], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9385 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 697:33] + node _T_9386 = mux(_T_9385, ic_tag_valid_out[1][6], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9387 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 697:33] + node _T_9388 = mux(_T_9387, ic_tag_valid_out[1][7], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9389 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 697:33] + node _T_9390 = mux(_T_9389, ic_tag_valid_out[1][8], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9391 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 697:33] + node _T_9392 = mux(_T_9391, ic_tag_valid_out[1][9], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9393 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 697:33] + node _T_9394 = mux(_T_9393, ic_tag_valid_out[1][10], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9395 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 697:33] + node _T_9396 = mux(_T_9395, ic_tag_valid_out[1][11], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9397 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 697:33] + node _T_9398 = mux(_T_9397, ic_tag_valid_out[1][12], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9399 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 697:33] + node _T_9400 = mux(_T_9399, ic_tag_valid_out[1][13], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9401 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 697:33] + node _T_9402 = mux(_T_9401, ic_tag_valid_out[1][14], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9403 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 697:33] + node _T_9404 = mux(_T_9403, ic_tag_valid_out[1][15], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9405 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 697:33] + node _T_9406 = mux(_T_9405, ic_tag_valid_out[1][16], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9407 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 697:33] + node _T_9408 = mux(_T_9407, ic_tag_valid_out[1][17], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9409 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 697:33] + node _T_9410 = mux(_T_9409, ic_tag_valid_out[1][18], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9411 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 697:33] + node _T_9412 = mux(_T_9411, ic_tag_valid_out[1][19], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9413 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 697:33] + node _T_9414 = mux(_T_9413, ic_tag_valid_out[1][20], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9415 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 697:33] + node _T_9416 = mux(_T_9415, ic_tag_valid_out[1][21], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9417 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 697:33] + node _T_9418 = mux(_T_9417, ic_tag_valid_out[1][22], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9419 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 697:33] + node _T_9420 = mux(_T_9419, ic_tag_valid_out[1][23], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9421 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 697:33] + node _T_9422 = mux(_T_9421, ic_tag_valid_out[1][24], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9423 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 697:33] + node _T_9424 = mux(_T_9423, ic_tag_valid_out[1][25], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9425 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 697:33] + node _T_9426 = mux(_T_9425, ic_tag_valid_out[1][26], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9427 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 697:33] + node _T_9428 = mux(_T_9427, ic_tag_valid_out[1][27], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9429 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 697:33] + node _T_9430 = mux(_T_9429, ic_tag_valid_out[1][28], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9431 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 697:33] + node _T_9432 = mux(_T_9431, ic_tag_valid_out[1][29], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9433 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 697:33] + node _T_9434 = mux(_T_9433, ic_tag_valid_out[1][30], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9435 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 697:33] + node _T_9436 = mux(_T_9435, ic_tag_valid_out[1][31], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9437 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 697:33] + node _T_9438 = mux(_T_9437, ic_tag_valid_out[1][32], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9439 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 697:33] + node _T_9440 = mux(_T_9439, ic_tag_valid_out[1][33], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9441 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 697:33] + node _T_9442 = mux(_T_9441, ic_tag_valid_out[1][34], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9443 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 697:33] + node _T_9444 = mux(_T_9443, ic_tag_valid_out[1][35], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9445 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 697:33] + node _T_9446 = mux(_T_9445, ic_tag_valid_out[1][36], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9447 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 697:33] + node _T_9448 = mux(_T_9447, ic_tag_valid_out[1][37], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9449 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 697:33] + node _T_9450 = mux(_T_9449, ic_tag_valid_out[1][38], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9451 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 697:33] + node _T_9452 = mux(_T_9451, ic_tag_valid_out[1][39], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9453 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 697:33] + node _T_9454 = mux(_T_9453, ic_tag_valid_out[1][40], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9455 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 697:33] + node _T_9456 = mux(_T_9455, ic_tag_valid_out[1][41], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9457 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 697:33] + node _T_9458 = mux(_T_9457, ic_tag_valid_out[1][42], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9459 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 697:33] + node _T_9460 = mux(_T_9459, ic_tag_valid_out[1][43], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9461 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 697:33] + node _T_9462 = mux(_T_9461, ic_tag_valid_out[1][44], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9463 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 697:33] + node _T_9464 = mux(_T_9463, ic_tag_valid_out[1][45], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9465 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 697:33] + node _T_9466 = mux(_T_9465, ic_tag_valid_out[1][46], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9467 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 697:33] + node _T_9468 = mux(_T_9467, ic_tag_valid_out[1][47], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9469 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 697:33] + node _T_9470 = mux(_T_9469, ic_tag_valid_out[1][48], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9471 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 697:33] + node _T_9472 = mux(_T_9471, ic_tag_valid_out[1][49], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9473 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 697:33] + node _T_9474 = mux(_T_9473, ic_tag_valid_out[1][50], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9475 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 697:33] + node _T_9476 = mux(_T_9475, ic_tag_valid_out[1][51], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9477 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 697:33] + node _T_9478 = mux(_T_9477, ic_tag_valid_out[1][52], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9479 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 697:33] + node _T_9480 = mux(_T_9479, ic_tag_valid_out[1][53], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9481 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 697:33] + node _T_9482 = mux(_T_9481, ic_tag_valid_out[1][54], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9483 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 697:33] + node _T_9484 = mux(_T_9483, ic_tag_valid_out[1][55], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9485 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 697:33] + node _T_9486 = mux(_T_9485, ic_tag_valid_out[1][56], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9487 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 697:33] + node _T_9488 = mux(_T_9487, ic_tag_valid_out[1][57], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9489 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 697:33] + node _T_9490 = mux(_T_9489, ic_tag_valid_out[1][58], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9491 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 697:33] + node _T_9492 = mux(_T_9491, ic_tag_valid_out[1][59], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9493 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 697:33] + node _T_9494 = mux(_T_9493, ic_tag_valid_out[1][60], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9495 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 697:33] + node _T_9496 = mux(_T_9495, ic_tag_valid_out[1][61], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9497 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 697:33] + node _T_9498 = mux(_T_9497, ic_tag_valid_out[1][62], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9499 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 697:33] + node _T_9500 = mux(_T_9499, ic_tag_valid_out[1][63], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9501 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 697:33] + node _T_9502 = mux(_T_9501, ic_tag_valid_out[1][64], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9503 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 697:33] + node _T_9504 = mux(_T_9503, ic_tag_valid_out[1][65], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9505 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 697:33] + node _T_9506 = mux(_T_9505, ic_tag_valid_out[1][66], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9507 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 697:33] + node _T_9508 = mux(_T_9507, ic_tag_valid_out[1][67], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9509 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 697:33] + node _T_9510 = mux(_T_9509, ic_tag_valid_out[1][68], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9511 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 697:33] + node _T_9512 = mux(_T_9511, ic_tag_valid_out[1][69], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9513 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 697:33] + node _T_9514 = mux(_T_9513, ic_tag_valid_out[1][70], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 697:33] + node _T_9516 = mux(_T_9515, ic_tag_valid_out[1][71], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9517 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 697:33] + node _T_9518 = mux(_T_9517, ic_tag_valid_out[1][72], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9519 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 697:33] + node _T_9520 = mux(_T_9519, ic_tag_valid_out[1][73], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9521 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 697:33] + node _T_9522 = mux(_T_9521, ic_tag_valid_out[1][74], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9523 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 697:33] + node _T_9524 = mux(_T_9523, ic_tag_valid_out[1][75], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 697:33] + node _T_9526 = mux(_T_9525, ic_tag_valid_out[1][76], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9527 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 697:33] + node _T_9528 = mux(_T_9527, ic_tag_valid_out[1][77], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9529 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 697:33] + node _T_9530 = mux(_T_9529, ic_tag_valid_out[1][78], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9531 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 697:33] + node _T_9532 = mux(_T_9531, ic_tag_valid_out[1][79], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9533 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 697:33] + node _T_9534 = mux(_T_9533, ic_tag_valid_out[1][80], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9535 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 697:33] + node _T_9536 = mux(_T_9535, ic_tag_valid_out[1][81], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9537 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 697:33] + node _T_9538 = mux(_T_9537, ic_tag_valid_out[1][82], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9539 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 697:33] + node _T_9540 = mux(_T_9539, ic_tag_valid_out[1][83], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9541 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 697:33] + node _T_9542 = mux(_T_9541, ic_tag_valid_out[1][84], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9543 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 697:33] + node _T_9544 = mux(_T_9543, ic_tag_valid_out[1][85], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 697:33] + node _T_9546 = mux(_T_9545, ic_tag_valid_out[1][86], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9547 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 697:33] + node _T_9548 = mux(_T_9547, ic_tag_valid_out[1][87], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9549 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 697:33] + node _T_9550 = mux(_T_9549, ic_tag_valid_out[1][88], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9551 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 697:33] + node _T_9552 = mux(_T_9551, ic_tag_valid_out[1][89], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9553 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 697:33] + node _T_9554 = mux(_T_9553, ic_tag_valid_out[1][90], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9555 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 697:33] + node _T_9556 = mux(_T_9555, ic_tag_valid_out[1][91], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9557 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 697:33] + node _T_9558 = mux(_T_9557, ic_tag_valid_out[1][92], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9559 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 697:33] + node _T_9560 = mux(_T_9559, ic_tag_valid_out[1][93], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9561 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 697:33] + node _T_9562 = mux(_T_9561, ic_tag_valid_out[1][94], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9563 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 697:33] + node _T_9564 = mux(_T_9563, ic_tag_valid_out[1][95], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9565 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 697:33] + node _T_9566 = mux(_T_9565, ic_tag_valid_out[1][96], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9567 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 697:33] + node _T_9568 = mux(_T_9567, ic_tag_valid_out[1][97], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9569 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 697:33] + node _T_9570 = mux(_T_9569, ic_tag_valid_out[1][98], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9571 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 697:33] + node _T_9572 = mux(_T_9571, ic_tag_valid_out[1][99], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9573 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 697:33] + node _T_9574 = mux(_T_9573, ic_tag_valid_out[1][100], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9575 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 697:33] + node _T_9576 = mux(_T_9575, ic_tag_valid_out[1][101], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9577 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 697:33] + node _T_9578 = mux(_T_9577, ic_tag_valid_out[1][102], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9579 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 697:33] + node _T_9580 = mux(_T_9579, ic_tag_valid_out[1][103], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9581 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 697:33] + node _T_9582 = mux(_T_9581, ic_tag_valid_out[1][104], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9583 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 697:33] + node _T_9584 = mux(_T_9583, ic_tag_valid_out[1][105], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9585 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 697:33] + node _T_9586 = mux(_T_9585, ic_tag_valid_out[1][106], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9587 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 697:33] + node _T_9588 = mux(_T_9587, ic_tag_valid_out[1][107], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9589 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 697:33] + node _T_9590 = mux(_T_9589, ic_tag_valid_out[1][108], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9591 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 697:33] + node _T_9592 = mux(_T_9591, ic_tag_valid_out[1][109], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9593 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 697:33] + node _T_9594 = mux(_T_9593, ic_tag_valid_out[1][110], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9595 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 697:33] + node _T_9596 = mux(_T_9595, ic_tag_valid_out[1][111], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9597 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 697:33] + node _T_9598 = mux(_T_9597, ic_tag_valid_out[1][112], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9599 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 697:33] + node _T_9600 = mux(_T_9599, ic_tag_valid_out[1][113], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9601 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 697:33] + node _T_9602 = mux(_T_9601, ic_tag_valid_out[1][114], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9603 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 697:33] + node _T_9604 = mux(_T_9603, ic_tag_valid_out[1][115], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9605 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 697:33] + node _T_9606 = mux(_T_9605, ic_tag_valid_out[1][116], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9607 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 697:33] + node _T_9608 = mux(_T_9607, ic_tag_valid_out[1][117], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9609 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 697:33] + node _T_9610 = mux(_T_9609, ic_tag_valid_out[1][118], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9611 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 697:33] + node _T_9612 = mux(_T_9611, ic_tag_valid_out[1][119], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9613 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 697:33] + node _T_9614 = mux(_T_9613, ic_tag_valid_out[1][120], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9615 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 697:33] + node _T_9616 = mux(_T_9615, ic_tag_valid_out[1][121], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9617 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 697:33] + node _T_9618 = mux(_T_9617, ic_tag_valid_out[1][122], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9619 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 697:33] + node _T_9620 = mux(_T_9619, ic_tag_valid_out[1][123], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9621 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 697:33] + node _T_9622 = mux(_T_9621, ic_tag_valid_out[1][124], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9623 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 697:33] + node _T_9624 = mux(_T_9623, ic_tag_valid_out[1][125], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9625 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 697:33] + node _T_9626 = mux(_T_9625, ic_tag_valid_out[1][126], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9627 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 697:33] + node _T_9628 = mux(_T_9627, ic_tag_valid_out[1][127], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] + node _T_9629 = or(_T_9374, _T_9376) @[ifu_mem_ctl.scala 697:91] + node _T_9630 = or(_T_9629, _T_9378) @[ifu_mem_ctl.scala 697:91] + node _T_9631 = or(_T_9630, _T_9380) @[ifu_mem_ctl.scala 697:91] + node _T_9632 = or(_T_9631, _T_9382) @[ifu_mem_ctl.scala 697:91] + node _T_9633 = or(_T_9632, _T_9384) @[ifu_mem_ctl.scala 697:91] + node _T_9634 = or(_T_9633, _T_9386) @[ifu_mem_ctl.scala 697:91] + node _T_9635 = or(_T_9634, _T_9388) @[ifu_mem_ctl.scala 697:91] + node _T_9636 = or(_T_9635, _T_9390) @[ifu_mem_ctl.scala 697:91] + node _T_9637 = or(_T_9636, _T_9392) @[ifu_mem_ctl.scala 697:91] + node _T_9638 = or(_T_9637, _T_9394) @[ifu_mem_ctl.scala 697:91] + node _T_9639 = or(_T_9638, _T_9396) @[ifu_mem_ctl.scala 697:91] + node _T_9640 = or(_T_9639, _T_9398) @[ifu_mem_ctl.scala 697:91] + node _T_9641 = or(_T_9640, _T_9400) @[ifu_mem_ctl.scala 697:91] + node _T_9642 = or(_T_9641, _T_9402) @[ifu_mem_ctl.scala 697:91] + node _T_9643 = or(_T_9642, _T_9404) @[ifu_mem_ctl.scala 697:91] + node _T_9644 = or(_T_9643, _T_9406) @[ifu_mem_ctl.scala 697:91] + node _T_9645 = or(_T_9644, _T_9408) @[ifu_mem_ctl.scala 697:91] + node _T_9646 = or(_T_9645, _T_9410) @[ifu_mem_ctl.scala 697:91] + node _T_9647 = or(_T_9646, _T_9412) @[ifu_mem_ctl.scala 697:91] + node _T_9648 = or(_T_9647, _T_9414) @[ifu_mem_ctl.scala 697:91] + node _T_9649 = or(_T_9648, _T_9416) @[ifu_mem_ctl.scala 697:91] + node _T_9650 = or(_T_9649, _T_9418) @[ifu_mem_ctl.scala 697:91] + node _T_9651 = or(_T_9650, _T_9420) @[ifu_mem_ctl.scala 697:91] + node _T_9652 = or(_T_9651, _T_9422) @[ifu_mem_ctl.scala 697:91] + node _T_9653 = or(_T_9652, _T_9424) @[ifu_mem_ctl.scala 697:91] + node _T_9654 = or(_T_9653, _T_9426) @[ifu_mem_ctl.scala 697:91] + node _T_9655 = or(_T_9654, _T_9428) @[ifu_mem_ctl.scala 697:91] + node _T_9656 = or(_T_9655, _T_9430) @[ifu_mem_ctl.scala 697:91] + node _T_9657 = or(_T_9656, _T_9432) @[ifu_mem_ctl.scala 697:91] + node _T_9658 = or(_T_9657, _T_9434) @[ifu_mem_ctl.scala 697:91] + node _T_9659 = or(_T_9658, _T_9436) @[ifu_mem_ctl.scala 697:91] + node _T_9660 = or(_T_9659, _T_9438) @[ifu_mem_ctl.scala 697:91] + node _T_9661 = or(_T_9660, _T_9440) @[ifu_mem_ctl.scala 697:91] + node _T_9662 = or(_T_9661, _T_9442) @[ifu_mem_ctl.scala 697:91] + node _T_9663 = or(_T_9662, _T_9444) @[ifu_mem_ctl.scala 697:91] + node _T_9664 = or(_T_9663, _T_9446) @[ifu_mem_ctl.scala 697:91] + node _T_9665 = or(_T_9664, _T_9448) @[ifu_mem_ctl.scala 697:91] + node _T_9666 = or(_T_9665, _T_9450) @[ifu_mem_ctl.scala 697:91] + node _T_9667 = or(_T_9666, _T_9452) @[ifu_mem_ctl.scala 697:91] + node _T_9668 = or(_T_9667, _T_9454) @[ifu_mem_ctl.scala 697:91] + node _T_9669 = or(_T_9668, _T_9456) @[ifu_mem_ctl.scala 697:91] + node _T_9670 = or(_T_9669, _T_9458) @[ifu_mem_ctl.scala 697:91] + node _T_9671 = or(_T_9670, _T_9460) @[ifu_mem_ctl.scala 697:91] + node _T_9672 = or(_T_9671, _T_9462) @[ifu_mem_ctl.scala 697:91] + node _T_9673 = or(_T_9672, _T_9464) @[ifu_mem_ctl.scala 697:91] + node _T_9674 = or(_T_9673, _T_9466) @[ifu_mem_ctl.scala 697:91] + node _T_9675 = or(_T_9674, _T_9468) @[ifu_mem_ctl.scala 697:91] + node _T_9676 = or(_T_9675, _T_9470) @[ifu_mem_ctl.scala 697:91] + node _T_9677 = or(_T_9676, _T_9472) @[ifu_mem_ctl.scala 697:91] + node _T_9678 = or(_T_9677, _T_9474) @[ifu_mem_ctl.scala 697:91] + node _T_9679 = or(_T_9678, _T_9476) @[ifu_mem_ctl.scala 697:91] + node _T_9680 = or(_T_9679, _T_9478) @[ifu_mem_ctl.scala 697:91] + node _T_9681 = or(_T_9680, _T_9480) @[ifu_mem_ctl.scala 697:91] + node _T_9682 = or(_T_9681, _T_9482) @[ifu_mem_ctl.scala 697:91] + node _T_9683 = or(_T_9682, _T_9484) @[ifu_mem_ctl.scala 697:91] + node _T_9684 = or(_T_9683, _T_9486) @[ifu_mem_ctl.scala 697:91] + node _T_9685 = or(_T_9684, _T_9488) @[ifu_mem_ctl.scala 697:91] + node _T_9686 = or(_T_9685, _T_9490) @[ifu_mem_ctl.scala 697:91] + node _T_9687 = or(_T_9686, _T_9492) @[ifu_mem_ctl.scala 697:91] + node _T_9688 = or(_T_9687, _T_9494) @[ifu_mem_ctl.scala 697:91] + node _T_9689 = or(_T_9688, _T_9496) @[ifu_mem_ctl.scala 697:91] + node _T_9690 = or(_T_9689, _T_9498) @[ifu_mem_ctl.scala 697:91] + node _T_9691 = or(_T_9690, _T_9500) @[ifu_mem_ctl.scala 697:91] + node _T_9692 = or(_T_9691, _T_9502) @[ifu_mem_ctl.scala 697:91] + node _T_9693 = or(_T_9692, _T_9504) @[ifu_mem_ctl.scala 697:91] + node _T_9694 = or(_T_9693, _T_9506) @[ifu_mem_ctl.scala 697:91] + node _T_9695 = or(_T_9694, _T_9508) @[ifu_mem_ctl.scala 697:91] + node _T_9696 = or(_T_9695, _T_9510) @[ifu_mem_ctl.scala 697:91] + node _T_9697 = or(_T_9696, _T_9512) @[ifu_mem_ctl.scala 697:91] + node _T_9698 = or(_T_9697, _T_9514) @[ifu_mem_ctl.scala 697:91] + node _T_9699 = or(_T_9698, _T_9516) @[ifu_mem_ctl.scala 697:91] + node _T_9700 = or(_T_9699, _T_9518) @[ifu_mem_ctl.scala 697:91] + node _T_9701 = or(_T_9700, _T_9520) @[ifu_mem_ctl.scala 697:91] + node _T_9702 = or(_T_9701, _T_9522) @[ifu_mem_ctl.scala 697:91] + node _T_9703 = or(_T_9702, _T_9524) @[ifu_mem_ctl.scala 697:91] + node _T_9704 = or(_T_9703, _T_9526) @[ifu_mem_ctl.scala 697:91] + node _T_9705 = or(_T_9704, _T_9528) @[ifu_mem_ctl.scala 697:91] + node _T_9706 = or(_T_9705, _T_9530) @[ifu_mem_ctl.scala 697:91] + node _T_9707 = or(_T_9706, _T_9532) @[ifu_mem_ctl.scala 697:91] + node _T_9708 = or(_T_9707, _T_9534) @[ifu_mem_ctl.scala 697:91] + node _T_9709 = or(_T_9708, _T_9536) @[ifu_mem_ctl.scala 697:91] + node _T_9710 = or(_T_9709, _T_9538) @[ifu_mem_ctl.scala 697:91] + node _T_9711 = or(_T_9710, _T_9540) @[ifu_mem_ctl.scala 697:91] + node _T_9712 = or(_T_9711, _T_9542) @[ifu_mem_ctl.scala 697:91] + node _T_9713 = or(_T_9712, _T_9544) @[ifu_mem_ctl.scala 697:91] + node _T_9714 = or(_T_9713, _T_9546) @[ifu_mem_ctl.scala 697:91] + node _T_9715 = or(_T_9714, _T_9548) @[ifu_mem_ctl.scala 697:91] + node _T_9716 = or(_T_9715, _T_9550) @[ifu_mem_ctl.scala 697:91] + node _T_9717 = or(_T_9716, _T_9552) @[ifu_mem_ctl.scala 697:91] + node _T_9718 = or(_T_9717, _T_9554) @[ifu_mem_ctl.scala 697:91] + node _T_9719 = or(_T_9718, _T_9556) @[ifu_mem_ctl.scala 697:91] + node _T_9720 = or(_T_9719, _T_9558) @[ifu_mem_ctl.scala 697:91] + node _T_9721 = or(_T_9720, _T_9560) @[ifu_mem_ctl.scala 697:91] + node _T_9722 = or(_T_9721, _T_9562) @[ifu_mem_ctl.scala 697:91] + node _T_9723 = or(_T_9722, _T_9564) @[ifu_mem_ctl.scala 697:91] + node _T_9724 = or(_T_9723, _T_9566) @[ifu_mem_ctl.scala 697:91] + node _T_9725 = or(_T_9724, _T_9568) @[ifu_mem_ctl.scala 697:91] + node _T_9726 = or(_T_9725, _T_9570) @[ifu_mem_ctl.scala 697:91] + node _T_9727 = or(_T_9726, _T_9572) @[ifu_mem_ctl.scala 697:91] + node _T_9728 = or(_T_9727, _T_9574) @[ifu_mem_ctl.scala 697:91] + node _T_9729 = or(_T_9728, _T_9576) @[ifu_mem_ctl.scala 697:91] + node _T_9730 = or(_T_9729, _T_9578) @[ifu_mem_ctl.scala 697:91] + node _T_9731 = or(_T_9730, _T_9580) @[ifu_mem_ctl.scala 697:91] + node _T_9732 = or(_T_9731, _T_9582) @[ifu_mem_ctl.scala 697:91] + node _T_9733 = or(_T_9732, _T_9584) @[ifu_mem_ctl.scala 697:91] + node _T_9734 = or(_T_9733, _T_9586) @[ifu_mem_ctl.scala 697:91] + node _T_9735 = or(_T_9734, _T_9588) @[ifu_mem_ctl.scala 697:91] + node _T_9736 = or(_T_9735, _T_9590) @[ifu_mem_ctl.scala 697:91] + node _T_9737 = or(_T_9736, _T_9592) @[ifu_mem_ctl.scala 697:91] + node _T_9738 = or(_T_9737, _T_9594) @[ifu_mem_ctl.scala 697:91] + node _T_9739 = or(_T_9738, _T_9596) @[ifu_mem_ctl.scala 697:91] + node _T_9740 = or(_T_9739, _T_9598) @[ifu_mem_ctl.scala 697:91] + node _T_9741 = or(_T_9740, _T_9600) @[ifu_mem_ctl.scala 697:91] + node _T_9742 = or(_T_9741, _T_9602) @[ifu_mem_ctl.scala 697:91] + node _T_9743 = or(_T_9742, _T_9604) @[ifu_mem_ctl.scala 697:91] + node _T_9744 = or(_T_9743, _T_9606) @[ifu_mem_ctl.scala 697:91] + node _T_9745 = or(_T_9744, _T_9608) @[ifu_mem_ctl.scala 697:91] + node _T_9746 = or(_T_9745, _T_9610) @[ifu_mem_ctl.scala 697:91] + node _T_9747 = or(_T_9746, _T_9612) @[ifu_mem_ctl.scala 697:91] + node _T_9748 = or(_T_9747, _T_9614) @[ifu_mem_ctl.scala 697:91] + node _T_9749 = or(_T_9748, _T_9616) @[ifu_mem_ctl.scala 697:91] + node _T_9750 = or(_T_9749, _T_9618) @[ifu_mem_ctl.scala 697:91] + node _T_9751 = or(_T_9750, _T_9620) @[ifu_mem_ctl.scala 697:91] + node _T_9752 = or(_T_9751, _T_9622) @[ifu_mem_ctl.scala 697:91] + node _T_9753 = or(_T_9752, _T_9624) @[ifu_mem_ctl.scala 697:91] + node _T_9754 = or(_T_9753, _T_9626) @[ifu_mem_ctl.scala 697:91] + node _T_9755 = or(_T_9754, _T_9628) @[ifu_mem_ctl.scala 697:91] node ic_tag_valid_unq = cat(_T_9755, _T_9372) @[Cat.scala 29:58] wire way_status_hit_new : UInt<1> way_status_hit_new <= UInt<1>("h00") - node _T_9756 = eq(way_status_mb_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 714:33] - node _T_9757 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 714:63] - node _T_9758 = and(_T_9756, _T_9757) @[ifu_mem_ctl.scala 714:51] - node _T_9759 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 714:79] - node _T_9760 = and(_T_9758, _T_9759) @[ifu_mem_ctl.scala 714:67] - node _T_9761 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 714:97] - node _T_9762 = eq(_T_9761, UInt<1>("h00")) @[ifu_mem_ctl.scala 714:86] - node _T_9763 = or(_T_9760, _T_9762) @[ifu_mem_ctl.scala 714:84] - replace_way_mb_any[0] <= _T_9763 @[ifu_mem_ctl.scala 714:29] - node _T_9764 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 715:62] - node _T_9765 = and(way_status_mb_ff, _T_9764) @[ifu_mem_ctl.scala 715:50] - node _T_9766 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 715:78] - node _T_9767 = and(_T_9765, _T_9766) @[ifu_mem_ctl.scala 715:66] - node _T_9768 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 715:96] - node _T_9769 = eq(_T_9768, UInt<1>("h00")) @[ifu_mem_ctl.scala 715:85] - node _T_9770 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 715:112] - node _T_9771 = and(_T_9769, _T_9770) @[ifu_mem_ctl.scala 715:100] - node _T_9772 = or(_T_9767, _T_9771) @[ifu_mem_ctl.scala 715:83] - replace_way_mb_any[1] <= _T_9772 @[ifu_mem_ctl.scala 715:29] - node _T_9773 = bits(io.ic.rd_hit, 0, 0) @[ifu_mem_ctl.scala 716:41] - way_status_hit_new <= _T_9773 @[ifu_mem_ctl.scala 716:26] - way_status_rep_new <= replace_way_mb_any[0] @[ifu_mem_ctl.scala 717:26] - node _T_9774 = and(bus_ifu_wr_en_ff_q, last_beat) @[ifu_mem_ctl.scala 719:47] - node _T_9775 = bits(_T_9774, 0, 0) @[ifu_mem_ctl.scala 719:60] - node _T_9776 = mux(_T_9775, way_status_rep_new, way_status_hit_new) @[ifu_mem_ctl.scala 719:26] - way_status_new <= _T_9776 @[ifu_mem_ctl.scala 719:20] - node _T_9777 = and(bus_ifu_wr_en_ff_q, last_beat) @[ifu_mem_ctl.scala 720:45] - node _T_9778 = or(_T_9777, ic_act_hit_f) @[ifu_mem_ctl.scala 720:58] - way_status_wr_en <= _T_9778 @[ifu_mem_ctl.scala 720:22] - node _T_9779 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[0]) @[ifu_mem_ctl.scala 721:74] - node bus_wren_0 = and(_T_9779, miss_pending) @[ifu_mem_ctl.scala 721:98] - node _T_9780 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[1]) @[ifu_mem_ctl.scala 721:74] - node bus_wren_1 = and(_T_9780, miss_pending) @[ifu_mem_ctl.scala 721:98] - node _T_9781 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[0]) @[ifu_mem_ctl.scala 723:84] - node _T_9782 = and(_T_9781, miss_pending) @[ifu_mem_ctl.scala 723:108] - node bus_wren_last_0 = and(_T_9782, bus_last_data_beat) @[ifu_mem_ctl.scala 723:123] - node _T_9783 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[1]) @[ifu_mem_ctl.scala 723:84] - node _T_9784 = and(_T_9783, miss_pending) @[ifu_mem_ctl.scala 723:108] - node bus_wren_last_1 = and(_T_9784, bus_last_data_beat) @[ifu_mem_ctl.scala 723:123] - node wren_reset_miss_0 = and(replace_way_mb_any[0], reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 724:84] - node wren_reset_miss_1 = and(replace_way_mb_any[1], reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 724:84] - node _T_9785 = or(bus_wren_last_0, wren_reset_miss_0) @[ifu_mem_ctl.scala 725:73] - node _T_9786 = or(bus_wren_last_1, wren_reset_miss_1) @[ifu_mem_ctl.scala 725:73] + node _T_9756 = eq(way_status_mb_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 721:33] + node _T_9757 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 721:63] + node _T_9758 = and(_T_9756, _T_9757) @[ifu_mem_ctl.scala 721:51] + node _T_9759 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 721:79] + node _T_9760 = and(_T_9758, _T_9759) @[ifu_mem_ctl.scala 721:67] + node _T_9761 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 721:97] + node _T_9762 = eq(_T_9761, UInt<1>("h00")) @[ifu_mem_ctl.scala 721:86] + node _T_9763 = or(_T_9760, _T_9762) @[ifu_mem_ctl.scala 721:84] + replace_way_mb_any[0] <= _T_9763 @[ifu_mem_ctl.scala 721:29] + node _T_9764 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 722:62] + node _T_9765 = and(way_status_mb_ff, _T_9764) @[ifu_mem_ctl.scala 722:50] + node _T_9766 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 722:78] + node _T_9767 = and(_T_9765, _T_9766) @[ifu_mem_ctl.scala 722:66] + node _T_9768 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 722:96] + node _T_9769 = eq(_T_9768, UInt<1>("h00")) @[ifu_mem_ctl.scala 722:85] + node _T_9770 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 722:112] + node _T_9771 = and(_T_9769, _T_9770) @[ifu_mem_ctl.scala 722:100] + node _T_9772 = or(_T_9767, _T_9771) @[ifu_mem_ctl.scala 722:83] + replace_way_mb_any[1] <= _T_9772 @[ifu_mem_ctl.scala 722:29] + node _T_9773 = bits(io.ic.rd_hit, 0, 0) @[ifu_mem_ctl.scala 723:41] + way_status_hit_new <= _T_9773 @[ifu_mem_ctl.scala 723:26] + way_status_rep_new <= replace_way_mb_any[0] @[ifu_mem_ctl.scala 724:26] + node _T_9774 = and(bus_ifu_wr_en_ff_q, last_beat) @[ifu_mem_ctl.scala 726:47] + node _T_9775 = bits(_T_9774, 0, 0) @[ifu_mem_ctl.scala 726:60] + node _T_9776 = mux(_T_9775, way_status_rep_new, way_status_hit_new) @[ifu_mem_ctl.scala 726:26] + way_status_new <= _T_9776 @[ifu_mem_ctl.scala 726:20] + node _T_9777 = and(bus_ifu_wr_en_ff_q, last_beat) @[ifu_mem_ctl.scala 727:45] + node _T_9778 = or(_T_9777, ic_act_hit_f) @[ifu_mem_ctl.scala 727:58] + way_status_wr_en <= _T_9778 @[ifu_mem_ctl.scala 727:22] + node _T_9779 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[0]) @[ifu_mem_ctl.scala 728:74] + node bus_wren_0 = and(_T_9779, miss_pending) @[ifu_mem_ctl.scala 728:98] + node _T_9780 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[1]) @[ifu_mem_ctl.scala 728:74] + node bus_wren_1 = and(_T_9780, miss_pending) @[ifu_mem_ctl.scala 728:98] + node _T_9781 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[0]) @[ifu_mem_ctl.scala 730:84] + node _T_9782 = and(_T_9781, miss_pending) @[ifu_mem_ctl.scala 730:108] + node bus_wren_last_0 = and(_T_9782, bus_last_data_beat) @[ifu_mem_ctl.scala 730:123] + node _T_9783 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[1]) @[ifu_mem_ctl.scala 730:84] + node _T_9784 = and(_T_9783, miss_pending) @[ifu_mem_ctl.scala 730:108] + node bus_wren_last_1 = and(_T_9784, bus_last_data_beat) @[ifu_mem_ctl.scala 730:123] + node wren_reset_miss_0 = and(replace_way_mb_any[0], reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 731:84] + node wren_reset_miss_1 = and(replace_way_mb_any[1], reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 731:84] + node _T_9785 = or(bus_wren_last_0, wren_reset_miss_0) @[ifu_mem_ctl.scala 732:73] + node _T_9786 = or(bus_wren_last_1, wren_reset_miss_1) @[ifu_mem_ctl.scala 732:73] node _T_9787 = cat(_T_9786, _T_9785) @[Cat.scala 29:58] - ifu_tag_wren <= _T_9787 @[ifu_mem_ctl.scala 725:18] + ifu_tag_wren <= _T_9787 @[ifu_mem_ctl.scala 732:18] node _T_9788 = cat(bus_wren_1, bus_wren_0) @[Cat.scala 29:58] - bus_ic_wr_en <= _T_9788 @[ifu_mem_ctl.scala 727:16] - node _T_9789 = eq(fetch_uncacheable_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 741:63] - node _T_9790 = and(_T_9789, ifc_fetch_req_f) @[ifu_mem_ctl.scala 741:85] + bus_ic_wr_en <= _T_9788 @[ifu_mem_ctl.scala 734:16] + node _T_9789 = eq(fetch_uncacheable_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 748:63] + node _T_9790 = and(_T_9789, ifc_fetch_req_f) @[ifu_mem_ctl.scala 748:85] node _T_9791 = bits(_T_9790, 0, 0) @[Bitwise.scala 72:15] node _T_9792 = mux(_T_9791, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_9793 = and(ic_tag_valid_unq, _T_9792) @[ifu_mem_ctl.scala 741:39] - io.ic.tag_valid <= _T_9793 @[ifu_mem_ctl.scala 741:19] + node _T_9793 = and(ic_tag_valid_unq, _T_9792) @[ifu_mem_ctl.scala 748:39] + io.ic.tag_valid <= _T_9793 @[ifu_mem_ctl.scala 748:19] wire ic_debug_way_ff : UInt<2> ic_debug_way_ff <= UInt<1>("h00") node _T_9794 = bits(ic_debug_rd_en_ff, 0, 0) @[Bitwise.scala 72:15] node _T_9795 = mux(_T_9794, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_9796 = and(ic_debug_way_ff, _T_9795) @[ifu_mem_ctl.scala 744:67] - node _T_9797 = and(ic_tag_valid_unq, _T_9796) @[ifu_mem_ctl.scala 744:48] - node _T_9798 = orr(_T_9797) @[ifu_mem_ctl.scala 744:115] - ic_debug_tag_val_rd_out <= _T_9798 @[ifu_mem_ctl.scala 744:27] - reg _T_9799 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 746:70] - _T_9799 <= ic_act_miss_f @[ifu_mem_ctl.scala 746:70] - io.dec_mem_ctrl.ifu_pmu_ic_miss <= _T_9799 @[ifu_mem_ctl.scala 746:35] - reg _T_9800 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 747:69] - _T_9800 <= ic_act_hit_f @[ifu_mem_ctl.scala 747:69] - io.dec_mem_ctrl.ifu_pmu_ic_hit <= _T_9800 @[ifu_mem_ctl.scala 747:34] - reg _T_9801 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 748:72] - _T_9801 <= ifc_bus_acc_fault_f @[ifu_mem_ctl.scala 748:72] - io.dec_mem_ctrl.ifu_pmu_bus_error <= _T_9801 @[ifu_mem_ctl.scala 748:37] - node _T_9802 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 749:93] - node _T_9803 = and(ifu_bus_arvalid_ff, _T_9802) @[ifu_mem_ctl.scala 749:91] - node _T_9804 = and(_T_9803, miss_pending) @[ifu_mem_ctl.scala 749:113] - reg _T_9805 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 749:71] - _T_9805 <= _T_9804 @[ifu_mem_ctl.scala 749:71] - io.dec_mem_ctrl.ifu_pmu_bus_busy <= _T_9805 @[ifu_mem_ctl.scala 749:36] - reg _T_9806 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 750:71] - _T_9806 <= bus_cmd_sent @[ifu_mem_ctl.scala 750:71] - io.dec_mem_ctrl.ifu_pmu_bus_trxn <= _T_9806 @[ifu_mem_ctl.scala 750:36] - io.ic.debug_addr <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[ifu_mem_ctl.scala 753:20] - node _T_9807 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[ifu_mem_ctl.scala 754:79] - io.ic.debug_tag_array <= _T_9807 @[ifu_mem_ctl.scala 754:25] - io.ic.debug_rd_en <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[ifu_mem_ctl.scala 755:21] - io.ic.debug_wr_en <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[ifu_mem_ctl.scala 756:21] - node _T_9808 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 757:77] - node _T_9809 = eq(_T_9808, UInt<2>("h03")) @[ifu_mem_ctl.scala 757:84] - node _T_9810 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 757:143] - node _T_9811 = eq(_T_9810, UInt<2>("h02")) @[ifu_mem_ctl.scala 757:150] - node _T_9812 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 758:56] - node _T_9813 = eq(_T_9812, UInt<1>("h01")) @[ifu_mem_ctl.scala 758:63] - node _T_9814 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 758:122] - node _T_9815 = eq(_T_9814, UInt<1>("h00")) @[ifu_mem_ctl.scala 758:129] + node _T_9796 = and(ic_debug_way_ff, _T_9795) @[ifu_mem_ctl.scala 751:67] + node _T_9797 = and(ic_tag_valid_unq, _T_9796) @[ifu_mem_ctl.scala 751:48] + node _T_9798 = orr(_T_9797) @[ifu_mem_ctl.scala 751:115] + ic_debug_tag_val_rd_out <= _T_9798 @[ifu_mem_ctl.scala 751:27] + reg _T_9799 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 753:70] + _T_9799 <= ic_act_miss_f @[ifu_mem_ctl.scala 753:70] + io.dec_mem_ctrl.ifu_pmu_ic_miss <= _T_9799 @[ifu_mem_ctl.scala 753:35] + reg _T_9800 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 754:69] + _T_9800 <= ic_act_hit_f @[ifu_mem_ctl.scala 754:69] + io.dec_mem_ctrl.ifu_pmu_ic_hit <= _T_9800 @[ifu_mem_ctl.scala 754:34] + reg _T_9801 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 755:72] + _T_9801 <= ifc_bus_acc_fault_f @[ifu_mem_ctl.scala 755:72] + io.dec_mem_ctrl.ifu_pmu_bus_error <= _T_9801 @[ifu_mem_ctl.scala 755:37] + node _T_9802 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 756:93] + node _T_9803 = and(ifu_bus_arvalid_ff, _T_9802) @[ifu_mem_ctl.scala 756:91] + node _T_9804 = and(_T_9803, miss_pending) @[ifu_mem_ctl.scala 756:113] + reg _T_9805 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 756:71] + _T_9805 <= _T_9804 @[ifu_mem_ctl.scala 756:71] + io.dec_mem_ctrl.ifu_pmu_bus_busy <= _T_9805 @[ifu_mem_ctl.scala 756:36] + reg _T_9806 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 757:71] + _T_9806 <= bus_cmd_sent @[ifu_mem_ctl.scala 757:71] + io.dec_mem_ctrl.ifu_pmu_bus_trxn <= _T_9806 @[ifu_mem_ctl.scala 757:36] + io.ic.debug_addr <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[ifu_mem_ctl.scala 760:20] + node _T_9807 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[ifu_mem_ctl.scala 761:79] + io.ic.debug_tag_array <= _T_9807 @[ifu_mem_ctl.scala 761:25] + io.ic.debug_rd_en <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[ifu_mem_ctl.scala 762:21] + io.ic.debug_wr_en <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[ifu_mem_ctl.scala 763:21] + node _T_9808 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 764:77] + node _T_9809 = eq(_T_9808, UInt<2>("h03")) @[ifu_mem_ctl.scala 764:84] + node _T_9810 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 764:143] + node _T_9811 = eq(_T_9810, UInt<2>("h02")) @[ifu_mem_ctl.scala 764:150] + node _T_9812 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 765:56] + node _T_9813 = eq(_T_9812, UInt<1>("h01")) @[ifu_mem_ctl.scala 765:63] + node _T_9814 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 765:122] + node _T_9815 = eq(_T_9814, UInt<1>("h00")) @[ifu_mem_ctl.scala 765:129] node _T_9816 = cat(_T_9813, _T_9815) @[Cat.scala 29:58] node _T_9817 = cat(_T_9809, _T_9811) @[Cat.scala 29:58] node _T_9818 = cat(_T_9817, _T_9816) @[Cat.scala 29:58] - io.ic.debug_way <= _T_9818 @[ifu_mem_ctl.scala 757:19] - node _T_9819 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 759:65] + io.ic.debug_way <= _T_9818 @[ifu_mem_ctl.scala 764:19] + node _T_9819 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 766:65] node _T_9820 = bits(_T_9819, 0, 0) @[Bitwise.scala 72:15] node _T_9821 = mux(_T_9820, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_9822 = and(_T_9821, io.ic.debug_way) @[ifu_mem_ctl.scala 759:90] - ic_debug_tag_wr_en <= _T_9822 @[ifu_mem_ctl.scala 759:22] - node ic_debug_ict_array_sel_in = and(io.ic.debug_rd_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 760:53] - reg _T_9823 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 761:53] - _T_9823 <= io.ic.debug_way @[ifu_mem_ctl.scala 761:53] - ic_debug_way_ff <= _T_9823 @[ifu_mem_ctl.scala 761:19] - reg _T_9824 : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 762:63] - _T_9824 <= ic_debug_ict_array_sel_in @[ifu_mem_ctl.scala 762:63] - ic_debug_ict_array_sel_ff <= _T_9824 @[ifu_mem_ctl.scala 762:29] - reg _T_9825 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 763:54] - _T_9825 <= io.ic.debug_rd_en @[ifu_mem_ctl.scala 763:54] - ic_debug_rd_en_ff <= _T_9825 @[ifu_mem_ctl.scala 763:21] - reg _T_9826 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 764:79] - _T_9826 <= ic_debug_rd_en_ff @[ifu_mem_ctl.scala 764:79] - io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= _T_9826 @[ifu_mem_ctl.scala 764:46] + node _T_9822 = and(_T_9821, io.ic.debug_way) @[ifu_mem_ctl.scala 766:90] + ic_debug_tag_wr_en <= _T_9822 @[ifu_mem_ctl.scala 766:22] + node ic_debug_ict_array_sel_in = and(io.ic.debug_rd_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 767:53] + reg _T_9823 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 768:53] + _T_9823 <= io.ic.debug_way @[ifu_mem_ctl.scala 768:53] + ic_debug_way_ff <= _T_9823 @[ifu_mem_ctl.scala 768:19] + reg _T_9824 : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 769:63] + _T_9824 <= ic_debug_ict_array_sel_in @[ifu_mem_ctl.scala 769:63] + ic_debug_ict_array_sel_ff <= _T_9824 @[ifu_mem_ctl.scala 769:29] + reg _T_9825 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 770:54] + _T_9825 <= io.ic.debug_rd_en @[ifu_mem_ctl.scala 770:54] + ic_debug_rd_en_ff <= _T_9825 @[ifu_mem_ctl.scala 770:21] + reg _T_9826 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 771:79] + _T_9826 <= ic_debug_rd_en_ff @[ifu_mem_ctl.scala 771:79] + io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= _T_9826 @[ifu_mem_ctl.scala 771:46] node _T_9827 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_9828 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_9829 = cat(_T_9828, _T_9827) @[Cat.scala 29:58] @@ -15747,65 +15747,65 @@ circuit quasar_wrapper : node _T_9831 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] node _T_9832 = cat(_T_9831, _T_9830) @[Cat.scala 29:58] node _T_9833 = cat(_T_9832, _T_9829) @[Cat.scala 29:58] - node _T_9834 = orr(_T_9833) @[ifu_mem_ctl.scala 765:215] - node _T_9835 = eq(_T_9834, UInt<1>("h00")) @[ifu_mem_ctl.scala 765:29] + node _T_9834 = orr(_T_9833) @[ifu_mem_ctl.scala 773:215] + node _T_9835 = eq(_T_9834, UInt<1>("h00")) @[ifu_mem_ctl.scala 773:29] node _T_9836 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9837 = or(_T_9836, UInt<31>("h07fffffff")) @[ifu_mem_ctl.scala 766:65] - node _T_9838 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[ifu_mem_ctl.scala 766:129] - node _T_9839 = eq(_T_9837, _T_9838) @[ifu_mem_ctl.scala 766:96] - node _T_9840 = and(UInt<1>("h01"), _T_9839) @[ifu_mem_ctl.scala 766:30] - node _T_9841 = or(_T_9835, _T_9840) @[ifu_mem_ctl.scala 765:219] + node _T_9837 = or(_T_9836, UInt<31>("h07fffffff")) @[ifu_mem_ctl.scala 774:65] + node _T_9838 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[ifu_mem_ctl.scala 774:129] + node _T_9839 = eq(_T_9837, _T_9838) @[ifu_mem_ctl.scala 774:96] + node _T_9840 = and(UInt<1>("h01"), _T_9839) @[ifu_mem_ctl.scala 774:30] + node _T_9841 = or(_T_9835, _T_9840) @[ifu_mem_ctl.scala 773:219] node _T_9842 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9843 = or(_T_9842, UInt<30>("h03fffffff")) @[ifu_mem_ctl.scala 767:65] - node _T_9844 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[ifu_mem_ctl.scala 767:129] - node _T_9845 = eq(_T_9843, _T_9844) @[ifu_mem_ctl.scala 767:96] - node _T_9846 = and(UInt<1>("h01"), _T_9845) @[ifu_mem_ctl.scala 767:30] - node _T_9847 = or(_T_9841, _T_9846) @[ifu_mem_ctl.scala 766:162] + node _T_9843 = or(_T_9842, UInt<30>("h03fffffff")) @[ifu_mem_ctl.scala 775:65] + node _T_9844 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[ifu_mem_ctl.scala 775:129] + node _T_9845 = eq(_T_9843, _T_9844) @[ifu_mem_ctl.scala 775:96] + node _T_9846 = and(UInt<1>("h01"), _T_9845) @[ifu_mem_ctl.scala 775:30] + node _T_9847 = or(_T_9841, _T_9846) @[ifu_mem_ctl.scala 774:162] node _T_9848 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9849 = or(_T_9848, UInt<29>("h01fffffff")) @[ifu_mem_ctl.scala 768:65] - node _T_9850 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[ifu_mem_ctl.scala 768:129] - node _T_9851 = eq(_T_9849, _T_9850) @[ifu_mem_ctl.scala 768:96] - node _T_9852 = and(UInt<1>("h01"), _T_9851) @[ifu_mem_ctl.scala 768:30] - node _T_9853 = or(_T_9847, _T_9852) @[ifu_mem_ctl.scala 767:162] + node _T_9849 = or(_T_9848, UInt<29>("h01fffffff")) @[ifu_mem_ctl.scala 776:65] + node _T_9850 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[ifu_mem_ctl.scala 776:129] + node _T_9851 = eq(_T_9849, _T_9850) @[ifu_mem_ctl.scala 776:96] + node _T_9852 = and(UInt<1>("h01"), _T_9851) @[ifu_mem_ctl.scala 776:30] + node _T_9853 = or(_T_9847, _T_9852) @[ifu_mem_ctl.scala 775:162] node _T_9854 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9855 = or(_T_9854, UInt<28>("h0fffffff")) @[ifu_mem_ctl.scala 769:65] - node _T_9856 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[ifu_mem_ctl.scala 769:129] - node _T_9857 = eq(_T_9855, _T_9856) @[ifu_mem_ctl.scala 769:96] - node _T_9858 = and(UInt<1>("h01"), _T_9857) @[ifu_mem_ctl.scala 769:30] - node _T_9859 = or(_T_9853, _T_9858) @[ifu_mem_ctl.scala 768:162] + node _T_9855 = or(_T_9854, UInt<28>("h0fffffff")) @[ifu_mem_ctl.scala 777:65] + node _T_9856 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[ifu_mem_ctl.scala 777:129] + node _T_9857 = eq(_T_9855, _T_9856) @[ifu_mem_ctl.scala 777:96] + node _T_9858 = and(UInt<1>("h01"), _T_9857) @[ifu_mem_ctl.scala 777:30] + node _T_9859 = or(_T_9853, _T_9858) @[ifu_mem_ctl.scala 776:162] node _T_9860 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9861 = or(_T_9860, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 770:65] - node _T_9862 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 770:129] - node _T_9863 = eq(_T_9861, _T_9862) @[ifu_mem_ctl.scala 770:96] - node _T_9864 = and(UInt<1>("h00"), _T_9863) @[ifu_mem_ctl.scala 770:30] - node _T_9865 = or(_T_9859, _T_9864) @[ifu_mem_ctl.scala 769:162] + node _T_9861 = or(_T_9860, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 778:65] + node _T_9862 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 778:129] + node _T_9863 = eq(_T_9861, _T_9862) @[ifu_mem_ctl.scala 778:96] + node _T_9864 = and(UInt<1>("h00"), _T_9863) @[ifu_mem_ctl.scala 778:30] + node _T_9865 = or(_T_9859, _T_9864) @[ifu_mem_ctl.scala 777:162] node _T_9866 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9867 = or(_T_9866, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 771:65] - node _T_9868 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 771:129] - node _T_9869 = eq(_T_9867, _T_9868) @[ifu_mem_ctl.scala 771:96] - node _T_9870 = and(UInt<1>("h00"), _T_9869) @[ifu_mem_ctl.scala 771:30] - node _T_9871 = or(_T_9865, _T_9870) @[ifu_mem_ctl.scala 770:162] + node _T_9867 = or(_T_9866, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 779:65] + node _T_9868 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 779:129] + node _T_9869 = eq(_T_9867, _T_9868) @[ifu_mem_ctl.scala 779:96] + node _T_9870 = and(UInt<1>("h00"), _T_9869) @[ifu_mem_ctl.scala 779:30] + node _T_9871 = or(_T_9865, _T_9870) @[ifu_mem_ctl.scala 778:162] node _T_9872 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9873 = or(_T_9872, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 772:65] - node _T_9874 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 772:129] - node _T_9875 = eq(_T_9873, _T_9874) @[ifu_mem_ctl.scala 772:96] - node _T_9876 = and(UInt<1>("h00"), _T_9875) @[ifu_mem_ctl.scala 772:30] - node _T_9877 = or(_T_9871, _T_9876) @[ifu_mem_ctl.scala 771:162] + node _T_9873 = or(_T_9872, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 780:65] + node _T_9874 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 780:129] + node _T_9875 = eq(_T_9873, _T_9874) @[ifu_mem_ctl.scala 780:96] + node _T_9876 = and(UInt<1>("h00"), _T_9875) @[ifu_mem_ctl.scala 780:30] + node _T_9877 = or(_T_9871, _T_9876) @[ifu_mem_ctl.scala 779:162] node _T_9878 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9879 = or(_T_9878, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 773:65] - node _T_9880 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 773:129] - node _T_9881 = eq(_T_9879, _T_9880) @[ifu_mem_ctl.scala 773:96] - node _T_9882 = and(UInt<1>("h00"), _T_9881) @[ifu_mem_ctl.scala 773:30] - node ifc_region_acc_okay = or(_T_9877, _T_9882) @[ifu_mem_ctl.scala 772:162] - node _T_9883 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 774:40] - node _T_9884 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[ifu_mem_ctl.scala 774:65] - node _T_9885 = and(_T_9883, _T_9884) @[ifu_mem_ctl.scala 774:63] - node ifc_region_acc_fault_memory_bf = and(_T_9885, io.ifc_fetch_req_bf) @[ifu_mem_ctl.scala 774:86] - node _T_9886 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[ifu_mem_ctl.scala 775:63] - ifc_region_acc_fault_final_bf <= _T_9886 @[ifu_mem_ctl.scala 775:33] - reg _T_9887 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 776:66] - _T_9887 <= ifc_region_acc_fault_memory_bf @[ifu_mem_ctl.scala 776:66] - ifc_region_acc_fault_memory_f <= _T_9887 @[ifu_mem_ctl.scala 776:33] + node _T_9879 = or(_T_9878, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 781:65] + node _T_9880 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 781:129] + node _T_9881 = eq(_T_9879, _T_9880) @[ifu_mem_ctl.scala 781:96] + node _T_9882 = and(UInt<1>("h00"), _T_9881) @[ifu_mem_ctl.scala 781:30] + node ifc_region_acc_okay = or(_T_9877, _T_9882) @[ifu_mem_ctl.scala 780:162] + node _T_9883 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 782:40] + node _T_9884 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[ifu_mem_ctl.scala 782:65] + node _T_9885 = and(_T_9883, _T_9884) @[ifu_mem_ctl.scala 782:63] + node ifc_region_acc_fault_memory_bf = and(_T_9885, io.ifc_fetch_req_bf) @[ifu_mem_ctl.scala 782:86] + node _T_9886 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[ifu_mem_ctl.scala 783:63] + ifc_region_acc_fault_final_bf <= _T_9886 @[ifu_mem_ctl.scala 783:33] + reg _T_9887 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 784:66] + _T_9887 <= ifc_region_acc_fault_memory_bf @[ifu_mem_ctl.scala 784:66] + ifc_region_acc_fault_memory_f <= _T_9887 @[ifu_mem_ctl.scala 784:33] extmodule gated_latch_94 : output Q : Clock @@ -62636,30 +62636,30 @@ circuit quasar_wrapper : shift_2B <= UInt<1>("h00") wire f0_shift_2B : UInt<1> f0_shift_2B <= UInt<1>("h00") - node _T = or(error_stall, io.ifu_async_error_start) @[ifu_aln_ctl.scala 98:34] - node _T_1 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 98:64] - node _T_2 = and(_T, _T_1) @[ifu_aln_ctl.scala 98:62] - error_stall_in <= _T_2 @[ifu_aln_ctl.scala 98:18] - reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 100:51] - _T_3 <= error_stall_in @[ifu_aln_ctl.scala 100:51] - error_stall <= _T_3 @[ifu_aln_ctl.scala 100:15] - reg wrptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 101:48] - wrptr <= wrptr_in @[ifu_aln_ctl.scala 101:48] - reg rdptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 102:48] - rdptr <= rdptr_in @[ifu_aln_ctl.scala 102:48] - reg f2val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 104:48] - f2val <= f2val_in @[ifu_aln_ctl.scala 104:48] - reg f1val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 105:48] - f1val <= f1val_in @[ifu_aln_ctl.scala 105:48] - reg f0val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 106:48] - f0val <= f0val_in @[ifu_aln_ctl.scala 106:48] - reg q2off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 108:48] - q2off <= q2off_in @[ifu_aln_ctl.scala 108:48] - reg q1off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 109:48] - q1off <= q1off_in @[ifu_aln_ctl.scala 109:48] - reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 110:48] - q0off <= q0off_in @[ifu_aln_ctl.scala 110:48] - node _T_4 = bits(f2_wr_en, 0, 0) @[ifu_aln_ctl.scala 112:47] + node _T = or(error_stall, io.ifu_async_error_start) @[ifu_aln_ctl.scala 99:34] + node _T_1 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 99:64] + node _T_2 = and(_T, _T_1) @[ifu_aln_ctl.scala 99:62] + error_stall_in <= _T_2 @[ifu_aln_ctl.scala 99:18] + reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 102:51] + _T_3 <= error_stall_in @[ifu_aln_ctl.scala 102:51] + error_stall <= _T_3 @[ifu_aln_ctl.scala 102:15] + reg wrptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 104:48] + wrptr <= wrptr_in @[ifu_aln_ctl.scala 104:48] + reg rdptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 106:48] + rdptr <= rdptr_in @[ifu_aln_ctl.scala 106:48] + reg f2val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 108:48] + f2val <= f2val_in @[ifu_aln_ctl.scala 108:48] + reg f1val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 109:48] + f1val <= f1val_in @[ifu_aln_ctl.scala 109:48] + reg f0val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 110:48] + f0val <= f0val_in @[ifu_aln_ctl.scala 110:48] + reg q2off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 112:48] + q2off <= q2off_in @[ifu_aln_ctl.scala 112:48] + reg q1off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 113:48] + q1off <= q1off_in @[ifu_aln_ctl.scala 113:48] + reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 114:48] + q0off <= q0off_in @[ifu_aln_ctl.scala 114:48] + node _T_4 = bits(f2_wr_en, 0, 0) @[ifu_aln_ctl.scala 116:47] inst rvclkhdr of rvclkhdr_648 @[lib.scala 352:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -62668,7 +62668,7 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg f2pc : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] f2pc <= io.ifu_fetch_pc @[lib.scala 358:16] - node _T_5 = bits(f1_shift_wr_en, 0, 0) @[ifu_aln_ctl.scala 113:45] + node _T_5 = bits(f1_shift_wr_en, 0, 0) @[ifu_aln_ctl.scala 117:45] inst rvclkhdr_1 of rvclkhdr_649 @[lib.scala 352:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -62677,7 +62677,7 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg f1pc : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] f1pc <= f1pc_in @[lib.scala 358:16] - node _T_6 = bits(f0_shift_wr_en, 0, 0) @[ifu_aln_ctl.scala 114:45] + node _T_6 = bits(f0_shift_wr_en, 0, 0) @[ifu_aln_ctl.scala 118:45] inst rvclkhdr_2 of rvclkhdr_650 @[lib.scala 352:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -62686,7 +62686,7 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg f0pc : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] f0pc <= f0pc_in @[lib.scala 358:16] - node _T_7 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 116:36] + node _T_7 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 120:36] inst rvclkhdr_3 of rvclkhdr_651 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -62695,8 +62695,8 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_8 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_8 <= brdata_in @[lib.scala 358:16] - brdata2 <= _T_8 @[ifu_aln_ctl.scala 116:11] - node _T_9 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 117:36] + brdata2 <= _T_8 @[ifu_aln_ctl.scala 120:11] + node _T_9 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 121:36] inst rvclkhdr_4 of rvclkhdr_652 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -62705,8 +62705,8 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_10 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_10 <= brdata_in @[lib.scala 358:16] - brdata1 <= _T_10 @[ifu_aln_ctl.scala 117:11] - node _T_11 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 118:36] + brdata1 <= _T_10 @[ifu_aln_ctl.scala 121:11] + node _T_11 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 122:36] inst rvclkhdr_5 of rvclkhdr_653 @[lib.scala 352:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -62715,8 +62715,8 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_12 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_12 <= brdata_in @[lib.scala 358:16] - brdata0 <= _T_12 @[ifu_aln_ctl.scala 118:11] - node _T_13 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 120:37] + brdata0 <= _T_12 @[ifu_aln_ctl.scala 122:11] + node _T_13 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 124:37] inst rvclkhdr_6 of rvclkhdr_654 @[lib.scala 352:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -62725,8 +62725,8 @@ circuit quasar_wrapper : rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_14 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_14 <= misc_data_in @[lib.scala 358:16] - misc2 <= _T_14 @[ifu_aln_ctl.scala 120:9] - node _T_15 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 121:37] + misc2 <= _T_14 @[ifu_aln_ctl.scala 124:9] + node _T_15 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 125:37] inst rvclkhdr_7 of rvclkhdr_655 @[lib.scala 352:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -62735,8 +62735,8 @@ circuit quasar_wrapper : rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_16 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_16 <= misc_data_in @[lib.scala 358:16] - misc1 <= _T_16 @[ifu_aln_ctl.scala 121:9] - node _T_17 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 122:37] + misc1 <= _T_16 @[ifu_aln_ctl.scala 125:9] + node _T_17 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 126:37] inst rvclkhdr_8 of rvclkhdr_656 @[lib.scala 352:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -62745,8 +62745,8 @@ circuit quasar_wrapper : rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_18 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_18 <= misc_data_in @[lib.scala 358:16] - misc0 <= _T_18 @[ifu_aln_ctl.scala 122:9] - node _T_19 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 124:41] + misc0 <= _T_18 @[ifu_aln_ctl.scala 126:9] + node _T_19 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 128:41] inst rvclkhdr_9 of rvclkhdr_657 @[lib.scala 352:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -62755,8 +62755,8 @@ circuit quasar_wrapper : rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_20 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_20 <= io.ifu_fetch_data_f @[lib.scala 358:16] - q2 <= _T_20 @[ifu_aln_ctl.scala 124:6] - node _T_21 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 125:41] + q2 <= _T_20 @[ifu_aln_ctl.scala 128:6] + node _T_21 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 129:41] inst rvclkhdr_10 of rvclkhdr_658 @[lib.scala 352:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset @@ -62765,8 +62765,8 @@ circuit quasar_wrapper : rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_22 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_22 <= io.ifu_fetch_data_f @[lib.scala 358:16] - q1 <= _T_22 @[ifu_aln_ctl.scala 125:6] - node _T_23 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 126:41] + q1 <= _T_22 @[ifu_aln_ctl.scala 129:6] + node _T_23 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 130:41] inst rvclkhdr_11 of rvclkhdr_659 @[lib.scala 352:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset @@ -62775,66 +62775,66 @@ circuit quasar_wrapper : rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_24 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_24 <= io.ifu_fetch_data_f @[lib.scala 358:16] - q0 <= _T_24 @[ifu_aln_ctl.scala 126:6] - f2_wr_en <= fetch_to_f2 @[ifu_aln_ctl.scala 128:18] - node _T_25 = or(fetch_to_f1, shift_f2_f1) @[ifu_aln_ctl.scala 129:33] - node _T_26 = or(_T_25, f1_shift_2B) @[ifu_aln_ctl.scala 129:47] - f1_shift_wr_en <= _T_26 @[ifu_aln_ctl.scala 129:18] - node _T_27 = or(fetch_to_f0, shift_f2_f0) @[ifu_aln_ctl.scala 130:33] - node _T_28 = or(_T_27, shift_f1_f0) @[ifu_aln_ctl.scala 130:47] - node _T_29 = or(_T_28, shift_2B) @[ifu_aln_ctl.scala 130:61] - node _T_30 = or(_T_29, shift_4B) @[ifu_aln_ctl.scala 130:72] - f0_shift_wr_en <= _T_30 @[ifu_aln_ctl.scala 130:18] - node _T_31 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 132:24] - node _T_32 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 132:39] - node _T_33 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 132:54] + q0 <= _T_24 @[ifu_aln_ctl.scala 130:6] + f2_wr_en <= fetch_to_f2 @[ifu_aln_ctl.scala 133:18] + node _T_25 = or(fetch_to_f1, shift_f2_f1) @[ifu_aln_ctl.scala 134:33] + node _T_26 = or(_T_25, f1_shift_2B) @[ifu_aln_ctl.scala 134:47] + f1_shift_wr_en <= _T_26 @[ifu_aln_ctl.scala 134:18] + node _T_27 = or(fetch_to_f0, shift_f2_f0) @[ifu_aln_ctl.scala 135:33] + node _T_28 = or(_T_27, shift_f1_f0) @[ifu_aln_ctl.scala 135:47] + node _T_29 = or(_T_28, shift_2B) @[ifu_aln_ctl.scala 135:61] + node _T_30 = or(_T_29, shift_4B) @[ifu_aln_ctl.scala 135:72] + f0_shift_wr_en <= _T_30 @[ifu_aln_ctl.scala 135:18] + node _T_31 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 137:24] + node _T_32 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 137:39] + node _T_33 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 137:54] node _T_34 = cat(_T_31, _T_32) @[Cat.scala 29:58] node qren = cat(_T_34, _T_33) @[Cat.scala 29:58] - node _T_35 = eq(wrptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 133:21] - node _T_36 = and(_T_35, ifvalid) @[ifu_aln_ctl.scala 133:29] - node _T_37 = eq(wrptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 133:46] - node _T_38 = and(_T_37, ifvalid) @[ifu_aln_ctl.scala 133:54] - node _T_39 = eq(wrptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 133:71] - node _T_40 = and(_T_39, ifvalid) @[ifu_aln_ctl.scala 133:79] + node _T_35 = eq(wrptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 139:21] + node _T_36 = and(_T_35, ifvalid) @[ifu_aln_ctl.scala 139:29] + node _T_37 = eq(wrptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 139:46] + node _T_38 = and(_T_37, ifvalid) @[ifu_aln_ctl.scala 139:54] + node _T_39 = eq(wrptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 139:71] + node _T_40 = and(_T_39, ifvalid) @[ifu_aln_ctl.scala 139:79] node _T_41 = cat(_T_36, _T_38) @[Cat.scala 29:58] node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58] - qwen <= _T_42 @[ifu_aln_ctl.scala 133:8] - node _T_43 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 135:30] - node _T_44 = and(_T_43, io.ifu_fb_consume1) @[ifu_aln_ctl.scala 135:34] - node _T_45 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 135:57] - node _T_46 = and(_T_44, _T_45) @[ifu_aln_ctl.scala 135:55] - node _T_47 = bits(_T_46, 0, 0) @[ifu_aln_ctl.scala 135:78] - node _T_48 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 136:10] - node _T_49 = and(_T_48, io.ifu_fb_consume1) @[ifu_aln_ctl.scala 136:14] - node _T_50 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 136:37] - node _T_51 = and(_T_49, _T_50) @[ifu_aln_ctl.scala 136:35] - node _T_52 = bits(_T_51, 0, 0) @[ifu_aln_ctl.scala 136:58] - node _T_53 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 137:10] - node _T_54 = and(_T_53, io.ifu_fb_consume1) @[ifu_aln_ctl.scala 137:14] - node _T_55 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 137:37] - node _T_56 = and(_T_54, _T_55) @[ifu_aln_ctl.scala 137:35] - node _T_57 = bits(_T_56, 0, 0) @[ifu_aln_ctl.scala 137:58] - node _T_58 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 138:10] - node _T_59 = and(_T_58, io.ifu_fb_consume2) @[ifu_aln_ctl.scala 138:14] - node _T_60 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 138:37] - node _T_61 = and(_T_59, _T_60) @[ifu_aln_ctl.scala 138:35] - node _T_62 = bits(_T_61, 0, 0) @[ifu_aln_ctl.scala 138:58] - node _T_63 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 139:10] - node _T_64 = and(_T_63, io.ifu_fb_consume2) @[ifu_aln_ctl.scala 139:14] - node _T_65 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 139:37] - node _T_66 = and(_T_64, _T_65) @[ifu_aln_ctl.scala 139:35] - node _T_67 = bits(_T_66, 0, 0) @[ifu_aln_ctl.scala 139:58] - node _T_68 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 140:10] - node _T_69 = and(_T_68, io.ifu_fb_consume2) @[ifu_aln_ctl.scala 140:14] - node _T_70 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 140:37] - node _T_71 = and(_T_69, _T_70) @[ifu_aln_ctl.scala 140:35] - node _T_72 = bits(_T_71, 0, 0) @[ifu_aln_ctl.scala 140:58] - node _T_73 = eq(io.ifu_fb_consume1, UInt<1>("h00")) @[ifu_aln_ctl.scala 141:6] - node _T_74 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[ifu_aln_ctl.scala 141:28] - node _T_75 = and(_T_73, _T_74) @[ifu_aln_ctl.scala 141:26] - node _T_76 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 141:50] - node _T_77 = and(_T_75, _T_76) @[ifu_aln_ctl.scala 141:48] - node _T_78 = bits(_T_77, 0, 0) @[ifu_aln_ctl.scala 141:71] + qwen <= _T_42 @[ifu_aln_ctl.scala 139:8] + node _T_43 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 143:30] + node _T_44 = and(_T_43, io.ifu_fb_consume1) @[ifu_aln_ctl.scala 143:34] + node _T_45 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 143:57] + node _T_46 = and(_T_44, _T_45) @[ifu_aln_ctl.scala 143:55] + node _T_47 = bits(_T_46, 0, 0) @[ifu_aln_ctl.scala 143:78] + node _T_48 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 144:10] + node _T_49 = and(_T_48, io.ifu_fb_consume1) @[ifu_aln_ctl.scala 144:14] + node _T_50 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 144:37] + node _T_51 = and(_T_49, _T_50) @[ifu_aln_ctl.scala 144:35] + node _T_52 = bits(_T_51, 0, 0) @[ifu_aln_ctl.scala 144:58] + node _T_53 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 145:10] + node _T_54 = and(_T_53, io.ifu_fb_consume1) @[ifu_aln_ctl.scala 145:14] + node _T_55 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 145:37] + node _T_56 = and(_T_54, _T_55) @[ifu_aln_ctl.scala 145:35] + node _T_57 = bits(_T_56, 0, 0) @[ifu_aln_ctl.scala 145:58] + node _T_58 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 146:10] + node _T_59 = and(_T_58, io.ifu_fb_consume2) @[ifu_aln_ctl.scala 146:14] + node _T_60 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 146:37] + node _T_61 = and(_T_59, _T_60) @[ifu_aln_ctl.scala 146:35] + node _T_62 = bits(_T_61, 0, 0) @[ifu_aln_ctl.scala 146:58] + node _T_63 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 147:10] + node _T_64 = and(_T_63, io.ifu_fb_consume2) @[ifu_aln_ctl.scala 147:14] + node _T_65 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 147:37] + node _T_66 = and(_T_64, _T_65) @[ifu_aln_ctl.scala 147:35] + node _T_67 = bits(_T_66, 0, 0) @[ifu_aln_ctl.scala 147:58] + node _T_68 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 148:10] + node _T_69 = and(_T_68, io.ifu_fb_consume2) @[ifu_aln_ctl.scala 148:14] + node _T_70 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 148:37] + node _T_71 = and(_T_69, _T_70) @[ifu_aln_ctl.scala 148:35] + node _T_72 = bits(_T_71, 0, 0) @[ifu_aln_ctl.scala 148:58] + node _T_73 = eq(io.ifu_fb_consume1, UInt<1>("h00")) @[ifu_aln_ctl.scala 149:6] + node _T_74 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[ifu_aln_ctl.scala 149:28] + node _T_75 = and(_T_73, _T_74) @[ifu_aln_ctl.scala 149:26] + node _T_76 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 149:50] + node _T_77 = and(_T_75, _T_76) @[ifu_aln_ctl.scala 149:48] + node _T_78 = bits(_T_77, 0, 0) @[ifu_aln_ctl.scala 149:71] node _T_79 = mux(_T_47, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_80 = mux(_T_52, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_81 = mux(_T_57, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -62850,23 +62850,23 @@ circuit quasar_wrapper : node _T_91 = or(_T_90, _T_85) @[Mux.scala 27:72] wire _T_92 : UInt @[Mux.scala 27:72] _T_92 <= _T_91 @[Mux.scala 27:72] - rdptr_in <= _T_92 @[ifu_aln_ctl.scala 135:12] - node _T_93 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 143:30] - node _T_94 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 143:36] - node _T_95 = and(_T_93, _T_94) @[ifu_aln_ctl.scala 143:34] - node _T_96 = bits(_T_95, 0, 0) @[ifu_aln_ctl.scala 143:57] - node _T_97 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 144:10] - node _T_98 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 144:16] - node _T_99 = and(_T_97, _T_98) @[ifu_aln_ctl.scala 144:14] - node _T_100 = bits(_T_99, 0, 0) @[ifu_aln_ctl.scala 144:37] - node _T_101 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 145:10] - node _T_102 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 145:16] - node _T_103 = and(_T_101, _T_102) @[ifu_aln_ctl.scala 145:14] - node _T_104 = bits(_T_103, 0, 0) @[ifu_aln_ctl.scala 145:37] - node _T_105 = eq(ifvalid, UInt<1>("h00")) @[ifu_aln_ctl.scala 146:6] - node _T_106 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 146:17] - node _T_107 = and(_T_105, _T_106) @[ifu_aln_ctl.scala 146:15] - node _T_108 = bits(_T_107, 0, 0) @[ifu_aln_ctl.scala 146:38] + rdptr_in <= _T_92 @[ifu_aln_ctl.scala 143:12] + node _T_93 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 152:30] + node _T_94 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 152:36] + node _T_95 = and(_T_93, _T_94) @[ifu_aln_ctl.scala 152:34] + node _T_96 = bits(_T_95, 0, 0) @[ifu_aln_ctl.scala 152:57] + node _T_97 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 153:10] + node _T_98 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 153:16] + node _T_99 = and(_T_97, _T_98) @[ifu_aln_ctl.scala 153:14] + node _T_100 = bits(_T_99, 0, 0) @[ifu_aln_ctl.scala 153:37] + node _T_101 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 154:10] + node _T_102 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 154:16] + node _T_103 = and(_T_101, _T_102) @[ifu_aln_ctl.scala 154:14] + node _T_104 = bits(_T_103, 0, 0) @[ifu_aln_ctl.scala 154:37] + node _T_105 = eq(ifvalid, UInt<1>("h00")) @[ifu_aln_ctl.scala 155:6] + node _T_106 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 155:17] + node _T_107 = and(_T_105, _T_106) @[ifu_aln_ctl.scala 155:15] + node _T_108 = bits(_T_107, 0, 0) @[ifu_aln_ctl.scala 155:38] node _T_109 = mux(_T_96, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_110 = mux(_T_100, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_111 = mux(_T_104, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -62876,24 +62876,24 @@ circuit quasar_wrapper : node _T_115 = or(_T_114, _T_112) @[Mux.scala 27:72] wire _T_116 : UInt @[Mux.scala 27:72] _T_116 <= _T_115 @[Mux.scala 27:72] - wrptr_in <= _T_116 @[ifu_aln_ctl.scala 143:12] - node _T_117 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 148:31] - node _T_118 = eq(_T_117, UInt<1>("h00")) @[ifu_aln_ctl.scala 148:26] - node _T_119 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 148:43] - node _T_120 = and(_T_118, _T_119) @[ifu_aln_ctl.scala 148:35] - node _T_121 = bits(_T_120, 0, 0) @[ifu_aln_ctl.scala 148:52] - node _T_122 = or(q2off, f0_shift_2B) @[ifu_aln_ctl.scala 148:74] - node _T_123 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 149:11] - node _T_124 = eq(_T_123, UInt<1>("h00")) @[ifu_aln_ctl.scala 149:6] - node _T_125 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 149:23] - node _T_126 = and(_T_124, _T_125) @[ifu_aln_ctl.scala 149:15] - node _T_127 = bits(_T_126, 0, 0) @[ifu_aln_ctl.scala 149:32] - node _T_128 = or(q2off, f1_shift_2B) @[ifu_aln_ctl.scala 149:54] - node _T_129 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 150:11] - node _T_130 = eq(_T_129, UInt<1>("h00")) @[ifu_aln_ctl.scala 150:6] - node _T_131 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 150:23] - node _T_132 = and(_T_130, _T_131) @[ifu_aln_ctl.scala 150:15] - node _T_133 = bits(_T_132, 0, 0) @[ifu_aln_ctl.scala 150:32] + wrptr_in <= _T_116 @[ifu_aln_ctl.scala 152:12] + node _T_117 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 157:31] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[ifu_aln_ctl.scala 157:26] + node _T_119 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 157:43] + node _T_120 = and(_T_118, _T_119) @[ifu_aln_ctl.scala 157:35] + node _T_121 = bits(_T_120, 0, 0) @[ifu_aln_ctl.scala 157:52] + node _T_122 = or(q2off, f0_shift_2B) @[ifu_aln_ctl.scala 157:74] + node _T_123 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 158:11] + node _T_124 = eq(_T_123, UInt<1>("h00")) @[ifu_aln_ctl.scala 158:6] + node _T_125 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 158:23] + node _T_126 = and(_T_124, _T_125) @[ifu_aln_ctl.scala 158:15] + node _T_127 = bits(_T_126, 0, 0) @[ifu_aln_ctl.scala 158:32] + node _T_128 = or(q2off, f1_shift_2B) @[ifu_aln_ctl.scala 158:54] + node _T_129 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 159:11] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[ifu_aln_ctl.scala 159:6] + node _T_131 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 159:23] + node _T_132 = and(_T_130, _T_131) @[ifu_aln_ctl.scala 159:15] + node _T_133 = bits(_T_132, 0, 0) @[ifu_aln_ctl.scala 159:32] node _T_134 = mux(_T_121, _T_122, UInt<1>("h00")) @[Mux.scala 27:72] node _T_135 = mux(_T_127, _T_128, UInt<1>("h00")) @[Mux.scala 27:72] node _T_136 = mux(_T_133, q2off, UInt<1>("h00")) @[Mux.scala 27:72] @@ -62901,24 +62901,24 @@ circuit quasar_wrapper : node _T_138 = or(_T_137, _T_136) @[Mux.scala 27:72] wire _T_139 : UInt @[Mux.scala 27:72] _T_139 <= _T_138 @[Mux.scala 27:72] - q2off_in <= _T_139 @[ifu_aln_ctl.scala 148:12] - node _T_140 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 152:31] - node _T_141 = eq(_T_140, UInt<1>("h00")) @[ifu_aln_ctl.scala 152:26] - node _T_142 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 152:43] - node _T_143 = and(_T_141, _T_142) @[ifu_aln_ctl.scala 152:35] - node _T_144 = bits(_T_143, 0, 0) @[ifu_aln_ctl.scala 152:52] - node _T_145 = or(q1off, f0_shift_2B) @[ifu_aln_ctl.scala 152:74] - node _T_146 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 153:11] - node _T_147 = eq(_T_146, UInt<1>("h00")) @[ifu_aln_ctl.scala 153:6] - node _T_148 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 153:23] - node _T_149 = and(_T_147, _T_148) @[ifu_aln_ctl.scala 153:15] - node _T_150 = bits(_T_149, 0, 0) @[ifu_aln_ctl.scala 153:32] - node _T_151 = or(q1off, f1_shift_2B) @[ifu_aln_ctl.scala 153:54] - node _T_152 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 154:11] - node _T_153 = eq(_T_152, UInt<1>("h00")) @[ifu_aln_ctl.scala 154:6] - node _T_154 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 154:23] - node _T_155 = and(_T_153, _T_154) @[ifu_aln_ctl.scala 154:15] - node _T_156 = bits(_T_155, 0, 0) @[ifu_aln_ctl.scala 154:32] + q2off_in <= _T_139 @[ifu_aln_ctl.scala 157:12] + node _T_140 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 161:31] + node _T_141 = eq(_T_140, UInt<1>("h00")) @[ifu_aln_ctl.scala 161:26] + node _T_142 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 161:43] + node _T_143 = and(_T_141, _T_142) @[ifu_aln_ctl.scala 161:35] + node _T_144 = bits(_T_143, 0, 0) @[ifu_aln_ctl.scala 161:52] + node _T_145 = or(q1off, f0_shift_2B) @[ifu_aln_ctl.scala 161:74] + node _T_146 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 162:11] + node _T_147 = eq(_T_146, UInt<1>("h00")) @[ifu_aln_ctl.scala 162:6] + node _T_148 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 162:23] + node _T_149 = and(_T_147, _T_148) @[ifu_aln_ctl.scala 162:15] + node _T_150 = bits(_T_149, 0, 0) @[ifu_aln_ctl.scala 162:32] + node _T_151 = or(q1off, f1_shift_2B) @[ifu_aln_ctl.scala 162:54] + node _T_152 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 163:11] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[ifu_aln_ctl.scala 163:6] + node _T_154 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 163:23] + node _T_155 = and(_T_153, _T_154) @[ifu_aln_ctl.scala 163:15] + node _T_156 = bits(_T_155, 0, 0) @[ifu_aln_ctl.scala 163:32] node _T_157 = mux(_T_144, _T_145, UInt<1>("h00")) @[Mux.scala 27:72] node _T_158 = mux(_T_150, _T_151, UInt<1>("h00")) @[Mux.scala 27:72] node _T_159 = mux(_T_156, q1off, UInt<1>("h00")) @[Mux.scala 27:72] @@ -62926,24 +62926,24 @@ circuit quasar_wrapper : node _T_161 = or(_T_160, _T_159) @[Mux.scala 27:72] wire _T_162 : UInt @[Mux.scala 27:72] _T_162 <= _T_161 @[Mux.scala 27:72] - q1off_in <= _T_162 @[ifu_aln_ctl.scala 152:12] - node _T_163 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 156:31] - node _T_164 = eq(_T_163, UInt<1>("h00")) @[ifu_aln_ctl.scala 156:26] - node _T_165 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 156:43] - node _T_166 = and(_T_164, _T_165) @[ifu_aln_ctl.scala 156:35] - node _T_167 = bits(_T_166, 0, 0) @[ifu_aln_ctl.scala 156:52] - node _T_168 = or(q0off, f0_shift_2B) @[ifu_aln_ctl.scala 156:76] - node _T_169 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 157:31] - node _T_170 = eq(_T_169, UInt<1>("h00")) @[ifu_aln_ctl.scala 157:26] - node _T_171 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 157:43] - node _T_172 = and(_T_170, _T_171) @[ifu_aln_ctl.scala 157:35] - node _T_173 = bits(_T_172, 0, 0) @[ifu_aln_ctl.scala 157:52] - node _T_174 = or(q0off, f1_shift_2B) @[ifu_aln_ctl.scala 157:76] - node _T_175 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 158:31] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[ifu_aln_ctl.scala 158:26] - node _T_177 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 158:43] - node _T_178 = and(_T_176, _T_177) @[ifu_aln_ctl.scala 158:35] - node _T_179 = bits(_T_178, 0, 0) @[ifu_aln_ctl.scala 158:52] + q1off_in <= _T_162 @[ifu_aln_ctl.scala 161:12] + node _T_163 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 165:31] + node _T_164 = eq(_T_163, UInt<1>("h00")) @[ifu_aln_ctl.scala 165:26] + node _T_165 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 165:43] + node _T_166 = and(_T_164, _T_165) @[ifu_aln_ctl.scala 165:35] + node _T_167 = bits(_T_166, 0, 0) @[ifu_aln_ctl.scala 165:52] + node _T_168 = or(q0off, f0_shift_2B) @[ifu_aln_ctl.scala 165:76] + node _T_169 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 166:31] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[ifu_aln_ctl.scala 166:26] + node _T_171 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 166:43] + node _T_172 = and(_T_170, _T_171) @[ifu_aln_ctl.scala 166:35] + node _T_173 = bits(_T_172, 0, 0) @[ifu_aln_ctl.scala 166:52] + node _T_174 = or(q0off, f1_shift_2B) @[ifu_aln_ctl.scala 166:76] + node _T_175 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 167:31] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[ifu_aln_ctl.scala 167:26] + node _T_177 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 167:43] + node _T_178 = and(_T_176, _T_177) @[ifu_aln_ctl.scala 167:35] + node _T_179 = bits(_T_178, 0, 0) @[ifu_aln_ctl.scala 167:52] node _T_180 = mux(_T_167, _T_168, UInt<1>("h00")) @[Mux.scala 27:72] node _T_181 = mux(_T_173, _T_174, UInt<1>("h00")) @[Mux.scala 27:72] node _T_182 = mux(_T_179, q0off, UInt<1>("h00")) @[Mux.scala 27:72] @@ -62951,10 +62951,10 @@ circuit quasar_wrapper : node _T_184 = or(_T_183, _T_182) @[Mux.scala 27:72] wire _T_185 : UInt @[Mux.scala 27:72] _T_185 <= _T_184 @[Mux.scala 27:72] - q0off_in <= _T_185 @[ifu_aln_ctl.scala 156:12] - node _T_186 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 160:31] - node _T_187 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 161:11] - node _T_188 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 162:11] + q0off_in <= _T_185 @[ifu_aln_ctl.scala 165:12] + node _T_186 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 169:31] + node _T_187 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 170:11] + node _T_188 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 171:11] node _T_189 = mux(_T_186, q0off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_190 = mux(_T_187, q1off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_191 = mux(_T_188, q2off, UInt<1>("h00")) @[Mux.scala 27:72] @@ -62962,9 +62962,9 @@ circuit quasar_wrapper : node _T_193 = or(_T_192, _T_191) @[Mux.scala 27:72] wire q0ptr : UInt @[Mux.scala 27:72] q0ptr <= _T_193 @[Mux.scala 27:72] - node _T_194 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 164:32] - node _T_195 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 164:57] - node _T_196 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 164:83] + node _T_194 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 173:32] + node _T_195 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 173:57] + node _T_196 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 173:83] node _T_197 = mux(_T_194, q1off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_198 = mux(_T_195, q2off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_199 = mux(_T_196, q0off, UInt<1>("h00")) @[Mux.scala 27:72] @@ -62972,24 +62972,24 @@ circuit quasar_wrapper : node _T_201 = or(_T_200, _T_199) @[Mux.scala 27:72] wire q1ptr : UInt @[Mux.scala 27:72] q1ptr <= _T_201 @[Mux.scala 27:72] - node _T_202 = eq(q0ptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 166:26] + node _T_202 = eq(q0ptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 175:26] node q0sel = cat(q0ptr, _T_202) @[Cat.scala 29:58] - node _T_203 = eq(q1ptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 168:26] + node _T_203 = eq(q1ptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 177:26] node q1sel = cat(q1ptr, _T_203) @[Cat.scala 29:58] node _T_204 = cat(io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f) @[Cat.scala 29:58] node _T_205 = cat(_T_204, io.ifu_bp_fghr_f) @[Cat.scala 29:58] node _T_206 = cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f) @[Cat.scala 29:58] node _T_207 = cat(_T_206, io.ic_access_fault_type_f) @[Cat.scala 29:58] node _T_208 = cat(_T_207, _T_205) @[Cat.scala 29:58] - misc_data_in <= _T_208 @[ifu_aln_ctl.scala 170:16] - node _T_209 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 173:31] - node _T_210 = bits(_T_209, 0, 0) @[ifu_aln_ctl.scala 173:41] + misc_data_in <= _T_208 @[ifu_aln_ctl.scala 179:16] + node _T_209 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 182:31] + node _T_210 = bits(_T_209, 0, 0) @[ifu_aln_ctl.scala 182:41] node _T_211 = cat(misc1, misc0) @[Cat.scala 29:58] - node _T_212 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 174:9] - node _T_213 = bits(_T_212, 0, 0) @[ifu_aln_ctl.scala 174:19] + node _T_212 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 183:9] + node _T_213 = bits(_T_212, 0, 0) @[ifu_aln_ctl.scala 183:19] node _T_214 = cat(misc2, misc1) @[Cat.scala 29:58] - node _T_215 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 175:9] - node _T_216 = bits(_T_215, 0, 0) @[ifu_aln_ctl.scala 175:19] + node _T_215 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 184:9] + node _T_216 = bits(_T_215, 0, 0) @[ifu_aln_ctl.scala 184:19] node _T_217 = cat(misc0, misc2) @[Cat.scala 29:58] node _T_218 = mux(_T_210, _T_211, UInt<1>("h00")) @[Mux.scala 27:72] node _T_219 = mux(_T_213, _T_214, UInt<1>("h00")) @[Mux.scala 27:72] @@ -62998,34 +62998,34 @@ circuit quasar_wrapper : node _T_222 = or(_T_221, _T_220) @[Mux.scala 27:72] wire misceff : UInt<110> @[Mux.scala 27:72] misceff <= _T_222 @[Mux.scala 27:72] - node misc1eff = bits(misceff, 109, 55) @[ifu_aln_ctl.scala 177:25] - node misc0eff = bits(misceff, 54, 0) @[ifu_aln_ctl.scala 178:25] - node f1dbecc = bits(misc1eff, 54, 54) @[ifu_aln_ctl.scala 181:25] - node _T_223 = bits(misc1eff, 53, 53) @[ifu_aln_ctl.scala 182:21] - f1icaf <= _T_223 @[ifu_aln_ctl.scala 182:10] - node f1ictype = bits(misc1eff, 52, 51) @[ifu_aln_ctl.scala 183:26] - node f1prett = bits(misc1eff, 50, 20) @[ifu_aln_ctl.scala 184:25] - node f1poffset = bits(misc1eff, 19, 8) @[ifu_aln_ctl.scala 185:27] - node f1fghr = bits(misc1eff, 7, 0) @[ifu_aln_ctl.scala 186:24] - node f0dbecc = bits(misc0eff, 54, 54) @[ifu_aln_ctl.scala 188:25] - node _T_224 = bits(misc0eff, 53, 53) @[ifu_aln_ctl.scala 189:21] - f0icaf <= _T_224 @[ifu_aln_ctl.scala 189:10] - node f0ictype = bits(misc0eff, 52, 51) @[ifu_aln_ctl.scala 190:26] - node f0prett = bits(misc0eff, 50, 20) @[ifu_aln_ctl.scala 191:25] - node f0poffset = bits(misc0eff, 19, 8) @[ifu_aln_ctl.scala 192:27] - node f0fghr = bits(misc0eff, 7, 0) @[ifu_aln_ctl.scala 193:24] - node _T_225 = bits(io.ifu_bp_hist1_f, 1, 1) @[ifu_aln_ctl.scala 195:37] - node _T_226 = bits(io.ifu_bp_hist0_f, 1, 1) @[ifu_aln_ctl.scala 195:58] - node _T_227 = bits(io.ifu_bp_pc4_f, 1, 1) @[ifu_aln_ctl.scala 195:77] - node _T_228 = bits(io.ifu_bp_way_f, 1, 1) @[ifu_aln_ctl.scala 195:96] - node _T_229 = bits(io.ifu_bp_valid_f, 1, 1) @[ifu_aln_ctl.scala 195:117] - node _T_230 = bits(io.ifu_bp_ret_f, 1, 1) @[ifu_aln_ctl.scala 196:20] - node _T_231 = bits(io.ifu_bp_hist1_f, 0, 0) @[ifu_aln_ctl.scala 196:42] - node _T_232 = bits(io.ifu_bp_hist0_f, 0, 0) @[ifu_aln_ctl.scala 196:63] - node _T_233 = bits(io.ifu_bp_pc4_f, 0, 0) @[ifu_aln_ctl.scala 196:82] - node _T_234 = bits(io.ifu_bp_way_f, 0, 0) @[ifu_aln_ctl.scala 196:101] - node _T_235 = bits(io.ifu_bp_valid_f, 0, 0) @[ifu_aln_ctl.scala 197:22] - node _T_236 = bits(io.ifu_bp_ret_f, 0, 0) @[ifu_aln_ctl.scala 197:41] + node misc1eff = bits(misceff, 109, 55) @[ifu_aln_ctl.scala 186:25] + node misc0eff = bits(misceff, 54, 0) @[ifu_aln_ctl.scala 187:25] + node f1dbecc = bits(misc1eff, 54, 54) @[ifu_aln_ctl.scala 190:25] + node _T_223 = bits(misc1eff, 53, 53) @[ifu_aln_ctl.scala 191:21] + f1icaf <= _T_223 @[ifu_aln_ctl.scala 191:10] + node f1ictype = bits(misc1eff, 52, 51) @[ifu_aln_ctl.scala 192:26] + node f1prett = bits(misc1eff, 50, 20) @[ifu_aln_ctl.scala 193:25] + node f1poffset = bits(misc1eff, 19, 8) @[ifu_aln_ctl.scala 194:27] + node f1fghr = bits(misc1eff, 7, 0) @[ifu_aln_ctl.scala 195:24] + node f0dbecc = bits(misc0eff, 54, 54) @[ifu_aln_ctl.scala 197:25] + node _T_224 = bits(misc0eff, 53, 53) @[ifu_aln_ctl.scala 198:21] + f0icaf <= _T_224 @[ifu_aln_ctl.scala 198:10] + node f0ictype = bits(misc0eff, 52, 51) @[ifu_aln_ctl.scala 199:26] + node f0prett = bits(misc0eff, 50, 20) @[ifu_aln_ctl.scala 200:25] + node f0poffset = bits(misc0eff, 19, 8) @[ifu_aln_ctl.scala 201:27] + node f0fghr = bits(misc0eff, 7, 0) @[ifu_aln_ctl.scala 202:24] + node _T_225 = bits(io.ifu_bp_hist1_f, 1, 1) @[ifu_aln_ctl.scala 205:37] + node _T_226 = bits(io.ifu_bp_hist0_f, 1, 1) @[ifu_aln_ctl.scala 205:58] + node _T_227 = bits(io.ifu_bp_pc4_f, 1, 1) @[ifu_aln_ctl.scala 205:77] + node _T_228 = bits(io.ifu_bp_way_f, 1, 1) @[ifu_aln_ctl.scala 205:96] + node _T_229 = bits(io.ifu_bp_valid_f, 1, 1) @[ifu_aln_ctl.scala 205:117] + node _T_230 = bits(io.ifu_bp_ret_f, 1, 1) @[ifu_aln_ctl.scala 206:20] + node _T_231 = bits(io.ifu_bp_hist1_f, 0, 0) @[ifu_aln_ctl.scala 206:42] + node _T_232 = bits(io.ifu_bp_hist0_f, 0, 0) @[ifu_aln_ctl.scala 206:63] + node _T_233 = bits(io.ifu_bp_pc4_f, 0, 0) @[ifu_aln_ctl.scala 206:82] + node _T_234 = bits(io.ifu_bp_way_f, 0, 0) @[ifu_aln_ctl.scala 206:101] + node _T_235 = bits(io.ifu_bp_valid_f, 0, 0) @[ifu_aln_ctl.scala 207:22] + node _T_236 = bits(io.ifu_bp_ret_f, 0, 0) @[ifu_aln_ctl.scala 207:41] node _T_237 = cat(_T_234, _T_235) @[Cat.scala 29:58] node _T_238 = cat(_T_237, _T_236) @[Cat.scala 29:58] node _T_239 = cat(_T_231, _T_232) @[Cat.scala 29:58] @@ -63037,15 +63037,15 @@ circuit quasar_wrapper : node _T_245 = cat(_T_244, _T_227) @[Cat.scala 29:58] node _T_246 = cat(_T_245, _T_243) @[Cat.scala 29:58] node _T_247 = cat(_T_246, _T_241) @[Cat.scala 29:58] - brdata_in <= _T_247 @[ifu_aln_ctl.scala 195:13] - node _T_248 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 199:33] - node _T_249 = bits(_T_248, 0, 0) @[ifu_aln_ctl.scala 199:37] + brdata_in <= _T_247 @[ifu_aln_ctl.scala 205:13] + node _T_248 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 209:33] + node _T_249 = bits(_T_248, 0, 0) @[ifu_aln_ctl.scala 209:37] node _T_250 = cat(brdata1, brdata0) @[Cat.scala 29:58] - node _T_251 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 200:9] - node _T_252 = bits(_T_251, 0, 0) @[ifu_aln_ctl.scala 200:13] + node _T_251 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 210:9] + node _T_252 = bits(_T_251, 0, 0) @[ifu_aln_ctl.scala 210:13] node _T_253 = cat(brdata2, brdata1) @[Cat.scala 29:58] - node _T_254 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 201:9] - node _T_255 = bits(_T_254, 0, 0) @[ifu_aln_ctl.scala 201:13] + node _T_254 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 211:9] + node _T_255 = bits(_T_254, 0, 0) @[ifu_aln_ctl.scala 211:13] node _T_256 = cat(brdata0, brdata2) @[Cat.scala 29:58] node _T_257 = mux(_T_249, _T_250, UInt<1>("h00")) @[Mux.scala 27:72] node _T_258 = mux(_T_252, _T_253, UInt<1>("h00")) @[Mux.scala 27:72] @@ -63054,154 +63054,154 @@ circuit quasar_wrapper : node _T_261 = or(_T_260, _T_259) @[Mux.scala 27:72] wire brdataeff : UInt<24> @[Mux.scala 27:72] brdataeff <= _T_261 @[Mux.scala 27:72] - node brdata0eff = bits(brdataeff, 11, 0) @[ifu_aln_ctl.scala 203:43] - node brdata1eff = bits(brdataeff, 23, 12) @[ifu_aln_ctl.scala 203:61] - node _T_262 = bits(q0sel, 0, 0) @[ifu_aln_ctl.scala 205:37] - node _T_263 = bits(_T_262, 0, 0) @[ifu_aln_ctl.scala 205:41] - node _T_264 = bits(q0sel, 1, 1) @[ifu_aln_ctl.scala 205:68] - node _T_265 = bits(_T_264, 0, 0) @[ifu_aln_ctl.scala 205:72] - node _T_266 = bits(brdata0eff, 11, 6) @[ifu_aln_ctl.scala 205:92] + node brdata0eff = bits(brdataeff, 11, 0) @[ifu_aln_ctl.scala 213:43] + node brdata1eff = bits(brdataeff, 23, 12) @[ifu_aln_ctl.scala 213:61] + node _T_262 = bits(q0sel, 0, 0) @[ifu_aln_ctl.scala 215:37] + node _T_263 = bits(_T_262, 0, 0) @[ifu_aln_ctl.scala 215:41] + node _T_264 = bits(q0sel, 1, 1) @[ifu_aln_ctl.scala 215:68] + node _T_265 = bits(_T_264, 0, 0) @[ifu_aln_ctl.scala 215:72] + node _T_266 = bits(brdata0eff, 11, 6) @[ifu_aln_ctl.scala 215:92] node _T_267 = mux(_T_263, brdata0eff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_268 = mux(_T_265, _T_266, UInt<1>("h00")) @[Mux.scala 27:72] node _T_269 = or(_T_267, _T_268) @[Mux.scala 27:72] wire brdata0final : UInt<12> @[Mux.scala 27:72] brdata0final <= _T_269 @[Mux.scala 27:72] - node _T_270 = bits(q1sel, 0, 0) @[ifu_aln_ctl.scala 206:37] - node _T_271 = bits(_T_270, 0, 0) @[ifu_aln_ctl.scala 206:41] - node _T_272 = bits(q1sel, 1, 1) @[ifu_aln_ctl.scala 206:68] - node _T_273 = bits(_T_272, 0, 0) @[ifu_aln_ctl.scala 206:72] - node _T_274 = bits(brdata1eff, 11, 6) @[ifu_aln_ctl.scala 206:92] + node _T_270 = bits(q1sel, 0, 0) @[ifu_aln_ctl.scala 216:37] + node _T_271 = bits(_T_270, 0, 0) @[ifu_aln_ctl.scala 216:41] + node _T_272 = bits(q1sel, 1, 1) @[ifu_aln_ctl.scala 216:68] + node _T_273 = bits(_T_272, 0, 0) @[ifu_aln_ctl.scala 216:72] + node _T_274 = bits(brdata1eff, 11, 6) @[ifu_aln_ctl.scala 216:92] node _T_275 = mux(_T_271, brdata1eff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_276 = mux(_T_273, _T_274, UInt<1>("h00")) @[Mux.scala 27:72] node _T_277 = or(_T_275, _T_276) @[Mux.scala 27:72] wire brdata1final : UInt<12> @[Mux.scala 27:72] brdata1final <= _T_277 @[Mux.scala 27:72] - node _T_278 = bits(brdata0final, 6, 6) @[ifu_aln_ctl.scala 208:31] - node _T_279 = bits(brdata0final, 0, 0) @[ifu_aln_ctl.scala 208:47] + node _T_278 = bits(brdata0final, 6, 6) @[ifu_aln_ctl.scala 218:31] + node _T_279 = bits(brdata0final, 0, 0) @[ifu_aln_ctl.scala 218:47] node f0ret = cat(_T_278, _T_279) @[Cat.scala 29:58] - node _T_280 = bits(brdata0final, 7, 7) @[ifu_aln_ctl.scala 209:33] - node _T_281 = bits(brdata0final, 1, 1) @[ifu_aln_ctl.scala 209:49] + node _T_280 = bits(brdata0final, 7, 7) @[ifu_aln_ctl.scala 219:33] + node _T_281 = bits(brdata0final, 1, 1) @[ifu_aln_ctl.scala 219:49] node f0brend = cat(_T_280, _T_281) @[Cat.scala 29:58] - node _T_282 = bits(brdata0final, 8, 8) @[ifu_aln_ctl.scala 210:31] - node _T_283 = bits(brdata0final, 2, 2) @[ifu_aln_ctl.scala 210:47] + node _T_282 = bits(brdata0final, 8, 8) @[ifu_aln_ctl.scala 220:31] + node _T_283 = bits(brdata0final, 2, 2) @[ifu_aln_ctl.scala 220:47] node f0way = cat(_T_282, _T_283) @[Cat.scala 29:58] - node _T_284 = bits(brdata0final, 9, 9) @[ifu_aln_ctl.scala 211:31] - node _T_285 = bits(brdata0final, 3, 3) @[ifu_aln_ctl.scala 211:47] + node _T_284 = bits(brdata0final, 9, 9) @[ifu_aln_ctl.scala 221:31] + node _T_285 = bits(brdata0final, 3, 3) @[ifu_aln_ctl.scala 221:47] node f0pc4 = cat(_T_284, _T_285) @[Cat.scala 29:58] - node _T_286 = bits(brdata0final, 10, 10) @[ifu_aln_ctl.scala 212:33] - node _T_287 = bits(brdata0final, 4, 4) @[ifu_aln_ctl.scala 212:50] + node _T_286 = bits(brdata0final, 10, 10) @[ifu_aln_ctl.scala 222:33] + node _T_287 = bits(brdata0final, 4, 4) @[ifu_aln_ctl.scala 222:50] node f0hist0 = cat(_T_286, _T_287) @[Cat.scala 29:58] - node _T_288 = bits(brdata0final, 11, 11) @[ifu_aln_ctl.scala 213:33] - node _T_289 = bits(brdata0final, 5, 5) @[ifu_aln_ctl.scala 213:50] + node _T_288 = bits(brdata0final, 11, 11) @[ifu_aln_ctl.scala 223:33] + node _T_289 = bits(brdata0final, 5, 5) @[ifu_aln_ctl.scala 223:50] node f0hist1 = cat(_T_288, _T_289) @[Cat.scala 29:58] - node _T_290 = bits(brdata1final, 6, 6) @[ifu_aln_ctl.scala 215:31] - node _T_291 = bits(brdata1final, 0, 0) @[ifu_aln_ctl.scala 215:47] + node _T_290 = bits(brdata1final, 6, 6) @[ifu_aln_ctl.scala 225:31] + node _T_291 = bits(brdata1final, 0, 0) @[ifu_aln_ctl.scala 225:47] node f1ret = cat(_T_290, _T_291) @[Cat.scala 29:58] - node _T_292 = bits(brdata1final, 7, 7) @[ifu_aln_ctl.scala 216:33] - node _T_293 = bits(brdata1final, 1, 1) @[ifu_aln_ctl.scala 216:49] + node _T_292 = bits(brdata1final, 7, 7) @[ifu_aln_ctl.scala 226:33] + node _T_293 = bits(brdata1final, 1, 1) @[ifu_aln_ctl.scala 226:49] node f1brend = cat(_T_292, _T_293) @[Cat.scala 29:58] - node _T_294 = bits(brdata1final, 8, 8) @[ifu_aln_ctl.scala 217:31] - node _T_295 = bits(brdata1final, 2, 2) @[ifu_aln_ctl.scala 217:47] + node _T_294 = bits(brdata1final, 8, 8) @[ifu_aln_ctl.scala 227:31] + node _T_295 = bits(brdata1final, 2, 2) @[ifu_aln_ctl.scala 227:47] node f1way = cat(_T_294, _T_295) @[Cat.scala 29:58] - node _T_296 = bits(brdata1final, 9, 9) @[ifu_aln_ctl.scala 218:31] - node _T_297 = bits(brdata1final, 3, 3) @[ifu_aln_ctl.scala 218:47] + node _T_296 = bits(brdata1final, 9, 9) @[ifu_aln_ctl.scala 228:31] + node _T_297 = bits(brdata1final, 3, 3) @[ifu_aln_ctl.scala 228:47] node f1pc4 = cat(_T_296, _T_297) @[Cat.scala 29:58] - node _T_298 = bits(brdata1final, 10, 10) @[ifu_aln_ctl.scala 219:33] - node _T_299 = bits(brdata1final, 4, 4) @[ifu_aln_ctl.scala 219:50] + node _T_298 = bits(brdata1final, 10, 10) @[ifu_aln_ctl.scala 229:33] + node _T_299 = bits(brdata1final, 4, 4) @[ifu_aln_ctl.scala 229:50] node f1hist0 = cat(_T_298, _T_299) @[Cat.scala 29:58] - node _T_300 = bits(brdata1final, 11, 11) @[ifu_aln_ctl.scala 220:33] - node _T_301 = bits(brdata1final, 5, 5) @[ifu_aln_ctl.scala 220:50] + node _T_300 = bits(brdata1final, 11, 11) @[ifu_aln_ctl.scala 230:33] + node _T_301 = bits(brdata1final, 5, 5) @[ifu_aln_ctl.scala 230:50] node f1hist1 = cat(_T_300, _T_301) @[Cat.scala 29:58] - node _T_302 = bits(f2val, 0, 0) @[ifu_aln_ctl.scala 223:20] - f2_valid <= _T_302 @[ifu_aln_ctl.scala 223:12] - node _T_303 = bits(sf1val, 0, 0) @[ifu_aln_ctl.scala 224:22] - sf1_valid <= _T_303 @[ifu_aln_ctl.scala 224:13] - node _T_304 = bits(sf0val, 0, 0) @[ifu_aln_ctl.scala 225:22] - sf0_valid <= _T_304 @[ifu_aln_ctl.scala 225:13] - node _T_305 = bits(sf0val, 0, 0) @[ifu_aln_ctl.scala 227:28] - node _T_306 = eq(_T_305, UInt<1>("h00")) @[ifu_aln_ctl.scala 227:21] - node _T_307 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 227:39] - node consume_fb0 = and(_T_306, _T_307) @[ifu_aln_ctl.scala 227:32] - node _T_308 = bits(sf1val, 0, 0) @[ifu_aln_ctl.scala 228:28] - node _T_309 = eq(_T_308, UInt<1>("h00")) @[ifu_aln_ctl.scala 228:21] - node _T_310 = bits(f1val, 0, 0) @[ifu_aln_ctl.scala 228:39] - node consume_fb1 = and(_T_309, _T_310) @[ifu_aln_ctl.scala 228:32] - node _T_311 = eq(consume_fb1, UInt<1>("h00")) @[ifu_aln_ctl.scala 230:39] - node _T_312 = and(consume_fb0, _T_311) @[ifu_aln_ctl.scala 230:37] - node _T_313 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 230:54] - node _T_314 = and(_T_312, _T_313) @[ifu_aln_ctl.scala 230:52] - io.ifu_fb_consume1 <= _T_314 @[ifu_aln_ctl.scala 230:22] - node _T_315 = and(consume_fb0, consume_fb1) @[ifu_aln_ctl.scala 231:37] - node _T_316 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 231:54] - node _T_317 = and(_T_315, _T_316) @[ifu_aln_ctl.scala 231:52] - io.ifu_fb_consume2 <= _T_317 @[ifu_aln_ctl.scala 231:22] - node _T_318 = bits(io.ifu_fetch_val, 0, 0) @[ifu_aln_ctl.scala 233:30] - ifvalid <= _T_318 @[ifu_aln_ctl.scala 233:11] - node _T_319 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 235:18] - node _T_320 = and(_T_319, sf1_valid) @[ifu_aln_ctl.scala 235:29] - shift_f1_f0 <= _T_320 @[ifu_aln_ctl.scala 235:15] - node _T_321 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 236:18] - node _T_322 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 236:31] - node _T_323 = and(_T_321, _T_322) @[ifu_aln_ctl.scala 236:29] - node _T_324 = and(_T_323, f2_valid) @[ifu_aln_ctl.scala 236:42] - shift_f2_f0 <= _T_324 @[ifu_aln_ctl.scala 236:15] - node _T_325 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 237:18] - node _T_326 = and(_T_325, sf1_valid) @[ifu_aln_ctl.scala 237:29] - node _T_327 = and(_T_326, f2_valid) @[ifu_aln_ctl.scala 237:42] - shift_f2_f1 <= _T_327 @[ifu_aln_ctl.scala 237:15] - node _T_328 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 239:26] - node _T_329 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 239:39] - node _T_330 = and(_T_328, _T_329) @[ifu_aln_ctl.scala 239:37] - node _T_331 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 239:52] - node _T_332 = and(_T_330, _T_331) @[ifu_aln_ctl.scala 239:50] - node _T_333 = and(_T_332, ifvalid) @[ifu_aln_ctl.scala 239:62] - fetch_to_f0 <= _T_333 @[ifu_aln_ctl.scala 239:22] - node _T_334 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 240:26] - node _T_335 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 240:39] - node _T_336 = and(_T_334, _T_335) @[ifu_aln_ctl.scala 240:37] - node _T_337 = and(_T_336, f2_valid) @[ifu_aln_ctl.scala 240:50] - node _T_338 = and(_T_337, ifvalid) @[ifu_aln_ctl.scala 240:62] - node _T_339 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 241:26] - node _T_340 = and(_T_339, sf1_valid) @[ifu_aln_ctl.scala 241:37] - node _T_341 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 241:52] - node _T_342 = and(_T_340, _T_341) @[ifu_aln_ctl.scala 241:50] - node _T_343 = and(_T_342, ifvalid) @[ifu_aln_ctl.scala 241:62] - node _T_344 = or(_T_338, _T_343) @[ifu_aln_ctl.scala 240:74] - node _T_345 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 242:39] - node _T_346 = and(sf0_valid, _T_345) @[ifu_aln_ctl.scala 242:37] - node _T_347 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 242:52] - node _T_348 = and(_T_346, _T_347) @[ifu_aln_ctl.scala 242:50] - node _T_349 = and(_T_348, ifvalid) @[ifu_aln_ctl.scala 242:62] - node _T_350 = or(_T_344, _T_349) @[ifu_aln_ctl.scala 241:74] - fetch_to_f1 <= _T_350 @[ifu_aln_ctl.scala 240:22] - node _T_351 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 244:26] - node _T_352 = and(_T_351, sf1_valid) @[ifu_aln_ctl.scala 244:37] - node _T_353 = and(_T_352, f2_valid) @[ifu_aln_ctl.scala 244:50] - node _T_354 = and(_T_353, ifvalid) @[ifu_aln_ctl.scala 244:62] - node _T_355 = and(sf0_valid, sf1_valid) @[ifu_aln_ctl.scala 245:37] - node _T_356 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 245:52] - node _T_357 = and(_T_355, _T_356) @[ifu_aln_ctl.scala 245:50] - node _T_358 = and(_T_357, ifvalid) @[ifu_aln_ctl.scala 245:62] - node _T_359 = or(_T_354, _T_358) @[ifu_aln_ctl.scala 244:74] - fetch_to_f2 <= _T_359 @[ifu_aln_ctl.scala 244:22] - node _T_360 = add(f0pc, UInt<1>("h01")) @[ifu_aln_ctl.scala 247:25] - node f0pc_plus1 = tail(_T_360, 1) @[ifu_aln_ctl.scala 247:25] - node _T_361 = add(f1pc, UInt<1>("h01")) @[ifu_aln_ctl.scala 249:25] - node f1pc_plus1 = tail(_T_361, 1) @[ifu_aln_ctl.scala 249:25] + node _T_302 = bits(f2val, 0, 0) @[ifu_aln_ctl.scala 233:20] + f2_valid <= _T_302 @[ifu_aln_ctl.scala 233:12] + node _T_303 = bits(sf1val, 0, 0) @[ifu_aln_ctl.scala 234:22] + sf1_valid <= _T_303 @[ifu_aln_ctl.scala 234:13] + node _T_304 = bits(sf0val, 0, 0) @[ifu_aln_ctl.scala 235:22] + sf0_valid <= _T_304 @[ifu_aln_ctl.scala 235:13] + node _T_305 = bits(sf0val, 0, 0) @[ifu_aln_ctl.scala 237:28] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[ifu_aln_ctl.scala 237:21] + node _T_307 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 237:39] + node consume_fb0 = and(_T_306, _T_307) @[ifu_aln_ctl.scala 237:32] + node _T_308 = bits(sf1val, 0, 0) @[ifu_aln_ctl.scala 238:28] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[ifu_aln_ctl.scala 238:21] + node _T_310 = bits(f1val, 0, 0) @[ifu_aln_ctl.scala 238:39] + node consume_fb1 = and(_T_309, _T_310) @[ifu_aln_ctl.scala 238:32] + node _T_311 = eq(consume_fb1, UInt<1>("h00")) @[ifu_aln_ctl.scala 241:39] + node _T_312 = and(consume_fb0, _T_311) @[ifu_aln_ctl.scala 241:37] + node _T_313 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 241:54] + node _T_314 = and(_T_312, _T_313) @[ifu_aln_ctl.scala 241:52] + io.ifu_fb_consume1 <= _T_314 @[ifu_aln_ctl.scala 241:22] + node _T_315 = and(consume_fb0, consume_fb1) @[ifu_aln_ctl.scala 242:37] + node _T_316 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 242:54] + node _T_317 = and(_T_315, _T_316) @[ifu_aln_ctl.scala 242:52] + io.ifu_fb_consume2 <= _T_317 @[ifu_aln_ctl.scala 242:22] + node _T_318 = bits(io.ifu_fetch_val, 0, 0) @[ifu_aln_ctl.scala 244:30] + ifvalid <= _T_318 @[ifu_aln_ctl.scala 244:11] + node _T_319 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 247:18] + node _T_320 = and(_T_319, sf1_valid) @[ifu_aln_ctl.scala 247:29] + shift_f1_f0 <= _T_320 @[ifu_aln_ctl.scala 247:15] + node _T_321 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 248:18] + node _T_322 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 248:31] + node _T_323 = and(_T_321, _T_322) @[ifu_aln_ctl.scala 248:29] + node _T_324 = and(_T_323, f2_valid) @[ifu_aln_ctl.scala 248:42] + shift_f2_f0 <= _T_324 @[ifu_aln_ctl.scala 248:15] + node _T_325 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 249:18] + node _T_326 = and(_T_325, sf1_valid) @[ifu_aln_ctl.scala 249:29] + node _T_327 = and(_T_326, f2_valid) @[ifu_aln_ctl.scala 249:42] + shift_f2_f1 <= _T_327 @[ifu_aln_ctl.scala 249:15] + node _T_328 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 251:26] + node _T_329 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 251:39] + node _T_330 = and(_T_328, _T_329) @[ifu_aln_ctl.scala 251:37] + node _T_331 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 251:52] + node _T_332 = and(_T_330, _T_331) @[ifu_aln_ctl.scala 251:50] + node _T_333 = and(_T_332, ifvalid) @[ifu_aln_ctl.scala 251:62] + fetch_to_f0 <= _T_333 @[ifu_aln_ctl.scala 251:22] + node _T_334 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 252:26] + node _T_335 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 252:39] + node _T_336 = and(_T_334, _T_335) @[ifu_aln_ctl.scala 252:37] + node _T_337 = and(_T_336, f2_valid) @[ifu_aln_ctl.scala 252:50] + node _T_338 = and(_T_337, ifvalid) @[ifu_aln_ctl.scala 252:62] + node _T_339 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 253:26] + node _T_340 = and(_T_339, sf1_valid) @[ifu_aln_ctl.scala 253:37] + node _T_341 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 253:52] + node _T_342 = and(_T_340, _T_341) @[ifu_aln_ctl.scala 253:50] + node _T_343 = and(_T_342, ifvalid) @[ifu_aln_ctl.scala 253:62] + node _T_344 = or(_T_338, _T_343) @[ifu_aln_ctl.scala 252:74] + node _T_345 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 254:39] + node _T_346 = and(sf0_valid, _T_345) @[ifu_aln_ctl.scala 254:37] + node _T_347 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 254:52] + node _T_348 = and(_T_346, _T_347) @[ifu_aln_ctl.scala 254:50] + node _T_349 = and(_T_348, ifvalid) @[ifu_aln_ctl.scala 254:62] + node _T_350 = or(_T_344, _T_349) @[ifu_aln_ctl.scala 253:74] + fetch_to_f1 <= _T_350 @[ifu_aln_ctl.scala 252:22] + node _T_351 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 256:26] + node _T_352 = and(_T_351, sf1_valid) @[ifu_aln_ctl.scala 256:37] + node _T_353 = and(_T_352, f2_valid) @[ifu_aln_ctl.scala 256:50] + node _T_354 = and(_T_353, ifvalid) @[ifu_aln_ctl.scala 256:62] + node _T_355 = and(sf0_valid, sf1_valid) @[ifu_aln_ctl.scala 257:37] + node _T_356 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 257:52] + node _T_357 = and(_T_355, _T_356) @[ifu_aln_ctl.scala 257:50] + node _T_358 = and(_T_357, ifvalid) @[ifu_aln_ctl.scala 257:62] + node _T_359 = or(_T_354, _T_358) @[ifu_aln_ctl.scala 256:74] + fetch_to_f2 <= _T_359 @[ifu_aln_ctl.scala 256:22] + node _T_360 = add(f0pc, UInt<1>("h01")) @[ifu_aln_ctl.scala 259:25] + node f0pc_plus1 = tail(_T_360, 1) @[ifu_aln_ctl.scala 259:25] + node _T_361 = add(f1pc, UInt<1>("h01")) @[ifu_aln_ctl.scala 261:25] + node f1pc_plus1 = tail(_T_361, 1) @[ifu_aln_ctl.scala 261:25] node _T_362 = bits(f1_shift_2B, 0, 0) @[Bitwise.scala 72:15] node _T_363 = mux(_T_362, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_364 = and(_T_363, f1pc_plus1) @[ifu_aln_ctl.scala 251:38] - node _T_365 = eq(f1_shift_2B, UInt<1>("h00")) @[ifu_aln_ctl.scala 251:64] + node _T_364 = and(_T_363, f1pc_plus1) @[ifu_aln_ctl.scala 263:38] + node _T_365 = eq(f1_shift_2B, UInt<1>("h00")) @[ifu_aln_ctl.scala 263:64] node _T_366 = bits(_T_365, 0, 0) @[Bitwise.scala 72:15] node _T_367 = mux(_T_366, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_368 = and(_T_367, f1pc) @[ifu_aln_ctl.scala 251:78] - node sf1pc = or(_T_364, _T_368) @[ifu_aln_ctl.scala 251:52] - node _T_369 = bits(fetch_to_f1, 0, 0) @[ifu_aln_ctl.scala 253:36] - node _T_370 = bits(shift_f2_f1, 0, 0) @[ifu_aln_ctl.scala 254:17] - node _T_371 = eq(fetch_to_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 255:6] - node _T_372 = eq(shift_f2_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 255:21] - node _T_373 = and(_T_371, _T_372) @[ifu_aln_ctl.scala 255:19] - node _T_374 = bits(_T_373, 0, 0) @[ifu_aln_ctl.scala 255:35] + node _T_368 = and(_T_367, f1pc) @[ifu_aln_ctl.scala 263:78] + node sf1pc = or(_T_364, _T_368) @[ifu_aln_ctl.scala 263:52] + node _T_369 = bits(fetch_to_f1, 0, 0) @[ifu_aln_ctl.scala 265:36] + node _T_370 = bits(shift_f2_f1, 0, 0) @[ifu_aln_ctl.scala 266:17] + node _T_371 = eq(fetch_to_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 267:6] + node _T_372 = eq(shift_f2_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 267:21] + node _T_373 = and(_T_371, _T_372) @[ifu_aln_ctl.scala 267:19] + node _T_374 = bits(_T_373, 0, 0) @[ifu_aln_ctl.scala 267:35] node _T_375 = mux(_T_369, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_376 = mux(_T_370, f2pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_377 = mux(_T_374, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72] @@ -63209,16 +63209,16 @@ circuit quasar_wrapper : node _T_379 = or(_T_378, _T_377) @[Mux.scala 27:72] wire _T_380 : UInt @[Mux.scala 27:72] _T_380 <= _T_379 @[Mux.scala 27:72] - f1pc_in <= _T_380 @[ifu_aln_ctl.scala 253:11] - node _T_381 = bits(fetch_to_f0, 0, 0) @[ifu_aln_ctl.scala 257:36] - node _T_382 = bits(shift_f2_f0, 0, 0) @[ifu_aln_ctl.scala 258:36] - node _T_383 = bits(shift_f1_f0, 0, 0) @[ifu_aln_ctl.scala 259:36] - node _T_384 = eq(fetch_to_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 260:24] - node _T_385 = eq(shift_f2_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 260:39] - node _T_386 = and(_T_384, _T_385) @[ifu_aln_ctl.scala 260:37] - node _T_387 = eq(shift_f1_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 260:54] - node _T_388 = and(_T_386, _T_387) @[ifu_aln_ctl.scala 260:52] - node _T_389 = bits(_T_388, 0, 0) @[ifu_aln_ctl.scala 260:68] + f1pc_in <= _T_380 @[ifu_aln_ctl.scala 265:11] + node _T_381 = bits(fetch_to_f0, 0, 0) @[ifu_aln_ctl.scala 269:36] + node _T_382 = bits(shift_f2_f0, 0, 0) @[ifu_aln_ctl.scala 270:36] + node _T_383 = bits(shift_f1_f0, 0, 0) @[ifu_aln_ctl.scala 271:36] + node _T_384 = eq(fetch_to_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 272:24] + node _T_385 = eq(shift_f2_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 272:39] + node _T_386 = and(_T_384, _T_385) @[ifu_aln_ctl.scala 272:37] + node _T_387 = eq(shift_f1_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 272:54] + node _T_388 = and(_T_386, _T_387) @[ifu_aln_ctl.scala 272:52] + node _T_389 = bits(_T_388, 0, 0) @[ifu_aln_ctl.scala 272:68] node _T_390 = mux(_T_381, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_391 = mux(_T_382, f2pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_392 = mux(_T_383, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72] @@ -63228,48 +63228,48 @@ circuit quasar_wrapper : node _T_396 = or(_T_395, _T_393) @[Mux.scala 27:72] wire _T_397 : UInt @[Mux.scala 27:72] _T_397 <= _T_396 @[Mux.scala 27:72] - f0pc_in <= _T_397 @[ifu_aln_ctl.scala 257:11] - node _T_398 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 262:40] - node _T_399 = and(fetch_to_f2, _T_398) @[ifu_aln_ctl.scala 262:38] - node _T_400 = bits(_T_399, 0, 0) @[ifu_aln_ctl.scala 262:61] - node _T_401 = eq(fetch_to_f2, UInt<1>("h00")) @[ifu_aln_ctl.scala 263:25] - node _T_402 = eq(shift_f2_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 263:40] - node _T_403 = and(_T_401, _T_402) @[ifu_aln_ctl.scala 263:38] - node _T_404 = eq(shift_f2_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 263:55] - node _T_405 = and(_T_403, _T_404) @[ifu_aln_ctl.scala 263:53] - node _T_406 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 263:70] - node _T_407 = and(_T_405, _T_406) @[ifu_aln_ctl.scala 263:68] - node _T_408 = bits(_T_407, 0, 0) @[ifu_aln_ctl.scala 263:91] + f0pc_in <= _T_397 @[ifu_aln_ctl.scala 269:11] + node _T_398 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 274:40] + node _T_399 = and(fetch_to_f2, _T_398) @[ifu_aln_ctl.scala 274:38] + node _T_400 = bits(_T_399, 0, 0) @[ifu_aln_ctl.scala 274:61] + node _T_401 = eq(fetch_to_f2, UInt<1>("h00")) @[ifu_aln_ctl.scala 275:25] + node _T_402 = eq(shift_f2_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 275:40] + node _T_403 = and(_T_401, _T_402) @[ifu_aln_ctl.scala 275:38] + node _T_404 = eq(shift_f2_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 275:55] + node _T_405 = and(_T_403, _T_404) @[ifu_aln_ctl.scala 275:53] + node _T_406 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 275:70] + node _T_407 = and(_T_405, _T_406) @[ifu_aln_ctl.scala 275:68] + node _T_408 = bits(_T_407, 0, 0) @[ifu_aln_ctl.scala 275:91] node _T_409 = mux(_T_400, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_410 = mux(_T_408, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_411 = or(_T_409, _T_410) @[Mux.scala 27:72] wire _T_412 : UInt @[Mux.scala 27:72] _T_412 <= _T_411 @[Mux.scala 27:72] - f2val_in <= _T_412 @[ifu_aln_ctl.scala 262:12] - node _T_413 = bits(f1_shift_2B, 0, 0) @[ifu_aln_ctl.scala 265:35] - node _T_414 = bits(f1val, 1, 1) @[ifu_aln_ctl.scala 265:48] - node _T_415 = bits(f1_shift_2B, 0, 0) @[ifu_aln_ctl.scala 265:66] - node _T_416 = eq(_T_415, UInt<1>("h00")) @[ifu_aln_ctl.scala 265:53] + f2val_in <= _T_412 @[ifu_aln_ctl.scala 274:12] + node _T_413 = bits(f1_shift_2B, 0, 0) @[ifu_aln_ctl.scala 277:35] + node _T_414 = bits(f1val, 1, 1) @[ifu_aln_ctl.scala 277:48] + node _T_415 = bits(f1_shift_2B, 0, 0) @[ifu_aln_ctl.scala 277:66] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[ifu_aln_ctl.scala 277:53] node _T_417 = mux(_T_413, _T_414, UInt<1>("h00")) @[Mux.scala 27:72] node _T_418 = mux(_T_416, f1val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_419 = or(_T_417, _T_418) @[Mux.scala 27:72] wire _T_420 : UInt @[Mux.scala 27:72] _T_420 <= _T_419 @[Mux.scala 27:72] - sf1val <= _T_420 @[ifu_aln_ctl.scala 265:10] - node _T_421 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 267:71] - node _T_422 = and(fetch_to_f1, _T_421) @[ifu_aln_ctl.scala 267:39] - node _T_423 = bits(_T_422, 0, 0) @[ifu_aln_ctl.scala 267:92] - node _T_424 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 268:71] - node _T_425 = and(shift_f2_f1, _T_424) @[ifu_aln_ctl.scala 268:54] - node _T_426 = bits(_T_425, 0, 0) @[ifu_aln_ctl.scala 268:92] - node _T_427 = eq(fetch_to_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 269:26] - node _T_428 = eq(shift_f2_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 269:41] - node _T_429 = and(_T_427, _T_428) @[ifu_aln_ctl.scala 269:39] - node _T_430 = eq(shift_f1_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 269:56] - node _T_431 = and(_T_429, _T_430) @[ifu_aln_ctl.scala 269:54] - node _T_432 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 269:71] - node _T_433 = and(_T_431, _T_432) @[ifu_aln_ctl.scala 269:69] - node _T_434 = bits(_T_433, 0, 0) @[ifu_aln_ctl.scala 269:92] + sf1val <= _T_420 @[ifu_aln_ctl.scala 277:10] + node _T_421 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 279:71] + node _T_422 = and(fetch_to_f1, _T_421) @[ifu_aln_ctl.scala 279:39] + node _T_423 = bits(_T_422, 0, 0) @[ifu_aln_ctl.scala 279:92] + node _T_424 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 280:71] + node _T_425 = and(shift_f2_f1, _T_424) @[ifu_aln_ctl.scala 280:54] + node _T_426 = bits(_T_425, 0, 0) @[ifu_aln_ctl.scala 280:92] + node _T_427 = eq(fetch_to_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 281:26] + node _T_428 = eq(shift_f2_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 281:41] + node _T_429 = and(_T_427, _T_428) @[ifu_aln_ctl.scala 281:39] + node _T_430 = eq(shift_f1_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 281:56] + node _T_431 = and(_T_429, _T_430) @[ifu_aln_ctl.scala 281:54] + node _T_432 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 281:71] + node _T_433 = and(_T_431, _T_432) @[ifu_aln_ctl.scala 281:69] + node _T_434 = bits(_T_433, 0, 0) @[ifu_aln_ctl.scala 281:92] node _T_435 = mux(_T_423, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_436 = mux(_T_426, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_437 = mux(_T_434, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] @@ -63277,37 +63277,37 @@ circuit quasar_wrapper : node _T_439 = or(_T_438, _T_437) @[Mux.scala 27:72] wire _T_440 : UInt @[Mux.scala 27:72] _T_440 <= _T_439 @[Mux.scala 27:72] - f1val_in <= _T_440 @[ifu_aln_ctl.scala 267:12] - node _T_441 = bits(shift_2B, 0, 0) @[ifu_aln_ctl.scala 271:32] - node _T_442 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 271:54] + f1val_in <= _T_440 @[ifu_aln_ctl.scala 279:12] + node _T_441 = bits(shift_2B, 0, 0) @[ifu_aln_ctl.scala 283:32] + node _T_442 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 283:54] node _T_443 = cat(UInt<1>("h00"), _T_442) @[Cat.scala 29:58] - node _T_444 = eq(shift_2B, UInt<1>("h00")) @[ifu_aln_ctl.scala 272:18] - node _T_445 = eq(shift_4B, UInt<1>("h00")) @[ifu_aln_ctl.scala 272:30] - node _T_446 = and(_T_444, _T_445) @[ifu_aln_ctl.scala 272:28] - node _T_447 = bits(_T_446, 0, 0) @[ifu_aln_ctl.scala 272:41] + node _T_444 = eq(shift_2B, UInt<1>("h00")) @[ifu_aln_ctl.scala 284:18] + node _T_445 = eq(shift_4B, UInt<1>("h00")) @[ifu_aln_ctl.scala 284:30] + node _T_446 = and(_T_444, _T_445) @[ifu_aln_ctl.scala 284:28] + node _T_447 = bits(_T_446, 0, 0) @[ifu_aln_ctl.scala 284:41] node _T_448 = mux(_T_441, _T_443, UInt<1>("h00")) @[Mux.scala 27:72] node _T_449 = mux(_T_447, f0val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_450 = or(_T_448, _T_449) @[Mux.scala 27:72] wire _T_451 : UInt @[Mux.scala 27:72] _T_451 <= _T_450 @[Mux.scala 27:72] - sf0val <= _T_451 @[ifu_aln_ctl.scala 271:10] - node _T_452 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 274:71] - node _T_453 = and(fetch_to_f0, _T_452) @[ifu_aln_ctl.scala 274:38] - node _T_454 = bits(_T_453, 0, 0) @[ifu_aln_ctl.scala 274:92] - node _T_455 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 275:71] - node _T_456 = and(shift_f2_f0, _T_455) @[ifu_aln_ctl.scala 275:54] - node _T_457 = bits(_T_456, 0, 0) @[ifu_aln_ctl.scala 275:92] - node _T_458 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 276:71] - node _T_459 = and(shift_f1_f0, _T_458) @[ifu_aln_ctl.scala 276:69] - node _T_460 = bits(_T_459, 0, 0) @[ifu_aln_ctl.scala 276:92] - node _T_461 = eq(fetch_to_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 277:26] - node _T_462 = eq(shift_f2_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 277:41] - node _T_463 = and(_T_461, _T_462) @[ifu_aln_ctl.scala 277:39] - node _T_464 = eq(shift_f1_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 277:56] - node _T_465 = and(_T_463, _T_464) @[ifu_aln_ctl.scala 277:54] - node _T_466 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 277:71] - node _T_467 = and(_T_465, _T_466) @[ifu_aln_ctl.scala 277:69] - node _T_468 = bits(_T_467, 0, 0) @[ifu_aln_ctl.scala 277:92] + sf0val <= _T_451 @[ifu_aln_ctl.scala 283:10] + node _T_452 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 286:71] + node _T_453 = and(fetch_to_f0, _T_452) @[ifu_aln_ctl.scala 286:38] + node _T_454 = bits(_T_453, 0, 0) @[ifu_aln_ctl.scala 286:92] + node _T_455 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 287:71] + node _T_456 = and(shift_f2_f0, _T_455) @[ifu_aln_ctl.scala 287:54] + node _T_457 = bits(_T_456, 0, 0) @[ifu_aln_ctl.scala 287:92] + node _T_458 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 288:71] + node _T_459 = and(shift_f1_f0, _T_458) @[ifu_aln_ctl.scala 288:69] + node _T_460 = bits(_T_459, 0, 0) @[ifu_aln_ctl.scala 288:92] + node _T_461 = eq(fetch_to_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 289:26] + node _T_462 = eq(shift_f2_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 289:41] + node _T_463 = and(_T_461, _T_462) @[ifu_aln_ctl.scala 289:39] + node _T_464 = eq(shift_f1_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 289:56] + node _T_465 = and(_T_463, _T_464) @[ifu_aln_ctl.scala 289:54] + node _T_466 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 289:71] + node _T_467 = and(_T_465, _T_466) @[ifu_aln_ctl.scala 289:69] + node _T_468 = bits(_T_467, 0, 0) @[ifu_aln_ctl.scala 289:92] node _T_469 = mux(_T_454, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_470 = mux(_T_457, f2val, UInt<1>("h00")) @[Mux.scala 27:72] node _T_471 = mux(_T_460, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] @@ -63317,15 +63317,15 @@ circuit quasar_wrapper : node _T_475 = or(_T_474, _T_472) @[Mux.scala 27:72] wire _T_476 : UInt @[Mux.scala 27:72] _T_476 <= _T_475 @[Mux.scala 27:72] - f0val_in <= _T_476 @[ifu_aln_ctl.scala 274:12] - node _T_477 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 279:28] - node _T_478 = bits(_T_477, 0, 0) @[ifu_aln_ctl.scala 279:32] + f0val_in <= _T_476 @[ifu_aln_ctl.scala 286:12] + node _T_477 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 291:28] + node _T_478 = bits(_T_477, 0, 0) @[ifu_aln_ctl.scala 291:32] node _T_479 = cat(q1, q0) @[Cat.scala 29:58] - node _T_480 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 280:9] - node _T_481 = bits(_T_480, 0, 0) @[ifu_aln_ctl.scala 280:13] + node _T_480 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 292:9] + node _T_481 = bits(_T_480, 0, 0) @[ifu_aln_ctl.scala 292:13] node _T_482 = cat(q2, q1) @[Cat.scala 29:58] - node _T_483 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 281:9] - node _T_484 = bits(_T_483, 0, 0) @[ifu_aln_ctl.scala 281:13] + node _T_483 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 293:9] + node _T_484 = bits(_T_483, 0, 0) @[ifu_aln_ctl.scala 293:13] node _T_485 = cat(q0, q2) @[Cat.scala 29:58] node _T_486 = mux(_T_478, _T_479, UInt<1>("h00")) @[Mux.scala 27:72] node _T_487 = mux(_T_481, _T_482, UInt<1>("h00")) @[Mux.scala 27:72] @@ -63334,263 +63334,263 @@ circuit quasar_wrapper : node _T_490 = or(_T_489, _T_488) @[Mux.scala 27:72] wire qeff : UInt<64> @[Mux.scala 27:72] qeff <= _T_490 @[Mux.scala 27:72] - node q1eff = bits(qeff, 63, 32) @[ifu_aln_ctl.scala 282:29] - node q0eff = bits(qeff, 31, 0) @[ifu_aln_ctl.scala 282:42] - node _T_491 = bits(q0sel, 0, 0) @[ifu_aln_ctl.scala 284:29] - node _T_492 = bits(_T_491, 0, 0) @[ifu_aln_ctl.scala 284:33] - node _T_493 = bits(q0sel, 1, 1) @[ifu_aln_ctl.scala 284:53] - node _T_494 = bits(_T_493, 0, 0) @[ifu_aln_ctl.scala 284:57] - node _T_495 = bits(q0eff, 31, 16) @[ifu_aln_ctl.scala 284:70] + node q1eff = bits(qeff, 63, 32) @[ifu_aln_ctl.scala 294:29] + node q0eff = bits(qeff, 31, 0) @[ifu_aln_ctl.scala 294:42] + node _T_491 = bits(q0sel, 0, 0) @[ifu_aln_ctl.scala 296:29] + node _T_492 = bits(_T_491, 0, 0) @[ifu_aln_ctl.scala 296:33] + node _T_493 = bits(q0sel, 1, 1) @[ifu_aln_ctl.scala 296:53] + node _T_494 = bits(_T_493, 0, 0) @[ifu_aln_ctl.scala 296:57] + node _T_495 = bits(q0eff, 31, 16) @[ifu_aln_ctl.scala 296:70] node _T_496 = mux(_T_492, q0eff, UInt<1>("h00")) @[Mux.scala 27:72] node _T_497 = mux(_T_494, _T_495, UInt<1>("h00")) @[Mux.scala 27:72] node _T_498 = or(_T_496, _T_497) @[Mux.scala 27:72] wire _T_499 : UInt<32> @[Mux.scala 27:72] _T_499 <= _T_498 @[Mux.scala 27:72] - q0final <= _T_499 @[ifu_aln_ctl.scala 284:11] - node _T_500 = bits(q1sel, 0, 0) @[ifu_aln_ctl.scala 286:29] - node _T_501 = bits(_T_500, 0, 0) @[ifu_aln_ctl.scala 286:33] - node _T_502 = bits(q1eff, 15, 0) @[ifu_aln_ctl.scala 286:46] - node _T_503 = bits(q1sel, 1, 1) @[ifu_aln_ctl.scala 286:59] - node _T_504 = bits(_T_503, 0, 0) @[ifu_aln_ctl.scala 286:63] - node _T_505 = bits(q1eff, 31, 16) @[ifu_aln_ctl.scala 286:76] + q0final <= _T_499 @[ifu_aln_ctl.scala 296:11] + node _T_500 = bits(q1sel, 0, 0) @[ifu_aln_ctl.scala 298:29] + node _T_501 = bits(_T_500, 0, 0) @[ifu_aln_ctl.scala 298:33] + node _T_502 = bits(q1eff, 15, 0) @[ifu_aln_ctl.scala 298:46] + node _T_503 = bits(q1sel, 1, 1) @[ifu_aln_ctl.scala 298:59] + node _T_504 = bits(_T_503, 0, 0) @[ifu_aln_ctl.scala 298:63] + node _T_505 = bits(q1eff, 31, 16) @[ifu_aln_ctl.scala 298:76] node _T_506 = mux(_T_501, _T_502, UInt<1>("h00")) @[Mux.scala 27:72] node _T_507 = mux(_T_504, _T_505, UInt<1>("h00")) @[Mux.scala 27:72] node _T_508 = or(_T_506, _T_507) @[Mux.scala 27:72] wire _T_509 : UInt<16> @[Mux.scala 27:72] _T_509 <= _T_508 @[Mux.scala 27:72] - q1final <= _T_509 @[ifu_aln_ctl.scala 286:11] - node _T_510 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 288:34] - node _T_511 = bits(_T_510, 0, 0) @[ifu_aln_ctl.scala 288:38] - node _T_512 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 288:64] - node _T_513 = not(_T_512) @[ifu_aln_ctl.scala 288:58] - node _T_514 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 288:75] - node _T_515 = and(_T_513, _T_514) @[ifu_aln_ctl.scala 288:68] - node _T_516 = bits(_T_515, 0, 0) @[ifu_aln_ctl.scala 288:80] - node _T_517 = bits(q1final, 15, 0) @[ifu_aln_ctl.scala 288:101] - node _T_518 = bits(q0final, 15, 0) @[ifu_aln_ctl.scala 288:115] + q1final <= _T_509 @[ifu_aln_ctl.scala 298:11] + node _T_510 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 301:34] + node _T_511 = bits(_T_510, 0, 0) @[ifu_aln_ctl.scala 301:38] + node _T_512 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 301:64] + node _T_513 = not(_T_512) @[ifu_aln_ctl.scala 301:58] + node _T_514 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 301:75] + node _T_515 = and(_T_513, _T_514) @[ifu_aln_ctl.scala 301:68] + node _T_516 = bits(_T_515, 0, 0) @[ifu_aln_ctl.scala 301:80] + node _T_517 = bits(q1final, 15, 0) @[ifu_aln_ctl.scala 301:101] + node _T_518 = bits(q0final, 15, 0) @[ifu_aln_ctl.scala 301:115] node _T_519 = cat(_T_517, _T_518) @[Cat.scala 29:58] node _T_520 = mux(_T_511, q0final, UInt<1>("h00")) @[Mux.scala 27:72] node _T_521 = mux(_T_516, _T_519, UInt<1>("h00")) @[Mux.scala 27:72] node _T_522 = or(_T_520, _T_521) @[Mux.scala 27:72] wire aligndata : UInt<32> @[Mux.scala 27:72] aligndata <= _T_522 @[Mux.scala 27:72] - node _T_523 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 290:30] - node _T_524 = bits(_T_523, 0, 0) @[ifu_aln_ctl.scala 290:34] - node _T_525 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 290:54] - node _T_526 = eq(_T_525, UInt<1>("h00")) @[ifu_aln_ctl.scala 290:48] - node _T_527 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 290:65] - node _T_528 = and(_T_526, _T_527) @[ifu_aln_ctl.scala 290:58] - node _T_529 = bits(f1val, 0, 0) @[ifu_aln_ctl.scala 290:82] + node _T_523 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 303:30] + node _T_524 = bits(_T_523, 0, 0) @[ifu_aln_ctl.scala 303:34] + node _T_525 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 303:54] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[ifu_aln_ctl.scala 303:48] + node _T_527 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 303:65] + node _T_528 = and(_T_526, _T_527) @[ifu_aln_ctl.scala 303:58] + node _T_529 = bits(f1val, 0, 0) @[ifu_aln_ctl.scala 303:82] node _T_530 = cat(_T_529, UInt<1>("h01")) @[Cat.scala 29:58] node _T_531 = mux(_T_524, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_532 = mux(_T_528, _T_530, UInt<1>("h00")) @[Mux.scala 27:72] node _T_533 = or(_T_531, _T_532) @[Mux.scala 27:72] wire _T_534 : UInt<2> @[Mux.scala 27:72] _T_534 <= _T_533 @[Mux.scala 27:72] - alignval <= _T_534 @[ifu_aln_ctl.scala 290:12] - node _T_535 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 292:34] - node _T_536 = bits(_T_535, 0, 0) @[ifu_aln_ctl.scala 292:38] - node _T_537 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 292:63] - node _T_538 = not(_T_537) @[ifu_aln_ctl.scala 292:57] - node _T_539 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 292:74] - node _T_540 = and(_T_538, _T_539) @[ifu_aln_ctl.scala 292:67] - node _T_541 = bits(_T_540, 0, 0) @[ifu_aln_ctl.scala 292:79] + alignval <= _T_534 @[ifu_aln_ctl.scala 303:12] + node _T_535 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 305:34] + node _T_536 = bits(_T_535, 0, 0) @[ifu_aln_ctl.scala 305:38] + node _T_537 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 305:63] + node _T_538 = not(_T_537) @[ifu_aln_ctl.scala 305:57] + node _T_539 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 305:74] + node _T_540 = and(_T_538, _T_539) @[ifu_aln_ctl.scala 305:67] + node _T_541 = bits(_T_540, 0, 0) @[ifu_aln_ctl.scala 305:79] node _T_542 = cat(f1icaf, f0icaf) @[Cat.scala 29:58] node _T_543 = mux(_T_536, f0icaf, UInt<1>("h00")) @[Mux.scala 27:72] node _T_544 = mux(_T_541, _T_542, UInt<1>("h00")) @[Mux.scala 27:72] node _T_545 = or(_T_543, _T_544) @[Mux.scala 27:72] wire alignicaf : UInt<2> @[Mux.scala 27:72] alignicaf <= _T_545 @[Mux.scala 27:72] - node _T_546 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 294:35] - node _T_547 = bits(_T_546, 0, 0) @[ifu_aln_ctl.scala 294:39] + node _T_546 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 307:35] + node _T_547 = bits(_T_546, 0, 0) @[ifu_aln_ctl.scala 307:39] node _T_548 = bits(f0dbecc, 0, 0) @[Bitwise.scala 72:15] node _T_549 = mux(_T_548, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_550 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 294:73] - node _T_551 = eq(_T_550, UInt<1>("h00")) @[ifu_aln_ctl.scala 294:67] - node _T_552 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 294:84] - node _T_553 = and(_T_551, _T_552) @[ifu_aln_ctl.scala 294:77] - node _T_554 = bits(_T_553, 0, 0) @[ifu_aln_ctl.scala 294:89] + node _T_550 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 307:73] + node _T_551 = eq(_T_550, UInt<1>("h00")) @[ifu_aln_ctl.scala 307:67] + node _T_552 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 307:84] + node _T_553 = and(_T_551, _T_552) @[ifu_aln_ctl.scala 307:77] + node _T_554 = bits(_T_553, 0, 0) @[ifu_aln_ctl.scala 307:89] node _T_555 = cat(f1dbecc, f0dbecc) @[Cat.scala 29:58] node _T_556 = mux(_T_547, _T_549, UInt<1>("h00")) @[Mux.scala 27:72] node _T_557 = mux(_T_554, _T_555, UInt<1>("h00")) @[Mux.scala 27:72] node _T_558 = or(_T_556, _T_557) @[Mux.scala 27:72] wire aligndbecc : UInt<2> @[Mux.scala 27:72] aligndbecc <= _T_558 @[Mux.scala 27:72] - node _T_559 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 296:35] - node _T_560 = bits(_T_559, 0, 0) @[ifu_aln_ctl.scala 296:45] - node _T_561 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 296:65] - node _T_562 = eq(_T_561, UInt<1>("h00")) @[ifu_aln_ctl.scala 296:59] - node _T_563 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 296:76] - node _T_564 = and(_T_562, _T_563) @[ifu_aln_ctl.scala 296:69] - node _T_565 = bits(_T_564, 0, 0) @[ifu_aln_ctl.scala 296:81] - node _T_566 = bits(f1brend, 0, 0) @[ifu_aln_ctl.scala 296:100] - node _T_567 = bits(f0brend, 0, 0) @[ifu_aln_ctl.scala 296:111] + node _T_559 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 309:35] + node _T_560 = bits(_T_559, 0, 0) @[ifu_aln_ctl.scala 309:45] + node _T_561 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 309:65] + node _T_562 = eq(_T_561, UInt<1>("h00")) @[ifu_aln_ctl.scala 309:59] + node _T_563 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 309:76] + node _T_564 = and(_T_562, _T_563) @[ifu_aln_ctl.scala 309:69] + node _T_565 = bits(_T_564, 0, 0) @[ifu_aln_ctl.scala 309:81] + node _T_566 = bits(f1brend, 0, 0) @[ifu_aln_ctl.scala 309:100] + node _T_567 = bits(f0brend, 0, 0) @[ifu_aln_ctl.scala 309:111] node _T_568 = cat(_T_566, _T_567) @[Cat.scala 29:58] node _T_569 = mux(_T_560, f0brend, UInt<1>("h00")) @[Mux.scala 27:72] node _T_570 = mux(_T_565, _T_568, UInt<1>("h00")) @[Mux.scala 27:72] node _T_571 = or(_T_569, _T_570) @[Mux.scala 27:72] wire alignbrend : UInt<2> @[Mux.scala 27:72] alignbrend <= _T_571 @[Mux.scala 27:72] - node _T_572 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 298:33] - node _T_573 = bits(_T_572, 0, 0) @[ifu_aln_ctl.scala 298:43] - node _T_574 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 298:61] - node _T_575 = eq(_T_574, UInt<1>("h00")) @[ifu_aln_ctl.scala 298:55] - node _T_576 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 298:72] - node _T_577 = and(_T_575, _T_576) @[ifu_aln_ctl.scala 298:65] - node _T_578 = bits(_T_577, 0, 0) @[ifu_aln_ctl.scala 298:77] - node _T_579 = bits(f1pc4, 0, 0) @[ifu_aln_ctl.scala 298:94] - node _T_580 = bits(f0pc4, 0, 0) @[ifu_aln_ctl.scala 298:103] + node _T_572 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 311:33] + node _T_573 = bits(_T_572, 0, 0) @[ifu_aln_ctl.scala 311:43] + node _T_574 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 311:61] + node _T_575 = eq(_T_574, UInt<1>("h00")) @[ifu_aln_ctl.scala 311:55] + node _T_576 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 311:72] + node _T_577 = and(_T_575, _T_576) @[ifu_aln_ctl.scala 311:65] + node _T_578 = bits(_T_577, 0, 0) @[ifu_aln_ctl.scala 311:77] + node _T_579 = bits(f1pc4, 0, 0) @[ifu_aln_ctl.scala 311:94] + node _T_580 = bits(f0pc4, 0, 0) @[ifu_aln_ctl.scala 311:103] node _T_581 = cat(_T_579, _T_580) @[Cat.scala 29:58] node _T_582 = mux(_T_573, f0pc4, UInt<1>("h00")) @[Mux.scala 27:72] node _T_583 = mux(_T_578, _T_581, UInt<1>("h00")) @[Mux.scala 27:72] node _T_584 = or(_T_582, _T_583) @[Mux.scala 27:72] wire alignpc4 : UInt<2> @[Mux.scala 27:72] alignpc4 <= _T_584 @[Mux.scala 27:72] - node _T_585 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 300:33] - node _T_586 = bits(_T_585, 0, 0) @[ifu_aln_ctl.scala 300:43] - node _T_587 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 300:61] - node _T_588 = eq(_T_587, UInt<1>("h00")) @[ifu_aln_ctl.scala 300:55] - node _T_589 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 300:72] - node _T_590 = and(_T_588, _T_589) @[ifu_aln_ctl.scala 300:65] - node _T_591 = bits(_T_590, 0, 0) @[ifu_aln_ctl.scala 300:77] - node _T_592 = bits(f1ret, 0, 0) @[ifu_aln_ctl.scala 300:94] - node _T_593 = bits(f0ret, 0, 0) @[ifu_aln_ctl.scala 300:103] + node _T_585 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 313:33] + node _T_586 = bits(_T_585, 0, 0) @[ifu_aln_ctl.scala 313:43] + node _T_587 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 313:61] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[ifu_aln_ctl.scala 313:55] + node _T_589 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 313:72] + node _T_590 = and(_T_588, _T_589) @[ifu_aln_ctl.scala 313:65] + node _T_591 = bits(_T_590, 0, 0) @[ifu_aln_ctl.scala 313:77] + node _T_592 = bits(f1ret, 0, 0) @[ifu_aln_ctl.scala 313:94] + node _T_593 = bits(f0ret, 0, 0) @[ifu_aln_ctl.scala 313:103] node _T_594 = cat(_T_592, _T_593) @[Cat.scala 29:58] node _T_595 = mux(_T_586, f0ret, UInt<1>("h00")) @[Mux.scala 27:72] node _T_596 = mux(_T_591, _T_594, UInt<1>("h00")) @[Mux.scala 27:72] node _T_597 = or(_T_595, _T_596) @[Mux.scala 27:72] wire alignret : UInt<2> @[Mux.scala 27:72] alignret <= _T_597 @[Mux.scala 27:72] - node _T_598 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 302:33] - node _T_599 = bits(_T_598, 0, 0) @[ifu_aln_ctl.scala 302:43] - node _T_600 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 302:61] - node _T_601 = eq(_T_600, UInt<1>("h00")) @[ifu_aln_ctl.scala 302:55] - node _T_602 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 302:72] - node _T_603 = and(_T_601, _T_602) @[ifu_aln_ctl.scala 302:65] - node _T_604 = bits(_T_603, 0, 0) @[ifu_aln_ctl.scala 302:77] - node _T_605 = bits(f1way, 0, 0) @[ifu_aln_ctl.scala 302:94] - node _T_606 = bits(f0way, 0, 0) @[ifu_aln_ctl.scala 302:103] + node _T_598 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 315:33] + node _T_599 = bits(_T_598, 0, 0) @[ifu_aln_ctl.scala 315:43] + node _T_600 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 315:61] + node _T_601 = eq(_T_600, UInt<1>("h00")) @[ifu_aln_ctl.scala 315:55] + node _T_602 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 315:72] + node _T_603 = and(_T_601, _T_602) @[ifu_aln_ctl.scala 315:65] + node _T_604 = bits(_T_603, 0, 0) @[ifu_aln_ctl.scala 315:77] + node _T_605 = bits(f1way, 0, 0) @[ifu_aln_ctl.scala 315:94] + node _T_606 = bits(f0way, 0, 0) @[ifu_aln_ctl.scala 315:103] node _T_607 = cat(_T_605, _T_606) @[Cat.scala 29:58] node _T_608 = mux(_T_599, f0way, UInt<1>("h00")) @[Mux.scala 27:72] node _T_609 = mux(_T_604, _T_607, UInt<1>("h00")) @[Mux.scala 27:72] node _T_610 = or(_T_608, _T_609) @[Mux.scala 27:72] wire alignway : UInt<2> @[Mux.scala 27:72] alignway <= _T_610 @[Mux.scala 27:72] - node _T_611 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 304:35] - node _T_612 = bits(_T_611, 0, 0) @[ifu_aln_ctl.scala 304:45] - node _T_613 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 304:65] - node _T_614 = eq(_T_613, UInt<1>("h00")) @[ifu_aln_ctl.scala 304:59] - node _T_615 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 304:76] - node _T_616 = and(_T_614, _T_615) @[ifu_aln_ctl.scala 304:69] - node _T_617 = bits(_T_616, 0, 0) @[ifu_aln_ctl.scala 304:81] - node _T_618 = bits(f1hist1, 0, 0) @[ifu_aln_ctl.scala 304:100] - node _T_619 = bits(f0hist1, 0, 0) @[ifu_aln_ctl.scala 304:111] + node _T_611 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 317:35] + node _T_612 = bits(_T_611, 0, 0) @[ifu_aln_ctl.scala 317:45] + node _T_613 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 317:65] + node _T_614 = eq(_T_613, UInt<1>("h00")) @[ifu_aln_ctl.scala 317:59] + node _T_615 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 317:76] + node _T_616 = and(_T_614, _T_615) @[ifu_aln_ctl.scala 317:69] + node _T_617 = bits(_T_616, 0, 0) @[ifu_aln_ctl.scala 317:81] + node _T_618 = bits(f1hist1, 0, 0) @[ifu_aln_ctl.scala 317:100] + node _T_619 = bits(f0hist1, 0, 0) @[ifu_aln_ctl.scala 317:111] node _T_620 = cat(_T_618, _T_619) @[Cat.scala 29:58] node _T_621 = mux(_T_612, f0hist1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_622 = mux(_T_617, _T_620, UInt<1>("h00")) @[Mux.scala 27:72] node _T_623 = or(_T_621, _T_622) @[Mux.scala 27:72] wire alignhist1 : UInt<2> @[Mux.scala 27:72] alignhist1 <= _T_623 @[Mux.scala 27:72] - node _T_624 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 306:35] - node _T_625 = bits(_T_624, 0, 0) @[ifu_aln_ctl.scala 306:45] - node _T_626 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 306:65] - node _T_627 = eq(_T_626, UInt<1>("h00")) @[ifu_aln_ctl.scala 306:59] - node _T_628 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 306:76] - node _T_629 = and(_T_627, _T_628) @[ifu_aln_ctl.scala 306:69] - node _T_630 = bits(_T_629, 0, 0) @[ifu_aln_ctl.scala 306:81] - node _T_631 = bits(f1hist0, 0, 0) @[ifu_aln_ctl.scala 306:100] - node _T_632 = bits(f0hist0, 0, 0) @[ifu_aln_ctl.scala 306:111] + node _T_624 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 319:35] + node _T_625 = bits(_T_624, 0, 0) @[ifu_aln_ctl.scala 319:45] + node _T_626 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 319:65] + node _T_627 = eq(_T_626, UInt<1>("h00")) @[ifu_aln_ctl.scala 319:59] + node _T_628 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 319:76] + node _T_629 = and(_T_627, _T_628) @[ifu_aln_ctl.scala 319:69] + node _T_630 = bits(_T_629, 0, 0) @[ifu_aln_ctl.scala 319:81] + node _T_631 = bits(f1hist0, 0, 0) @[ifu_aln_ctl.scala 319:100] + node _T_632 = bits(f0hist0, 0, 0) @[ifu_aln_ctl.scala 319:111] node _T_633 = cat(_T_631, _T_632) @[Cat.scala 29:58] node _T_634 = mux(_T_625, f0hist0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_635 = mux(_T_630, _T_633, UInt<1>("h00")) @[Mux.scala 27:72] node _T_636 = or(_T_634, _T_635) @[Mux.scala 27:72] wire alignhist0 : UInt<2> @[Mux.scala 27:72] alignhist0 <= _T_636 @[Mux.scala 27:72] - node _T_637 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 308:27] - node _T_638 = eq(_T_637, UInt<1>("h00")) @[ifu_aln_ctl.scala 308:21] - node _T_639 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 308:38] - node alignfromf1 = and(_T_638, _T_639) @[ifu_aln_ctl.scala 308:31] - node _T_640 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 310:33] - node _T_641 = bits(_T_640, 0, 0) @[ifu_aln_ctl.scala 310:43] - node _T_642 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 310:67] - node _T_643 = eq(_T_642, UInt<1>("h00")) @[ifu_aln_ctl.scala 310:61] - node _T_644 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 310:78] - node _T_645 = and(_T_643, _T_644) @[ifu_aln_ctl.scala 310:71] - node _T_646 = bits(_T_645, 0, 0) @[ifu_aln_ctl.scala 310:83] + node _T_637 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 321:27] + node _T_638 = eq(_T_637, UInt<1>("h00")) @[ifu_aln_ctl.scala 321:21] + node _T_639 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 321:38] + node alignfromf1 = and(_T_638, _T_639) @[ifu_aln_ctl.scala 321:31] + node _T_640 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 323:33] + node _T_641 = bits(_T_640, 0, 0) @[ifu_aln_ctl.scala 323:43] + node _T_642 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 323:67] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[ifu_aln_ctl.scala 323:61] + node _T_644 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 323:78] + node _T_645 = and(_T_643, _T_644) @[ifu_aln_ctl.scala 323:71] + node _T_646 = bits(_T_645, 0, 0) @[ifu_aln_ctl.scala 323:83] node _T_647 = mux(_T_641, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_648 = mux(_T_646, f1pc, UInt<1>("h00")) @[Mux.scala 27:72] node _T_649 = or(_T_647, _T_648) @[Mux.scala 27:72] wire secondpc : UInt @[Mux.scala 27:72] secondpc <= _T_649 @[Mux.scala 27:72] - io.dec_aln.aln_ib.ifu_i0_pc <= f0pc @[ifu_aln_ctl.scala 312:31] - io.dec_aln.aln_ib.ifu_i0_pc4 <= first4B @[ifu_aln_ctl.scala 316:32] - node _T_650 = bits(aligndata, 15, 0) @[ifu_aln_ctl.scala 318:47] - io.dec_aln.aln_dec.ifu_i0_cinst <= _T_650 @[ifu_aln_ctl.scala 318:35] - node _T_651 = bits(aligndata, 1, 0) @[ifu_aln_ctl.scala 320:23] - node _T_652 = eq(_T_651, UInt<2>("h03")) @[ifu_aln_ctl.scala 320:29] - first4B <= _T_652 @[ifu_aln_ctl.scala 320:11] - node first2B = not(first4B) @[ifu_aln_ctl.scala 322:17] - node _T_653 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 324:55] - node _T_654 = bits(alignval, 1, 1) @[ifu_aln_ctl.scala 324:73] - node _T_655 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 324:86] - node _T_656 = bits(alignval, 0, 0) @[ifu_aln_ctl.scala 324:104] + io.dec_aln.aln_ib.ifu_i0_pc <= f0pc @[ifu_aln_ctl.scala 325:31] + io.dec_aln.aln_ib.ifu_i0_pc4 <= first4B @[ifu_aln_ctl.scala 329:32] + node _T_650 = bits(aligndata, 15, 0) @[ifu_aln_ctl.scala 331:47] + io.dec_aln.aln_dec.ifu_i0_cinst <= _T_650 @[ifu_aln_ctl.scala 331:35] + node _T_651 = bits(aligndata, 1, 0) @[ifu_aln_ctl.scala 334:23] + node _T_652 = eq(_T_651, UInt<2>("h03")) @[ifu_aln_ctl.scala 334:29] + first4B <= _T_652 @[ifu_aln_ctl.scala 334:11] + node first2B = not(first4B) @[ifu_aln_ctl.scala 336:17] + node _T_653 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 338:55] + node _T_654 = bits(alignval, 1, 1) @[ifu_aln_ctl.scala 338:73] + node _T_655 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 338:86] + node _T_656 = bits(alignval, 0, 0) @[ifu_aln_ctl.scala 338:104] node _T_657 = mux(_T_653, _T_654, UInt<1>("h00")) @[Mux.scala 27:72] node _T_658 = mux(_T_655, _T_656, UInt<1>("h00")) @[Mux.scala 27:72] node _T_659 = or(_T_657, _T_658) @[Mux.scala 27:72] wire _T_660 : UInt<1> @[Mux.scala 27:72] _T_660 <= _T_659 @[Mux.scala 27:72] - io.dec_aln.aln_ib.ifu_i0_valid <= _T_660 @[ifu_aln_ctl.scala 324:34] - node _T_661 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 326:54] - node _T_662 = orr(alignicaf) @[ifu_aln_ctl.scala 326:74] - node _T_663 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 326:87] - node _T_664 = bits(alignicaf, 0, 0) @[ifu_aln_ctl.scala 326:106] + io.dec_aln.aln_ib.ifu_i0_valid <= _T_660 @[ifu_aln_ctl.scala 338:34] + node _T_661 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 340:54] + node _T_662 = orr(alignicaf) @[ifu_aln_ctl.scala 340:74] + node _T_663 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 340:87] + node _T_664 = bits(alignicaf, 0, 0) @[ifu_aln_ctl.scala 340:106] node _T_665 = mux(_T_661, _T_662, UInt<1>("h00")) @[Mux.scala 27:72] node _T_666 = mux(_T_663, _T_664, UInt<1>("h00")) @[Mux.scala 27:72] node _T_667 = or(_T_665, _T_666) @[Mux.scala 27:72] wire _T_668 : UInt<1> @[Mux.scala 27:72] _T_668 <= _T_667 @[Mux.scala 27:72] - io.dec_aln.aln_ib.ifu_i0_icaf <= _T_668 @[ifu_aln_ctl.scala 326:33] - node _T_669 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 328:62] - node _T_670 = eq(_T_669, UInt<1>("h00")) @[ifu_aln_ctl.scala 328:56] - node _T_671 = and(first4B, _T_670) @[ifu_aln_ctl.scala 328:54] - node _T_672 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 328:73] - node _T_673 = and(_T_671, _T_672) @[ifu_aln_ctl.scala 328:66] - node _T_674 = bits(alignicaf, 0, 0) @[ifu_aln_ctl.scala 328:89] - node _T_675 = eq(_T_674, UInt<1>("h00")) @[ifu_aln_ctl.scala 328:79] - node _T_676 = and(_T_673, _T_675) @[ifu_aln_ctl.scala 328:77] - node _T_677 = bits(aligndbecc, 0, 0) @[ifu_aln_ctl.scala 328:106] - node _T_678 = eq(_T_677, UInt<1>("h00")) @[ifu_aln_ctl.scala 328:95] - node _T_679 = and(_T_676, _T_678) @[ifu_aln_ctl.scala 328:93] - node _T_680 = bits(_T_679, 0, 0) @[ifu_aln_ctl.scala 328:111] - node _T_681 = mux(_T_680, f1ictype, f0ictype) @[ifu_aln_ctl.scala 328:44] - io.dec_aln.aln_ib.ifu_i0_icaf_type <= _T_681 @[ifu_aln_ctl.scala 328:38] - node _T_682 = bits(alignicaf, 1, 1) @[ifu_aln_ctl.scala 330:27] - node _T_683 = bits(aligndbecc, 1, 1) @[ifu_aln_ctl.scala 330:43] - node icaf_eff = or(_T_682, _T_683) @[ifu_aln_ctl.scala 330:31] - node _T_684 = and(first4B, icaf_eff) @[ifu_aln_ctl.scala 332:47] - node _T_685 = and(_T_684, alignfromf1) @[ifu_aln_ctl.scala 332:58] - io.dec_aln.aln_ib.ifu_i0_icaf_f1 <= _T_685 @[ifu_aln_ctl.scala 332:36] - node _T_686 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 334:55] - node _T_687 = orr(aligndbecc) @[ifu_aln_ctl.scala 334:74] - node _T_688 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 334:87] - node _T_689 = bits(aligndbecc, 0, 0) @[ifu_aln_ctl.scala 334:105] + io.dec_aln.aln_ib.ifu_i0_icaf <= _T_668 @[ifu_aln_ctl.scala 340:33] + node _T_669 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 342:62] + node _T_670 = eq(_T_669, UInt<1>("h00")) @[ifu_aln_ctl.scala 342:56] + node _T_671 = and(first4B, _T_670) @[ifu_aln_ctl.scala 342:54] + node _T_672 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 342:73] + node _T_673 = and(_T_671, _T_672) @[ifu_aln_ctl.scala 342:66] + node _T_674 = bits(alignicaf, 0, 0) @[ifu_aln_ctl.scala 342:89] + node _T_675 = eq(_T_674, UInt<1>("h00")) @[ifu_aln_ctl.scala 342:79] + node _T_676 = and(_T_673, _T_675) @[ifu_aln_ctl.scala 342:77] + node _T_677 = bits(aligndbecc, 0, 0) @[ifu_aln_ctl.scala 342:106] + node _T_678 = eq(_T_677, UInt<1>("h00")) @[ifu_aln_ctl.scala 342:95] + node _T_679 = and(_T_676, _T_678) @[ifu_aln_ctl.scala 342:93] + node _T_680 = bits(_T_679, 0, 0) @[ifu_aln_ctl.scala 342:111] + node _T_681 = mux(_T_680, f1ictype, f0ictype) @[ifu_aln_ctl.scala 342:44] + io.dec_aln.aln_ib.ifu_i0_icaf_type <= _T_681 @[ifu_aln_ctl.scala 342:38] + node _T_682 = bits(alignicaf, 1, 1) @[ifu_aln_ctl.scala 344:27] + node _T_683 = bits(aligndbecc, 1, 1) @[ifu_aln_ctl.scala 344:43] + node icaf_eff = or(_T_682, _T_683) @[ifu_aln_ctl.scala 344:31] + node _T_684 = and(first4B, icaf_eff) @[ifu_aln_ctl.scala 346:47] + node _T_685 = and(_T_684, alignfromf1) @[ifu_aln_ctl.scala 346:58] + io.dec_aln.aln_ib.ifu_i0_icaf_f1 <= _T_685 @[ifu_aln_ctl.scala 346:36] + node _T_686 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 348:55] + node _T_687 = orr(aligndbecc) @[ifu_aln_ctl.scala 348:74] + node _T_688 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 348:87] + node _T_689 = bits(aligndbecc, 0, 0) @[ifu_aln_ctl.scala 348:105] node _T_690 = mux(_T_686, _T_687, UInt<1>("h00")) @[Mux.scala 27:72] node _T_691 = mux(_T_688, _T_689, UInt<1>("h00")) @[Mux.scala 27:72] node _T_692 = or(_T_690, _T_691) @[Mux.scala 27:72] wire _T_693 : UInt<1> @[Mux.scala 27:72] _T_693 <= _T_692 @[Mux.scala 27:72] - io.dec_aln.aln_ib.ifu_i0_dbecc <= _T_693 @[ifu_aln_ctl.scala 334:34] - inst decompressed of ifu_compress_ctl @[ifu_aln_ctl.scala 338:28] + io.dec_aln.aln_ib.ifu_i0_dbecc <= _T_693 @[ifu_aln_ctl.scala 348:34] + inst decompressed of ifu_compress_ctl @[ifu_aln_ctl.scala 352:28] decompressed.clock <= clock decompressed.reset <= reset - node _T_694 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 340:55] - node _T_695 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 340:81] + node _T_694 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 354:55] + node _T_695 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 354:81] node _T_696 = mux(_T_694, aligndata, UInt<1>("h00")) @[Mux.scala 27:72] node _T_697 = mux(_T_695, decompressed.io.dout, UInt<1>("h00")) @[Mux.scala 27:72] node _T_698 = or(_T_696, _T_697) @[Mux.scala 27:72] wire _T_699 : UInt<32> @[Mux.scala 27:72] _T_699 <= _T_698 @[Mux.scala 27:72] - io.dec_aln.aln_ib.ifu_i0_instr <= _T_699 @[ifu_aln_ctl.scala 340:34] + io.dec_aln.aln_ib.ifu_i0_instr <= _T_699 @[ifu_aln_ctl.scala 354:34] node _T_700 = bits(f0pc, 8, 1) @[lib.scala 35:13] node _T_701 = bits(f0pc, 16, 9) @[lib.scala 35:51] node _T_702 = xor(_T_700, _T_701) @[lib.scala 35:47] @@ -63619,114 +63619,114 @@ circuit quasar_wrapper : _T_716[2] <= _T_715 @[lib.scala 26:24] node _T_717 = xor(_T_716[0], _T_716[1]) @[lib.scala 26:111] node secondbrtag_hash = xor(_T_717, _T_716[2]) @[lib.scala 26:111] - node _T_718 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 350:57] - node _T_719 = and(first2B, _T_718) @[ifu_aln_ctl.scala 350:45] - node _T_720 = bits(alignbrend, 1, 1) @[ifu_aln_ctl.scala 350:85] - node _T_721 = and(first4B, _T_720) @[ifu_aln_ctl.scala 350:73] - node _T_722 = or(_T_719, _T_721) @[ifu_aln_ctl.scala 350:62] - node _T_723 = bits(alignval, 1, 1) @[ifu_aln_ctl.scala 350:111] - node _T_724 = and(first4B, _T_723) @[ifu_aln_ctl.scala 350:101] - node _T_725 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 350:127] - node _T_726 = and(_T_724, _T_725) @[ifu_aln_ctl.scala 350:115] - node _T_727 = or(_T_722, _T_726) @[ifu_aln_ctl.scala 350:90] - io.dec_aln.aln_ib.i0_brp.valid <= _T_727 @[ifu_aln_ctl.scala 350:34] - node _T_728 = bits(alignret, 0, 0) @[ifu_aln_ctl.scala 352:59] - node _T_729 = and(first2B, _T_728) @[ifu_aln_ctl.scala 352:49] - node _T_730 = bits(alignret, 1, 1) @[ifu_aln_ctl.scala 352:85] - node _T_731 = and(first4B, _T_730) @[ifu_aln_ctl.scala 352:75] - node _T_732 = or(_T_729, _T_731) @[ifu_aln_ctl.scala 352:64] - io.dec_aln.aln_ib.i0_brp.bits.ret <= _T_732 @[ifu_aln_ctl.scala 352:37] - node _T_733 = bits(alignpc4, 0, 0) @[ifu_aln_ctl.scala 354:39] - node _T_734 = and(first2B, _T_733) @[ifu_aln_ctl.scala 354:29] - node _T_735 = bits(alignpc4, 1, 1) @[ifu_aln_ctl.scala 354:65] - node _T_736 = and(first4B, _T_735) @[ifu_aln_ctl.scala 354:55] - node i0_brp_pc4 = or(_T_734, _T_736) @[ifu_aln_ctl.scala 354:44] - node _T_737 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 356:65] - node _T_738 = or(first2B, _T_737) @[ifu_aln_ctl.scala 356:53] - node _T_739 = bits(_T_738, 0, 0) @[ifu_aln_ctl.scala 356:70] - node _T_740 = bits(alignway, 0, 0) @[ifu_aln_ctl.scala 356:86] - node _T_741 = bits(alignway, 1, 1) @[ifu_aln_ctl.scala 356:100] - node _T_742 = mux(_T_739, _T_740, _T_741) @[ifu_aln_ctl.scala 356:43] - io.dec_aln.aln_ib.i0_brp.bits.way <= _T_742 @[ifu_aln_ctl.scala 356:37] - node _T_743 = bits(alignhist1, 0, 0) @[ifu_aln_ctl.scala 358:66] - node _T_744 = and(first2B, _T_743) @[ifu_aln_ctl.scala 358:54] - node _T_745 = bits(alignhist1, 1, 1) @[ifu_aln_ctl.scala 358:94] - node _T_746 = and(first4B, _T_745) @[ifu_aln_ctl.scala 358:82] - node _T_747 = or(_T_744, _T_746) @[ifu_aln_ctl.scala 358:71] - node _T_748 = bits(alignhist0, 0, 0) @[ifu_aln_ctl.scala 359:26] - node _T_749 = and(first2B, _T_748) @[ifu_aln_ctl.scala 359:14] - node _T_750 = bits(alignhist0, 1, 1) @[ifu_aln_ctl.scala 359:54] - node _T_751 = and(first4B, _T_750) @[ifu_aln_ctl.scala 359:42] - node _T_752 = or(_T_749, _T_751) @[ifu_aln_ctl.scala 359:31] + node _T_718 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 365:57] + node _T_719 = and(first2B, _T_718) @[ifu_aln_ctl.scala 365:45] + node _T_720 = bits(alignbrend, 1, 1) @[ifu_aln_ctl.scala 365:85] + node _T_721 = and(first4B, _T_720) @[ifu_aln_ctl.scala 365:73] + node _T_722 = or(_T_719, _T_721) @[ifu_aln_ctl.scala 365:62] + node _T_723 = bits(alignval, 1, 1) @[ifu_aln_ctl.scala 365:111] + node _T_724 = and(first4B, _T_723) @[ifu_aln_ctl.scala 365:101] + node _T_725 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 365:127] + node _T_726 = and(_T_724, _T_725) @[ifu_aln_ctl.scala 365:115] + node _T_727 = or(_T_722, _T_726) @[ifu_aln_ctl.scala 365:90] + io.dec_aln.aln_ib.i0_brp.valid <= _T_727 @[ifu_aln_ctl.scala 365:34] + node _T_728 = bits(alignret, 0, 0) @[ifu_aln_ctl.scala 367:59] + node _T_729 = and(first2B, _T_728) @[ifu_aln_ctl.scala 367:49] + node _T_730 = bits(alignret, 1, 1) @[ifu_aln_ctl.scala 367:85] + node _T_731 = and(first4B, _T_730) @[ifu_aln_ctl.scala 367:75] + node _T_732 = or(_T_729, _T_731) @[ifu_aln_ctl.scala 367:64] + io.dec_aln.aln_ib.i0_brp.bits.ret <= _T_732 @[ifu_aln_ctl.scala 367:37] + node _T_733 = bits(alignpc4, 0, 0) @[ifu_aln_ctl.scala 369:39] + node _T_734 = and(first2B, _T_733) @[ifu_aln_ctl.scala 369:29] + node _T_735 = bits(alignpc4, 1, 1) @[ifu_aln_ctl.scala 369:65] + node _T_736 = and(first4B, _T_735) @[ifu_aln_ctl.scala 369:55] + node i0_brp_pc4 = or(_T_734, _T_736) @[ifu_aln_ctl.scala 369:44] + node _T_737 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 371:65] + node _T_738 = or(first2B, _T_737) @[ifu_aln_ctl.scala 371:53] + node _T_739 = bits(_T_738, 0, 0) @[ifu_aln_ctl.scala 371:70] + node _T_740 = bits(alignway, 0, 0) @[ifu_aln_ctl.scala 371:86] + node _T_741 = bits(alignway, 1, 1) @[ifu_aln_ctl.scala 371:100] + node _T_742 = mux(_T_739, _T_740, _T_741) @[ifu_aln_ctl.scala 371:43] + io.dec_aln.aln_ib.i0_brp.bits.way <= _T_742 @[ifu_aln_ctl.scala 371:37] + node _T_743 = bits(alignhist1, 0, 0) @[ifu_aln_ctl.scala 373:66] + node _T_744 = and(first2B, _T_743) @[ifu_aln_ctl.scala 373:54] + node _T_745 = bits(alignhist1, 1, 1) @[ifu_aln_ctl.scala 373:94] + node _T_746 = and(first4B, _T_745) @[ifu_aln_ctl.scala 373:82] + node _T_747 = or(_T_744, _T_746) @[ifu_aln_ctl.scala 373:71] + node _T_748 = bits(alignhist0, 0, 0) @[ifu_aln_ctl.scala 374:26] + node _T_749 = and(first2B, _T_748) @[ifu_aln_ctl.scala 374:14] + node _T_750 = bits(alignhist0, 1, 1) @[ifu_aln_ctl.scala 374:54] + node _T_751 = and(first4B, _T_750) @[ifu_aln_ctl.scala 374:42] + node _T_752 = or(_T_749, _T_751) @[ifu_aln_ctl.scala 374:31] node _T_753 = cat(_T_747, _T_752) @[Cat.scala 29:58] - io.dec_aln.aln_ib.i0_brp.bits.hist <= _T_753 @[ifu_aln_ctl.scala 358:38] - node i0_ends_f1 = and(first4B, alignfromf1) @[ifu_aln_ctl.scala 361:28] - node _T_754 = bits(i0_ends_f1, 0, 0) @[ifu_aln_ctl.scala 362:59] - node _T_755 = mux(_T_754, f1poffset, f0poffset) @[ifu_aln_ctl.scala 362:47] - io.dec_aln.aln_ib.i0_brp.bits.toffset <= _T_755 @[ifu_aln_ctl.scala 362:41] - node _T_756 = bits(i0_ends_f1, 0, 0) @[ifu_aln_ctl.scala 364:57] - node _T_757 = mux(_T_756, f1prett, f0prett) @[ifu_aln_ctl.scala 364:45] - io.dec_aln.aln_ib.i0_brp.bits.prett <= _T_757 @[ifu_aln_ctl.scala 364:39] - node _T_758 = bits(alignval, 1, 1) @[ifu_aln_ctl.scala 366:71] - node _T_759 = and(first4B, _T_758) @[ifu_aln_ctl.scala 366:61] - node _T_760 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 366:87] - node _T_761 = and(_T_759, _T_760) @[ifu_aln_ctl.scala 366:75] - io.dec_aln.aln_ib.i0_brp.bits.br_start_error <= _T_761 @[ifu_aln_ctl.scala 366:49] - node _T_762 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 368:77] - node _T_763 = or(first2B, _T_762) @[ifu_aln_ctl.scala 368:65] - node _T_764 = bits(_T_763, 0, 0) @[ifu_aln_ctl.scala 368:82] - node _T_765 = bits(f0pc, 0, 0) @[ifu_aln_ctl.scala 368:97] - node _T_766 = bits(secondpc, 0, 0) @[ifu_aln_ctl.scala 368:110] - node _T_767 = mux(_T_764, _T_765, _T_766) @[ifu_aln_ctl.scala 368:55] - io.dec_aln.aln_ib.i0_brp.bits.bank <= _T_767 @[ifu_aln_ctl.scala 368:49] - node _T_768 = and(io.dec_aln.aln_ib.i0_brp.valid, i0_brp_pc4) @[ifu_aln_ctl.scala 370:77] - node _T_769 = and(_T_768, first2B) @[ifu_aln_ctl.scala 370:91] - node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[ifu_aln_ctl.scala 370:139] - node _T_771 = and(io.dec_aln.aln_ib.i0_brp.valid, _T_770) @[ifu_aln_ctl.scala 370:137] - node _T_772 = and(_T_771, first4B) @[ifu_aln_ctl.scala 370:151] - node _T_773 = or(_T_769, _T_772) @[ifu_aln_ctl.scala 370:103] - io.dec_aln.aln_ib.i0_brp.bits.br_error <= _T_773 @[ifu_aln_ctl.scala 370:42] - node _T_774 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 372:65] - node _T_775 = or(first2B, _T_774) @[ifu_aln_ctl.scala 372:53] - node _T_776 = bits(_T_775, 0, 0) @[ifu_aln_ctl.scala 372:70] - node _T_777 = mux(_T_776, firstpc_hash, secondpc_hash) @[ifu_aln_ctl.scala 372:43] - io.dec_aln.aln_ib.ifu_i0_bp_index <= _T_777 @[ifu_aln_ctl.scala 372:37] - node _T_778 = and(first4B, alignfromf1) @[ifu_aln_ctl.scala 374:52] - node _T_779 = bits(_T_778, 0, 0) @[ifu_aln_ctl.scala 374:67] - node _T_780 = mux(_T_779, f1fghr, f0fghr) @[ifu_aln_ctl.scala 374:42] - io.dec_aln.aln_ib.ifu_i0_bp_fghr <= _T_780 @[ifu_aln_ctl.scala 374:36] - node _T_781 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 376:64] - node _T_782 = or(first2B, _T_781) @[ifu_aln_ctl.scala 376:52] - node _T_783 = bits(_T_782, 0, 0) @[ifu_aln_ctl.scala 376:69] - node _T_784 = mux(_T_783, firstbrtag_hash, secondbrtag_hash) @[ifu_aln_ctl.scala 376:42] - io.dec_aln.aln_ib.ifu_i0_bp_btag <= _T_784 @[ifu_aln_ctl.scala 376:36] - decompressed.io.din <= aligndata @[ifu_aln_ctl.scala 378:23] - node _T_785 = not(error_stall) @[ifu_aln_ctl.scala 380:55] - node i0_shift = and(io.dec_aln.aln_dec.dec_i0_decode_d, _T_785) @[ifu_aln_ctl.scala 380:53] - io.dec_aln.ifu_pmu_instr_aligned <= i0_shift @[ifu_aln_ctl.scala 382:36] - node _T_786 = and(i0_shift, first2B) @[ifu_aln_ctl.scala 384:24] - shift_2B <= _T_786 @[ifu_aln_ctl.scala 384:12] - node _T_787 = and(i0_shift, first4B) @[ifu_aln_ctl.scala 385:24] - shift_4B <= _T_787 @[ifu_aln_ctl.scala 385:12] - node _T_788 = bits(shift_2B, 0, 0) @[ifu_aln_ctl.scala 387:37] - node _T_789 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 387:52] - node _T_790 = bits(shift_4B, 0, 0) @[ifu_aln_ctl.scala 387:66] - node _T_791 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 387:82] - node _T_792 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 387:94] - node _T_793 = eq(_T_792, UInt<1>("h00")) @[ifu_aln_ctl.scala 387:88] - node _T_794 = and(_T_791, _T_793) @[ifu_aln_ctl.scala 387:86] + io.dec_aln.aln_ib.i0_brp.bits.hist <= _T_753 @[ifu_aln_ctl.scala 373:38] + node i0_ends_f1 = and(first4B, alignfromf1) @[ifu_aln_ctl.scala 376:28] + node _T_754 = bits(i0_ends_f1, 0, 0) @[ifu_aln_ctl.scala 377:59] + node _T_755 = mux(_T_754, f1poffset, f0poffset) @[ifu_aln_ctl.scala 377:47] + io.dec_aln.aln_ib.i0_brp.bits.toffset <= _T_755 @[ifu_aln_ctl.scala 377:41] + node _T_756 = bits(i0_ends_f1, 0, 0) @[ifu_aln_ctl.scala 379:57] + node _T_757 = mux(_T_756, f1prett, f0prett) @[ifu_aln_ctl.scala 379:45] + io.dec_aln.aln_ib.i0_brp.bits.prett <= _T_757 @[ifu_aln_ctl.scala 379:39] + node _T_758 = bits(alignval, 1, 1) @[ifu_aln_ctl.scala 381:71] + node _T_759 = and(first4B, _T_758) @[ifu_aln_ctl.scala 381:61] + node _T_760 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 381:87] + node _T_761 = and(_T_759, _T_760) @[ifu_aln_ctl.scala 381:75] + io.dec_aln.aln_ib.i0_brp.bits.br_start_error <= _T_761 @[ifu_aln_ctl.scala 381:49] + node _T_762 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 383:77] + node _T_763 = or(first2B, _T_762) @[ifu_aln_ctl.scala 383:65] + node _T_764 = bits(_T_763, 0, 0) @[ifu_aln_ctl.scala 383:82] + node _T_765 = bits(f0pc, 0, 0) @[ifu_aln_ctl.scala 383:97] + node _T_766 = bits(secondpc, 0, 0) @[ifu_aln_ctl.scala 383:110] + node _T_767 = mux(_T_764, _T_765, _T_766) @[ifu_aln_ctl.scala 383:55] + io.dec_aln.aln_ib.i0_brp.bits.bank <= _T_767 @[ifu_aln_ctl.scala 383:49] + node _T_768 = and(io.dec_aln.aln_ib.i0_brp.valid, i0_brp_pc4) @[ifu_aln_ctl.scala 385:77] + node _T_769 = and(_T_768, first2B) @[ifu_aln_ctl.scala 385:91] + node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[ifu_aln_ctl.scala 385:139] + node _T_771 = and(io.dec_aln.aln_ib.i0_brp.valid, _T_770) @[ifu_aln_ctl.scala 385:137] + node _T_772 = and(_T_771, first4B) @[ifu_aln_ctl.scala 385:151] + node _T_773 = or(_T_769, _T_772) @[ifu_aln_ctl.scala 385:103] + io.dec_aln.aln_ib.i0_brp.bits.br_error <= _T_773 @[ifu_aln_ctl.scala 385:42] + node _T_774 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 387:65] + node _T_775 = or(first2B, _T_774) @[ifu_aln_ctl.scala 387:53] + node _T_776 = bits(_T_775, 0, 0) @[ifu_aln_ctl.scala 387:70] + node _T_777 = mux(_T_776, firstpc_hash, secondpc_hash) @[ifu_aln_ctl.scala 387:43] + io.dec_aln.aln_ib.ifu_i0_bp_index <= _T_777 @[ifu_aln_ctl.scala 387:37] + node _T_778 = and(first4B, alignfromf1) @[ifu_aln_ctl.scala 389:52] + node _T_779 = bits(_T_778, 0, 0) @[ifu_aln_ctl.scala 389:67] + node _T_780 = mux(_T_779, f1fghr, f0fghr) @[ifu_aln_ctl.scala 389:42] + io.dec_aln.aln_ib.ifu_i0_bp_fghr <= _T_780 @[ifu_aln_ctl.scala 389:36] + node _T_781 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 391:64] + node _T_782 = or(first2B, _T_781) @[ifu_aln_ctl.scala 391:52] + node _T_783 = bits(_T_782, 0, 0) @[ifu_aln_ctl.scala 391:69] + node _T_784 = mux(_T_783, firstbrtag_hash, secondbrtag_hash) @[ifu_aln_ctl.scala 391:42] + io.dec_aln.aln_ib.ifu_i0_bp_btag <= _T_784 @[ifu_aln_ctl.scala 391:36] + decompressed.io.din <= aligndata @[ifu_aln_ctl.scala 393:23] + node _T_785 = not(error_stall) @[ifu_aln_ctl.scala 395:55] + node i0_shift = and(io.dec_aln.aln_dec.dec_i0_decode_d, _T_785) @[ifu_aln_ctl.scala 395:53] + io.dec_aln.ifu_pmu_instr_aligned <= i0_shift @[ifu_aln_ctl.scala 397:36] + node _T_786 = and(i0_shift, first2B) @[ifu_aln_ctl.scala 399:24] + shift_2B <= _T_786 @[ifu_aln_ctl.scala 399:12] + node _T_787 = and(i0_shift, first4B) @[ifu_aln_ctl.scala 400:24] + shift_4B <= _T_787 @[ifu_aln_ctl.scala 400:12] + node _T_788 = bits(shift_2B, 0, 0) @[ifu_aln_ctl.scala 402:37] + node _T_789 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 402:52] + node _T_790 = bits(shift_4B, 0, 0) @[ifu_aln_ctl.scala 402:66] + node _T_791 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 402:82] + node _T_792 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 402:94] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[ifu_aln_ctl.scala 402:88] + node _T_794 = and(_T_791, _T_793) @[ifu_aln_ctl.scala 402:86] node _T_795 = mux(_T_788, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] node _T_796 = mux(_T_790, _T_794, UInt<1>("h00")) @[Mux.scala 27:72] node _T_797 = or(_T_795, _T_796) @[Mux.scala 27:72] wire _T_798 : UInt<1> @[Mux.scala 27:72] _T_798 <= _T_797 @[Mux.scala 27:72] - f0_shift_2B <= _T_798 @[ifu_aln_ctl.scala 387:15] - node _T_799 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 388:24] - node _T_800 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 388:36] - node _T_801 = eq(_T_800, UInt<1>("h00")) @[ifu_aln_ctl.scala 388:30] - node _T_802 = and(_T_799, _T_801) @[ifu_aln_ctl.scala 388:28] - node _T_803 = and(_T_802, shift_4B) @[ifu_aln_ctl.scala 388:40] - f1_shift_2B <= _T_803 @[ifu_aln_ctl.scala 388:15] + f0_shift_2B <= _T_798 @[ifu_aln_ctl.scala 402:15] + node _T_799 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 403:24] + node _T_800 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 403:36] + node _T_801 = eq(_T_800, UInt<1>("h00")) @[ifu_aln_ctl.scala 403:30] + node _T_802 = and(_T_799, _T_801) @[ifu_aln_ctl.scala 403:28] + node _T_803 = and(_T_802, shift_4B) @[ifu_aln_ctl.scala 403:40] + f1_shift_2B <= _T_803 @[ifu_aln_ctl.scala 403:15] extmodule gated_latch_660 : output Q : Clock @@ -63820,10 +63820,10 @@ circuit quasar_wrapper : node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 69:69] node _T_12 = and(_T_10, _T_11) @[ifu_ifc_ctl.scala 69:67] node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[ifu_ifc_ctl.scala 69:92] - node _T_13 = bits(io.exu_flush_final, 0, 0) @[ifu_ifc_ctl.scala 72:56] - node _T_14 = bits(sel_last_addr_bf, 0, 0) @[ifu_ifc_ctl.scala 73:26] - node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[ifu_ifc_ctl.scala 74:25] - node _T_16 = bits(sel_next_addr_bf, 0, 0) @[ifu_ifc_ctl.scala 75:26] + node _T_13 = bits(io.exu_flush_final, 0, 0) @[ifu_ifc_ctl.scala 73:56] + node _T_14 = bits(sel_last_addr_bf, 0, 0) @[ifu_ifc_ctl.scala 74:26] + node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[ifu_ifc_ctl.scala 75:25] + node _T_16 = bits(sel_next_addr_bf, 0, 0) @[ifu_ifc_ctl.scala 76:26] node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72] node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72] @@ -63833,121 +63833,121 @@ circuit quasar_wrapper : node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] wire _T_24 : UInt<31> @[Mux.scala 27:72] _T_24 <= _T_23 @[Mux.scala 27:72] - io.ifc_fetch_addr_bf <= _T_24 @[ifu_ifc_ctl.scala 72:24] - node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[ifu_ifc_ctl.scala 77:42] - node _T_26 = add(_T_25, UInt<1>("h01")) @[ifu_ifc_ctl.scala 77:48] - node address_upper = tail(_T_26, 1) @[ifu_ifc_ctl.scala 77:48] - node _T_27 = bits(address_upper, 4, 4) @[ifu_ifc_ctl.scala 78:39] - node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[ifu_ifc_ctl.scala 78:84] - node _T_29 = xor(_T_27, _T_28) @[ifu_ifc_ctl.scala 78:63] - node _T_30 = eq(_T_29, UInt<1>("h00")) @[ifu_ifc_ctl.scala 78:24] - node _T_31 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_ifc_ctl.scala 78:130] - node _T_32 = and(_T_30, _T_31) @[ifu_ifc_ctl.scala 78:109] - fetch_addr_next_0 <= _T_32 @[ifu_ifc_ctl.scala 78:21] + io.ifc_fetch_addr_bf <= _T_24 @[ifu_ifc_ctl.scala 73:24] + node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[ifu_ifc_ctl.scala 78:42] + node _T_26 = add(_T_25, UInt<1>("h01")) @[ifu_ifc_ctl.scala 78:48] + node address_upper = tail(_T_26, 1) @[ifu_ifc_ctl.scala 78:48] + node _T_27 = bits(address_upper, 4, 4) @[ifu_ifc_ctl.scala 79:39] + node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[ifu_ifc_ctl.scala 79:84] + node _T_29 = xor(_T_27, _T_28) @[ifu_ifc_ctl.scala 79:63] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[ifu_ifc_ctl.scala 79:24] + node _T_31 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_ifc_ctl.scala 79:130] + node _T_32 = and(_T_30, _T_31) @[ifu_ifc_ctl.scala 79:109] + fetch_addr_next_0 <= _T_32 @[ifu_ifc_ctl.scala 79:21] node _T_33 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58] - fetch_addr_next <= _T_33 @[ifu_ifc_ctl.scala 80:19] - node _T_34 = not(idle) @[ifu_ifc_ctl.scala 82:30] - io.ifc_fetch_req_bf_raw <= _T_34 @[ifu_ifc_ctl.scala 82:27] - node _T_35 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 84:91] - node _T_36 = eq(_T_35, UInt<1>("h00")) @[ifu_ifc_ctl.scala 84:70] - node _T_37 = and(fb_full_f_ns, _T_36) @[ifu_ifc_ctl.scala 84:68] - node _T_38 = eq(_T_37, UInt<1>("h00")) @[ifu_ifc_ctl.scala 84:53] - node _T_39 = and(io.ifc_fetch_req_bf_raw, _T_38) @[ifu_ifc_ctl.scala 84:51] - node _T_40 = eq(dma_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 85:5] - node _T_41 = and(_T_39, _T_40) @[ifu_ifc_ctl.scala 84:114] - node _T_42 = eq(io.ic_write_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 85:18] - node _T_43 = and(_T_41, _T_42) @[ifu_ifc_ctl.scala 85:16] - node _T_44 = eq(io.dec_ifc.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 85:39] - node _T_45 = and(_T_43, _T_44) @[ifu_ifc_ctl.scala 85:37] - io.ifc_fetch_req_bf <= _T_45 @[ifu_ifc_ctl.scala 84:23] - node _T_46 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 87:37] - fetch_bf_en <= _T_46 @[ifu_ifc_ctl.scala 87:15] - node _T_47 = eq(io.ic_hit_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 89:34] - node _T_48 = and(io.ifc_fetch_req_f, _T_47) @[ifu_ifc_ctl.scala 89:32] - node _T_49 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 89:49] - node _T_50 = and(_T_48, _T_49) @[ifu_ifc_ctl.scala 89:47] - miss_f <= _T_50 @[ifu_ifc_ctl.scala 89:10] - node _T_51 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[ifu_ifc_ctl.scala 91:39] - node _T_52 = eq(dma_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 91:63] - node _T_53 = and(_T_51, _T_52) @[ifu_ifc_ctl.scala 91:61] - node _T_54 = eq(miss_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 91:76] - node _T_55 = and(_T_53, _T_54) @[ifu_ifc_ctl.scala 91:74] - node _T_56 = eq(miss_a, UInt<1>("h00")) @[ifu_ifc_ctl.scala 91:86] - node _T_57 = and(_T_55, _T_56) @[ifu_ifc_ctl.scala 91:84] - mb_empty_mod <= _T_57 @[ifu_ifc_ctl.scala 91:16] - node _T_58 = and(io.exu_flush_final, io.dec_ifc.dec_tlu_flush_noredir_wb) @[ifu_ifc_ctl.scala 93:35] - goto_idle <= _T_58 @[ifu_ifc_ctl.scala 93:13] - node _T_59 = eq(io.dec_ifc.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 95:38] - node _T_60 = and(io.exu_flush_final, _T_59) @[ifu_ifc_ctl.scala 95:36] - node _T_61 = and(_T_60, idle) @[ifu_ifc_ctl.scala 95:75] - leave_idle <= _T_61 @[ifu_ifc_ctl.scala 95:14] - node _T_62 = bits(state, 1, 1) @[ifu_ifc_ctl.scala 97:29] - node _T_63 = eq(_T_62, UInt<1>("h00")) @[ifu_ifc_ctl.scala 97:23] - node _T_64 = bits(state, 0, 0) @[ifu_ifc_ctl.scala 97:40] - node _T_65 = and(_T_63, _T_64) @[ifu_ifc_ctl.scala 97:33] - node _T_66 = and(_T_65, miss_f) @[ifu_ifc_ctl.scala 97:44] - node _T_67 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 97:55] - node _T_68 = and(_T_66, _T_67) @[ifu_ifc_ctl.scala 97:53] - node _T_69 = bits(state, 1, 1) @[ifu_ifc_ctl.scala 98:11] - node _T_70 = eq(mb_empty_mod, UInt<1>("h00")) @[ifu_ifc_ctl.scala 98:17] - node _T_71 = and(_T_69, _T_70) @[ifu_ifc_ctl.scala 98:15] - node _T_72 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 98:33] - node _T_73 = and(_T_71, _T_72) @[ifu_ifc_ctl.scala 98:31] - node next_state_1 = or(_T_68, _T_73) @[ifu_ifc_ctl.scala 97:67] - node _T_74 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 100:23] - node _T_75 = and(_T_74, leave_idle) @[ifu_ifc_ctl.scala 100:34] - node _T_76 = bits(state, 0, 0) @[ifu_ifc_ctl.scala 100:56] - node _T_77 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 100:62] - node _T_78 = and(_T_76, _T_77) @[ifu_ifc_ctl.scala 100:60] - node next_state_0 = or(_T_75, _T_78) @[ifu_ifc_ctl.scala 100:48] + fetch_addr_next <= _T_33 @[ifu_ifc_ctl.scala 82:19] + node _T_34 = not(idle) @[ifu_ifc_ctl.scala 84:30] + io.ifc_fetch_req_bf_raw <= _T_34 @[ifu_ifc_ctl.scala 84:27] + node _T_35 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 86:91] + node _T_36 = eq(_T_35, UInt<1>("h00")) @[ifu_ifc_ctl.scala 86:70] + node _T_37 = and(fb_full_f_ns, _T_36) @[ifu_ifc_ctl.scala 86:68] + node _T_38 = eq(_T_37, UInt<1>("h00")) @[ifu_ifc_ctl.scala 86:53] + node _T_39 = and(io.ifc_fetch_req_bf_raw, _T_38) @[ifu_ifc_ctl.scala 86:51] + node _T_40 = eq(dma_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 87:5] + node _T_41 = and(_T_39, _T_40) @[ifu_ifc_ctl.scala 86:114] + node _T_42 = eq(io.ic_write_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 87:18] + node _T_43 = and(_T_41, _T_42) @[ifu_ifc_ctl.scala 87:16] + node _T_44 = eq(io.dec_ifc.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 87:39] + node _T_45 = and(_T_43, _T_44) @[ifu_ifc_ctl.scala 87:37] + io.ifc_fetch_req_bf <= _T_45 @[ifu_ifc_ctl.scala 86:23] + node _T_46 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 89:37] + fetch_bf_en <= _T_46 @[ifu_ifc_ctl.scala 89:15] + node _T_47 = eq(io.ic_hit_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 91:34] + node _T_48 = and(io.ifc_fetch_req_f, _T_47) @[ifu_ifc_ctl.scala 91:32] + node _T_49 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 91:49] + node _T_50 = and(_T_48, _T_49) @[ifu_ifc_ctl.scala 91:47] + miss_f <= _T_50 @[ifu_ifc_ctl.scala 91:10] + node _T_51 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[ifu_ifc_ctl.scala 93:39] + node _T_52 = eq(dma_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 93:63] + node _T_53 = and(_T_51, _T_52) @[ifu_ifc_ctl.scala 93:61] + node _T_54 = eq(miss_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 93:76] + node _T_55 = and(_T_53, _T_54) @[ifu_ifc_ctl.scala 93:74] + node _T_56 = eq(miss_a, UInt<1>("h00")) @[ifu_ifc_ctl.scala 93:86] + node _T_57 = and(_T_55, _T_56) @[ifu_ifc_ctl.scala 93:84] + mb_empty_mod <= _T_57 @[ifu_ifc_ctl.scala 93:16] + node _T_58 = and(io.exu_flush_final, io.dec_ifc.dec_tlu_flush_noredir_wb) @[ifu_ifc_ctl.scala 95:35] + goto_idle <= _T_58 @[ifu_ifc_ctl.scala 95:13] + node _T_59 = eq(io.dec_ifc.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 97:38] + node _T_60 = and(io.exu_flush_final, _T_59) @[ifu_ifc_ctl.scala 97:36] + node _T_61 = and(_T_60, idle) @[ifu_ifc_ctl.scala 97:75] + leave_idle <= _T_61 @[ifu_ifc_ctl.scala 97:14] + node _T_62 = bits(state, 1, 1) @[ifu_ifc_ctl.scala 99:29] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[ifu_ifc_ctl.scala 99:23] + node _T_64 = bits(state, 0, 0) @[ifu_ifc_ctl.scala 99:40] + node _T_65 = and(_T_63, _T_64) @[ifu_ifc_ctl.scala 99:33] + node _T_66 = and(_T_65, miss_f) @[ifu_ifc_ctl.scala 99:44] + node _T_67 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 99:55] + node _T_68 = and(_T_66, _T_67) @[ifu_ifc_ctl.scala 99:53] + node _T_69 = bits(state, 1, 1) @[ifu_ifc_ctl.scala 100:11] + node _T_70 = eq(mb_empty_mod, UInt<1>("h00")) @[ifu_ifc_ctl.scala 100:17] + node _T_71 = and(_T_69, _T_70) @[ifu_ifc_ctl.scala 100:15] + node _T_72 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 100:33] + node _T_73 = and(_T_71, _T_72) @[ifu_ifc_ctl.scala 100:31] + node next_state_1 = or(_T_68, _T_73) @[ifu_ifc_ctl.scala 99:67] + node _T_74 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 102:23] + node _T_75 = and(_T_74, leave_idle) @[ifu_ifc_ctl.scala 102:34] + node _T_76 = bits(state, 0, 0) @[ifu_ifc_ctl.scala 102:56] + node _T_77 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 102:62] + node _T_78 = and(_T_76, _T_77) @[ifu_ifc_ctl.scala 102:60] + node next_state_0 = or(_T_75, _T_78) @[ifu_ifc_ctl.scala 102:48] node _T_79 = cat(next_state_1, next_state_0) @[Cat.scala 29:58] - reg _T_80 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_ifc_ctl.scala 102:45] - _T_80 <= _T_79 @[ifu_ifc_ctl.scala 102:45] - state <= _T_80 @[ifu_ifc_ctl.scala 102:9] - flush_fb <= io.exu_flush_final @[ifu_ifc_ctl.scala 104:12] - node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[ifu_ifc_ctl.scala 106:38] - node _T_82 = and(io.ifu_fb_consume1, _T_81) @[ifu_ifc_ctl.scala 106:36] - node _T_83 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 106:61] - node _T_84 = or(_T_83, miss_f) @[ifu_ifc_ctl.scala 106:81] - node _T_85 = and(_T_82, _T_84) @[ifu_ifc_ctl.scala 106:58] - node _T_86 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 107:25] - node _T_87 = or(_T_85, _T_86) @[ifu_ifc_ctl.scala 106:92] - fb_right <= _T_87 @[ifu_ifc_ctl.scala 106:12] - node _T_88 = not(io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 109:39] - node _T_89 = or(_T_88, miss_f) @[ifu_ifc_ctl.scala 109:59] - node _T_90 = and(io.ifu_fb_consume2, _T_89) @[ifu_ifc_ctl.scala 109:36] - fb_right2 <= _T_90 @[ifu_ifc_ctl.scala 109:13] - node _T_91 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[ifu_ifc_ctl.scala 110:56] - node _T_92 = eq(_T_91, UInt<1>("h00")) @[ifu_ifc_ctl.scala 110:35] - node _T_93 = and(io.ifc_fetch_req_f, _T_92) @[ifu_ifc_ctl.scala 110:33] - node _T_94 = eq(miss_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 110:80] - node _T_95 = and(_T_93, _T_94) @[ifu_ifc_ctl.scala 110:78] - fb_left <= _T_95 @[ifu_ifc_ctl.scala 110:11] - node _T_96 = bits(flush_fb, 0, 0) @[ifu_ifc_ctl.scala 112:37] - node _T_97 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 113:6] - node _T_98 = and(_T_97, fb_right) @[ifu_ifc_ctl.scala 113:16] - node _T_99 = bits(_T_98, 0, 0) @[ifu_ifc_ctl.scala 113:28] - node _T_100 = bits(fb_write_f, 3, 1) @[ifu_ifc_ctl.scala 113:62] + reg _T_80 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_ifc_ctl.scala 104:45] + _T_80 <= _T_79 @[ifu_ifc_ctl.scala 104:45] + state <= _T_80 @[ifu_ifc_ctl.scala 104:9] + flush_fb <= io.exu_flush_final @[ifu_ifc_ctl.scala 106:12] + node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[ifu_ifc_ctl.scala 109:38] + node _T_82 = and(io.ifu_fb_consume1, _T_81) @[ifu_ifc_ctl.scala 109:36] + node _T_83 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 109:61] + node _T_84 = or(_T_83, miss_f) @[ifu_ifc_ctl.scala 109:81] + node _T_85 = and(_T_82, _T_84) @[ifu_ifc_ctl.scala 109:58] + node _T_86 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 110:25] + node _T_87 = or(_T_85, _T_86) @[ifu_ifc_ctl.scala 109:92] + fb_right <= _T_87 @[ifu_ifc_ctl.scala 109:12] + node _T_88 = not(io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 112:39] + node _T_89 = or(_T_88, miss_f) @[ifu_ifc_ctl.scala 112:59] + node _T_90 = and(io.ifu_fb_consume2, _T_89) @[ifu_ifc_ctl.scala 112:36] + fb_right2 <= _T_90 @[ifu_ifc_ctl.scala 112:13] + node _T_91 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[ifu_ifc_ctl.scala 113:56] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[ifu_ifc_ctl.scala 113:35] + node _T_93 = and(io.ifc_fetch_req_f, _T_92) @[ifu_ifc_ctl.scala 113:33] + node _T_94 = eq(miss_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 113:80] + node _T_95 = and(_T_93, _T_94) @[ifu_ifc_ctl.scala 113:78] + fb_left <= _T_95 @[ifu_ifc_ctl.scala 113:11] + node _T_96 = bits(flush_fb, 0, 0) @[ifu_ifc_ctl.scala 116:37] + node _T_97 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 117:6] + node _T_98 = and(_T_97, fb_right) @[ifu_ifc_ctl.scala 117:16] + node _T_99 = bits(_T_98, 0, 0) @[ifu_ifc_ctl.scala 117:28] + node _T_100 = bits(fb_write_f, 3, 1) @[ifu_ifc_ctl.scala 117:62] node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58] - node _T_102 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 114:6] - node _T_103 = and(_T_102, fb_right2) @[ifu_ifc_ctl.scala 114:16] - node _T_104 = bits(_T_103, 0, 0) @[ifu_ifc_ctl.scala 114:29] - node _T_105 = bits(fb_write_f, 3, 2) @[ifu_ifc_ctl.scala 114:63] + node _T_102 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 118:6] + node _T_103 = and(_T_102, fb_right2) @[ifu_ifc_ctl.scala 118:16] + node _T_104 = bits(_T_103, 0, 0) @[ifu_ifc_ctl.scala 118:29] + node _T_105 = bits(fb_write_f, 3, 2) @[ifu_ifc_ctl.scala 118:63] node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58] - node _T_107 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 115:6] - node _T_108 = and(_T_107, fb_left) @[ifu_ifc_ctl.scala 115:16] - node _T_109 = bits(_T_108, 0, 0) @[ifu_ifc_ctl.scala 115:27] - node _T_110 = bits(fb_write_f, 2, 0) @[ifu_ifc_ctl.scala 115:51] + node _T_107 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 119:6] + node _T_108 = and(_T_107, fb_left) @[ifu_ifc_ctl.scala 119:16] + node _T_109 = bits(_T_108, 0, 0) @[ifu_ifc_ctl.scala 119:27] + node _T_110 = bits(fb_write_f, 2, 0) @[ifu_ifc_ctl.scala 119:51] node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_112 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 116:6] - node _T_113 = eq(fb_right, UInt<1>("h00")) @[ifu_ifc_ctl.scala 116:18] - node _T_114 = and(_T_112, _T_113) @[ifu_ifc_ctl.scala 116:16] - node _T_115 = eq(fb_right2, UInt<1>("h00")) @[ifu_ifc_ctl.scala 116:30] - node _T_116 = and(_T_114, _T_115) @[ifu_ifc_ctl.scala 116:28] - node _T_117 = eq(fb_left, UInt<1>("h00")) @[ifu_ifc_ctl.scala 116:43] - node _T_118 = and(_T_116, _T_117) @[ifu_ifc_ctl.scala 116:41] - node _T_119 = bits(_T_118, 0, 0) @[ifu_ifc_ctl.scala 116:53] - node _T_120 = bits(fb_write_f, 3, 0) @[ifu_ifc_ctl.scala 116:73] + node _T_112 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 120:6] + node _T_113 = eq(fb_right, UInt<1>("h00")) @[ifu_ifc_ctl.scala 120:18] + node _T_114 = and(_T_112, _T_113) @[ifu_ifc_ctl.scala 120:16] + node _T_115 = eq(fb_right2, UInt<1>("h00")) @[ifu_ifc_ctl.scala 120:30] + node _T_116 = and(_T_114, _T_115) @[ifu_ifc_ctl.scala 120:28] + node _T_117 = eq(fb_left, UInt<1>("h00")) @[ifu_ifc_ctl.scala 120:43] + node _T_118 = and(_T_116, _T_117) @[ifu_ifc_ctl.scala 120:41] + node _T_119 = bits(_T_118, 0, 0) @[ifu_ifc_ctl.scala 120:53] + node _T_120 = bits(fb_write_f, 3, 0) @[ifu_ifc_ctl.scala 120:73] node _T_121 = mux(_T_96, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72] node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72] @@ -63959,58 +63959,58 @@ circuit quasar_wrapper : node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72] wire _T_130 : UInt<4> @[Mux.scala 27:72] _T_130 <= _T_129 @[Mux.scala 27:72] - fb_write_ns <= _T_130 @[ifu_ifc_ctl.scala 112:15] - node _T_131 = eq(state, UInt<2>("h00")) @[ifu_ifc_ctl.scala 119:17] - idle <= _T_131 @[ifu_ifc_ctl.scala 119:8] - node _T_132 = eq(state, UInt<2>("h03")) @[ifu_ifc_ctl.scala 120:16] - wfm <= _T_132 @[ifu_ifc_ctl.scala 120:7] - node _T_133 = bits(fb_write_ns, 3, 3) @[ifu_ifc_ctl.scala 122:30] - fb_full_f_ns <= _T_133 @[ifu_ifc_ctl.scala 122:16] - reg fb_full_f : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_ifc_ctl.scala 123:52] - fb_full_f <= fb_full_f_ns @[ifu_ifc_ctl.scala 123:52] - reg _T_134 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_ifc_ctl.scala 124:50] - _T_134 <= fb_write_ns @[ifu_ifc_ctl.scala 124:50] - fb_write_f <= _T_134 @[ifu_ifc_ctl.scala 124:14] - node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 127:40] - node _T_136 = or(_T_135, io.exu_flush_final) @[ifu_ifc_ctl.scala 127:61] - node _T_137 = eq(_T_136, UInt<1>("h00")) @[ifu_ifc_ctl.scala 127:19] - node _T_138 = and(fb_full_f, _T_137) @[ifu_ifc_ctl.scala 127:17] - node _T_139 = or(_T_138, dma_stall) @[ifu_ifc_ctl.scala 127:84] - node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[ifu_ifc_ctl.scala 126:68] - node _T_141 = or(wfm, _T_140) @[ifu_ifc_ctl.scala 126:41] - io.dec_ifc.ifu_pmu_fetch_stall <= _T_141 @[ifu_ifc_ctl.scala 126:34] + fb_write_ns <= _T_130 @[ifu_ifc_ctl.scala 116:15] + node _T_131 = eq(state, UInt<2>("h00")) @[ifu_ifc_ctl.scala 123:17] + idle <= _T_131 @[ifu_ifc_ctl.scala 123:8] + node _T_132 = eq(state, UInt<2>("h03")) @[ifu_ifc_ctl.scala 124:16] + wfm <= _T_132 @[ifu_ifc_ctl.scala 124:7] + node _T_133 = bits(fb_write_ns, 3, 3) @[ifu_ifc_ctl.scala 126:30] + fb_full_f_ns <= _T_133 @[ifu_ifc_ctl.scala 126:16] + reg fb_full_f : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_ifc_ctl.scala 127:52] + fb_full_f <= fb_full_f_ns @[ifu_ifc_ctl.scala 127:52] + reg _T_134 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_ifc_ctl.scala 128:50] + _T_134 <= fb_write_ns @[ifu_ifc_ctl.scala 128:50] + fb_write_f <= _T_134 @[ifu_ifc_ctl.scala 128:14] + node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 131:40] + node _T_136 = or(_T_135, io.exu_flush_final) @[ifu_ifc_ctl.scala 131:61] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[ifu_ifc_ctl.scala 131:19] + node _T_138 = and(fb_full_f, _T_137) @[ifu_ifc_ctl.scala 131:17] + node _T_139 = or(_T_138, dma_stall) @[ifu_ifc_ctl.scala 131:84] + node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[ifu_ifc_ctl.scala 130:68] + node _T_141 = or(wfm, _T_140) @[ifu_ifc_ctl.scala 130:41] + io.dec_ifc.ifu_pmu_fetch_stall <= _T_141 @[ifu_ifc_ctl.scala 130:34] node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_143 = bits(_T_142, 31, 28) @[lib.scala 68:25] node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[lib.scala 68:47] node _T_144 = bits(_T_142, 31, 16) @[lib.scala 71:14] node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[lib.scala 71:29] - io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[ifu_ifc_ctl.scala 132:25] - node _T_145 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 133:30] - node _T_146 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 134:39] - node _T_147 = eq(_T_146, UInt<1>("h00")) @[ifu_ifc_ctl.scala 134:18] - node _T_148 = and(fb_full_f, _T_147) @[ifu_ifc_ctl.scala 134:16] - node _T_149 = or(_T_145, _T_148) @[ifu_ifc_ctl.scala 133:53] - node _T_150 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 135:13] - node _T_151 = and(wfm, _T_150) @[ifu_ifc_ctl.scala 135:11] - node _T_152 = or(_T_149, _T_151) @[ifu_ifc_ctl.scala 134:62] - node _T_153 = or(_T_152, idle) @[ifu_ifc_ctl.scala 135:35] - node _T_154 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 135:46] - node _T_155 = and(_T_153, _T_154) @[ifu_ifc_ctl.scala 135:44] - node _T_156 = or(_T_155, dma_iccm_stall_any_f) @[ifu_ifc_ctl.scala 135:67] - io.ifc_dma_access_ok <= _T_156 @[ifu_ifc_ctl.scala 133:24] - node _T_157 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 137:33] - node _T_158 = and(_T_157, iccm_acc_in_region_bf) @[ifu_ifc_ctl.scala 137:55] - io.ifc_region_acc_fault_bf <= _T_158 @[ifu_ifc_ctl.scala 137:30] - node _T_159 = bits(io.ifc_fetch_addr_bf, 30, 27) @[ifu_ifc_ctl.scala 138:86] + io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[ifu_ifc_ctl.scala 137:25] + node _T_145 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 138:30] + node _T_146 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 139:39] + node _T_147 = eq(_T_146, UInt<1>("h00")) @[ifu_ifc_ctl.scala 139:18] + node _T_148 = and(fb_full_f, _T_147) @[ifu_ifc_ctl.scala 139:16] + node _T_149 = or(_T_145, _T_148) @[ifu_ifc_ctl.scala 138:53] + node _T_150 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 140:13] + node _T_151 = and(wfm, _T_150) @[ifu_ifc_ctl.scala 140:11] + node _T_152 = or(_T_149, _T_151) @[ifu_ifc_ctl.scala 139:62] + node _T_153 = or(_T_152, idle) @[ifu_ifc_ctl.scala 140:35] + node _T_154 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 140:46] + node _T_155 = and(_T_153, _T_154) @[ifu_ifc_ctl.scala 140:44] + node _T_156 = or(_T_155, dma_iccm_stall_any_f) @[ifu_ifc_ctl.scala 140:67] + io.ifc_dma_access_ok <= _T_156 @[ifu_ifc_ctl.scala 138:24] + node _T_157 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 142:33] + node _T_158 = and(_T_157, iccm_acc_in_region_bf) @[ifu_ifc_ctl.scala 142:55] + io.ifc_region_acc_fault_bf <= _T_158 @[ifu_ifc_ctl.scala 142:30] + node _T_159 = bits(io.ifc_fetch_addr_bf, 30, 27) @[ifu_ifc_ctl.scala 143:86] node _T_160 = cat(_T_159, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_161 = dshr(io.dec_ifc.dec_tlu_mrac_ff, _T_160) @[ifu_ifc_ctl.scala 138:61] - node _T_162 = bits(_T_161, 0, 0) @[ifu_ifc_ctl.scala 138:61] - node _T_163 = not(_T_162) @[ifu_ifc_ctl.scala 138:34] - io.ifc_fetch_uncacheable_bf <= _T_163 @[ifu_ifc_ctl.scala 138:31] - reg _T_164 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_ifc_ctl.scala 140:57] - _T_164 <= io.ifc_fetch_req_bf @[ifu_ifc_ctl.scala 140:57] - io.ifc_fetch_req_f <= _T_164 @[ifu_ifc_ctl.scala 140:22] - node _T_165 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 142:73] + node _T_161 = dshr(io.dec_ifc.dec_tlu_mrac_ff, _T_160) @[ifu_ifc_ctl.scala 143:61] + node _T_162 = bits(_T_161, 0, 0) @[ifu_ifc_ctl.scala 143:61] + node _T_163 = not(_T_162) @[ifu_ifc_ctl.scala 143:34] + io.ifc_fetch_uncacheable_bf <= _T_163 @[ifu_ifc_ctl.scala 143:31] + reg _T_164 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_ifc_ctl.scala 145:57] + _T_164 <= io.ifc_fetch_req_bf @[ifu_ifc_ctl.scala 145:57] + io.ifc_fetch_req_f <= _T_164 @[ifu_ifc_ctl.scala 145:22] + node _T_165 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 147:73] inst rvclkhdr of rvclkhdr_660 @[lib.scala 352:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -64019,7 +64019,7 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_166 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_166 <= io.ifc_fetch_addr_bf @[lib.scala 358:16] - io.ifc_fetch_addr_f <= _T_166 @[ifu_ifc_ctl.scala 142:23] + io.ifc_fetch_addr_f <= _T_166 @[ifu_ifc_ctl.scala 147:23] module ifu : input clock : Clock @@ -74026,380 +74026,381 @@ circuit quasar_wrapper : node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2128:100] node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2128:71] node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2130:34] - node _T_754 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2130:86] - node _T_755 = mux(_T_753, io.dec_csr_wrdata_r, _T_754) @[dec_tlu_ctl.scala 2130:21] - node _T_756 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2132:78] - node _T_757 = bits(_T_756, 0, 0) @[dec_tlu_ctl.scala 2132:111] - reg _T_758 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_757 : @[Reg.scala 28:19] - _T_758 <= _T_755 @[Reg.scala 28:23] + node _T_754 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2130:61] + node _T_755 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2130:91] + node _T_756 = mux(_T_753, _T_754, _T_755) @[dec_tlu_ctl.scala 2130:21] + node _T_757 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2132:78] + node _T_758 = bits(_T_757, 0, 0) @[dec_tlu_ctl.scala 2132:111] + reg _T_759 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_758 : @[Reg.scala 28:19] + _T_759 <= _T_756 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_748 <= _T_758 @[dec_tlu_ctl.scala 2132:13] - node _T_759 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] - dicad1 <= _T_759 @[dec_tlu_ctl.scala 2133:9] - node _T_760 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2155:69] - node _T_761 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2155:83] - node _T_762 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2155:97] - node _T_763 = cat(_T_760, _T_761) @[Cat.scala 29:58] - node _T_764 = cat(_T_763, _T_762) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_764 @[dec_tlu_ctl.scala 2155:56] + _T_748 <= _T_759 @[dec_tlu_ctl.scala 2132:13] + node _T_760 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] + dicad1 <= _T_760 @[dec_tlu_ctl.scala 2133:9] + node _T_761 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2155:69] + node _T_762 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2155:83] + node _T_763 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2155:97] + node _T_764 = cat(_T_761, _T_762) @[Cat.scala 29:58] + node _T_765 = cat(_T_764, _T_763) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_765 @[dec_tlu_ctl.scala 2155:56] io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2158:41] - node _T_765 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2160:52] - node _T_766 = and(_T_765, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2160:75] - node _T_767 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2160:98] - node _T_768 = and(_T_766, _T_767) @[dec_tlu_ctl.scala 2160:96] - node _T_769 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2160:142] - node _T_770 = eq(_T_769, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:149] - node icache_rd_valid = and(_T_768, _T_770) @[dec_tlu_ctl.scala 2160:120] - node _T_771 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2161:52] - node _T_772 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2161:97] - node _T_773 = eq(_T_772, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2161:104] - node icache_wr_valid = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2161:75] + node _T_766 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2160:52] + node _T_767 = and(_T_766, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2160:75] + node _T_768 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2160:98] + node _T_769 = and(_T_767, _T_768) @[dec_tlu_ctl.scala 2160:96] + node _T_770 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2160:142] + node _T_771 = eq(_T_770, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:149] + node icache_rd_valid = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2160:120] + node _T_772 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2161:52] + node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2161:97] + node _T_774 = eq(_T_773, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2161:104] + node icache_wr_valid = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2161:75] reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2163:58] icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2163:58] reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2164:58] icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2164:58] io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2166:41] io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2167:41] - node _T_774 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2175:62] - node _T_775 = eq(_T_774, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2175:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_775) @[dec_tlu_ctl.scala 2175:40] - node _T_776 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2176:32] - node _T_777 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2176:59] - node mtsel_ns = mux(_T_776, _T_777, mtsel) @[dec_tlu_ctl.scala 2176:20] - reg _T_778 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2178:43] - _T_778 <= mtsel_ns @[dec_tlu_ctl.scala 2178:43] - mtsel <= _T_778 @[dec_tlu_ctl.scala 2178:8] - node _T_779 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2213:38] - node _T_780 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:64] - node _T_781 = not(_T_780) @[dec_tlu_ctl.scala 2213:44] - node tdata_load = and(_T_779, _T_781) @[dec_tlu_ctl.scala 2213:42] - node _T_782 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2215:40] - node _T_783 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2215:66] - node _T_784 = not(_T_783) @[dec_tlu_ctl.scala 2215:46] - node tdata_opcode = and(_T_782, _T_784) @[dec_tlu_ctl.scala 2215:44] - node _T_785 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:41] - node _T_786 = and(_T_785, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:46] - node _T_787 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2217:90] - node tdata_action = and(_T_786, _T_787) @[dec_tlu_ctl.scala 2217:69] - node _T_788 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2219:47] - node _T_789 = and(_T_788, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2219:52] - node _T_790 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2219:94] - node _T_791 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2219:136] - node _T_792 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2220:43] - node _T_793 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2220:83] - node _T_794 = cat(_T_793, tdata_load) @[Cat.scala 29:58] - node _T_795 = cat(_T_792, tdata_opcode) @[Cat.scala 29:58] - node _T_796 = cat(_T_795, _T_794) @[Cat.scala 29:58] - node _T_797 = cat(tdata_action, _T_791) @[Cat.scala 29:58] - node _T_798 = cat(_T_789, _T_790) @[Cat.scala 29:58] - node _T_799 = cat(_T_798, _T_797) @[Cat.scala 29:58] - node tdata_wrdata_r = cat(_T_799, _T_796) @[Cat.scala 29:58] - node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2223:70] - node _T_803 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2223:121] - node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2223:112] - node _T_805 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2223:138] - node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2223:135] - node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2223:70] - node _T_812 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2223:121] - node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2223:112] - node _T_814 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2223:138] - node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2223:135] - node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2223:70] - node _T_821 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2223:121] - node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2223:112] - node _T_823 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2223:138] - node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2223:135] - node _T_827 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] - node _T_828 = eq(_T_827, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] - node _T_829 = and(io.dec_csr_wen_r_mod, _T_828) @[dec_tlu_ctl.scala 2223:70] - node _T_830 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2223:121] - node _T_831 = and(_T_829, _T_830) @[dec_tlu_ctl.scala 2223:112] - node _T_832 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:154] - node _T_833 = not(_T_832) @[dec_tlu_ctl.scala 2223:138] - node _T_834 = or(_T_833, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] - node _T_835 = and(_T_831, _T_834) @[dec_tlu_ctl.scala 2223:135] + node _T_775 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2175:62] + node _T_776 = eq(_T_775, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2175:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_776) @[dec_tlu_ctl.scala 2175:40] + node _T_777 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2176:32] + node _T_778 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2176:59] + node mtsel_ns = mux(_T_777, _T_778, mtsel) @[dec_tlu_ctl.scala 2176:20] + reg _T_779 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2178:43] + _T_779 <= mtsel_ns @[dec_tlu_ctl.scala 2178:43] + mtsel <= _T_779 @[dec_tlu_ctl.scala 2178:8] + node _T_780 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2213:38] + node _T_781 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:64] + node _T_782 = not(_T_781) @[dec_tlu_ctl.scala 2213:44] + node tdata_load = and(_T_780, _T_782) @[dec_tlu_ctl.scala 2213:42] + node _T_783 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2215:40] + node _T_784 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2215:66] + node _T_785 = not(_T_784) @[dec_tlu_ctl.scala 2215:46] + node tdata_opcode = and(_T_783, _T_785) @[dec_tlu_ctl.scala 2215:44] + node _T_786 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:41] + node _T_787 = and(_T_786, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:46] + node _T_788 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2217:90] + node tdata_action = and(_T_787, _T_788) @[dec_tlu_ctl.scala 2217:69] + node _T_789 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2219:47] + node _T_790 = and(_T_789, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2219:52] + node _T_791 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2219:94] + node _T_792 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2219:136] + node _T_793 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2220:43] + node _T_794 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2220:83] + node _T_795 = cat(_T_794, tdata_load) @[Cat.scala 29:58] + node _T_796 = cat(_T_793, tdata_opcode) @[Cat.scala 29:58] + node _T_797 = cat(_T_796, _T_795) @[Cat.scala 29:58] + node _T_798 = cat(tdata_action, _T_792) @[Cat.scala 29:58] + node _T_799 = cat(_T_790, _T_791) @[Cat.scala 29:58] + node _T_800 = cat(_T_799, _T_798) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_800, _T_797) @[Cat.scala 29:58] + node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2223:70] + node _T_804 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2223:121] + node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2223:112] + node _T_806 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2223:138] + node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2223:135] + node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2223:70] + node _T_813 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2223:121] + node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2223:112] + node _T_815 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2223:138] + node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2223:135] + node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2223:70] + node _T_822 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2223:121] + node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2223:112] + node _T_824 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2223:138] + node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2223:135] + node _T_828 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_829 = eq(_T_828, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_830 = and(io.dec_csr_wen_r_mod, _T_829) @[dec_tlu_ctl.scala 2223:70] + node _T_831 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2223:121] + node _T_832 = and(_T_830, _T_831) @[dec_tlu_ctl.scala 2223:112] + node _T_833 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_834 = not(_T_833) @[dec_tlu_ctl.scala 2223:138] + node _T_835 = or(_T_834, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_836 = and(_T_832, _T_835) @[dec_tlu_ctl.scala 2223:135] wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[0] <= _T_808 @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[1] <= _T_817 @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[2] <= _T_826 @[dec_tlu_ctl.scala 2223:42] - wr_mtdata1_t_r[3] <= _T_835 @[dec_tlu_ctl.scala 2223:42] - node _T_836 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_837 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_838 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2224:135] - node _T_839 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2224:139] - node _T_841 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58] - node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58] - node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2224:49] - node _T_845 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_846 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_847 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2224:135] - node _T_848 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2224:139] - node _T_850 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58] - node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58] - node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2224:49] - node _T_854 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_855 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_856 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2224:135] - node _T_857 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2224:139] - node _T_859 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58] - node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58] - node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2224:49] - node _T_863 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2224:68] - node _T_864 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:111] - node _T_865 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2224:135] - node _T_866 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2224:156] - node _T_867 = or(_T_865, _T_866) @[dec_tlu_ctl.scala 2224:139] - node _T_868 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2224:176] - node _T_869 = cat(_T_864, _T_867) @[Cat.scala 29:58] - node _T_870 = cat(_T_869, _T_868) @[Cat.scala 29:58] - node _T_871 = mux(_T_863, tdata_wrdata_r, _T_870) @[dec_tlu_ctl.scala 2224:49] + wr_mtdata1_t_r[0] <= _T_809 @[dec_tlu_ctl.scala 2223:42] + wr_mtdata1_t_r[1] <= _T_818 @[dec_tlu_ctl.scala 2223:42] + wr_mtdata1_t_r[2] <= _T_827 @[dec_tlu_ctl.scala 2223:42] + wr_mtdata1_t_r[3] <= _T_836 @[dec_tlu_ctl.scala 2223:42] + node _T_837 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_838 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_839 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2224:135] + node _T_840 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2224:139] + node _T_842 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2224:176] + node _T_843 = cat(_T_838, _T_841) @[Cat.scala 29:58] + node _T_844 = cat(_T_843, _T_842) @[Cat.scala 29:58] + node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2224:49] + node _T_846 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_847 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_848 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2224:135] + node _T_849 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2224:139] + node _T_851 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2224:176] + node _T_852 = cat(_T_847, _T_850) @[Cat.scala 29:58] + node _T_853 = cat(_T_852, _T_851) @[Cat.scala 29:58] + node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2224:49] + node _T_855 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_856 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_857 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2224:135] + node _T_858 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2224:139] + node _T_860 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2224:176] + node _T_861 = cat(_T_856, _T_859) @[Cat.scala 29:58] + node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58] + node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2224:49] + node _T_864 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_865 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_866 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2224:135] + node _T_867 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_868 = or(_T_866, _T_867) @[dec_tlu_ctl.scala 2224:139] + node _T_869 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2224:176] + node _T_870 = cat(_T_865, _T_868) @[Cat.scala 29:58] + node _T_871 = cat(_T_870, _T_869) @[Cat.scala 29:58] + node _T_872 = mux(_T_864, tdata_wrdata_r, _T_871) @[dec_tlu_ctl.scala 2224:49] wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[0] <= _T_844 @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[1] <= _T_853 @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[2] <= _T_862 @[dec_tlu_ctl.scala 2224:40] - mtdata1_t_ns[3] <= _T_871 @[dec_tlu_ctl.scala 2224:40] - reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_872 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[0] <= _T_872 @[dec_tlu_ctl.scala 2226:39] + mtdata1_t_ns[0] <= _T_845 @[dec_tlu_ctl.scala 2224:40] + mtdata1_t_ns[1] <= _T_854 @[dec_tlu_ctl.scala 2224:40] + mtdata1_t_ns[2] <= _T_863 @[dec_tlu_ctl.scala 2224:40] + mtdata1_t_ns[3] <= _T_872 @[dec_tlu_ctl.scala 2224:40] reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_873 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[1] <= _T_873 @[dec_tlu_ctl.scala 2226:39] + _T_873 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[0] <= _T_873 @[dec_tlu_ctl.scala 2226:39] reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_874 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[2] <= _T_874 @[dec_tlu_ctl.scala 2226:39] + _T_874 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[1] <= _T_874 @[dec_tlu_ctl.scala 2226:39] reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] - _T_875 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2226:74] - io.mtdata1_t[3] <= _T_875 @[dec_tlu_ctl.scala 2226:39] - node _T_876 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:58] - node _T_877 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_878 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_879 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_880 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_881 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_882 = cat(UInt<3>("h00"), _T_881) @[Cat.scala 29:58] - node _T_883 = cat(_T_879, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_884 = cat(_T_883, _T_880) @[Cat.scala 29:58] - node _T_885 = cat(_T_884, _T_882) @[Cat.scala 29:58] - node _T_886 = cat(_T_878, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_887 = cat(UInt<4>("h02"), _T_877) @[Cat.scala 29:58] - node _T_888 = cat(_T_887, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_889 = cat(_T_888, _T_886) @[Cat.scala 29:58] - node _T_890 = cat(_T_889, _T_885) @[Cat.scala 29:58] - node _T_891 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:58] - node _T_892 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_893 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_894 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_895 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_896 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_897 = cat(UInt<3>("h00"), _T_896) @[Cat.scala 29:58] - node _T_898 = cat(_T_894, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_899 = cat(_T_898, _T_895) @[Cat.scala 29:58] - node _T_900 = cat(_T_899, _T_897) @[Cat.scala 29:58] - node _T_901 = cat(_T_893, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_902 = cat(UInt<4>("h02"), _T_892) @[Cat.scala 29:58] - node _T_903 = cat(_T_902, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_904 = cat(_T_903, _T_901) @[Cat.scala 29:58] - node _T_905 = cat(_T_904, _T_900) @[Cat.scala 29:58] - node _T_906 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:58] - node _T_907 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_908 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_909 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_910 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_911 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_912 = cat(UInt<3>("h00"), _T_911) @[Cat.scala 29:58] - node _T_913 = cat(_T_909, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_914 = cat(_T_913, _T_910) @[Cat.scala 29:58] - node _T_915 = cat(_T_914, _T_912) @[Cat.scala 29:58] - node _T_916 = cat(_T_908, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_917 = cat(UInt<4>("h02"), _T_907) @[Cat.scala 29:58] - node _T_918 = cat(_T_917, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_919 = cat(_T_918, _T_916) @[Cat.scala 29:58] - node _T_920 = cat(_T_919, _T_915) @[Cat.scala 29:58] - node _T_921 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:58] - node _T_922 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2229:104] - node _T_923 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2229:142] - node _T_924 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2229:174] - node _T_925 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2229:206] - node _T_926 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2229:238] - node _T_927 = cat(UInt<3>("h00"), _T_926) @[Cat.scala 29:58] - node _T_928 = cat(_T_924, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_929 = cat(_T_928, _T_925) @[Cat.scala 29:58] - node _T_930 = cat(_T_929, _T_927) @[Cat.scala 29:58] - node _T_931 = cat(_T_923, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_932 = cat(UInt<4>("h02"), _T_922) @[Cat.scala 29:58] - node _T_933 = cat(_T_932, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] - node _T_935 = cat(_T_934, _T_930) @[Cat.scala 29:58] - node _T_936 = mux(_T_876, _T_890, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_937 = mux(_T_891, _T_905, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_938 = mux(_T_906, _T_920, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_939 = mux(_T_921, _T_935, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_940 = or(_T_936, _T_937) @[Mux.scala 27:72] - node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] + _T_875 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[2] <= _T_875 @[dec_tlu_ctl.scala 2226:39] + reg _T_876 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] + _T_876 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[3] <= _T_876 @[dec_tlu_ctl.scala 2226:39] + node _T_877 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:58] + node _T_878 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_879 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_880 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_881 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_882 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2229:238] + node _T_883 = cat(UInt<3>("h00"), _T_882) @[Cat.scala 29:58] + node _T_884 = cat(_T_880, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_885 = cat(_T_884, _T_881) @[Cat.scala 29:58] + node _T_886 = cat(_T_885, _T_883) @[Cat.scala 29:58] + node _T_887 = cat(_T_879, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_888 = cat(UInt<4>("h02"), _T_878) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_887) @[Cat.scala 29:58] + node _T_891 = cat(_T_890, _T_886) @[Cat.scala 29:58] + node _T_892 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:58] + node _T_893 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_894 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_895 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_896 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_897 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2229:238] + node _T_898 = cat(UInt<3>("h00"), _T_897) @[Cat.scala 29:58] + node _T_899 = cat(_T_895, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_900 = cat(_T_899, _T_896) @[Cat.scala 29:58] + node _T_901 = cat(_T_900, _T_898) @[Cat.scala 29:58] + node _T_902 = cat(_T_894, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_903 = cat(UInt<4>("h02"), _T_893) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_902) @[Cat.scala 29:58] + node _T_906 = cat(_T_905, _T_901) @[Cat.scala 29:58] + node _T_907 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:58] + node _T_908 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_909 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_910 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_911 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_912 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2229:238] + node _T_913 = cat(UInt<3>("h00"), _T_912) @[Cat.scala 29:58] + node _T_914 = cat(_T_910, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_915 = cat(_T_914, _T_911) @[Cat.scala 29:58] + node _T_916 = cat(_T_915, _T_913) @[Cat.scala 29:58] + node _T_917 = cat(_T_909, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_918 = cat(UInt<4>("h02"), _T_908) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_920 = cat(_T_919, _T_917) @[Cat.scala 29:58] + node _T_921 = cat(_T_920, _T_916) @[Cat.scala 29:58] + node _T_922 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:58] + node _T_923 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_924 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_925 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_926 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_927 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2229:238] + node _T_928 = cat(UInt<3>("h00"), _T_927) @[Cat.scala 29:58] + node _T_929 = cat(_T_925, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_930 = cat(_T_929, _T_926) @[Cat.scala 29:58] + node _T_931 = cat(_T_930, _T_928) @[Cat.scala 29:58] + node _T_932 = cat(_T_924, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_933 = cat(UInt<4>("h02"), _T_923) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_935 = cat(_T_934, _T_932) @[Cat.scala 29:58] + node _T_936 = cat(_T_935, _T_931) @[Cat.scala 29:58] + node _T_937 = mux(_T_877, _T_891, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_892, _T_906, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = mux(_T_907, _T_921, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_940 = mux(_T_922, _T_936, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_941 = or(_T_937, _T_938) @[Mux.scala 27:72] node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72] + node _T_943 = or(_T_942, _T_940) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata1_tsel_out <= _T_942 @[Mux.scala 27:72] - node _T_943 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[0].select <= _T_943 @[dec_tlu_ctl.scala 2231:40] - node _T_944 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[0].match_pkt <= _T_944 @[dec_tlu_ctl.scala 2232:43] - node _T_945 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[0].store <= _T_945 @[dec_tlu_ctl.scala 2233:40] - node _T_946 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[0].load <= _T_946 @[dec_tlu_ctl.scala 2234:40] - node _T_947 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[0].execute <= _T_947 @[dec_tlu_ctl.scala 2235:40] - node _T_948 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[0].m <= _T_948 @[dec_tlu_ctl.scala 2236:40] - node _T_949 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[1].select <= _T_949 @[dec_tlu_ctl.scala 2231:40] - node _T_950 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[1].match_pkt <= _T_950 @[dec_tlu_ctl.scala 2232:43] - node _T_951 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[1].store <= _T_951 @[dec_tlu_ctl.scala 2233:40] - node _T_952 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[1].load <= _T_952 @[dec_tlu_ctl.scala 2234:40] - node _T_953 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[1].execute <= _T_953 @[dec_tlu_ctl.scala 2235:40] - node _T_954 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[1].m <= _T_954 @[dec_tlu_ctl.scala 2236:40] - node _T_955 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[2].select <= _T_955 @[dec_tlu_ctl.scala 2231:40] - node _T_956 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[2].match_pkt <= _T_956 @[dec_tlu_ctl.scala 2232:43] - node _T_957 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[2].store <= _T_957 @[dec_tlu_ctl.scala 2233:40] - node _T_958 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[2].load <= _T_958 @[dec_tlu_ctl.scala 2234:40] - node _T_959 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[2].execute <= _T_959 @[dec_tlu_ctl.scala 2235:40] - node _T_960 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[2].m <= _T_960 @[dec_tlu_ctl.scala 2236:40] - node _T_961 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[3].select <= _T_961 @[dec_tlu_ctl.scala 2231:40] - node _T_962 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2232:61] - io.trigger_pkt_any[3].match_pkt <= _T_962 @[dec_tlu_ctl.scala 2232:43] - node _T_963 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[3].store <= _T_963 @[dec_tlu_ctl.scala 2233:40] - node _T_964 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[3].load <= _T_964 @[dec_tlu_ctl.scala 2234:40] - node _T_965 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[3].execute <= _T_965 @[dec_tlu_ctl.scala 2235:40] - node _T_966 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2236:58] - io.trigger_pkt_any[3].m <= _T_966 @[dec_tlu_ctl.scala 2236:40] - node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2243:69] - node _T_970 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2243:120] - node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2243:111] - node _T_972 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2243:137] - node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2243:134] - node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2243:69] - node _T_979 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2243:120] - node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2243:111] - node _T_981 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2243:137] - node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2243:134] - node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2243:69] - node _T_988 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2243:120] - node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2243:111] - node _T_990 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2243:137] - node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2243:134] - node _T_994 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] - node _T_995 = eq(_T_994, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] - node _T_996 = and(io.dec_csr_wen_r_mod, _T_995) @[dec_tlu_ctl.scala 2243:69] - node _T_997 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2243:120] - node _T_998 = and(_T_996, _T_997) @[dec_tlu_ctl.scala 2243:111] - node _T_999 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2243:153] - node _T_1000 = not(_T_999) @[dec_tlu_ctl.scala 2243:137] - node _T_1001 = or(_T_1000, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] - node _T_1002 = and(_T_998, _T_1001) @[dec_tlu_ctl.scala 2243:134] + mtdata1_tsel_out <= _T_943 @[Mux.scala 27:72] + node _T_944 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[0].select <= _T_944 @[dec_tlu_ctl.scala 2231:40] + node _T_945 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[0].match_pkt <= _T_945 @[dec_tlu_ctl.scala 2232:43] + node _T_946 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[0].store <= _T_946 @[dec_tlu_ctl.scala 2233:40] + node _T_947 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[0].load <= _T_947 @[dec_tlu_ctl.scala 2234:40] + node _T_948 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[0].execute <= _T_948 @[dec_tlu_ctl.scala 2235:40] + node _T_949 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[0].m <= _T_949 @[dec_tlu_ctl.scala 2236:40] + node _T_950 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[1].select <= _T_950 @[dec_tlu_ctl.scala 2231:40] + node _T_951 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[1].match_pkt <= _T_951 @[dec_tlu_ctl.scala 2232:43] + node _T_952 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[1].store <= _T_952 @[dec_tlu_ctl.scala 2233:40] + node _T_953 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[1].load <= _T_953 @[dec_tlu_ctl.scala 2234:40] + node _T_954 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[1].execute <= _T_954 @[dec_tlu_ctl.scala 2235:40] + node _T_955 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[1].m <= _T_955 @[dec_tlu_ctl.scala 2236:40] + node _T_956 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[2].select <= _T_956 @[dec_tlu_ctl.scala 2231:40] + node _T_957 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[2].match_pkt <= _T_957 @[dec_tlu_ctl.scala 2232:43] + node _T_958 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[2].store <= _T_958 @[dec_tlu_ctl.scala 2233:40] + node _T_959 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[2].load <= _T_959 @[dec_tlu_ctl.scala 2234:40] + node _T_960 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[2].execute <= _T_960 @[dec_tlu_ctl.scala 2235:40] + node _T_961 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[2].m <= _T_961 @[dec_tlu_ctl.scala 2236:40] + node _T_962 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[3].select <= _T_962 @[dec_tlu_ctl.scala 2231:40] + node _T_963 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[3].match_pkt <= _T_963 @[dec_tlu_ctl.scala 2232:43] + node _T_964 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[3].store <= _T_964 @[dec_tlu_ctl.scala 2233:40] + node _T_965 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[3].load <= _T_965 @[dec_tlu_ctl.scala 2234:40] + node _T_966 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[3].execute <= _T_966 @[dec_tlu_ctl.scala 2235:40] + node _T_967 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[3].m <= _T_967 @[dec_tlu_ctl.scala 2236:40] + node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2243:69] + node _T_971 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2243:120] + node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2243:111] + node _T_973 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2243:137] + node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2243:134] + node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2243:69] + node _T_980 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2243:120] + node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2243:111] + node _T_982 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2243:137] + node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2243:134] + node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2243:69] + node _T_989 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2243:120] + node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2243:111] + node _T_991 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2243:137] + node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2243:134] + node _T_995 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_996 = eq(_T_995, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_997 = and(io.dec_csr_wen_r_mod, _T_996) @[dec_tlu_ctl.scala 2243:69] + node _T_998 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2243:120] + node _T_999 = and(_T_997, _T_998) @[dec_tlu_ctl.scala 2243:111] + node _T_1000 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_1001 = not(_T_1000) @[dec_tlu_ctl.scala 2243:137] + node _T_1002 = or(_T_1001, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_1003 = and(_T_999, _T_1002) @[dec_tlu_ctl.scala 2243:134] wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[0] <= _T_975 @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[1] <= _T_984 @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[2] <= _T_993 @[dec_tlu_ctl.scala 2243:42] - wr_mtdata2_t_r[3] <= _T_1002 @[dec_tlu_ctl.scala 2243:42] - node _T_1003 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2244:84] + wr_mtdata2_t_r[0] <= _T_976 @[dec_tlu_ctl.scala 2243:42] + wr_mtdata2_t_r[1] <= _T_985 @[dec_tlu_ctl.scala 2243:42] + wr_mtdata2_t_r[2] <= _T_994 @[dec_tlu_ctl.scala 2243:42] + wr_mtdata2_t_r[3] <= _T_1003 @[dec_tlu_ctl.scala 2243:42] + node _T_1004 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 352:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset rvclkhdr_22.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_22.io.en <= _T_1003 @[lib.scala 355:17] + rvclkhdr_22.io.en <= _T_1004 @[lib.scala 355:17] rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_1004 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_1004 <= io.dec_csr_wrdata_r @[lib.scala 358:16] - mtdata2_t[0] <= _T_1004 @[dec_tlu_ctl.scala 2244:36] - node _T_1005 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2244:84] + reg _T_1005 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_1005 <= io.dec_csr_wrdata_r @[lib.scala 358:16] + mtdata2_t[0] <= _T_1005 @[dec_tlu_ctl.scala 2244:36] + node _T_1006 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 352:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset rvclkhdr_23.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_23.io.en <= _T_1005 @[lib.scala 355:17] + rvclkhdr_23.io.en <= _T_1006 @[lib.scala 355:17] rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_1006 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_1006 <= io.dec_csr_wrdata_r @[lib.scala 358:16] - mtdata2_t[1] <= _T_1006 @[dec_tlu_ctl.scala 2244:36] - node _T_1007 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2244:84] + reg _T_1007 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_1007 <= io.dec_csr_wrdata_r @[lib.scala 358:16] + mtdata2_t[1] <= _T_1007 @[dec_tlu_ctl.scala 2244:36] + node _T_1008 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 352:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset rvclkhdr_24.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_24.io.en <= _T_1007 @[lib.scala 355:17] + rvclkhdr_24.io.en <= _T_1008 @[lib.scala 355:17] rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_1008 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_1008 <= io.dec_csr_wrdata_r @[lib.scala 358:16] - mtdata2_t[2] <= _T_1008 @[dec_tlu_ctl.scala 2244:36] - node _T_1009 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2244:84] + reg _T_1009 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_1009 <= io.dec_csr_wrdata_r @[lib.scala 358:16] + mtdata2_t[2] <= _T_1009 @[dec_tlu_ctl.scala 2244:36] + node _T_1010 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 352:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset rvclkhdr_25.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_25.io.en <= _T_1009 @[lib.scala 355:17] + rvclkhdr_25.io.en <= _T_1010 @[lib.scala 355:17] rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_1010 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_1010 <= io.dec_csr_wrdata_r @[lib.scala 358:16] - mtdata2_t[3] <= _T_1010 @[dec_tlu_ctl.scala 2244:36] - node _T_1011 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2248:57] - node _T_1012 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2248:57] - node _T_1013 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2248:57] - node _T_1014 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2248:57] - node _T_1015 = mux(_T_1011, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1016 = mux(_T_1012, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1017 = mux(_T_1013, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1018 = mux(_T_1014, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1019 = or(_T_1015, _T_1016) @[Mux.scala 27:72] - node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] + reg _T_1011 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_1011 <= io.dec_csr_wrdata_r @[lib.scala 358:16] + mtdata2_t[3] <= _T_1011 @[dec_tlu_ctl.scala 2244:36] + node _T_1012 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2248:57] + node _T_1013 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2248:57] + node _T_1014 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2248:57] + node _T_1015 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2248:57] + node _T_1016 = mux(_T_1012, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1017 = mux(_T_1013, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1018 = mux(_T_1014, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1019 = mux(_T_1015, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1020 = or(_T_1016, _T_1017) @[Mux.scala 27:72] node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72] + node _T_1022 = or(_T_1021, _T_1019) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata2_tsel_out <= _T_1021 @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1022 @[Mux.scala 27:72] io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2249:51] io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2249:51] io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2249:51] @@ -74408,239 +74409,238 @@ circuit quasar_wrapper : mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2260:15] mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2261:15] mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2262:15] - node _T_1022 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] - node _T_1023 = mux(_T_1022, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1023) @[dec_tlu_ctl.scala 2268:59] + node _T_1023 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1024 = mux(_T_1023, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1024) @[dec_tlu_ctl.scala 2268:59] wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2269:24] wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2270:27] - node _T_1024 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2274:38] - node _T_1025 = not(_T_1024) @[dec_tlu_ctl.scala 2274:24] - node _T_1026 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1028 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1030 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1031 = bits(_T_1030, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1032 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1034 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1035 = and(io.tlu_i0_commit_cmt, _T_1034) @[dec_tlu_ctl.scala 2278:94] - node _T_1036 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1037 = bits(_T_1036, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1038 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1039 = and(io.tlu_i0_commit_cmt, _T_1038) @[dec_tlu_ctl.scala 2279:94] - node _T_1040 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1041 = and(_T_1039, _T_1040) @[dec_tlu_ctl.scala 2279:115] - node _T_1042 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1044 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1045 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1046 = and(_T_1044, _T_1045) @[dec_tlu_ctl.scala 2280:115] - node _T_1047 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1049 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1051 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1053 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1058 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1062 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1063 = bits(_T_1062, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1064 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1068 = and(_T_1067, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1069 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1072 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2289:101] - node _T_1074 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1077 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1080 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1083 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1086 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1089 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1092 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1095 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1096 = bits(_T_1095, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1097 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1098 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1100 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1101 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1103 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1105 = or(_T_1103, _T_1104) @[dec_tlu_ctl.scala 2299:101] - node _T_1106 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1108 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1111 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1112 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1114 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1115 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1117 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1119 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1121 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1123 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1125 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1127 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1129 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1131 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1132 = or(_T_1131, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1133 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1135 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1136 = or(_T_1135, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1137 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1139 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1141 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1143 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1144 = and(_T_1143, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1149 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1151 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1153 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1155 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1157 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1159 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_1160 = bits(_T_1159, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1161 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1162 = bits(_T_1161, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1163 = not(_T_1162) @[dec_tlu_ctl.scala 2322:73] - node _T_1164 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1166 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_1168 = not(_T_1167) @[dec_tlu_ctl.scala 2323:73] - node _T_1169 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_1170 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_1171 = and(_T_1169, _T_1170) @[dec_tlu_ctl.scala 2323:113] - node _T_1172 = orr(_T_1171) @[dec_tlu_ctl.scala 2323:125] - node _T_1173 = and(_T_1168, _T_1172) @[dec_tlu_ctl.scala 2323:98] - node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_1186 = bits(_T_1185, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_1188 = bits(_T_1187, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_1190 = bits(_T_1189, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_1192 = bits(_T_1191, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1193 = mux(_T_1027, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1194 = mux(_T_1029, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1195 = mux(_T_1031, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1196 = mux(_T_1033, _T_1035, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1197 = mux(_T_1037, _T_1041, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1198 = mux(_T_1043, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1199 = mux(_T_1048, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1200 = mux(_T_1050, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1201 = mux(_T_1052, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1202 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1203 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1204 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1205 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1206 = mux(_T_1066, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1207 = mux(_T_1070, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1208 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1209 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1210 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1211 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1212 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1213 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1214 = mux(_T_1093, _T_1094, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1215 = mux(_T_1096, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1216 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1217 = mux(_T_1102, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1218 = mux(_T_1107, _T_1108, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1219 = mux(_T_1110, _T_1111, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1220 = mux(_T_1113, _T_1114, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1221 = mux(_T_1116, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1222 = mux(_T_1118, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1223 = mux(_T_1120, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1224 = mux(_T_1122, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1225 = mux(_T_1124, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1226 = mux(_T_1126, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1227 = mux(_T_1128, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1228 = mux(_T_1130, _T_1132, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1229 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1230 = mux(_T_1138, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1231 = mux(_T_1140, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1232 = mux(_T_1142, _T_1144, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1233 = mux(_T_1146, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1234 = mux(_T_1148, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1235 = mux(_T_1150, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1236 = mux(_T_1152, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1237 = mux(_T_1154, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1238 = mux(_T_1156, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1239 = mux(_T_1158, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1240 = mux(_T_1160, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1241 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1242 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1243 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1244 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1245 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1246 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1247 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1248 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1249 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1250 = or(_T_1193, _T_1194) @[Mux.scala 27:72] - node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72] + node _T_1025 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2274:38] + node _T_1026 = not(_T_1025) @[dec_tlu_ctl.scala 2274:24] + node _T_1027 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1029 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1030 = bits(_T_1029, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1031 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1032 = bits(_T_1031, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1033 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1036 = and(io.tlu_i0_commit_cmt, _T_1035) @[dec_tlu_ctl.scala 2278:94] + node _T_1037 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1039 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1040 = and(io.tlu_i0_commit_cmt, _T_1039) @[dec_tlu_ctl.scala 2279:94] + node _T_1041 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1042 = and(_T_1040, _T_1041) @[dec_tlu_ctl.scala 2279:115] + node _T_1043 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1045 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1046 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1047 = and(_T_1045, _T_1046) @[dec_tlu_ctl.scala 2280:115] + node _T_1048 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1050 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1051 = bits(_T_1050, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1052 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1054 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1059 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1060 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1061 = bits(_T_1060, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1062 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1063 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1064 = bits(_T_1063, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1065 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1069 = and(_T_1068, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1070 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1074 = and(_T_1072, _T_1073) @[dec_tlu_ctl.scala 2289:101] + node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1106 = or(_T_1104, _T_1105) @[dec_tlu_ctl.scala 2299:101] + node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1111 = bits(_T_1110, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1117 = bits(_T_1116, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1119 = bits(_T_1118, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1121 = bits(_T_1120, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1123 = bits(_T_1122, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1125 = bits(_T_1124, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1127 = bits(_T_1126, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1129 = bits(_T_1128, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1131 = bits(_T_1130, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1135 = bits(_T_1134, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1139 = bits(_T_1138, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1141 = bits(_T_1140, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1143 = bits(_T_1142, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1147 = bits(_T_1146, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_1149 = bits(_T_1148, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_1151 = bits(_T_1150, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_1153 = bits(_T_1152, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_1161 = bits(_T_1160, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1163 = bits(_T_1162, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1164 = not(_T_1163) @[dec_tlu_ctl.scala 2322:73] + node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_1166 = bits(_T_1165, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_1169 = not(_T_1168) @[dec_tlu_ctl.scala 2323:73] + node _T_1170 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_1171 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_1172 = and(_T_1170, _T_1171) @[dec_tlu_ctl.scala 2323:113] + node _T_1173 = orr(_T_1172) @[dec_tlu_ctl.scala 2323:125] + node _T_1174 = and(_T_1169, _T_1173) @[dec_tlu_ctl.scala 2323:98] + node _T_1175 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1177 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_1178 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_1179 = bits(_T_1178, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1180 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1181 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1183 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_1184 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_1185 = bits(_T_1184, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1186 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_1187 = bits(_T_1186, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1188 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_1189 = bits(_T_1188, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1190 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_1191 = bits(_T_1190, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1192 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_1193 = bits(_T_1192, 0, 0) @[dec_tlu_ctl.scala 2332:62] + node _T_1194 = mux(_T_1028, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1032, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1034, _T_1036, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1038, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1044, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1049, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1051, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1053, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1055, _T_1056, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1058, _T_1059, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1061, _T_1062, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1064, _T_1065, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1067, _T_1069, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1071, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = mux(_T_1166, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1243 = mux(_T_1176, _T_1177, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1244 = mux(_T_1179, _T_1180, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1245 = mux(_T_1182, _T_1183, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1246 = mux(_T_1185, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1247 = mux(_T_1187, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1248 = mux(_T_1189, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1249 = mux(_T_1191, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1250 = mux(_T_1193, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1251 = or(_T_1194, _T_1195) @[Mux.scala 27:72] node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72] node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72] node _T_1254 = or(_T_1253, _T_1198) @[Mux.scala 27:72] @@ -74695,238 +74695,238 @@ circuit quasar_wrapper : node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72] node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72] node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72] - wire _T_1306 : UInt<1> @[Mux.scala 27:72] - _T_1306 <= _T_1305 @[Mux.scala 27:72] - node _T_1307 = and(_T_1025, _T_1306) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[0] <= _T_1307 @[dec_tlu_ctl.scala 2274:19] - node _T_1308 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2274:38] - node _T_1309 = not(_T_1308) @[dec_tlu_ctl.scala 2274:24] - node _T_1310 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1312 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1314 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1315 = bits(_T_1314, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1316 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1318 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1319 = and(io.tlu_i0_commit_cmt, _T_1318) @[dec_tlu_ctl.scala 2278:94] - node _T_1320 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1321 = bits(_T_1320, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1322 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1323 = and(io.tlu_i0_commit_cmt, _T_1322) @[dec_tlu_ctl.scala 2279:94] - node _T_1324 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1325 = and(_T_1323, _T_1324) @[dec_tlu_ctl.scala 2279:115] - node _T_1326 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1328 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1329 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1330 = and(_T_1328, _T_1329) @[dec_tlu_ctl.scala 2280:115] - node _T_1331 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1333 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1335 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1337 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1342 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1346 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1347 = bits(_T_1346, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1348 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1352 = and(_T_1351, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1353 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1357 = and(_T_1355, _T_1356) @[dec_tlu_ctl.scala 2289:101] - node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1380 = bits(_T_1379, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1389 = or(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2299:101] - node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_1444 = bits(_T_1443, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1446 = bits(_T_1445, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1447 = not(_T_1446) @[dec_tlu_ctl.scala 2322:73] - node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_1452 = not(_T_1451) @[dec_tlu_ctl.scala 2323:73] - node _T_1453 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_1454 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_1455 = and(_T_1453, _T_1454) @[dec_tlu_ctl.scala 2323:113] - node _T_1456 = orr(_T_1455) @[dec_tlu_ctl.scala 2323:125] - node _T_1457 = and(_T_1452, _T_1456) @[dec_tlu_ctl.scala 2323:98] - node _T_1458 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1460 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_1461 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1463 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1464 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1469 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_1470 = bits(_T_1469, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1471 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_1472 = bits(_T_1471, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1473 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_1474 = bits(_T_1473, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1475 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_1476 = bits(_T_1475, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1477 = mux(_T_1311, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1479 = mux(_T_1315, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1480 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1481 = mux(_T_1321, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1482 = mux(_T_1327, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1483 = mux(_T_1332, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1484 = mux(_T_1334, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1485 = mux(_T_1336, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1486 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1487 = mux(_T_1341, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1488 = mux(_T_1344, _T_1345, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1489 = mux(_T_1347, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1490 = mux(_T_1350, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1491 = mux(_T_1354, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1492 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1493 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1494 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1495 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1496 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1497 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1498 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1499 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1500 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1501 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1502 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1503 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1504 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1505 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1506 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1507 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1508 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1509 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1510 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1511 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1512 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1513 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1514 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1515 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1516 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1517 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1518 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1519 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1520 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1521 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1522 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1523 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1524 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1525 = mux(_T_1449, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1526 = mux(_T_1459, _T_1460, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1527 = mux(_T_1462, _T_1463, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1528 = mux(_T_1465, _T_1466, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1529 = mux(_T_1468, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1530 = mux(_T_1470, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1531 = mux(_T_1472, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1532 = mux(_T_1474, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1533 = mux(_T_1476, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1534 = or(_T_1477, _T_1478) @[Mux.scala 27:72] - node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72] + node _T_1306 = or(_T_1305, _T_1250) @[Mux.scala 27:72] + wire _T_1307 : UInt<1> @[Mux.scala 27:72] + _T_1307 <= _T_1306 @[Mux.scala 27:72] + node _T_1308 = and(_T_1026, _T_1307) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[0] <= _T_1308 @[dec_tlu_ctl.scala 2274:19] + node _T_1309 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2274:38] + node _T_1310 = not(_T_1309) @[dec_tlu_ctl.scala 2274:24] + node _T_1311 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1312 = bits(_T_1311, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1313 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1314 = bits(_T_1313, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1315 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1316 = bits(_T_1315, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1317 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1318 = bits(_T_1317, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1320 = and(io.tlu_i0_commit_cmt, _T_1319) @[dec_tlu_ctl.scala 2278:94] + node _T_1321 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1323 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1324 = and(io.tlu_i0_commit_cmt, _T_1323) @[dec_tlu_ctl.scala 2279:94] + node _T_1325 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1326 = and(_T_1324, _T_1325) @[dec_tlu_ctl.scala 2279:115] + node _T_1327 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1329 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1330 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1331 = and(_T_1329, _T_1330) @[dec_tlu_ctl.scala 2280:115] + node _T_1332 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1334 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1335 = bits(_T_1334, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1336 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1338 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1343 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1345 = bits(_T_1344, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1348 = bits(_T_1347, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1353 = and(_T_1352, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1354 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1357 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1358 = and(_T_1356, _T_1357) @[dec_tlu_ctl.scala 2289:101] + node _T_1359 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1362 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1365 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1368 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1371 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1374 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1377 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1380 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1382 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1383 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1385 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1386 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1389 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1390 = or(_T_1388, _T_1389) @[dec_tlu_ctl.scala 2299:101] + node _T_1391 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1393 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1394 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1395 = bits(_T_1394, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1396 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1397 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1399 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1400 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1401 = bits(_T_1400, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1402 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1403 = bits(_T_1402, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1404 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1405 = bits(_T_1404, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1406 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1407 = bits(_T_1406, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1408 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1409 = bits(_T_1408, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1410 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1411 = bits(_T_1410, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1412 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1413 = bits(_T_1412, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1414 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1415 = bits(_T_1414, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1416 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1417 = or(_T_1416, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1418 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1419 = bits(_T_1418, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1420 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1421 = or(_T_1420, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1422 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1423 = bits(_T_1422, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1424 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1425 = bits(_T_1424, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1426 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1427 = bits(_T_1426, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1428 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1429 = and(_T_1428, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1430 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1431 = bits(_T_1430, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1432 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_1433 = bits(_T_1432, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1434 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_1435 = bits(_T_1434, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1436 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_1437 = bits(_T_1436, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1438 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1440 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1442 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1444 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_1445 = bits(_T_1444, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1446 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1447 = bits(_T_1446, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1448 = not(_T_1447) @[dec_tlu_ctl.scala 2322:73] + node _T_1449 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_1450 = bits(_T_1449, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1451 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_1453 = not(_T_1452) @[dec_tlu_ctl.scala 2323:73] + node _T_1454 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_1455 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_1456 = and(_T_1454, _T_1455) @[dec_tlu_ctl.scala 2323:113] + node _T_1457 = orr(_T_1456) @[dec_tlu_ctl.scala 2323:125] + node _T_1458 = and(_T_1453, _T_1457) @[dec_tlu_ctl.scala 2323:98] + node _T_1459 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1461 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_1462 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_1463 = bits(_T_1462, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1464 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1465 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1467 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_1469 = bits(_T_1468, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_1471 = bits(_T_1470, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_1473 = bits(_T_1472, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_1475 = bits(_T_1474, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1476 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_1477 = bits(_T_1476, 0, 0) @[dec_tlu_ctl.scala 2332:62] + node _T_1478 = mux(_T_1312, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1314, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1316, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1318, _T_1320, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1322, _T_1326, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1328, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1333, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1335, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1337, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1348, _T_1349, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1351, _T_1353, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1355, _T_1358, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1360, _T_1361, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1363, _T_1364, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1366, _T_1367, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1369, _T_1370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1372, _T_1373, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1375, _T_1376, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1378, _T_1379, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1381, _T_1382, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1384, _T_1385, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1387, _T_1390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1392, _T_1393, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1395, _T_1396, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1398, _T_1399, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1401, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1403, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1405, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1407, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1409, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1411, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1413, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1415, _T_1417, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1419, _T_1421, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1423, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1425, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1427, _T_1429, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1431, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1433, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1435, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1437, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1439, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1441, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1443, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1445, _T_1448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1450, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1460, _T_1461, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1463, _T_1464, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1466, _T_1467, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1469, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = mux(_T_1471, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1532 = mux(_T_1473, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1533 = mux(_T_1475, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1534 = mux(_T_1477, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1535 = or(_T_1478, _T_1479) @[Mux.scala 27:72] node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72] node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72] node _T_1538 = or(_T_1537, _T_1482) @[Mux.scala 27:72] @@ -74981,238 +74981,238 @@ circuit quasar_wrapper : node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72] node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72] node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72] - wire _T_1590 : UInt<1> @[Mux.scala 27:72] - _T_1590 <= _T_1589 @[Mux.scala 27:72] - node _T_1591 = and(_T_1309, _T_1590) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[1] <= _T_1591 @[dec_tlu_ctl.scala 2274:19] - node _T_1592 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2274:38] - node _T_1593 = not(_T_1592) @[dec_tlu_ctl.scala 2274:24] - node _T_1594 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1596 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1598 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1599 = bits(_T_1598, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1600 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1602 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1603 = and(io.tlu_i0_commit_cmt, _T_1602) @[dec_tlu_ctl.scala 2278:94] - node _T_1604 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1605 = bits(_T_1604, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1606 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1607 = and(io.tlu_i0_commit_cmt, _T_1606) @[dec_tlu_ctl.scala 2279:94] - node _T_1608 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1609 = and(_T_1607, _T_1608) @[dec_tlu_ctl.scala 2279:115] - node _T_1610 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1612 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1613 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1614 = and(_T_1612, _T_1613) @[dec_tlu_ctl.scala 2280:115] - node _T_1615 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1617 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1619 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1621 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1626 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1631 = bits(_T_1630, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1636 = and(_T_1635, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1637 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1640 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1641 = and(_T_1639, _T_1640) @[dec_tlu_ctl.scala 2289:101] - node _T_1642 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1645 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1648 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1651 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1654 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1657 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1660 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1663 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1664 = bits(_T_1663, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1665 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1666 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1668 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1669 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1673 = or(_T_1671, _T_1672) @[dec_tlu_ctl.scala 2299:101] - node _T_1674 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1676 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1679 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1680 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1682 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1683 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1685 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1687 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1689 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1691 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1693 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1695 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1697 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1699 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1700 = or(_T_1699, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1701 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1703 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1704 = or(_T_1703, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1705 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1707 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1709 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1711 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1712 = and(_T_1711, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1717 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1719 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1721 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1723 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1725 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1727 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_1728 = bits(_T_1727, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1729 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1730 = bits(_T_1729, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1731 = not(_T_1730) @[dec_tlu_ctl.scala 2322:73] - node _T_1732 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1734 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_1736 = not(_T_1735) @[dec_tlu_ctl.scala 2323:73] - node _T_1737 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_1738 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_1739 = and(_T_1737, _T_1738) @[dec_tlu_ctl.scala 2323:113] - node _T_1740 = orr(_T_1739) @[dec_tlu_ctl.scala 2323:125] - node _T_1741 = and(_T_1736, _T_1740) @[dec_tlu_ctl.scala 2323:98] - node _T_1742 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1744 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_1745 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1747 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1748 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1750 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_1754 = bits(_T_1753, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_1756 = bits(_T_1755, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_1758 = bits(_T_1757, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1759 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_1760 = bits(_T_1759, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1761 = mux(_T_1595, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1762 = mux(_T_1597, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1763 = mux(_T_1599, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1764 = mux(_T_1601, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1765 = mux(_T_1605, _T_1609, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1766 = mux(_T_1611, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1767 = mux(_T_1616, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1768 = mux(_T_1618, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1769 = mux(_T_1620, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1770 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1771 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1772 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1773 = mux(_T_1631, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1774 = mux(_T_1634, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1775 = mux(_T_1638, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1776 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1777 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1778 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1779 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1780 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1781 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1782 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1783 = mux(_T_1664, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1784 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1785 = mux(_T_1670, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1786 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1787 = mux(_T_1678, _T_1679, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1788 = mux(_T_1681, _T_1682, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1789 = mux(_T_1684, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1790 = mux(_T_1686, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1791 = mux(_T_1688, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1792 = mux(_T_1690, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1793 = mux(_T_1692, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1794 = mux(_T_1694, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1795 = mux(_T_1696, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1796 = mux(_T_1698, _T_1700, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1797 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1798 = mux(_T_1706, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1799 = mux(_T_1708, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1800 = mux(_T_1710, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1801 = mux(_T_1714, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1802 = mux(_T_1716, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1803 = mux(_T_1718, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1804 = mux(_T_1720, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1805 = mux(_T_1722, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1806 = mux(_T_1724, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1807 = mux(_T_1726, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1808 = mux(_T_1728, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1809 = mux(_T_1733, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1810 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1811 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1812 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1813 = mux(_T_1752, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1814 = mux(_T_1754, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1815 = mux(_T_1756, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1816 = mux(_T_1758, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1817 = mux(_T_1760, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1818 = or(_T_1761, _T_1762) @[Mux.scala 27:72] - node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72] + node _T_1590 = or(_T_1589, _T_1534) @[Mux.scala 27:72] + wire _T_1591 : UInt<1> @[Mux.scala 27:72] + _T_1591 <= _T_1590 @[Mux.scala 27:72] + node _T_1592 = and(_T_1310, _T_1591) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[1] <= _T_1592 @[dec_tlu_ctl.scala 2274:19] + node _T_1593 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2274:38] + node _T_1594 = not(_T_1593) @[dec_tlu_ctl.scala 2274:24] + node _T_1595 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1596 = bits(_T_1595, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1597 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1598 = bits(_T_1597, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1599 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1600 = bits(_T_1599, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1601 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1602 = bits(_T_1601, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[dec_tlu_ctl.scala 2278:94] + node _T_1605 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1607 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1608 = and(io.tlu_i0_commit_cmt, _T_1607) @[dec_tlu_ctl.scala 2279:94] + node _T_1609 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1610 = and(_T_1608, _T_1609) @[dec_tlu_ctl.scala 2279:115] + node _T_1611 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1613 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1614 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1615 = and(_T_1613, _T_1614) @[dec_tlu_ctl.scala 2280:115] + node _T_1616 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1618 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1619 = bits(_T_1618, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1620 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1622 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1627 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1628 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1629 = bits(_T_1628, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1630 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1631 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1632 = bits(_T_1631, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1633 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1637 = and(_T_1636, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1638 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1641 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1642 = and(_T_1640, _T_1641) @[dec_tlu_ctl.scala 2289:101] + node _T_1643 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1646 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1649 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1652 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1655 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1658 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1661 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1664 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1666 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1667 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1669 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1670 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1673 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1674 = or(_T_1672, _T_1673) @[dec_tlu_ctl.scala 2299:101] + node _T_1675 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1677 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1678 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1679 = bits(_T_1678, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1680 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1681 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1683 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1685 = bits(_T_1684, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1687 = bits(_T_1686, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1688 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1689 = bits(_T_1688, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1690 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1691 = bits(_T_1690, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1692 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1693 = bits(_T_1692, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1694 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1695 = bits(_T_1694, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1696 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1697 = bits(_T_1696, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1698 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1699 = bits(_T_1698, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1700 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1701 = or(_T_1700, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1702 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1703 = bits(_T_1702, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1704 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1705 = or(_T_1704, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1706 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1707 = bits(_T_1706, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1708 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1709 = bits(_T_1708, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1710 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1711 = bits(_T_1710, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1712 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1713 = and(_T_1712, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1715 = bits(_T_1714, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_1717 = bits(_T_1716, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_1719 = bits(_T_1718, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_1721 = bits(_T_1720, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1724 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1726 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1728 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_1729 = bits(_T_1728, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1730 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1731 = bits(_T_1730, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1732 = not(_T_1731) @[dec_tlu_ctl.scala 2322:73] + node _T_1733 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_1734 = bits(_T_1733, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1735 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_1737 = not(_T_1736) @[dec_tlu_ctl.scala 2323:73] + node _T_1738 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_1739 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_1740 = and(_T_1738, _T_1739) @[dec_tlu_ctl.scala 2323:113] + node _T_1741 = orr(_T_1740) @[dec_tlu_ctl.scala 2323:125] + node _T_1742 = and(_T_1737, _T_1741) @[dec_tlu_ctl.scala 2323:98] + node _T_1743 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1745 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_1746 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_1747 = bits(_T_1746, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1749 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1751 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_1752 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_1753 = bits(_T_1752, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1754 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_1755 = bits(_T_1754, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1756 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_1757 = bits(_T_1756, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1758 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_1759 = bits(_T_1758, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1760 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_1761 = bits(_T_1760, 0, 0) @[dec_tlu_ctl.scala 2332:62] + node _T_1762 = mux(_T_1596, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1598, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1600, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1602, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1606, _T_1610, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1612, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1617, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1619, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1621, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1626, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1629, _T_1630, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1635, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1639, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1662, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1665, _T_1666, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1668, _T_1669, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1671, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1676, _T_1677, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1682, _T_1683, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1685, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1687, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1689, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1691, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1693, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1695, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1697, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1699, _T_1701, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1703, _T_1705, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1707, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1709, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1711, _T_1713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1715, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1717, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1719, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1721, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1723, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1725, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1727, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1729, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = mux(_T_1734, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1811 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1812 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1813 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1814 = mux(_T_1753, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1815 = mux(_T_1755, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1816 = mux(_T_1757, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1817 = mux(_T_1759, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1818 = mux(_T_1761, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1819 = or(_T_1762, _T_1763) @[Mux.scala 27:72] node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72] node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72] node _T_1822 = or(_T_1821, _T_1766) @[Mux.scala 27:72] @@ -75267,238 +75267,238 @@ circuit quasar_wrapper : node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72] node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72] node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72] - wire _T_1874 : UInt<1> @[Mux.scala 27:72] - _T_1874 <= _T_1873 @[Mux.scala 27:72] - node _T_1875 = and(_T_1593, _T_1874) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[2] <= _T_1875 @[dec_tlu_ctl.scala 2274:19] - node _T_1876 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2274:38] - node _T_1877 = not(_T_1876) @[dec_tlu_ctl.scala 2274:24] - node _T_1878 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] - node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1880 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] - node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1882 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] - node _T_1883 = bits(_T_1882, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1884 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] - node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1886 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] - node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[dec_tlu_ctl.scala 2278:94] - node _T_1888 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] - node _T_1889 = bits(_T_1888, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1890 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] - node _T_1891 = and(io.tlu_i0_commit_cmt, _T_1890) @[dec_tlu_ctl.scala 2279:94] - node _T_1892 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1893 = and(_T_1891, _T_1892) @[dec_tlu_ctl.scala 2279:115] - node _T_1894 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] - node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1896 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] - node _T_1897 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] - node _T_1898 = and(_T_1896, _T_1897) @[dec_tlu_ctl.scala 2280:115] - node _T_1899 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] - node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1901 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] - node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1903 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] - node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1905 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] - node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] - node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] - node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1910 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] - node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] - node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1914 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] - node _T_1915 = bits(_T_1914, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1916 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] - node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] - node _T_1920 = and(_T_1919, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] - node _T_1921 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] - node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] - node _T_1924 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] - node _T_1925 = and(_T_1923, _T_1924) @[dec_tlu_ctl.scala 2289:101] - node _T_1926 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] - node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] - node _T_1929 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] - node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] - node _T_1932 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] - node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] - node _T_1935 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] - node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] - node _T_1938 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] - node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] - node _T_1941 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] - node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] - node _T_1944 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] - node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] - node _T_1947 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] - node _T_1948 = bits(_T_1947, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1949 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] - node _T_1950 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] - node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1952 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] - node _T_1953 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] - node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1955 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] - node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] - node _T_1957 = or(_T_1955, _T_1956) @[dec_tlu_ctl.scala 2299:101] - node _T_1958 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] - node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1960 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] - node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] - node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1963 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] - node _T_1964 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] - node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1966 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] - node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] - node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] - node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1971 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] - node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1973 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] - node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1975 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] - node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1977 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] - node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1979 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] - node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1981 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] - node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1983 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] - node _T_1984 = or(_T_1983, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] - node _T_1985 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] - node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1987 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] - node _T_1988 = or(_T_1987, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] - node _T_1989 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] - node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1991 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] - node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1993 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] - node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1995 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] - node _T_1996 = and(_T_1995, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] - node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] - node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] - node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] - node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] - node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] - node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_2007 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] - node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_2009 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] - node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_2011 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] - node _T_2012 = bits(_T_2011, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_2013 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_2014 = bits(_T_2013, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_2015 = not(_T_2014) @[dec_tlu_ctl.scala 2322:73] - node _T_2016 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] - node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_2018 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] - node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2323:84] - node _T_2020 = not(_T_2019) @[dec_tlu_ctl.scala 2323:73] - node _T_2021 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] - node _T_2022 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] - node _T_2023 = and(_T_2021, _T_2022) @[dec_tlu_ctl.scala 2323:113] - node _T_2024 = orr(_T_2023) @[dec_tlu_ctl.scala 2323:125] - node _T_2025 = and(_T_2020, _T_2024) @[dec_tlu_ctl.scala 2323:98] - node _T_2026 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] - node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_2028 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] - node _T_2029 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] - node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_2032 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] - node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_2034 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] - node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] - node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_2037 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] - node _T_2038 = bits(_T_2037, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_2039 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] - node _T_2040 = bits(_T_2039, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_2041 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] - node _T_2042 = bits(_T_2041, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_2043 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] - node _T_2044 = bits(_T_2043, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_2045 = mux(_T_1879, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2046 = mux(_T_1881, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_1883, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_1885, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_1889, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_1895, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_1900, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_1902, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_1904, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_1909, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_1912, _T_1913, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_1915, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = mux(_T_1918, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2059 = mux(_T_1922, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2060 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2061 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2062 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2063 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2064 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2065 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2066 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2067 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2068 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2069 = mux(_T_1954, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2070 = mux(_T_1959, _T_1960, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2071 = mux(_T_1962, _T_1963, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2072 = mux(_T_1965, _T_1966, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2073 = mux(_T_1968, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2074 = mux(_T_1970, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2075 = mux(_T_1972, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2076 = mux(_T_1974, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2077 = mux(_T_1976, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2078 = mux(_T_1978, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2079 = mux(_T_1980, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2080 = mux(_T_1982, _T_1984, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2081 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2082 = mux(_T_1990, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2083 = mux(_T_1992, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2084 = mux(_T_1994, _T_1996, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2085 = mux(_T_1998, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2086 = mux(_T_2000, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2087 = mux(_T_2002, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2088 = mux(_T_2004, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2089 = mux(_T_2006, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2090 = mux(_T_2008, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2091 = mux(_T_2010, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2092 = mux(_T_2012, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2093 = mux(_T_2017, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2094 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2095 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2096 = mux(_T_2033, _T_2034, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2097 = mux(_T_2036, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2098 = mux(_T_2038, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2099 = mux(_T_2040, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2100 = mux(_T_2042, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2101 = mux(_T_2044, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2102 = or(_T_2045, _T_2046) @[Mux.scala 27:72] - node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72] + node _T_1874 = or(_T_1873, _T_1818) @[Mux.scala 27:72] + wire _T_1875 : UInt<1> @[Mux.scala 27:72] + _T_1875 <= _T_1874 @[Mux.scala 27:72] + node _T_1876 = and(_T_1594, _T_1875) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[2] <= _T_1876 @[dec_tlu_ctl.scala 2274:19] + node _T_1877 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2274:38] + node _T_1878 = not(_T_1877) @[dec_tlu_ctl.scala 2274:24] + node _T_1879 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1880 = bits(_T_1879, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1881 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1882 = bits(_T_1881, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1883 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1884 = bits(_T_1883, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1885 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1886 = bits(_T_1885, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1888 = and(io.tlu_i0_commit_cmt, _T_1887) @[dec_tlu_ctl.scala 2278:94] + node _T_1889 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1891 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1892 = and(io.tlu_i0_commit_cmt, _T_1891) @[dec_tlu_ctl.scala 2279:94] + node _T_1893 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1894 = and(_T_1892, _T_1893) @[dec_tlu_ctl.scala 2279:115] + node _T_1895 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1897 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1898 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1899 = and(_T_1897, _T_1898) @[dec_tlu_ctl.scala 2280:115] + node _T_1900 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1902 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1903 = bits(_T_1902, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1904 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1906 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1911 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1912 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1913 = bits(_T_1912, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1914 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1915 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1916 = bits(_T_1915, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1917 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1921 = and(_T_1920, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1922 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1925 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1926 = and(_T_1924, _T_1925) @[dec_tlu_ctl.scala 2289:101] + node _T_1927 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1930 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1933 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1936 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1939 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1942 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1945 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1948 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1951 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1954 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1957 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1958 = or(_T_1956, _T_1957) @[dec_tlu_ctl.scala 2299:101] + node _T_1959 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1961 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1963 = bits(_T_1962, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1964 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1967 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1968 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1969 = bits(_T_1968, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1970 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1971 = bits(_T_1970, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1972 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1973 = bits(_T_1972, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1974 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1975 = bits(_T_1974, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1976 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1977 = bits(_T_1976, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1978 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1979 = bits(_T_1978, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1980 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1981 = bits(_T_1980, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1982 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1983 = bits(_T_1982, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1984 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1985 = or(_T_1984, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1986 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1987 = bits(_T_1986, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1988 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1989 = or(_T_1988, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1990 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1991 = bits(_T_1990, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1992 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1993 = bits(_T_1992, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1994 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1995 = bits(_T_1994, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1996 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1997 = and(_T_1996, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1998 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1999 = bits(_T_1998, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_2000 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_2001 = bits(_T_2000, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_2002 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_2003 = bits(_T_2002, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_2004 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_2005 = bits(_T_2004, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_2006 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_2008 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_2010 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_2012 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_2013 = bits(_T_2012, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_2014 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_2015 = bits(_T_2014, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_2016 = not(_T_2015) @[dec_tlu_ctl.scala 2322:73] + node _T_2017 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_2018 = bits(_T_2017, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_2019 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_2021 = not(_T_2020) @[dec_tlu_ctl.scala 2323:73] + node _T_2022 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_2023 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_2024 = and(_T_2022, _T_2023) @[dec_tlu_ctl.scala 2323:113] + node _T_2025 = orr(_T_2024) @[dec_tlu_ctl.scala 2323:125] + node _T_2026 = and(_T_2021, _T_2025) @[dec_tlu_ctl.scala 2323:98] + node _T_2027 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_2029 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_2030 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_2031 = bits(_T_2030, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_2032 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_2033 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_2035 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_2037 = bits(_T_2036, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_2039 = bits(_T_2038, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_2041 = bits(_T_2040, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_2042 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_2043 = bits(_T_2042, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_2044 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_2045 = bits(_T_2044, 0, 0) @[dec_tlu_ctl.scala 2332:62] + node _T_2046 = mux(_T_1880, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1882, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1884, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1886, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1890, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1896, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1901, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1903, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1905, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1907, _T_1908, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1910, _T_1911, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1913, _T_1914, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1916, _T_1917, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1919, _T_1921, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1923, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1955, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1966, _T_1967, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1969, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1971, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1973, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1975, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1977, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1979, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1981, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1983, _T_1985, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_1987, _T_1989, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_1991, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_1993, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_1995, _T_1997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_1999, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2001, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2003, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2005, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2007, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2009, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2011, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2013, _T_2016, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = mux(_T_2018, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2095 = mux(_T_2028, _T_2029, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2096 = mux(_T_2031, _T_2032, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2097 = mux(_T_2034, _T_2035, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2098 = mux(_T_2037, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2099 = mux(_T_2039, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2100 = mux(_T_2041, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2101 = mux(_T_2043, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2102 = mux(_T_2045, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2103 = or(_T_2046, _T_2047) @[Mux.scala 27:72] node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72] node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72] node _T_2106 = or(_T_2105, _T_2050) @[Mux.scala 27:72] @@ -75553,576 +75553,576 @@ circuit quasar_wrapper : node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72] node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72] node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72] - wire _T_2158 : UInt<1> @[Mux.scala 27:72] - _T_2158 <= _T_2157 @[Mux.scala 27:72] - node _T_2159 = and(_T_1877, _T_2158) @[dec_tlu_ctl.scala 2274:44] - mhpmc_inc_r[3] <= _T_2159 @[dec_tlu_ctl.scala 2274:19] - reg _T_2160 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] - _T_2160 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2335:53] - mhpmc_inc_r_d1[0] <= _T_2160 @[dec_tlu_ctl.scala 2335:20] - reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] - _T_2161 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2336:53] - mhpmc_inc_r_d1[1] <= _T_2161 @[dec_tlu_ctl.scala 2336:20] - reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] - _T_2162 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2337:53] - mhpmc_inc_r_d1[2] <= _T_2162 @[dec_tlu_ctl.scala 2337:20] - reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:53] - _T_2163 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2338:53] - mhpmc_inc_r_d1[3] <= _T_2163 @[dec_tlu_ctl.scala 2338:20] + node _T_2158 = or(_T_2157, _T_2102) @[Mux.scala 27:72] + wire _T_2159 : UInt<1> @[Mux.scala 27:72] + _T_2159 <= _T_2158 @[Mux.scala 27:72] + node _T_2160 = and(_T_1878, _T_2159) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[3] <= _T_2160 @[dec_tlu_ctl.scala 2274:19] + reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] + _T_2161 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2335:53] + mhpmc_inc_r_d1[0] <= _T_2161 @[dec_tlu_ctl.scala 2335:20] + reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] + _T_2162 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2336:53] + mhpmc_inc_r_d1[1] <= _T_2162 @[dec_tlu_ctl.scala 2336:20] + reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] + _T_2163 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2337:53] + mhpmc_inc_r_d1[2] <= _T_2163 @[dec_tlu_ctl.scala 2337:20] + reg _T_2164 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:53] + _T_2164 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2338:53] + mhpmc_inc_r_d1[3] <= _T_2164 @[dec_tlu_ctl.scala 2338:20] reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2339:56] perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2339:56] - node _T_2164 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:53] - node _T_2165 = and(io.dec_tlu_dbg_halted, _T_2164) @[dec_tlu_ctl.scala 2342:44] - node _T_2166 = or(_T_2165, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2342:67] - perfcnt_halted <= _T_2166 @[dec_tlu_ctl.scala 2342:17] - node _T_2167 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2343:70] - node _T_2168 = and(io.dec_tlu_dbg_halted, _T_2167) @[dec_tlu_ctl.scala 2343:61] - node _T_2169 = not(_T_2168) @[dec_tlu_ctl.scala 2343:37] - node _T_2170 = bits(_T_2169, 0, 0) @[Bitwise.scala 72:15] - node _T_2171 = mux(_T_2170, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2172 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2343:104] - node _T_2173 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2343:120] - node _T_2174 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2343:136] - node _T_2175 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2343:152] - node _T_2176 = cat(_T_2174, _T_2175) @[Cat.scala 29:58] - node _T_2177 = cat(_T_2172, _T_2173) @[Cat.scala 29:58] - node _T_2178 = cat(_T_2177, _T_2176) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2171, _T_2178) @[dec_tlu_ctl.scala 2343:86] - node _T_2179 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2345:88] - node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2345:67] - node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2345:65] - node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2345:45] - node _T_2183 = and(mhpmc_inc_r_d1[0], _T_2182) @[dec_tlu_ctl.scala 2345:43] - io.dec_tlu_perfcnt0 <= _T_2183 @[dec_tlu_ctl.scala 2345:22] - node _T_2184 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2346:88] - node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2346:67] - node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2346:65] - node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2346:45] - node _T_2188 = and(mhpmc_inc_r_d1[1], _T_2187) @[dec_tlu_ctl.scala 2346:43] - io.dec_tlu_perfcnt1 <= _T_2188 @[dec_tlu_ctl.scala 2346:22] - node _T_2189 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2347:88] - node _T_2190 = not(_T_2189) @[dec_tlu_ctl.scala 2347:67] - node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[dec_tlu_ctl.scala 2347:65] - node _T_2192 = not(_T_2191) @[dec_tlu_ctl.scala 2347:45] - node _T_2193 = and(mhpmc_inc_r_d1[2], _T_2192) @[dec_tlu_ctl.scala 2347:43] - io.dec_tlu_perfcnt2 <= _T_2193 @[dec_tlu_ctl.scala 2347:22] - node _T_2194 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2348:88] - node _T_2195 = not(_T_2194) @[dec_tlu_ctl.scala 2348:67] - node _T_2196 = and(perfcnt_halted_d1, _T_2195) @[dec_tlu_ctl.scala 2348:65] - node _T_2197 = not(_T_2196) @[dec_tlu_ctl.scala 2348:45] - node _T_2198 = and(mhpmc_inc_r_d1[3], _T_2197) @[dec_tlu_ctl.scala 2348:43] - io.dec_tlu_perfcnt3 <= _T_2198 @[dec_tlu_ctl.scala 2348:22] - node _T_2199 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] - node _T_2200 = eq(_T_2199, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2354:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2200) @[dec_tlu_ctl.scala 2354:43] - node _T_2201 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] - node _T_2202 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2355:61] - node _T_2203 = or(_T_2201, _T_2202) @[dec_tlu_ctl.scala 2355:39] - node _T_2204 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2355:86] - node mhpmc3_wr_en1 = and(_T_2203, _T_2204) @[dec_tlu_ctl.scala 2355:66] + node _T_2165 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:53] + node _T_2166 = and(io.dec_tlu_dbg_halted, _T_2165) @[dec_tlu_ctl.scala 2342:44] + node _T_2167 = or(_T_2166, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2342:67] + perfcnt_halted <= _T_2167 @[dec_tlu_ctl.scala 2342:17] + node _T_2168 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2343:70] + node _T_2169 = and(io.dec_tlu_dbg_halted, _T_2168) @[dec_tlu_ctl.scala 2343:61] + node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2343:37] + node _T_2171 = bits(_T_2170, 0, 0) @[Bitwise.scala 72:15] + node _T_2172 = mux(_T_2171, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2173 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2343:104] + node _T_2174 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2343:120] + node _T_2175 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2343:136] + node _T_2176 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2343:152] + node _T_2177 = cat(_T_2175, _T_2176) @[Cat.scala 29:58] + node _T_2178 = cat(_T_2173, _T_2174) @[Cat.scala 29:58] + node _T_2179 = cat(_T_2178, _T_2177) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2172, _T_2179) @[dec_tlu_ctl.scala 2343:86] + node _T_2180 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2345:88] + node _T_2181 = not(_T_2180) @[dec_tlu_ctl.scala 2345:67] + node _T_2182 = and(perfcnt_halted_d1, _T_2181) @[dec_tlu_ctl.scala 2345:65] + node _T_2183 = not(_T_2182) @[dec_tlu_ctl.scala 2345:45] + node _T_2184 = and(mhpmc_inc_r_d1[0], _T_2183) @[dec_tlu_ctl.scala 2345:43] + io.dec_tlu_perfcnt0 <= _T_2184 @[dec_tlu_ctl.scala 2345:22] + node _T_2185 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2346:88] + node _T_2186 = not(_T_2185) @[dec_tlu_ctl.scala 2346:67] + node _T_2187 = and(perfcnt_halted_d1, _T_2186) @[dec_tlu_ctl.scala 2346:65] + node _T_2188 = not(_T_2187) @[dec_tlu_ctl.scala 2346:45] + node _T_2189 = and(mhpmc_inc_r_d1[1], _T_2188) @[dec_tlu_ctl.scala 2346:43] + io.dec_tlu_perfcnt1 <= _T_2189 @[dec_tlu_ctl.scala 2346:22] + node _T_2190 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2347:88] + node _T_2191 = not(_T_2190) @[dec_tlu_ctl.scala 2347:67] + node _T_2192 = and(perfcnt_halted_d1, _T_2191) @[dec_tlu_ctl.scala 2347:65] + node _T_2193 = not(_T_2192) @[dec_tlu_ctl.scala 2347:45] + node _T_2194 = and(mhpmc_inc_r_d1[2], _T_2193) @[dec_tlu_ctl.scala 2347:43] + io.dec_tlu_perfcnt2 <= _T_2194 @[dec_tlu_ctl.scala 2347:22] + node _T_2195 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2348:88] + node _T_2196 = not(_T_2195) @[dec_tlu_ctl.scala 2348:67] + node _T_2197 = and(perfcnt_halted_d1, _T_2196) @[dec_tlu_ctl.scala 2348:65] + node _T_2198 = not(_T_2197) @[dec_tlu_ctl.scala 2348:45] + node _T_2199 = and(mhpmc_inc_r_d1[3], _T_2198) @[dec_tlu_ctl.scala 2348:43] + io.dec_tlu_perfcnt3 <= _T_2199 @[dec_tlu_ctl.scala 2348:22] + node _T_2200 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] + node _T_2201 = eq(_T_2200, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2354:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2201) @[dec_tlu_ctl.scala 2354:43] + node _T_2202 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] + node _T_2203 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2355:61] + node _T_2204 = or(_T_2202, _T_2203) @[dec_tlu_ctl.scala 2355:39] + node _T_2205 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2355:86] + node mhpmc3_wr_en1 = and(_T_2204, _T_2205) @[dec_tlu_ctl.scala 2355:66] node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2356:36] - node _T_2205 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2359:28] - node _T_2206 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2359:41] - node _T_2207 = cat(_T_2205, _T_2206) @[Cat.scala 29:58] - node _T_2208 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2209 = add(_T_2207, _T_2208) @[dec_tlu_ctl.scala 2359:49] - node _T_2210 = tail(_T_2209, 1) @[dec_tlu_ctl.scala 2359:49] - mhpmc3_incr <= _T_2210 @[dec_tlu_ctl.scala 2359:14] - node _T_2211 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2360:36] - node _T_2212 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2360:76] - node mhpmc3_ns = mux(_T_2211, io.dec_csr_wrdata_r, _T_2212) @[dec_tlu_ctl.scala 2360:21] - node _T_2213 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:42] + node _T_2206 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2359:28] + node _T_2207 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2359:41] + node _T_2208 = cat(_T_2206, _T_2207) @[Cat.scala 29:58] + node _T_2209 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2210 = add(_T_2208, _T_2209) @[dec_tlu_ctl.scala 2359:49] + node _T_2211 = tail(_T_2210, 1) @[dec_tlu_ctl.scala 2359:49] + mhpmc3_incr <= _T_2211 @[dec_tlu_ctl.scala 2359:14] + node _T_2212 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2360:36] + node _T_2213 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2360:76] + node mhpmc3_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[dec_tlu_ctl.scala 2360:21] + node _T_2214 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 352:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset rvclkhdr_26.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_26.io.en <= _T_2213 @[lib.scala 355:17] + rvclkhdr_26.io.en <= _T_2214 @[lib.scala 355:17] rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_2214 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_2214 <= mhpmc3_ns @[lib.scala 358:16] - mhpmc3 <= _T_2214 @[dec_tlu_ctl.scala 2362:9] - node _T_2215 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] - node _T_2216 = eq(_T_2215, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2364:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2216) @[dec_tlu_ctl.scala 2364:44] + reg _T_2215 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_2215 <= mhpmc3_ns @[lib.scala 358:16] + mhpmc3 <= _T_2215 @[dec_tlu_ctl.scala 2362:9] + node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] + node _T_2217 = eq(_T_2216, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2364:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[dec_tlu_ctl.scala 2364:44] node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2365:38] - node _T_2217 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] - node _T_2218 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] - node mhpmc3h_ns = mux(_T_2217, io.dec_csr_wrdata_r, _T_2218) @[dec_tlu_ctl.scala 2366:22] - node _T_2219 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2368:46] + node _T_2218 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] + node _T_2219 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] + node mhpmc3h_ns = mux(_T_2218, io.dec_csr_wrdata_r, _T_2219) @[dec_tlu_ctl.scala 2366:22] + node _T_2220 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2368:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 352:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset rvclkhdr_27.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_27.io.en <= _T_2219 @[lib.scala 355:17] + rvclkhdr_27.io.en <= _T_2220 @[lib.scala 355:17] rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_2220 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_2220 <= mhpmc3h_ns @[lib.scala 358:16] - mhpmc3h <= _T_2220 @[dec_tlu_ctl.scala 2368:10] - node _T_2221 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] - node _T_2222 = eq(_T_2221, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2373:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2222) @[dec_tlu_ctl.scala 2373:43] - node _T_2223 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] - node _T_2224 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2374:61] - node _T_2225 = or(_T_2223, _T_2224) @[dec_tlu_ctl.scala 2374:39] - node _T_2226 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2374:86] - node mhpmc4_wr_en1 = and(_T_2225, _T_2226) @[dec_tlu_ctl.scala 2374:66] + reg _T_2221 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_2221 <= mhpmc3h_ns @[lib.scala 358:16] + mhpmc3h <= _T_2221 @[dec_tlu_ctl.scala 2368:10] + node _T_2222 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] + node _T_2223 = eq(_T_2222, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2373:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2223) @[dec_tlu_ctl.scala 2373:43] + node _T_2224 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] + node _T_2225 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2374:61] + node _T_2226 = or(_T_2224, _T_2225) @[dec_tlu_ctl.scala 2374:39] + node _T_2227 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2374:86] + node mhpmc4_wr_en1 = and(_T_2226, _T_2227) @[dec_tlu_ctl.scala 2374:66] node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2375:36] - node _T_2227 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2379:28] - node _T_2228 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2379:41] - node _T_2229 = cat(_T_2227, _T_2228) @[Cat.scala 29:58] - node _T_2230 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2231 = add(_T_2229, _T_2230) @[dec_tlu_ctl.scala 2379:49] - node _T_2232 = tail(_T_2231, 1) @[dec_tlu_ctl.scala 2379:49] - mhpmc4_incr <= _T_2232 @[dec_tlu_ctl.scala 2379:14] - node _T_2233 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2380:36] - node _T_2234 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2380:63] - node _T_2235 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2380:82] - node mhpmc4_ns = mux(_T_2233, _T_2234, _T_2235) @[dec_tlu_ctl.scala 2380:21] - node _T_2236 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2381:43] + node _T_2228 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2379:28] + node _T_2229 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2379:41] + node _T_2230 = cat(_T_2228, _T_2229) @[Cat.scala 29:58] + node _T_2231 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2232 = add(_T_2230, _T_2231) @[dec_tlu_ctl.scala 2379:49] + node _T_2233 = tail(_T_2232, 1) @[dec_tlu_ctl.scala 2379:49] + mhpmc4_incr <= _T_2233 @[dec_tlu_ctl.scala 2379:14] + node _T_2234 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2380:36] + node _T_2235 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2380:63] + node _T_2236 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2380:82] + node mhpmc4_ns = mux(_T_2234, _T_2235, _T_2236) @[dec_tlu_ctl.scala 2380:21] + node _T_2237 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2381:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 352:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset rvclkhdr_28.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_28.io.en <= _T_2236 @[lib.scala 355:17] + rvclkhdr_28.io.en <= _T_2237 @[lib.scala 355:17] rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_2237 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_2237 <= mhpmc4_ns @[lib.scala 358:16] - mhpmc4 <= _T_2237 @[dec_tlu_ctl.scala 2381:9] - node _T_2238 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2383:66] - node _T_2239 = eq(_T_2238, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2383:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2239) @[dec_tlu_ctl.scala 2383:44] + reg _T_2238 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_2238 <= mhpmc4_ns @[lib.scala 358:16] + mhpmc4 <= _T_2238 @[dec_tlu_ctl.scala 2381:9] + node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2383:66] + node _T_2240 = eq(_T_2239, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2383:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[dec_tlu_ctl.scala 2383:44] node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2384:38] - node _T_2240 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2385:38] - node _T_2241 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2385:78] - node mhpmc4h_ns = mux(_T_2240, io.dec_csr_wrdata_r, _T_2241) @[dec_tlu_ctl.scala 2385:22] - node _T_2242 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] + node _T_2241 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2385:38] + node _T_2242 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2385:78] + node mhpmc4h_ns = mux(_T_2241, io.dec_csr_wrdata_r, _T_2242) @[dec_tlu_ctl.scala 2385:22] + node _T_2243 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 352:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset rvclkhdr_29.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_29.io.en <= _T_2242 @[lib.scala 355:17] + rvclkhdr_29.io.en <= _T_2243 @[lib.scala 355:17] rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_2243 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_2243 <= mhpmc4h_ns @[lib.scala 358:16] - mhpmc4h <= _T_2243 @[dec_tlu_ctl.scala 2386:10] - node _T_2244 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2392:65] - node _T_2245 = eq(_T_2244, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2392:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2245) @[dec_tlu_ctl.scala 2392:43] - node _T_2246 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2393:23] - node _T_2247 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2393:61] - node _T_2248 = or(_T_2246, _T_2247) @[dec_tlu_ctl.scala 2393:39] - node _T_2249 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2393:86] - node mhpmc5_wr_en1 = and(_T_2248, _T_2249) @[dec_tlu_ctl.scala 2393:66] + reg _T_2244 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_2244 <= mhpmc4h_ns @[lib.scala 358:16] + mhpmc4h <= _T_2244 @[dec_tlu_ctl.scala 2386:10] + node _T_2245 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2392:65] + node _T_2246 = eq(_T_2245, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2392:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2246) @[dec_tlu_ctl.scala 2392:43] + node _T_2247 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2393:23] + node _T_2248 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2393:61] + node _T_2249 = or(_T_2247, _T_2248) @[dec_tlu_ctl.scala 2393:39] + node _T_2250 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2393:86] + node mhpmc5_wr_en1 = and(_T_2249, _T_2250) @[dec_tlu_ctl.scala 2393:66] node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2394:36] - node _T_2250 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2396:28] - node _T_2251 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2396:41] - node _T_2252 = cat(_T_2250, _T_2251) @[Cat.scala 29:58] - node _T_2253 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2254 = add(_T_2252, _T_2253) @[dec_tlu_ctl.scala 2396:49] - node _T_2255 = tail(_T_2254, 1) @[dec_tlu_ctl.scala 2396:49] - mhpmc5_incr <= _T_2255 @[dec_tlu_ctl.scala 2396:14] - node _T_2256 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2397:36] - node _T_2257 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2397:76] - node mhpmc5_ns = mux(_T_2256, io.dec_csr_wrdata_r, _T_2257) @[dec_tlu_ctl.scala 2397:21] - node _T_2258 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2399:43] + node _T_2251 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2396:28] + node _T_2252 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2396:41] + node _T_2253 = cat(_T_2251, _T_2252) @[Cat.scala 29:58] + node _T_2254 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2255 = add(_T_2253, _T_2254) @[dec_tlu_ctl.scala 2396:49] + node _T_2256 = tail(_T_2255, 1) @[dec_tlu_ctl.scala 2396:49] + mhpmc5_incr <= _T_2256 @[dec_tlu_ctl.scala 2396:14] + node _T_2257 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2397:36] + node _T_2258 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2397:76] + node mhpmc5_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[dec_tlu_ctl.scala 2397:21] + node _T_2259 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2399:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 352:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset rvclkhdr_30.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_30.io.en <= _T_2258 @[lib.scala 355:17] + rvclkhdr_30.io.en <= _T_2259 @[lib.scala 355:17] rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_2259 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_2259 <= mhpmc5_ns @[lib.scala 358:16] - mhpmc5 <= _T_2259 @[dec_tlu_ctl.scala 2399:9] - node _T_2260 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2401:66] - node _T_2261 = eq(_T_2260, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2401:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2261) @[dec_tlu_ctl.scala 2401:44] + reg _T_2260 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_2260 <= mhpmc5_ns @[lib.scala 358:16] + mhpmc5 <= _T_2260 @[dec_tlu_ctl.scala 2399:9] + node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2401:66] + node _T_2262 = eq(_T_2261, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2401:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[dec_tlu_ctl.scala 2401:44] node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2402:38] - node _T_2262 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2403:38] - node _T_2263 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2403:78] - node mhpmc5h_ns = mux(_T_2262, io.dec_csr_wrdata_r, _T_2263) @[dec_tlu_ctl.scala 2403:22] - node _T_2264 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2405:46] + node _T_2263 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2403:38] + node _T_2264 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2403:78] + node mhpmc5h_ns = mux(_T_2263, io.dec_csr_wrdata_r, _T_2264) @[dec_tlu_ctl.scala 2403:22] + node _T_2265 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2405:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 352:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset rvclkhdr_31.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_31.io.en <= _T_2264 @[lib.scala 355:17] + rvclkhdr_31.io.en <= _T_2265 @[lib.scala 355:17] rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_2265 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_2265 <= mhpmc5h_ns @[lib.scala 358:16] - mhpmc5h <= _T_2265 @[dec_tlu_ctl.scala 2405:10] - node _T_2266 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2410:65] - node _T_2267 = eq(_T_2266, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2410:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2267) @[dec_tlu_ctl.scala 2410:43] - node _T_2268 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2411:23] - node _T_2269 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2411:61] - node _T_2270 = or(_T_2268, _T_2269) @[dec_tlu_ctl.scala 2411:39] - node _T_2271 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2411:86] - node mhpmc6_wr_en1 = and(_T_2270, _T_2271) @[dec_tlu_ctl.scala 2411:66] + reg _T_2266 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_2266 <= mhpmc5h_ns @[lib.scala 358:16] + mhpmc5h <= _T_2266 @[dec_tlu_ctl.scala 2405:10] + node _T_2267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2410:65] + node _T_2268 = eq(_T_2267, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2410:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2268) @[dec_tlu_ctl.scala 2410:43] + node _T_2269 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2411:23] + node _T_2270 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2411:61] + node _T_2271 = or(_T_2269, _T_2270) @[dec_tlu_ctl.scala 2411:39] + node _T_2272 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2411:86] + node mhpmc6_wr_en1 = and(_T_2271, _T_2272) @[dec_tlu_ctl.scala 2411:66] node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2412:36] - node _T_2272 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2414:28] - node _T_2273 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2414:41] - node _T_2274 = cat(_T_2272, _T_2273) @[Cat.scala 29:58] - node _T_2275 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2276 = add(_T_2274, _T_2275) @[dec_tlu_ctl.scala 2414:49] - node _T_2277 = tail(_T_2276, 1) @[dec_tlu_ctl.scala 2414:49] - mhpmc6_incr <= _T_2277 @[dec_tlu_ctl.scala 2414:14] - node _T_2278 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2415:36] - node _T_2279 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2415:76] - node mhpmc6_ns = mux(_T_2278, io.dec_csr_wrdata_r, _T_2279) @[dec_tlu_ctl.scala 2415:21] - node _T_2280 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2417:43] + node _T_2273 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2414:28] + node _T_2274 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2414:41] + node _T_2275 = cat(_T_2273, _T_2274) @[Cat.scala 29:58] + node _T_2276 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2277 = add(_T_2275, _T_2276) @[dec_tlu_ctl.scala 2414:49] + node _T_2278 = tail(_T_2277, 1) @[dec_tlu_ctl.scala 2414:49] + mhpmc6_incr <= _T_2278 @[dec_tlu_ctl.scala 2414:14] + node _T_2279 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2415:36] + node _T_2280 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2415:76] + node mhpmc6_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[dec_tlu_ctl.scala 2415:21] + node _T_2281 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2417:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 352:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset rvclkhdr_32.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_32.io.en <= _T_2280 @[lib.scala 355:17] + rvclkhdr_32.io.en <= _T_2281 @[lib.scala 355:17] rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_2281 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_2281 <= mhpmc6_ns @[lib.scala 358:16] - mhpmc6 <= _T_2281 @[dec_tlu_ctl.scala 2417:9] - node _T_2282 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2419:66] - node _T_2283 = eq(_T_2282, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2419:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2283) @[dec_tlu_ctl.scala 2419:44] + reg _T_2282 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_2282 <= mhpmc6_ns @[lib.scala 358:16] + mhpmc6 <= _T_2282 @[dec_tlu_ctl.scala 2417:9] + node _T_2283 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2419:66] + node _T_2284 = eq(_T_2283, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2419:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2284) @[dec_tlu_ctl.scala 2419:44] node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2420:38] - node _T_2284 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2421:38] - node _T_2285 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2421:78] - node mhpmc6h_ns = mux(_T_2284, io.dec_csr_wrdata_r, _T_2285) @[dec_tlu_ctl.scala 2421:22] - node _T_2286 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2423:46] + node _T_2285 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2421:38] + node _T_2286 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2421:78] + node mhpmc6h_ns = mux(_T_2285, io.dec_csr_wrdata_r, _T_2286) @[dec_tlu_ctl.scala 2421:22] + node _T_2287 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2423:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 352:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset rvclkhdr_33.io.clk <= clock @[lib.scala 354:18] - rvclkhdr_33.io.en <= _T_2286 @[lib.scala 355:17] + rvclkhdr_33.io.en <= _T_2287 @[lib.scala 355:17] rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 356:24] - reg _T_2287 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] - _T_2287 <= mhpmc6h_ns @[lib.scala 358:16] - mhpmc6h <= _T_2287 @[dec_tlu_ctl.scala 2423:10] - node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:50] - node _T_2289 = gt(_T_2288, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2430:56] - node _T_2290 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2430:93] - node _T_2291 = orr(_T_2290) @[dec_tlu_ctl.scala 2430:102] - node _T_2292 = or(_T_2289, _T_2291) @[dec_tlu_ctl.scala 2430:71] - node _T_2293 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:141] - node event_saturate_r = mux(_T_2292, UInt<10>("h0204"), _T_2293) @[dec_tlu_ctl.scala 2430:28] - node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2432:63] - node _T_2295 = eq(_T_2294, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2432:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2432:41] - node _T_2296 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2434:80] - reg _T_2297 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2296 : @[Reg.scala 28:19] - _T_2297 <= event_saturate_r @[Reg.scala 28:23] + reg _T_2288 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] + _T_2288 <= mhpmc6h_ns @[lib.scala 358:16] + mhpmc6h <= _T_2288 @[dec_tlu_ctl.scala 2423:10] + node _T_2289 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:50] + node _T_2290 = gt(_T_2289, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2430:56] + node _T_2291 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2430:93] + node _T_2292 = orr(_T_2291) @[dec_tlu_ctl.scala 2430:102] + node _T_2293 = or(_T_2290, _T_2292) @[dec_tlu_ctl.scala 2430:71] + node _T_2294 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:141] + node event_saturate_r = mux(_T_2293, UInt<10>("h0204"), _T_2294) @[dec_tlu_ctl.scala 2430:28] + node _T_2295 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2432:63] + node _T_2296 = eq(_T_2295, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2432:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2296) @[dec_tlu_ctl.scala 2432:41] + node _T_2297 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2434:80] + reg _T_2298 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2297 : @[Reg.scala 28:19] + _T_2298 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2297 @[dec_tlu_ctl.scala 2434:9] - node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2439:63] - node _T_2299 = eq(_T_2298, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2439:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2439:41] - node _T_2300 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2440:80] - reg _T_2301 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2300 : @[Reg.scala 28:19] - _T_2301 <= event_saturate_r @[Reg.scala 28:23] + mhpme3 <= _T_2298 @[dec_tlu_ctl.scala 2434:9] + node _T_2299 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2439:63] + node _T_2300 = eq(_T_2299, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2439:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2300) @[dec_tlu_ctl.scala 2439:41] + node _T_2301 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2440:80] + reg _T_2302 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2301 : @[Reg.scala 28:19] + _T_2302 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2301 @[dec_tlu_ctl.scala 2440:9] - node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2446:63] - node _T_2303 = eq(_T_2302, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2446:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2446:41] - node _T_2304 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2447:80] - reg _T_2305 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2304 : @[Reg.scala 28:19] - _T_2305 <= event_saturate_r @[Reg.scala 28:23] + mhpme4 <= _T_2302 @[dec_tlu_ctl.scala 2440:9] + node _T_2303 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2446:63] + node _T_2304 = eq(_T_2303, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2446:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2304) @[dec_tlu_ctl.scala 2446:41] + node _T_2305 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2447:80] + reg _T_2306 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2305 : @[Reg.scala 28:19] + _T_2306 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2305 @[dec_tlu_ctl.scala 2447:9] - node _T_2306 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2453:63] - node _T_2307 = eq(_T_2306, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2453:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2307) @[dec_tlu_ctl.scala 2453:41] - node _T_2308 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2454:80] - reg _T_2309 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2308 : @[Reg.scala 28:19] - _T_2309 <= event_saturate_r @[Reg.scala 28:23] + mhpme5 <= _T_2306 @[dec_tlu_ctl.scala 2447:9] + node _T_2307 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2453:63] + node _T_2308 = eq(_T_2307, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2453:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2308) @[dec_tlu_ctl.scala 2453:41] + node _T_2309 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2454:80] + reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2309 : @[Reg.scala 28:19] + _T_2310 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2309 @[dec_tlu_ctl.scala 2454:9] - node _T_2310 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2470:70] - node _T_2311 = eq(_T_2310, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2470:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2311) @[dec_tlu_ctl.scala 2470:48] - node _T_2312 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2472:54] + mhpme6 <= _T_2310 @[dec_tlu_ctl.scala 2454:9] + node _T_2311 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2470:70] + node _T_2312 = eq(_T_2311, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2470:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2312) @[dec_tlu_ctl.scala 2470:48] + node _T_2313 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2472:54] wire temp_ncount0 : UInt<1> - temp_ncount0 <= _T_2312 - node _T_2313 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2473:54] + temp_ncount0 <= _T_2313 + node _T_2314 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2473:54] wire temp_ncount1 : UInt<1> - temp_ncount1 <= _T_2313 - node _T_2314 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2474:55] + temp_ncount1 <= _T_2314 + node _T_2315 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2474:55] wire temp_ncount6_2 : UInt<5> - temp_ncount6_2 <= _T_2314 - node _T_2315 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2475:74] - node _T_2316 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:103] - reg _T_2317 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2316 : @[Reg.scala 28:19] - _T_2317 <= _T_2315 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2315 + node _T_2316 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2475:74] + node _T_2317 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:103] + reg _T_2318 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2317 : @[Reg.scala 28:19] + _T_2318 <= _T_2316 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2317 @[dec_tlu_ctl.scala 2475:17] - node _T_2318 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2477:72] - node _T_2319 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2477:99] - reg _T_2320 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2319 : @[Reg.scala 28:19] - _T_2320 <= _T_2318 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2318 @[dec_tlu_ctl.scala 2475:17] + node _T_2319 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2477:72] + node _T_2320 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2477:99] + reg _T_2321 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2320 : @[Reg.scala 28:19] + _T_2321 <= _T_2319 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2320 @[dec_tlu_ctl.scala 2477:15] - node _T_2321 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2322 = cat(_T_2321, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2322 @[dec_tlu_ctl.scala 2478:16] - node _T_2323 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2485:51] - node _T_2324 = or(_T_2323, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2485:78] - node _T_2325 = or(_T_2324, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2485:104] - node _T_2326 = or(_T_2325, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2485:130] - node _T_2327 = or(_T_2326, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2486:32] - node _T_2328 = or(_T_2327, io.clk_override) @[dec_tlu_ctl.scala 2486:59] - node _T_2329 = bits(_T_2328, 0, 0) @[dec_tlu_ctl.scala 2486:78] + temp_ncount0 <= _T_2321 @[dec_tlu_ctl.scala 2477:15] + node _T_2322 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2323 = cat(_T_2322, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2323 @[dec_tlu_ctl.scala 2478:16] + node _T_2324 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2485:51] + node _T_2325 = or(_T_2324, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2485:78] + node _T_2326 = or(_T_2325, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2485:104] + node _T_2327 = or(_T_2326, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2485:130] + node _T_2328 = or(_T_2327, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2486:32] + node _T_2329 = or(_T_2328, io.clk_override) @[dec_tlu_ctl.scala 2486:59] + node _T_2330 = bits(_T_2329, 0, 0) @[dec_tlu_ctl.scala 2486:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 327:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 328:17] - rvclkhdr_34.io.en <= _T_2329 @[lib.scala 329:16] + rvclkhdr_34.io.en <= _T_2330 @[lib.scala 329:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] - _T_2330 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2488:62] - io.dec_tlu_i0_valid_wb1 <= _T_2330 @[dec_tlu_ctl.scala 2488:30] - node _T_2331 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2489:91] - node _T_2332 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2489:137] - node _T_2333 = and(io.trigger_hit_r_d1, _T_2332) @[dec_tlu_ctl.scala 2489:135] - node _T_2334 = or(_T_2331, _T_2333) @[dec_tlu_ctl.scala 2489:112] - reg _T_2335 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] - _T_2335 <= _T_2334 @[dec_tlu_ctl.scala 2489:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2335 @[dec_tlu_ctl.scala 2489:30] - reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] - _T_2336 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2490:62] - io.dec_tlu_exc_cause_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2490:30] - reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2491:62] - _T_2337 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2491:62] - io.dec_tlu_int_valid_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2491:30] + reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] + _T_2331 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2488:62] + io.dec_tlu_i0_valid_wb1 <= _T_2331 @[dec_tlu_ctl.scala 2488:30] + node _T_2332 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2489:91] + node _T_2333 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2489:137] + node _T_2334 = and(io.trigger_hit_r_d1, _T_2333) @[dec_tlu_ctl.scala 2489:135] + node _T_2335 = or(_T_2332, _T_2334) @[dec_tlu_ctl.scala 2489:112] + reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] + _T_2336 <= _T_2335 @[dec_tlu_ctl.scala 2489:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2489:30] + reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] + _T_2337 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2490:62] + io.dec_tlu_exc_cause_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2490:30] + reg _T_2338 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2491:62] + _T_2338 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2491:62] + io.dec_tlu_int_valid_wb1 <= _T_2338 @[dec_tlu_ctl.scala 2491:30] io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2493:24] - node _T_2338 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2499:61] - node _T_2339 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2500:42] - node _T_2340 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2501:40] - node _T_2341 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2502:39] - node _T_2342 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2503:40] - node _T_2343 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2344 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:40] - node _T_2345 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2504:103] - node _T_2346 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:128] - node _T_2347 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] - node _T_2348 = cat(_T_2347, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2349 = cat(UInt<3>("h00"), _T_2345) @[Cat.scala 29:58] - node _T_2350 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2351 = cat(_T_2350, _T_2349) @[Cat.scala 29:58] - node _T_2352 = cat(_T_2351, _T_2348) @[Cat.scala 29:58] - node _T_2353 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:38] - node _T_2354 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2505:70] - node _T_2355 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:96] - node _T_2356 = cat(_T_2354, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2357 = cat(_T_2356, _T_2355) @[Cat.scala 29:58] - node _T_2358 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2506:36] - node _T_2359 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2506:78] - node _T_2360 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2506:102] - node _T_2361 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2506:123] - node _T_2362 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2506:144] - node _T_2363 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2364 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2365 = cat(_T_2364, _T_2363) @[Cat.scala 29:58] - node _T_2366 = cat(_T_2360, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2367 = cat(UInt<1>("h00"), _T_2359) @[Cat.scala 29:58] - node _T_2368 = cat(_T_2367, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2369 = cat(_T_2368, _T_2366) @[Cat.scala 29:58] - node _T_2370 = cat(_T_2369, _T_2365) @[Cat.scala 29:58] - node _T_2371 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2507:36] - node _T_2372 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2507:75] - node _T_2373 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2507:96] - node _T_2374 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2507:114] - node _T_2375 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2507:132] - node _T_2376 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2377 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2378 = cat(_T_2377, _T_2376) @[Cat.scala 29:58] - node _T_2379 = cat(_T_2373, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2380 = cat(UInt<1>("h00"), _T_2372) @[Cat.scala 29:58] - node _T_2381 = cat(_T_2380, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2382 = cat(_T_2381, _T_2379) @[Cat.scala 29:58] - node _T_2383 = cat(_T_2382, _T_2378) @[Cat.scala 29:58] - node _T_2384 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2508:40] - node _T_2385 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2508:65] - node _T_2386 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2509:40] - node _T_2387 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2509:69] - node _T_2388 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2510:42] - node _T_2389 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2510:72] - node _T_2390 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2511:42] - node _T_2391 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2511:72] - node _T_2392 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2512:41] - node _T_2393 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2512:66] - node _T_2394 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2513:37] - node _T_2395 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2396 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2514:39] - node _T_2397 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2514:64] - node _T_2398 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2515:40] - node _T_2399 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2515:80] - node _T_2400 = cat(UInt<28>("h00"), _T_2399) @[Cat.scala 29:58] - node _T_2401 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2516:38] - node _T_2402 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2516:63] - node _T_2403 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2517:37] - node _T_2404 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2517:62] - node _T_2405 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2518:39] - node _T_2406 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2518:64] - node _T_2407 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2519:38] - node _T_2408 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2409 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2520:39] - node _T_2410 = cat(meivt, meihap) @[Cat.scala 29:58] - node _T_2411 = cat(_T_2410, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2412 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] - node _T_2413 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] - node _T_2414 = cat(UInt<28>("h00"), _T_2413) @[Cat.scala 29:58] - node _T_2415 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2522:41] - node _T_2416 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2522:81] - node _T_2417 = cat(UInt<28>("h00"), _T_2416) @[Cat.scala 29:58] - node _T_2418 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2523:38] - node _T_2419 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2523:78] - node _T_2420 = cat(UInt<28>("h00"), _T_2419) @[Cat.scala 29:58] - node _T_2421 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2524:37] - node _T_2422 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2524:77] - node _T_2423 = cat(UInt<23>("h00"), _T_2422) @[Cat.scala 29:58] - node _T_2424 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2525:37] - node _T_2425 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2525:77] - node _T_2426 = cat(UInt<13>("h00"), _T_2425) @[Cat.scala 29:58] - node _T_2427 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2526:37] - node _T_2428 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2526:85] - node _T_2429 = cat(UInt<16>("h04000"), _T_2428) @[Cat.scala 29:58] - node _T_2430 = cat(_T_2429, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2431 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2527:36] - node _T_2432 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2433 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2528:39] - node _T_2434 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2528:64] - node _T_2435 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2529:40] - node _T_2436 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2529:65] - node _T_2437 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2530:39] - node _T_2438 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2530:64] - node _T_2439 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2531:41] - node _T_2440 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2531:80] - node _T_2441 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2531:104] - node _T_2442 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2531:131] - node _T_2443 = cat(UInt<3>("h00"), _T_2442) @[Cat.scala 29:58] - node _T_2444 = cat(_T_2443, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2445 = cat(UInt<2>("h00"), _T_2441) @[Cat.scala 29:58] - node _T_2446 = cat(UInt<7>("h00"), _T_2440) @[Cat.scala 29:58] - node _T_2447 = cat(_T_2446, _T_2445) @[Cat.scala 29:58] - node _T_2448 = cat(_T_2447, _T_2444) @[Cat.scala 29:58] - node _T_2449 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2532:38] - node _T_2450 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2532:78] - node _T_2451 = cat(UInt<30>("h00"), _T_2450) @[Cat.scala 29:58] - node _T_2452 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2533:40] - node _T_2453 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] - node _T_2454 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2534:40] - node _T_2455 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2534:74] - node _T_2456 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2535:39] - node _T_2457 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2535:64] - node _T_2458 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] - node _T_2459 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] - node _T_2460 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2537:41] - node _T_2461 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2537:66] - node _T_2462 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2538:39] - node _T_2463 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2538:64] - node _T_2464 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2539:39] - node _T_2465 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2539:64] - node _T_2466 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2540:39] - node _T_2467 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2540:64] - node _T_2468 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2541:39] - node _T_2469 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2541:64] - node _T_2470 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2542:40] - node _T_2471 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2542:65] - node _T_2472 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2543:40] - node _T_2473 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2543:65] - node _T_2474 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2544:40] - node _T_2475 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2544:65] - node _T_2476 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2545:40] - node _T_2477 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2545:65] - node _T_2478 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2546:38] - node _T_2479 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2546:78] - node _T_2480 = cat(UInt<26>("h00"), _T_2479) @[Cat.scala 29:58] - node _T_2481 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2547:38] - node _T_2482 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2547:78] - node _T_2483 = cat(UInt<30>("h00"), _T_2482) @[Cat.scala 29:58] - node _T_2484 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2548:39] - node _T_2485 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2548:79] - node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58] - node _T_2487 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2549:39] - node _T_2488 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2549:79] - node _T_2489 = cat(UInt<22>("h00"), _T_2488) @[Cat.scala 29:58] - node _T_2490 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2550:39] - node _T_2491 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2550:78] - node _T_2492 = cat(UInt<22>("h00"), _T_2491) @[Cat.scala 29:58] - node _T_2493 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2551:39] - node _T_2494 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2551:78] - node _T_2495 = cat(UInt<22>("h00"), _T_2494) @[Cat.scala 29:58] - node _T_2496 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2552:46] - node _T_2497 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2552:86] - node _T_2498 = cat(UInt<25>("h00"), _T_2497) @[Cat.scala 29:58] - node _T_2499 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2553:37] - node _T_2500 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] - node _T_2501 = cat(_T_2500, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2502 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2554:37] - node _T_2503 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2554:76] - node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2507 = mux(_T_2341, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2511 = mux(_T_2358, _T_2370, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2512 = mux(_T_2371, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2513 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2514 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2515 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2516 = mux(_T_2390, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2517 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2518 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2519 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2520 = mux(_T_2398, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2521 = mux(_T_2401, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2522 = mux(_T_2403, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2523 = mux(_T_2405, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2524 = mux(_T_2407, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2525 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2526 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2527 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2528 = mux(_T_2418, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2529 = mux(_T_2421, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2530 = mux(_T_2424, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2531 = mux(_T_2427, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2532 = mux(_T_2431, _T_2432, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2533 = mux(_T_2433, _T_2434, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2534 = mux(_T_2435, _T_2436, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2535 = mux(_T_2437, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2536 = mux(_T_2439, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2537 = mux(_T_2449, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2538 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2539 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2540 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2541 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2542 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2543 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2544 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2545 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2546 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2547 = mux(_T_2470, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2548 = mux(_T_2472, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2549 = mux(_T_2474, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2550 = mux(_T_2476, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2551 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2552 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2553 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2554 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2555 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2556 = mux(_T_2493, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2557 = mux(_T_2496, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2558 = mux(_T_2499, _T_2501, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2559 = mux(_T_2502, _T_2503, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2560 = or(_T_2504, _T_2505) @[Mux.scala 27:72] - node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] + node _T_2339 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2499:61] + node _T_2340 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2500:42] + node _T_2341 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2501:40] + node _T_2342 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2502:39] + node _T_2343 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2503:40] + node _T_2344 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2345 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:40] + node _T_2346 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2504:103] + node _T_2347 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:128] + node _T_2348 = cat(UInt<3>("h00"), _T_2347) @[Cat.scala 29:58] + node _T_2349 = cat(_T_2348, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2350 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] + node _T_2351 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58] + node _T_2353 = cat(_T_2352, _T_2349) @[Cat.scala 29:58] + node _T_2354 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:38] + node _T_2355 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2505:70] + node _T_2356 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:96] + node _T_2357 = cat(_T_2355, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2358 = cat(_T_2357, _T_2356) @[Cat.scala 29:58] + node _T_2359 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2506:36] + node _T_2360 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2506:78] + node _T_2361 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2506:102] + node _T_2362 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2506:123] + node _T_2363 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2506:144] + node _T_2364 = cat(_T_2363, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2365 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2366 = cat(_T_2365, _T_2364) @[Cat.scala 29:58] + node _T_2367 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2368 = cat(UInt<1>("h00"), _T_2360) @[Cat.scala 29:58] + node _T_2369 = cat(_T_2368, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2370 = cat(_T_2369, _T_2367) @[Cat.scala 29:58] + node _T_2371 = cat(_T_2370, _T_2366) @[Cat.scala 29:58] + node _T_2372 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2507:36] + node _T_2373 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2507:75] + node _T_2374 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2507:96] + node _T_2375 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2507:114] + node _T_2376 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2507:132] + node _T_2377 = cat(_T_2376, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2378 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2379 = cat(_T_2378, _T_2377) @[Cat.scala 29:58] + node _T_2380 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2381 = cat(UInt<1>("h00"), _T_2373) @[Cat.scala 29:58] + node _T_2382 = cat(_T_2381, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2383 = cat(_T_2382, _T_2380) @[Cat.scala 29:58] + node _T_2384 = cat(_T_2383, _T_2379) @[Cat.scala 29:58] + node _T_2385 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2508:40] + node _T_2386 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2508:65] + node _T_2387 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2509:40] + node _T_2388 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2509:69] + node _T_2389 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2510:42] + node _T_2390 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2510:72] + node _T_2391 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2511:42] + node _T_2392 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2511:72] + node _T_2393 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2512:41] + node _T_2394 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2512:66] + node _T_2395 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2513:37] + node _T_2396 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2397 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2514:39] + node _T_2398 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2514:64] + node _T_2399 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2515:40] + node _T_2400 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2515:80] + node _T_2401 = cat(UInt<28>("h00"), _T_2400) @[Cat.scala 29:58] + node _T_2402 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2516:38] + node _T_2403 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2516:63] + node _T_2404 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2517:37] + node _T_2405 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2517:62] + node _T_2406 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2518:39] + node _T_2407 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2518:64] + node _T_2408 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2519:38] + node _T_2409 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2410 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2520:39] + node _T_2411 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2412 = cat(_T_2411, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2413 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] + node _T_2414 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] + node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58] + node _T_2416 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2522:41] + node _T_2417 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2522:81] + node _T_2418 = cat(UInt<28>("h00"), _T_2417) @[Cat.scala 29:58] + node _T_2419 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2523:38] + node _T_2420 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2523:78] + node _T_2421 = cat(UInt<28>("h00"), _T_2420) @[Cat.scala 29:58] + node _T_2422 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2524:37] + node _T_2423 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2524:77] + node _T_2424 = cat(UInt<23>("h00"), _T_2423) @[Cat.scala 29:58] + node _T_2425 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2525:37] + node _T_2426 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2525:77] + node _T_2427 = cat(UInt<13>("h00"), _T_2426) @[Cat.scala 29:58] + node _T_2428 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2526:37] + node _T_2429 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2526:85] + node _T_2430 = cat(UInt<16>("h04000"), _T_2429) @[Cat.scala 29:58] + node _T_2431 = cat(_T_2430, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2432 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2527:36] + node _T_2433 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2434 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2528:39] + node _T_2435 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2528:64] + node _T_2436 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2529:40] + node _T_2437 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2529:65] + node _T_2438 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2530:39] + node _T_2439 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2530:64] + node _T_2440 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2531:41] + node _T_2441 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2531:80] + node _T_2442 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2531:104] + node _T_2443 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2531:131] + node _T_2444 = cat(UInt<3>("h00"), _T_2443) @[Cat.scala 29:58] + node _T_2445 = cat(_T_2444, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2446 = cat(UInt<2>("h00"), _T_2442) @[Cat.scala 29:58] + node _T_2447 = cat(UInt<7>("h00"), _T_2441) @[Cat.scala 29:58] + node _T_2448 = cat(_T_2447, _T_2446) @[Cat.scala 29:58] + node _T_2449 = cat(_T_2448, _T_2445) @[Cat.scala 29:58] + node _T_2450 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2532:38] + node _T_2451 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2532:78] + node _T_2452 = cat(UInt<30>("h00"), _T_2451) @[Cat.scala 29:58] + node _T_2453 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2533:40] + node _T_2454 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] + node _T_2455 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2534:40] + node _T_2456 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2534:74] + node _T_2457 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2535:39] + node _T_2458 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2535:64] + node _T_2459 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] + node _T_2460 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] + node _T_2461 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2537:41] + node _T_2462 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2537:66] + node _T_2463 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2538:39] + node _T_2464 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2538:64] + node _T_2465 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2539:39] + node _T_2466 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2539:64] + node _T_2467 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2540:39] + node _T_2468 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2540:64] + node _T_2469 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2541:39] + node _T_2470 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2541:64] + node _T_2471 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2542:40] + node _T_2472 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2542:65] + node _T_2473 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2543:40] + node _T_2474 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2543:65] + node _T_2475 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2544:40] + node _T_2476 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2544:65] + node _T_2477 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2545:40] + node _T_2478 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2545:65] + node _T_2479 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2546:38] + node _T_2480 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2546:78] + node _T_2481 = cat(UInt<26>("h00"), _T_2480) @[Cat.scala 29:58] + node _T_2482 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2547:38] + node _T_2483 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2547:78] + node _T_2484 = cat(UInt<30>("h00"), _T_2483) @[Cat.scala 29:58] + node _T_2485 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2548:39] + node _T_2486 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2548:79] + node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] + node _T_2488 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2549:39] + node _T_2489 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2549:79] + node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58] + node _T_2491 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2550:39] + node _T_2492 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2550:78] + node _T_2493 = cat(UInt<22>("h00"), _T_2492) @[Cat.scala 29:58] + node _T_2494 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2551:39] + node _T_2495 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2551:78] + node _T_2496 = cat(UInt<22>("h00"), _T_2495) @[Cat.scala 29:58] + node _T_2497 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2552:46] + node _T_2498 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2552:86] + node _T_2499 = cat(UInt<25>("h00"), _T_2498) @[Cat.scala 29:58] + node _T_2500 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2553:37] + node _T_2501 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2502 = cat(_T_2501, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2503 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2554:37] + node _T_2504 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2554:76] + node _T_2505 = mux(_T_2339, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2340, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2341, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2342, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2343, _T_2344, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2345, _T_2353, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2354, _T_2358, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2359, _T_2371, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2372, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2399, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2404, _T_2405, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2406, _T_2407, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2408, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2422, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2425, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2428, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2434, _T_2435, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2436, _T_2437, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2438, _T_2439, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2440, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2450, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2473, _T_2474, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2475, _T_2476, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2477, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2553 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2554 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2555 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2556 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2557 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2558 = mux(_T_2497, _T_2499, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2559 = mux(_T_2500, _T_2502, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2560 = mux(_T_2503, _T_2504, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2561 = or(_T_2505, _T_2506) @[Mux.scala 27:72] node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72] @@ -76176,9 +76176,10 @@ circuit quasar_wrapper : node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72] node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72] node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72] - wire _T_2615 : UInt @[Mux.scala 27:72] - _T_2615 <= _T_2614 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2615 @[dec_tlu_ctl.scala 2498:21] + node _T_2615 = or(_T_2614, _T_2560) @[Mux.scala 27:72] + wire _T_2616 : UInt @[Mux.scala 27:72] + _T_2616 <= _T_2615 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2616 @[dec_tlu_ctl.scala 2498:21] module dec_decode_csr_read : input clock : Clock diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 51e88d96..84067792 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -970,36 +970,36 @@ module ifu_mem_ctl( wire rvclkhdr_93_io_clk; // @[lib.scala 327:22] wire rvclkhdr_93_io_en; // @[lib.scala 327:22] wire rvclkhdr_93_io_scan_mode; // @[lib.scala 327:22] - reg flush_final_f; // @[ifu_mem_ctl.scala 108:53] - reg ifc_fetch_req_f_raw; // @[ifu_mem_ctl.scala 244:61] - wire _T_319 = ~io_exu_flush_final; // @[ifu_mem_ctl.scala 245:44] - wire ifc_fetch_req_f = ifc_fetch_req_f_raw & _T_319; // @[ifu_mem_ctl.scala 245:42] - wire _T = io_ifc_fetch_req_bf_raw | ifc_fetch_req_f; // @[ifu_mem_ctl.scala 109:53] + reg flush_final_f; // @[ifu_mem_ctl.scala 90:53] + reg ifc_fetch_req_f_raw; // @[ifu_mem_ctl.scala 227:61] + wire _T_319 = ~io_exu_flush_final; // @[ifu_mem_ctl.scala 228:44] + wire ifc_fetch_req_f = ifc_fetch_req_f_raw & _T_319; // @[ifu_mem_ctl.scala 228:42] + wire _T = io_ifc_fetch_req_bf_raw | ifc_fetch_req_f; // @[ifu_mem_ctl.scala 91:53] reg [2:0] miss_state; // @[Reg.scala 27:20] - wire miss_pending = miss_state != 3'h0; // @[ifu_mem_ctl.scala 176:30] - wire _T_1 = _T | miss_pending; // @[ifu_mem_ctl.scala 109:71] - wire _T_2 = _T_1 | io_exu_flush_final; // @[ifu_mem_ctl.scala 109:86] - reg scnd_miss_req_q; // @[ifu_mem_ctl.scala 477:52] - wire scnd_miss_req = scnd_miss_req_q & _T_319; // @[ifu_mem_ctl.scala 479:36] - wire debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[ifu_mem_ctl.scala 110:42] + wire miss_pending = miss_state != 3'h0; // @[ifu_mem_ctl.scala 159:30] + wire _T_1 = _T | miss_pending; // @[ifu_mem_ctl.scala 91:71] + wire _T_2 = _T_1 | io_exu_flush_final; // @[ifu_mem_ctl.scala 91:86] + reg scnd_miss_req_q; // @[ifu_mem_ctl.scala 464:52] + wire scnd_miss_req = scnd_miss_req_q & _T_319; // @[ifu_mem_ctl.scala 466:36] + wire debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[ifu_mem_ctl.scala 92:42] wire [3:0] ic_fetch_val_int_f = {2'h0,io_ic_fetch_val_f}; // @[Cat.scala 29:58] - reg [30:0] ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 231:63] - wire [4:0] _GEN_435 = {{1'd0}, ic_fetch_val_int_f}; // @[ifu_mem_ctl.scala 595:53] - wire [4:0] ic_fetch_val_shift_right = _GEN_435 << ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 595:53] - wire _T_3129 = |ic_fetch_val_shift_right[3:2]; // @[ifu_mem_ctl.scala 598:91] - wire _T_3131 = _T_3129 & _T_319; // @[ifu_mem_ctl.scala 598:95] - reg ifc_iccm_access_f; // @[ifu_mem_ctl.scala 246:60] - wire fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 198:46] - wire _T_3132 = _T_3131 & fetch_req_iccm_f; // @[ifu_mem_ctl.scala 598:117] - reg iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 584:59] - wire _T_3133 = _T_3132 | iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 598:134] - wire _T_3134 = ~io_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu_mem_ctl.scala 598:158] - wire _T_3135 = _T_3133 & _T_3134; // @[ifu_mem_ctl.scala 598:156] - wire _T_3121 = |ic_fetch_val_shift_right[1:0]; // @[ifu_mem_ctl.scala 598:91] - wire _T_3123 = _T_3121 & _T_319; // @[ifu_mem_ctl.scala 598:95] - wire _T_3124 = _T_3123 & fetch_req_iccm_f; // @[ifu_mem_ctl.scala 598:117] - wire _T_3125 = _T_3124 | iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 598:134] - wire _T_3127 = _T_3125 & _T_3134; // @[ifu_mem_ctl.scala 598:156] + reg [30:0] ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 214:63] + wire [4:0] _GEN_435 = {{1'd0}, ic_fetch_val_int_f}; // @[ifu_mem_ctl.scala 603:53] + wire [4:0] ic_fetch_val_shift_right = _GEN_435 << ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 603:53] + wire _T_3129 = |ic_fetch_val_shift_right[3:2]; // @[ifu_mem_ctl.scala 606:91] + wire _T_3131 = _T_3129 & _T_319; // @[ifu_mem_ctl.scala 606:95] + reg ifc_iccm_access_f; // @[ifu_mem_ctl.scala 229:60] + wire fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 181:46] + wire _T_3132 = _T_3131 & fetch_req_iccm_f; // @[ifu_mem_ctl.scala 606:117] + reg iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 592:59] + wire _T_3133 = _T_3132 | iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 606:134] + wire _T_3134 = ~io_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu_mem_ctl.scala 606:158] + wire _T_3135 = _T_3133 & _T_3134; // @[ifu_mem_ctl.scala 606:156] + wire _T_3121 = |ic_fetch_val_shift_right[1:0]; // @[ifu_mem_ctl.scala 606:91] + wire _T_3123 = _T_3121 & _T_319; // @[ifu_mem_ctl.scala 606:95] + wire _T_3124 = _T_3123 & fetch_req_iccm_f; // @[ifu_mem_ctl.scala 606:117] + wire _T_3125 = _T_3124 | iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 606:134] + wire _T_3127 = _T_3125 & _T_3134; // @[ifu_mem_ctl.scala 606:156] wire [1:0] iccm_ecc_word_enable = {_T_3135,_T_3127}; // @[Cat.scala 29:58] wire _T_3620 = ^io_iccm_rd_data_ecc[70:39]; // @[lib.scala 177:30] wire _T_3621 = ^io_iccm_rd_data_ecc[77:71]; // @[lib.scala 177:44] @@ -1062,238 +1062,238 @@ module ifu_mem_ctl( wire _T_3349 = iccm_ecc_word_enable[0] & _T_3348; // @[lib.scala 178:32] wire _T_3351 = _T_3349 & _T_3347[6]; // @[lib.scala 178:53] wire [1:0] iccm_single_ecc_error = {_T_3736,_T_3351}; // @[Cat.scala 29:58] - wire _T_3 = |iccm_single_ecc_error; // @[ifu_mem_ctl.scala 113:52] - reg dma_iccm_req_f; // @[ifu_mem_ctl.scala 561:51] - wire _T_6 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu_mem_ctl.scala 114:74] + wire _T_3 = |iccm_single_ecc_error; // @[ifu_mem_ctl.scala 95:52] + reg dma_iccm_req_f; // @[ifu_mem_ctl.scala 569:51] + wire _T_6 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu_mem_ctl.scala 96:74] reg [2:0] perr_state; // @[Reg.scala 27:20] - wire _T_7 = perr_state == 3'h4; // @[ifu_mem_ctl.scala 115:54] - wire iccm_correct_ecc = perr_state == 3'h3; // @[ifu_mem_ctl.scala 405:34] - wire _T_8 = iccm_correct_ecc | _T_7; // @[ifu_mem_ctl.scala 115:40] + wire _T_7 = perr_state == 3'h4; // @[ifu_mem_ctl.scala 97:54] + wire iccm_correct_ecc = perr_state == 3'h3; // @[ifu_mem_ctl.scala 392:34] + wire _T_8 = iccm_correct_ecc | _T_7; // @[ifu_mem_ctl.scala 97:40] reg [1:0] err_stop_state; // @[Reg.scala 27:20] - wire _T_9 = err_stop_state == 2'h3; // @[ifu_mem_ctl.scala 115:90] - wire _T_10 = _T_8 | _T_9; // @[ifu_mem_ctl.scala 115:72] + wire _T_9 = err_stop_state == 2'h3; // @[ifu_mem_ctl.scala 97:90] + wire _T_10 = _T_8 | _T_9; // @[ifu_mem_ctl.scala 97:72] wire _T_2526 = 2'h0 == err_stop_state; // @[Conditional.scala 37:30] wire _T_2531 = 2'h1 == err_stop_state; // @[Conditional.scala 37:30] - wire _T_2551 = io_ifu_fetch_val == 2'h3; // @[ifu_mem_ctl.scala 454:48] - wire two_byte_instr = io_ic_data_f[1:0] != 2'h3; // @[ifu_mem_ctl.scala 320:42] - wire _T_2553 = io_ifu_fetch_val[0] & two_byte_instr; // @[ifu_mem_ctl.scala 454:79] - wire _T_2554 = _T_2551 | _T_2553; // @[ifu_mem_ctl.scala 454:56] - wire _T_2555 = io_exu_flush_final | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 454:122] - wire _T_2556 = ~_T_2555; // @[ifu_mem_ctl.scala 454:101] - wire _T_2557 = _T_2554 & _T_2556; // @[ifu_mem_ctl.scala 454:99] + wire _T_2551 = io_ifu_fetch_val == 2'h3; // @[ifu_mem_ctl.scala 441:48] + wire two_byte_instr = io_ic_data_f[1:0] != 2'h3; // @[ifu_mem_ctl.scala 306:42] + wire _T_2553 = io_ifu_fetch_val[0] & two_byte_instr; // @[ifu_mem_ctl.scala 441:79] + wire _T_2554 = _T_2551 | _T_2553; // @[ifu_mem_ctl.scala 441:56] + wire _T_2555 = io_exu_flush_final | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 441:122] + wire _T_2556 = ~_T_2555; // @[ifu_mem_ctl.scala 441:101] + wire _T_2557 = _T_2554 & _T_2556; // @[ifu_mem_ctl.scala 441:99] wire _T_2558 = 2'h2 == err_stop_state; // @[Conditional.scala 37:30] - wire _T_2572 = io_ifu_fetch_val[0] & _T_319; // @[ifu_mem_ctl.scala 461:45] - wire _T_2573 = ~io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 461:69] - wire _T_2574 = _T_2572 & _T_2573; // @[ifu_mem_ctl.scala 461:67] + wire _T_2572 = io_ifu_fetch_val[0] & _T_319; // @[ifu_mem_ctl.scala 448:45] + wire _T_2573 = ~io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 448:69] + wire _T_2574 = _T_2572 & _T_2573; // @[ifu_mem_ctl.scala 448:67] wire _T_2575 = 2'h3 == err_stop_state; // @[Conditional.scala 37:30] wire _GEN_37 = _T_2558 ? _T_2574 : _T_2575; // @[Conditional.scala 39:67] wire _GEN_41 = _T_2531 ? _T_2557 : _GEN_37; // @[Conditional.scala 39:67] wire err_stop_fetch = _T_2526 ? 1'h0 : _GEN_41; // @[Conditional.scala 40:58] - wire _T_11 = _T_10 | err_stop_fetch; // @[ifu_mem_ctl.scala 115:112] - wire _T_13 = io_ifu_axi_r_valid & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 117:44] - wire _T_14 = _T_13 & io_ifu_axi_r_ready; // @[ifu_mem_ctl.scala 117:65] - wire _T_227 = |io_ic_rd_hit; // @[ifu_mem_ctl.scala 206:37] - wire _T_228 = ~_T_227; // @[ifu_mem_ctl.scala 206:23] - reg reset_all_tags; // @[ifu_mem_ctl.scala 630:53] - wire _T_229 = _T_228 | reset_all_tags; // @[ifu_mem_ctl.scala 206:41] - wire _T_207 = ~ifc_iccm_access_f; // @[ifu_mem_ctl.scala 197:48] - wire _T_208 = ifc_fetch_req_f & _T_207; // @[ifu_mem_ctl.scala 197:46] - reg ifc_region_acc_fault_final_f; // @[ifu_mem_ctl.scala 248:71] - wire _T_209 = ~ifc_region_acc_fault_final_f; // @[ifu_mem_ctl.scala 197:69] - wire fetch_req_icache_f = _T_208 & _T_209; // @[ifu_mem_ctl.scala 197:67] - wire _T_230 = _T_229 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 206:59] - wire _T_231 = ~miss_pending; // @[ifu_mem_ctl.scala 206:82] - wire _T_232 = _T_230 & _T_231; // @[ifu_mem_ctl.scala 206:80] - wire _T_233 = _T_232 | scnd_miss_req; // @[ifu_mem_ctl.scala 206:97] - wire ic_act_miss_f = _T_233 & _T_209; // @[ifu_mem_ctl.scala 206:114] - reg ifu_bus_rvalid_unq_ff; // @[ifu_mem_ctl.scala 504:56] - reg bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 476:61] - wire ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 518:49] - wire bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; // @[ifu_mem_ctl.scala 545:41] - reg uncacheable_miss_ff; // @[ifu_mem_ctl.scala 233:62] - reg [2:0] bus_data_beat_count; // @[ifu_mem_ctl.scala 526:56] - wire _T_2672 = bus_data_beat_count == 3'h1; // @[ifu_mem_ctl.scala 543:69] - wire _T_2673 = &bus_data_beat_count; // @[ifu_mem_ctl.scala 543:101] - wire bus_last_data_beat = uncacheable_miss_ff ? _T_2672 : _T_2673; // @[ifu_mem_ctl.scala 543:28] - wire _T_2624 = bus_ifu_wr_en_ff & bus_last_data_beat; // @[ifu_mem_ctl.scala 522:68] - wire _T_2625 = ic_act_miss_f | _T_2624; // @[ifu_mem_ctl.scala 522:48] - wire bus_reset_data_beat_cnt = _T_2625 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 522:91] - wire _T_2621 = ~bus_last_data_beat; // @[ifu_mem_ctl.scala 521:50] - wire _T_2622 = bus_ifu_wr_en_ff & _T_2621; // @[ifu_mem_ctl.scala 521:48] - wire _T_2623 = ~io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 521:72] - wire bus_inc_data_beat_cnt = _T_2622 & _T_2623; // @[ifu_mem_ctl.scala 521:70] - wire [2:0] _T_2629 = bus_data_beat_count + 3'h1; // @[ifu_mem_ctl.scala 525:115] + wire _T_11 = _T_10 | err_stop_fetch; // @[ifu_mem_ctl.scala 97:112] + wire _T_13 = io_ifu_axi_r_valid & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 99:44] + wire _T_14 = _T_13 & io_ifu_axi_r_ready; // @[ifu_mem_ctl.scala 99:65] + wire _T_227 = |io_ic_rd_hit; // @[ifu_mem_ctl.scala 189:37] + wire _T_228 = ~_T_227; // @[ifu_mem_ctl.scala 189:23] + reg reset_all_tags; // @[ifu_mem_ctl.scala 638:53] + wire _T_229 = _T_228 | reset_all_tags; // @[ifu_mem_ctl.scala 189:41] + wire _T_207 = ~ifc_iccm_access_f; // @[ifu_mem_ctl.scala 180:48] + wire _T_208 = ifc_fetch_req_f & _T_207; // @[ifu_mem_ctl.scala 180:46] + reg ifc_region_acc_fault_final_f; // @[ifu_mem_ctl.scala 231:71] + wire _T_209 = ~ifc_region_acc_fault_final_f; // @[ifu_mem_ctl.scala 180:69] + wire fetch_req_icache_f = _T_208 & _T_209; // @[ifu_mem_ctl.scala 180:67] + wire _T_230 = _T_229 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 189:59] + wire _T_231 = ~miss_pending; // @[ifu_mem_ctl.scala 189:82] + wire _T_232 = _T_230 & _T_231; // @[ifu_mem_ctl.scala 189:80] + wire _T_233 = _T_232 | scnd_miss_req; // @[ifu_mem_ctl.scala 189:97] + wire ic_act_miss_f = _T_233 & _T_209; // @[ifu_mem_ctl.scala 189:114] + reg ifu_bus_rvalid_unq_ff; // @[ifu_mem_ctl.scala 511:56] + reg bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 463:61] + wire ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 525:49] + wire bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; // @[ifu_mem_ctl.scala 553:41] + reg uncacheable_miss_ff; // @[ifu_mem_ctl.scala 216:62] + reg [2:0] bus_data_beat_count; // @[ifu_mem_ctl.scala 534:56] + wire _T_2672 = bus_data_beat_count == 3'h1; // @[ifu_mem_ctl.scala 551:69] + wire _T_2673 = &bus_data_beat_count; // @[ifu_mem_ctl.scala 551:101] + wire bus_last_data_beat = uncacheable_miss_ff ? _T_2672 : _T_2673; // @[ifu_mem_ctl.scala 551:28] + wire _T_2624 = bus_ifu_wr_en_ff & bus_last_data_beat; // @[ifu_mem_ctl.scala 530:68] + wire _T_2625 = ic_act_miss_f | _T_2624; // @[ifu_mem_ctl.scala 530:48] + wire bus_reset_data_beat_cnt = _T_2625 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 530:91] + wire _T_2621 = ~bus_last_data_beat; // @[ifu_mem_ctl.scala 529:50] + wire _T_2622 = bus_ifu_wr_en_ff & _T_2621; // @[ifu_mem_ctl.scala 529:48] + wire _T_2623 = ~io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 529:72] + wire bus_inc_data_beat_cnt = _T_2622 & _T_2623; // @[ifu_mem_ctl.scala 529:70] + wire [2:0] _T_2629 = bus_data_beat_count + 3'h1; // @[ifu_mem_ctl.scala 533:115] wire [2:0] _T_2631 = bus_inc_data_beat_cnt ? _T_2629 : 3'h0; // @[Mux.scala 27:72] - wire _T_2626 = ~bus_inc_data_beat_cnt; // @[ifu_mem_ctl.scala 523:32] - wire _T_2627 = ~bus_reset_data_beat_cnt; // @[ifu_mem_ctl.scala 523:57] - wire bus_hold_data_beat_cnt = _T_2626 & _T_2627; // @[ifu_mem_ctl.scala 523:55] + wire _T_2626 = ~bus_inc_data_beat_cnt; // @[ifu_mem_ctl.scala 531:32] + wire _T_2627 = ~bus_reset_data_beat_cnt; // @[ifu_mem_ctl.scala 531:57] + wire bus_hold_data_beat_cnt = _T_2626 & _T_2627; // @[ifu_mem_ctl.scala 531:55] wire [2:0] _T_2632 = bus_hold_data_beat_cnt ? bus_data_beat_count : 3'h0; // @[Mux.scala 27:72] wire [2:0] bus_new_data_beat_count = _T_2631 | _T_2632; // @[Mux.scala 27:72] - wire _T_15 = &bus_new_data_beat_count; // @[ifu_mem_ctl.scala 117:112] - wire _T_16 = _T_14 & _T_15; // @[ifu_mem_ctl.scala 117:85] - wire _T_17 = ~uncacheable_miss_ff; // @[ifu_mem_ctl.scala 118:5] - wire _T_18 = _T_16 & _T_17; // @[ifu_mem_ctl.scala 117:118] - wire _T_19 = miss_state == 3'h5; // @[ifu_mem_ctl.scala 118:41] + wire _T_15 = &bus_new_data_beat_count; // @[ifu_mem_ctl.scala 99:112] + wire _T_16 = _T_14 & _T_15; // @[ifu_mem_ctl.scala 99:85] + wire _T_17 = ~uncacheable_miss_ff; // @[ifu_mem_ctl.scala 100:5] + wire _T_18 = _T_16 & _T_17; // @[ifu_mem_ctl.scala 99:118] + wire _T_19 = miss_state == 3'h5; // @[ifu_mem_ctl.scala 100:41] wire _T_24 = 3'h0 == miss_state; // @[Conditional.scala 37:30] - wire _T_26 = ic_act_miss_f & _T_319; // @[ifu_mem_ctl.scala 124:43] - wire [2:0] _T_28 = _T_26 ? 3'h1 : 3'h2; // @[ifu_mem_ctl.scala 124:27] + wire _T_26 = ic_act_miss_f & _T_319; // @[ifu_mem_ctl.scala 106:43] + wire [2:0] _T_28 = _T_26 ? 3'h1 : 3'h2; // @[ifu_mem_ctl.scala 106:27] wire _T_31 = 3'h1 == miss_state; // @[Conditional.scala 37:30] - wire [4:0] byp_fetch_index = ifu_fetch_addr_int_f[4:0]; // @[ifu_mem_ctl.scala 357:45] - wire _T_2155 = byp_fetch_index[4:2] == 3'h0; // @[ifu_mem_ctl.scala 378:127] - reg [7:0] ic_miss_buff_data_valid; // @[ifu_mem_ctl.scala 334:60] + wire [4:0] byp_fetch_index = ifu_fetch_addr_int_f[4:0]; // @[ifu_mem_ctl.scala 343:45] + wire _T_2155 = byp_fetch_index[4:2] == 3'h0; // @[ifu_mem_ctl.scala 364:127] + reg [7:0] ic_miss_buff_data_valid; // @[ifu_mem_ctl.scala 320:60] wire _T_2186 = _T_2155 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72] - wire _T_2159 = byp_fetch_index[4:2] == 3'h1; // @[ifu_mem_ctl.scala 378:127] + wire _T_2159 = byp_fetch_index[4:2] == 3'h1; // @[ifu_mem_ctl.scala 364:127] wire _T_2187 = _T_2159 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72] wire _T_2194 = _T_2186 | _T_2187; // @[Mux.scala 27:72] - wire _T_2163 = byp_fetch_index[4:2] == 3'h2; // @[ifu_mem_ctl.scala 378:127] + wire _T_2163 = byp_fetch_index[4:2] == 3'h2; // @[ifu_mem_ctl.scala 364:127] wire _T_2188 = _T_2163 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72] wire _T_2195 = _T_2194 | _T_2188; // @[Mux.scala 27:72] - wire _T_2167 = byp_fetch_index[4:2] == 3'h3; // @[ifu_mem_ctl.scala 378:127] + wire _T_2167 = byp_fetch_index[4:2] == 3'h3; // @[ifu_mem_ctl.scala 364:127] wire _T_2189 = _T_2167 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72] wire _T_2196 = _T_2195 | _T_2189; // @[Mux.scala 27:72] - wire _T_2171 = byp_fetch_index[4:2] == 3'h4; // @[ifu_mem_ctl.scala 378:127] + wire _T_2171 = byp_fetch_index[4:2] == 3'h4; // @[ifu_mem_ctl.scala 364:127] wire _T_2190 = _T_2171 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72] wire _T_2197 = _T_2196 | _T_2190; // @[Mux.scala 27:72] - wire _T_2175 = byp_fetch_index[4:2] == 3'h5; // @[ifu_mem_ctl.scala 378:127] + wire _T_2175 = byp_fetch_index[4:2] == 3'h5; // @[ifu_mem_ctl.scala 364:127] wire _T_2191 = _T_2175 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72] wire _T_2198 = _T_2197 | _T_2191; // @[Mux.scala 27:72] - wire _T_2179 = byp_fetch_index[4:2] == 3'h6; // @[ifu_mem_ctl.scala 378:127] + wire _T_2179 = byp_fetch_index[4:2] == 3'h6; // @[ifu_mem_ctl.scala 364:127] wire _T_2192 = _T_2179 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72] wire _T_2199 = _T_2198 | _T_2192; // @[Mux.scala 27:72] - wire _T_2183 = byp_fetch_index[4:2] == 3'h7; // @[ifu_mem_ctl.scala 378:127] + wire _T_2183 = byp_fetch_index[4:2] == 3'h7; // @[ifu_mem_ctl.scala 364:127] wire _T_2193 = _T_2183 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72] wire ic_miss_buff_data_valid_bypass_index = _T_2199 | _T_2193; // @[Mux.scala 27:72] - wire _T_2241 = ~byp_fetch_index[1]; // @[ifu_mem_ctl.scala 380:69] - wire _T_2242 = ic_miss_buff_data_valid_bypass_index & _T_2241; // @[ifu_mem_ctl.scala 380:67] - wire _T_2244 = ~byp_fetch_index[0]; // @[ifu_mem_ctl.scala 380:91] - wire _T_2245 = _T_2242 & _T_2244; // @[ifu_mem_ctl.scala 380:89] - wire _T_2250 = _T_2242 & byp_fetch_index[0]; // @[ifu_mem_ctl.scala 381:65] - wire _T_2251 = _T_2245 | _T_2250; // @[ifu_mem_ctl.scala 380:112] - wire _T_2253 = ic_miss_buff_data_valid_bypass_index & byp_fetch_index[1]; // @[ifu_mem_ctl.scala 382:43] - wire _T_2256 = _T_2253 & _T_2244; // @[ifu_mem_ctl.scala 382:65] - wire _T_2257 = _T_2251 | _T_2256; // @[ifu_mem_ctl.scala 381:88] - wire _T_2261 = _T_2253 & byp_fetch_index[0]; // @[ifu_mem_ctl.scala 383:65] - wire [2:0] byp_fetch_index_inc = ifu_fetch_addr_int_f[4:2] + 3'h1; // @[ifu_mem_ctl.scala 360:75] - wire _T_2201 = byp_fetch_index_inc == 3'h0; // @[ifu_mem_ctl.scala 379:110] + wire _T_2241 = ~byp_fetch_index[1]; // @[ifu_mem_ctl.scala 366:69] + wire _T_2242 = ic_miss_buff_data_valid_bypass_index & _T_2241; // @[ifu_mem_ctl.scala 366:67] + wire _T_2244 = ~byp_fetch_index[0]; // @[ifu_mem_ctl.scala 366:91] + wire _T_2245 = _T_2242 & _T_2244; // @[ifu_mem_ctl.scala 366:89] + wire _T_2250 = _T_2242 & byp_fetch_index[0]; // @[ifu_mem_ctl.scala 367:65] + wire _T_2251 = _T_2245 | _T_2250; // @[ifu_mem_ctl.scala 366:112] + wire _T_2253 = ic_miss_buff_data_valid_bypass_index & byp_fetch_index[1]; // @[ifu_mem_ctl.scala 368:43] + wire _T_2256 = _T_2253 & _T_2244; // @[ifu_mem_ctl.scala 368:65] + wire _T_2257 = _T_2251 | _T_2256; // @[ifu_mem_ctl.scala 367:88] + wire _T_2261 = _T_2253 & byp_fetch_index[0]; // @[ifu_mem_ctl.scala 369:65] + wire [2:0] byp_fetch_index_inc = ifu_fetch_addr_int_f[4:2] + 3'h1; // @[ifu_mem_ctl.scala 346:75] + wire _T_2201 = byp_fetch_index_inc == 3'h0; // @[ifu_mem_ctl.scala 365:110] wire _T_2225 = _T_2201 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72] - wire _T_2204 = byp_fetch_index_inc == 3'h1; // @[ifu_mem_ctl.scala 379:110] + wire _T_2204 = byp_fetch_index_inc == 3'h1; // @[ifu_mem_ctl.scala 365:110] wire _T_2226 = _T_2204 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72] wire _T_2233 = _T_2225 | _T_2226; // @[Mux.scala 27:72] - wire _T_2207 = byp_fetch_index_inc == 3'h2; // @[ifu_mem_ctl.scala 379:110] + wire _T_2207 = byp_fetch_index_inc == 3'h2; // @[ifu_mem_ctl.scala 365:110] wire _T_2227 = _T_2207 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72] wire _T_2234 = _T_2233 | _T_2227; // @[Mux.scala 27:72] - wire _T_2210 = byp_fetch_index_inc == 3'h3; // @[ifu_mem_ctl.scala 379:110] + wire _T_2210 = byp_fetch_index_inc == 3'h3; // @[ifu_mem_ctl.scala 365:110] wire _T_2228 = _T_2210 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72] wire _T_2235 = _T_2234 | _T_2228; // @[Mux.scala 27:72] - wire _T_2213 = byp_fetch_index_inc == 3'h4; // @[ifu_mem_ctl.scala 379:110] + wire _T_2213 = byp_fetch_index_inc == 3'h4; // @[ifu_mem_ctl.scala 365:110] wire _T_2229 = _T_2213 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72] wire _T_2236 = _T_2235 | _T_2229; // @[Mux.scala 27:72] - wire _T_2216 = byp_fetch_index_inc == 3'h5; // @[ifu_mem_ctl.scala 379:110] + wire _T_2216 = byp_fetch_index_inc == 3'h5; // @[ifu_mem_ctl.scala 365:110] wire _T_2230 = _T_2216 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72] wire _T_2237 = _T_2236 | _T_2230; // @[Mux.scala 27:72] - wire _T_2219 = byp_fetch_index_inc == 3'h6; // @[ifu_mem_ctl.scala 379:110] + wire _T_2219 = byp_fetch_index_inc == 3'h6; // @[ifu_mem_ctl.scala 365:110] wire _T_2231 = _T_2219 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72] wire _T_2238 = _T_2237 | _T_2231; // @[Mux.scala 27:72] - wire _T_2222 = byp_fetch_index_inc == 3'h7; // @[ifu_mem_ctl.scala 379:110] + wire _T_2222 = byp_fetch_index_inc == 3'h7; // @[ifu_mem_ctl.scala 365:110] wire _T_2232 = _T_2222 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72] wire ic_miss_buff_data_valid_inc_bypass_index = _T_2238 | _T_2232; // @[Mux.scala 27:72] - wire _T_2262 = _T_2261 & ic_miss_buff_data_valid_inc_bypass_index; // @[ifu_mem_ctl.scala 383:87] - wire _T_2263 = _T_2257 | _T_2262; // @[ifu_mem_ctl.scala 382:88] - wire _T_2267 = ic_miss_buff_data_valid_bypass_index & _T_2183; // @[ifu_mem_ctl.scala 384:43] - wire miss_buff_hit_unq_f = _T_2263 | _T_2267; // @[ifu_mem_ctl.scala 383:131] - wire _T_2283 = miss_state == 3'h4; // @[ifu_mem_ctl.scala 389:55] - wire _T_2284 = miss_state == 3'h1; // @[ifu_mem_ctl.scala 389:87] - wire _T_2285 = _T_2283 | _T_2284; // @[ifu_mem_ctl.scala 389:74] - wire crit_byp_hit_f = miss_buff_hit_unq_f & _T_2285; // @[ifu_mem_ctl.scala 389:41] - wire _T_2268 = miss_state == 3'h6; // @[ifu_mem_ctl.scala 386:30] - reg [30:0] imb_ff; // @[ifu_mem_ctl.scala 234:49] - wire miss_wrap_f = imb_ff[5] != ifu_fetch_addr_int_f[5]; // @[ifu_mem_ctl.scala 377:51] - wire _T_2269 = ~miss_wrap_f; // @[ifu_mem_ctl.scala 386:68] - wire _T_2270 = miss_buff_hit_unq_f & _T_2269; // @[ifu_mem_ctl.scala 386:66] - wire stream_hit_f = _T_2268 & _T_2270; // @[ifu_mem_ctl.scala 386:43] - wire _T_215 = crit_byp_hit_f | stream_hit_f; // @[ifu_mem_ctl.scala 201:35] - wire _T_216 = _T_215 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 201:52] - wire ic_byp_hit_f = _T_216 & miss_pending; // @[ifu_mem_ctl.scala 201:73] - reg last_data_recieved_ff; // @[ifu_mem_ctl.scala 528:58] - wire last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 555:35] - wire _T_32 = bus_ifu_wr_en_ff & last_beat; // @[ifu_mem_ctl.scala 128:126] - wire _T_33 = last_data_recieved_ff | _T_32; // @[ifu_mem_ctl.scala 128:106] - wire _T_34 = ic_byp_hit_f & _T_33; // @[ifu_mem_ctl.scala 128:80] - wire _T_35 = _T_34 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 128:140] - wire _T_36 = io_dec_mem_ctrl_dec_tlu_force_halt | _T_35; // @[ifu_mem_ctl.scala 128:64] - wire _T_38 = ~last_data_recieved_ff; // @[ifu_mem_ctl.scala 129:30] - wire _T_39 = ic_byp_hit_f & _T_38; // @[ifu_mem_ctl.scala 129:27] - wire _T_40 = _T_39 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 129:53] - wire _T_42 = ~ic_byp_hit_f; // @[ifu_mem_ctl.scala 130:16] - wire _T_44 = _T_42 & _T_319; // @[ifu_mem_ctl.scala 130:30] - wire _T_46 = _T_44 & _T_32; // @[ifu_mem_ctl.scala 130:52] - wire _T_47 = _T_46 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 130:85] - wire _T_51 = _T_32 & _T_17; // @[ifu_mem_ctl.scala 131:49] - wire _T_54 = ic_byp_hit_f & _T_319; // @[ifu_mem_ctl.scala 132:33] - wire _T_56 = ~_T_32; // @[ifu_mem_ctl.scala 132:57] - wire _T_57 = _T_54 & _T_56; // @[ifu_mem_ctl.scala 132:55] - wire ifu_bp_hit_taken_q_f = io_ifu_bp_hit_taken_f & io_ic_hit_f; // @[ifu_mem_ctl.scala 120:52] - wire _T_58 = ~ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 132:91] - wire _T_59 = _T_57 & _T_58; // @[ifu_mem_ctl.scala 132:89] - wire _T_61 = _T_59 & _T_17; // @[ifu_mem_ctl.scala 132:113] - wire _T_64 = bus_ifu_wr_en_ff & _T_319; // @[ifu_mem_ctl.scala 133:39] - wire _T_67 = _T_64 & _T_56; // @[ifu_mem_ctl.scala 133:61] - wire _T_69 = _T_67 & _T_58; // @[ifu_mem_ctl.scala 133:95] - wire _T_71 = _T_69 & _T_17; // @[ifu_mem_ctl.scala 133:119] - wire _T_79 = _T_46 & _T_17; // @[ifu_mem_ctl.scala 134:100] - wire _T_81 = io_exu_flush_final | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 135:44] - wire _T_84 = _T_81 & _T_56; // @[ifu_mem_ctl.scala 135:68] - wire [2:0] _T_86 = _T_84 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 135:22] - wire [2:0] _T_87 = _T_79 ? 3'h0 : _T_86; // @[ifu_mem_ctl.scala 134:20] - wire [2:0] _T_88 = _T_71 ? 3'h6 : _T_87; // @[ifu_mem_ctl.scala 133:20] - wire [2:0] _T_89 = _T_61 ? 3'h6 : _T_88; // @[ifu_mem_ctl.scala 132:18] - wire [2:0] _T_90 = _T_51 ? 3'h0 : _T_89; // @[ifu_mem_ctl.scala 131:16] - wire [2:0] _T_91 = _T_47 ? 3'h4 : _T_90; // @[ifu_mem_ctl.scala 130:14] - wire [2:0] _T_92 = _T_40 ? 3'h3 : _T_91; // @[ifu_mem_ctl.scala 129:12] - wire [2:0] _T_93 = _T_36 ? 3'h0 : _T_92; // @[ifu_mem_ctl.scala 128:27] + wire _T_2262 = _T_2261 & ic_miss_buff_data_valid_inc_bypass_index; // @[ifu_mem_ctl.scala 369:87] + wire _T_2263 = _T_2257 | _T_2262; // @[ifu_mem_ctl.scala 368:88] + wire _T_2267 = ic_miss_buff_data_valid_bypass_index & _T_2183; // @[ifu_mem_ctl.scala 370:43] + wire miss_buff_hit_unq_f = _T_2263 | _T_2267; // @[ifu_mem_ctl.scala 369:131] + wire _T_2283 = miss_state == 3'h4; // @[ifu_mem_ctl.scala 375:55] + wire _T_2284 = miss_state == 3'h1; // @[ifu_mem_ctl.scala 375:87] + wire _T_2285 = _T_2283 | _T_2284; // @[ifu_mem_ctl.scala 375:74] + wire crit_byp_hit_f = miss_buff_hit_unq_f & _T_2285; // @[ifu_mem_ctl.scala 375:41] + wire _T_2268 = miss_state == 3'h6; // @[ifu_mem_ctl.scala 372:30] + reg [30:0] imb_ff; // @[ifu_mem_ctl.scala 217:49] + wire miss_wrap_f = imb_ff[5] != ifu_fetch_addr_int_f[5]; // @[ifu_mem_ctl.scala 363:51] + wire _T_2269 = ~miss_wrap_f; // @[ifu_mem_ctl.scala 372:68] + wire _T_2270 = miss_buff_hit_unq_f & _T_2269; // @[ifu_mem_ctl.scala 372:66] + wire stream_hit_f = _T_2268 & _T_2270; // @[ifu_mem_ctl.scala 372:43] + wire _T_215 = crit_byp_hit_f | stream_hit_f; // @[ifu_mem_ctl.scala 184:35] + wire _T_216 = _T_215 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 184:52] + wire ic_byp_hit_f = _T_216 & miss_pending; // @[ifu_mem_ctl.scala 184:73] + reg last_data_recieved_ff; // @[ifu_mem_ctl.scala 536:58] + wire last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 563:35] + wire _T_32 = bus_ifu_wr_en_ff & last_beat; // @[ifu_mem_ctl.scala 110:126] + wire _T_33 = last_data_recieved_ff | _T_32; // @[ifu_mem_ctl.scala 110:106] + wire _T_34 = ic_byp_hit_f & _T_33; // @[ifu_mem_ctl.scala 110:80] + wire _T_35 = _T_34 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 110:140] + wire _T_36 = io_dec_mem_ctrl_dec_tlu_force_halt | _T_35; // @[ifu_mem_ctl.scala 110:64] + wire _T_38 = ~last_data_recieved_ff; // @[ifu_mem_ctl.scala 111:30] + wire _T_39 = ic_byp_hit_f & _T_38; // @[ifu_mem_ctl.scala 111:27] + wire _T_40 = _T_39 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 111:53] + wire _T_42 = ~ic_byp_hit_f; // @[ifu_mem_ctl.scala 112:16] + wire _T_44 = _T_42 & _T_319; // @[ifu_mem_ctl.scala 112:30] + wire _T_46 = _T_44 & _T_32; // @[ifu_mem_ctl.scala 112:52] + wire _T_47 = _T_46 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 112:85] + wire _T_51 = _T_32 & _T_17; // @[ifu_mem_ctl.scala 113:49] + wire _T_54 = ic_byp_hit_f & _T_319; // @[ifu_mem_ctl.scala 114:33] + wire _T_56 = ~_T_32; // @[ifu_mem_ctl.scala 114:57] + wire _T_57 = _T_54 & _T_56; // @[ifu_mem_ctl.scala 114:55] + wire ifu_bp_hit_taken_q_f = io_ifu_bp_hit_taken_f & io_ic_hit_f; // @[ifu_mem_ctl.scala 102:52] + wire _T_58 = ~ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 114:91] + wire _T_59 = _T_57 & _T_58; // @[ifu_mem_ctl.scala 114:89] + wire _T_61 = _T_59 & _T_17; // @[ifu_mem_ctl.scala 114:113] + wire _T_64 = bus_ifu_wr_en_ff & _T_319; // @[ifu_mem_ctl.scala 115:39] + wire _T_67 = _T_64 & _T_56; // @[ifu_mem_ctl.scala 115:61] + wire _T_69 = _T_67 & _T_58; // @[ifu_mem_ctl.scala 115:95] + wire _T_71 = _T_69 & _T_17; // @[ifu_mem_ctl.scala 115:119] + wire _T_79 = _T_46 & _T_17; // @[ifu_mem_ctl.scala 116:100] + wire _T_81 = io_exu_flush_final | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 117:44] + wire _T_84 = _T_81 & _T_56; // @[ifu_mem_ctl.scala 117:68] + wire [2:0] _T_86 = _T_84 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 117:22] + wire [2:0] _T_87 = _T_79 ? 3'h0 : _T_86; // @[ifu_mem_ctl.scala 116:20] + wire [2:0] _T_88 = _T_71 ? 3'h6 : _T_87; // @[ifu_mem_ctl.scala 115:20] + wire [2:0] _T_89 = _T_61 ? 3'h6 : _T_88; // @[ifu_mem_ctl.scala 114:18] + wire [2:0] _T_90 = _T_51 ? 3'h0 : _T_89; // @[ifu_mem_ctl.scala 113:16] + wire [2:0] _T_91 = _T_47 ? 3'h4 : _T_90; // @[ifu_mem_ctl.scala 112:14] + wire [2:0] _T_92 = _T_40 ? 3'h3 : _T_91; // @[ifu_mem_ctl.scala 111:12] + wire [2:0] _T_93 = _T_36 ? 3'h0 : _T_92; // @[ifu_mem_ctl.scala 110:27] wire _T_102 = 3'h4 == miss_state; // @[Conditional.scala 37:30] wire _T_106 = 3'h6 == miss_state; // @[Conditional.scala 37:30] - wire _T_2280 = byp_fetch_index[4:1] == 4'hf; // @[ifu_mem_ctl.scala 388:60] - wire _T_2281 = _T_2280 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 388:94] - wire stream_eol_f = _T_2281 & stream_hit_f; // @[ifu_mem_ctl.scala 388:112] - wire _T_108 = _T_81 | stream_eol_f; // @[ifu_mem_ctl.scala 143:72] - wire _T_111 = _T_108 & _T_56; // @[ifu_mem_ctl.scala 143:87] - wire _T_113 = _T_111 & _T_2623; // @[ifu_mem_ctl.scala 143:122] - wire [2:0] _T_115 = _T_113 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 143:27] + wire _T_2280 = byp_fetch_index[4:1] == 4'hf; // @[ifu_mem_ctl.scala 374:60] + wire _T_2281 = _T_2280 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 374:94] + wire stream_eol_f = _T_2281 & stream_hit_f; // @[ifu_mem_ctl.scala 374:112] + wire _T_108 = _T_81 | stream_eol_f; // @[ifu_mem_ctl.scala 125:72] + wire _T_111 = _T_108 & _T_56; // @[ifu_mem_ctl.scala 125:87] + wire _T_113 = _T_111 & _T_2623; // @[ifu_mem_ctl.scala 125:122] + wire [2:0] _T_115 = _T_113 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 125:27] wire _T_121 = 3'h3 == miss_state; // @[Conditional.scala 37:30] - wire _T_124 = io_exu_flush_final & _T_56; // @[ifu_mem_ctl.scala 147:48] - wire _T_126 = _T_124 & _T_2623; // @[ifu_mem_ctl.scala 147:82] - wire [2:0] _T_128 = _T_126 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 147:27] + wire _T_124 = io_exu_flush_final & _T_56; // @[ifu_mem_ctl.scala 129:48] + wire _T_126 = _T_124 & _T_2623; // @[ifu_mem_ctl.scala 129:82] + wire [2:0] _T_128 = _T_126 ? 3'h2 : 3'h0; // @[ifu_mem_ctl.scala 129:27] wire _T_132 = 3'h2 == miss_state; // @[Conditional.scala 37:30] - wire _T_236 = io_ic_rd_hit == 2'h0; // @[ifu_mem_ctl.scala 207:28] - wire _T_237 = _T_236 | reset_all_tags; // @[ifu_mem_ctl.scala 207:42] - wire _T_238 = _T_237 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 207:60] - wire _T_239 = miss_state == 3'h2; // @[ifu_mem_ctl.scala 207:94] - wire _T_240 = _T_238 & _T_239; // @[ifu_mem_ctl.scala 207:81] - wire _T_243 = imb_ff[30:5] != ifu_fetch_addr_int_f[30:5]; // @[ifu_mem_ctl.scala 208:39] - wire _T_244 = _T_240 & _T_243; // @[ifu_mem_ctl.scala 207:111] - wire _T_246 = _T_244 & _T_17; // @[ifu_mem_ctl.scala 208:91] - reg sel_mb_addr_ff; // @[ifu_mem_ctl.scala 262:51] - wire _T_247 = ~sel_mb_addr_ff; // @[ifu_mem_ctl.scala 208:116] - wire _T_248 = _T_246 & _T_247; // @[ifu_mem_ctl.scala 208:114] - wire ic_miss_under_miss_f = _T_248 & _T_209; // @[ifu_mem_ctl.scala 208:132] - wire _T_135 = ic_miss_under_miss_f & _T_56; // @[ifu_mem_ctl.scala 151:50] - wire _T_137 = _T_135 & _T_2623; // @[ifu_mem_ctl.scala 151:84] - wire _T_256 = _T_230 & _T_239; // @[ifu_mem_ctl.scala 209:85] - wire _T_259 = imb_ff[30:5] == ifu_fetch_addr_int_f[30:5]; // @[ifu_mem_ctl.scala 210:39] - wire _T_260 = _T_259 | uncacheable_miss_ff; // @[ifu_mem_ctl.scala 210:91] - wire ic_ignore_2nd_miss_f = _T_256 & _T_260; // @[ifu_mem_ctl.scala 209:117] - wire _T_141 = ic_ignore_2nd_miss_f & _T_56; // @[ifu_mem_ctl.scala 152:35] - wire _T_143 = _T_141 & _T_2623; // @[ifu_mem_ctl.scala 152:69] - wire [2:0] _T_145 = _T_143 ? 3'h7 : 3'h0; // @[ifu_mem_ctl.scala 152:12] - wire [2:0] _T_146 = _T_137 ? 3'h5 : _T_145; // @[ifu_mem_ctl.scala 151:27] + wire _T_236 = io_ic_rd_hit == 2'h0; // @[ifu_mem_ctl.scala 190:28] + wire _T_237 = _T_236 | reset_all_tags; // @[ifu_mem_ctl.scala 190:42] + wire _T_238 = _T_237 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 190:60] + wire _T_239 = miss_state == 3'h2; // @[ifu_mem_ctl.scala 190:94] + wire _T_240 = _T_238 & _T_239; // @[ifu_mem_ctl.scala 190:81] + wire _T_243 = imb_ff[30:5] != ifu_fetch_addr_int_f[30:5]; // @[ifu_mem_ctl.scala 191:39] + wire _T_244 = _T_240 & _T_243; // @[ifu_mem_ctl.scala 190:111] + wire _T_246 = _T_244 & _T_17; // @[ifu_mem_ctl.scala 191:91] + reg sel_mb_addr_ff; // @[ifu_mem_ctl.scala 245:51] + wire _T_247 = ~sel_mb_addr_ff; // @[ifu_mem_ctl.scala 191:116] + wire _T_248 = _T_246 & _T_247; // @[ifu_mem_ctl.scala 191:114] + wire ic_miss_under_miss_f = _T_248 & _T_209; // @[ifu_mem_ctl.scala 191:132] + wire _T_135 = ic_miss_under_miss_f & _T_56; // @[ifu_mem_ctl.scala 133:50] + wire _T_137 = _T_135 & _T_2623; // @[ifu_mem_ctl.scala 133:84] + wire _T_256 = _T_230 & _T_239; // @[ifu_mem_ctl.scala 192:85] + wire _T_259 = imb_ff[30:5] == ifu_fetch_addr_int_f[30:5]; // @[ifu_mem_ctl.scala 193:39] + wire _T_260 = _T_259 | uncacheable_miss_ff; // @[ifu_mem_ctl.scala 193:91] + wire ic_ignore_2nd_miss_f = _T_256 & _T_260; // @[ifu_mem_ctl.scala 192:117] + wire _T_141 = ic_ignore_2nd_miss_f & _T_56; // @[ifu_mem_ctl.scala 134:35] + wire _T_143 = _T_141 & _T_2623; // @[ifu_mem_ctl.scala 134:69] + wire [2:0] _T_145 = _T_143 ? 3'h7 : 3'h0; // @[ifu_mem_ctl.scala 134:12] + wire [2:0] _T_146 = _T_137 ? 3'h5 : _T_145; // @[ifu_mem_ctl.scala 133:27] wire _T_151 = 3'h5 == miss_state; // @[Conditional.scala 37:30] - wire [2:0] _T_154 = _T_32 ? 3'h0 : 3'h2; // @[ifu_mem_ctl.scala 157:12] - wire [2:0] _T_155 = io_exu_flush_final ? _T_154 : 3'h1; // @[ifu_mem_ctl.scala 156:75] - wire [2:0] _T_156 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_155; // @[ifu_mem_ctl.scala 156:27] + wire [2:0] _T_154 = _T_32 ? 3'h0 : 3'h2; // @[ifu_mem_ctl.scala 139:12] + wire [2:0] _T_155 = io_exu_flush_final ? _T_154 : 3'h1; // @[ifu_mem_ctl.scala 138:75] + wire [2:0] _T_156 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_155; // @[ifu_mem_ctl.scala 138:27] wire _T_160 = 3'h7 == miss_state; // @[Conditional.scala 37:30] - wire [2:0] _T_164 = io_exu_flush_final ? _T_154 : 3'h0; // @[ifu_mem_ctl.scala 161:75] - wire [2:0] _T_165 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_164; // @[ifu_mem_ctl.scala 161:27] + wire [2:0] _T_164 = io_exu_flush_final ? _T_154 : 3'h0; // @[ifu_mem_ctl.scala 143:75] + wire [2:0] _T_165 = io_dec_mem_ctrl_dec_tlu_force_halt ? 3'h0 : _T_164; // @[ifu_mem_ctl.scala 143:27] wire [2:0] _GEN_0 = _T_160 ? _T_165 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_2 = _T_151 ? _T_156 : _GEN_0; // @[Conditional.scala 39:67] wire [2:0] _GEN_4 = _T_132 ? _T_146 : _GEN_2; // @[Conditional.scala 39:67] @@ -1302,28 +1302,28 @@ module ifu_mem_ctl( wire [2:0] _GEN_10 = _T_102 ? 3'h0 : _GEN_8; // @[Conditional.scala 39:67] wire [2:0] _GEN_12 = _T_31 ? _T_93 : _GEN_10; // @[Conditional.scala 39:67] wire [2:0] miss_nxtstate = _T_24 ? _T_28 : _GEN_12; // @[Conditional.scala 40:58] - wire _T_20 = miss_nxtstate == 3'h5; // @[ifu_mem_ctl.scala 118:73] - wire _T_21 = _T_19 | _T_20; // @[ifu_mem_ctl.scala 118:57] - wire _T_22 = _T_18 & _T_21; // @[ifu_mem_ctl.scala 118:26] - wire _T_30 = ic_act_miss_f & _T_2623; // @[ifu_mem_ctl.scala 125:38] - wire _T_94 = io_dec_mem_ctrl_dec_tlu_force_halt | io_exu_flush_final; // @[ifu_mem_ctl.scala 136:59] - wire _T_95 = _T_94 | ic_byp_hit_f; // @[ifu_mem_ctl.scala 136:80] - wire _T_96 = _T_95 | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 136:95] - wire _T_98 = _T_96 | _T_32; // @[ifu_mem_ctl.scala 136:118] - wire _T_100 = bus_ifu_wr_en_ff & _T_17; // @[ifu_mem_ctl.scala 136:171] - wire _T_101 = _T_98 | _T_100; // @[ifu_mem_ctl.scala 136:151] - wire _T_103 = io_exu_flush_final | flush_final_f; // @[ifu_mem_ctl.scala 140:43] - wire _T_104 = _T_103 | ic_byp_hit_f; // @[ifu_mem_ctl.scala 140:59] - wire _T_105 = _T_104 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 140:74] - wire _T_119 = _T_108 | _T_32; // @[ifu_mem_ctl.scala 144:84] - wire _T_120 = _T_119 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 144:118] - wire _T_130 = io_exu_flush_final | _T_32; // @[ifu_mem_ctl.scala 148:43] - wire _T_131 = _T_130 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 148:76] - wire _T_148 = _T_32 | ic_miss_under_miss_f; // @[ifu_mem_ctl.scala 153:55] - wire _T_149 = _T_148 | ic_ignore_2nd_miss_f; // @[ifu_mem_ctl.scala 153:78] - wire _T_150 = _T_149 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 153:101] - wire _T_158 = _T_32 | io_exu_flush_final; // @[ifu_mem_ctl.scala 158:55] - wire _T_159 = _T_158 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 158:76] + wire _T_20 = miss_nxtstate == 3'h5; // @[ifu_mem_ctl.scala 100:73] + wire _T_21 = _T_19 | _T_20; // @[ifu_mem_ctl.scala 100:57] + wire _T_22 = _T_18 & _T_21; // @[ifu_mem_ctl.scala 100:26] + wire _T_30 = ic_act_miss_f & _T_2623; // @[ifu_mem_ctl.scala 107:38] + wire _T_94 = io_dec_mem_ctrl_dec_tlu_force_halt | io_exu_flush_final; // @[ifu_mem_ctl.scala 118:59] + wire _T_95 = _T_94 | ic_byp_hit_f; // @[ifu_mem_ctl.scala 118:80] + wire _T_96 = _T_95 | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 118:95] + wire _T_98 = _T_96 | _T_32; // @[ifu_mem_ctl.scala 118:118] + wire _T_100 = bus_ifu_wr_en_ff & _T_17; // @[ifu_mem_ctl.scala 118:171] + wire _T_101 = _T_98 | _T_100; // @[ifu_mem_ctl.scala 118:151] + wire _T_103 = io_exu_flush_final | flush_final_f; // @[ifu_mem_ctl.scala 122:43] + wire _T_104 = _T_103 | ic_byp_hit_f; // @[ifu_mem_ctl.scala 122:59] + wire _T_105 = _T_104 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 122:74] + wire _T_119 = _T_108 | _T_32; // @[ifu_mem_ctl.scala 126:84] + wire _T_120 = _T_119 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 126:118] + wire _T_130 = io_exu_flush_final | _T_32; // @[ifu_mem_ctl.scala 130:43] + wire _T_131 = _T_130 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 130:76] + wire _T_148 = _T_32 | ic_miss_under_miss_f; // @[ifu_mem_ctl.scala 135:55] + wire _T_149 = _T_148 | ic_ignore_2nd_miss_f; // @[ifu_mem_ctl.scala 135:78] + wire _T_150 = _T_149 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 135:101] + wire _T_158 = _T_32 | io_exu_flush_final; // @[ifu_mem_ctl.scala 140:55] + wire _T_159 = _T_158 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 140:76] wire _GEN_1 = _T_160 & _T_159; // @[Conditional.scala 39:67] wire _GEN_3 = _T_151 ? _T_159 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_5 = _T_132 ? _T_150 : _GEN_3; // @[Conditional.scala 39:67] @@ -1332,651 +1332,651 @@ module ifu_mem_ctl( wire _GEN_11 = _T_102 ? _T_105 : _GEN_9; // @[Conditional.scala 39:67] wire _GEN_13 = _T_31 ? _T_101 : _GEN_11; // @[Conditional.scala 39:67] wire miss_state_en = _T_24 ? _T_30 : _GEN_13; // @[Conditional.scala 40:58] - wire _T_174 = ~flush_final_f; // @[ifu_mem_ctl.scala 177:95] - wire _T_175 = _T_2283 & _T_174; // @[ifu_mem_ctl.scala 177:93] - wire crit_wd_byp_ok_ff = _T_2284 | _T_175; // @[ifu_mem_ctl.scala 177:58] - wire _T_178 = miss_pending & _T_56; // @[ifu_mem_ctl.scala 178:36] - wire _T_180 = _T_2283 & io_exu_flush_final; // @[ifu_mem_ctl.scala 178:106] - wire _T_181 = ~_T_180; // @[ifu_mem_ctl.scala 178:72] - wire _T_182 = _T_178 & _T_181; // @[ifu_mem_ctl.scala 178:70] - wire _T_184 = _T_2283 & crit_byp_hit_f; // @[ifu_mem_ctl.scala 179:57] - wire _T_185 = ~_T_184; // @[ifu_mem_ctl.scala 179:23] - wire _T_186 = _T_182 & _T_185; // @[ifu_mem_ctl.scala 178:128] - wire _T_187 = _T_186 | ic_act_miss_f; // @[ifu_mem_ctl.scala 179:77] - wire _T_188 = miss_nxtstate == 3'h4; // @[ifu_mem_ctl.scala 180:36] - wire _T_189 = miss_pending & _T_188; // @[ifu_mem_ctl.scala 180:19] - wire sel_hold_imb = _T_187 | _T_189; // @[ifu_mem_ctl.scala 179:93] - wire _T_191 = _T_19 | ic_miss_under_miss_f; // @[ifu_mem_ctl.scala 182:57] - wire sel_hold_imb_scnd = _T_191 & _T_174; // @[ifu_mem_ctl.scala 182:81] - reg way_status_mb_scnd_ff; // @[ifu_mem_ctl.scala 190:64] - reg [6:0] ifu_ic_rw_int_addr_ff; // @[ifu_mem_ctl.scala 662:14] - wire _T_4671 = ifu_ic_rw_int_addr_ff == 7'h0; // @[ifu_mem_ctl.scala 658:80] + wire _T_174 = ~flush_final_f; // @[ifu_mem_ctl.scala 160:95] + wire _T_175 = _T_2283 & _T_174; // @[ifu_mem_ctl.scala 160:93] + wire crit_wd_byp_ok_ff = _T_2284 | _T_175; // @[ifu_mem_ctl.scala 160:58] + wire _T_178 = miss_pending & _T_56; // @[ifu_mem_ctl.scala 161:36] + wire _T_180 = _T_2283 & io_exu_flush_final; // @[ifu_mem_ctl.scala 161:106] + wire _T_181 = ~_T_180; // @[ifu_mem_ctl.scala 161:72] + wire _T_182 = _T_178 & _T_181; // @[ifu_mem_ctl.scala 161:70] + wire _T_184 = _T_2283 & crit_byp_hit_f; // @[ifu_mem_ctl.scala 162:57] + wire _T_185 = ~_T_184; // @[ifu_mem_ctl.scala 162:23] + wire _T_186 = _T_182 & _T_185; // @[ifu_mem_ctl.scala 161:128] + wire _T_187 = _T_186 | ic_act_miss_f; // @[ifu_mem_ctl.scala 162:77] + wire _T_188 = miss_nxtstate == 3'h4; // @[ifu_mem_ctl.scala 163:36] + wire _T_189 = miss_pending & _T_188; // @[ifu_mem_ctl.scala 163:19] + wire sel_hold_imb = _T_187 | _T_189; // @[ifu_mem_ctl.scala 162:93] + wire _T_191 = _T_19 | ic_miss_under_miss_f; // @[ifu_mem_ctl.scala 165:57] + wire sel_hold_imb_scnd = _T_191 & _T_174; // @[ifu_mem_ctl.scala 165:81] + reg way_status_mb_scnd_ff; // @[ifu_mem_ctl.scala 173:64] + reg [6:0] ifu_ic_rw_int_addr_ff; // @[ifu_mem_ctl.scala 670:14] + wire _T_4671 = ifu_ic_rw_int_addr_ff == 7'h0; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_0; // @[Reg.scala 27:20] wire _T_4799 = _T_4671 & way_status_out_0; // @[Mux.scala 27:72] - wire _T_4672 = ifu_ic_rw_int_addr_ff == 7'h1; // @[ifu_mem_ctl.scala 658:80] + wire _T_4672 = ifu_ic_rw_int_addr_ff == 7'h1; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_1; // @[Reg.scala 27:20] wire _T_4800 = _T_4672 & way_status_out_1; // @[Mux.scala 27:72] wire _T_4927 = _T_4799 | _T_4800; // @[Mux.scala 27:72] - wire _T_4673 = ifu_ic_rw_int_addr_ff == 7'h2; // @[ifu_mem_ctl.scala 658:80] + wire _T_4673 = ifu_ic_rw_int_addr_ff == 7'h2; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_2; // @[Reg.scala 27:20] wire _T_4801 = _T_4673 & way_status_out_2; // @[Mux.scala 27:72] wire _T_4928 = _T_4927 | _T_4801; // @[Mux.scala 27:72] - wire _T_4674 = ifu_ic_rw_int_addr_ff == 7'h3; // @[ifu_mem_ctl.scala 658:80] + wire _T_4674 = ifu_ic_rw_int_addr_ff == 7'h3; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_3; // @[Reg.scala 27:20] wire _T_4802 = _T_4674 & way_status_out_3; // @[Mux.scala 27:72] wire _T_4929 = _T_4928 | _T_4802; // @[Mux.scala 27:72] - wire _T_4675 = ifu_ic_rw_int_addr_ff == 7'h4; // @[ifu_mem_ctl.scala 658:80] + wire _T_4675 = ifu_ic_rw_int_addr_ff == 7'h4; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_4; // @[Reg.scala 27:20] wire _T_4803 = _T_4675 & way_status_out_4; // @[Mux.scala 27:72] wire _T_4930 = _T_4929 | _T_4803; // @[Mux.scala 27:72] - wire _T_4676 = ifu_ic_rw_int_addr_ff == 7'h5; // @[ifu_mem_ctl.scala 658:80] + wire _T_4676 = ifu_ic_rw_int_addr_ff == 7'h5; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_5; // @[Reg.scala 27:20] wire _T_4804 = _T_4676 & way_status_out_5; // @[Mux.scala 27:72] wire _T_4931 = _T_4930 | _T_4804; // @[Mux.scala 27:72] - wire _T_4677 = ifu_ic_rw_int_addr_ff == 7'h6; // @[ifu_mem_ctl.scala 658:80] + wire _T_4677 = ifu_ic_rw_int_addr_ff == 7'h6; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_6; // @[Reg.scala 27:20] wire _T_4805 = _T_4677 & way_status_out_6; // @[Mux.scala 27:72] wire _T_4932 = _T_4931 | _T_4805; // @[Mux.scala 27:72] - wire _T_4678 = ifu_ic_rw_int_addr_ff == 7'h7; // @[ifu_mem_ctl.scala 658:80] + wire _T_4678 = ifu_ic_rw_int_addr_ff == 7'h7; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_7; // @[Reg.scala 27:20] wire _T_4806 = _T_4678 & way_status_out_7; // @[Mux.scala 27:72] wire _T_4933 = _T_4932 | _T_4806; // @[Mux.scala 27:72] - wire _T_4679 = ifu_ic_rw_int_addr_ff == 7'h8; // @[ifu_mem_ctl.scala 658:80] + wire _T_4679 = ifu_ic_rw_int_addr_ff == 7'h8; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_8; // @[Reg.scala 27:20] wire _T_4807 = _T_4679 & way_status_out_8; // @[Mux.scala 27:72] wire _T_4934 = _T_4933 | _T_4807; // @[Mux.scala 27:72] - wire _T_4680 = ifu_ic_rw_int_addr_ff == 7'h9; // @[ifu_mem_ctl.scala 658:80] + wire _T_4680 = ifu_ic_rw_int_addr_ff == 7'h9; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_9; // @[Reg.scala 27:20] wire _T_4808 = _T_4680 & way_status_out_9; // @[Mux.scala 27:72] wire _T_4935 = _T_4934 | _T_4808; // @[Mux.scala 27:72] - wire _T_4681 = ifu_ic_rw_int_addr_ff == 7'ha; // @[ifu_mem_ctl.scala 658:80] + wire _T_4681 = ifu_ic_rw_int_addr_ff == 7'ha; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_10; // @[Reg.scala 27:20] wire _T_4809 = _T_4681 & way_status_out_10; // @[Mux.scala 27:72] wire _T_4936 = _T_4935 | _T_4809; // @[Mux.scala 27:72] - wire _T_4682 = ifu_ic_rw_int_addr_ff == 7'hb; // @[ifu_mem_ctl.scala 658:80] + wire _T_4682 = ifu_ic_rw_int_addr_ff == 7'hb; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_11; // @[Reg.scala 27:20] wire _T_4810 = _T_4682 & way_status_out_11; // @[Mux.scala 27:72] wire _T_4937 = _T_4936 | _T_4810; // @[Mux.scala 27:72] - wire _T_4683 = ifu_ic_rw_int_addr_ff == 7'hc; // @[ifu_mem_ctl.scala 658:80] + wire _T_4683 = ifu_ic_rw_int_addr_ff == 7'hc; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_12; // @[Reg.scala 27:20] wire _T_4811 = _T_4683 & way_status_out_12; // @[Mux.scala 27:72] wire _T_4938 = _T_4937 | _T_4811; // @[Mux.scala 27:72] - wire _T_4684 = ifu_ic_rw_int_addr_ff == 7'hd; // @[ifu_mem_ctl.scala 658:80] + wire _T_4684 = ifu_ic_rw_int_addr_ff == 7'hd; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_13; // @[Reg.scala 27:20] wire _T_4812 = _T_4684 & way_status_out_13; // @[Mux.scala 27:72] wire _T_4939 = _T_4938 | _T_4812; // @[Mux.scala 27:72] - wire _T_4685 = ifu_ic_rw_int_addr_ff == 7'he; // @[ifu_mem_ctl.scala 658:80] + wire _T_4685 = ifu_ic_rw_int_addr_ff == 7'he; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_14; // @[Reg.scala 27:20] wire _T_4813 = _T_4685 & way_status_out_14; // @[Mux.scala 27:72] wire _T_4940 = _T_4939 | _T_4813; // @[Mux.scala 27:72] - wire _T_4686 = ifu_ic_rw_int_addr_ff == 7'hf; // @[ifu_mem_ctl.scala 658:80] + wire _T_4686 = ifu_ic_rw_int_addr_ff == 7'hf; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_15; // @[Reg.scala 27:20] wire _T_4814 = _T_4686 & way_status_out_15; // @[Mux.scala 27:72] wire _T_4941 = _T_4940 | _T_4814; // @[Mux.scala 27:72] - wire _T_4687 = ifu_ic_rw_int_addr_ff == 7'h10; // @[ifu_mem_ctl.scala 658:80] + wire _T_4687 = ifu_ic_rw_int_addr_ff == 7'h10; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_16; // @[Reg.scala 27:20] wire _T_4815 = _T_4687 & way_status_out_16; // @[Mux.scala 27:72] wire _T_4942 = _T_4941 | _T_4815; // @[Mux.scala 27:72] - wire _T_4688 = ifu_ic_rw_int_addr_ff == 7'h11; // @[ifu_mem_ctl.scala 658:80] + wire _T_4688 = ifu_ic_rw_int_addr_ff == 7'h11; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_17; // @[Reg.scala 27:20] wire _T_4816 = _T_4688 & way_status_out_17; // @[Mux.scala 27:72] wire _T_4943 = _T_4942 | _T_4816; // @[Mux.scala 27:72] - wire _T_4689 = ifu_ic_rw_int_addr_ff == 7'h12; // @[ifu_mem_ctl.scala 658:80] + wire _T_4689 = ifu_ic_rw_int_addr_ff == 7'h12; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_18; // @[Reg.scala 27:20] wire _T_4817 = _T_4689 & way_status_out_18; // @[Mux.scala 27:72] wire _T_4944 = _T_4943 | _T_4817; // @[Mux.scala 27:72] - wire _T_4690 = ifu_ic_rw_int_addr_ff == 7'h13; // @[ifu_mem_ctl.scala 658:80] + wire _T_4690 = ifu_ic_rw_int_addr_ff == 7'h13; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_19; // @[Reg.scala 27:20] wire _T_4818 = _T_4690 & way_status_out_19; // @[Mux.scala 27:72] wire _T_4945 = _T_4944 | _T_4818; // @[Mux.scala 27:72] - wire _T_4691 = ifu_ic_rw_int_addr_ff == 7'h14; // @[ifu_mem_ctl.scala 658:80] + wire _T_4691 = ifu_ic_rw_int_addr_ff == 7'h14; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_20; // @[Reg.scala 27:20] wire _T_4819 = _T_4691 & way_status_out_20; // @[Mux.scala 27:72] wire _T_4946 = _T_4945 | _T_4819; // @[Mux.scala 27:72] - wire _T_4692 = ifu_ic_rw_int_addr_ff == 7'h15; // @[ifu_mem_ctl.scala 658:80] + wire _T_4692 = ifu_ic_rw_int_addr_ff == 7'h15; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_21; // @[Reg.scala 27:20] wire _T_4820 = _T_4692 & way_status_out_21; // @[Mux.scala 27:72] wire _T_4947 = _T_4946 | _T_4820; // @[Mux.scala 27:72] - wire _T_4693 = ifu_ic_rw_int_addr_ff == 7'h16; // @[ifu_mem_ctl.scala 658:80] + wire _T_4693 = ifu_ic_rw_int_addr_ff == 7'h16; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_22; // @[Reg.scala 27:20] wire _T_4821 = _T_4693 & way_status_out_22; // @[Mux.scala 27:72] wire _T_4948 = _T_4947 | _T_4821; // @[Mux.scala 27:72] - wire _T_4694 = ifu_ic_rw_int_addr_ff == 7'h17; // @[ifu_mem_ctl.scala 658:80] + wire _T_4694 = ifu_ic_rw_int_addr_ff == 7'h17; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_23; // @[Reg.scala 27:20] wire _T_4822 = _T_4694 & way_status_out_23; // @[Mux.scala 27:72] wire _T_4949 = _T_4948 | _T_4822; // @[Mux.scala 27:72] - wire _T_4695 = ifu_ic_rw_int_addr_ff == 7'h18; // @[ifu_mem_ctl.scala 658:80] + wire _T_4695 = ifu_ic_rw_int_addr_ff == 7'h18; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_24; // @[Reg.scala 27:20] wire _T_4823 = _T_4695 & way_status_out_24; // @[Mux.scala 27:72] wire _T_4950 = _T_4949 | _T_4823; // @[Mux.scala 27:72] - wire _T_4696 = ifu_ic_rw_int_addr_ff == 7'h19; // @[ifu_mem_ctl.scala 658:80] + wire _T_4696 = ifu_ic_rw_int_addr_ff == 7'h19; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_25; // @[Reg.scala 27:20] wire _T_4824 = _T_4696 & way_status_out_25; // @[Mux.scala 27:72] wire _T_4951 = _T_4950 | _T_4824; // @[Mux.scala 27:72] - wire _T_4697 = ifu_ic_rw_int_addr_ff == 7'h1a; // @[ifu_mem_ctl.scala 658:80] + wire _T_4697 = ifu_ic_rw_int_addr_ff == 7'h1a; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_26; // @[Reg.scala 27:20] wire _T_4825 = _T_4697 & way_status_out_26; // @[Mux.scala 27:72] wire _T_4952 = _T_4951 | _T_4825; // @[Mux.scala 27:72] - wire _T_4698 = ifu_ic_rw_int_addr_ff == 7'h1b; // @[ifu_mem_ctl.scala 658:80] + wire _T_4698 = ifu_ic_rw_int_addr_ff == 7'h1b; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_27; // @[Reg.scala 27:20] wire _T_4826 = _T_4698 & way_status_out_27; // @[Mux.scala 27:72] wire _T_4953 = _T_4952 | _T_4826; // @[Mux.scala 27:72] - wire _T_4699 = ifu_ic_rw_int_addr_ff == 7'h1c; // @[ifu_mem_ctl.scala 658:80] + wire _T_4699 = ifu_ic_rw_int_addr_ff == 7'h1c; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_28; // @[Reg.scala 27:20] wire _T_4827 = _T_4699 & way_status_out_28; // @[Mux.scala 27:72] wire _T_4954 = _T_4953 | _T_4827; // @[Mux.scala 27:72] - wire _T_4700 = ifu_ic_rw_int_addr_ff == 7'h1d; // @[ifu_mem_ctl.scala 658:80] + wire _T_4700 = ifu_ic_rw_int_addr_ff == 7'h1d; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_29; // @[Reg.scala 27:20] wire _T_4828 = _T_4700 & way_status_out_29; // @[Mux.scala 27:72] wire _T_4955 = _T_4954 | _T_4828; // @[Mux.scala 27:72] - wire _T_4701 = ifu_ic_rw_int_addr_ff == 7'h1e; // @[ifu_mem_ctl.scala 658:80] + wire _T_4701 = ifu_ic_rw_int_addr_ff == 7'h1e; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_30; // @[Reg.scala 27:20] wire _T_4829 = _T_4701 & way_status_out_30; // @[Mux.scala 27:72] wire _T_4956 = _T_4955 | _T_4829; // @[Mux.scala 27:72] - wire _T_4702 = ifu_ic_rw_int_addr_ff == 7'h1f; // @[ifu_mem_ctl.scala 658:80] + wire _T_4702 = ifu_ic_rw_int_addr_ff == 7'h1f; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_31; // @[Reg.scala 27:20] wire _T_4830 = _T_4702 & way_status_out_31; // @[Mux.scala 27:72] wire _T_4957 = _T_4956 | _T_4830; // @[Mux.scala 27:72] - wire _T_4703 = ifu_ic_rw_int_addr_ff == 7'h20; // @[ifu_mem_ctl.scala 658:80] + wire _T_4703 = ifu_ic_rw_int_addr_ff == 7'h20; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_32; // @[Reg.scala 27:20] wire _T_4831 = _T_4703 & way_status_out_32; // @[Mux.scala 27:72] wire _T_4958 = _T_4957 | _T_4831; // @[Mux.scala 27:72] - wire _T_4704 = ifu_ic_rw_int_addr_ff == 7'h21; // @[ifu_mem_ctl.scala 658:80] + wire _T_4704 = ifu_ic_rw_int_addr_ff == 7'h21; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_33; // @[Reg.scala 27:20] wire _T_4832 = _T_4704 & way_status_out_33; // @[Mux.scala 27:72] wire _T_4959 = _T_4958 | _T_4832; // @[Mux.scala 27:72] - wire _T_4705 = ifu_ic_rw_int_addr_ff == 7'h22; // @[ifu_mem_ctl.scala 658:80] + wire _T_4705 = ifu_ic_rw_int_addr_ff == 7'h22; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_34; // @[Reg.scala 27:20] wire _T_4833 = _T_4705 & way_status_out_34; // @[Mux.scala 27:72] wire _T_4960 = _T_4959 | _T_4833; // @[Mux.scala 27:72] - wire _T_4706 = ifu_ic_rw_int_addr_ff == 7'h23; // @[ifu_mem_ctl.scala 658:80] + wire _T_4706 = ifu_ic_rw_int_addr_ff == 7'h23; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_35; // @[Reg.scala 27:20] wire _T_4834 = _T_4706 & way_status_out_35; // @[Mux.scala 27:72] wire _T_4961 = _T_4960 | _T_4834; // @[Mux.scala 27:72] - wire _T_4707 = ifu_ic_rw_int_addr_ff == 7'h24; // @[ifu_mem_ctl.scala 658:80] + wire _T_4707 = ifu_ic_rw_int_addr_ff == 7'h24; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_36; // @[Reg.scala 27:20] wire _T_4835 = _T_4707 & way_status_out_36; // @[Mux.scala 27:72] wire _T_4962 = _T_4961 | _T_4835; // @[Mux.scala 27:72] - wire _T_4708 = ifu_ic_rw_int_addr_ff == 7'h25; // @[ifu_mem_ctl.scala 658:80] + wire _T_4708 = ifu_ic_rw_int_addr_ff == 7'h25; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_37; // @[Reg.scala 27:20] wire _T_4836 = _T_4708 & way_status_out_37; // @[Mux.scala 27:72] wire _T_4963 = _T_4962 | _T_4836; // @[Mux.scala 27:72] - wire _T_4709 = ifu_ic_rw_int_addr_ff == 7'h26; // @[ifu_mem_ctl.scala 658:80] + wire _T_4709 = ifu_ic_rw_int_addr_ff == 7'h26; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_38; // @[Reg.scala 27:20] wire _T_4837 = _T_4709 & way_status_out_38; // @[Mux.scala 27:72] wire _T_4964 = _T_4963 | _T_4837; // @[Mux.scala 27:72] - wire _T_4710 = ifu_ic_rw_int_addr_ff == 7'h27; // @[ifu_mem_ctl.scala 658:80] + wire _T_4710 = ifu_ic_rw_int_addr_ff == 7'h27; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_39; // @[Reg.scala 27:20] wire _T_4838 = _T_4710 & way_status_out_39; // @[Mux.scala 27:72] wire _T_4965 = _T_4964 | _T_4838; // @[Mux.scala 27:72] - wire _T_4711 = ifu_ic_rw_int_addr_ff == 7'h28; // @[ifu_mem_ctl.scala 658:80] + wire _T_4711 = ifu_ic_rw_int_addr_ff == 7'h28; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_40; // @[Reg.scala 27:20] wire _T_4839 = _T_4711 & way_status_out_40; // @[Mux.scala 27:72] wire _T_4966 = _T_4965 | _T_4839; // @[Mux.scala 27:72] - wire _T_4712 = ifu_ic_rw_int_addr_ff == 7'h29; // @[ifu_mem_ctl.scala 658:80] + wire _T_4712 = ifu_ic_rw_int_addr_ff == 7'h29; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_41; // @[Reg.scala 27:20] wire _T_4840 = _T_4712 & way_status_out_41; // @[Mux.scala 27:72] wire _T_4967 = _T_4966 | _T_4840; // @[Mux.scala 27:72] - wire _T_4713 = ifu_ic_rw_int_addr_ff == 7'h2a; // @[ifu_mem_ctl.scala 658:80] + wire _T_4713 = ifu_ic_rw_int_addr_ff == 7'h2a; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_42; // @[Reg.scala 27:20] wire _T_4841 = _T_4713 & way_status_out_42; // @[Mux.scala 27:72] wire _T_4968 = _T_4967 | _T_4841; // @[Mux.scala 27:72] - wire _T_4714 = ifu_ic_rw_int_addr_ff == 7'h2b; // @[ifu_mem_ctl.scala 658:80] + wire _T_4714 = ifu_ic_rw_int_addr_ff == 7'h2b; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_43; // @[Reg.scala 27:20] wire _T_4842 = _T_4714 & way_status_out_43; // @[Mux.scala 27:72] wire _T_4969 = _T_4968 | _T_4842; // @[Mux.scala 27:72] - wire _T_4715 = ifu_ic_rw_int_addr_ff == 7'h2c; // @[ifu_mem_ctl.scala 658:80] + wire _T_4715 = ifu_ic_rw_int_addr_ff == 7'h2c; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_44; // @[Reg.scala 27:20] wire _T_4843 = _T_4715 & way_status_out_44; // @[Mux.scala 27:72] wire _T_4970 = _T_4969 | _T_4843; // @[Mux.scala 27:72] - wire _T_4716 = ifu_ic_rw_int_addr_ff == 7'h2d; // @[ifu_mem_ctl.scala 658:80] + wire _T_4716 = ifu_ic_rw_int_addr_ff == 7'h2d; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_45; // @[Reg.scala 27:20] wire _T_4844 = _T_4716 & way_status_out_45; // @[Mux.scala 27:72] wire _T_4971 = _T_4970 | _T_4844; // @[Mux.scala 27:72] - wire _T_4717 = ifu_ic_rw_int_addr_ff == 7'h2e; // @[ifu_mem_ctl.scala 658:80] + wire _T_4717 = ifu_ic_rw_int_addr_ff == 7'h2e; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_46; // @[Reg.scala 27:20] wire _T_4845 = _T_4717 & way_status_out_46; // @[Mux.scala 27:72] wire _T_4972 = _T_4971 | _T_4845; // @[Mux.scala 27:72] - wire _T_4718 = ifu_ic_rw_int_addr_ff == 7'h2f; // @[ifu_mem_ctl.scala 658:80] + wire _T_4718 = ifu_ic_rw_int_addr_ff == 7'h2f; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_47; // @[Reg.scala 27:20] wire _T_4846 = _T_4718 & way_status_out_47; // @[Mux.scala 27:72] wire _T_4973 = _T_4972 | _T_4846; // @[Mux.scala 27:72] - wire _T_4719 = ifu_ic_rw_int_addr_ff == 7'h30; // @[ifu_mem_ctl.scala 658:80] + wire _T_4719 = ifu_ic_rw_int_addr_ff == 7'h30; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_48; // @[Reg.scala 27:20] wire _T_4847 = _T_4719 & way_status_out_48; // @[Mux.scala 27:72] wire _T_4974 = _T_4973 | _T_4847; // @[Mux.scala 27:72] - wire _T_4720 = ifu_ic_rw_int_addr_ff == 7'h31; // @[ifu_mem_ctl.scala 658:80] + wire _T_4720 = ifu_ic_rw_int_addr_ff == 7'h31; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_49; // @[Reg.scala 27:20] wire _T_4848 = _T_4720 & way_status_out_49; // @[Mux.scala 27:72] wire _T_4975 = _T_4974 | _T_4848; // @[Mux.scala 27:72] - wire _T_4721 = ifu_ic_rw_int_addr_ff == 7'h32; // @[ifu_mem_ctl.scala 658:80] + wire _T_4721 = ifu_ic_rw_int_addr_ff == 7'h32; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_50; // @[Reg.scala 27:20] wire _T_4849 = _T_4721 & way_status_out_50; // @[Mux.scala 27:72] wire _T_4976 = _T_4975 | _T_4849; // @[Mux.scala 27:72] - wire _T_4722 = ifu_ic_rw_int_addr_ff == 7'h33; // @[ifu_mem_ctl.scala 658:80] + wire _T_4722 = ifu_ic_rw_int_addr_ff == 7'h33; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_51; // @[Reg.scala 27:20] wire _T_4850 = _T_4722 & way_status_out_51; // @[Mux.scala 27:72] wire _T_4977 = _T_4976 | _T_4850; // @[Mux.scala 27:72] - wire _T_4723 = ifu_ic_rw_int_addr_ff == 7'h34; // @[ifu_mem_ctl.scala 658:80] + wire _T_4723 = ifu_ic_rw_int_addr_ff == 7'h34; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_52; // @[Reg.scala 27:20] wire _T_4851 = _T_4723 & way_status_out_52; // @[Mux.scala 27:72] wire _T_4978 = _T_4977 | _T_4851; // @[Mux.scala 27:72] - wire _T_4724 = ifu_ic_rw_int_addr_ff == 7'h35; // @[ifu_mem_ctl.scala 658:80] + wire _T_4724 = ifu_ic_rw_int_addr_ff == 7'h35; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_53; // @[Reg.scala 27:20] wire _T_4852 = _T_4724 & way_status_out_53; // @[Mux.scala 27:72] wire _T_4979 = _T_4978 | _T_4852; // @[Mux.scala 27:72] - wire _T_4725 = ifu_ic_rw_int_addr_ff == 7'h36; // @[ifu_mem_ctl.scala 658:80] + wire _T_4725 = ifu_ic_rw_int_addr_ff == 7'h36; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_54; // @[Reg.scala 27:20] wire _T_4853 = _T_4725 & way_status_out_54; // @[Mux.scala 27:72] wire _T_4980 = _T_4979 | _T_4853; // @[Mux.scala 27:72] - wire _T_4726 = ifu_ic_rw_int_addr_ff == 7'h37; // @[ifu_mem_ctl.scala 658:80] + wire _T_4726 = ifu_ic_rw_int_addr_ff == 7'h37; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_55; // @[Reg.scala 27:20] wire _T_4854 = _T_4726 & way_status_out_55; // @[Mux.scala 27:72] wire _T_4981 = _T_4980 | _T_4854; // @[Mux.scala 27:72] - wire _T_4727 = ifu_ic_rw_int_addr_ff == 7'h38; // @[ifu_mem_ctl.scala 658:80] + wire _T_4727 = ifu_ic_rw_int_addr_ff == 7'h38; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_56; // @[Reg.scala 27:20] wire _T_4855 = _T_4727 & way_status_out_56; // @[Mux.scala 27:72] wire _T_4982 = _T_4981 | _T_4855; // @[Mux.scala 27:72] - wire _T_4728 = ifu_ic_rw_int_addr_ff == 7'h39; // @[ifu_mem_ctl.scala 658:80] + wire _T_4728 = ifu_ic_rw_int_addr_ff == 7'h39; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_57; // @[Reg.scala 27:20] wire _T_4856 = _T_4728 & way_status_out_57; // @[Mux.scala 27:72] wire _T_4983 = _T_4982 | _T_4856; // @[Mux.scala 27:72] - wire _T_4729 = ifu_ic_rw_int_addr_ff == 7'h3a; // @[ifu_mem_ctl.scala 658:80] + wire _T_4729 = ifu_ic_rw_int_addr_ff == 7'h3a; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_58; // @[Reg.scala 27:20] wire _T_4857 = _T_4729 & way_status_out_58; // @[Mux.scala 27:72] wire _T_4984 = _T_4983 | _T_4857; // @[Mux.scala 27:72] - wire _T_4730 = ifu_ic_rw_int_addr_ff == 7'h3b; // @[ifu_mem_ctl.scala 658:80] + wire _T_4730 = ifu_ic_rw_int_addr_ff == 7'h3b; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_59; // @[Reg.scala 27:20] wire _T_4858 = _T_4730 & way_status_out_59; // @[Mux.scala 27:72] wire _T_4985 = _T_4984 | _T_4858; // @[Mux.scala 27:72] - wire _T_4731 = ifu_ic_rw_int_addr_ff == 7'h3c; // @[ifu_mem_ctl.scala 658:80] + wire _T_4731 = ifu_ic_rw_int_addr_ff == 7'h3c; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_60; // @[Reg.scala 27:20] wire _T_4859 = _T_4731 & way_status_out_60; // @[Mux.scala 27:72] wire _T_4986 = _T_4985 | _T_4859; // @[Mux.scala 27:72] - wire _T_4732 = ifu_ic_rw_int_addr_ff == 7'h3d; // @[ifu_mem_ctl.scala 658:80] + wire _T_4732 = ifu_ic_rw_int_addr_ff == 7'h3d; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_61; // @[Reg.scala 27:20] wire _T_4860 = _T_4732 & way_status_out_61; // @[Mux.scala 27:72] wire _T_4987 = _T_4986 | _T_4860; // @[Mux.scala 27:72] - wire _T_4733 = ifu_ic_rw_int_addr_ff == 7'h3e; // @[ifu_mem_ctl.scala 658:80] + wire _T_4733 = ifu_ic_rw_int_addr_ff == 7'h3e; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_62; // @[Reg.scala 27:20] wire _T_4861 = _T_4733 & way_status_out_62; // @[Mux.scala 27:72] wire _T_4988 = _T_4987 | _T_4861; // @[Mux.scala 27:72] - wire _T_4734 = ifu_ic_rw_int_addr_ff == 7'h3f; // @[ifu_mem_ctl.scala 658:80] + wire _T_4734 = ifu_ic_rw_int_addr_ff == 7'h3f; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_63; // @[Reg.scala 27:20] wire _T_4862 = _T_4734 & way_status_out_63; // @[Mux.scala 27:72] wire _T_4989 = _T_4988 | _T_4862; // @[Mux.scala 27:72] - wire _T_4735 = ifu_ic_rw_int_addr_ff == 7'h40; // @[ifu_mem_ctl.scala 658:80] + wire _T_4735 = ifu_ic_rw_int_addr_ff == 7'h40; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_64; // @[Reg.scala 27:20] wire _T_4863 = _T_4735 & way_status_out_64; // @[Mux.scala 27:72] wire _T_4990 = _T_4989 | _T_4863; // @[Mux.scala 27:72] - wire _T_4736 = ifu_ic_rw_int_addr_ff == 7'h41; // @[ifu_mem_ctl.scala 658:80] + wire _T_4736 = ifu_ic_rw_int_addr_ff == 7'h41; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_65; // @[Reg.scala 27:20] wire _T_4864 = _T_4736 & way_status_out_65; // @[Mux.scala 27:72] wire _T_4991 = _T_4990 | _T_4864; // @[Mux.scala 27:72] - wire _T_4737 = ifu_ic_rw_int_addr_ff == 7'h42; // @[ifu_mem_ctl.scala 658:80] + wire _T_4737 = ifu_ic_rw_int_addr_ff == 7'h42; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_66; // @[Reg.scala 27:20] wire _T_4865 = _T_4737 & way_status_out_66; // @[Mux.scala 27:72] wire _T_4992 = _T_4991 | _T_4865; // @[Mux.scala 27:72] - wire _T_4738 = ifu_ic_rw_int_addr_ff == 7'h43; // @[ifu_mem_ctl.scala 658:80] + wire _T_4738 = ifu_ic_rw_int_addr_ff == 7'h43; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_67; // @[Reg.scala 27:20] wire _T_4866 = _T_4738 & way_status_out_67; // @[Mux.scala 27:72] wire _T_4993 = _T_4992 | _T_4866; // @[Mux.scala 27:72] - wire _T_4739 = ifu_ic_rw_int_addr_ff == 7'h44; // @[ifu_mem_ctl.scala 658:80] + wire _T_4739 = ifu_ic_rw_int_addr_ff == 7'h44; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_68; // @[Reg.scala 27:20] wire _T_4867 = _T_4739 & way_status_out_68; // @[Mux.scala 27:72] wire _T_4994 = _T_4993 | _T_4867; // @[Mux.scala 27:72] - wire _T_4740 = ifu_ic_rw_int_addr_ff == 7'h45; // @[ifu_mem_ctl.scala 658:80] + wire _T_4740 = ifu_ic_rw_int_addr_ff == 7'h45; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_69; // @[Reg.scala 27:20] wire _T_4868 = _T_4740 & way_status_out_69; // @[Mux.scala 27:72] wire _T_4995 = _T_4994 | _T_4868; // @[Mux.scala 27:72] - wire _T_4741 = ifu_ic_rw_int_addr_ff == 7'h46; // @[ifu_mem_ctl.scala 658:80] + wire _T_4741 = ifu_ic_rw_int_addr_ff == 7'h46; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_70; // @[Reg.scala 27:20] wire _T_4869 = _T_4741 & way_status_out_70; // @[Mux.scala 27:72] wire _T_4996 = _T_4995 | _T_4869; // @[Mux.scala 27:72] - wire _T_4742 = ifu_ic_rw_int_addr_ff == 7'h47; // @[ifu_mem_ctl.scala 658:80] + wire _T_4742 = ifu_ic_rw_int_addr_ff == 7'h47; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_71; // @[Reg.scala 27:20] wire _T_4870 = _T_4742 & way_status_out_71; // @[Mux.scala 27:72] wire _T_4997 = _T_4996 | _T_4870; // @[Mux.scala 27:72] - wire _T_4743 = ifu_ic_rw_int_addr_ff == 7'h48; // @[ifu_mem_ctl.scala 658:80] + wire _T_4743 = ifu_ic_rw_int_addr_ff == 7'h48; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_72; // @[Reg.scala 27:20] wire _T_4871 = _T_4743 & way_status_out_72; // @[Mux.scala 27:72] wire _T_4998 = _T_4997 | _T_4871; // @[Mux.scala 27:72] - wire _T_4744 = ifu_ic_rw_int_addr_ff == 7'h49; // @[ifu_mem_ctl.scala 658:80] + wire _T_4744 = ifu_ic_rw_int_addr_ff == 7'h49; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_73; // @[Reg.scala 27:20] wire _T_4872 = _T_4744 & way_status_out_73; // @[Mux.scala 27:72] wire _T_4999 = _T_4998 | _T_4872; // @[Mux.scala 27:72] - wire _T_4745 = ifu_ic_rw_int_addr_ff == 7'h4a; // @[ifu_mem_ctl.scala 658:80] + wire _T_4745 = ifu_ic_rw_int_addr_ff == 7'h4a; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_74; // @[Reg.scala 27:20] wire _T_4873 = _T_4745 & way_status_out_74; // @[Mux.scala 27:72] wire _T_5000 = _T_4999 | _T_4873; // @[Mux.scala 27:72] - wire _T_4746 = ifu_ic_rw_int_addr_ff == 7'h4b; // @[ifu_mem_ctl.scala 658:80] + wire _T_4746 = ifu_ic_rw_int_addr_ff == 7'h4b; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_75; // @[Reg.scala 27:20] wire _T_4874 = _T_4746 & way_status_out_75; // @[Mux.scala 27:72] wire _T_5001 = _T_5000 | _T_4874; // @[Mux.scala 27:72] - wire _T_4747 = ifu_ic_rw_int_addr_ff == 7'h4c; // @[ifu_mem_ctl.scala 658:80] + wire _T_4747 = ifu_ic_rw_int_addr_ff == 7'h4c; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_76; // @[Reg.scala 27:20] wire _T_4875 = _T_4747 & way_status_out_76; // @[Mux.scala 27:72] wire _T_5002 = _T_5001 | _T_4875; // @[Mux.scala 27:72] - wire _T_4748 = ifu_ic_rw_int_addr_ff == 7'h4d; // @[ifu_mem_ctl.scala 658:80] + wire _T_4748 = ifu_ic_rw_int_addr_ff == 7'h4d; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_77; // @[Reg.scala 27:20] wire _T_4876 = _T_4748 & way_status_out_77; // @[Mux.scala 27:72] wire _T_5003 = _T_5002 | _T_4876; // @[Mux.scala 27:72] - wire _T_4749 = ifu_ic_rw_int_addr_ff == 7'h4e; // @[ifu_mem_ctl.scala 658:80] + wire _T_4749 = ifu_ic_rw_int_addr_ff == 7'h4e; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_78; // @[Reg.scala 27:20] wire _T_4877 = _T_4749 & way_status_out_78; // @[Mux.scala 27:72] wire _T_5004 = _T_5003 | _T_4877; // @[Mux.scala 27:72] - wire _T_4750 = ifu_ic_rw_int_addr_ff == 7'h4f; // @[ifu_mem_ctl.scala 658:80] + wire _T_4750 = ifu_ic_rw_int_addr_ff == 7'h4f; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_79; // @[Reg.scala 27:20] wire _T_4878 = _T_4750 & way_status_out_79; // @[Mux.scala 27:72] wire _T_5005 = _T_5004 | _T_4878; // @[Mux.scala 27:72] - wire _T_4751 = ifu_ic_rw_int_addr_ff == 7'h50; // @[ifu_mem_ctl.scala 658:80] + wire _T_4751 = ifu_ic_rw_int_addr_ff == 7'h50; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_80; // @[Reg.scala 27:20] wire _T_4879 = _T_4751 & way_status_out_80; // @[Mux.scala 27:72] wire _T_5006 = _T_5005 | _T_4879; // @[Mux.scala 27:72] - wire _T_4752 = ifu_ic_rw_int_addr_ff == 7'h51; // @[ifu_mem_ctl.scala 658:80] + wire _T_4752 = ifu_ic_rw_int_addr_ff == 7'h51; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_81; // @[Reg.scala 27:20] wire _T_4880 = _T_4752 & way_status_out_81; // @[Mux.scala 27:72] wire _T_5007 = _T_5006 | _T_4880; // @[Mux.scala 27:72] - wire _T_4753 = ifu_ic_rw_int_addr_ff == 7'h52; // @[ifu_mem_ctl.scala 658:80] + wire _T_4753 = ifu_ic_rw_int_addr_ff == 7'h52; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_82; // @[Reg.scala 27:20] wire _T_4881 = _T_4753 & way_status_out_82; // @[Mux.scala 27:72] wire _T_5008 = _T_5007 | _T_4881; // @[Mux.scala 27:72] - wire _T_4754 = ifu_ic_rw_int_addr_ff == 7'h53; // @[ifu_mem_ctl.scala 658:80] + wire _T_4754 = ifu_ic_rw_int_addr_ff == 7'h53; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_83; // @[Reg.scala 27:20] wire _T_4882 = _T_4754 & way_status_out_83; // @[Mux.scala 27:72] wire _T_5009 = _T_5008 | _T_4882; // @[Mux.scala 27:72] - wire _T_4755 = ifu_ic_rw_int_addr_ff == 7'h54; // @[ifu_mem_ctl.scala 658:80] + wire _T_4755 = ifu_ic_rw_int_addr_ff == 7'h54; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_84; // @[Reg.scala 27:20] wire _T_4883 = _T_4755 & way_status_out_84; // @[Mux.scala 27:72] wire _T_5010 = _T_5009 | _T_4883; // @[Mux.scala 27:72] - wire _T_4756 = ifu_ic_rw_int_addr_ff == 7'h55; // @[ifu_mem_ctl.scala 658:80] + wire _T_4756 = ifu_ic_rw_int_addr_ff == 7'h55; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_85; // @[Reg.scala 27:20] wire _T_4884 = _T_4756 & way_status_out_85; // @[Mux.scala 27:72] wire _T_5011 = _T_5010 | _T_4884; // @[Mux.scala 27:72] - wire _T_4757 = ifu_ic_rw_int_addr_ff == 7'h56; // @[ifu_mem_ctl.scala 658:80] + wire _T_4757 = ifu_ic_rw_int_addr_ff == 7'h56; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_86; // @[Reg.scala 27:20] wire _T_4885 = _T_4757 & way_status_out_86; // @[Mux.scala 27:72] wire _T_5012 = _T_5011 | _T_4885; // @[Mux.scala 27:72] - wire _T_4758 = ifu_ic_rw_int_addr_ff == 7'h57; // @[ifu_mem_ctl.scala 658:80] + wire _T_4758 = ifu_ic_rw_int_addr_ff == 7'h57; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_87; // @[Reg.scala 27:20] wire _T_4886 = _T_4758 & way_status_out_87; // @[Mux.scala 27:72] wire _T_5013 = _T_5012 | _T_4886; // @[Mux.scala 27:72] - wire _T_4759 = ifu_ic_rw_int_addr_ff == 7'h58; // @[ifu_mem_ctl.scala 658:80] + wire _T_4759 = ifu_ic_rw_int_addr_ff == 7'h58; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_88; // @[Reg.scala 27:20] wire _T_4887 = _T_4759 & way_status_out_88; // @[Mux.scala 27:72] wire _T_5014 = _T_5013 | _T_4887; // @[Mux.scala 27:72] - wire _T_4760 = ifu_ic_rw_int_addr_ff == 7'h59; // @[ifu_mem_ctl.scala 658:80] + wire _T_4760 = ifu_ic_rw_int_addr_ff == 7'h59; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_89; // @[Reg.scala 27:20] wire _T_4888 = _T_4760 & way_status_out_89; // @[Mux.scala 27:72] wire _T_5015 = _T_5014 | _T_4888; // @[Mux.scala 27:72] - wire _T_4761 = ifu_ic_rw_int_addr_ff == 7'h5a; // @[ifu_mem_ctl.scala 658:80] + wire _T_4761 = ifu_ic_rw_int_addr_ff == 7'h5a; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_90; // @[Reg.scala 27:20] wire _T_4889 = _T_4761 & way_status_out_90; // @[Mux.scala 27:72] wire _T_5016 = _T_5015 | _T_4889; // @[Mux.scala 27:72] - wire _T_4762 = ifu_ic_rw_int_addr_ff == 7'h5b; // @[ifu_mem_ctl.scala 658:80] + wire _T_4762 = ifu_ic_rw_int_addr_ff == 7'h5b; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_91; // @[Reg.scala 27:20] wire _T_4890 = _T_4762 & way_status_out_91; // @[Mux.scala 27:72] wire _T_5017 = _T_5016 | _T_4890; // @[Mux.scala 27:72] - wire _T_4763 = ifu_ic_rw_int_addr_ff == 7'h5c; // @[ifu_mem_ctl.scala 658:80] + wire _T_4763 = ifu_ic_rw_int_addr_ff == 7'h5c; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_92; // @[Reg.scala 27:20] wire _T_4891 = _T_4763 & way_status_out_92; // @[Mux.scala 27:72] wire _T_5018 = _T_5017 | _T_4891; // @[Mux.scala 27:72] - wire _T_4764 = ifu_ic_rw_int_addr_ff == 7'h5d; // @[ifu_mem_ctl.scala 658:80] + wire _T_4764 = ifu_ic_rw_int_addr_ff == 7'h5d; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_93; // @[Reg.scala 27:20] wire _T_4892 = _T_4764 & way_status_out_93; // @[Mux.scala 27:72] wire _T_5019 = _T_5018 | _T_4892; // @[Mux.scala 27:72] - wire _T_4765 = ifu_ic_rw_int_addr_ff == 7'h5e; // @[ifu_mem_ctl.scala 658:80] + wire _T_4765 = ifu_ic_rw_int_addr_ff == 7'h5e; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_94; // @[Reg.scala 27:20] wire _T_4893 = _T_4765 & way_status_out_94; // @[Mux.scala 27:72] wire _T_5020 = _T_5019 | _T_4893; // @[Mux.scala 27:72] - wire _T_4766 = ifu_ic_rw_int_addr_ff == 7'h5f; // @[ifu_mem_ctl.scala 658:80] + wire _T_4766 = ifu_ic_rw_int_addr_ff == 7'h5f; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_95; // @[Reg.scala 27:20] wire _T_4894 = _T_4766 & way_status_out_95; // @[Mux.scala 27:72] wire _T_5021 = _T_5020 | _T_4894; // @[Mux.scala 27:72] - wire _T_4767 = ifu_ic_rw_int_addr_ff == 7'h60; // @[ifu_mem_ctl.scala 658:80] + wire _T_4767 = ifu_ic_rw_int_addr_ff == 7'h60; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_96; // @[Reg.scala 27:20] wire _T_4895 = _T_4767 & way_status_out_96; // @[Mux.scala 27:72] wire _T_5022 = _T_5021 | _T_4895; // @[Mux.scala 27:72] - wire _T_4768 = ifu_ic_rw_int_addr_ff == 7'h61; // @[ifu_mem_ctl.scala 658:80] + wire _T_4768 = ifu_ic_rw_int_addr_ff == 7'h61; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_97; // @[Reg.scala 27:20] wire _T_4896 = _T_4768 & way_status_out_97; // @[Mux.scala 27:72] wire _T_5023 = _T_5022 | _T_4896; // @[Mux.scala 27:72] - wire _T_4769 = ifu_ic_rw_int_addr_ff == 7'h62; // @[ifu_mem_ctl.scala 658:80] + wire _T_4769 = ifu_ic_rw_int_addr_ff == 7'h62; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_98; // @[Reg.scala 27:20] wire _T_4897 = _T_4769 & way_status_out_98; // @[Mux.scala 27:72] wire _T_5024 = _T_5023 | _T_4897; // @[Mux.scala 27:72] - wire _T_4770 = ifu_ic_rw_int_addr_ff == 7'h63; // @[ifu_mem_ctl.scala 658:80] + wire _T_4770 = ifu_ic_rw_int_addr_ff == 7'h63; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_99; // @[Reg.scala 27:20] wire _T_4898 = _T_4770 & way_status_out_99; // @[Mux.scala 27:72] wire _T_5025 = _T_5024 | _T_4898; // @[Mux.scala 27:72] - wire _T_4771 = ifu_ic_rw_int_addr_ff == 7'h64; // @[ifu_mem_ctl.scala 658:80] + wire _T_4771 = ifu_ic_rw_int_addr_ff == 7'h64; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_100; // @[Reg.scala 27:20] wire _T_4899 = _T_4771 & way_status_out_100; // @[Mux.scala 27:72] wire _T_5026 = _T_5025 | _T_4899; // @[Mux.scala 27:72] - wire _T_4772 = ifu_ic_rw_int_addr_ff == 7'h65; // @[ifu_mem_ctl.scala 658:80] + wire _T_4772 = ifu_ic_rw_int_addr_ff == 7'h65; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_101; // @[Reg.scala 27:20] wire _T_4900 = _T_4772 & way_status_out_101; // @[Mux.scala 27:72] wire _T_5027 = _T_5026 | _T_4900; // @[Mux.scala 27:72] - wire _T_4773 = ifu_ic_rw_int_addr_ff == 7'h66; // @[ifu_mem_ctl.scala 658:80] + wire _T_4773 = ifu_ic_rw_int_addr_ff == 7'h66; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_102; // @[Reg.scala 27:20] wire _T_4901 = _T_4773 & way_status_out_102; // @[Mux.scala 27:72] wire _T_5028 = _T_5027 | _T_4901; // @[Mux.scala 27:72] - wire _T_4774 = ifu_ic_rw_int_addr_ff == 7'h67; // @[ifu_mem_ctl.scala 658:80] + wire _T_4774 = ifu_ic_rw_int_addr_ff == 7'h67; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_103; // @[Reg.scala 27:20] wire _T_4902 = _T_4774 & way_status_out_103; // @[Mux.scala 27:72] wire _T_5029 = _T_5028 | _T_4902; // @[Mux.scala 27:72] - wire _T_4775 = ifu_ic_rw_int_addr_ff == 7'h68; // @[ifu_mem_ctl.scala 658:80] + wire _T_4775 = ifu_ic_rw_int_addr_ff == 7'h68; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_104; // @[Reg.scala 27:20] wire _T_4903 = _T_4775 & way_status_out_104; // @[Mux.scala 27:72] wire _T_5030 = _T_5029 | _T_4903; // @[Mux.scala 27:72] - wire _T_4776 = ifu_ic_rw_int_addr_ff == 7'h69; // @[ifu_mem_ctl.scala 658:80] + wire _T_4776 = ifu_ic_rw_int_addr_ff == 7'h69; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_105; // @[Reg.scala 27:20] wire _T_4904 = _T_4776 & way_status_out_105; // @[Mux.scala 27:72] wire _T_5031 = _T_5030 | _T_4904; // @[Mux.scala 27:72] - wire _T_4777 = ifu_ic_rw_int_addr_ff == 7'h6a; // @[ifu_mem_ctl.scala 658:80] + wire _T_4777 = ifu_ic_rw_int_addr_ff == 7'h6a; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_106; // @[Reg.scala 27:20] wire _T_4905 = _T_4777 & way_status_out_106; // @[Mux.scala 27:72] wire _T_5032 = _T_5031 | _T_4905; // @[Mux.scala 27:72] - wire _T_4778 = ifu_ic_rw_int_addr_ff == 7'h6b; // @[ifu_mem_ctl.scala 658:80] + wire _T_4778 = ifu_ic_rw_int_addr_ff == 7'h6b; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_107; // @[Reg.scala 27:20] wire _T_4906 = _T_4778 & way_status_out_107; // @[Mux.scala 27:72] wire _T_5033 = _T_5032 | _T_4906; // @[Mux.scala 27:72] - wire _T_4779 = ifu_ic_rw_int_addr_ff == 7'h6c; // @[ifu_mem_ctl.scala 658:80] + wire _T_4779 = ifu_ic_rw_int_addr_ff == 7'h6c; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_108; // @[Reg.scala 27:20] wire _T_4907 = _T_4779 & way_status_out_108; // @[Mux.scala 27:72] wire _T_5034 = _T_5033 | _T_4907; // @[Mux.scala 27:72] - wire _T_4780 = ifu_ic_rw_int_addr_ff == 7'h6d; // @[ifu_mem_ctl.scala 658:80] + wire _T_4780 = ifu_ic_rw_int_addr_ff == 7'h6d; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_109; // @[Reg.scala 27:20] wire _T_4908 = _T_4780 & way_status_out_109; // @[Mux.scala 27:72] wire _T_5035 = _T_5034 | _T_4908; // @[Mux.scala 27:72] - wire _T_4781 = ifu_ic_rw_int_addr_ff == 7'h6e; // @[ifu_mem_ctl.scala 658:80] + wire _T_4781 = ifu_ic_rw_int_addr_ff == 7'h6e; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_110; // @[Reg.scala 27:20] wire _T_4909 = _T_4781 & way_status_out_110; // @[Mux.scala 27:72] wire _T_5036 = _T_5035 | _T_4909; // @[Mux.scala 27:72] - wire _T_4782 = ifu_ic_rw_int_addr_ff == 7'h6f; // @[ifu_mem_ctl.scala 658:80] + wire _T_4782 = ifu_ic_rw_int_addr_ff == 7'h6f; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_111; // @[Reg.scala 27:20] wire _T_4910 = _T_4782 & way_status_out_111; // @[Mux.scala 27:72] wire _T_5037 = _T_5036 | _T_4910; // @[Mux.scala 27:72] - wire _T_4783 = ifu_ic_rw_int_addr_ff == 7'h70; // @[ifu_mem_ctl.scala 658:80] + wire _T_4783 = ifu_ic_rw_int_addr_ff == 7'h70; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_112; // @[Reg.scala 27:20] wire _T_4911 = _T_4783 & way_status_out_112; // @[Mux.scala 27:72] wire _T_5038 = _T_5037 | _T_4911; // @[Mux.scala 27:72] - wire _T_4784 = ifu_ic_rw_int_addr_ff == 7'h71; // @[ifu_mem_ctl.scala 658:80] + wire _T_4784 = ifu_ic_rw_int_addr_ff == 7'h71; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_113; // @[Reg.scala 27:20] wire _T_4912 = _T_4784 & way_status_out_113; // @[Mux.scala 27:72] wire _T_5039 = _T_5038 | _T_4912; // @[Mux.scala 27:72] - wire _T_4785 = ifu_ic_rw_int_addr_ff == 7'h72; // @[ifu_mem_ctl.scala 658:80] + wire _T_4785 = ifu_ic_rw_int_addr_ff == 7'h72; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_114; // @[Reg.scala 27:20] wire _T_4913 = _T_4785 & way_status_out_114; // @[Mux.scala 27:72] wire _T_5040 = _T_5039 | _T_4913; // @[Mux.scala 27:72] - wire _T_4786 = ifu_ic_rw_int_addr_ff == 7'h73; // @[ifu_mem_ctl.scala 658:80] + wire _T_4786 = ifu_ic_rw_int_addr_ff == 7'h73; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_115; // @[Reg.scala 27:20] wire _T_4914 = _T_4786 & way_status_out_115; // @[Mux.scala 27:72] wire _T_5041 = _T_5040 | _T_4914; // @[Mux.scala 27:72] - wire _T_4787 = ifu_ic_rw_int_addr_ff == 7'h74; // @[ifu_mem_ctl.scala 658:80] + wire _T_4787 = ifu_ic_rw_int_addr_ff == 7'h74; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_116; // @[Reg.scala 27:20] wire _T_4915 = _T_4787 & way_status_out_116; // @[Mux.scala 27:72] wire _T_5042 = _T_5041 | _T_4915; // @[Mux.scala 27:72] - wire _T_4788 = ifu_ic_rw_int_addr_ff == 7'h75; // @[ifu_mem_ctl.scala 658:80] + wire _T_4788 = ifu_ic_rw_int_addr_ff == 7'h75; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_117; // @[Reg.scala 27:20] wire _T_4916 = _T_4788 & way_status_out_117; // @[Mux.scala 27:72] wire _T_5043 = _T_5042 | _T_4916; // @[Mux.scala 27:72] - wire _T_4789 = ifu_ic_rw_int_addr_ff == 7'h76; // @[ifu_mem_ctl.scala 658:80] + wire _T_4789 = ifu_ic_rw_int_addr_ff == 7'h76; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_118; // @[Reg.scala 27:20] wire _T_4917 = _T_4789 & way_status_out_118; // @[Mux.scala 27:72] wire _T_5044 = _T_5043 | _T_4917; // @[Mux.scala 27:72] - wire _T_4790 = ifu_ic_rw_int_addr_ff == 7'h77; // @[ifu_mem_ctl.scala 658:80] + wire _T_4790 = ifu_ic_rw_int_addr_ff == 7'h77; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_119; // @[Reg.scala 27:20] wire _T_4918 = _T_4790 & way_status_out_119; // @[Mux.scala 27:72] wire _T_5045 = _T_5044 | _T_4918; // @[Mux.scala 27:72] - wire _T_4791 = ifu_ic_rw_int_addr_ff == 7'h78; // @[ifu_mem_ctl.scala 658:80] + wire _T_4791 = ifu_ic_rw_int_addr_ff == 7'h78; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_120; // @[Reg.scala 27:20] wire _T_4919 = _T_4791 & way_status_out_120; // @[Mux.scala 27:72] wire _T_5046 = _T_5045 | _T_4919; // @[Mux.scala 27:72] - wire _T_4792 = ifu_ic_rw_int_addr_ff == 7'h79; // @[ifu_mem_ctl.scala 658:80] + wire _T_4792 = ifu_ic_rw_int_addr_ff == 7'h79; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_121; // @[Reg.scala 27:20] wire _T_4920 = _T_4792 & way_status_out_121; // @[Mux.scala 27:72] wire _T_5047 = _T_5046 | _T_4920; // @[Mux.scala 27:72] - wire _T_4793 = ifu_ic_rw_int_addr_ff == 7'h7a; // @[ifu_mem_ctl.scala 658:80] + wire _T_4793 = ifu_ic_rw_int_addr_ff == 7'h7a; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_122; // @[Reg.scala 27:20] wire _T_4921 = _T_4793 & way_status_out_122; // @[Mux.scala 27:72] wire _T_5048 = _T_5047 | _T_4921; // @[Mux.scala 27:72] - wire _T_4794 = ifu_ic_rw_int_addr_ff == 7'h7b; // @[ifu_mem_ctl.scala 658:80] + wire _T_4794 = ifu_ic_rw_int_addr_ff == 7'h7b; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_123; // @[Reg.scala 27:20] wire _T_4922 = _T_4794 & way_status_out_123; // @[Mux.scala 27:72] wire _T_5049 = _T_5048 | _T_4922; // @[Mux.scala 27:72] - wire _T_4795 = ifu_ic_rw_int_addr_ff == 7'h7c; // @[ifu_mem_ctl.scala 658:80] + wire _T_4795 = ifu_ic_rw_int_addr_ff == 7'h7c; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_124; // @[Reg.scala 27:20] wire _T_4923 = _T_4795 & way_status_out_124; // @[Mux.scala 27:72] wire _T_5050 = _T_5049 | _T_4923; // @[Mux.scala 27:72] - wire _T_4796 = ifu_ic_rw_int_addr_ff == 7'h7d; // @[ifu_mem_ctl.scala 658:80] + wire _T_4796 = ifu_ic_rw_int_addr_ff == 7'h7d; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_125; // @[Reg.scala 27:20] wire _T_4924 = _T_4796 & way_status_out_125; // @[Mux.scala 27:72] wire _T_5051 = _T_5050 | _T_4924; // @[Mux.scala 27:72] - wire _T_4797 = ifu_ic_rw_int_addr_ff == 7'h7e; // @[ifu_mem_ctl.scala 658:80] + wire _T_4797 = ifu_ic_rw_int_addr_ff == 7'h7e; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_126; // @[Reg.scala 27:20] wire _T_4925 = _T_4797 & way_status_out_126; // @[Mux.scala 27:72] wire _T_5052 = _T_5051 | _T_4925; // @[Mux.scala 27:72] - wire _T_4798 = ifu_ic_rw_int_addr_ff == 7'h7f; // @[ifu_mem_ctl.scala 658:80] + wire _T_4798 = ifu_ic_rw_int_addr_ff == 7'h7f; // @[ifu_mem_ctl.scala 666:80] reg way_status_out_127; // @[Reg.scala 27:20] wire _T_4926 = _T_4798 & way_status_out_127; // @[Mux.scala 27:72] wire way_status = _T_5052 | _T_4926; // @[Mux.scala 27:72] - wire _T_195 = ~reset_all_tags; // @[ifu_mem_ctl.scala 185:96] + wire _T_195 = ~reset_all_tags; // @[ifu_mem_ctl.scala 168:96] wire [1:0] _T_197 = _T_195 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_198 = _T_197 & io_ic_tag_valid; // @[ifu_mem_ctl.scala 185:113] - reg [1:0] tagv_mb_scnd_ff; // @[ifu_mem_ctl.scala 191:58] - reg uncacheable_miss_scnd_ff; // @[ifu_mem_ctl.scala 187:67] - reg [30:0] imb_scnd_ff; // @[ifu_mem_ctl.scala 189:54] + wire [1:0] _T_198 = _T_197 & io_ic_tag_valid; // @[ifu_mem_ctl.scala 168:113] + reg [1:0] tagv_mb_scnd_ff; // @[ifu_mem_ctl.scala 174:58] + reg uncacheable_miss_scnd_ff; // @[ifu_mem_ctl.scala 170:67] + reg [30:0] imb_scnd_ff; // @[ifu_mem_ctl.scala 172:54] wire [2:0] _T_206 = bus_ifu_wr_en_ff ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - reg [2:0] ifu_bus_rid_ff; // @[ifu_mem_ctl.scala 508:46] - wire [2:0] ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & _T_206; // @[ifu_mem_ctl.scala 194:45] - wire _T_212 = _T_231 | _T_239; // @[ifu_mem_ctl.scala 199:59] - wire _T_214 = _T_212 | _T_2268; // @[ifu_mem_ctl.scala 199:91] - wire ic_iccm_hit_f = fetch_req_iccm_f & _T_214; // @[ifu_mem_ctl.scala 199:41] - wire _T_219 = _T_227 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 205:39] - wire _T_221 = _T_219 & _T_195; // @[ifu_mem_ctl.scala 205:60] - wire _T_225 = _T_221 & _T_212; // @[ifu_mem_ctl.scala 205:78] - wire ic_act_hit_f = _T_225 & _T_247; // @[ifu_mem_ctl.scala 205:126] - wire _T_262 = ic_act_hit_f | ic_byp_hit_f; // @[ifu_mem_ctl.scala 212:31] - wire _T_263 = _T_262 | ic_iccm_hit_f; // @[ifu_mem_ctl.scala 212:46] - wire _T_264 = ifc_region_acc_fault_final_f & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 212:94] - wire _T_268 = sel_hold_imb ? uncacheable_miss_ff : io_ifc_fetch_uncacheable_bf; // @[ifu_mem_ctl.scala 213:84] - wire uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : _T_268; // @[ifu_mem_ctl.scala 213:32] - wire _T_274 = imb_ff[11:5] == imb_scnd_ff[11:5]; // @[ifu_mem_ctl.scala 216:79] - wire _T_275 = _T_274 & scnd_miss_req; // @[ifu_mem_ctl.scala 216:135] - reg [1:0] ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 506:51] - wire _T_2693 = |ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 551:48] - wire _T_2694 = _T_2693 & ifu_bus_rvalid_ff; // @[ifu_mem_ctl.scala 551:52] - wire bus_ifu_wr_data_error_ff = _T_2694 & miss_pending; // @[ifu_mem_ctl.scala 551:73] - reg ifu_wr_data_comb_err_ff; // @[ifu_mem_ctl.scala 290:61] - wire ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[ifu_mem_ctl.scala 289:55] - wire _T_276 = ~ifu_wr_cumulative_err_data; // @[ifu_mem_ctl.scala 216:153] - wire scnd_miss_index_match = _T_275 & _T_276; // @[ifu_mem_ctl.scala 216:151] - wire _T_277 = ~scnd_miss_index_match; // @[ifu_mem_ctl.scala 219:47] - wire _T_278 = scnd_miss_req & _T_277; // @[ifu_mem_ctl.scala 219:45] - wire _T_280 = scnd_miss_req & scnd_miss_index_match; // @[ifu_mem_ctl.scala 220:26] - reg way_status_mb_ff; // @[ifu_mem_ctl.scala 240:59] - wire _T_9756 = ~way_status_mb_ff; // @[ifu_mem_ctl.scala 714:33] - reg [1:0] tagv_mb_ff; // @[ifu_mem_ctl.scala 241:53] - wire _T_9758 = _T_9756 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 714:51] - wire _T_9760 = _T_9758 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 714:67] - wire _T_9762 = ~tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 714:86] - wire replace_way_mb_any_0 = _T_9760 | _T_9762; // @[ifu_mem_ctl.scala 714:84] + reg [2:0] ifu_bus_rid_ff; // @[ifu_mem_ctl.scala 515:46] + wire [2:0] ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & _T_206; // @[ifu_mem_ctl.scala 177:45] + wire _T_212 = _T_231 | _T_239; // @[ifu_mem_ctl.scala 182:59] + wire _T_214 = _T_212 | _T_2268; // @[ifu_mem_ctl.scala 182:91] + wire ic_iccm_hit_f = fetch_req_iccm_f & _T_214; // @[ifu_mem_ctl.scala 182:41] + wire _T_219 = _T_227 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 188:39] + wire _T_221 = _T_219 & _T_195; // @[ifu_mem_ctl.scala 188:60] + wire _T_225 = _T_221 & _T_212; // @[ifu_mem_ctl.scala 188:78] + wire ic_act_hit_f = _T_225 & _T_247; // @[ifu_mem_ctl.scala 188:126] + wire _T_262 = ic_act_hit_f | ic_byp_hit_f; // @[ifu_mem_ctl.scala 195:31] + wire _T_263 = _T_262 | ic_iccm_hit_f; // @[ifu_mem_ctl.scala 195:46] + wire _T_264 = ifc_region_acc_fault_final_f & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 195:94] + wire _T_268 = sel_hold_imb ? uncacheable_miss_ff : io_ifc_fetch_uncacheable_bf; // @[ifu_mem_ctl.scala 196:84] + wire uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : _T_268; // @[ifu_mem_ctl.scala 196:32] + wire _T_274 = imb_ff[11:5] == imb_scnd_ff[11:5]; // @[ifu_mem_ctl.scala 199:79] + wire _T_275 = _T_274 & scnd_miss_req; // @[ifu_mem_ctl.scala 199:135] + reg [1:0] ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 513:51] + wire _T_2693 = |ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 559:48] + wire _T_2694 = _T_2693 & ifu_bus_rvalid_ff; // @[ifu_mem_ctl.scala 559:52] + wire bus_ifu_wr_data_error_ff = _T_2694 & miss_pending; // @[ifu_mem_ctl.scala 559:73] + reg ifu_wr_data_comb_err_ff; // @[ifu_mem_ctl.scala 276:61] + wire ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[ifu_mem_ctl.scala 275:55] + wire _T_276 = ~ifu_wr_cumulative_err_data; // @[ifu_mem_ctl.scala 199:153] + wire scnd_miss_index_match = _T_275 & _T_276; // @[ifu_mem_ctl.scala 199:151] + wire _T_277 = ~scnd_miss_index_match; // @[ifu_mem_ctl.scala 202:47] + wire _T_278 = scnd_miss_req & _T_277; // @[ifu_mem_ctl.scala 202:45] + wire _T_280 = scnd_miss_req & scnd_miss_index_match; // @[ifu_mem_ctl.scala 203:26] + reg way_status_mb_ff; // @[ifu_mem_ctl.scala 223:59] + wire _T_9756 = ~way_status_mb_ff; // @[ifu_mem_ctl.scala 721:33] + reg [1:0] tagv_mb_ff; // @[ifu_mem_ctl.scala 224:53] + wire _T_9758 = _T_9756 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 721:51] + wire _T_9760 = _T_9758 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 721:67] + wire _T_9762 = ~tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 721:86] + wire replace_way_mb_any_0 = _T_9760 | _T_9762; // @[ifu_mem_ctl.scala 721:84] wire [1:0] _T_287 = scnd_miss_index_match ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_9765 = way_status_mb_ff & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 715:50] - wire _T_9767 = _T_9765 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 715:66] - wire _T_9769 = ~tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 715:85] - wire _T_9771 = _T_9769 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 715:100] - wire replace_way_mb_any_1 = _T_9767 | _T_9771; // @[ifu_mem_ctl.scala 715:83] + wire _T_9765 = way_status_mb_ff & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 722:50] + wire _T_9767 = _T_9765 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 722:66] + wire _T_9769 = ~tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 722:85] + wire _T_9771 = _T_9769 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 722:100] + wire replace_way_mb_any_1 = _T_9767 | _T_9771; // @[ifu_mem_ctl.scala 722:83] wire [1:0] _T_288 = {replace_way_mb_any_1,replace_way_mb_any_0}; // @[Cat.scala 29:58] - wire [1:0] _T_289 = _T_287 & _T_288; // @[ifu_mem_ctl.scala 224:110] - wire [1:0] _T_290 = tagv_mb_scnd_ff | _T_289; // @[ifu_mem_ctl.scala 224:62] - wire [1:0] _T_295 = io_ic_tag_valid & _T_197; // @[ifu_mem_ctl.scala 225:56] - wire _T_297 = ~scnd_miss_req_q; // @[ifu_mem_ctl.scala 228:36] - wire _T_298 = miss_pending & _T_297; // @[ifu_mem_ctl.scala 228:34] - reg reset_ic_ff; // @[ifu_mem_ctl.scala 229:48] - wire _T_299 = reset_all_tags | reset_ic_ff; // @[ifu_mem_ctl.scala 228:72] - wire reset_ic_in = _T_298 & _T_299; // @[ifu_mem_ctl.scala 228:53] - reg fetch_uncacheable_ff; // @[ifu_mem_ctl.scala 230:62] - reg [25:0] miss_addr; // @[ifu_mem_ctl.scala 239:48] - wire _T_309 = io_ifu_bus_clk_en | ic_act_miss_f; // @[ifu_mem_ctl.scala 238:57] - wire _T_315 = _T_2283 & flush_final_f; // @[ifu_mem_ctl.scala 243:87] - wire _T_316 = ~_T_315; // @[ifu_mem_ctl.scala 243:55] - wire _T_317 = io_ifc_fetch_req_bf & _T_316; // @[ifu_mem_ctl.scala 243:53] - wire _T_2275 = ~_T_2270; // @[ifu_mem_ctl.scala 387:46] - wire _T_2276 = _T_2268 & _T_2275; // @[ifu_mem_ctl.scala 387:44] - wire stream_miss_f = _T_2276 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 387:84] - wire _T_318 = ~stream_miss_f; // @[ifu_mem_ctl.scala 243:106] - reg ifc_region_acc_fault_f; // @[ifu_mem_ctl.scala 249:68] - reg [2:0] bus_rd_addr_count; // @[ifu_mem_ctl.scala 533:55] + wire [1:0] _T_289 = _T_287 & _T_288; // @[ifu_mem_ctl.scala 207:110] + wire [1:0] _T_290 = tagv_mb_scnd_ff | _T_289; // @[ifu_mem_ctl.scala 207:62] + wire [1:0] _T_295 = io_ic_tag_valid & _T_197; // @[ifu_mem_ctl.scala 208:56] + wire _T_297 = ~scnd_miss_req_q; // @[ifu_mem_ctl.scala 211:36] + wire _T_298 = miss_pending & _T_297; // @[ifu_mem_ctl.scala 211:34] + reg reset_ic_ff; // @[ifu_mem_ctl.scala 212:48] + wire _T_299 = reset_all_tags | reset_ic_ff; // @[ifu_mem_ctl.scala 211:72] + wire reset_ic_in = _T_298 & _T_299; // @[ifu_mem_ctl.scala 211:53] + reg fetch_uncacheable_ff; // @[ifu_mem_ctl.scala 213:62] + reg [25:0] miss_addr; // @[ifu_mem_ctl.scala 222:48] + wire _T_309 = io_ifu_bus_clk_en | ic_act_miss_f; // @[ifu_mem_ctl.scala 221:57] + wire _T_315 = _T_2283 & flush_final_f; // @[ifu_mem_ctl.scala 226:87] + wire _T_316 = ~_T_315; // @[ifu_mem_ctl.scala 226:55] + wire _T_317 = io_ifc_fetch_req_bf & _T_316; // @[ifu_mem_ctl.scala 226:53] + wire _T_2275 = ~_T_2270; // @[ifu_mem_ctl.scala 373:46] + wire _T_2276 = _T_2268 & _T_2275; // @[ifu_mem_ctl.scala 373:44] + wire stream_miss_f = _T_2276 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 373:84] + wire _T_318 = ~stream_miss_f; // @[ifu_mem_ctl.scala 226:106] + reg ifc_region_acc_fault_f; // @[ifu_mem_ctl.scala 232:68] + reg [2:0] bus_rd_addr_count; // @[ifu_mem_ctl.scala 541:55] wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58] - wire _T_325 = _T_239 | _T_2268; // @[ifu_mem_ctl.scala 251:55] - wire _T_328 = _T_325 & _T_56; // @[ifu_mem_ctl.scala 251:82] - wire _T_2289 = ~ifu_bus_rid_ff[0]; // @[ifu_mem_ctl.scala 392:55] + wire _T_325 = _T_239 | _T_2268; // @[ifu_mem_ctl.scala 234:55] + wire _T_328 = _T_325 & _T_56; // @[ifu_mem_ctl.scala 234:82] + wire _T_2289 = ~ifu_bus_rid_ff[0]; // @[ifu_mem_ctl.scala 378:55] wire [2:0] other_tag = {ifu_bus_rid_ff[2:1],_T_2289}; // @[Cat.scala 29:58] - wire _T_2290 = other_tag == 3'h0; // @[ifu_mem_ctl.scala 393:81] + wire _T_2290 = other_tag == 3'h0; // @[ifu_mem_ctl.scala 379:81] wire _T_2314 = _T_2290 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72] - wire _T_2293 = other_tag == 3'h1; // @[ifu_mem_ctl.scala 393:81] + wire _T_2293 = other_tag == 3'h1; // @[ifu_mem_ctl.scala 379:81] wire _T_2315 = _T_2293 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72] wire _T_2322 = _T_2314 | _T_2315; // @[Mux.scala 27:72] - wire _T_2296 = other_tag == 3'h2; // @[ifu_mem_ctl.scala 393:81] + wire _T_2296 = other_tag == 3'h2; // @[ifu_mem_ctl.scala 379:81] wire _T_2316 = _T_2296 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72] wire _T_2323 = _T_2322 | _T_2316; // @[Mux.scala 27:72] - wire _T_2299 = other_tag == 3'h3; // @[ifu_mem_ctl.scala 393:81] + wire _T_2299 = other_tag == 3'h3; // @[ifu_mem_ctl.scala 379:81] wire _T_2317 = _T_2299 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72] wire _T_2324 = _T_2323 | _T_2317; // @[Mux.scala 27:72] - wire _T_2302 = other_tag == 3'h4; // @[ifu_mem_ctl.scala 393:81] + wire _T_2302 = other_tag == 3'h4; // @[ifu_mem_ctl.scala 379:81] wire _T_2318 = _T_2302 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72] wire _T_2325 = _T_2324 | _T_2318; // @[Mux.scala 27:72] - wire _T_2305 = other_tag == 3'h5; // @[ifu_mem_ctl.scala 393:81] + wire _T_2305 = other_tag == 3'h5; // @[ifu_mem_ctl.scala 379:81] wire _T_2319 = _T_2305 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72] wire _T_2326 = _T_2325 | _T_2319; // @[Mux.scala 27:72] - wire _T_2308 = other_tag == 3'h6; // @[ifu_mem_ctl.scala 393:81] + wire _T_2308 = other_tag == 3'h6; // @[ifu_mem_ctl.scala 379:81] wire _T_2320 = _T_2308 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72] wire _T_2327 = _T_2326 | _T_2320; // @[Mux.scala 27:72] - wire _T_2311 = other_tag == 3'h7; // @[ifu_mem_ctl.scala 393:81] + wire _T_2311 = other_tag == 3'h7; // @[ifu_mem_ctl.scala 379:81] wire _T_2321 = _T_2311 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72] wire second_half_available = _T_2327 | _T_2321; // @[Mux.scala 27:72] - wire write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 394:46] - wire _T_332 = miss_pending & write_ic_16_bytes; // @[ifu_mem_ctl.scala 255:35] - wire _T_334 = _T_332 & _T_17; // @[ifu_mem_ctl.scala 255:55] - reg ic_act_miss_f_delayed; // @[ifu_mem_ctl.scala 548:61] - wire _T_2687 = ic_act_miss_f_delayed & _T_2284; // @[ifu_mem_ctl.scala 549:53] - wire reset_tag_valid_for_miss = _T_2687 & _T_17; // @[ifu_mem_ctl.scala 549:84] - wire sel_mb_addr = _T_334 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 255:79] + wire write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 380:46] + wire _T_332 = miss_pending & write_ic_16_bytes; // @[ifu_mem_ctl.scala 238:35] + wire _T_334 = _T_332 & _T_17; // @[ifu_mem_ctl.scala 238:55] + reg ic_act_miss_f_delayed; // @[ifu_mem_ctl.scala 556:61] + wire _T_2687 = ic_act_miss_f_delayed & _T_2284; // @[ifu_mem_ctl.scala 557:53] + wire reset_tag_valid_for_miss = _T_2687 & _T_17; // @[ifu_mem_ctl.scala 557:84] + wire sel_mb_addr = _T_334 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 238:79] wire [30:0] _T_338 = {imb_ff[30:5],ic_wr_addr_bits_hi_3,imb_ff[1:0]}; // @[Cat.scala 29:58] - wire _T_339 = ~sel_mb_addr; // @[ifu_mem_ctl.scala 257:37] + wire _T_339 = ~sel_mb_addr; // @[ifu_mem_ctl.scala 240:37] wire [30:0] _T_340 = sel_mb_addr ? _T_338 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_341 = _T_339 ? io_ifc_fetch_addr_bf : 31'h0; // @[Mux.scala 27:72] wire [30:0] ifu_ic_rw_int_addr = _T_340 | _T_341; // @[Mux.scala 27:72] - wire _T_346 = _T_334 & last_beat; // @[ifu_mem_ctl.scala 259:85] - wire _T_2681 = ~_T_2693; // @[ifu_mem_ctl.scala 546:84] - wire _T_2682 = _T_100 & _T_2681; // @[ifu_mem_ctl.scala 546:82] - wire bus_ifu_wr_en_ff_q = _T_2682 & write_ic_16_bytes; // @[ifu_mem_ctl.scala 546:108] - wire _T_347 = _T_346 & bus_ifu_wr_en_ff_q; // @[ifu_mem_ctl.scala 259:97] - wire sel_mb_status_addr = _T_347 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 259:119] - wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_338 : ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 260:31] - reg [63:0] ifu_bus_rdata_ff; // @[ifu_mem_ctl.scala 507:48] + wire _T_346 = _T_334 & last_beat; // @[ifu_mem_ctl.scala 242:85] + wire _T_2681 = ~_T_2693; // @[ifu_mem_ctl.scala 554:84] + wire _T_2682 = _T_100 & _T_2681; // @[ifu_mem_ctl.scala 554:82] + wire bus_ifu_wr_en_ff_q = _T_2682 & write_ic_16_bytes; // @[ifu_mem_ctl.scala 554:108] + wire _T_347 = _T_346 & bus_ifu_wr_en_ff_q; // @[ifu_mem_ctl.scala 242:97] + wire sel_mb_status_addr = _T_347 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 242:119] + wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_338 : ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 243:31] + reg [63:0] ifu_bus_rdata_ff; // @[ifu_mem_ctl.scala 514:48] wire [6:0] _T_570 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[57]}; // @[lib.scala 260:13] wire _T_571 = ^_T_570; // @[lib.scala 260:20] wire [6:0] _T_577 = {ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31],ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[26]}; // @[lib.scala 260:30] @@ -2012,115 +2012,115 @@ module ifu_mem_ctl( wire [34:0] _T_768 = {_T_767,_T_750}; // @[lib.scala 260:115] wire _T_769 = ^_T_768; // @[lib.scala 260:122] wire [3:0] _T_2330 = {ifu_bus_rid_ff[2:1],_T_2289,1'h1}; // @[Cat.scala 29:58] - wire _T_2331 = _T_2330 == 4'h0; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_0; // @[ifu_mem_ctl.scala 330:65] + wire _T_2331 = _T_2330 == 4'h0; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_0; // @[ifu_mem_ctl.scala 316:65] wire [31:0] _T_2378 = _T_2331 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] - wire _T_2334 = _T_2330 == 4'h1; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_1; // @[ifu_mem_ctl.scala 331:67] + wire _T_2334 = _T_2330 == 4'h1; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_1; // @[ifu_mem_ctl.scala 317:67] wire [31:0] _T_2379 = _T_2334 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2394 = _T_2378 | _T_2379; // @[Mux.scala 27:72] - wire _T_2337 = _T_2330 == 4'h2; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_2; // @[ifu_mem_ctl.scala 330:65] + wire _T_2337 = _T_2330 == 4'h2; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_2; // @[ifu_mem_ctl.scala 316:65] wire [31:0] _T_2380 = _T_2337 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2395 = _T_2394 | _T_2380; // @[Mux.scala 27:72] - wire _T_2340 = _T_2330 == 4'h3; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_3; // @[ifu_mem_ctl.scala 331:67] + wire _T_2340 = _T_2330 == 4'h3; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_3; // @[ifu_mem_ctl.scala 317:67] wire [31:0] _T_2381 = _T_2340 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2396 = _T_2395 | _T_2381; // @[Mux.scala 27:72] - wire _T_2343 = _T_2330 == 4'h4; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_4; // @[ifu_mem_ctl.scala 330:65] + wire _T_2343 = _T_2330 == 4'h4; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_4; // @[ifu_mem_ctl.scala 316:65] wire [31:0] _T_2382 = _T_2343 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2397 = _T_2396 | _T_2382; // @[Mux.scala 27:72] - wire _T_2346 = _T_2330 == 4'h5; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_5; // @[ifu_mem_ctl.scala 331:67] + wire _T_2346 = _T_2330 == 4'h5; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_5; // @[ifu_mem_ctl.scala 317:67] wire [31:0] _T_2383 = _T_2346 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2398 = _T_2397 | _T_2383; // @[Mux.scala 27:72] - wire _T_2349 = _T_2330 == 4'h6; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_6; // @[ifu_mem_ctl.scala 330:65] + wire _T_2349 = _T_2330 == 4'h6; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_6; // @[ifu_mem_ctl.scala 316:65] wire [31:0] _T_2384 = _T_2349 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2399 = _T_2398 | _T_2384; // @[Mux.scala 27:72] - wire _T_2352 = _T_2330 == 4'h7; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_7; // @[ifu_mem_ctl.scala 331:67] + wire _T_2352 = _T_2330 == 4'h7; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_7; // @[ifu_mem_ctl.scala 317:67] wire [31:0] _T_2385 = _T_2352 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2400 = _T_2399 | _T_2385; // @[Mux.scala 27:72] - wire _T_2355 = _T_2330 == 4'h8; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_8; // @[ifu_mem_ctl.scala 330:65] + wire _T_2355 = _T_2330 == 4'h8; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_8; // @[ifu_mem_ctl.scala 316:65] wire [31:0] _T_2386 = _T_2355 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2401 = _T_2400 | _T_2386; // @[Mux.scala 27:72] - wire _T_2358 = _T_2330 == 4'h9; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_9; // @[ifu_mem_ctl.scala 331:67] + wire _T_2358 = _T_2330 == 4'h9; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_9; // @[ifu_mem_ctl.scala 317:67] wire [31:0] _T_2387 = _T_2358 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2402 = _T_2401 | _T_2387; // @[Mux.scala 27:72] - wire _T_2361 = _T_2330 == 4'ha; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_10; // @[ifu_mem_ctl.scala 330:65] + wire _T_2361 = _T_2330 == 4'ha; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_10; // @[ifu_mem_ctl.scala 316:65] wire [31:0] _T_2388 = _T_2361 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2403 = _T_2402 | _T_2388; // @[Mux.scala 27:72] - wire _T_2364 = _T_2330 == 4'hb; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_11; // @[ifu_mem_ctl.scala 331:67] + wire _T_2364 = _T_2330 == 4'hb; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_11; // @[ifu_mem_ctl.scala 317:67] wire [31:0] _T_2389 = _T_2364 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2404 = _T_2403 | _T_2389; // @[Mux.scala 27:72] - wire _T_2367 = _T_2330 == 4'hc; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_12; // @[ifu_mem_ctl.scala 330:65] + wire _T_2367 = _T_2330 == 4'hc; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_12; // @[ifu_mem_ctl.scala 316:65] wire [31:0] _T_2390 = _T_2367 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2405 = _T_2404 | _T_2390; // @[Mux.scala 27:72] - wire _T_2370 = _T_2330 == 4'hd; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_13; // @[ifu_mem_ctl.scala 331:67] + wire _T_2370 = _T_2330 == 4'hd; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_13; // @[ifu_mem_ctl.scala 317:67] wire [31:0] _T_2391 = _T_2370 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2406 = _T_2405 | _T_2391; // @[Mux.scala 27:72] - wire _T_2373 = _T_2330 == 4'he; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_14; // @[ifu_mem_ctl.scala 330:65] + wire _T_2373 = _T_2330 == 4'he; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_14; // @[ifu_mem_ctl.scala 316:65] wire [31:0] _T_2392 = _T_2373 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2407 = _T_2406 | _T_2392; // @[Mux.scala 27:72] - wire _T_2376 = _T_2330 == 4'hf; // @[ifu_mem_ctl.scala 395:89] - reg [31:0] ic_miss_buff_data_15; // @[ifu_mem_ctl.scala 331:67] + wire _T_2376 = _T_2330 == 4'hf; // @[ifu_mem_ctl.scala 381:89] + reg [31:0] ic_miss_buff_data_15; // @[ifu_mem_ctl.scala 317:67] wire [31:0] _T_2393 = _T_2376 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2408 = _T_2407 | _T_2393; // @[Mux.scala 27:72] wire [3:0] _T_2410 = {ifu_bus_rid_ff[2:1],_T_2289,1'h0}; // @[Cat.scala 29:58] - wire _T_2411 = _T_2410 == 4'h0; // @[ifu_mem_ctl.scala 396:66] + wire _T_2411 = _T_2410 == 4'h0; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2458 = _T_2411 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] - wire _T_2414 = _T_2410 == 4'h1; // @[ifu_mem_ctl.scala 396:66] + wire _T_2414 = _T_2410 == 4'h1; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2459 = _T_2414 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2474 = _T_2458 | _T_2459; // @[Mux.scala 27:72] - wire _T_2417 = _T_2410 == 4'h2; // @[ifu_mem_ctl.scala 396:66] + wire _T_2417 = _T_2410 == 4'h2; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2460 = _T_2417 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2475 = _T_2474 | _T_2460; // @[Mux.scala 27:72] - wire _T_2420 = _T_2410 == 4'h3; // @[ifu_mem_ctl.scala 396:66] + wire _T_2420 = _T_2410 == 4'h3; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2461 = _T_2420 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2476 = _T_2475 | _T_2461; // @[Mux.scala 27:72] - wire _T_2423 = _T_2410 == 4'h4; // @[ifu_mem_ctl.scala 396:66] + wire _T_2423 = _T_2410 == 4'h4; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2462 = _T_2423 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2477 = _T_2476 | _T_2462; // @[Mux.scala 27:72] - wire _T_2426 = _T_2410 == 4'h5; // @[ifu_mem_ctl.scala 396:66] + wire _T_2426 = _T_2410 == 4'h5; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2463 = _T_2426 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2478 = _T_2477 | _T_2463; // @[Mux.scala 27:72] - wire _T_2429 = _T_2410 == 4'h6; // @[ifu_mem_ctl.scala 396:66] + wire _T_2429 = _T_2410 == 4'h6; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2464 = _T_2429 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2479 = _T_2478 | _T_2464; // @[Mux.scala 27:72] - wire _T_2432 = _T_2410 == 4'h7; // @[ifu_mem_ctl.scala 396:66] + wire _T_2432 = _T_2410 == 4'h7; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2465 = _T_2432 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2480 = _T_2479 | _T_2465; // @[Mux.scala 27:72] - wire _T_2435 = _T_2410 == 4'h8; // @[ifu_mem_ctl.scala 396:66] + wire _T_2435 = _T_2410 == 4'h8; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2466 = _T_2435 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2481 = _T_2480 | _T_2466; // @[Mux.scala 27:72] - wire _T_2438 = _T_2410 == 4'h9; // @[ifu_mem_ctl.scala 396:66] + wire _T_2438 = _T_2410 == 4'h9; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2467 = _T_2438 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2482 = _T_2481 | _T_2467; // @[Mux.scala 27:72] - wire _T_2441 = _T_2410 == 4'ha; // @[ifu_mem_ctl.scala 396:66] + wire _T_2441 = _T_2410 == 4'ha; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2468 = _T_2441 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2483 = _T_2482 | _T_2468; // @[Mux.scala 27:72] - wire _T_2444 = _T_2410 == 4'hb; // @[ifu_mem_ctl.scala 396:66] + wire _T_2444 = _T_2410 == 4'hb; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2469 = _T_2444 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2484 = _T_2483 | _T_2469; // @[Mux.scala 27:72] - wire _T_2447 = _T_2410 == 4'hc; // @[ifu_mem_ctl.scala 396:66] + wire _T_2447 = _T_2410 == 4'hc; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2470 = _T_2447 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2485 = _T_2484 | _T_2470; // @[Mux.scala 27:72] - wire _T_2450 = _T_2410 == 4'hd; // @[ifu_mem_ctl.scala 396:66] + wire _T_2450 = _T_2410 == 4'hd; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2471 = _T_2450 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2486 = _T_2485 | _T_2471; // @[Mux.scala 27:72] - wire _T_2453 = _T_2410 == 4'he; // @[ifu_mem_ctl.scala 396:66] + wire _T_2453 = _T_2410 == 4'he; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2472 = _T_2453 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2487 = _T_2486 | _T_2472; // @[Mux.scala 27:72] - wire _T_2456 = _T_2410 == 4'hf; // @[ifu_mem_ctl.scala 396:66] + wire _T_2456 = _T_2410 == 4'hf; // @[ifu_mem_ctl.scala 382:66] wire [31:0] _T_2473 = _T_2456 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2488 = _T_2487 | _T_2473; // @[Mux.scala 27:72] wire [63:0] ic_miss_buff_half = {_T_2408,_T_2488}; // @[Cat.scala 29:58] @@ -2162,1126 +2162,1126 @@ module ifu_mem_ctl( wire [70:0] _T_1235 = {_T_993,_T_1024,_T_1055,_T_1086,_T_1121,_T_1156,_T_1191,_T_2408,_T_2488}; // @[Cat.scala 29:58] wire [141:0] _T_1237 = {_T_571,_T_602,_T_633,_T_664,_T_699,_T_734,_T_769,ifu_bus_rdata_ff,_T_1235}; // @[Cat.scala 29:58] wire [141:0] _T_1240 = {_T_993,_T_1024,_T_1055,_T_1086,_T_1121,_T_1156,_T_1191,_T_2408,_T_2488,_T_1236}; // @[Cat.scala 29:58] - wire [141:0] ic_wr_16bytes_data = ifu_bus_rid_ff[0] ? _T_1237 : _T_1240; // @[ifu_mem_ctl.scala 281:28] - wire _T_1199 = |io_ic_eccerr; // @[ifu_mem_ctl.scala 271:73] - wire _T_1200 = _T_1199 & ic_act_hit_f; // @[ifu_mem_ctl.scala 271:100] - wire [4:0] bypass_index = imb_ff[4:0]; // @[ifu_mem_ctl.scala 342:28] - wire _T_1404 = bypass_index[4:2] == 3'h0; // @[ifu_mem_ctl.scala 344:114] - wire bus_ifu_wr_en = _T_13 & miss_pending; // @[ifu_mem_ctl.scala 544:35] - wire _T_1289 = io_ifu_axi_r_bits_id == 3'h0; // @[ifu_mem_ctl.scala 326:91] - wire write_fill_data_0 = bus_ifu_wr_en & _T_1289; // @[ifu_mem_ctl.scala 326:73] - wire _T_1330 = ~ic_act_miss_f; // @[ifu_mem_ctl.scala 333:118] - wire _T_1331 = ic_miss_buff_data_valid[0] & _T_1330; // @[ifu_mem_ctl.scala 333:116] - wire ic_miss_buff_data_valid_in_0 = write_fill_data_0 | _T_1331; // @[ifu_mem_ctl.scala 333:88] + wire [141:0] ic_wr_16bytes_data = ifu_bus_rid_ff[0] ? _T_1237 : _T_1240; // @[ifu_mem_ctl.scala 267:28] + wire _T_1199 = |io_ic_eccerr; // @[ifu_mem_ctl.scala 256:73] + wire _T_1200 = _T_1199 & ic_act_hit_f; // @[ifu_mem_ctl.scala 256:100] + wire [4:0] bypass_index = imb_ff[4:0]; // @[ifu_mem_ctl.scala 328:28] + wire _T_1404 = bypass_index[4:2] == 3'h0; // @[ifu_mem_ctl.scala 330:114] + wire bus_ifu_wr_en = _T_13 & miss_pending; // @[ifu_mem_ctl.scala 552:35] + wire _T_1289 = io_ifu_axi_r_bits_id == 3'h0; // @[ifu_mem_ctl.scala 312:91] + wire write_fill_data_0 = bus_ifu_wr_en & _T_1289; // @[ifu_mem_ctl.scala 312:73] + wire _T_1330 = ~ic_act_miss_f; // @[ifu_mem_ctl.scala 319:118] + wire _T_1331 = ic_miss_buff_data_valid[0] & _T_1330; // @[ifu_mem_ctl.scala 319:116] + wire ic_miss_buff_data_valid_in_0 = write_fill_data_0 | _T_1331; // @[ifu_mem_ctl.scala 319:88] wire _T_1427 = _T_1404 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72] - wire _T_1407 = bypass_index[4:2] == 3'h1; // @[ifu_mem_ctl.scala 344:114] - wire _T_1290 = io_ifu_axi_r_bits_id == 3'h1; // @[ifu_mem_ctl.scala 326:91] - wire write_fill_data_1 = bus_ifu_wr_en & _T_1290; // @[ifu_mem_ctl.scala 326:73] - wire _T_1334 = ic_miss_buff_data_valid[1] & _T_1330; // @[ifu_mem_ctl.scala 333:116] - wire ic_miss_buff_data_valid_in_1 = write_fill_data_1 | _T_1334; // @[ifu_mem_ctl.scala 333:88] + wire _T_1407 = bypass_index[4:2] == 3'h1; // @[ifu_mem_ctl.scala 330:114] + wire _T_1290 = io_ifu_axi_r_bits_id == 3'h1; // @[ifu_mem_ctl.scala 312:91] + wire write_fill_data_1 = bus_ifu_wr_en & _T_1290; // @[ifu_mem_ctl.scala 312:73] + wire _T_1334 = ic_miss_buff_data_valid[1] & _T_1330; // @[ifu_mem_ctl.scala 319:116] + wire ic_miss_buff_data_valid_in_1 = write_fill_data_1 | _T_1334; // @[ifu_mem_ctl.scala 319:88] wire _T_1428 = _T_1407 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72] wire _T_1435 = _T_1427 | _T_1428; // @[Mux.scala 27:72] - wire _T_1410 = bypass_index[4:2] == 3'h2; // @[ifu_mem_ctl.scala 344:114] - wire _T_1291 = io_ifu_axi_r_bits_id == 3'h2; // @[ifu_mem_ctl.scala 326:91] - wire write_fill_data_2 = bus_ifu_wr_en & _T_1291; // @[ifu_mem_ctl.scala 326:73] - wire _T_1337 = ic_miss_buff_data_valid[2] & _T_1330; // @[ifu_mem_ctl.scala 333:116] - wire ic_miss_buff_data_valid_in_2 = write_fill_data_2 | _T_1337; // @[ifu_mem_ctl.scala 333:88] + wire _T_1410 = bypass_index[4:2] == 3'h2; // @[ifu_mem_ctl.scala 330:114] + wire _T_1291 = io_ifu_axi_r_bits_id == 3'h2; // @[ifu_mem_ctl.scala 312:91] + wire write_fill_data_2 = bus_ifu_wr_en & _T_1291; // @[ifu_mem_ctl.scala 312:73] + wire _T_1337 = ic_miss_buff_data_valid[2] & _T_1330; // @[ifu_mem_ctl.scala 319:116] + wire ic_miss_buff_data_valid_in_2 = write_fill_data_2 | _T_1337; // @[ifu_mem_ctl.scala 319:88] wire _T_1429 = _T_1410 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72] wire _T_1436 = _T_1435 | _T_1429; // @[Mux.scala 27:72] - wire _T_1413 = bypass_index[4:2] == 3'h3; // @[ifu_mem_ctl.scala 344:114] - wire _T_1292 = io_ifu_axi_r_bits_id == 3'h3; // @[ifu_mem_ctl.scala 326:91] - wire write_fill_data_3 = bus_ifu_wr_en & _T_1292; // @[ifu_mem_ctl.scala 326:73] - wire _T_1340 = ic_miss_buff_data_valid[3] & _T_1330; // @[ifu_mem_ctl.scala 333:116] - wire ic_miss_buff_data_valid_in_3 = write_fill_data_3 | _T_1340; // @[ifu_mem_ctl.scala 333:88] + wire _T_1413 = bypass_index[4:2] == 3'h3; // @[ifu_mem_ctl.scala 330:114] + wire _T_1292 = io_ifu_axi_r_bits_id == 3'h3; // @[ifu_mem_ctl.scala 312:91] + wire write_fill_data_3 = bus_ifu_wr_en & _T_1292; // @[ifu_mem_ctl.scala 312:73] + wire _T_1340 = ic_miss_buff_data_valid[3] & _T_1330; // @[ifu_mem_ctl.scala 319:116] + wire ic_miss_buff_data_valid_in_3 = write_fill_data_3 | _T_1340; // @[ifu_mem_ctl.scala 319:88] wire _T_1430 = _T_1413 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72] wire _T_1437 = _T_1436 | _T_1430; // @[Mux.scala 27:72] - wire _T_1416 = bypass_index[4:2] == 3'h4; // @[ifu_mem_ctl.scala 344:114] - wire _T_1293 = io_ifu_axi_r_bits_id == 3'h4; // @[ifu_mem_ctl.scala 326:91] - wire write_fill_data_4 = bus_ifu_wr_en & _T_1293; // @[ifu_mem_ctl.scala 326:73] - wire _T_1343 = ic_miss_buff_data_valid[4] & _T_1330; // @[ifu_mem_ctl.scala 333:116] - wire ic_miss_buff_data_valid_in_4 = write_fill_data_4 | _T_1343; // @[ifu_mem_ctl.scala 333:88] + wire _T_1416 = bypass_index[4:2] == 3'h4; // @[ifu_mem_ctl.scala 330:114] + wire _T_1293 = io_ifu_axi_r_bits_id == 3'h4; // @[ifu_mem_ctl.scala 312:91] + wire write_fill_data_4 = bus_ifu_wr_en & _T_1293; // @[ifu_mem_ctl.scala 312:73] + wire _T_1343 = ic_miss_buff_data_valid[4] & _T_1330; // @[ifu_mem_ctl.scala 319:116] + wire ic_miss_buff_data_valid_in_4 = write_fill_data_4 | _T_1343; // @[ifu_mem_ctl.scala 319:88] wire _T_1431 = _T_1416 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72] wire _T_1438 = _T_1437 | _T_1431; // @[Mux.scala 27:72] - wire _T_1419 = bypass_index[4:2] == 3'h5; // @[ifu_mem_ctl.scala 344:114] - wire _T_1294 = io_ifu_axi_r_bits_id == 3'h5; // @[ifu_mem_ctl.scala 326:91] - wire write_fill_data_5 = bus_ifu_wr_en & _T_1294; // @[ifu_mem_ctl.scala 326:73] - wire _T_1346 = ic_miss_buff_data_valid[5] & _T_1330; // @[ifu_mem_ctl.scala 333:116] - wire ic_miss_buff_data_valid_in_5 = write_fill_data_5 | _T_1346; // @[ifu_mem_ctl.scala 333:88] + wire _T_1419 = bypass_index[4:2] == 3'h5; // @[ifu_mem_ctl.scala 330:114] + wire _T_1294 = io_ifu_axi_r_bits_id == 3'h5; // @[ifu_mem_ctl.scala 312:91] + wire write_fill_data_5 = bus_ifu_wr_en & _T_1294; // @[ifu_mem_ctl.scala 312:73] + wire _T_1346 = ic_miss_buff_data_valid[5] & _T_1330; // @[ifu_mem_ctl.scala 319:116] + wire ic_miss_buff_data_valid_in_5 = write_fill_data_5 | _T_1346; // @[ifu_mem_ctl.scala 319:88] wire _T_1432 = _T_1419 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72] wire _T_1439 = _T_1438 | _T_1432; // @[Mux.scala 27:72] - wire _T_1422 = bypass_index[4:2] == 3'h6; // @[ifu_mem_ctl.scala 344:114] - wire _T_1295 = io_ifu_axi_r_bits_id == 3'h6; // @[ifu_mem_ctl.scala 326:91] - wire write_fill_data_6 = bus_ifu_wr_en & _T_1295; // @[ifu_mem_ctl.scala 326:73] - wire _T_1349 = ic_miss_buff_data_valid[6] & _T_1330; // @[ifu_mem_ctl.scala 333:116] - wire ic_miss_buff_data_valid_in_6 = write_fill_data_6 | _T_1349; // @[ifu_mem_ctl.scala 333:88] + wire _T_1422 = bypass_index[4:2] == 3'h6; // @[ifu_mem_ctl.scala 330:114] + wire _T_1295 = io_ifu_axi_r_bits_id == 3'h6; // @[ifu_mem_ctl.scala 312:91] + wire write_fill_data_6 = bus_ifu_wr_en & _T_1295; // @[ifu_mem_ctl.scala 312:73] + wire _T_1349 = ic_miss_buff_data_valid[6] & _T_1330; // @[ifu_mem_ctl.scala 319:116] + wire ic_miss_buff_data_valid_in_6 = write_fill_data_6 | _T_1349; // @[ifu_mem_ctl.scala 319:88] wire _T_1433 = _T_1422 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72] wire _T_1440 = _T_1439 | _T_1433; // @[Mux.scala 27:72] - wire _T_1425 = bypass_index[4:2] == 3'h7; // @[ifu_mem_ctl.scala 344:114] - wire _T_1296 = io_ifu_axi_r_bits_id == 3'h7; // @[ifu_mem_ctl.scala 326:91] - wire write_fill_data_7 = bus_ifu_wr_en & _T_1296; // @[ifu_mem_ctl.scala 326:73] - wire _T_1352 = ic_miss_buff_data_valid[7] & _T_1330; // @[ifu_mem_ctl.scala 333:116] - wire ic_miss_buff_data_valid_in_7 = write_fill_data_7 | _T_1352; // @[ifu_mem_ctl.scala 333:88] + wire _T_1425 = bypass_index[4:2] == 3'h7; // @[ifu_mem_ctl.scala 330:114] + wire _T_1296 = io_ifu_axi_r_bits_id == 3'h7; // @[ifu_mem_ctl.scala 312:91] + wire write_fill_data_7 = bus_ifu_wr_en & _T_1296; // @[ifu_mem_ctl.scala 312:73] + wire _T_1352 = ic_miss_buff_data_valid[7] & _T_1330; // @[ifu_mem_ctl.scala 319:116] + wire ic_miss_buff_data_valid_in_7 = write_fill_data_7 | _T_1352; // @[ifu_mem_ctl.scala 319:88] wire _T_1434 = _T_1425 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72] wire bypass_valid_value_check = _T_1440 | _T_1434; // @[Mux.scala 27:72] - wire _T_1443 = ~bypass_index[1]; // @[ifu_mem_ctl.scala 345:58] - wire _T_1444 = bypass_valid_value_check & _T_1443; // @[ifu_mem_ctl.scala 345:56] - wire _T_1446 = ~bypass_index[0]; // @[ifu_mem_ctl.scala 345:77] - wire _T_1447 = _T_1444 & _T_1446; // @[ifu_mem_ctl.scala 345:75] - wire _T_1452 = _T_1444 & bypass_index[0]; // @[ifu_mem_ctl.scala 346:75] - wire _T_1453 = _T_1447 | _T_1452; // @[ifu_mem_ctl.scala 345:95] - wire _T_1455 = bypass_valid_value_check & bypass_index[1]; // @[ifu_mem_ctl.scala 347:56] - wire _T_1458 = _T_1455 & _T_1446; // @[ifu_mem_ctl.scala 347:74] - wire _T_1459 = _T_1453 | _T_1458; // @[ifu_mem_ctl.scala 346:94] - wire _T_1463 = _T_1455 & bypass_index[0]; // @[ifu_mem_ctl.scala 348:51] - wire [2:0] bypass_index_5_3_inc = bypass_index[4:2] + 3'h1; // @[ifu_mem_ctl.scala 343:70] - wire _T_1464 = bypass_index_5_3_inc == 3'h0; // @[ifu_mem_ctl.scala 348:132] + wire _T_1443 = ~bypass_index[1]; // @[ifu_mem_ctl.scala 331:58] + wire _T_1444 = bypass_valid_value_check & _T_1443; // @[ifu_mem_ctl.scala 331:56] + wire _T_1446 = ~bypass_index[0]; // @[ifu_mem_ctl.scala 331:77] + wire _T_1447 = _T_1444 & _T_1446; // @[ifu_mem_ctl.scala 331:75] + wire _T_1452 = _T_1444 & bypass_index[0]; // @[ifu_mem_ctl.scala 332:75] + wire _T_1453 = _T_1447 | _T_1452; // @[ifu_mem_ctl.scala 331:95] + wire _T_1455 = bypass_valid_value_check & bypass_index[1]; // @[ifu_mem_ctl.scala 333:56] + wire _T_1458 = _T_1455 & _T_1446; // @[ifu_mem_ctl.scala 333:74] + wire _T_1459 = _T_1453 | _T_1458; // @[ifu_mem_ctl.scala 332:94] + wire _T_1463 = _T_1455 & bypass_index[0]; // @[ifu_mem_ctl.scala 334:51] + wire [2:0] bypass_index_5_3_inc = bypass_index[4:2] + 3'h1; // @[ifu_mem_ctl.scala 329:70] + wire _T_1464 = bypass_index_5_3_inc == 3'h0; // @[ifu_mem_ctl.scala 334:132] wire _T_1480 = _T_1464 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72] - wire _T_1466 = bypass_index_5_3_inc == 3'h1; // @[ifu_mem_ctl.scala 348:132] + wire _T_1466 = bypass_index_5_3_inc == 3'h1; // @[ifu_mem_ctl.scala 334:132] wire _T_1481 = _T_1466 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72] wire _T_1488 = _T_1480 | _T_1481; // @[Mux.scala 27:72] - wire _T_1468 = bypass_index_5_3_inc == 3'h2; // @[ifu_mem_ctl.scala 348:132] + wire _T_1468 = bypass_index_5_3_inc == 3'h2; // @[ifu_mem_ctl.scala 334:132] wire _T_1482 = _T_1468 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72] wire _T_1489 = _T_1488 | _T_1482; // @[Mux.scala 27:72] - wire _T_1470 = bypass_index_5_3_inc == 3'h3; // @[ifu_mem_ctl.scala 348:132] + wire _T_1470 = bypass_index_5_3_inc == 3'h3; // @[ifu_mem_ctl.scala 334:132] wire _T_1483 = _T_1470 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72] wire _T_1490 = _T_1489 | _T_1483; // @[Mux.scala 27:72] - wire _T_1472 = bypass_index_5_3_inc == 3'h4; // @[ifu_mem_ctl.scala 348:132] + wire _T_1472 = bypass_index_5_3_inc == 3'h4; // @[ifu_mem_ctl.scala 334:132] wire _T_1484 = _T_1472 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72] wire _T_1491 = _T_1490 | _T_1484; // @[Mux.scala 27:72] - wire _T_1474 = bypass_index_5_3_inc == 3'h5; // @[ifu_mem_ctl.scala 348:132] + wire _T_1474 = bypass_index_5_3_inc == 3'h5; // @[ifu_mem_ctl.scala 334:132] wire _T_1485 = _T_1474 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72] wire _T_1492 = _T_1491 | _T_1485; // @[Mux.scala 27:72] - wire _T_1476 = bypass_index_5_3_inc == 3'h6; // @[ifu_mem_ctl.scala 348:132] + wire _T_1476 = bypass_index_5_3_inc == 3'h6; // @[ifu_mem_ctl.scala 334:132] wire _T_1486 = _T_1476 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72] wire _T_1493 = _T_1492 | _T_1486; // @[Mux.scala 27:72] - wire _T_1478 = bypass_index_5_3_inc == 3'h7; // @[ifu_mem_ctl.scala 348:132] + wire _T_1478 = bypass_index_5_3_inc == 3'h7; // @[ifu_mem_ctl.scala 334:132] wire _T_1487 = _T_1478 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72] wire _T_1494 = _T_1493 | _T_1487; // @[Mux.scala 27:72] - wire _T_1496 = _T_1463 & _T_1494; // @[ifu_mem_ctl.scala 348:69] - wire _T_1497 = _T_1459 | _T_1496; // @[ifu_mem_ctl.scala 347:94] - wire [4:0] _GEN_436 = {{2'd0}, bypass_index[4:2]}; // @[ifu_mem_ctl.scala 349:95] - wire _T_1500 = _GEN_436 == 5'h1f; // @[ifu_mem_ctl.scala 349:95] - wire _T_1501 = bypass_valid_value_check & _T_1500; // @[ifu_mem_ctl.scala 349:56] - wire bypass_data_ready_in = _T_1497 | _T_1501; // @[ifu_mem_ctl.scala 348:181] - wire _T_1502 = bypass_data_ready_in & crit_wd_byp_ok_ff; // @[ifu_mem_ctl.scala 353:53] - wire _T_1503 = _T_1502 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 353:73] - wire _T_1505 = _T_1503 & _T_319; // @[ifu_mem_ctl.scala 353:96] - wire _T_1507 = _T_1505 & _T_58; // @[ifu_mem_ctl.scala 353:118] - wire _T_1509 = crit_wd_byp_ok_ff & _T_17; // @[ifu_mem_ctl.scala 354:73] - wire _T_1511 = _T_1509 & _T_319; // @[ifu_mem_ctl.scala 354:96] - wire _T_1513 = _T_1511 & _T_58; // @[ifu_mem_ctl.scala 354:118] - wire _T_1514 = _T_1507 | _T_1513; // @[ifu_mem_ctl.scala 353:143] - reg ic_crit_wd_rdy_new_ff; // @[ifu_mem_ctl.scala 356:58] - wire _T_1515 = ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff; // @[ifu_mem_ctl.scala 355:54] - wire _T_1516 = ~fetch_req_icache_f; // @[ifu_mem_ctl.scala 355:76] - wire _T_1517 = _T_1515 & _T_1516; // @[ifu_mem_ctl.scala 355:74] - wire _T_1519 = _T_1517 & _T_319; // @[ifu_mem_ctl.scala 355:96] - wire ic_crit_wd_rdy_new_in = _T_1514 | _T_1519; // @[ifu_mem_ctl.scala 354:143] - wire ic_crit_wd_rdy = ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff; // @[ifu_mem_ctl.scala 554:43] - wire _T_1252 = ic_crit_wd_rdy | _T_2268; // @[ifu_mem_ctl.scala 294:38] - wire _T_1254 = _T_1252 | _T_2284; // @[ifu_mem_ctl.scala 294:64] - wire _T_1255 = ~_T_1254; // @[ifu_mem_ctl.scala 294:21] - wire _T_1256 = ~fetch_req_iccm_f; // @[ifu_mem_ctl.scala 294:98] - wire sel_ic_data = _T_1255 & _T_1256; // @[ifu_mem_ctl.scala 294:96] - wire _T_2491 = io_ic_tag_perr & sel_ic_data; // @[ifu_mem_ctl.scala 398:44] - wire _T_1612 = ~ifu_fetch_addr_int_f[1]; // @[ifu_mem_ctl.scala 365:30] - wire _T_1614 = ~ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 365:57] - wire _T_1615 = _T_1612 & _T_1614; // @[ifu_mem_ctl.scala 365:55] - reg [7:0] ic_miss_buff_data_error; // @[ifu_mem_ctl.scala 339:60] - wire [7:0] _T_1617 = ic_miss_buff_data_error >> byp_fetch_index[4:2]; // @[ifu_mem_ctl.scala 365:107] - wire _T_1619 = _T_1615 & _T_1617[0]; // @[ifu_mem_ctl.scala 365:82] - wire _T_1623 = _T_1612 & ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 366:33] - wire _T_1627 = _T_1623 & _T_1617[0]; // @[ifu_mem_ctl.scala 366:60] - wire _T_1628 = _T_1619 | _T_1627; // @[ifu_mem_ctl.scala 365:151] - wire _T_1637 = _T_1628 | _T_1627; // @[ifu_mem_ctl.scala 366:129] - wire _T_1641 = ifu_fetch_addr_int_f[1] & _T_1614; // @[ifu_mem_ctl.scala 368:33] - wire _T_1645 = _T_1641 & _T_1617[0]; // @[ifu_mem_ctl.scala 368:60] - wire _T_1646 = _T_1637 | _T_1645; // @[ifu_mem_ctl.scala 367:129] - wire _T_1649 = ifu_fetch_addr_int_f[1] & ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 369:32] - wire [7:0] _T_1654 = ic_miss_buff_data_error >> byp_fetch_index_inc; // @[ifu_mem_ctl.scala 370:32] - wire _T_1656 = _T_1617[0] | _T_1654[0]; // @[ifu_mem_ctl.scala 369:127] - wire _T_1657 = _T_1649 & _T_1656; // @[ifu_mem_ctl.scala 369:58] - wire ifu_byp_data_err_new = _T_1646 | _T_1657; // @[ifu_mem_ctl.scala 368:129] - wire ifc_bus_acc_fault_f = ic_byp_hit_f & ifu_byp_data_err_new; // @[ifu_mem_ctl.scala 311:42] - wire _T_2492 = ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f; // @[ifu_mem_ctl.scala 398:91] - wire _T_2493 = ~_T_2492; // @[ifu_mem_ctl.scala 398:60] - wire ic_rd_parity_final_err = _T_2491 & _T_2493; // @[ifu_mem_ctl.scala 398:58] - reg ic_debug_ict_array_sel_ff; // @[ifu_mem_ctl.scala 762:63] + wire _T_1496 = _T_1463 & _T_1494; // @[ifu_mem_ctl.scala 334:69] + wire _T_1497 = _T_1459 | _T_1496; // @[ifu_mem_ctl.scala 333:94] + wire [4:0] _GEN_436 = {{2'd0}, bypass_index[4:2]}; // @[ifu_mem_ctl.scala 335:95] + wire _T_1500 = _GEN_436 == 5'h1f; // @[ifu_mem_ctl.scala 335:95] + wire _T_1501 = bypass_valid_value_check & _T_1500; // @[ifu_mem_ctl.scala 335:56] + wire bypass_data_ready_in = _T_1497 | _T_1501; // @[ifu_mem_ctl.scala 334:181] + wire _T_1502 = bypass_data_ready_in & crit_wd_byp_ok_ff; // @[ifu_mem_ctl.scala 339:53] + wire _T_1503 = _T_1502 & uncacheable_miss_ff; // @[ifu_mem_ctl.scala 339:73] + wire _T_1505 = _T_1503 & _T_319; // @[ifu_mem_ctl.scala 339:96] + wire _T_1507 = _T_1505 & _T_58; // @[ifu_mem_ctl.scala 339:118] + wire _T_1509 = crit_wd_byp_ok_ff & _T_17; // @[ifu_mem_ctl.scala 340:73] + wire _T_1511 = _T_1509 & _T_319; // @[ifu_mem_ctl.scala 340:96] + wire _T_1513 = _T_1511 & _T_58; // @[ifu_mem_ctl.scala 340:118] + wire _T_1514 = _T_1507 | _T_1513; // @[ifu_mem_ctl.scala 339:143] + reg ic_crit_wd_rdy_new_ff; // @[ifu_mem_ctl.scala 342:58] + wire _T_1515 = ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff; // @[ifu_mem_ctl.scala 341:54] + wire _T_1516 = ~fetch_req_icache_f; // @[ifu_mem_ctl.scala 341:76] + wire _T_1517 = _T_1515 & _T_1516; // @[ifu_mem_ctl.scala 341:74] + wire _T_1519 = _T_1517 & _T_319; // @[ifu_mem_ctl.scala 341:96] + wire ic_crit_wd_rdy_new_in = _T_1514 | _T_1519; // @[ifu_mem_ctl.scala 340:143] + wire ic_crit_wd_rdy = ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff; // @[ifu_mem_ctl.scala 562:43] + wire _T_1252 = ic_crit_wd_rdy | _T_2268; // @[ifu_mem_ctl.scala 280:38] + wire _T_1254 = _T_1252 | _T_2284; // @[ifu_mem_ctl.scala 280:64] + wire _T_1255 = ~_T_1254; // @[ifu_mem_ctl.scala 280:21] + wire _T_1256 = ~fetch_req_iccm_f; // @[ifu_mem_ctl.scala 280:98] + wire sel_ic_data = _T_1255 & _T_1256; // @[ifu_mem_ctl.scala 280:96] + wire _T_2491 = io_ic_tag_perr & sel_ic_data; // @[ifu_mem_ctl.scala 385:44] + wire _T_1612 = ~ifu_fetch_addr_int_f[1]; // @[ifu_mem_ctl.scala 351:30] + wire _T_1614 = ~ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 351:57] + wire _T_1615 = _T_1612 & _T_1614; // @[ifu_mem_ctl.scala 351:55] + reg [7:0] ic_miss_buff_data_error; // @[ifu_mem_ctl.scala 325:60] + wire [7:0] _T_1617 = ic_miss_buff_data_error >> byp_fetch_index[4:2]; // @[ifu_mem_ctl.scala 351:107] + wire _T_1619 = _T_1615 & _T_1617[0]; // @[ifu_mem_ctl.scala 351:82] + wire _T_1623 = _T_1612 & ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 352:33] + wire _T_1627 = _T_1623 & _T_1617[0]; // @[ifu_mem_ctl.scala 352:60] + wire _T_1628 = _T_1619 | _T_1627; // @[ifu_mem_ctl.scala 351:151] + wire _T_1637 = _T_1628 | _T_1627; // @[ifu_mem_ctl.scala 352:129] + wire _T_1641 = ifu_fetch_addr_int_f[1] & _T_1614; // @[ifu_mem_ctl.scala 354:33] + wire _T_1645 = _T_1641 & _T_1617[0]; // @[ifu_mem_ctl.scala 354:60] + wire _T_1646 = _T_1637 | _T_1645; // @[ifu_mem_ctl.scala 353:129] + wire _T_1649 = ifu_fetch_addr_int_f[1] & ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 355:32] + wire [7:0] _T_1654 = ic_miss_buff_data_error >> byp_fetch_index_inc; // @[ifu_mem_ctl.scala 356:32] + wire _T_1656 = _T_1617[0] | _T_1654[0]; // @[ifu_mem_ctl.scala 355:127] + wire _T_1657 = _T_1649 & _T_1656; // @[ifu_mem_ctl.scala 355:58] + wire ifu_byp_data_err_new = _T_1646 | _T_1657; // @[ifu_mem_ctl.scala 354:129] + wire ifc_bus_acc_fault_f = ic_byp_hit_f & ifu_byp_data_err_new; // @[ifu_mem_ctl.scala 297:42] + wire _T_2492 = ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f; // @[ifu_mem_ctl.scala 385:91] + wire _T_2493 = ~_T_2492; // @[ifu_mem_ctl.scala 385:60] + wire ic_rd_parity_final_err = _T_2491 & _T_2493; // @[ifu_mem_ctl.scala 385:58] + reg ic_debug_ict_array_sel_ff; // @[ifu_mem_ctl.scala 769:63] reg ic_tag_valid_out_1_0; // @[Reg.scala 27:20] - wire _T_9374 = _T_4671 & ic_tag_valid_out_1_0; // @[ifu_mem_ctl.scala 689:10] + wire _T_9374 = _T_4671 & ic_tag_valid_out_1_0; // @[ifu_mem_ctl.scala 697:10] reg ic_tag_valid_out_1_1; // @[Reg.scala 27:20] - wire _T_9376 = _T_4672 & ic_tag_valid_out_1_1; // @[ifu_mem_ctl.scala 689:10] - wire _T_9629 = _T_9374 | _T_9376; // @[ifu_mem_ctl.scala 689:91] + wire _T_9376 = _T_4672 & ic_tag_valid_out_1_1; // @[ifu_mem_ctl.scala 697:10] + wire _T_9629 = _T_9374 | _T_9376; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_2; // @[Reg.scala 27:20] - wire _T_9378 = _T_4673 & ic_tag_valid_out_1_2; // @[ifu_mem_ctl.scala 689:10] - wire _T_9630 = _T_9629 | _T_9378; // @[ifu_mem_ctl.scala 689:91] + wire _T_9378 = _T_4673 & ic_tag_valid_out_1_2; // @[ifu_mem_ctl.scala 697:10] + wire _T_9630 = _T_9629 | _T_9378; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_3; // @[Reg.scala 27:20] - wire _T_9380 = _T_4674 & ic_tag_valid_out_1_3; // @[ifu_mem_ctl.scala 689:10] - wire _T_9631 = _T_9630 | _T_9380; // @[ifu_mem_ctl.scala 689:91] + wire _T_9380 = _T_4674 & ic_tag_valid_out_1_3; // @[ifu_mem_ctl.scala 697:10] + wire _T_9631 = _T_9630 | _T_9380; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_4; // @[Reg.scala 27:20] - wire _T_9382 = _T_4675 & ic_tag_valid_out_1_4; // @[ifu_mem_ctl.scala 689:10] - wire _T_9632 = _T_9631 | _T_9382; // @[ifu_mem_ctl.scala 689:91] + wire _T_9382 = _T_4675 & ic_tag_valid_out_1_4; // @[ifu_mem_ctl.scala 697:10] + wire _T_9632 = _T_9631 | _T_9382; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_5; // @[Reg.scala 27:20] - wire _T_9384 = _T_4676 & ic_tag_valid_out_1_5; // @[ifu_mem_ctl.scala 689:10] - wire _T_9633 = _T_9632 | _T_9384; // @[ifu_mem_ctl.scala 689:91] + wire _T_9384 = _T_4676 & ic_tag_valid_out_1_5; // @[ifu_mem_ctl.scala 697:10] + wire _T_9633 = _T_9632 | _T_9384; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_6; // @[Reg.scala 27:20] - wire _T_9386 = _T_4677 & ic_tag_valid_out_1_6; // @[ifu_mem_ctl.scala 689:10] - wire _T_9634 = _T_9633 | _T_9386; // @[ifu_mem_ctl.scala 689:91] + wire _T_9386 = _T_4677 & ic_tag_valid_out_1_6; // @[ifu_mem_ctl.scala 697:10] + wire _T_9634 = _T_9633 | _T_9386; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_7; // @[Reg.scala 27:20] - wire _T_9388 = _T_4678 & ic_tag_valid_out_1_7; // @[ifu_mem_ctl.scala 689:10] - wire _T_9635 = _T_9634 | _T_9388; // @[ifu_mem_ctl.scala 689:91] + wire _T_9388 = _T_4678 & ic_tag_valid_out_1_7; // @[ifu_mem_ctl.scala 697:10] + wire _T_9635 = _T_9634 | _T_9388; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_8; // @[Reg.scala 27:20] - wire _T_9390 = _T_4679 & ic_tag_valid_out_1_8; // @[ifu_mem_ctl.scala 689:10] - wire _T_9636 = _T_9635 | _T_9390; // @[ifu_mem_ctl.scala 689:91] + wire _T_9390 = _T_4679 & ic_tag_valid_out_1_8; // @[ifu_mem_ctl.scala 697:10] + wire _T_9636 = _T_9635 | _T_9390; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_9; // @[Reg.scala 27:20] - wire _T_9392 = _T_4680 & ic_tag_valid_out_1_9; // @[ifu_mem_ctl.scala 689:10] - wire _T_9637 = _T_9636 | _T_9392; // @[ifu_mem_ctl.scala 689:91] + wire _T_9392 = _T_4680 & ic_tag_valid_out_1_9; // @[ifu_mem_ctl.scala 697:10] + wire _T_9637 = _T_9636 | _T_9392; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_10; // @[Reg.scala 27:20] - wire _T_9394 = _T_4681 & ic_tag_valid_out_1_10; // @[ifu_mem_ctl.scala 689:10] - wire _T_9638 = _T_9637 | _T_9394; // @[ifu_mem_ctl.scala 689:91] + wire _T_9394 = _T_4681 & ic_tag_valid_out_1_10; // @[ifu_mem_ctl.scala 697:10] + wire _T_9638 = _T_9637 | _T_9394; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_11; // @[Reg.scala 27:20] - wire _T_9396 = _T_4682 & ic_tag_valid_out_1_11; // @[ifu_mem_ctl.scala 689:10] - wire _T_9639 = _T_9638 | _T_9396; // @[ifu_mem_ctl.scala 689:91] + wire _T_9396 = _T_4682 & ic_tag_valid_out_1_11; // @[ifu_mem_ctl.scala 697:10] + wire _T_9639 = _T_9638 | _T_9396; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_12; // @[Reg.scala 27:20] - wire _T_9398 = _T_4683 & ic_tag_valid_out_1_12; // @[ifu_mem_ctl.scala 689:10] - wire _T_9640 = _T_9639 | _T_9398; // @[ifu_mem_ctl.scala 689:91] + wire _T_9398 = _T_4683 & ic_tag_valid_out_1_12; // @[ifu_mem_ctl.scala 697:10] + wire _T_9640 = _T_9639 | _T_9398; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_13; // @[Reg.scala 27:20] - wire _T_9400 = _T_4684 & ic_tag_valid_out_1_13; // @[ifu_mem_ctl.scala 689:10] - wire _T_9641 = _T_9640 | _T_9400; // @[ifu_mem_ctl.scala 689:91] + wire _T_9400 = _T_4684 & ic_tag_valid_out_1_13; // @[ifu_mem_ctl.scala 697:10] + wire _T_9641 = _T_9640 | _T_9400; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_14; // @[Reg.scala 27:20] - wire _T_9402 = _T_4685 & ic_tag_valid_out_1_14; // @[ifu_mem_ctl.scala 689:10] - wire _T_9642 = _T_9641 | _T_9402; // @[ifu_mem_ctl.scala 689:91] + wire _T_9402 = _T_4685 & ic_tag_valid_out_1_14; // @[ifu_mem_ctl.scala 697:10] + wire _T_9642 = _T_9641 | _T_9402; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_15; // @[Reg.scala 27:20] - wire _T_9404 = _T_4686 & ic_tag_valid_out_1_15; // @[ifu_mem_ctl.scala 689:10] - wire _T_9643 = _T_9642 | _T_9404; // @[ifu_mem_ctl.scala 689:91] + wire _T_9404 = _T_4686 & ic_tag_valid_out_1_15; // @[ifu_mem_ctl.scala 697:10] + wire _T_9643 = _T_9642 | _T_9404; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_16; // @[Reg.scala 27:20] - wire _T_9406 = _T_4687 & ic_tag_valid_out_1_16; // @[ifu_mem_ctl.scala 689:10] - wire _T_9644 = _T_9643 | _T_9406; // @[ifu_mem_ctl.scala 689:91] + wire _T_9406 = _T_4687 & ic_tag_valid_out_1_16; // @[ifu_mem_ctl.scala 697:10] + wire _T_9644 = _T_9643 | _T_9406; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_17; // @[Reg.scala 27:20] - wire _T_9408 = _T_4688 & ic_tag_valid_out_1_17; // @[ifu_mem_ctl.scala 689:10] - wire _T_9645 = _T_9644 | _T_9408; // @[ifu_mem_ctl.scala 689:91] + wire _T_9408 = _T_4688 & ic_tag_valid_out_1_17; // @[ifu_mem_ctl.scala 697:10] + wire _T_9645 = _T_9644 | _T_9408; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_18; // @[Reg.scala 27:20] - wire _T_9410 = _T_4689 & ic_tag_valid_out_1_18; // @[ifu_mem_ctl.scala 689:10] - wire _T_9646 = _T_9645 | _T_9410; // @[ifu_mem_ctl.scala 689:91] + wire _T_9410 = _T_4689 & ic_tag_valid_out_1_18; // @[ifu_mem_ctl.scala 697:10] + wire _T_9646 = _T_9645 | _T_9410; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_19; // @[Reg.scala 27:20] - wire _T_9412 = _T_4690 & ic_tag_valid_out_1_19; // @[ifu_mem_ctl.scala 689:10] - wire _T_9647 = _T_9646 | _T_9412; // @[ifu_mem_ctl.scala 689:91] + wire _T_9412 = _T_4690 & ic_tag_valid_out_1_19; // @[ifu_mem_ctl.scala 697:10] + wire _T_9647 = _T_9646 | _T_9412; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_20; // @[Reg.scala 27:20] - wire _T_9414 = _T_4691 & ic_tag_valid_out_1_20; // @[ifu_mem_ctl.scala 689:10] - wire _T_9648 = _T_9647 | _T_9414; // @[ifu_mem_ctl.scala 689:91] + wire _T_9414 = _T_4691 & ic_tag_valid_out_1_20; // @[ifu_mem_ctl.scala 697:10] + wire _T_9648 = _T_9647 | _T_9414; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_21; // @[Reg.scala 27:20] - wire _T_9416 = _T_4692 & ic_tag_valid_out_1_21; // @[ifu_mem_ctl.scala 689:10] - wire _T_9649 = _T_9648 | _T_9416; // @[ifu_mem_ctl.scala 689:91] + wire _T_9416 = _T_4692 & ic_tag_valid_out_1_21; // @[ifu_mem_ctl.scala 697:10] + wire _T_9649 = _T_9648 | _T_9416; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_22; // @[Reg.scala 27:20] - wire _T_9418 = _T_4693 & ic_tag_valid_out_1_22; // @[ifu_mem_ctl.scala 689:10] - wire _T_9650 = _T_9649 | _T_9418; // @[ifu_mem_ctl.scala 689:91] + wire _T_9418 = _T_4693 & ic_tag_valid_out_1_22; // @[ifu_mem_ctl.scala 697:10] + wire _T_9650 = _T_9649 | _T_9418; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_23; // @[Reg.scala 27:20] - wire _T_9420 = _T_4694 & ic_tag_valid_out_1_23; // @[ifu_mem_ctl.scala 689:10] - wire _T_9651 = _T_9650 | _T_9420; // @[ifu_mem_ctl.scala 689:91] + wire _T_9420 = _T_4694 & ic_tag_valid_out_1_23; // @[ifu_mem_ctl.scala 697:10] + wire _T_9651 = _T_9650 | _T_9420; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_24; // @[Reg.scala 27:20] - wire _T_9422 = _T_4695 & ic_tag_valid_out_1_24; // @[ifu_mem_ctl.scala 689:10] - wire _T_9652 = _T_9651 | _T_9422; // @[ifu_mem_ctl.scala 689:91] + wire _T_9422 = _T_4695 & ic_tag_valid_out_1_24; // @[ifu_mem_ctl.scala 697:10] + wire _T_9652 = _T_9651 | _T_9422; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_25; // @[Reg.scala 27:20] - wire _T_9424 = _T_4696 & ic_tag_valid_out_1_25; // @[ifu_mem_ctl.scala 689:10] - wire _T_9653 = _T_9652 | _T_9424; // @[ifu_mem_ctl.scala 689:91] + wire _T_9424 = _T_4696 & ic_tag_valid_out_1_25; // @[ifu_mem_ctl.scala 697:10] + wire _T_9653 = _T_9652 | _T_9424; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_26; // @[Reg.scala 27:20] - wire _T_9426 = _T_4697 & ic_tag_valid_out_1_26; // @[ifu_mem_ctl.scala 689:10] - wire _T_9654 = _T_9653 | _T_9426; // @[ifu_mem_ctl.scala 689:91] + wire _T_9426 = _T_4697 & ic_tag_valid_out_1_26; // @[ifu_mem_ctl.scala 697:10] + wire _T_9654 = _T_9653 | _T_9426; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_27; // @[Reg.scala 27:20] - wire _T_9428 = _T_4698 & ic_tag_valid_out_1_27; // @[ifu_mem_ctl.scala 689:10] - wire _T_9655 = _T_9654 | _T_9428; // @[ifu_mem_ctl.scala 689:91] + wire _T_9428 = _T_4698 & ic_tag_valid_out_1_27; // @[ifu_mem_ctl.scala 697:10] + wire _T_9655 = _T_9654 | _T_9428; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_28; // @[Reg.scala 27:20] - wire _T_9430 = _T_4699 & ic_tag_valid_out_1_28; // @[ifu_mem_ctl.scala 689:10] - wire _T_9656 = _T_9655 | _T_9430; // @[ifu_mem_ctl.scala 689:91] + wire _T_9430 = _T_4699 & ic_tag_valid_out_1_28; // @[ifu_mem_ctl.scala 697:10] + wire _T_9656 = _T_9655 | _T_9430; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_29; // @[Reg.scala 27:20] - wire _T_9432 = _T_4700 & ic_tag_valid_out_1_29; // @[ifu_mem_ctl.scala 689:10] - wire _T_9657 = _T_9656 | _T_9432; // @[ifu_mem_ctl.scala 689:91] + wire _T_9432 = _T_4700 & ic_tag_valid_out_1_29; // @[ifu_mem_ctl.scala 697:10] + wire _T_9657 = _T_9656 | _T_9432; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_30; // @[Reg.scala 27:20] - wire _T_9434 = _T_4701 & ic_tag_valid_out_1_30; // @[ifu_mem_ctl.scala 689:10] - wire _T_9658 = _T_9657 | _T_9434; // @[ifu_mem_ctl.scala 689:91] + wire _T_9434 = _T_4701 & ic_tag_valid_out_1_30; // @[ifu_mem_ctl.scala 697:10] + wire _T_9658 = _T_9657 | _T_9434; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_31; // @[Reg.scala 27:20] - wire _T_9436 = _T_4702 & ic_tag_valid_out_1_31; // @[ifu_mem_ctl.scala 689:10] - wire _T_9659 = _T_9658 | _T_9436; // @[ifu_mem_ctl.scala 689:91] + wire _T_9436 = _T_4702 & ic_tag_valid_out_1_31; // @[ifu_mem_ctl.scala 697:10] + wire _T_9659 = _T_9658 | _T_9436; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_32; // @[Reg.scala 27:20] - wire _T_9438 = _T_4703 & ic_tag_valid_out_1_32; // @[ifu_mem_ctl.scala 689:10] - wire _T_9660 = _T_9659 | _T_9438; // @[ifu_mem_ctl.scala 689:91] + wire _T_9438 = _T_4703 & ic_tag_valid_out_1_32; // @[ifu_mem_ctl.scala 697:10] + wire _T_9660 = _T_9659 | _T_9438; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_33; // @[Reg.scala 27:20] - wire _T_9440 = _T_4704 & ic_tag_valid_out_1_33; // @[ifu_mem_ctl.scala 689:10] - wire _T_9661 = _T_9660 | _T_9440; // @[ifu_mem_ctl.scala 689:91] + wire _T_9440 = _T_4704 & ic_tag_valid_out_1_33; // @[ifu_mem_ctl.scala 697:10] + wire _T_9661 = _T_9660 | _T_9440; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_34; // @[Reg.scala 27:20] - wire _T_9442 = _T_4705 & ic_tag_valid_out_1_34; // @[ifu_mem_ctl.scala 689:10] - wire _T_9662 = _T_9661 | _T_9442; // @[ifu_mem_ctl.scala 689:91] + wire _T_9442 = _T_4705 & ic_tag_valid_out_1_34; // @[ifu_mem_ctl.scala 697:10] + wire _T_9662 = _T_9661 | _T_9442; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_35; // @[Reg.scala 27:20] - wire _T_9444 = _T_4706 & ic_tag_valid_out_1_35; // @[ifu_mem_ctl.scala 689:10] - wire _T_9663 = _T_9662 | _T_9444; // @[ifu_mem_ctl.scala 689:91] + wire _T_9444 = _T_4706 & ic_tag_valid_out_1_35; // @[ifu_mem_ctl.scala 697:10] + wire _T_9663 = _T_9662 | _T_9444; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_36; // @[Reg.scala 27:20] - wire _T_9446 = _T_4707 & ic_tag_valid_out_1_36; // @[ifu_mem_ctl.scala 689:10] - wire _T_9664 = _T_9663 | _T_9446; // @[ifu_mem_ctl.scala 689:91] + wire _T_9446 = _T_4707 & ic_tag_valid_out_1_36; // @[ifu_mem_ctl.scala 697:10] + wire _T_9664 = _T_9663 | _T_9446; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_37; // @[Reg.scala 27:20] - wire _T_9448 = _T_4708 & ic_tag_valid_out_1_37; // @[ifu_mem_ctl.scala 689:10] - wire _T_9665 = _T_9664 | _T_9448; // @[ifu_mem_ctl.scala 689:91] + wire _T_9448 = _T_4708 & ic_tag_valid_out_1_37; // @[ifu_mem_ctl.scala 697:10] + wire _T_9665 = _T_9664 | _T_9448; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_38; // @[Reg.scala 27:20] - wire _T_9450 = _T_4709 & ic_tag_valid_out_1_38; // @[ifu_mem_ctl.scala 689:10] - wire _T_9666 = _T_9665 | _T_9450; // @[ifu_mem_ctl.scala 689:91] + wire _T_9450 = _T_4709 & ic_tag_valid_out_1_38; // @[ifu_mem_ctl.scala 697:10] + wire _T_9666 = _T_9665 | _T_9450; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_39; // @[Reg.scala 27:20] - wire _T_9452 = _T_4710 & ic_tag_valid_out_1_39; // @[ifu_mem_ctl.scala 689:10] - wire _T_9667 = _T_9666 | _T_9452; // @[ifu_mem_ctl.scala 689:91] + wire _T_9452 = _T_4710 & ic_tag_valid_out_1_39; // @[ifu_mem_ctl.scala 697:10] + wire _T_9667 = _T_9666 | _T_9452; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_40; // @[Reg.scala 27:20] - wire _T_9454 = _T_4711 & ic_tag_valid_out_1_40; // @[ifu_mem_ctl.scala 689:10] - wire _T_9668 = _T_9667 | _T_9454; // @[ifu_mem_ctl.scala 689:91] + wire _T_9454 = _T_4711 & ic_tag_valid_out_1_40; // @[ifu_mem_ctl.scala 697:10] + wire _T_9668 = _T_9667 | _T_9454; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_41; // @[Reg.scala 27:20] - wire _T_9456 = _T_4712 & ic_tag_valid_out_1_41; // @[ifu_mem_ctl.scala 689:10] - wire _T_9669 = _T_9668 | _T_9456; // @[ifu_mem_ctl.scala 689:91] + wire _T_9456 = _T_4712 & ic_tag_valid_out_1_41; // @[ifu_mem_ctl.scala 697:10] + wire _T_9669 = _T_9668 | _T_9456; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_42; // @[Reg.scala 27:20] - wire _T_9458 = _T_4713 & ic_tag_valid_out_1_42; // @[ifu_mem_ctl.scala 689:10] - wire _T_9670 = _T_9669 | _T_9458; // @[ifu_mem_ctl.scala 689:91] + wire _T_9458 = _T_4713 & ic_tag_valid_out_1_42; // @[ifu_mem_ctl.scala 697:10] + wire _T_9670 = _T_9669 | _T_9458; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_43; // @[Reg.scala 27:20] - wire _T_9460 = _T_4714 & ic_tag_valid_out_1_43; // @[ifu_mem_ctl.scala 689:10] - wire _T_9671 = _T_9670 | _T_9460; // @[ifu_mem_ctl.scala 689:91] + wire _T_9460 = _T_4714 & ic_tag_valid_out_1_43; // @[ifu_mem_ctl.scala 697:10] + wire _T_9671 = _T_9670 | _T_9460; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_44; // @[Reg.scala 27:20] - wire _T_9462 = _T_4715 & ic_tag_valid_out_1_44; // @[ifu_mem_ctl.scala 689:10] - wire _T_9672 = _T_9671 | _T_9462; // @[ifu_mem_ctl.scala 689:91] + wire _T_9462 = _T_4715 & ic_tag_valid_out_1_44; // @[ifu_mem_ctl.scala 697:10] + wire _T_9672 = _T_9671 | _T_9462; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_45; // @[Reg.scala 27:20] - wire _T_9464 = _T_4716 & ic_tag_valid_out_1_45; // @[ifu_mem_ctl.scala 689:10] - wire _T_9673 = _T_9672 | _T_9464; // @[ifu_mem_ctl.scala 689:91] + wire _T_9464 = _T_4716 & ic_tag_valid_out_1_45; // @[ifu_mem_ctl.scala 697:10] + wire _T_9673 = _T_9672 | _T_9464; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_46; // @[Reg.scala 27:20] - wire _T_9466 = _T_4717 & ic_tag_valid_out_1_46; // @[ifu_mem_ctl.scala 689:10] - wire _T_9674 = _T_9673 | _T_9466; // @[ifu_mem_ctl.scala 689:91] + wire _T_9466 = _T_4717 & ic_tag_valid_out_1_46; // @[ifu_mem_ctl.scala 697:10] + wire _T_9674 = _T_9673 | _T_9466; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_47; // @[Reg.scala 27:20] - wire _T_9468 = _T_4718 & ic_tag_valid_out_1_47; // @[ifu_mem_ctl.scala 689:10] - wire _T_9675 = _T_9674 | _T_9468; // @[ifu_mem_ctl.scala 689:91] + wire _T_9468 = _T_4718 & ic_tag_valid_out_1_47; // @[ifu_mem_ctl.scala 697:10] + wire _T_9675 = _T_9674 | _T_9468; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_48; // @[Reg.scala 27:20] - wire _T_9470 = _T_4719 & ic_tag_valid_out_1_48; // @[ifu_mem_ctl.scala 689:10] - wire _T_9676 = _T_9675 | _T_9470; // @[ifu_mem_ctl.scala 689:91] + wire _T_9470 = _T_4719 & ic_tag_valid_out_1_48; // @[ifu_mem_ctl.scala 697:10] + wire _T_9676 = _T_9675 | _T_9470; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_49; // @[Reg.scala 27:20] - wire _T_9472 = _T_4720 & ic_tag_valid_out_1_49; // @[ifu_mem_ctl.scala 689:10] - wire _T_9677 = _T_9676 | _T_9472; // @[ifu_mem_ctl.scala 689:91] + wire _T_9472 = _T_4720 & ic_tag_valid_out_1_49; // @[ifu_mem_ctl.scala 697:10] + wire _T_9677 = _T_9676 | _T_9472; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_50; // @[Reg.scala 27:20] - wire _T_9474 = _T_4721 & ic_tag_valid_out_1_50; // @[ifu_mem_ctl.scala 689:10] - wire _T_9678 = _T_9677 | _T_9474; // @[ifu_mem_ctl.scala 689:91] + wire _T_9474 = _T_4721 & ic_tag_valid_out_1_50; // @[ifu_mem_ctl.scala 697:10] + wire _T_9678 = _T_9677 | _T_9474; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_51; // @[Reg.scala 27:20] - wire _T_9476 = _T_4722 & ic_tag_valid_out_1_51; // @[ifu_mem_ctl.scala 689:10] - wire _T_9679 = _T_9678 | _T_9476; // @[ifu_mem_ctl.scala 689:91] + wire _T_9476 = _T_4722 & ic_tag_valid_out_1_51; // @[ifu_mem_ctl.scala 697:10] + wire _T_9679 = _T_9678 | _T_9476; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_52; // @[Reg.scala 27:20] - wire _T_9478 = _T_4723 & ic_tag_valid_out_1_52; // @[ifu_mem_ctl.scala 689:10] - wire _T_9680 = _T_9679 | _T_9478; // @[ifu_mem_ctl.scala 689:91] + wire _T_9478 = _T_4723 & ic_tag_valid_out_1_52; // @[ifu_mem_ctl.scala 697:10] + wire _T_9680 = _T_9679 | _T_9478; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_53; // @[Reg.scala 27:20] - wire _T_9480 = _T_4724 & ic_tag_valid_out_1_53; // @[ifu_mem_ctl.scala 689:10] - wire _T_9681 = _T_9680 | _T_9480; // @[ifu_mem_ctl.scala 689:91] + wire _T_9480 = _T_4724 & ic_tag_valid_out_1_53; // @[ifu_mem_ctl.scala 697:10] + wire _T_9681 = _T_9680 | _T_9480; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_54; // @[Reg.scala 27:20] - wire _T_9482 = _T_4725 & ic_tag_valid_out_1_54; // @[ifu_mem_ctl.scala 689:10] - wire _T_9682 = _T_9681 | _T_9482; // @[ifu_mem_ctl.scala 689:91] + wire _T_9482 = _T_4725 & ic_tag_valid_out_1_54; // @[ifu_mem_ctl.scala 697:10] + wire _T_9682 = _T_9681 | _T_9482; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_55; // @[Reg.scala 27:20] - wire _T_9484 = _T_4726 & ic_tag_valid_out_1_55; // @[ifu_mem_ctl.scala 689:10] - wire _T_9683 = _T_9682 | _T_9484; // @[ifu_mem_ctl.scala 689:91] + wire _T_9484 = _T_4726 & ic_tag_valid_out_1_55; // @[ifu_mem_ctl.scala 697:10] + wire _T_9683 = _T_9682 | _T_9484; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_56; // @[Reg.scala 27:20] - wire _T_9486 = _T_4727 & ic_tag_valid_out_1_56; // @[ifu_mem_ctl.scala 689:10] - wire _T_9684 = _T_9683 | _T_9486; // @[ifu_mem_ctl.scala 689:91] + wire _T_9486 = _T_4727 & ic_tag_valid_out_1_56; // @[ifu_mem_ctl.scala 697:10] + wire _T_9684 = _T_9683 | _T_9486; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_57; // @[Reg.scala 27:20] - wire _T_9488 = _T_4728 & ic_tag_valid_out_1_57; // @[ifu_mem_ctl.scala 689:10] - wire _T_9685 = _T_9684 | _T_9488; // @[ifu_mem_ctl.scala 689:91] + wire _T_9488 = _T_4728 & ic_tag_valid_out_1_57; // @[ifu_mem_ctl.scala 697:10] + wire _T_9685 = _T_9684 | _T_9488; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_58; // @[Reg.scala 27:20] - wire _T_9490 = _T_4729 & ic_tag_valid_out_1_58; // @[ifu_mem_ctl.scala 689:10] - wire _T_9686 = _T_9685 | _T_9490; // @[ifu_mem_ctl.scala 689:91] + wire _T_9490 = _T_4729 & ic_tag_valid_out_1_58; // @[ifu_mem_ctl.scala 697:10] + wire _T_9686 = _T_9685 | _T_9490; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_59; // @[Reg.scala 27:20] - wire _T_9492 = _T_4730 & ic_tag_valid_out_1_59; // @[ifu_mem_ctl.scala 689:10] - wire _T_9687 = _T_9686 | _T_9492; // @[ifu_mem_ctl.scala 689:91] + wire _T_9492 = _T_4730 & ic_tag_valid_out_1_59; // @[ifu_mem_ctl.scala 697:10] + wire _T_9687 = _T_9686 | _T_9492; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_60; // @[Reg.scala 27:20] - wire _T_9494 = _T_4731 & ic_tag_valid_out_1_60; // @[ifu_mem_ctl.scala 689:10] - wire _T_9688 = _T_9687 | _T_9494; // @[ifu_mem_ctl.scala 689:91] + wire _T_9494 = _T_4731 & ic_tag_valid_out_1_60; // @[ifu_mem_ctl.scala 697:10] + wire _T_9688 = _T_9687 | _T_9494; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_61; // @[Reg.scala 27:20] - wire _T_9496 = _T_4732 & ic_tag_valid_out_1_61; // @[ifu_mem_ctl.scala 689:10] - wire _T_9689 = _T_9688 | _T_9496; // @[ifu_mem_ctl.scala 689:91] + wire _T_9496 = _T_4732 & ic_tag_valid_out_1_61; // @[ifu_mem_ctl.scala 697:10] + wire _T_9689 = _T_9688 | _T_9496; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_62; // @[Reg.scala 27:20] - wire _T_9498 = _T_4733 & ic_tag_valid_out_1_62; // @[ifu_mem_ctl.scala 689:10] - wire _T_9690 = _T_9689 | _T_9498; // @[ifu_mem_ctl.scala 689:91] + wire _T_9498 = _T_4733 & ic_tag_valid_out_1_62; // @[ifu_mem_ctl.scala 697:10] + wire _T_9690 = _T_9689 | _T_9498; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_63; // @[Reg.scala 27:20] - wire _T_9500 = _T_4734 & ic_tag_valid_out_1_63; // @[ifu_mem_ctl.scala 689:10] - wire _T_9691 = _T_9690 | _T_9500; // @[ifu_mem_ctl.scala 689:91] + wire _T_9500 = _T_4734 & ic_tag_valid_out_1_63; // @[ifu_mem_ctl.scala 697:10] + wire _T_9691 = _T_9690 | _T_9500; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_64; // @[Reg.scala 27:20] - wire _T_9502 = _T_4735 & ic_tag_valid_out_1_64; // @[ifu_mem_ctl.scala 689:10] - wire _T_9692 = _T_9691 | _T_9502; // @[ifu_mem_ctl.scala 689:91] + wire _T_9502 = _T_4735 & ic_tag_valid_out_1_64; // @[ifu_mem_ctl.scala 697:10] + wire _T_9692 = _T_9691 | _T_9502; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_65; // @[Reg.scala 27:20] - wire _T_9504 = _T_4736 & ic_tag_valid_out_1_65; // @[ifu_mem_ctl.scala 689:10] - wire _T_9693 = _T_9692 | _T_9504; // @[ifu_mem_ctl.scala 689:91] + wire _T_9504 = _T_4736 & ic_tag_valid_out_1_65; // @[ifu_mem_ctl.scala 697:10] + wire _T_9693 = _T_9692 | _T_9504; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_66; // @[Reg.scala 27:20] - wire _T_9506 = _T_4737 & ic_tag_valid_out_1_66; // @[ifu_mem_ctl.scala 689:10] - wire _T_9694 = _T_9693 | _T_9506; // @[ifu_mem_ctl.scala 689:91] + wire _T_9506 = _T_4737 & ic_tag_valid_out_1_66; // @[ifu_mem_ctl.scala 697:10] + wire _T_9694 = _T_9693 | _T_9506; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_67; // @[Reg.scala 27:20] - wire _T_9508 = _T_4738 & ic_tag_valid_out_1_67; // @[ifu_mem_ctl.scala 689:10] - wire _T_9695 = _T_9694 | _T_9508; // @[ifu_mem_ctl.scala 689:91] + wire _T_9508 = _T_4738 & ic_tag_valid_out_1_67; // @[ifu_mem_ctl.scala 697:10] + wire _T_9695 = _T_9694 | _T_9508; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_68; // @[Reg.scala 27:20] - wire _T_9510 = _T_4739 & ic_tag_valid_out_1_68; // @[ifu_mem_ctl.scala 689:10] - wire _T_9696 = _T_9695 | _T_9510; // @[ifu_mem_ctl.scala 689:91] + wire _T_9510 = _T_4739 & ic_tag_valid_out_1_68; // @[ifu_mem_ctl.scala 697:10] + wire _T_9696 = _T_9695 | _T_9510; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_69; // @[Reg.scala 27:20] - wire _T_9512 = _T_4740 & ic_tag_valid_out_1_69; // @[ifu_mem_ctl.scala 689:10] - wire _T_9697 = _T_9696 | _T_9512; // @[ifu_mem_ctl.scala 689:91] + wire _T_9512 = _T_4740 & ic_tag_valid_out_1_69; // @[ifu_mem_ctl.scala 697:10] + wire _T_9697 = _T_9696 | _T_9512; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_70; // @[Reg.scala 27:20] - wire _T_9514 = _T_4741 & ic_tag_valid_out_1_70; // @[ifu_mem_ctl.scala 689:10] - wire _T_9698 = _T_9697 | _T_9514; // @[ifu_mem_ctl.scala 689:91] + wire _T_9514 = _T_4741 & ic_tag_valid_out_1_70; // @[ifu_mem_ctl.scala 697:10] + wire _T_9698 = _T_9697 | _T_9514; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_71; // @[Reg.scala 27:20] - wire _T_9516 = _T_4742 & ic_tag_valid_out_1_71; // @[ifu_mem_ctl.scala 689:10] - wire _T_9699 = _T_9698 | _T_9516; // @[ifu_mem_ctl.scala 689:91] + wire _T_9516 = _T_4742 & ic_tag_valid_out_1_71; // @[ifu_mem_ctl.scala 697:10] + wire _T_9699 = _T_9698 | _T_9516; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_72; // @[Reg.scala 27:20] - wire _T_9518 = _T_4743 & ic_tag_valid_out_1_72; // @[ifu_mem_ctl.scala 689:10] - wire _T_9700 = _T_9699 | _T_9518; // @[ifu_mem_ctl.scala 689:91] + wire _T_9518 = _T_4743 & ic_tag_valid_out_1_72; // @[ifu_mem_ctl.scala 697:10] + wire _T_9700 = _T_9699 | _T_9518; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_73; // @[Reg.scala 27:20] - wire _T_9520 = _T_4744 & ic_tag_valid_out_1_73; // @[ifu_mem_ctl.scala 689:10] - wire _T_9701 = _T_9700 | _T_9520; // @[ifu_mem_ctl.scala 689:91] + wire _T_9520 = _T_4744 & ic_tag_valid_out_1_73; // @[ifu_mem_ctl.scala 697:10] + wire _T_9701 = _T_9700 | _T_9520; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_74; // @[Reg.scala 27:20] - wire _T_9522 = _T_4745 & ic_tag_valid_out_1_74; // @[ifu_mem_ctl.scala 689:10] - wire _T_9702 = _T_9701 | _T_9522; // @[ifu_mem_ctl.scala 689:91] + wire _T_9522 = _T_4745 & ic_tag_valid_out_1_74; // @[ifu_mem_ctl.scala 697:10] + wire _T_9702 = _T_9701 | _T_9522; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_75; // @[Reg.scala 27:20] - wire _T_9524 = _T_4746 & ic_tag_valid_out_1_75; // @[ifu_mem_ctl.scala 689:10] - wire _T_9703 = _T_9702 | _T_9524; // @[ifu_mem_ctl.scala 689:91] + wire _T_9524 = _T_4746 & ic_tag_valid_out_1_75; // @[ifu_mem_ctl.scala 697:10] + wire _T_9703 = _T_9702 | _T_9524; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_76; // @[Reg.scala 27:20] - wire _T_9526 = _T_4747 & ic_tag_valid_out_1_76; // @[ifu_mem_ctl.scala 689:10] - wire _T_9704 = _T_9703 | _T_9526; // @[ifu_mem_ctl.scala 689:91] + wire _T_9526 = _T_4747 & ic_tag_valid_out_1_76; // @[ifu_mem_ctl.scala 697:10] + wire _T_9704 = _T_9703 | _T_9526; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_77; // @[Reg.scala 27:20] - wire _T_9528 = _T_4748 & ic_tag_valid_out_1_77; // @[ifu_mem_ctl.scala 689:10] - wire _T_9705 = _T_9704 | _T_9528; // @[ifu_mem_ctl.scala 689:91] + wire _T_9528 = _T_4748 & ic_tag_valid_out_1_77; // @[ifu_mem_ctl.scala 697:10] + wire _T_9705 = _T_9704 | _T_9528; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_78; // @[Reg.scala 27:20] - wire _T_9530 = _T_4749 & ic_tag_valid_out_1_78; // @[ifu_mem_ctl.scala 689:10] - wire _T_9706 = _T_9705 | _T_9530; // @[ifu_mem_ctl.scala 689:91] + wire _T_9530 = _T_4749 & ic_tag_valid_out_1_78; // @[ifu_mem_ctl.scala 697:10] + wire _T_9706 = _T_9705 | _T_9530; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_79; // @[Reg.scala 27:20] - wire _T_9532 = _T_4750 & ic_tag_valid_out_1_79; // @[ifu_mem_ctl.scala 689:10] - wire _T_9707 = _T_9706 | _T_9532; // @[ifu_mem_ctl.scala 689:91] + wire _T_9532 = _T_4750 & ic_tag_valid_out_1_79; // @[ifu_mem_ctl.scala 697:10] + wire _T_9707 = _T_9706 | _T_9532; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_80; // @[Reg.scala 27:20] - wire _T_9534 = _T_4751 & ic_tag_valid_out_1_80; // @[ifu_mem_ctl.scala 689:10] - wire _T_9708 = _T_9707 | _T_9534; // @[ifu_mem_ctl.scala 689:91] + wire _T_9534 = _T_4751 & ic_tag_valid_out_1_80; // @[ifu_mem_ctl.scala 697:10] + wire _T_9708 = _T_9707 | _T_9534; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_81; // @[Reg.scala 27:20] - wire _T_9536 = _T_4752 & ic_tag_valid_out_1_81; // @[ifu_mem_ctl.scala 689:10] - wire _T_9709 = _T_9708 | _T_9536; // @[ifu_mem_ctl.scala 689:91] + wire _T_9536 = _T_4752 & ic_tag_valid_out_1_81; // @[ifu_mem_ctl.scala 697:10] + wire _T_9709 = _T_9708 | _T_9536; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_82; // @[Reg.scala 27:20] - wire _T_9538 = _T_4753 & ic_tag_valid_out_1_82; // @[ifu_mem_ctl.scala 689:10] - wire _T_9710 = _T_9709 | _T_9538; // @[ifu_mem_ctl.scala 689:91] + wire _T_9538 = _T_4753 & ic_tag_valid_out_1_82; // @[ifu_mem_ctl.scala 697:10] + wire _T_9710 = _T_9709 | _T_9538; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_83; // @[Reg.scala 27:20] - wire _T_9540 = _T_4754 & ic_tag_valid_out_1_83; // @[ifu_mem_ctl.scala 689:10] - wire _T_9711 = _T_9710 | _T_9540; // @[ifu_mem_ctl.scala 689:91] + wire _T_9540 = _T_4754 & ic_tag_valid_out_1_83; // @[ifu_mem_ctl.scala 697:10] + wire _T_9711 = _T_9710 | _T_9540; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_84; // @[Reg.scala 27:20] - wire _T_9542 = _T_4755 & ic_tag_valid_out_1_84; // @[ifu_mem_ctl.scala 689:10] - wire _T_9712 = _T_9711 | _T_9542; // @[ifu_mem_ctl.scala 689:91] + wire _T_9542 = _T_4755 & ic_tag_valid_out_1_84; // @[ifu_mem_ctl.scala 697:10] + wire _T_9712 = _T_9711 | _T_9542; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_85; // @[Reg.scala 27:20] - wire _T_9544 = _T_4756 & ic_tag_valid_out_1_85; // @[ifu_mem_ctl.scala 689:10] - wire _T_9713 = _T_9712 | _T_9544; // @[ifu_mem_ctl.scala 689:91] + wire _T_9544 = _T_4756 & ic_tag_valid_out_1_85; // @[ifu_mem_ctl.scala 697:10] + wire _T_9713 = _T_9712 | _T_9544; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_86; // @[Reg.scala 27:20] - wire _T_9546 = _T_4757 & ic_tag_valid_out_1_86; // @[ifu_mem_ctl.scala 689:10] - wire _T_9714 = _T_9713 | _T_9546; // @[ifu_mem_ctl.scala 689:91] + wire _T_9546 = _T_4757 & ic_tag_valid_out_1_86; // @[ifu_mem_ctl.scala 697:10] + wire _T_9714 = _T_9713 | _T_9546; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_87; // @[Reg.scala 27:20] - wire _T_9548 = _T_4758 & ic_tag_valid_out_1_87; // @[ifu_mem_ctl.scala 689:10] - wire _T_9715 = _T_9714 | _T_9548; // @[ifu_mem_ctl.scala 689:91] + wire _T_9548 = _T_4758 & ic_tag_valid_out_1_87; // @[ifu_mem_ctl.scala 697:10] + wire _T_9715 = _T_9714 | _T_9548; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_88; // @[Reg.scala 27:20] - wire _T_9550 = _T_4759 & ic_tag_valid_out_1_88; // @[ifu_mem_ctl.scala 689:10] - wire _T_9716 = _T_9715 | _T_9550; // @[ifu_mem_ctl.scala 689:91] + wire _T_9550 = _T_4759 & ic_tag_valid_out_1_88; // @[ifu_mem_ctl.scala 697:10] + wire _T_9716 = _T_9715 | _T_9550; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_89; // @[Reg.scala 27:20] - wire _T_9552 = _T_4760 & ic_tag_valid_out_1_89; // @[ifu_mem_ctl.scala 689:10] - wire _T_9717 = _T_9716 | _T_9552; // @[ifu_mem_ctl.scala 689:91] + wire _T_9552 = _T_4760 & ic_tag_valid_out_1_89; // @[ifu_mem_ctl.scala 697:10] + wire _T_9717 = _T_9716 | _T_9552; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_90; // @[Reg.scala 27:20] - wire _T_9554 = _T_4761 & ic_tag_valid_out_1_90; // @[ifu_mem_ctl.scala 689:10] - wire _T_9718 = _T_9717 | _T_9554; // @[ifu_mem_ctl.scala 689:91] + wire _T_9554 = _T_4761 & ic_tag_valid_out_1_90; // @[ifu_mem_ctl.scala 697:10] + wire _T_9718 = _T_9717 | _T_9554; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_91; // @[Reg.scala 27:20] - wire _T_9556 = _T_4762 & ic_tag_valid_out_1_91; // @[ifu_mem_ctl.scala 689:10] - wire _T_9719 = _T_9718 | _T_9556; // @[ifu_mem_ctl.scala 689:91] + wire _T_9556 = _T_4762 & ic_tag_valid_out_1_91; // @[ifu_mem_ctl.scala 697:10] + wire _T_9719 = _T_9718 | _T_9556; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_92; // @[Reg.scala 27:20] - wire _T_9558 = _T_4763 & ic_tag_valid_out_1_92; // @[ifu_mem_ctl.scala 689:10] - wire _T_9720 = _T_9719 | _T_9558; // @[ifu_mem_ctl.scala 689:91] + wire _T_9558 = _T_4763 & ic_tag_valid_out_1_92; // @[ifu_mem_ctl.scala 697:10] + wire _T_9720 = _T_9719 | _T_9558; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_93; // @[Reg.scala 27:20] - wire _T_9560 = _T_4764 & ic_tag_valid_out_1_93; // @[ifu_mem_ctl.scala 689:10] - wire _T_9721 = _T_9720 | _T_9560; // @[ifu_mem_ctl.scala 689:91] + wire _T_9560 = _T_4764 & ic_tag_valid_out_1_93; // @[ifu_mem_ctl.scala 697:10] + wire _T_9721 = _T_9720 | _T_9560; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_94; // @[Reg.scala 27:20] - wire _T_9562 = _T_4765 & ic_tag_valid_out_1_94; // @[ifu_mem_ctl.scala 689:10] - wire _T_9722 = _T_9721 | _T_9562; // @[ifu_mem_ctl.scala 689:91] + wire _T_9562 = _T_4765 & ic_tag_valid_out_1_94; // @[ifu_mem_ctl.scala 697:10] + wire _T_9722 = _T_9721 | _T_9562; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_95; // @[Reg.scala 27:20] - wire _T_9564 = _T_4766 & ic_tag_valid_out_1_95; // @[ifu_mem_ctl.scala 689:10] - wire _T_9723 = _T_9722 | _T_9564; // @[ifu_mem_ctl.scala 689:91] + wire _T_9564 = _T_4766 & ic_tag_valid_out_1_95; // @[ifu_mem_ctl.scala 697:10] + wire _T_9723 = _T_9722 | _T_9564; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_96; // @[Reg.scala 27:20] - wire _T_9566 = _T_4767 & ic_tag_valid_out_1_96; // @[ifu_mem_ctl.scala 689:10] - wire _T_9724 = _T_9723 | _T_9566; // @[ifu_mem_ctl.scala 689:91] + wire _T_9566 = _T_4767 & ic_tag_valid_out_1_96; // @[ifu_mem_ctl.scala 697:10] + wire _T_9724 = _T_9723 | _T_9566; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_97; // @[Reg.scala 27:20] - wire _T_9568 = _T_4768 & ic_tag_valid_out_1_97; // @[ifu_mem_ctl.scala 689:10] - wire _T_9725 = _T_9724 | _T_9568; // @[ifu_mem_ctl.scala 689:91] + wire _T_9568 = _T_4768 & ic_tag_valid_out_1_97; // @[ifu_mem_ctl.scala 697:10] + wire _T_9725 = _T_9724 | _T_9568; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_98; // @[Reg.scala 27:20] - wire _T_9570 = _T_4769 & ic_tag_valid_out_1_98; // @[ifu_mem_ctl.scala 689:10] - wire _T_9726 = _T_9725 | _T_9570; // @[ifu_mem_ctl.scala 689:91] + wire _T_9570 = _T_4769 & ic_tag_valid_out_1_98; // @[ifu_mem_ctl.scala 697:10] + wire _T_9726 = _T_9725 | _T_9570; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_99; // @[Reg.scala 27:20] - wire _T_9572 = _T_4770 & ic_tag_valid_out_1_99; // @[ifu_mem_ctl.scala 689:10] - wire _T_9727 = _T_9726 | _T_9572; // @[ifu_mem_ctl.scala 689:91] + wire _T_9572 = _T_4770 & ic_tag_valid_out_1_99; // @[ifu_mem_ctl.scala 697:10] + wire _T_9727 = _T_9726 | _T_9572; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_100; // @[Reg.scala 27:20] - wire _T_9574 = _T_4771 & ic_tag_valid_out_1_100; // @[ifu_mem_ctl.scala 689:10] - wire _T_9728 = _T_9727 | _T_9574; // @[ifu_mem_ctl.scala 689:91] + wire _T_9574 = _T_4771 & ic_tag_valid_out_1_100; // @[ifu_mem_ctl.scala 697:10] + wire _T_9728 = _T_9727 | _T_9574; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_101; // @[Reg.scala 27:20] - wire _T_9576 = _T_4772 & ic_tag_valid_out_1_101; // @[ifu_mem_ctl.scala 689:10] - wire _T_9729 = _T_9728 | _T_9576; // @[ifu_mem_ctl.scala 689:91] + wire _T_9576 = _T_4772 & ic_tag_valid_out_1_101; // @[ifu_mem_ctl.scala 697:10] + wire _T_9729 = _T_9728 | _T_9576; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_102; // @[Reg.scala 27:20] - wire _T_9578 = _T_4773 & ic_tag_valid_out_1_102; // @[ifu_mem_ctl.scala 689:10] - wire _T_9730 = _T_9729 | _T_9578; // @[ifu_mem_ctl.scala 689:91] + wire _T_9578 = _T_4773 & ic_tag_valid_out_1_102; // @[ifu_mem_ctl.scala 697:10] + wire _T_9730 = _T_9729 | _T_9578; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_103; // @[Reg.scala 27:20] - wire _T_9580 = _T_4774 & ic_tag_valid_out_1_103; // @[ifu_mem_ctl.scala 689:10] - wire _T_9731 = _T_9730 | _T_9580; // @[ifu_mem_ctl.scala 689:91] + wire _T_9580 = _T_4774 & ic_tag_valid_out_1_103; // @[ifu_mem_ctl.scala 697:10] + wire _T_9731 = _T_9730 | _T_9580; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_104; // @[Reg.scala 27:20] - wire _T_9582 = _T_4775 & ic_tag_valid_out_1_104; // @[ifu_mem_ctl.scala 689:10] - wire _T_9732 = _T_9731 | _T_9582; // @[ifu_mem_ctl.scala 689:91] + wire _T_9582 = _T_4775 & ic_tag_valid_out_1_104; // @[ifu_mem_ctl.scala 697:10] + wire _T_9732 = _T_9731 | _T_9582; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_105; // @[Reg.scala 27:20] - wire _T_9584 = _T_4776 & ic_tag_valid_out_1_105; // @[ifu_mem_ctl.scala 689:10] - wire _T_9733 = _T_9732 | _T_9584; // @[ifu_mem_ctl.scala 689:91] + wire _T_9584 = _T_4776 & ic_tag_valid_out_1_105; // @[ifu_mem_ctl.scala 697:10] + wire _T_9733 = _T_9732 | _T_9584; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_106; // @[Reg.scala 27:20] - wire _T_9586 = _T_4777 & ic_tag_valid_out_1_106; // @[ifu_mem_ctl.scala 689:10] - wire _T_9734 = _T_9733 | _T_9586; // @[ifu_mem_ctl.scala 689:91] + wire _T_9586 = _T_4777 & ic_tag_valid_out_1_106; // @[ifu_mem_ctl.scala 697:10] + wire _T_9734 = _T_9733 | _T_9586; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_107; // @[Reg.scala 27:20] - wire _T_9588 = _T_4778 & ic_tag_valid_out_1_107; // @[ifu_mem_ctl.scala 689:10] - wire _T_9735 = _T_9734 | _T_9588; // @[ifu_mem_ctl.scala 689:91] + wire _T_9588 = _T_4778 & ic_tag_valid_out_1_107; // @[ifu_mem_ctl.scala 697:10] + wire _T_9735 = _T_9734 | _T_9588; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_108; // @[Reg.scala 27:20] - wire _T_9590 = _T_4779 & ic_tag_valid_out_1_108; // @[ifu_mem_ctl.scala 689:10] - wire _T_9736 = _T_9735 | _T_9590; // @[ifu_mem_ctl.scala 689:91] + wire _T_9590 = _T_4779 & ic_tag_valid_out_1_108; // @[ifu_mem_ctl.scala 697:10] + wire _T_9736 = _T_9735 | _T_9590; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_109; // @[Reg.scala 27:20] - wire _T_9592 = _T_4780 & ic_tag_valid_out_1_109; // @[ifu_mem_ctl.scala 689:10] - wire _T_9737 = _T_9736 | _T_9592; // @[ifu_mem_ctl.scala 689:91] + wire _T_9592 = _T_4780 & ic_tag_valid_out_1_109; // @[ifu_mem_ctl.scala 697:10] + wire _T_9737 = _T_9736 | _T_9592; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_110; // @[Reg.scala 27:20] - wire _T_9594 = _T_4781 & ic_tag_valid_out_1_110; // @[ifu_mem_ctl.scala 689:10] - wire _T_9738 = _T_9737 | _T_9594; // @[ifu_mem_ctl.scala 689:91] + wire _T_9594 = _T_4781 & ic_tag_valid_out_1_110; // @[ifu_mem_ctl.scala 697:10] + wire _T_9738 = _T_9737 | _T_9594; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_111; // @[Reg.scala 27:20] - wire _T_9596 = _T_4782 & ic_tag_valid_out_1_111; // @[ifu_mem_ctl.scala 689:10] - wire _T_9739 = _T_9738 | _T_9596; // @[ifu_mem_ctl.scala 689:91] + wire _T_9596 = _T_4782 & ic_tag_valid_out_1_111; // @[ifu_mem_ctl.scala 697:10] + wire _T_9739 = _T_9738 | _T_9596; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_112; // @[Reg.scala 27:20] - wire _T_9598 = _T_4783 & ic_tag_valid_out_1_112; // @[ifu_mem_ctl.scala 689:10] - wire _T_9740 = _T_9739 | _T_9598; // @[ifu_mem_ctl.scala 689:91] + wire _T_9598 = _T_4783 & ic_tag_valid_out_1_112; // @[ifu_mem_ctl.scala 697:10] + wire _T_9740 = _T_9739 | _T_9598; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_113; // @[Reg.scala 27:20] - wire _T_9600 = _T_4784 & ic_tag_valid_out_1_113; // @[ifu_mem_ctl.scala 689:10] - wire _T_9741 = _T_9740 | _T_9600; // @[ifu_mem_ctl.scala 689:91] + wire _T_9600 = _T_4784 & ic_tag_valid_out_1_113; // @[ifu_mem_ctl.scala 697:10] + wire _T_9741 = _T_9740 | _T_9600; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_114; // @[Reg.scala 27:20] - wire _T_9602 = _T_4785 & ic_tag_valid_out_1_114; // @[ifu_mem_ctl.scala 689:10] - wire _T_9742 = _T_9741 | _T_9602; // @[ifu_mem_ctl.scala 689:91] + wire _T_9602 = _T_4785 & ic_tag_valid_out_1_114; // @[ifu_mem_ctl.scala 697:10] + wire _T_9742 = _T_9741 | _T_9602; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_115; // @[Reg.scala 27:20] - wire _T_9604 = _T_4786 & ic_tag_valid_out_1_115; // @[ifu_mem_ctl.scala 689:10] - wire _T_9743 = _T_9742 | _T_9604; // @[ifu_mem_ctl.scala 689:91] + wire _T_9604 = _T_4786 & ic_tag_valid_out_1_115; // @[ifu_mem_ctl.scala 697:10] + wire _T_9743 = _T_9742 | _T_9604; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_116; // @[Reg.scala 27:20] - wire _T_9606 = _T_4787 & ic_tag_valid_out_1_116; // @[ifu_mem_ctl.scala 689:10] - wire _T_9744 = _T_9743 | _T_9606; // @[ifu_mem_ctl.scala 689:91] + wire _T_9606 = _T_4787 & ic_tag_valid_out_1_116; // @[ifu_mem_ctl.scala 697:10] + wire _T_9744 = _T_9743 | _T_9606; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_117; // @[Reg.scala 27:20] - wire _T_9608 = _T_4788 & ic_tag_valid_out_1_117; // @[ifu_mem_ctl.scala 689:10] - wire _T_9745 = _T_9744 | _T_9608; // @[ifu_mem_ctl.scala 689:91] + wire _T_9608 = _T_4788 & ic_tag_valid_out_1_117; // @[ifu_mem_ctl.scala 697:10] + wire _T_9745 = _T_9744 | _T_9608; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_118; // @[Reg.scala 27:20] - wire _T_9610 = _T_4789 & ic_tag_valid_out_1_118; // @[ifu_mem_ctl.scala 689:10] - wire _T_9746 = _T_9745 | _T_9610; // @[ifu_mem_ctl.scala 689:91] + wire _T_9610 = _T_4789 & ic_tag_valid_out_1_118; // @[ifu_mem_ctl.scala 697:10] + wire _T_9746 = _T_9745 | _T_9610; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_119; // @[Reg.scala 27:20] - wire _T_9612 = _T_4790 & ic_tag_valid_out_1_119; // @[ifu_mem_ctl.scala 689:10] - wire _T_9747 = _T_9746 | _T_9612; // @[ifu_mem_ctl.scala 689:91] + wire _T_9612 = _T_4790 & ic_tag_valid_out_1_119; // @[ifu_mem_ctl.scala 697:10] + wire _T_9747 = _T_9746 | _T_9612; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_120; // @[Reg.scala 27:20] - wire _T_9614 = _T_4791 & ic_tag_valid_out_1_120; // @[ifu_mem_ctl.scala 689:10] - wire _T_9748 = _T_9747 | _T_9614; // @[ifu_mem_ctl.scala 689:91] + wire _T_9614 = _T_4791 & ic_tag_valid_out_1_120; // @[ifu_mem_ctl.scala 697:10] + wire _T_9748 = _T_9747 | _T_9614; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_121; // @[Reg.scala 27:20] - wire _T_9616 = _T_4792 & ic_tag_valid_out_1_121; // @[ifu_mem_ctl.scala 689:10] - wire _T_9749 = _T_9748 | _T_9616; // @[ifu_mem_ctl.scala 689:91] + wire _T_9616 = _T_4792 & ic_tag_valid_out_1_121; // @[ifu_mem_ctl.scala 697:10] + wire _T_9749 = _T_9748 | _T_9616; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_122; // @[Reg.scala 27:20] - wire _T_9618 = _T_4793 & ic_tag_valid_out_1_122; // @[ifu_mem_ctl.scala 689:10] - wire _T_9750 = _T_9749 | _T_9618; // @[ifu_mem_ctl.scala 689:91] + wire _T_9618 = _T_4793 & ic_tag_valid_out_1_122; // @[ifu_mem_ctl.scala 697:10] + wire _T_9750 = _T_9749 | _T_9618; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_123; // @[Reg.scala 27:20] - wire _T_9620 = _T_4794 & ic_tag_valid_out_1_123; // @[ifu_mem_ctl.scala 689:10] - wire _T_9751 = _T_9750 | _T_9620; // @[ifu_mem_ctl.scala 689:91] + wire _T_9620 = _T_4794 & ic_tag_valid_out_1_123; // @[ifu_mem_ctl.scala 697:10] + wire _T_9751 = _T_9750 | _T_9620; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_124; // @[Reg.scala 27:20] - wire _T_9622 = _T_4795 & ic_tag_valid_out_1_124; // @[ifu_mem_ctl.scala 689:10] - wire _T_9752 = _T_9751 | _T_9622; // @[ifu_mem_ctl.scala 689:91] + wire _T_9622 = _T_4795 & ic_tag_valid_out_1_124; // @[ifu_mem_ctl.scala 697:10] + wire _T_9752 = _T_9751 | _T_9622; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_125; // @[Reg.scala 27:20] - wire _T_9624 = _T_4796 & ic_tag_valid_out_1_125; // @[ifu_mem_ctl.scala 689:10] - wire _T_9753 = _T_9752 | _T_9624; // @[ifu_mem_ctl.scala 689:91] + wire _T_9624 = _T_4796 & ic_tag_valid_out_1_125; // @[ifu_mem_ctl.scala 697:10] + wire _T_9753 = _T_9752 | _T_9624; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_126; // @[Reg.scala 27:20] - wire _T_9626 = _T_4797 & ic_tag_valid_out_1_126; // @[ifu_mem_ctl.scala 689:10] - wire _T_9754 = _T_9753 | _T_9626; // @[ifu_mem_ctl.scala 689:91] + wire _T_9626 = _T_4797 & ic_tag_valid_out_1_126; // @[ifu_mem_ctl.scala 697:10] + wire _T_9754 = _T_9753 | _T_9626; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_1_127; // @[Reg.scala 27:20] - wire _T_9628 = _T_4798 & ic_tag_valid_out_1_127; // @[ifu_mem_ctl.scala 689:10] - wire _T_9755 = _T_9754 | _T_9628; // @[ifu_mem_ctl.scala 689:91] + wire _T_9628 = _T_4798 & ic_tag_valid_out_1_127; // @[ifu_mem_ctl.scala 697:10] + wire _T_9755 = _T_9754 | _T_9628; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_0; // @[Reg.scala 27:20] - wire _T_8991 = _T_4671 & ic_tag_valid_out_0_0; // @[ifu_mem_ctl.scala 689:10] + wire _T_8991 = _T_4671 & ic_tag_valid_out_0_0; // @[ifu_mem_ctl.scala 697:10] reg ic_tag_valid_out_0_1; // @[Reg.scala 27:20] - wire _T_8993 = _T_4672 & ic_tag_valid_out_0_1; // @[ifu_mem_ctl.scala 689:10] - wire _T_9246 = _T_8991 | _T_8993; // @[ifu_mem_ctl.scala 689:91] + wire _T_8993 = _T_4672 & ic_tag_valid_out_0_1; // @[ifu_mem_ctl.scala 697:10] + wire _T_9246 = _T_8991 | _T_8993; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_2; // @[Reg.scala 27:20] - wire _T_8995 = _T_4673 & ic_tag_valid_out_0_2; // @[ifu_mem_ctl.scala 689:10] - wire _T_9247 = _T_9246 | _T_8995; // @[ifu_mem_ctl.scala 689:91] + wire _T_8995 = _T_4673 & ic_tag_valid_out_0_2; // @[ifu_mem_ctl.scala 697:10] + wire _T_9247 = _T_9246 | _T_8995; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_3; // @[Reg.scala 27:20] - wire _T_8997 = _T_4674 & ic_tag_valid_out_0_3; // @[ifu_mem_ctl.scala 689:10] - wire _T_9248 = _T_9247 | _T_8997; // @[ifu_mem_ctl.scala 689:91] + wire _T_8997 = _T_4674 & ic_tag_valid_out_0_3; // @[ifu_mem_ctl.scala 697:10] + wire _T_9248 = _T_9247 | _T_8997; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_4; // @[Reg.scala 27:20] - wire _T_8999 = _T_4675 & ic_tag_valid_out_0_4; // @[ifu_mem_ctl.scala 689:10] - wire _T_9249 = _T_9248 | _T_8999; // @[ifu_mem_ctl.scala 689:91] + wire _T_8999 = _T_4675 & ic_tag_valid_out_0_4; // @[ifu_mem_ctl.scala 697:10] + wire _T_9249 = _T_9248 | _T_8999; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_5; // @[Reg.scala 27:20] - wire _T_9001 = _T_4676 & ic_tag_valid_out_0_5; // @[ifu_mem_ctl.scala 689:10] - wire _T_9250 = _T_9249 | _T_9001; // @[ifu_mem_ctl.scala 689:91] + wire _T_9001 = _T_4676 & ic_tag_valid_out_0_5; // @[ifu_mem_ctl.scala 697:10] + wire _T_9250 = _T_9249 | _T_9001; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_6; // @[Reg.scala 27:20] - wire _T_9003 = _T_4677 & ic_tag_valid_out_0_6; // @[ifu_mem_ctl.scala 689:10] - wire _T_9251 = _T_9250 | _T_9003; // @[ifu_mem_ctl.scala 689:91] + wire _T_9003 = _T_4677 & ic_tag_valid_out_0_6; // @[ifu_mem_ctl.scala 697:10] + wire _T_9251 = _T_9250 | _T_9003; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_7; // @[Reg.scala 27:20] - wire _T_9005 = _T_4678 & ic_tag_valid_out_0_7; // @[ifu_mem_ctl.scala 689:10] - wire _T_9252 = _T_9251 | _T_9005; // @[ifu_mem_ctl.scala 689:91] + wire _T_9005 = _T_4678 & ic_tag_valid_out_0_7; // @[ifu_mem_ctl.scala 697:10] + wire _T_9252 = _T_9251 | _T_9005; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_8; // @[Reg.scala 27:20] - wire _T_9007 = _T_4679 & ic_tag_valid_out_0_8; // @[ifu_mem_ctl.scala 689:10] - wire _T_9253 = _T_9252 | _T_9007; // @[ifu_mem_ctl.scala 689:91] + wire _T_9007 = _T_4679 & ic_tag_valid_out_0_8; // @[ifu_mem_ctl.scala 697:10] + wire _T_9253 = _T_9252 | _T_9007; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_9; // @[Reg.scala 27:20] - wire _T_9009 = _T_4680 & ic_tag_valid_out_0_9; // @[ifu_mem_ctl.scala 689:10] - wire _T_9254 = _T_9253 | _T_9009; // @[ifu_mem_ctl.scala 689:91] + wire _T_9009 = _T_4680 & ic_tag_valid_out_0_9; // @[ifu_mem_ctl.scala 697:10] + wire _T_9254 = _T_9253 | _T_9009; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_10; // @[Reg.scala 27:20] - wire _T_9011 = _T_4681 & ic_tag_valid_out_0_10; // @[ifu_mem_ctl.scala 689:10] - wire _T_9255 = _T_9254 | _T_9011; // @[ifu_mem_ctl.scala 689:91] + wire _T_9011 = _T_4681 & ic_tag_valid_out_0_10; // @[ifu_mem_ctl.scala 697:10] + wire _T_9255 = _T_9254 | _T_9011; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_11; // @[Reg.scala 27:20] - wire _T_9013 = _T_4682 & ic_tag_valid_out_0_11; // @[ifu_mem_ctl.scala 689:10] - wire _T_9256 = _T_9255 | _T_9013; // @[ifu_mem_ctl.scala 689:91] + wire _T_9013 = _T_4682 & ic_tag_valid_out_0_11; // @[ifu_mem_ctl.scala 697:10] + wire _T_9256 = _T_9255 | _T_9013; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_12; // @[Reg.scala 27:20] - wire _T_9015 = _T_4683 & ic_tag_valid_out_0_12; // @[ifu_mem_ctl.scala 689:10] - wire _T_9257 = _T_9256 | _T_9015; // @[ifu_mem_ctl.scala 689:91] + wire _T_9015 = _T_4683 & ic_tag_valid_out_0_12; // @[ifu_mem_ctl.scala 697:10] + wire _T_9257 = _T_9256 | _T_9015; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_13; // @[Reg.scala 27:20] - wire _T_9017 = _T_4684 & ic_tag_valid_out_0_13; // @[ifu_mem_ctl.scala 689:10] - wire _T_9258 = _T_9257 | _T_9017; // @[ifu_mem_ctl.scala 689:91] + wire _T_9017 = _T_4684 & ic_tag_valid_out_0_13; // @[ifu_mem_ctl.scala 697:10] + wire _T_9258 = _T_9257 | _T_9017; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_14; // @[Reg.scala 27:20] - wire _T_9019 = _T_4685 & ic_tag_valid_out_0_14; // @[ifu_mem_ctl.scala 689:10] - wire _T_9259 = _T_9258 | _T_9019; // @[ifu_mem_ctl.scala 689:91] + wire _T_9019 = _T_4685 & ic_tag_valid_out_0_14; // @[ifu_mem_ctl.scala 697:10] + wire _T_9259 = _T_9258 | _T_9019; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_15; // @[Reg.scala 27:20] - wire _T_9021 = _T_4686 & ic_tag_valid_out_0_15; // @[ifu_mem_ctl.scala 689:10] - wire _T_9260 = _T_9259 | _T_9021; // @[ifu_mem_ctl.scala 689:91] + wire _T_9021 = _T_4686 & ic_tag_valid_out_0_15; // @[ifu_mem_ctl.scala 697:10] + wire _T_9260 = _T_9259 | _T_9021; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_16; // @[Reg.scala 27:20] - wire _T_9023 = _T_4687 & ic_tag_valid_out_0_16; // @[ifu_mem_ctl.scala 689:10] - wire _T_9261 = _T_9260 | _T_9023; // @[ifu_mem_ctl.scala 689:91] + wire _T_9023 = _T_4687 & ic_tag_valid_out_0_16; // @[ifu_mem_ctl.scala 697:10] + wire _T_9261 = _T_9260 | _T_9023; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_17; // @[Reg.scala 27:20] - wire _T_9025 = _T_4688 & ic_tag_valid_out_0_17; // @[ifu_mem_ctl.scala 689:10] - wire _T_9262 = _T_9261 | _T_9025; // @[ifu_mem_ctl.scala 689:91] + wire _T_9025 = _T_4688 & ic_tag_valid_out_0_17; // @[ifu_mem_ctl.scala 697:10] + wire _T_9262 = _T_9261 | _T_9025; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_18; // @[Reg.scala 27:20] - wire _T_9027 = _T_4689 & ic_tag_valid_out_0_18; // @[ifu_mem_ctl.scala 689:10] - wire _T_9263 = _T_9262 | _T_9027; // @[ifu_mem_ctl.scala 689:91] + wire _T_9027 = _T_4689 & ic_tag_valid_out_0_18; // @[ifu_mem_ctl.scala 697:10] + wire _T_9263 = _T_9262 | _T_9027; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_19; // @[Reg.scala 27:20] - wire _T_9029 = _T_4690 & ic_tag_valid_out_0_19; // @[ifu_mem_ctl.scala 689:10] - wire _T_9264 = _T_9263 | _T_9029; // @[ifu_mem_ctl.scala 689:91] + wire _T_9029 = _T_4690 & ic_tag_valid_out_0_19; // @[ifu_mem_ctl.scala 697:10] + wire _T_9264 = _T_9263 | _T_9029; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_20; // @[Reg.scala 27:20] - wire _T_9031 = _T_4691 & ic_tag_valid_out_0_20; // @[ifu_mem_ctl.scala 689:10] - wire _T_9265 = _T_9264 | _T_9031; // @[ifu_mem_ctl.scala 689:91] + wire _T_9031 = _T_4691 & ic_tag_valid_out_0_20; // @[ifu_mem_ctl.scala 697:10] + wire _T_9265 = _T_9264 | _T_9031; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_21; // @[Reg.scala 27:20] - wire _T_9033 = _T_4692 & ic_tag_valid_out_0_21; // @[ifu_mem_ctl.scala 689:10] - wire _T_9266 = _T_9265 | _T_9033; // @[ifu_mem_ctl.scala 689:91] + wire _T_9033 = _T_4692 & ic_tag_valid_out_0_21; // @[ifu_mem_ctl.scala 697:10] + wire _T_9266 = _T_9265 | _T_9033; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_22; // @[Reg.scala 27:20] - wire _T_9035 = _T_4693 & ic_tag_valid_out_0_22; // @[ifu_mem_ctl.scala 689:10] - wire _T_9267 = _T_9266 | _T_9035; // @[ifu_mem_ctl.scala 689:91] + wire _T_9035 = _T_4693 & ic_tag_valid_out_0_22; // @[ifu_mem_ctl.scala 697:10] + wire _T_9267 = _T_9266 | _T_9035; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_23; // @[Reg.scala 27:20] - wire _T_9037 = _T_4694 & ic_tag_valid_out_0_23; // @[ifu_mem_ctl.scala 689:10] - wire _T_9268 = _T_9267 | _T_9037; // @[ifu_mem_ctl.scala 689:91] + wire _T_9037 = _T_4694 & ic_tag_valid_out_0_23; // @[ifu_mem_ctl.scala 697:10] + wire _T_9268 = _T_9267 | _T_9037; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_24; // @[Reg.scala 27:20] - wire _T_9039 = _T_4695 & ic_tag_valid_out_0_24; // @[ifu_mem_ctl.scala 689:10] - wire _T_9269 = _T_9268 | _T_9039; // @[ifu_mem_ctl.scala 689:91] + wire _T_9039 = _T_4695 & ic_tag_valid_out_0_24; // @[ifu_mem_ctl.scala 697:10] + wire _T_9269 = _T_9268 | _T_9039; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_25; // @[Reg.scala 27:20] - wire _T_9041 = _T_4696 & ic_tag_valid_out_0_25; // @[ifu_mem_ctl.scala 689:10] - wire _T_9270 = _T_9269 | _T_9041; // @[ifu_mem_ctl.scala 689:91] + wire _T_9041 = _T_4696 & ic_tag_valid_out_0_25; // @[ifu_mem_ctl.scala 697:10] + wire _T_9270 = _T_9269 | _T_9041; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_26; // @[Reg.scala 27:20] - wire _T_9043 = _T_4697 & ic_tag_valid_out_0_26; // @[ifu_mem_ctl.scala 689:10] - wire _T_9271 = _T_9270 | _T_9043; // @[ifu_mem_ctl.scala 689:91] + wire _T_9043 = _T_4697 & ic_tag_valid_out_0_26; // @[ifu_mem_ctl.scala 697:10] + wire _T_9271 = _T_9270 | _T_9043; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_27; // @[Reg.scala 27:20] - wire _T_9045 = _T_4698 & ic_tag_valid_out_0_27; // @[ifu_mem_ctl.scala 689:10] - wire _T_9272 = _T_9271 | _T_9045; // @[ifu_mem_ctl.scala 689:91] + wire _T_9045 = _T_4698 & ic_tag_valid_out_0_27; // @[ifu_mem_ctl.scala 697:10] + wire _T_9272 = _T_9271 | _T_9045; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_28; // @[Reg.scala 27:20] - wire _T_9047 = _T_4699 & ic_tag_valid_out_0_28; // @[ifu_mem_ctl.scala 689:10] - wire _T_9273 = _T_9272 | _T_9047; // @[ifu_mem_ctl.scala 689:91] + wire _T_9047 = _T_4699 & ic_tag_valid_out_0_28; // @[ifu_mem_ctl.scala 697:10] + wire _T_9273 = _T_9272 | _T_9047; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_29; // @[Reg.scala 27:20] - wire _T_9049 = _T_4700 & ic_tag_valid_out_0_29; // @[ifu_mem_ctl.scala 689:10] - wire _T_9274 = _T_9273 | _T_9049; // @[ifu_mem_ctl.scala 689:91] + wire _T_9049 = _T_4700 & ic_tag_valid_out_0_29; // @[ifu_mem_ctl.scala 697:10] + wire _T_9274 = _T_9273 | _T_9049; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_30; // @[Reg.scala 27:20] - wire _T_9051 = _T_4701 & ic_tag_valid_out_0_30; // @[ifu_mem_ctl.scala 689:10] - wire _T_9275 = _T_9274 | _T_9051; // @[ifu_mem_ctl.scala 689:91] + wire _T_9051 = _T_4701 & ic_tag_valid_out_0_30; // @[ifu_mem_ctl.scala 697:10] + wire _T_9275 = _T_9274 | _T_9051; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_31; // @[Reg.scala 27:20] - wire _T_9053 = _T_4702 & ic_tag_valid_out_0_31; // @[ifu_mem_ctl.scala 689:10] - wire _T_9276 = _T_9275 | _T_9053; // @[ifu_mem_ctl.scala 689:91] + wire _T_9053 = _T_4702 & ic_tag_valid_out_0_31; // @[ifu_mem_ctl.scala 697:10] + wire _T_9276 = _T_9275 | _T_9053; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_32; // @[Reg.scala 27:20] - wire _T_9055 = _T_4703 & ic_tag_valid_out_0_32; // @[ifu_mem_ctl.scala 689:10] - wire _T_9277 = _T_9276 | _T_9055; // @[ifu_mem_ctl.scala 689:91] + wire _T_9055 = _T_4703 & ic_tag_valid_out_0_32; // @[ifu_mem_ctl.scala 697:10] + wire _T_9277 = _T_9276 | _T_9055; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_33; // @[Reg.scala 27:20] - wire _T_9057 = _T_4704 & ic_tag_valid_out_0_33; // @[ifu_mem_ctl.scala 689:10] - wire _T_9278 = _T_9277 | _T_9057; // @[ifu_mem_ctl.scala 689:91] + wire _T_9057 = _T_4704 & ic_tag_valid_out_0_33; // @[ifu_mem_ctl.scala 697:10] + wire _T_9278 = _T_9277 | _T_9057; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_34; // @[Reg.scala 27:20] - wire _T_9059 = _T_4705 & ic_tag_valid_out_0_34; // @[ifu_mem_ctl.scala 689:10] - wire _T_9279 = _T_9278 | _T_9059; // @[ifu_mem_ctl.scala 689:91] + wire _T_9059 = _T_4705 & ic_tag_valid_out_0_34; // @[ifu_mem_ctl.scala 697:10] + wire _T_9279 = _T_9278 | _T_9059; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_35; // @[Reg.scala 27:20] - wire _T_9061 = _T_4706 & ic_tag_valid_out_0_35; // @[ifu_mem_ctl.scala 689:10] - wire _T_9280 = _T_9279 | _T_9061; // @[ifu_mem_ctl.scala 689:91] + wire _T_9061 = _T_4706 & ic_tag_valid_out_0_35; // @[ifu_mem_ctl.scala 697:10] + wire _T_9280 = _T_9279 | _T_9061; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_36; // @[Reg.scala 27:20] - wire _T_9063 = _T_4707 & ic_tag_valid_out_0_36; // @[ifu_mem_ctl.scala 689:10] - wire _T_9281 = _T_9280 | _T_9063; // @[ifu_mem_ctl.scala 689:91] + wire _T_9063 = _T_4707 & ic_tag_valid_out_0_36; // @[ifu_mem_ctl.scala 697:10] + wire _T_9281 = _T_9280 | _T_9063; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_37; // @[Reg.scala 27:20] - wire _T_9065 = _T_4708 & ic_tag_valid_out_0_37; // @[ifu_mem_ctl.scala 689:10] - wire _T_9282 = _T_9281 | _T_9065; // @[ifu_mem_ctl.scala 689:91] + wire _T_9065 = _T_4708 & ic_tag_valid_out_0_37; // @[ifu_mem_ctl.scala 697:10] + wire _T_9282 = _T_9281 | _T_9065; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_38; // @[Reg.scala 27:20] - wire _T_9067 = _T_4709 & ic_tag_valid_out_0_38; // @[ifu_mem_ctl.scala 689:10] - wire _T_9283 = _T_9282 | _T_9067; // @[ifu_mem_ctl.scala 689:91] + wire _T_9067 = _T_4709 & ic_tag_valid_out_0_38; // @[ifu_mem_ctl.scala 697:10] + wire _T_9283 = _T_9282 | _T_9067; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_39; // @[Reg.scala 27:20] - wire _T_9069 = _T_4710 & ic_tag_valid_out_0_39; // @[ifu_mem_ctl.scala 689:10] - wire _T_9284 = _T_9283 | _T_9069; // @[ifu_mem_ctl.scala 689:91] + wire _T_9069 = _T_4710 & ic_tag_valid_out_0_39; // @[ifu_mem_ctl.scala 697:10] + wire _T_9284 = _T_9283 | _T_9069; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_40; // @[Reg.scala 27:20] - wire _T_9071 = _T_4711 & ic_tag_valid_out_0_40; // @[ifu_mem_ctl.scala 689:10] - wire _T_9285 = _T_9284 | _T_9071; // @[ifu_mem_ctl.scala 689:91] + wire _T_9071 = _T_4711 & ic_tag_valid_out_0_40; // @[ifu_mem_ctl.scala 697:10] + wire _T_9285 = _T_9284 | _T_9071; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_41; // @[Reg.scala 27:20] - wire _T_9073 = _T_4712 & ic_tag_valid_out_0_41; // @[ifu_mem_ctl.scala 689:10] - wire _T_9286 = _T_9285 | _T_9073; // @[ifu_mem_ctl.scala 689:91] + wire _T_9073 = _T_4712 & ic_tag_valid_out_0_41; // @[ifu_mem_ctl.scala 697:10] + wire _T_9286 = _T_9285 | _T_9073; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_42; // @[Reg.scala 27:20] - wire _T_9075 = _T_4713 & ic_tag_valid_out_0_42; // @[ifu_mem_ctl.scala 689:10] - wire _T_9287 = _T_9286 | _T_9075; // @[ifu_mem_ctl.scala 689:91] + wire _T_9075 = _T_4713 & ic_tag_valid_out_0_42; // @[ifu_mem_ctl.scala 697:10] + wire _T_9287 = _T_9286 | _T_9075; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_43; // @[Reg.scala 27:20] - wire _T_9077 = _T_4714 & ic_tag_valid_out_0_43; // @[ifu_mem_ctl.scala 689:10] - wire _T_9288 = _T_9287 | _T_9077; // @[ifu_mem_ctl.scala 689:91] + wire _T_9077 = _T_4714 & ic_tag_valid_out_0_43; // @[ifu_mem_ctl.scala 697:10] + wire _T_9288 = _T_9287 | _T_9077; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_44; // @[Reg.scala 27:20] - wire _T_9079 = _T_4715 & ic_tag_valid_out_0_44; // @[ifu_mem_ctl.scala 689:10] - wire _T_9289 = _T_9288 | _T_9079; // @[ifu_mem_ctl.scala 689:91] + wire _T_9079 = _T_4715 & ic_tag_valid_out_0_44; // @[ifu_mem_ctl.scala 697:10] + wire _T_9289 = _T_9288 | _T_9079; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_45; // @[Reg.scala 27:20] - wire _T_9081 = _T_4716 & ic_tag_valid_out_0_45; // @[ifu_mem_ctl.scala 689:10] - wire _T_9290 = _T_9289 | _T_9081; // @[ifu_mem_ctl.scala 689:91] + wire _T_9081 = _T_4716 & ic_tag_valid_out_0_45; // @[ifu_mem_ctl.scala 697:10] + wire _T_9290 = _T_9289 | _T_9081; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_46; // @[Reg.scala 27:20] - wire _T_9083 = _T_4717 & ic_tag_valid_out_0_46; // @[ifu_mem_ctl.scala 689:10] - wire _T_9291 = _T_9290 | _T_9083; // @[ifu_mem_ctl.scala 689:91] + wire _T_9083 = _T_4717 & ic_tag_valid_out_0_46; // @[ifu_mem_ctl.scala 697:10] + wire _T_9291 = _T_9290 | _T_9083; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_47; // @[Reg.scala 27:20] - wire _T_9085 = _T_4718 & ic_tag_valid_out_0_47; // @[ifu_mem_ctl.scala 689:10] - wire _T_9292 = _T_9291 | _T_9085; // @[ifu_mem_ctl.scala 689:91] + wire _T_9085 = _T_4718 & ic_tag_valid_out_0_47; // @[ifu_mem_ctl.scala 697:10] + wire _T_9292 = _T_9291 | _T_9085; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_48; // @[Reg.scala 27:20] - wire _T_9087 = _T_4719 & ic_tag_valid_out_0_48; // @[ifu_mem_ctl.scala 689:10] - wire _T_9293 = _T_9292 | _T_9087; // @[ifu_mem_ctl.scala 689:91] + wire _T_9087 = _T_4719 & ic_tag_valid_out_0_48; // @[ifu_mem_ctl.scala 697:10] + wire _T_9293 = _T_9292 | _T_9087; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_49; // @[Reg.scala 27:20] - wire _T_9089 = _T_4720 & ic_tag_valid_out_0_49; // @[ifu_mem_ctl.scala 689:10] - wire _T_9294 = _T_9293 | _T_9089; // @[ifu_mem_ctl.scala 689:91] + wire _T_9089 = _T_4720 & ic_tag_valid_out_0_49; // @[ifu_mem_ctl.scala 697:10] + wire _T_9294 = _T_9293 | _T_9089; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_50; // @[Reg.scala 27:20] - wire _T_9091 = _T_4721 & ic_tag_valid_out_0_50; // @[ifu_mem_ctl.scala 689:10] - wire _T_9295 = _T_9294 | _T_9091; // @[ifu_mem_ctl.scala 689:91] + wire _T_9091 = _T_4721 & ic_tag_valid_out_0_50; // @[ifu_mem_ctl.scala 697:10] + wire _T_9295 = _T_9294 | _T_9091; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_51; // @[Reg.scala 27:20] - wire _T_9093 = _T_4722 & ic_tag_valid_out_0_51; // @[ifu_mem_ctl.scala 689:10] - wire _T_9296 = _T_9295 | _T_9093; // @[ifu_mem_ctl.scala 689:91] + wire _T_9093 = _T_4722 & ic_tag_valid_out_0_51; // @[ifu_mem_ctl.scala 697:10] + wire _T_9296 = _T_9295 | _T_9093; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_52; // @[Reg.scala 27:20] - wire _T_9095 = _T_4723 & ic_tag_valid_out_0_52; // @[ifu_mem_ctl.scala 689:10] - wire _T_9297 = _T_9296 | _T_9095; // @[ifu_mem_ctl.scala 689:91] + wire _T_9095 = _T_4723 & ic_tag_valid_out_0_52; // @[ifu_mem_ctl.scala 697:10] + wire _T_9297 = _T_9296 | _T_9095; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_53; // @[Reg.scala 27:20] - wire _T_9097 = _T_4724 & ic_tag_valid_out_0_53; // @[ifu_mem_ctl.scala 689:10] - wire _T_9298 = _T_9297 | _T_9097; // @[ifu_mem_ctl.scala 689:91] + wire _T_9097 = _T_4724 & ic_tag_valid_out_0_53; // @[ifu_mem_ctl.scala 697:10] + wire _T_9298 = _T_9297 | _T_9097; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_54; // @[Reg.scala 27:20] - wire _T_9099 = _T_4725 & ic_tag_valid_out_0_54; // @[ifu_mem_ctl.scala 689:10] - wire _T_9299 = _T_9298 | _T_9099; // @[ifu_mem_ctl.scala 689:91] + wire _T_9099 = _T_4725 & ic_tag_valid_out_0_54; // @[ifu_mem_ctl.scala 697:10] + wire _T_9299 = _T_9298 | _T_9099; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_55; // @[Reg.scala 27:20] - wire _T_9101 = _T_4726 & ic_tag_valid_out_0_55; // @[ifu_mem_ctl.scala 689:10] - wire _T_9300 = _T_9299 | _T_9101; // @[ifu_mem_ctl.scala 689:91] + wire _T_9101 = _T_4726 & ic_tag_valid_out_0_55; // @[ifu_mem_ctl.scala 697:10] + wire _T_9300 = _T_9299 | _T_9101; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_56; // @[Reg.scala 27:20] - wire _T_9103 = _T_4727 & ic_tag_valid_out_0_56; // @[ifu_mem_ctl.scala 689:10] - wire _T_9301 = _T_9300 | _T_9103; // @[ifu_mem_ctl.scala 689:91] + wire _T_9103 = _T_4727 & ic_tag_valid_out_0_56; // @[ifu_mem_ctl.scala 697:10] + wire _T_9301 = _T_9300 | _T_9103; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_57; // @[Reg.scala 27:20] - wire _T_9105 = _T_4728 & ic_tag_valid_out_0_57; // @[ifu_mem_ctl.scala 689:10] - wire _T_9302 = _T_9301 | _T_9105; // @[ifu_mem_ctl.scala 689:91] + wire _T_9105 = _T_4728 & ic_tag_valid_out_0_57; // @[ifu_mem_ctl.scala 697:10] + wire _T_9302 = _T_9301 | _T_9105; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_58; // @[Reg.scala 27:20] - wire _T_9107 = _T_4729 & ic_tag_valid_out_0_58; // @[ifu_mem_ctl.scala 689:10] - wire _T_9303 = _T_9302 | _T_9107; // @[ifu_mem_ctl.scala 689:91] + wire _T_9107 = _T_4729 & ic_tag_valid_out_0_58; // @[ifu_mem_ctl.scala 697:10] + wire _T_9303 = _T_9302 | _T_9107; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_59; // @[Reg.scala 27:20] - wire _T_9109 = _T_4730 & ic_tag_valid_out_0_59; // @[ifu_mem_ctl.scala 689:10] - wire _T_9304 = _T_9303 | _T_9109; // @[ifu_mem_ctl.scala 689:91] + wire _T_9109 = _T_4730 & ic_tag_valid_out_0_59; // @[ifu_mem_ctl.scala 697:10] + wire _T_9304 = _T_9303 | _T_9109; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_60; // @[Reg.scala 27:20] - wire _T_9111 = _T_4731 & ic_tag_valid_out_0_60; // @[ifu_mem_ctl.scala 689:10] - wire _T_9305 = _T_9304 | _T_9111; // @[ifu_mem_ctl.scala 689:91] + wire _T_9111 = _T_4731 & ic_tag_valid_out_0_60; // @[ifu_mem_ctl.scala 697:10] + wire _T_9305 = _T_9304 | _T_9111; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_61; // @[Reg.scala 27:20] - wire _T_9113 = _T_4732 & ic_tag_valid_out_0_61; // @[ifu_mem_ctl.scala 689:10] - wire _T_9306 = _T_9305 | _T_9113; // @[ifu_mem_ctl.scala 689:91] + wire _T_9113 = _T_4732 & ic_tag_valid_out_0_61; // @[ifu_mem_ctl.scala 697:10] + wire _T_9306 = _T_9305 | _T_9113; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_62; // @[Reg.scala 27:20] - wire _T_9115 = _T_4733 & ic_tag_valid_out_0_62; // @[ifu_mem_ctl.scala 689:10] - wire _T_9307 = _T_9306 | _T_9115; // @[ifu_mem_ctl.scala 689:91] + wire _T_9115 = _T_4733 & ic_tag_valid_out_0_62; // @[ifu_mem_ctl.scala 697:10] + wire _T_9307 = _T_9306 | _T_9115; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_63; // @[Reg.scala 27:20] - wire _T_9117 = _T_4734 & ic_tag_valid_out_0_63; // @[ifu_mem_ctl.scala 689:10] - wire _T_9308 = _T_9307 | _T_9117; // @[ifu_mem_ctl.scala 689:91] + wire _T_9117 = _T_4734 & ic_tag_valid_out_0_63; // @[ifu_mem_ctl.scala 697:10] + wire _T_9308 = _T_9307 | _T_9117; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_64; // @[Reg.scala 27:20] - wire _T_9119 = _T_4735 & ic_tag_valid_out_0_64; // @[ifu_mem_ctl.scala 689:10] - wire _T_9309 = _T_9308 | _T_9119; // @[ifu_mem_ctl.scala 689:91] + wire _T_9119 = _T_4735 & ic_tag_valid_out_0_64; // @[ifu_mem_ctl.scala 697:10] + wire _T_9309 = _T_9308 | _T_9119; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_65; // @[Reg.scala 27:20] - wire _T_9121 = _T_4736 & ic_tag_valid_out_0_65; // @[ifu_mem_ctl.scala 689:10] - wire _T_9310 = _T_9309 | _T_9121; // @[ifu_mem_ctl.scala 689:91] + wire _T_9121 = _T_4736 & ic_tag_valid_out_0_65; // @[ifu_mem_ctl.scala 697:10] + wire _T_9310 = _T_9309 | _T_9121; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_66; // @[Reg.scala 27:20] - wire _T_9123 = _T_4737 & ic_tag_valid_out_0_66; // @[ifu_mem_ctl.scala 689:10] - wire _T_9311 = _T_9310 | _T_9123; // @[ifu_mem_ctl.scala 689:91] + wire _T_9123 = _T_4737 & ic_tag_valid_out_0_66; // @[ifu_mem_ctl.scala 697:10] + wire _T_9311 = _T_9310 | _T_9123; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_67; // @[Reg.scala 27:20] - wire _T_9125 = _T_4738 & ic_tag_valid_out_0_67; // @[ifu_mem_ctl.scala 689:10] - wire _T_9312 = _T_9311 | _T_9125; // @[ifu_mem_ctl.scala 689:91] + wire _T_9125 = _T_4738 & ic_tag_valid_out_0_67; // @[ifu_mem_ctl.scala 697:10] + wire _T_9312 = _T_9311 | _T_9125; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_68; // @[Reg.scala 27:20] - wire _T_9127 = _T_4739 & ic_tag_valid_out_0_68; // @[ifu_mem_ctl.scala 689:10] - wire _T_9313 = _T_9312 | _T_9127; // @[ifu_mem_ctl.scala 689:91] + wire _T_9127 = _T_4739 & ic_tag_valid_out_0_68; // @[ifu_mem_ctl.scala 697:10] + wire _T_9313 = _T_9312 | _T_9127; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_69; // @[Reg.scala 27:20] - wire _T_9129 = _T_4740 & ic_tag_valid_out_0_69; // @[ifu_mem_ctl.scala 689:10] - wire _T_9314 = _T_9313 | _T_9129; // @[ifu_mem_ctl.scala 689:91] + wire _T_9129 = _T_4740 & ic_tag_valid_out_0_69; // @[ifu_mem_ctl.scala 697:10] + wire _T_9314 = _T_9313 | _T_9129; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_70; // @[Reg.scala 27:20] - wire _T_9131 = _T_4741 & ic_tag_valid_out_0_70; // @[ifu_mem_ctl.scala 689:10] - wire _T_9315 = _T_9314 | _T_9131; // @[ifu_mem_ctl.scala 689:91] + wire _T_9131 = _T_4741 & ic_tag_valid_out_0_70; // @[ifu_mem_ctl.scala 697:10] + wire _T_9315 = _T_9314 | _T_9131; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_71; // @[Reg.scala 27:20] - wire _T_9133 = _T_4742 & ic_tag_valid_out_0_71; // @[ifu_mem_ctl.scala 689:10] - wire _T_9316 = _T_9315 | _T_9133; // @[ifu_mem_ctl.scala 689:91] + wire _T_9133 = _T_4742 & ic_tag_valid_out_0_71; // @[ifu_mem_ctl.scala 697:10] + wire _T_9316 = _T_9315 | _T_9133; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_72; // @[Reg.scala 27:20] - wire _T_9135 = _T_4743 & ic_tag_valid_out_0_72; // @[ifu_mem_ctl.scala 689:10] - wire _T_9317 = _T_9316 | _T_9135; // @[ifu_mem_ctl.scala 689:91] + wire _T_9135 = _T_4743 & ic_tag_valid_out_0_72; // @[ifu_mem_ctl.scala 697:10] + wire _T_9317 = _T_9316 | _T_9135; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_73; // @[Reg.scala 27:20] - wire _T_9137 = _T_4744 & ic_tag_valid_out_0_73; // @[ifu_mem_ctl.scala 689:10] - wire _T_9318 = _T_9317 | _T_9137; // @[ifu_mem_ctl.scala 689:91] + wire _T_9137 = _T_4744 & ic_tag_valid_out_0_73; // @[ifu_mem_ctl.scala 697:10] + wire _T_9318 = _T_9317 | _T_9137; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_74; // @[Reg.scala 27:20] - wire _T_9139 = _T_4745 & ic_tag_valid_out_0_74; // @[ifu_mem_ctl.scala 689:10] - wire _T_9319 = _T_9318 | _T_9139; // @[ifu_mem_ctl.scala 689:91] + wire _T_9139 = _T_4745 & ic_tag_valid_out_0_74; // @[ifu_mem_ctl.scala 697:10] + wire _T_9319 = _T_9318 | _T_9139; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_75; // @[Reg.scala 27:20] - wire _T_9141 = _T_4746 & ic_tag_valid_out_0_75; // @[ifu_mem_ctl.scala 689:10] - wire _T_9320 = _T_9319 | _T_9141; // @[ifu_mem_ctl.scala 689:91] + wire _T_9141 = _T_4746 & ic_tag_valid_out_0_75; // @[ifu_mem_ctl.scala 697:10] + wire _T_9320 = _T_9319 | _T_9141; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_76; // @[Reg.scala 27:20] - wire _T_9143 = _T_4747 & ic_tag_valid_out_0_76; // @[ifu_mem_ctl.scala 689:10] - wire _T_9321 = _T_9320 | _T_9143; // @[ifu_mem_ctl.scala 689:91] + wire _T_9143 = _T_4747 & ic_tag_valid_out_0_76; // @[ifu_mem_ctl.scala 697:10] + wire _T_9321 = _T_9320 | _T_9143; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_77; // @[Reg.scala 27:20] - wire _T_9145 = _T_4748 & ic_tag_valid_out_0_77; // @[ifu_mem_ctl.scala 689:10] - wire _T_9322 = _T_9321 | _T_9145; // @[ifu_mem_ctl.scala 689:91] + wire _T_9145 = _T_4748 & ic_tag_valid_out_0_77; // @[ifu_mem_ctl.scala 697:10] + wire _T_9322 = _T_9321 | _T_9145; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_78; // @[Reg.scala 27:20] - wire _T_9147 = _T_4749 & ic_tag_valid_out_0_78; // @[ifu_mem_ctl.scala 689:10] - wire _T_9323 = _T_9322 | _T_9147; // @[ifu_mem_ctl.scala 689:91] + wire _T_9147 = _T_4749 & ic_tag_valid_out_0_78; // @[ifu_mem_ctl.scala 697:10] + wire _T_9323 = _T_9322 | _T_9147; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_79; // @[Reg.scala 27:20] - wire _T_9149 = _T_4750 & ic_tag_valid_out_0_79; // @[ifu_mem_ctl.scala 689:10] - wire _T_9324 = _T_9323 | _T_9149; // @[ifu_mem_ctl.scala 689:91] + wire _T_9149 = _T_4750 & ic_tag_valid_out_0_79; // @[ifu_mem_ctl.scala 697:10] + wire _T_9324 = _T_9323 | _T_9149; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_80; // @[Reg.scala 27:20] - wire _T_9151 = _T_4751 & ic_tag_valid_out_0_80; // @[ifu_mem_ctl.scala 689:10] - wire _T_9325 = _T_9324 | _T_9151; // @[ifu_mem_ctl.scala 689:91] + wire _T_9151 = _T_4751 & ic_tag_valid_out_0_80; // @[ifu_mem_ctl.scala 697:10] + wire _T_9325 = _T_9324 | _T_9151; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_81; // @[Reg.scala 27:20] - wire _T_9153 = _T_4752 & ic_tag_valid_out_0_81; // @[ifu_mem_ctl.scala 689:10] - wire _T_9326 = _T_9325 | _T_9153; // @[ifu_mem_ctl.scala 689:91] + wire _T_9153 = _T_4752 & ic_tag_valid_out_0_81; // @[ifu_mem_ctl.scala 697:10] + wire _T_9326 = _T_9325 | _T_9153; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_82; // @[Reg.scala 27:20] - wire _T_9155 = _T_4753 & ic_tag_valid_out_0_82; // @[ifu_mem_ctl.scala 689:10] - wire _T_9327 = _T_9326 | _T_9155; // @[ifu_mem_ctl.scala 689:91] + wire _T_9155 = _T_4753 & ic_tag_valid_out_0_82; // @[ifu_mem_ctl.scala 697:10] + wire _T_9327 = _T_9326 | _T_9155; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_83; // @[Reg.scala 27:20] - wire _T_9157 = _T_4754 & ic_tag_valid_out_0_83; // @[ifu_mem_ctl.scala 689:10] - wire _T_9328 = _T_9327 | _T_9157; // @[ifu_mem_ctl.scala 689:91] + wire _T_9157 = _T_4754 & ic_tag_valid_out_0_83; // @[ifu_mem_ctl.scala 697:10] + wire _T_9328 = _T_9327 | _T_9157; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_84; // @[Reg.scala 27:20] - wire _T_9159 = _T_4755 & ic_tag_valid_out_0_84; // @[ifu_mem_ctl.scala 689:10] - wire _T_9329 = _T_9328 | _T_9159; // @[ifu_mem_ctl.scala 689:91] + wire _T_9159 = _T_4755 & ic_tag_valid_out_0_84; // @[ifu_mem_ctl.scala 697:10] + wire _T_9329 = _T_9328 | _T_9159; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_85; // @[Reg.scala 27:20] - wire _T_9161 = _T_4756 & ic_tag_valid_out_0_85; // @[ifu_mem_ctl.scala 689:10] - wire _T_9330 = _T_9329 | _T_9161; // @[ifu_mem_ctl.scala 689:91] + wire _T_9161 = _T_4756 & ic_tag_valid_out_0_85; // @[ifu_mem_ctl.scala 697:10] + wire _T_9330 = _T_9329 | _T_9161; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_86; // @[Reg.scala 27:20] - wire _T_9163 = _T_4757 & ic_tag_valid_out_0_86; // @[ifu_mem_ctl.scala 689:10] - wire _T_9331 = _T_9330 | _T_9163; // @[ifu_mem_ctl.scala 689:91] + wire _T_9163 = _T_4757 & ic_tag_valid_out_0_86; // @[ifu_mem_ctl.scala 697:10] + wire _T_9331 = _T_9330 | _T_9163; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_87; // @[Reg.scala 27:20] - wire _T_9165 = _T_4758 & ic_tag_valid_out_0_87; // @[ifu_mem_ctl.scala 689:10] - wire _T_9332 = _T_9331 | _T_9165; // @[ifu_mem_ctl.scala 689:91] + wire _T_9165 = _T_4758 & ic_tag_valid_out_0_87; // @[ifu_mem_ctl.scala 697:10] + wire _T_9332 = _T_9331 | _T_9165; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_88; // @[Reg.scala 27:20] - wire _T_9167 = _T_4759 & ic_tag_valid_out_0_88; // @[ifu_mem_ctl.scala 689:10] - wire _T_9333 = _T_9332 | _T_9167; // @[ifu_mem_ctl.scala 689:91] + wire _T_9167 = _T_4759 & ic_tag_valid_out_0_88; // @[ifu_mem_ctl.scala 697:10] + wire _T_9333 = _T_9332 | _T_9167; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_89; // @[Reg.scala 27:20] - wire _T_9169 = _T_4760 & ic_tag_valid_out_0_89; // @[ifu_mem_ctl.scala 689:10] - wire _T_9334 = _T_9333 | _T_9169; // @[ifu_mem_ctl.scala 689:91] + wire _T_9169 = _T_4760 & ic_tag_valid_out_0_89; // @[ifu_mem_ctl.scala 697:10] + wire _T_9334 = _T_9333 | _T_9169; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_90; // @[Reg.scala 27:20] - wire _T_9171 = _T_4761 & ic_tag_valid_out_0_90; // @[ifu_mem_ctl.scala 689:10] - wire _T_9335 = _T_9334 | _T_9171; // @[ifu_mem_ctl.scala 689:91] + wire _T_9171 = _T_4761 & ic_tag_valid_out_0_90; // @[ifu_mem_ctl.scala 697:10] + wire _T_9335 = _T_9334 | _T_9171; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_91; // @[Reg.scala 27:20] - wire _T_9173 = _T_4762 & ic_tag_valid_out_0_91; // @[ifu_mem_ctl.scala 689:10] - wire _T_9336 = _T_9335 | _T_9173; // @[ifu_mem_ctl.scala 689:91] + wire _T_9173 = _T_4762 & ic_tag_valid_out_0_91; // @[ifu_mem_ctl.scala 697:10] + wire _T_9336 = _T_9335 | _T_9173; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_92; // @[Reg.scala 27:20] - wire _T_9175 = _T_4763 & ic_tag_valid_out_0_92; // @[ifu_mem_ctl.scala 689:10] - wire _T_9337 = _T_9336 | _T_9175; // @[ifu_mem_ctl.scala 689:91] + wire _T_9175 = _T_4763 & ic_tag_valid_out_0_92; // @[ifu_mem_ctl.scala 697:10] + wire _T_9337 = _T_9336 | _T_9175; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_93; // @[Reg.scala 27:20] - wire _T_9177 = _T_4764 & ic_tag_valid_out_0_93; // @[ifu_mem_ctl.scala 689:10] - wire _T_9338 = _T_9337 | _T_9177; // @[ifu_mem_ctl.scala 689:91] + wire _T_9177 = _T_4764 & ic_tag_valid_out_0_93; // @[ifu_mem_ctl.scala 697:10] + wire _T_9338 = _T_9337 | _T_9177; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_94; // @[Reg.scala 27:20] - wire _T_9179 = _T_4765 & ic_tag_valid_out_0_94; // @[ifu_mem_ctl.scala 689:10] - wire _T_9339 = _T_9338 | _T_9179; // @[ifu_mem_ctl.scala 689:91] + wire _T_9179 = _T_4765 & ic_tag_valid_out_0_94; // @[ifu_mem_ctl.scala 697:10] + wire _T_9339 = _T_9338 | _T_9179; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_95; // @[Reg.scala 27:20] - wire _T_9181 = _T_4766 & ic_tag_valid_out_0_95; // @[ifu_mem_ctl.scala 689:10] - wire _T_9340 = _T_9339 | _T_9181; // @[ifu_mem_ctl.scala 689:91] + wire _T_9181 = _T_4766 & ic_tag_valid_out_0_95; // @[ifu_mem_ctl.scala 697:10] + wire _T_9340 = _T_9339 | _T_9181; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_96; // @[Reg.scala 27:20] - wire _T_9183 = _T_4767 & ic_tag_valid_out_0_96; // @[ifu_mem_ctl.scala 689:10] - wire _T_9341 = _T_9340 | _T_9183; // @[ifu_mem_ctl.scala 689:91] + wire _T_9183 = _T_4767 & ic_tag_valid_out_0_96; // @[ifu_mem_ctl.scala 697:10] + wire _T_9341 = _T_9340 | _T_9183; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_97; // @[Reg.scala 27:20] - wire _T_9185 = _T_4768 & ic_tag_valid_out_0_97; // @[ifu_mem_ctl.scala 689:10] - wire _T_9342 = _T_9341 | _T_9185; // @[ifu_mem_ctl.scala 689:91] + wire _T_9185 = _T_4768 & ic_tag_valid_out_0_97; // @[ifu_mem_ctl.scala 697:10] + wire _T_9342 = _T_9341 | _T_9185; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_98; // @[Reg.scala 27:20] - wire _T_9187 = _T_4769 & ic_tag_valid_out_0_98; // @[ifu_mem_ctl.scala 689:10] - wire _T_9343 = _T_9342 | _T_9187; // @[ifu_mem_ctl.scala 689:91] + wire _T_9187 = _T_4769 & ic_tag_valid_out_0_98; // @[ifu_mem_ctl.scala 697:10] + wire _T_9343 = _T_9342 | _T_9187; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_99; // @[Reg.scala 27:20] - wire _T_9189 = _T_4770 & ic_tag_valid_out_0_99; // @[ifu_mem_ctl.scala 689:10] - wire _T_9344 = _T_9343 | _T_9189; // @[ifu_mem_ctl.scala 689:91] + wire _T_9189 = _T_4770 & ic_tag_valid_out_0_99; // @[ifu_mem_ctl.scala 697:10] + wire _T_9344 = _T_9343 | _T_9189; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_100; // @[Reg.scala 27:20] - wire _T_9191 = _T_4771 & ic_tag_valid_out_0_100; // @[ifu_mem_ctl.scala 689:10] - wire _T_9345 = _T_9344 | _T_9191; // @[ifu_mem_ctl.scala 689:91] + wire _T_9191 = _T_4771 & ic_tag_valid_out_0_100; // @[ifu_mem_ctl.scala 697:10] + wire _T_9345 = _T_9344 | _T_9191; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_101; // @[Reg.scala 27:20] - wire _T_9193 = _T_4772 & ic_tag_valid_out_0_101; // @[ifu_mem_ctl.scala 689:10] - wire _T_9346 = _T_9345 | _T_9193; // @[ifu_mem_ctl.scala 689:91] + wire _T_9193 = _T_4772 & ic_tag_valid_out_0_101; // @[ifu_mem_ctl.scala 697:10] + wire _T_9346 = _T_9345 | _T_9193; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_102; // @[Reg.scala 27:20] - wire _T_9195 = _T_4773 & ic_tag_valid_out_0_102; // @[ifu_mem_ctl.scala 689:10] - wire _T_9347 = _T_9346 | _T_9195; // @[ifu_mem_ctl.scala 689:91] + wire _T_9195 = _T_4773 & ic_tag_valid_out_0_102; // @[ifu_mem_ctl.scala 697:10] + wire _T_9347 = _T_9346 | _T_9195; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_103; // @[Reg.scala 27:20] - wire _T_9197 = _T_4774 & ic_tag_valid_out_0_103; // @[ifu_mem_ctl.scala 689:10] - wire _T_9348 = _T_9347 | _T_9197; // @[ifu_mem_ctl.scala 689:91] + wire _T_9197 = _T_4774 & ic_tag_valid_out_0_103; // @[ifu_mem_ctl.scala 697:10] + wire _T_9348 = _T_9347 | _T_9197; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_104; // @[Reg.scala 27:20] - wire _T_9199 = _T_4775 & ic_tag_valid_out_0_104; // @[ifu_mem_ctl.scala 689:10] - wire _T_9349 = _T_9348 | _T_9199; // @[ifu_mem_ctl.scala 689:91] + wire _T_9199 = _T_4775 & ic_tag_valid_out_0_104; // @[ifu_mem_ctl.scala 697:10] + wire _T_9349 = _T_9348 | _T_9199; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_105; // @[Reg.scala 27:20] - wire _T_9201 = _T_4776 & ic_tag_valid_out_0_105; // @[ifu_mem_ctl.scala 689:10] - wire _T_9350 = _T_9349 | _T_9201; // @[ifu_mem_ctl.scala 689:91] + wire _T_9201 = _T_4776 & ic_tag_valid_out_0_105; // @[ifu_mem_ctl.scala 697:10] + wire _T_9350 = _T_9349 | _T_9201; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_106; // @[Reg.scala 27:20] - wire _T_9203 = _T_4777 & ic_tag_valid_out_0_106; // @[ifu_mem_ctl.scala 689:10] - wire _T_9351 = _T_9350 | _T_9203; // @[ifu_mem_ctl.scala 689:91] + wire _T_9203 = _T_4777 & ic_tag_valid_out_0_106; // @[ifu_mem_ctl.scala 697:10] + wire _T_9351 = _T_9350 | _T_9203; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_107; // @[Reg.scala 27:20] - wire _T_9205 = _T_4778 & ic_tag_valid_out_0_107; // @[ifu_mem_ctl.scala 689:10] - wire _T_9352 = _T_9351 | _T_9205; // @[ifu_mem_ctl.scala 689:91] + wire _T_9205 = _T_4778 & ic_tag_valid_out_0_107; // @[ifu_mem_ctl.scala 697:10] + wire _T_9352 = _T_9351 | _T_9205; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_108; // @[Reg.scala 27:20] - wire _T_9207 = _T_4779 & ic_tag_valid_out_0_108; // @[ifu_mem_ctl.scala 689:10] - wire _T_9353 = _T_9352 | _T_9207; // @[ifu_mem_ctl.scala 689:91] + wire _T_9207 = _T_4779 & ic_tag_valid_out_0_108; // @[ifu_mem_ctl.scala 697:10] + wire _T_9353 = _T_9352 | _T_9207; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_109; // @[Reg.scala 27:20] - wire _T_9209 = _T_4780 & ic_tag_valid_out_0_109; // @[ifu_mem_ctl.scala 689:10] - wire _T_9354 = _T_9353 | _T_9209; // @[ifu_mem_ctl.scala 689:91] + wire _T_9209 = _T_4780 & ic_tag_valid_out_0_109; // @[ifu_mem_ctl.scala 697:10] + wire _T_9354 = _T_9353 | _T_9209; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_110; // @[Reg.scala 27:20] - wire _T_9211 = _T_4781 & ic_tag_valid_out_0_110; // @[ifu_mem_ctl.scala 689:10] - wire _T_9355 = _T_9354 | _T_9211; // @[ifu_mem_ctl.scala 689:91] + wire _T_9211 = _T_4781 & ic_tag_valid_out_0_110; // @[ifu_mem_ctl.scala 697:10] + wire _T_9355 = _T_9354 | _T_9211; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_111; // @[Reg.scala 27:20] - wire _T_9213 = _T_4782 & ic_tag_valid_out_0_111; // @[ifu_mem_ctl.scala 689:10] - wire _T_9356 = _T_9355 | _T_9213; // @[ifu_mem_ctl.scala 689:91] + wire _T_9213 = _T_4782 & ic_tag_valid_out_0_111; // @[ifu_mem_ctl.scala 697:10] + wire _T_9356 = _T_9355 | _T_9213; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_112; // @[Reg.scala 27:20] - wire _T_9215 = _T_4783 & ic_tag_valid_out_0_112; // @[ifu_mem_ctl.scala 689:10] - wire _T_9357 = _T_9356 | _T_9215; // @[ifu_mem_ctl.scala 689:91] + wire _T_9215 = _T_4783 & ic_tag_valid_out_0_112; // @[ifu_mem_ctl.scala 697:10] + wire _T_9357 = _T_9356 | _T_9215; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_113; // @[Reg.scala 27:20] - wire _T_9217 = _T_4784 & ic_tag_valid_out_0_113; // @[ifu_mem_ctl.scala 689:10] - wire _T_9358 = _T_9357 | _T_9217; // @[ifu_mem_ctl.scala 689:91] + wire _T_9217 = _T_4784 & ic_tag_valid_out_0_113; // @[ifu_mem_ctl.scala 697:10] + wire _T_9358 = _T_9357 | _T_9217; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_114; // @[Reg.scala 27:20] - wire _T_9219 = _T_4785 & ic_tag_valid_out_0_114; // @[ifu_mem_ctl.scala 689:10] - wire _T_9359 = _T_9358 | _T_9219; // @[ifu_mem_ctl.scala 689:91] + wire _T_9219 = _T_4785 & ic_tag_valid_out_0_114; // @[ifu_mem_ctl.scala 697:10] + wire _T_9359 = _T_9358 | _T_9219; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_115; // @[Reg.scala 27:20] - wire _T_9221 = _T_4786 & ic_tag_valid_out_0_115; // @[ifu_mem_ctl.scala 689:10] - wire _T_9360 = _T_9359 | _T_9221; // @[ifu_mem_ctl.scala 689:91] + wire _T_9221 = _T_4786 & ic_tag_valid_out_0_115; // @[ifu_mem_ctl.scala 697:10] + wire _T_9360 = _T_9359 | _T_9221; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_116; // @[Reg.scala 27:20] - wire _T_9223 = _T_4787 & ic_tag_valid_out_0_116; // @[ifu_mem_ctl.scala 689:10] - wire _T_9361 = _T_9360 | _T_9223; // @[ifu_mem_ctl.scala 689:91] + wire _T_9223 = _T_4787 & ic_tag_valid_out_0_116; // @[ifu_mem_ctl.scala 697:10] + wire _T_9361 = _T_9360 | _T_9223; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_117; // @[Reg.scala 27:20] - wire _T_9225 = _T_4788 & ic_tag_valid_out_0_117; // @[ifu_mem_ctl.scala 689:10] - wire _T_9362 = _T_9361 | _T_9225; // @[ifu_mem_ctl.scala 689:91] + wire _T_9225 = _T_4788 & ic_tag_valid_out_0_117; // @[ifu_mem_ctl.scala 697:10] + wire _T_9362 = _T_9361 | _T_9225; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_118; // @[Reg.scala 27:20] - wire _T_9227 = _T_4789 & ic_tag_valid_out_0_118; // @[ifu_mem_ctl.scala 689:10] - wire _T_9363 = _T_9362 | _T_9227; // @[ifu_mem_ctl.scala 689:91] + wire _T_9227 = _T_4789 & ic_tag_valid_out_0_118; // @[ifu_mem_ctl.scala 697:10] + wire _T_9363 = _T_9362 | _T_9227; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_119; // @[Reg.scala 27:20] - wire _T_9229 = _T_4790 & ic_tag_valid_out_0_119; // @[ifu_mem_ctl.scala 689:10] - wire _T_9364 = _T_9363 | _T_9229; // @[ifu_mem_ctl.scala 689:91] + wire _T_9229 = _T_4790 & ic_tag_valid_out_0_119; // @[ifu_mem_ctl.scala 697:10] + wire _T_9364 = _T_9363 | _T_9229; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_120; // @[Reg.scala 27:20] - wire _T_9231 = _T_4791 & ic_tag_valid_out_0_120; // @[ifu_mem_ctl.scala 689:10] - wire _T_9365 = _T_9364 | _T_9231; // @[ifu_mem_ctl.scala 689:91] + wire _T_9231 = _T_4791 & ic_tag_valid_out_0_120; // @[ifu_mem_ctl.scala 697:10] + wire _T_9365 = _T_9364 | _T_9231; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_121; // @[Reg.scala 27:20] - wire _T_9233 = _T_4792 & ic_tag_valid_out_0_121; // @[ifu_mem_ctl.scala 689:10] - wire _T_9366 = _T_9365 | _T_9233; // @[ifu_mem_ctl.scala 689:91] + wire _T_9233 = _T_4792 & ic_tag_valid_out_0_121; // @[ifu_mem_ctl.scala 697:10] + wire _T_9366 = _T_9365 | _T_9233; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_122; // @[Reg.scala 27:20] - wire _T_9235 = _T_4793 & ic_tag_valid_out_0_122; // @[ifu_mem_ctl.scala 689:10] - wire _T_9367 = _T_9366 | _T_9235; // @[ifu_mem_ctl.scala 689:91] + wire _T_9235 = _T_4793 & ic_tag_valid_out_0_122; // @[ifu_mem_ctl.scala 697:10] + wire _T_9367 = _T_9366 | _T_9235; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_123; // @[Reg.scala 27:20] - wire _T_9237 = _T_4794 & ic_tag_valid_out_0_123; // @[ifu_mem_ctl.scala 689:10] - wire _T_9368 = _T_9367 | _T_9237; // @[ifu_mem_ctl.scala 689:91] + wire _T_9237 = _T_4794 & ic_tag_valid_out_0_123; // @[ifu_mem_ctl.scala 697:10] + wire _T_9368 = _T_9367 | _T_9237; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_124; // @[Reg.scala 27:20] - wire _T_9239 = _T_4795 & ic_tag_valid_out_0_124; // @[ifu_mem_ctl.scala 689:10] - wire _T_9369 = _T_9368 | _T_9239; // @[ifu_mem_ctl.scala 689:91] + wire _T_9239 = _T_4795 & ic_tag_valid_out_0_124; // @[ifu_mem_ctl.scala 697:10] + wire _T_9369 = _T_9368 | _T_9239; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_125; // @[Reg.scala 27:20] - wire _T_9241 = _T_4796 & ic_tag_valid_out_0_125; // @[ifu_mem_ctl.scala 689:10] - wire _T_9370 = _T_9369 | _T_9241; // @[ifu_mem_ctl.scala 689:91] + wire _T_9241 = _T_4796 & ic_tag_valid_out_0_125; // @[ifu_mem_ctl.scala 697:10] + wire _T_9370 = _T_9369 | _T_9241; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_126; // @[Reg.scala 27:20] - wire _T_9243 = _T_4797 & ic_tag_valid_out_0_126; // @[ifu_mem_ctl.scala 689:10] - wire _T_9371 = _T_9370 | _T_9243; // @[ifu_mem_ctl.scala 689:91] + wire _T_9243 = _T_4797 & ic_tag_valid_out_0_126; // @[ifu_mem_ctl.scala 697:10] + wire _T_9371 = _T_9370 | _T_9243; // @[ifu_mem_ctl.scala 697:91] reg ic_tag_valid_out_0_127; // @[Reg.scala 27:20] - wire _T_9245 = _T_4798 & ic_tag_valid_out_0_127; // @[ifu_mem_ctl.scala 689:10] - wire _T_9372 = _T_9371 | _T_9245; // @[ifu_mem_ctl.scala 689:91] + wire _T_9245 = _T_4798 & ic_tag_valid_out_0_127; // @[ifu_mem_ctl.scala 697:10] + wire _T_9372 = _T_9371 | _T_9245; // @[ifu_mem_ctl.scala 697:91] wire [1:0] ic_tag_valid_unq = {_T_9755,_T_9372}; // @[Cat.scala 29:58] - reg [1:0] ic_debug_way_ff; // @[ifu_mem_ctl.scala 761:53] - reg ic_debug_rd_en_ff; // @[ifu_mem_ctl.scala 763:54] + reg [1:0] ic_debug_way_ff; // @[ifu_mem_ctl.scala 768:53] + reg ic_debug_rd_en_ff; // @[ifu_mem_ctl.scala 770:54] wire [1:0] _T_9795 = ic_debug_rd_en_ff ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_9796 = ic_debug_way_ff & _T_9795; // @[ifu_mem_ctl.scala 744:67] - wire [1:0] _T_9797 = ic_tag_valid_unq & _T_9796; // @[ifu_mem_ctl.scala 744:48] - wire ic_debug_tag_val_rd_out = |_T_9797; // @[ifu_mem_ctl.scala 744:115] + wire [1:0] _T_9796 = ic_debug_way_ff & _T_9795; // @[ifu_mem_ctl.scala 751:67] + wire [1:0] _T_9797 = ic_tag_valid_unq & _T_9796; // @[ifu_mem_ctl.scala 751:48] + wire ic_debug_tag_val_rd_out = |_T_9797; // @[ifu_mem_ctl.scala 751:115] wire [70:0] _T_1211 = {2'h0,io_ic_tag_debug_rd_data[25:21],32'h0,io_ic_tag_debug_rd_data[20:0],6'h0,way_status,3'h0,ic_debug_tag_val_rd_out}; // @[Cat.scala 29:58] - reg [70:0] _T_1212; // @[ifu_mem_ctl.scala 277:76] - wire _T_1250 = ~ifu_byp_data_err_new; // @[ifu_mem_ctl.scala 293:98] - wire sel_byp_data = _T_1254 & _T_1250; // @[ifu_mem_ctl.scala 293:96] - wire _T_1257 = sel_byp_data | fetch_req_iccm_f; // @[ifu_mem_ctl.scala 298:46] - wire final_data_sel1_0 = _T_1257 | sel_ic_data; // @[ifu_mem_ctl.scala 298:62] + reg [70:0] _T_1212; // @[ifu_mem_ctl.scala 263:76] + wire _T_1250 = ~ifu_byp_data_err_new; // @[ifu_mem_ctl.scala 279:98] + wire sel_byp_data = _T_1254 & _T_1250; // @[ifu_mem_ctl.scala 279:96] + wire _T_1257 = sel_byp_data | fetch_req_iccm_f; // @[ifu_mem_ctl.scala 284:46] + wire final_data_sel1_0 = _T_1257 | sel_ic_data; // @[ifu_mem_ctl.scala 284:62] wire [63:0] _T_1263 = final_data_sel1_0 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] ic_final_data = _T_1263 & io_ic_rd_data; // @[ifu_mem_ctl.scala 302:92] + wire [63:0] ic_final_data = _T_1263 & io_ic_rd_data; // @[ifu_mem_ctl.scala 288:92] wire [63:0] _T_1265 = fetch_req_iccm_f ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_1266 = _T_1265 & io_iccm_rd_data; // @[ifu_mem_ctl.scala 306:69] + wire [63:0] _T_1266 = _T_1265 & io_iccm_rd_data; // @[ifu_mem_ctl.scala 292:69] wire [63:0] _T_1268 = sel_byp_data ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] wire [3:0] byp_fetch_index_inc_0 = {byp_fetch_index_inc,1'h0}; // @[Cat.scala 29:58] - wire _T_1662 = byp_fetch_index_inc_0 == 4'h0; // @[ifu_mem_ctl.scala 372:73] + wire _T_1662 = byp_fetch_index_inc_0 == 4'h0; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1710 = _T_1662 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72] - wire _T_1665 = byp_fetch_index_inc_0 == 4'h1; // @[ifu_mem_ctl.scala 372:73] + wire _T_1665 = byp_fetch_index_inc_0 == 4'h1; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1711 = _T_1665 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1726 = _T_1710 | _T_1711; // @[Mux.scala 27:72] - wire _T_1668 = byp_fetch_index_inc_0 == 4'h2; // @[ifu_mem_ctl.scala 372:73] + wire _T_1668 = byp_fetch_index_inc_0 == 4'h2; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1712 = _T_1668 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1727 = _T_1726 | _T_1712; // @[Mux.scala 27:72] - wire _T_1671 = byp_fetch_index_inc_0 == 4'h3; // @[ifu_mem_ctl.scala 372:73] + wire _T_1671 = byp_fetch_index_inc_0 == 4'h3; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1713 = _T_1671 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1728 = _T_1727 | _T_1713; // @[Mux.scala 27:72] - wire _T_1674 = byp_fetch_index_inc_0 == 4'h4; // @[ifu_mem_ctl.scala 372:73] + wire _T_1674 = byp_fetch_index_inc_0 == 4'h4; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1714 = _T_1674 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1729 = _T_1728 | _T_1714; // @[Mux.scala 27:72] - wire _T_1677 = byp_fetch_index_inc_0 == 4'h5; // @[ifu_mem_ctl.scala 372:73] + wire _T_1677 = byp_fetch_index_inc_0 == 4'h5; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1715 = _T_1677 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1730 = _T_1729 | _T_1715; // @[Mux.scala 27:72] - wire _T_1680 = byp_fetch_index_inc_0 == 4'h6; // @[ifu_mem_ctl.scala 372:73] + wire _T_1680 = byp_fetch_index_inc_0 == 4'h6; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1716 = _T_1680 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1731 = _T_1730 | _T_1716; // @[Mux.scala 27:72] - wire _T_1683 = byp_fetch_index_inc_0 == 4'h7; // @[ifu_mem_ctl.scala 372:73] + wire _T_1683 = byp_fetch_index_inc_0 == 4'h7; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1717 = _T_1683 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1732 = _T_1731 | _T_1717; // @[Mux.scala 27:72] - wire _T_1686 = byp_fetch_index_inc_0 == 4'h8; // @[ifu_mem_ctl.scala 372:73] + wire _T_1686 = byp_fetch_index_inc_0 == 4'h8; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1718 = _T_1686 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1733 = _T_1732 | _T_1718; // @[Mux.scala 27:72] - wire _T_1689 = byp_fetch_index_inc_0 == 4'h9; // @[ifu_mem_ctl.scala 372:73] + wire _T_1689 = byp_fetch_index_inc_0 == 4'h9; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1719 = _T_1689 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1734 = _T_1733 | _T_1719; // @[Mux.scala 27:72] - wire _T_1692 = byp_fetch_index_inc_0 == 4'ha; // @[ifu_mem_ctl.scala 372:73] + wire _T_1692 = byp_fetch_index_inc_0 == 4'ha; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1720 = _T_1692 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1735 = _T_1734 | _T_1720; // @[Mux.scala 27:72] - wire _T_1695 = byp_fetch_index_inc_0 == 4'hb; // @[ifu_mem_ctl.scala 372:73] + wire _T_1695 = byp_fetch_index_inc_0 == 4'hb; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1721 = _T_1695 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1736 = _T_1735 | _T_1721; // @[Mux.scala 27:72] - wire _T_1698 = byp_fetch_index_inc_0 == 4'hc; // @[ifu_mem_ctl.scala 372:73] + wire _T_1698 = byp_fetch_index_inc_0 == 4'hc; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1722 = _T_1698 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1737 = _T_1736 | _T_1722; // @[Mux.scala 27:72] - wire _T_1701 = byp_fetch_index_inc_0 == 4'hd; // @[ifu_mem_ctl.scala 372:73] + wire _T_1701 = byp_fetch_index_inc_0 == 4'hd; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1723 = _T_1701 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1738 = _T_1737 | _T_1723; // @[Mux.scala 27:72] - wire _T_1704 = byp_fetch_index_inc_0 == 4'he; // @[ifu_mem_ctl.scala 372:73] + wire _T_1704 = byp_fetch_index_inc_0 == 4'he; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1724 = _T_1704 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1739 = _T_1738 | _T_1724; // @[Mux.scala 27:72] - wire _T_1707 = byp_fetch_index_inc_0 == 4'hf; // @[ifu_mem_ctl.scala 372:73] + wire _T_1707 = byp_fetch_index_inc_0 == 4'hf; // @[ifu_mem_ctl.scala 358:73] wire [15:0] _T_1725 = _T_1707 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1740 = _T_1739 | _T_1725; // @[Mux.scala 27:72] wire [3:0] byp_fetch_index_1 = {ifu_fetch_addr_int_f[4:2],1'h1}; // @[Cat.scala 29:58] - wire _T_1742 = byp_fetch_index_1 == 4'h0; // @[ifu_mem_ctl.scala 372:179] + wire _T_1742 = byp_fetch_index_1 == 4'h0; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1790 = _T_1742 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] - wire _T_1745 = byp_fetch_index_1 == 4'h1; // @[ifu_mem_ctl.scala 372:179] + wire _T_1745 = byp_fetch_index_1 == 4'h1; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1791 = _T_1745 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1806 = _T_1790 | _T_1791; // @[Mux.scala 27:72] - wire _T_1748 = byp_fetch_index_1 == 4'h2; // @[ifu_mem_ctl.scala 372:179] + wire _T_1748 = byp_fetch_index_1 == 4'h2; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1792 = _T_1748 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1807 = _T_1806 | _T_1792; // @[Mux.scala 27:72] - wire _T_1751 = byp_fetch_index_1 == 4'h3; // @[ifu_mem_ctl.scala 372:179] + wire _T_1751 = byp_fetch_index_1 == 4'h3; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1793 = _T_1751 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1808 = _T_1807 | _T_1793; // @[Mux.scala 27:72] - wire _T_1754 = byp_fetch_index_1 == 4'h4; // @[ifu_mem_ctl.scala 372:179] + wire _T_1754 = byp_fetch_index_1 == 4'h4; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1794 = _T_1754 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1809 = _T_1808 | _T_1794; // @[Mux.scala 27:72] - wire _T_1757 = byp_fetch_index_1 == 4'h5; // @[ifu_mem_ctl.scala 372:179] + wire _T_1757 = byp_fetch_index_1 == 4'h5; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1795 = _T_1757 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1810 = _T_1809 | _T_1795; // @[Mux.scala 27:72] - wire _T_1760 = byp_fetch_index_1 == 4'h6; // @[ifu_mem_ctl.scala 372:179] + wire _T_1760 = byp_fetch_index_1 == 4'h6; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1796 = _T_1760 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1811 = _T_1810 | _T_1796; // @[Mux.scala 27:72] - wire _T_1763 = byp_fetch_index_1 == 4'h7; // @[ifu_mem_ctl.scala 372:179] + wire _T_1763 = byp_fetch_index_1 == 4'h7; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1797 = _T_1763 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1812 = _T_1811 | _T_1797; // @[Mux.scala 27:72] - wire _T_1766 = byp_fetch_index_1 == 4'h8; // @[ifu_mem_ctl.scala 372:179] + wire _T_1766 = byp_fetch_index_1 == 4'h8; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1798 = _T_1766 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1813 = _T_1812 | _T_1798; // @[Mux.scala 27:72] - wire _T_1769 = byp_fetch_index_1 == 4'h9; // @[ifu_mem_ctl.scala 372:179] + wire _T_1769 = byp_fetch_index_1 == 4'h9; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1799 = _T_1769 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1814 = _T_1813 | _T_1799; // @[Mux.scala 27:72] - wire _T_1772 = byp_fetch_index_1 == 4'ha; // @[ifu_mem_ctl.scala 372:179] + wire _T_1772 = byp_fetch_index_1 == 4'ha; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1800 = _T_1772 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1815 = _T_1814 | _T_1800; // @[Mux.scala 27:72] - wire _T_1775 = byp_fetch_index_1 == 4'hb; // @[ifu_mem_ctl.scala 372:179] + wire _T_1775 = byp_fetch_index_1 == 4'hb; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1801 = _T_1775 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1816 = _T_1815 | _T_1801; // @[Mux.scala 27:72] - wire _T_1778 = byp_fetch_index_1 == 4'hc; // @[ifu_mem_ctl.scala 372:179] + wire _T_1778 = byp_fetch_index_1 == 4'hc; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1802 = _T_1778 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1817 = _T_1816 | _T_1802; // @[Mux.scala 27:72] - wire _T_1781 = byp_fetch_index_1 == 4'hd; // @[ifu_mem_ctl.scala 372:179] + wire _T_1781 = byp_fetch_index_1 == 4'hd; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1803 = _T_1781 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1818 = _T_1817 | _T_1803; // @[Mux.scala 27:72] - wire _T_1784 = byp_fetch_index_1 == 4'he; // @[ifu_mem_ctl.scala 372:179] + wire _T_1784 = byp_fetch_index_1 == 4'he; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1804 = _T_1784 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1819 = _T_1818 | _T_1804; // @[Mux.scala 27:72] - wire _T_1787 = byp_fetch_index_1 == 4'hf; // @[ifu_mem_ctl.scala 372:179] + wire _T_1787 = byp_fetch_index_1 == 4'hf; // @[ifu_mem_ctl.scala 358:179] wire [31:0] _T_1805 = _T_1787 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1820 = _T_1819 | _T_1805; // @[Mux.scala 27:72] wire [3:0] byp_fetch_index_0 = {ifu_fetch_addr_int_f[4:2],1'h0}; // @[Cat.scala 29:58] - wire _T_1822 = byp_fetch_index_0 == 4'h0; // @[ifu_mem_ctl.scala 372:285] + wire _T_1822 = byp_fetch_index_0 == 4'h0; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1870 = _T_1822 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] - wire _T_1825 = byp_fetch_index_0 == 4'h1; // @[ifu_mem_ctl.scala 372:285] + wire _T_1825 = byp_fetch_index_0 == 4'h1; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1871 = _T_1825 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1886 = _T_1870 | _T_1871; // @[Mux.scala 27:72] - wire _T_1828 = byp_fetch_index_0 == 4'h2; // @[ifu_mem_ctl.scala 372:285] + wire _T_1828 = byp_fetch_index_0 == 4'h2; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1872 = _T_1828 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1887 = _T_1886 | _T_1872; // @[Mux.scala 27:72] - wire _T_1831 = byp_fetch_index_0 == 4'h3; // @[ifu_mem_ctl.scala 372:285] + wire _T_1831 = byp_fetch_index_0 == 4'h3; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1873 = _T_1831 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1888 = _T_1887 | _T_1873; // @[Mux.scala 27:72] - wire _T_1834 = byp_fetch_index_0 == 4'h4; // @[ifu_mem_ctl.scala 372:285] + wire _T_1834 = byp_fetch_index_0 == 4'h4; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1874 = _T_1834 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1889 = _T_1888 | _T_1874; // @[Mux.scala 27:72] - wire _T_1837 = byp_fetch_index_0 == 4'h5; // @[ifu_mem_ctl.scala 372:285] + wire _T_1837 = byp_fetch_index_0 == 4'h5; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1875 = _T_1837 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1890 = _T_1889 | _T_1875; // @[Mux.scala 27:72] - wire _T_1840 = byp_fetch_index_0 == 4'h6; // @[ifu_mem_ctl.scala 372:285] + wire _T_1840 = byp_fetch_index_0 == 4'h6; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1876 = _T_1840 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1891 = _T_1890 | _T_1876; // @[Mux.scala 27:72] - wire _T_1843 = byp_fetch_index_0 == 4'h7; // @[ifu_mem_ctl.scala 372:285] + wire _T_1843 = byp_fetch_index_0 == 4'h7; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1877 = _T_1843 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1892 = _T_1891 | _T_1877; // @[Mux.scala 27:72] - wire _T_1846 = byp_fetch_index_0 == 4'h8; // @[ifu_mem_ctl.scala 372:285] + wire _T_1846 = byp_fetch_index_0 == 4'h8; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1878 = _T_1846 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1893 = _T_1892 | _T_1878; // @[Mux.scala 27:72] - wire _T_1849 = byp_fetch_index_0 == 4'h9; // @[ifu_mem_ctl.scala 372:285] + wire _T_1849 = byp_fetch_index_0 == 4'h9; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1879 = _T_1849 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1894 = _T_1893 | _T_1879; // @[Mux.scala 27:72] - wire _T_1852 = byp_fetch_index_0 == 4'ha; // @[ifu_mem_ctl.scala 372:285] + wire _T_1852 = byp_fetch_index_0 == 4'ha; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1880 = _T_1852 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1895 = _T_1894 | _T_1880; // @[Mux.scala 27:72] - wire _T_1855 = byp_fetch_index_0 == 4'hb; // @[ifu_mem_ctl.scala 372:285] + wire _T_1855 = byp_fetch_index_0 == 4'hb; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1881 = _T_1855 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1896 = _T_1895 | _T_1881; // @[Mux.scala 27:72] - wire _T_1858 = byp_fetch_index_0 == 4'hc; // @[ifu_mem_ctl.scala 372:285] + wire _T_1858 = byp_fetch_index_0 == 4'hc; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1882 = _T_1858 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1897 = _T_1896 | _T_1882; // @[Mux.scala 27:72] - wire _T_1861 = byp_fetch_index_0 == 4'hd; // @[ifu_mem_ctl.scala 372:285] + wire _T_1861 = byp_fetch_index_0 == 4'hd; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1883 = _T_1861 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1898 = _T_1897 | _T_1883; // @[Mux.scala 27:72] - wire _T_1864 = byp_fetch_index_0 == 4'he; // @[ifu_mem_ctl.scala 372:285] + wire _T_1864 = byp_fetch_index_0 == 4'he; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1884 = _T_1864 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1899 = _T_1898 | _T_1884; // @[Mux.scala 27:72] - wire _T_1867 = byp_fetch_index_0 == 4'hf; // @[ifu_mem_ctl.scala 372:285] + wire _T_1867 = byp_fetch_index_0 == 4'hf; // @[ifu_mem_ctl.scala 358:285] wire [31:0] _T_1885 = _T_1867 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1900 = _T_1899 | _T_1885; // @[Mux.scala 27:72] wire [79:0] _T_1903 = {_T_1740,_T_1820,_T_1900}; // @[Cat.scala 29:58] wire [3:0] byp_fetch_index_inc_1 = {byp_fetch_index_inc,1'h1}; // @[Cat.scala 29:58] - wire _T_1904 = byp_fetch_index_inc_1 == 4'h0; // @[ifu_mem_ctl.scala 373:73] + wire _T_1904 = byp_fetch_index_inc_1 == 4'h0; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1952 = _T_1904 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72] - wire _T_1907 = byp_fetch_index_inc_1 == 4'h1; // @[ifu_mem_ctl.scala 373:73] + wire _T_1907 = byp_fetch_index_inc_1 == 4'h1; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1953 = _T_1907 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1968 = _T_1952 | _T_1953; // @[Mux.scala 27:72] - wire _T_1910 = byp_fetch_index_inc_1 == 4'h2; // @[ifu_mem_ctl.scala 373:73] + wire _T_1910 = byp_fetch_index_inc_1 == 4'h2; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1954 = _T_1910 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1969 = _T_1968 | _T_1954; // @[Mux.scala 27:72] - wire _T_1913 = byp_fetch_index_inc_1 == 4'h3; // @[ifu_mem_ctl.scala 373:73] + wire _T_1913 = byp_fetch_index_inc_1 == 4'h3; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1955 = _T_1913 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1970 = _T_1969 | _T_1955; // @[Mux.scala 27:72] - wire _T_1916 = byp_fetch_index_inc_1 == 4'h4; // @[ifu_mem_ctl.scala 373:73] + wire _T_1916 = byp_fetch_index_inc_1 == 4'h4; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1956 = _T_1916 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1971 = _T_1970 | _T_1956; // @[Mux.scala 27:72] - wire _T_1919 = byp_fetch_index_inc_1 == 4'h5; // @[ifu_mem_ctl.scala 373:73] + wire _T_1919 = byp_fetch_index_inc_1 == 4'h5; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1957 = _T_1919 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1972 = _T_1971 | _T_1957; // @[Mux.scala 27:72] - wire _T_1922 = byp_fetch_index_inc_1 == 4'h6; // @[ifu_mem_ctl.scala 373:73] + wire _T_1922 = byp_fetch_index_inc_1 == 4'h6; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1958 = _T_1922 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1973 = _T_1972 | _T_1958; // @[Mux.scala 27:72] - wire _T_1925 = byp_fetch_index_inc_1 == 4'h7; // @[ifu_mem_ctl.scala 373:73] + wire _T_1925 = byp_fetch_index_inc_1 == 4'h7; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1959 = _T_1925 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1974 = _T_1973 | _T_1959; // @[Mux.scala 27:72] - wire _T_1928 = byp_fetch_index_inc_1 == 4'h8; // @[ifu_mem_ctl.scala 373:73] + wire _T_1928 = byp_fetch_index_inc_1 == 4'h8; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1960 = _T_1928 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1975 = _T_1974 | _T_1960; // @[Mux.scala 27:72] - wire _T_1931 = byp_fetch_index_inc_1 == 4'h9; // @[ifu_mem_ctl.scala 373:73] + wire _T_1931 = byp_fetch_index_inc_1 == 4'h9; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1961 = _T_1931 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1976 = _T_1975 | _T_1961; // @[Mux.scala 27:72] - wire _T_1934 = byp_fetch_index_inc_1 == 4'ha; // @[ifu_mem_ctl.scala 373:73] + wire _T_1934 = byp_fetch_index_inc_1 == 4'ha; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1962 = _T_1934 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1977 = _T_1976 | _T_1962; // @[Mux.scala 27:72] - wire _T_1937 = byp_fetch_index_inc_1 == 4'hb; // @[ifu_mem_ctl.scala 373:73] + wire _T_1937 = byp_fetch_index_inc_1 == 4'hb; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1963 = _T_1937 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1978 = _T_1977 | _T_1963; // @[Mux.scala 27:72] - wire _T_1940 = byp_fetch_index_inc_1 == 4'hc; // @[ifu_mem_ctl.scala 373:73] + wire _T_1940 = byp_fetch_index_inc_1 == 4'hc; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1964 = _T_1940 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1979 = _T_1978 | _T_1964; // @[Mux.scala 27:72] - wire _T_1943 = byp_fetch_index_inc_1 == 4'hd; // @[ifu_mem_ctl.scala 373:73] + wire _T_1943 = byp_fetch_index_inc_1 == 4'hd; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1965 = _T_1943 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1980 = _T_1979 | _T_1965; // @[Mux.scala 27:72] - wire _T_1946 = byp_fetch_index_inc_1 == 4'he; // @[ifu_mem_ctl.scala 373:73] + wire _T_1946 = byp_fetch_index_inc_1 == 4'he; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1966 = _T_1946 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1981 = _T_1980 | _T_1966; // @[Mux.scala 27:72] - wire _T_1949 = byp_fetch_index_inc_1 == 4'hf; // @[ifu_mem_ctl.scala 373:73] + wire _T_1949 = byp_fetch_index_inc_1 == 4'hf; // @[ifu_mem_ctl.scala 359:73] wire [15:0] _T_1967 = _T_1949 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1982 = _T_1981 | _T_1967; // @[Mux.scala 27:72] wire [31:0] _T_2032 = _T_1662 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] @@ -3316,51 +3316,51 @@ module ifu_mem_ctl( wire [31:0] _T_2047 = _T_1707 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2062 = _T_2061 | _T_2047; // @[Mux.scala 27:72] wire [79:0] _T_2145 = {_T_1982,_T_2062,_T_1820}; // @[Cat.scala 29:58] - wire [79:0] ic_byp_data_only_pre_new = _T_1612 ? _T_1903 : _T_2145; // @[ifu_mem_ctl.scala 371:37] + wire [79:0] ic_byp_data_only_pre_new = _T_1612 ? _T_1903 : _T_2145; // @[ifu_mem_ctl.scala 357:37] wire [79:0] _T_2150 = {16'h0,ic_byp_data_only_pre_new[79:16]}; // @[Cat.scala 29:58] - wire [79:0] ic_byp_data_only_new = _T_1614 ? ic_byp_data_only_pre_new : _T_2150; // @[ifu_mem_ctl.scala 375:30] - wire [79:0] _GEN_437 = {{16'd0}, _T_1268}; // @[ifu_mem_ctl.scala 306:114] - wire [79:0] _T_1269 = _GEN_437 & ic_byp_data_only_new; // @[ifu_mem_ctl.scala 306:114] - wire [79:0] _GEN_438 = {{16'd0}, _T_1266}; // @[ifu_mem_ctl.scala 306:88] - wire [79:0] ic_premux_data_temp = _GEN_438 | _T_1269; // @[ifu_mem_ctl.scala 306:88] - wire fetch_req_f_qual = io_ic_hit_f & _T_319; // @[ifu_mem_ctl.scala 313:38] - reg ifc_region_acc_fault_memory_f; // @[ifu_mem_ctl.scala 776:66] - wire [1:0] _T_1277 = ifc_region_acc_fault_memory_f ? 2'h3 : 2'h0; // @[ifu_mem_ctl.scala 318:10] - wire [1:0] _T_1278 = ifc_region_acc_fault_f ? 2'h2 : _T_1277; // @[ifu_mem_ctl.scala 317:8] - wire _T_1280 = fetch_req_f_qual & io_ifu_bp_inst_mask_f; // @[ifu_mem_ctl.scala 319:45] - wire _T_1282 = byp_fetch_index == 5'h1f; // @[ifu_mem_ctl.scala 319:80] - wire _T_1283 = ~_T_1282; // @[ifu_mem_ctl.scala 319:71] - wire _T_1284 = _T_1280 & _T_1283; // @[ifu_mem_ctl.scala 319:69] - wire _T_1285 = err_stop_state != 2'h2; // @[ifu_mem_ctl.scala 319:131] - wire _T_1286 = _T_1284 & _T_1285; // @[ifu_mem_ctl.scala 319:114] + wire [79:0] ic_byp_data_only_new = _T_1614 ? ic_byp_data_only_pre_new : _T_2150; // @[ifu_mem_ctl.scala 361:30] + wire [79:0] _GEN_437 = {{16'd0}, _T_1268}; // @[ifu_mem_ctl.scala 292:114] + wire [79:0] _T_1269 = _GEN_437 & ic_byp_data_only_new; // @[ifu_mem_ctl.scala 292:114] + wire [79:0] _GEN_438 = {{16'd0}, _T_1266}; // @[ifu_mem_ctl.scala 292:88] + wire [79:0] ic_premux_data_temp = _GEN_438 | _T_1269; // @[ifu_mem_ctl.scala 292:88] + wire fetch_req_f_qual = io_ic_hit_f & _T_319; // @[ifu_mem_ctl.scala 299:38] + reg ifc_region_acc_fault_memory_f; // @[ifu_mem_ctl.scala 784:66] + wire [1:0] _T_1277 = ifc_region_acc_fault_memory_f ? 2'h3 : 2'h0; // @[ifu_mem_ctl.scala 304:10] + wire [1:0] _T_1278 = ifc_region_acc_fault_f ? 2'h2 : _T_1277; // @[ifu_mem_ctl.scala 303:8] + wire _T_1280 = fetch_req_f_qual & io_ifu_bp_inst_mask_f; // @[ifu_mem_ctl.scala 305:45] + wire _T_1282 = byp_fetch_index == 5'h1f; // @[ifu_mem_ctl.scala 305:80] + wire _T_1283 = ~_T_1282; // @[ifu_mem_ctl.scala 305:71] + wire _T_1284 = _T_1280 & _T_1283; // @[ifu_mem_ctl.scala 305:69] + wire _T_1285 = err_stop_state != 2'h2; // @[ifu_mem_ctl.scala 305:131] + wire _T_1286 = _T_1284 & _T_1285; // @[ifu_mem_ctl.scala 305:114] wire [6:0] _T_1358 = {ic_miss_buff_data_valid_in_7,ic_miss_buff_data_valid_in_6,ic_miss_buff_data_valid_in_5,ic_miss_buff_data_valid_in_4,ic_miss_buff_data_valid_in_3,ic_miss_buff_data_valid_in_2,ic_miss_buff_data_valid_in_1}; // @[Cat.scala 29:58] - wire _T_1364 = ic_miss_buff_data_error[0] & _T_1330; // @[ifu_mem_ctl.scala 338:32] - wire _T_2690 = |io_ifu_axi_r_bits_resp; // @[ifu_mem_ctl.scala 550:47] - wire _T_2691 = _T_2690 & _T_13; // @[ifu_mem_ctl.scala 550:50] - wire bus_ifu_wr_data_error = _T_2691 & miss_pending; // @[ifu_mem_ctl.scala 550:68] - wire ic_miss_buff_data_error_in_0 = write_fill_data_0 ? bus_ifu_wr_data_error : _T_1364; // @[ifu_mem_ctl.scala 337:72] - wire _T_1368 = ic_miss_buff_data_error[1] & _T_1330; // @[ifu_mem_ctl.scala 338:32] - wire ic_miss_buff_data_error_in_1 = write_fill_data_1 ? bus_ifu_wr_data_error : _T_1368; // @[ifu_mem_ctl.scala 337:72] - wire _T_1372 = ic_miss_buff_data_error[2] & _T_1330; // @[ifu_mem_ctl.scala 338:32] - wire ic_miss_buff_data_error_in_2 = write_fill_data_2 ? bus_ifu_wr_data_error : _T_1372; // @[ifu_mem_ctl.scala 337:72] - wire _T_1376 = ic_miss_buff_data_error[3] & _T_1330; // @[ifu_mem_ctl.scala 338:32] - wire ic_miss_buff_data_error_in_3 = write_fill_data_3 ? bus_ifu_wr_data_error : _T_1376; // @[ifu_mem_ctl.scala 337:72] - wire _T_1380 = ic_miss_buff_data_error[4] & _T_1330; // @[ifu_mem_ctl.scala 338:32] - wire ic_miss_buff_data_error_in_4 = write_fill_data_4 ? bus_ifu_wr_data_error : _T_1380; // @[ifu_mem_ctl.scala 337:72] - wire _T_1384 = ic_miss_buff_data_error[5] & _T_1330; // @[ifu_mem_ctl.scala 338:32] - wire ic_miss_buff_data_error_in_5 = write_fill_data_5 ? bus_ifu_wr_data_error : _T_1384; // @[ifu_mem_ctl.scala 337:72] - wire _T_1388 = ic_miss_buff_data_error[6] & _T_1330; // @[ifu_mem_ctl.scala 338:32] - wire ic_miss_buff_data_error_in_6 = write_fill_data_6 ? bus_ifu_wr_data_error : _T_1388; // @[ifu_mem_ctl.scala 337:72] - wire _T_1392 = ic_miss_buff_data_error[7] & _T_1330; // @[ifu_mem_ctl.scala 338:32] - wire ic_miss_buff_data_error_in_7 = write_fill_data_7 ? bus_ifu_wr_data_error : _T_1392; // @[ifu_mem_ctl.scala 337:72] + wire _T_1364 = ic_miss_buff_data_error[0] & _T_1330; // @[ifu_mem_ctl.scala 324:32] + wire _T_2690 = |io_ifu_axi_r_bits_resp; // @[ifu_mem_ctl.scala 558:47] + wire _T_2691 = _T_2690 & _T_13; // @[ifu_mem_ctl.scala 558:50] + wire bus_ifu_wr_data_error = _T_2691 & miss_pending; // @[ifu_mem_ctl.scala 558:68] + wire ic_miss_buff_data_error_in_0 = write_fill_data_0 ? bus_ifu_wr_data_error : _T_1364; // @[ifu_mem_ctl.scala 323:72] + wire _T_1368 = ic_miss_buff_data_error[1] & _T_1330; // @[ifu_mem_ctl.scala 324:32] + wire ic_miss_buff_data_error_in_1 = write_fill_data_1 ? bus_ifu_wr_data_error : _T_1368; // @[ifu_mem_ctl.scala 323:72] + wire _T_1372 = ic_miss_buff_data_error[2] & _T_1330; // @[ifu_mem_ctl.scala 324:32] + wire ic_miss_buff_data_error_in_2 = write_fill_data_2 ? bus_ifu_wr_data_error : _T_1372; // @[ifu_mem_ctl.scala 323:72] + wire _T_1376 = ic_miss_buff_data_error[3] & _T_1330; // @[ifu_mem_ctl.scala 324:32] + wire ic_miss_buff_data_error_in_3 = write_fill_data_3 ? bus_ifu_wr_data_error : _T_1376; // @[ifu_mem_ctl.scala 323:72] + wire _T_1380 = ic_miss_buff_data_error[4] & _T_1330; // @[ifu_mem_ctl.scala 324:32] + wire ic_miss_buff_data_error_in_4 = write_fill_data_4 ? bus_ifu_wr_data_error : _T_1380; // @[ifu_mem_ctl.scala 323:72] + wire _T_1384 = ic_miss_buff_data_error[5] & _T_1330; // @[ifu_mem_ctl.scala 324:32] + wire ic_miss_buff_data_error_in_5 = write_fill_data_5 ? bus_ifu_wr_data_error : _T_1384; // @[ifu_mem_ctl.scala 323:72] + wire _T_1388 = ic_miss_buff_data_error[6] & _T_1330; // @[ifu_mem_ctl.scala 324:32] + wire ic_miss_buff_data_error_in_6 = write_fill_data_6 ? bus_ifu_wr_data_error : _T_1388; // @[ifu_mem_ctl.scala 323:72] + wire _T_1392 = ic_miss_buff_data_error[7] & _T_1330; // @[ifu_mem_ctl.scala 324:32] + wire ic_miss_buff_data_error_in_7 = write_fill_data_7 ? bus_ifu_wr_data_error : _T_1392; // @[ifu_mem_ctl.scala 323:72] wire [6:0] _T_1398 = {ic_miss_buff_data_error_in_7,ic_miss_buff_data_error_in_6,ic_miss_buff_data_error_in_5,ic_miss_buff_data_error_in_4,ic_miss_buff_data_error_in_3,ic_miss_buff_data_error_in_2,ic_miss_buff_data_error_in_1}; // @[Cat.scala 29:58] reg [6:0] perr_ic_index_ff; // @[Reg.scala 27:20] wire _T_2500 = 3'h0 == perr_state; // @[Conditional.scala 37:30] - wire _T_2508 = _T_6 & _T_319; // @[ifu_mem_ctl.scala 418:82] - wire _T_2509 = _T_2508 | io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 418:105] - wire _T_2511 = _T_2509 & _T_2623; // @[ifu_mem_ctl.scala 418:129] + wire _T_2508 = _T_6 & _T_319; // @[ifu_mem_ctl.scala 405:82] + wire _T_2509 = _T_2508 | io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 405:105] + wire _T_2511 = _T_2509 & _T_2623; // @[ifu_mem_ctl.scala 405:129] wire _T_2512 = 3'h1 == perr_state; // @[Conditional.scala 37:30] - wire _T_2513 = io_dec_tlu_flush_lower_wb | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 423:50] + wire _T_2513 = io_dec_tlu_flush_lower_wb | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 410:50] wire _T_2515 = 3'h2 == perr_state; // @[Conditional.scala 37:30] wire _T_2522 = 3'h4 == perr_state; // @[Conditional.scala 37:30] wire _T_2524 = 3'h3 == perr_state; // @[Conditional.scala 37:30] @@ -3369,91 +3369,91 @@ module ifu_mem_ctl( wire _GEN_25 = _T_2512 ? _T_2513 : _GEN_23; // @[Conditional.scala 39:67] wire perr_state_en = _T_2500 ? _T_2511 : _GEN_25; // @[Conditional.scala 40:58] wire perr_sb_write_status = _T_2500 & perr_state_en; // @[Conditional.scala 40:58] - wire _T_2514 = io_dec_tlu_flush_lower_wb & io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 424:56] + wire _T_2514 = io_dec_tlu_flush_lower_wb & io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 411:56] wire _GEN_26 = _T_2512 & _T_2514; // @[Conditional.scala 39:67] wire perr_sel_invalidate = _T_2500 ? 1'h0 : _GEN_26; // @[Conditional.scala 40:58] wire [1:0] perr_err_inv_way = perr_sel_invalidate ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg dma_sb_err_state_ff; // @[ifu_mem_ctl.scala 409:58] - wire _T_2497 = ~dma_sb_err_state_ff; // @[ifu_mem_ctl.scala 408:49] - wire _T_2502 = io_dec_mem_ctrl_ifu_ic_error_start & _T_319; // @[ifu_mem_ctl.scala 417:104] - wire _T_2516 = ~io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 427:30] - wire _T_2517 = _T_2516 & io_dec_tlu_flush_lower_wb; // @[ifu_mem_ctl.scala 427:68] - wire _T_2518 = _T_2517 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 427:98] - wire _T_2527 = perr_state == 3'h2; // @[ifu_mem_ctl.scala 447:79] - wire _T_2528 = io_dec_mem_ctrl_dec_tlu_flush_err_wb & _T_2527; // @[ifu_mem_ctl.scala 447:65] - wire _T_2530 = _T_2528 & _T_2623; // @[ifu_mem_ctl.scala 447:94] - wire _T_2532 = io_dec_tlu_flush_lower_wb | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 450:59] - wire _T_2533 = _T_2532 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 450:99] - wire _T_2547 = _T_2532 | io_ifu_fetch_val[0]; // @[ifu_mem_ctl.scala 453:94] - wire _T_2548 = _T_2547 | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 453:116] - wire _T_2549 = _T_2548 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 453:139] - wire _T_2569 = _T_2547 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 460:116] - wire _T_2577 = io_dec_tlu_flush_lower_wb & _T_2516; // @[ifu_mem_ctl.scala 465:60] - wire _T_2578 = _T_2577 | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 465:101] - wire _T_2579 = _T_2578 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 465:141] + reg dma_sb_err_state_ff; // @[ifu_mem_ctl.scala 396:58] + wire _T_2497 = ~dma_sb_err_state_ff; // @[ifu_mem_ctl.scala 395:49] + wire _T_2502 = io_dec_mem_ctrl_ifu_ic_error_start & _T_319; // @[ifu_mem_ctl.scala 404:104] + wire _T_2516 = ~io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 414:30] + wire _T_2517 = _T_2516 & io_dec_tlu_flush_lower_wb; // @[ifu_mem_ctl.scala 414:68] + wire _T_2518 = _T_2517 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 414:98] + wire _T_2527 = perr_state == 3'h2; // @[ifu_mem_ctl.scala 434:79] + wire _T_2528 = io_dec_mem_ctrl_dec_tlu_flush_err_wb & _T_2527; // @[ifu_mem_ctl.scala 434:65] + wire _T_2530 = _T_2528 & _T_2623; // @[ifu_mem_ctl.scala 434:94] + wire _T_2532 = io_dec_tlu_flush_lower_wb | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 437:59] + wire _T_2533 = _T_2532 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 437:99] + wire _T_2547 = _T_2532 | io_ifu_fetch_val[0]; // @[ifu_mem_ctl.scala 440:94] + wire _T_2548 = _T_2547 | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 440:116] + wire _T_2549 = _T_2548 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 440:139] + wire _T_2569 = _T_2547 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 447:116] + wire _T_2577 = io_dec_tlu_flush_lower_wb & _T_2516; // @[ifu_mem_ctl.scala 452:60] + wire _T_2578 = _T_2577 | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 452:101] + wire _T_2579 = _T_2578 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 452:141] wire _GEN_33 = _T_2575 & _T_2533; // @[Conditional.scala 39:67] wire _GEN_36 = _T_2558 ? _T_2569 : _GEN_33; // @[Conditional.scala 39:67] wire _GEN_38 = _T_2558 | _T_2575; // @[Conditional.scala 39:67] wire _GEN_40 = _T_2531 ? _T_2549 : _GEN_36; // @[Conditional.scala 39:67] wire _GEN_42 = _T_2531 | _GEN_38; // @[Conditional.scala 39:67] wire err_stop_state_en = _T_2526 ? _T_2530 : _GEN_40; // @[Conditional.scala 40:58] - reg bus_cmd_req_hold; // @[ifu_mem_ctl.scala 488:53] - wire _T_2591 = ic_act_miss_f | bus_cmd_req_hold; // @[ifu_mem_ctl.scala 484:45] - reg ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 485:55] - wire _T_2592 = _T_2591 | ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 484:64] - wire _T_2594 = _T_2592 & _T_2623; // @[ifu_mem_ctl.scala 484:85] + reg bus_cmd_req_hold; // @[ifu_mem_ctl.scala 475:53] + wire _T_2591 = ic_act_miss_f | bus_cmd_req_hold; // @[ifu_mem_ctl.scala 471:45] + reg ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 472:55] + wire _T_2592 = _T_2591 | ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 471:64] + wire _T_2594 = _T_2592 & _T_2623; // @[ifu_mem_ctl.scala 471:85] reg [2:0] bus_cmd_beat_count; // @[Reg.scala 27:20] - wire _T_2596 = bus_cmd_beat_count == 3'h7; // @[ifu_mem_ctl.scala 484:146] - wire _T_2597 = _T_2596 & ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 484:177] - wire _T_2598 = _T_2597 & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 484:197] - wire _T_2599 = _T_2598 & miss_pending; // @[ifu_mem_ctl.scala 484:217] - wire _T_2600 = ~_T_2599; // @[ifu_mem_ctl.scala 484:125] - wire ifu_bus_arready = io_ifu_axi_ar_ready & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 516:45] - wire _T_2617 = io_ifu_axi_ar_valid & ifu_bus_arready; // @[ifu_mem_ctl.scala 519:35] - wire _T_2618 = _T_2617 & miss_pending; // @[ifu_mem_ctl.scala 519:53] - wire bus_cmd_sent = _T_2618 & _T_2623; // @[ifu_mem_ctl.scala 519:68] - wire _T_2603 = ~bus_cmd_sent; // @[ifu_mem_ctl.scala 487:61] - wire _T_2604 = _T_2591 & _T_2603; // @[ifu_mem_ctl.scala 487:59] + wire _T_2596 = bus_cmd_beat_count == 3'h7; // @[ifu_mem_ctl.scala 471:146] + wire _T_2597 = _T_2596 & ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 471:177] + wire _T_2598 = _T_2597 & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 471:197] + wire _T_2599 = _T_2598 & miss_pending; // @[ifu_mem_ctl.scala 471:217] + wire _T_2600 = ~_T_2599; // @[ifu_mem_ctl.scala 471:125] + wire ifu_bus_arready = io_ifu_axi_ar_ready & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 523:45] + wire _T_2617 = io_ifu_axi_ar_valid & ifu_bus_arready; // @[ifu_mem_ctl.scala 527:35] + wire _T_2618 = _T_2617 & miss_pending; // @[ifu_mem_ctl.scala 527:53] + wire bus_cmd_sent = _T_2618 & _T_2623; // @[ifu_mem_ctl.scala 527:68] + wire _T_2603 = ~bus_cmd_sent; // @[ifu_mem_ctl.scala 474:61] + wire _T_2604 = _T_2591 & _T_2603; // @[ifu_mem_ctl.scala 474:59] wire [2:0] _T_2608 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_2610 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58] wire [31:0] _T_2612 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - reg ifu_bus_arready_unq_ff; // @[ifu_mem_ctl.scala 503:57] - reg ifu_bus_arvalid_ff; // @[ifu_mem_ctl.scala 505:53] - wire ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 517:51] - wire _T_2638 = ~scnd_miss_req; // @[ifu_mem_ctl.scala 527:73] - wire _T_2639 = _T_2624 & _T_2638; // @[ifu_mem_ctl.scala 527:71] - wire _T_2641 = last_data_recieved_ff & _T_1330; // @[ifu_mem_ctl.scala 527:114] - wire [2:0] _T_2647 = bus_rd_addr_count + 3'h1; // @[ifu_mem_ctl.scala 532:45] - wire _T_2651 = ifu_bus_cmd_valid & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 535:48] - wire _T_2652 = _T_2651 & miss_pending; // @[ifu_mem_ctl.scala 535:68] - wire bus_inc_cmd_beat_cnt = _T_2652 & _T_2623; // @[ifu_mem_ctl.scala 535:83] - wire bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; // @[ifu_mem_ctl.scala 537:57] - wire _T_2656 = ~bus_inc_cmd_beat_cnt; // @[ifu_mem_ctl.scala 538:31] - wire _T_2657 = ic_act_miss_f | scnd_miss_req; // @[ifu_mem_ctl.scala 538:71] - wire _T_2658 = _T_2657 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 538:87] - wire _T_2659 = ~_T_2658; // @[ifu_mem_ctl.scala 538:55] - wire bus_hold_cmd_beat_cnt = _T_2656 & _T_2659; // @[ifu_mem_ctl.scala 538:53] - wire _T_2660 = bus_inc_cmd_beat_cnt | ic_act_miss_f; // @[ifu_mem_ctl.scala 539:46] - wire bus_cmd_beat_en = _T_2660 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 539:62] - wire [2:0] _T_2663 = bus_cmd_beat_count + 3'h1; // @[ifu_mem_ctl.scala 541:46] + reg ifu_bus_arready_unq_ff; // @[ifu_mem_ctl.scala 510:57] + reg ifu_bus_arvalid_ff; // @[ifu_mem_ctl.scala 512:53] + wire ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 524:51] + wire _T_2638 = ~scnd_miss_req; // @[ifu_mem_ctl.scala 535:73] + wire _T_2639 = _T_2624 & _T_2638; // @[ifu_mem_ctl.scala 535:71] + wire _T_2641 = last_data_recieved_ff & _T_1330; // @[ifu_mem_ctl.scala 535:114] + wire [2:0] _T_2647 = bus_rd_addr_count + 3'h1; // @[ifu_mem_ctl.scala 540:45] + wire _T_2651 = ifu_bus_cmd_valid & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 543:48] + wire _T_2652 = _T_2651 & miss_pending; // @[ifu_mem_ctl.scala 543:68] + wire bus_inc_cmd_beat_cnt = _T_2652 & _T_2623; // @[ifu_mem_ctl.scala 543:83] + wire bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; // @[ifu_mem_ctl.scala 545:57] + wire _T_2656 = ~bus_inc_cmd_beat_cnt; // @[ifu_mem_ctl.scala 546:31] + wire _T_2657 = ic_act_miss_f | scnd_miss_req; // @[ifu_mem_ctl.scala 546:71] + wire _T_2658 = _T_2657 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 546:87] + wire _T_2659 = ~_T_2658; // @[ifu_mem_ctl.scala 546:55] + wire bus_hold_cmd_beat_cnt = _T_2656 & _T_2659; // @[ifu_mem_ctl.scala 546:53] + wire _T_2660 = bus_inc_cmd_beat_cnt | ic_act_miss_f; // @[ifu_mem_ctl.scala 547:46] + wire bus_cmd_beat_en = _T_2660 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 547:62] + wire [2:0] _T_2663 = bus_cmd_beat_count + 3'h1; // @[ifu_mem_ctl.scala 549:46] wire [2:0] _T_2665 = bus_reset_cmd_beat_cnt_secondlast ? 3'h6 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_2666 = bus_inc_cmd_beat_cnt ? _T_2663 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_2667 = bus_hold_cmd_beat_cnt ? bus_cmd_beat_count : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_2669 = _T_2665 | _T_2666; // @[Mux.scala 27:72] wire [2:0] bus_new_cmd_beat_count = _T_2669 | _T_2667; // @[Mux.scala 27:72] - reg ifc_dma_access_ok_prev; // @[ifu_mem_ctl.scala 553:62] - wire _T_2698 = ~iccm_correct_ecc; // @[ifu_mem_ctl.scala 558:50] - wire _T_2699 = io_ifc_dma_access_ok & _T_2698; // @[ifu_mem_ctl.scala 558:47] - wire _T_2700 = ~io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 558:70] - wire _T_2704 = _T_2699 & ifc_dma_access_ok_prev; // @[ifu_mem_ctl.scala 559:72] - wire _T_2705 = perr_state == 3'h0; // @[ifu_mem_ctl.scala 559:111] - wire _T_2706 = _T_2704 & _T_2705; // @[ifu_mem_ctl.scala 559:97] - wire ifc_dma_access_q_ok = _T_2706 & _T_2700; // @[ifu_mem_ctl.scala 559:127] - wire _T_2709 = ifc_dma_access_q_ok & io_dma_mem_ctl_dma_iccm_req; // @[ifu_mem_ctl.scala 562:40] - wire _T_2710 = _T_2709 & io_dma_mem_ctl_dma_mem_write; // @[ifu_mem_ctl.scala 562:70] - wire _T_2713 = ~io_dma_mem_ctl_dma_mem_write; // @[ifu_mem_ctl.scala 563:72] - wire _T_2714 = _T_2709 & _T_2713; // @[ifu_mem_ctl.scala 563:70] - wire _T_2715 = io_ifc_iccm_access_bf & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 563:128] + reg ifc_dma_access_ok_prev; // @[ifu_mem_ctl.scala 561:62] + wire _T_2698 = ~iccm_correct_ecc; // @[ifu_mem_ctl.scala 566:50] + wire _T_2699 = io_ifc_dma_access_ok & _T_2698; // @[ifu_mem_ctl.scala 566:47] + wire _T_2700 = ~io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 566:70] + wire _T_2704 = _T_2699 & ifc_dma_access_ok_prev; // @[ifu_mem_ctl.scala 567:72] + wire _T_2705 = perr_state == 3'h0; // @[ifu_mem_ctl.scala 567:111] + wire _T_2706 = _T_2704 & _T_2705; // @[ifu_mem_ctl.scala 567:97] + wire ifc_dma_access_q_ok = _T_2706 & _T_2700; // @[ifu_mem_ctl.scala 567:127] + wire _T_2709 = ifc_dma_access_q_ok & io_dma_mem_ctl_dma_iccm_req; // @[ifu_mem_ctl.scala 570:40] + wire _T_2710 = _T_2709 & io_dma_mem_ctl_dma_mem_write; // @[ifu_mem_ctl.scala 570:70] + wire _T_2713 = ~io_dma_mem_ctl_dma_mem_write; // @[ifu_mem_ctl.scala 571:72] + wire _T_2714 = _T_2709 & _T_2713; // @[ifu_mem_ctl.scala 571:70] + wire _T_2715 = io_ifc_iccm_access_bf & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 571:128] wire [2:0] _T_2720 = io_dma_mem_ctl_dma_iccm_req ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire _T_2741 = io_dma_mem_ctl_dma_mem_wdata[32] ^ io_dma_mem_ctl_dma_mem_wdata[33]; // @[lib.scala 103:74] wire _T_2742 = _T_2741 ^ io_dma_mem_ctl_dma_mem_wdata[35]; // @[lib.scala 103:74] @@ -3633,12 +3633,12 @@ module ifu_mem_ctl( wire _T_3088 = _T_3086 ^ _T_3087; // @[lib.scala 111:18] wire [6:0] _T_3089 = {_T_3088,_T_3080,_T_3069,_T_3040,_T_3011,_T_2976,_T_2941}; // @[Cat.scala 29:58] wire [13:0] dma_mem_ecc = {_T_2904,_T_2896,_T_2885,_T_2856,_T_2827,_T_2792,_T_2757,_T_3089}; // @[Cat.scala 29:58] - wire _T_3091 = ~_T_2709; // @[ifu_mem_ctl.scala 569:45] - wire _T_3092 = iccm_correct_ecc & _T_3091; // @[ifu_mem_ctl.scala 569:43] + wire _T_3091 = ~_T_2709; // @[ifu_mem_ctl.scala 577:45] + wire _T_3092 = iccm_correct_ecc & _T_3091; // @[ifu_mem_ctl.scala 577:43] reg [38:0] iccm_ecc_corr_data_ff; // @[Reg.scala 27:20] wire [77:0] _T_3093 = {iccm_ecc_corr_data_ff,iccm_ecc_corr_data_ff}; // @[Cat.scala 29:58] wire [77:0] _T_3100 = {dma_mem_ecc[13:7],io_dma_mem_ctl_dma_mem_wdata[63:32],dma_mem_ecc[6:0],io_dma_mem_ctl_dma_mem_wdata[31:0]}; // @[Cat.scala 29:58] - reg [1:0] dma_mem_addr_ff; // @[ifu_mem_ctl.scala 583:53] + reg [1:0] dma_mem_addr_ff; // @[ifu_mem_ctl.scala 591:53] wire _T_3435 = _T_3347[5:0] == 6'h27; // @[lib.scala 183:41] wire _T_3433 = _T_3347[5:0] == 6'h26; // @[lib.scala 183:41] wire _T_3431 = _T_3347[5:0] == 6'h25; // @[lib.scala 183:41] @@ -3737,1354 +3737,1354 @@ module ifu_mem_ctl( wire [38:0] _T_3881 = _T_3880 ^ _T_3841; // @[lib.scala 186:76] wire [38:0] _T_3882 = _T_3736 ? _T_3881 : _T_3841; // @[lib.scala 186:31] wire [31:0] iccm_corrected_data_1 = {_T_3882[37:32],_T_3882[30:16],_T_3882[14:8],_T_3882[6:4],_T_3882[2]}; // @[Cat.scala 29:58] - wire [31:0] iccm_dma_rdata_1_muxed = dma_mem_addr_ff[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 575:35] + wire [31:0] iccm_dma_rdata_1_muxed = dma_mem_addr_ff[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 583:35] wire _T_3740 = ~_T_3732[6]; // @[lib.scala 179:55] wire _T_3741 = _T_3734 & _T_3740; // @[lib.scala 179:53] wire _T_3355 = ~_T_3347[6]; // @[lib.scala 179:55] wire _T_3356 = _T_3349 & _T_3355; // @[lib.scala 179:53] wire [1:0] iccm_double_ecc_error = {_T_3741,_T_3356}; // @[Cat.scala 29:58] - wire iccm_dma_ecc_error_in = |iccm_double_ecc_error; // @[ifu_mem_ctl.scala 577:53] + wire iccm_dma_ecc_error_in = |iccm_double_ecc_error; // @[ifu_mem_ctl.scala 585:53] wire [63:0] _T_3104 = {io_dma_mem_ctl_dma_mem_addr,io_dma_mem_ctl_dma_mem_addr}; // @[Cat.scala 29:58] wire [63:0] _T_3105 = {iccm_dma_rdata_1_muxed,_T_3497[37:32],_T_3497[30:16],_T_3497[14:8],_T_3497[6:4],_T_3497[2]}; // @[Cat.scala 29:58] - reg [2:0] dma_mem_tag_ff; // @[ifu_mem_ctl.scala 579:54] - reg [2:0] iccm_dma_rtag_temp; // @[ifu_mem_ctl.scala 580:74] - reg iccm_dma_rvalid_temp; // @[ifu_mem_ctl.scala 585:76] - reg iccm_dma_ecc_error; // @[ifu_mem_ctl.scala 587:74] - reg [63:0] iccm_dma_rdata_temp; // @[ifu_mem_ctl.scala 589:75] - wire _T_3110 = _T_2709 & _T_2698; // @[ifu_mem_ctl.scala 592:77] - wire _T_3114 = _T_3091 & iccm_correct_ecc; // @[ifu_mem_ctl.scala 593:62] + reg [2:0] dma_mem_tag_ff; // @[ifu_mem_ctl.scala 587:54] + reg [2:0] iccm_dma_rtag_temp; // @[ifu_mem_ctl.scala 588:74] + reg iccm_dma_rvalid_temp; // @[ifu_mem_ctl.scala 593:76] + reg iccm_dma_ecc_error; // @[ifu_mem_ctl.scala 595:74] + reg [63:0] iccm_dma_rdata_temp; // @[ifu_mem_ctl.scala 597:75] + wire _T_3110 = _T_2709 & _T_2698; // @[ifu_mem_ctl.scala 600:77] + wire _T_3114 = _T_3091 & iccm_correct_ecc; // @[ifu_mem_ctl.scala 601:62] reg [13:0] iccm_ecc_corr_index_ff; // @[Reg.scala 27:20] wire [14:0] _T_3115 = {iccm_ecc_corr_index_ff,1'h0}; // @[Cat.scala 29:58] - wire [14:0] _T_3117 = _T_3114 ? _T_3115 : io_ifc_fetch_addr_bf[14:0]; // @[ifu_mem_ctl.scala 593:8] + wire [14:0] _T_3117 = _T_3114 ? _T_3115 : io_ifc_fetch_addr_bf[14:0]; // @[ifu_mem_ctl.scala 601:8] wire _T_3509 = _T_3347 == 7'h40; // @[lib.scala 189:62] wire _T_3510 = _T_3497[38] ^ _T_3509; // @[lib.scala 189:44] wire [6:0] iccm_corrected_ecc_0 = {_T_3510,_T_3497[31],_T_3497[15],_T_3497[7],_T_3497[3],_T_3497[1:0]}; // @[Cat.scala 29:58] wire _T_3894 = _T_3732 == 7'h40; // @[lib.scala 189:62] wire _T_3895 = _T_3882[38] ^ _T_3894; // @[lib.scala 189:44] wire [6:0] iccm_corrected_ecc_1 = {_T_3895,_T_3882[31],_T_3882[15],_T_3882[7],_T_3882[3],_T_3882[1:0]}; // @[Cat.scala 29:58] - wire _T_3911 = _T_3 & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 605:75] - wire [31:0] iccm_corrected_data_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 607:38] - wire [6:0] iccm_corrected_ecc_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_ecc_0 : iccm_corrected_ecc_1; // @[ifu_mem_ctl.scala 608:37] - reg iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 616:62] - wire _T_3919 = ~iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 610:93] - wire _T_3920 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err & _T_3919; // @[ifu_mem_ctl.scala 610:91] - wire _T_3922 = _T_3920 & _T_319; // @[ifu_mem_ctl.scala 610:121] - wire iccm_ecc_write_status = _T_3922 | io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 610:144] - wire _T_3923 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 611:84] - reg [13:0] iccm_rw_addr_f; // @[ifu_mem_ctl.scala 615:51] - wire [13:0] _T_3928 = iccm_rw_addr_f + 14'h1; // @[ifu_mem_ctl.scala 614:102] + wire _T_3911 = _T_3 & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 613:75] + wire [31:0] iccm_corrected_data_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 615:38] + wire [6:0] iccm_corrected_ecc_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_ecc_0 : iccm_corrected_ecc_1; // @[ifu_mem_ctl.scala 616:37] + reg iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 624:62] + wire _T_3919 = ~iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 618:93] + wire _T_3920 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err & _T_3919; // @[ifu_mem_ctl.scala 618:91] + wire _T_3922 = _T_3920 & _T_319; // @[ifu_mem_ctl.scala 618:121] + wire iccm_ecc_write_status = _T_3922 | io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 618:144] + wire _T_3923 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 619:84] + reg [13:0] iccm_rw_addr_f; // @[ifu_mem_ctl.scala 623:51] + wire [13:0] _T_3928 = iccm_rw_addr_f + 14'h1; // @[ifu_mem_ctl.scala 622:102] wire [38:0] _T_3932 = {iccm_corrected_ecc_f_mux,iccm_corrected_data_f_mux}; // @[Cat.scala 29:58] - wire _T_3937 = ~io_ifc_fetch_uncacheable_bf; // @[ifu_mem_ctl.scala 619:41] - wire _T_3938 = io_ifc_fetch_req_bf & _T_3937; // @[ifu_mem_ctl.scala 619:39] - wire _T_3939 = ~io_ifc_iccm_access_bf; // @[ifu_mem_ctl.scala 619:72] - wire _T_3940 = _T_3938 & _T_3939; // @[ifu_mem_ctl.scala 619:70] - wire _T_3942 = ~miss_state_en; // @[ifu_mem_ctl.scala 620:34] - wire _T_3943 = _T_2268 & _T_3942; // @[ifu_mem_ctl.scala 620:32] - wire _T_3946 = _T_2284 & _T_3942; // @[ifu_mem_ctl.scala 621:37] - wire _T_3947 = _T_3943 | _T_3946; // @[ifu_mem_ctl.scala 620:88] - wire _T_3948 = miss_state == 3'h7; // @[ifu_mem_ctl.scala 622:19] - wire _T_3950 = _T_3948 & _T_3942; // @[ifu_mem_ctl.scala 622:41] - wire _T_3951 = _T_3947 | _T_3950; // @[ifu_mem_ctl.scala 621:88] - wire _T_3952 = miss_state == 3'h3; // @[ifu_mem_ctl.scala 623:19] - wire _T_3954 = _T_3952 & _T_3942; // @[ifu_mem_ctl.scala 623:35] - wire _T_3955 = _T_3951 | _T_3954; // @[ifu_mem_ctl.scala 622:88] - wire _T_3958 = _T_2283 & _T_3942; // @[ifu_mem_ctl.scala 624:38] - wire _T_3959 = _T_3955 | _T_3958; // @[ifu_mem_ctl.scala 623:88] - wire _T_3961 = _T_2284 & miss_state_en; // @[ifu_mem_ctl.scala 625:37] - wire _T_3962 = miss_nxtstate == 3'h3; // @[ifu_mem_ctl.scala 625:71] - wire _T_3963 = _T_3961 & _T_3962; // @[ifu_mem_ctl.scala 625:54] - wire _T_3964 = _T_3959 | _T_3963; // @[ifu_mem_ctl.scala 624:57] - wire _T_3965 = ~_T_3964; // @[ifu_mem_ctl.scala 620:5] - wire _T_3966 = _T_3940 & _T_3965; // @[ifu_mem_ctl.scala 619:96] - wire _T_3967 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[ifu_mem_ctl.scala 626:28] - wire _T_3969 = _T_3967 & _T_3937; // @[ifu_mem_ctl.scala 626:50] - wire _T_3971 = _T_3969 & _T_3939; // @[ifu_mem_ctl.scala 626:81] + wire _T_3937 = ~io_ifc_fetch_uncacheable_bf; // @[ifu_mem_ctl.scala 627:41] + wire _T_3938 = io_ifc_fetch_req_bf & _T_3937; // @[ifu_mem_ctl.scala 627:39] + wire _T_3939 = ~io_ifc_iccm_access_bf; // @[ifu_mem_ctl.scala 627:72] + wire _T_3940 = _T_3938 & _T_3939; // @[ifu_mem_ctl.scala 627:70] + wire _T_3942 = ~miss_state_en; // @[ifu_mem_ctl.scala 628:34] + wire _T_3943 = _T_2268 & _T_3942; // @[ifu_mem_ctl.scala 628:32] + wire _T_3946 = _T_2284 & _T_3942; // @[ifu_mem_ctl.scala 629:37] + wire _T_3947 = _T_3943 | _T_3946; // @[ifu_mem_ctl.scala 628:88] + wire _T_3948 = miss_state == 3'h7; // @[ifu_mem_ctl.scala 630:19] + wire _T_3950 = _T_3948 & _T_3942; // @[ifu_mem_ctl.scala 630:41] + wire _T_3951 = _T_3947 | _T_3950; // @[ifu_mem_ctl.scala 629:88] + wire _T_3952 = miss_state == 3'h3; // @[ifu_mem_ctl.scala 631:19] + wire _T_3954 = _T_3952 & _T_3942; // @[ifu_mem_ctl.scala 631:35] + wire _T_3955 = _T_3951 | _T_3954; // @[ifu_mem_ctl.scala 630:88] + wire _T_3958 = _T_2283 & _T_3942; // @[ifu_mem_ctl.scala 632:38] + wire _T_3959 = _T_3955 | _T_3958; // @[ifu_mem_ctl.scala 631:88] + wire _T_3961 = _T_2284 & miss_state_en; // @[ifu_mem_ctl.scala 633:37] + wire _T_3962 = miss_nxtstate == 3'h3; // @[ifu_mem_ctl.scala 633:71] + wire _T_3963 = _T_3961 & _T_3962; // @[ifu_mem_ctl.scala 633:54] + wire _T_3964 = _T_3959 | _T_3963; // @[ifu_mem_ctl.scala 632:57] + wire _T_3965 = ~_T_3964; // @[ifu_mem_ctl.scala 628:5] + wire _T_3966 = _T_3940 & _T_3965; // @[ifu_mem_ctl.scala 627:96] + wire _T_3967 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[ifu_mem_ctl.scala 634:28] + wire _T_3969 = _T_3967 & _T_3937; // @[ifu_mem_ctl.scala 634:50] + wire _T_3971 = _T_3969 & _T_3939; // @[ifu_mem_ctl.scala 634:81] wire [1:0] _T_3974 = write_ic_16_bytes ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_9780 = bus_ifu_wr_en_ff_q & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 721:74] - wire bus_wren_1 = _T_9780 & miss_pending; // @[ifu_mem_ctl.scala 721:98] - wire _T_9779 = bus_ifu_wr_en_ff_q & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 721:74] - wire bus_wren_0 = _T_9779 & miss_pending; // @[ifu_mem_ctl.scala 721:98] + wire _T_9780 = bus_ifu_wr_en_ff_q & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 728:74] + wire bus_wren_1 = _T_9780 & miss_pending; // @[ifu_mem_ctl.scala 728:98] + wire _T_9779 = bus_ifu_wr_en_ff_q & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 728:74] + wire bus_wren_0 = _T_9779 & miss_pending; // @[ifu_mem_ctl.scala 728:98] wire [1:0] bus_ic_wr_en = {bus_wren_1,bus_wren_0}; // @[Cat.scala 29:58] - wire _T_3980 = ~_T_108; // @[ifu_mem_ctl.scala 629:106] - wire _T_3981 = _T_2268 & _T_3980; // @[ifu_mem_ctl.scala 629:104] - wire _T_3982 = _T_2284 | _T_3981; // @[ifu_mem_ctl.scala 629:77] - wire _T_3986 = ~_T_51; // @[ifu_mem_ctl.scala 629:172] - wire _T_3987 = _T_3982 & _T_3986; // @[ifu_mem_ctl.scala 629:170] - wire _T_3988 = ~_T_3987; // @[ifu_mem_ctl.scala 629:44] - wire _T_3992 = reset_ic_in | reset_ic_ff; // @[ifu_mem_ctl.scala 632:64] - wire _T_3993 = ~_T_3992; // @[ifu_mem_ctl.scala 632:50] - wire _T_3994 = _T_276 & _T_3993; // @[ifu_mem_ctl.scala 632:48] - wire _T_3995 = ~reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 632:81] - wire ic_valid = _T_3994 & _T_3995; // @[ifu_mem_ctl.scala 632:79] - wire _T_3997 = debug_c1_clken & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 633:82] - reg [6:0] ifu_status_wr_addr_ff; // @[ifu_mem_ctl.scala 636:14] - wire _T_4000 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 639:74] - wire _T_9777 = bus_ifu_wr_en_ff_q & last_beat; // @[ifu_mem_ctl.scala 720:45] - wire way_status_wr_en = _T_9777 | ic_act_hit_f; // @[ifu_mem_ctl.scala 720:58] - reg way_status_wr_en_ff; // @[ifu_mem_ctl.scala 641:14] - wire way_status_hit_new = io_ic_rd_hit[0]; // @[ifu_mem_ctl.scala 716:41] - reg way_status_new_ff; // @[ifu_mem_ctl.scala 647:14] - wire _T_4020 = ifu_status_wr_addr_ff[2:0] == 3'h0; // @[ifu_mem_ctl.scala 653:128] - wire _T_4021 = _T_4020 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 653:136] - wire _T_4024 = ifu_status_wr_addr_ff[2:0] == 3'h1; // @[ifu_mem_ctl.scala 653:128] - wire _T_4025 = _T_4024 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 653:136] - wire _T_4028 = ifu_status_wr_addr_ff[2:0] == 3'h2; // @[ifu_mem_ctl.scala 653:128] - wire _T_4029 = _T_4028 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 653:136] - wire _T_4032 = ifu_status_wr_addr_ff[2:0] == 3'h3; // @[ifu_mem_ctl.scala 653:128] - wire _T_4033 = _T_4032 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 653:136] - wire _T_4036 = ifu_status_wr_addr_ff[2:0] == 3'h4; // @[ifu_mem_ctl.scala 653:128] - wire _T_4037 = _T_4036 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 653:136] - wire _T_4040 = ifu_status_wr_addr_ff[2:0] == 3'h5; // @[ifu_mem_ctl.scala 653:128] - wire _T_4041 = _T_4040 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 653:136] - wire _T_4044 = ifu_status_wr_addr_ff[2:0] == 3'h6; // @[ifu_mem_ctl.scala 653:128] - wire _T_4045 = _T_4044 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 653:136] - wire _T_4048 = ifu_status_wr_addr_ff[2:0] == 3'h7; // @[ifu_mem_ctl.scala 653:128] - wire _T_4049 = _T_4048 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 653:136] - wire _T_9783 = _T_100 & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 723:84] - wire _T_9784 = _T_9783 & miss_pending; // @[ifu_mem_ctl.scala 723:108] - wire bus_wren_last_1 = _T_9784 & bus_last_data_beat; // @[ifu_mem_ctl.scala 723:123] - wire wren_reset_miss_1 = replace_way_mb_any_1 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 724:84] - wire _T_9786 = bus_wren_last_1 | wren_reset_miss_1; // @[ifu_mem_ctl.scala 725:73] - wire _T_9781 = _T_100 & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 723:84] - wire _T_9782 = _T_9781 & miss_pending; // @[ifu_mem_ctl.scala 723:108] - wire bus_wren_last_0 = _T_9782 & bus_last_data_beat; // @[ifu_mem_ctl.scala 723:123] - wire wren_reset_miss_0 = replace_way_mb_any_0 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 724:84] - wire _T_9785 = bus_wren_last_0 | wren_reset_miss_0; // @[ifu_mem_ctl.scala 725:73] + wire _T_3980 = ~_T_108; // @[ifu_mem_ctl.scala 637:106] + wire _T_3981 = _T_2268 & _T_3980; // @[ifu_mem_ctl.scala 637:104] + wire _T_3982 = _T_2284 | _T_3981; // @[ifu_mem_ctl.scala 637:77] + wire _T_3986 = ~_T_51; // @[ifu_mem_ctl.scala 637:172] + wire _T_3987 = _T_3982 & _T_3986; // @[ifu_mem_ctl.scala 637:170] + wire _T_3988 = ~_T_3987; // @[ifu_mem_ctl.scala 637:44] + wire _T_3992 = reset_ic_in | reset_ic_ff; // @[ifu_mem_ctl.scala 640:64] + wire _T_3993 = ~_T_3992; // @[ifu_mem_ctl.scala 640:50] + wire _T_3994 = _T_276 & _T_3993; // @[ifu_mem_ctl.scala 640:48] + wire _T_3995 = ~reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 640:81] + wire ic_valid = _T_3994 & _T_3995; // @[ifu_mem_ctl.scala 640:79] + wire _T_3997 = debug_c1_clken & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 641:82] + reg [6:0] ifu_status_wr_addr_ff; // @[ifu_mem_ctl.scala 644:14] + wire _T_4000 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 647:74] + wire _T_9777 = bus_ifu_wr_en_ff_q & last_beat; // @[ifu_mem_ctl.scala 727:45] + wire way_status_wr_en = _T_9777 | ic_act_hit_f; // @[ifu_mem_ctl.scala 727:58] + reg way_status_wr_en_ff; // @[ifu_mem_ctl.scala 649:14] + wire way_status_hit_new = io_ic_rd_hit[0]; // @[ifu_mem_ctl.scala 723:41] + reg way_status_new_ff; // @[ifu_mem_ctl.scala 655:14] + wire _T_4020 = ifu_status_wr_addr_ff[2:0] == 3'h0; // @[ifu_mem_ctl.scala 661:128] + wire _T_4021 = _T_4020 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] + wire _T_4024 = ifu_status_wr_addr_ff[2:0] == 3'h1; // @[ifu_mem_ctl.scala 661:128] + wire _T_4025 = _T_4024 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] + wire _T_4028 = ifu_status_wr_addr_ff[2:0] == 3'h2; // @[ifu_mem_ctl.scala 661:128] + wire _T_4029 = _T_4028 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] + wire _T_4032 = ifu_status_wr_addr_ff[2:0] == 3'h3; // @[ifu_mem_ctl.scala 661:128] + wire _T_4033 = _T_4032 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] + wire _T_4036 = ifu_status_wr_addr_ff[2:0] == 3'h4; // @[ifu_mem_ctl.scala 661:128] + wire _T_4037 = _T_4036 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] + wire _T_4040 = ifu_status_wr_addr_ff[2:0] == 3'h5; // @[ifu_mem_ctl.scala 661:128] + wire _T_4041 = _T_4040 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] + wire _T_4044 = ifu_status_wr_addr_ff[2:0] == 3'h6; // @[ifu_mem_ctl.scala 661:128] + wire _T_4045 = _T_4044 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] + wire _T_4048 = ifu_status_wr_addr_ff[2:0] == 3'h7; // @[ifu_mem_ctl.scala 661:128] + wire _T_4049 = _T_4048 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] + wire _T_9783 = _T_100 & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 730:84] + wire _T_9784 = _T_9783 & miss_pending; // @[ifu_mem_ctl.scala 730:108] + wire bus_wren_last_1 = _T_9784 & bus_last_data_beat; // @[ifu_mem_ctl.scala 730:123] + wire wren_reset_miss_1 = replace_way_mb_any_1 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 731:84] + wire _T_9786 = bus_wren_last_1 | wren_reset_miss_1; // @[ifu_mem_ctl.scala 732:73] + wire _T_9781 = _T_100 & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 730:84] + wire _T_9782 = _T_9781 & miss_pending; // @[ifu_mem_ctl.scala 730:108] + wire bus_wren_last_0 = _T_9782 & bus_last_data_beat; // @[ifu_mem_ctl.scala 730:123] + wire wren_reset_miss_0 = replace_way_mb_any_0 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 731:84] + wire _T_9785 = bus_wren_last_0 | wren_reset_miss_0; // @[ifu_mem_ctl.scala 732:73] wire [1:0] ifu_tag_wren = {_T_9786,_T_9785}; // @[Cat.scala 29:58] wire [1:0] _T_9821 = _T_4000 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] ic_debug_tag_wr_en = _T_9821 & io_ic_debug_way; // @[ifu_mem_ctl.scala 759:90] - reg [1:0] ifu_tag_wren_ff; // @[ifu_mem_ctl.scala 668:14] - reg ic_valid_ff; // @[ifu_mem_ctl.scala 672:14] - wire _T_5063 = ifu_ic_rw_int_addr_ff[6:5] == 2'h0; // @[ifu_mem_ctl.scala 676:78] - wire _T_5065 = _T_5063 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 676:87] - wire _T_5067 = perr_ic_index_ff[6:5] == 2'h0; // @[ifu_mem_ctl.scala 677:70] - wire _T_5069 = _T_5067 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 677:79] - wire _T_5070 = _T_5065 | _T_5069; // @[ifu_mem_ctl.scala 676:109] - wire _T_5071 = _T_5070 | reset_all_tags; // @[ifu_mem_ctl.scala 677:102] - wire _T_5075 = _T_5063 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 676:87] - wire _T_5079 = _T_5067 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 677:79] - wire _T_5080 = _T_5075 | _T_5079; // @[ifu_mem_ctl.scala 676:109] - wire _T_5081 = _T_5080 | reset_all_tags; // @[ifu_mem_ctl.scala 677:102] + wire [1:0] ic_debug_tag_wr_en = _T_9821 & io_ic_debug_way; // @[ifu_mem_ctl.scala 766:90] + reg [1:0] ifu_tag_wren_ff; // @[ifu_mem_ctl.scala 676:14] + reg ic_valid_ff; // @[ifu_mem_ctl.scala 680:14] + wire _T_5063 = ifu_ic_rw_int_addr_ff[6:5] == 2'h0; // @[ifu_mem_ctl.scala 684:78] + wire _T_5065 = _T_5063 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 684:87] + wire _T_5067 = perr_ic_index_ff[6:5] == 2'h0; // @[ifu_mem_ctl.scala 685:70] + wire _T_5069 = _T_5067 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 685:79] + wire _T_5070 = _T_5065 | _T_5069; // @[ifu_mem_ctl.scala 684:109] + wire _T_5071 = _T_5070 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] + wire _T_5075 = _T_5063 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 684:87] + wire _T_5079 = _T_5067 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 685:79] + wire _T_5080 = _T_5075 | _T_5079; // @[ifu_mem_ctl.scala 684:109] + wire _T_5081 = _T_5080 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] wire [1:0] tag_valid_clken_0 = {_T_5081,_T_5071}; // @[Cat.scala 29:58] - wire _T_5083 = ifu_ic_rw_int_addr_ff[6:5] == 2'h1; // @[ifu_mem_ctl.scala 676:78] - wire _T_5085 = _T_5083 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 676:87] - wire _T_5087 = perr_ic_index_ff[6:5] == 2'h1; // @[ifu_mem_ctl.scala 677:70] - wire _T_5089 = _T_5087 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 677:79] - wire _T_5090 = _T_5085 | _T_5089; // @[ifu_mem_ctl.scala 676:109] - wire _T_5091 = _T_5090 | reset_all_tags; // @[ifu_mem_ctl.scala 677:102] - wire _T_5095 = _T_5083 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 676:87] - wire _T_5099 = _T_5087 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 677:79] - wire _T_5100 = _T_5095 | _T_5099; // @[ifu_mem_ctl.scala 676:109] - wire _T_5101 = _T_5100 | reset_all_tags; // @[ifu_mem_ctl.scala 677:102] + wire _T_5083 = ifu_ic_rw_int_addr_ff[6:5] == 2'h1; // @[ifu_mem_ctl.scala 684:78] + wire _T_5085 = _T_5083 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 684:87] + wire _T_5087 = perr_ic_index_ff[6:5] == 2'h1; // @[ifu_mem_ctl.scala 685:70] + wire _T_5089 = _T_5087 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 685:79] + wire _T_5090 = _T_5085 | _T_5089; // @[ifu_mem_ctl.scala 684:109] + wire _T_5091 = _T_5090 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] + wire _T_5095 = _T_5083 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 684:87] + wire _T_5099 = _T_5087 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 685:79] + wire _T_5100 = _T_5095 | _T_5099; // @[ifu_mem_ctl.scala 684:109] + wire _T_5101 = _T_5100 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] wire [1:0] tag_valid_clken_1 = {_T_5101,_T_5091}; // @[Cat.scala 29:58] - wire _T_5103 = ifu_ic_rw_int_addr_ff[6:5] == 2'h2; // @[ifu_mem_ctl.scala 676:78] - wire _T_5105 = _T_5103 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 676:87] - wire _T_5107 = perr_ic_index_ff[6:5] == 2'h2; // @[ifu_mem_ctl.scala 677:70] - wire _T_5109 = _T_5107 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 677:79] - wire _T_5110 = _T_5105 | _T_5109; // @[ifu_mem_ctl.scala 676:109] - wire _T_5111 = _T_5110 | reset_all_tags; // @[ifu_mem_ctl.scala 677:102] - wire _T_5115 = _T_5103 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 676:87] - wire _T_5119 = _T_5107 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 677:79] - wire _T_5120 = _T_5115 | _T_5119; // @[ifu_mem_ctl.scala 676:109] - wire _T_5121 = _T_5120 | reset_all_tags; // @[ifu_mem_ctl.scala 677:102] + wire _T_5103 = ifu_ic_rw_int_addr_ff[6:5] == 2'h2; // @[ifu_mem_ctl.scala 684:78] + wire _T_5105 = _T_5103 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 684:87] + wire _T_5107 = perr_ic_index_ff[6:5] == 2'h2; // @[ifu_mem_ctl.scala 685:70] + wire _T_5109 = _T_5107 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 685:79] + wire _T_5110 = _T_5105 | _T_5109; // @[ifu_mem_ctl.scala 684:109] + wire _T_5111 = _T_5110 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] + wire _T_5115 = _T_5103 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 684:87] + wire _T_5119 = _T_5107 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 685:79] + wire _T_5120 = _T_5115 | _T_5119; // @[ifu_mem_ctl.scala 684:109] + wire _T_5121 = _T_5120 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] wire [1:0] tag_valid_clken_2 = {_T_5121,_T_5111}; // @[Cat.scala 29:58] - wire _T_5123 = ifu_ic_rw_int_addr_ff[6:5] == 2'h3; // @[ifu_mem_ctl.scala 676:78] - wire _T_5125 = _T_5123 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 676:87] - wire _T_5127 = perr_ic_index_ff[6:5] == 2'h3; // @[ifu_mem_ctl.scala 677:70] - wire _T_5129 = _T_5127 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 677:79] - wire _T_5130 = _T_5125 | _T_5129; // @[ifu_mem_ctl.scala 676:109] - wire _T_5131 = _T_5130 | reset_all_tags; // @[ifu_mem_ctl.scala 677:102] - wire _T_5135 = _T_5123 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 676:87] - wire _T_5139 = _T_5127 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 677:79] - wire _T_5140 = _T_5135 | _T_5139; // @[ifu_mem_ctl.scala 676:109] - wire _T_5141 = _T_5140 | reset_all_tags; // @[ifu_mem_ctl.scala 677:102] + wire _T_5123 = ifu_ic_rw_int_addr_ff[6:5] == 2'h3; // @[ifu_mem_ctl.scala 684:78] + wire _T_5125 = _T_5123 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 684:87] + wire _T_5127 = perr_ic_index_ff[6:5] == 2'h3; // @[ifu_mem_ctl.scala 685:70] + wire _T_5129 = _T_5127 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 685:79] + wire _T_5130 = _T_5125 | _T_5129; // @[ifu_mem_ctl.scala 684:109] + wire _T_5131 = _T_5130 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] + wire _T_5135 = _T_5123 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 684:87] + wire _T_5139 = _T_5127 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 685:79] + wire _T_5140 = _T_5135 | _T_5139; // @[ifu_mem_ctl.scala 684:109] + wire _T_5141 = _T_5140 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] wire [1:0] tag_valid_clken_3 = {_T_5141,_T_5131}; // @[Cat.scala 29:58] - wire _T_5152 = ic_valid_ff & _T_195; // @[ifu_mem_ctl.scala 685:97] - wire _T_5153 = ~perr_sel_invalidate; // @[ifu_mem_ctl.scala 685:124] - wire _T_5154 = _T_5152 & _T_5153; // @[ifu_mem_ctl.scala 685:122] - wire _T_5157 = _T_4671 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5158 = perr_ic_index_ff == 7'h0; // @[ifu_mem_ctl.scala 686:102] - wire _T_5160 = _T_5158 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5161 = _T_5157 | _T_5160; // @[ifu_mem_ctl.scala 686:81] - wire _T_5162 = _T_5161 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5172 = _T_4672 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5173 = perr_ic_index_ff == 7'h1; // @[ifu_mem_ctl.scala 686:102] - wire _T_5175 = _T_5173 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5176 = _T_5172 | _T_5175; // @[ifu_mem_ctl.scala 686:81] - wire _T_5177 = _T_5176 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5187 = _T_4673 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5188 = perr_ic_index_ff == 7'h2; // @[ifu_mem_ctl.scala 686:102] - wire _T_5190 = _T_5188 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5191 = _T_5187 | _T_5190; // @[ifu_mem_ctl.scala 686:81] - wire _T_5192 = _T_5191 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5202 = _T_4674 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5203 = perr_ic_index_ff == 7'h3; // @[ifu_mem_ctl.scala 686:102] - wire _T_5205 = _T_5203 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5206 = _T_5202 | _T_5205; // @[ifu_mem_ctl.scala 686:81] - wire _T_5207 = _T_5206 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5217 = _T_4675 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5218 = perr_ic_index_ff == 7'h4; // @[ifu_mem_ctl.scala 686:102] - wire _T_5220 = _T_5218 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5221 = _T_5217 | _T_5220; // @[ifu_mem_ctl.scala 686:81] - wire _T_5222 = _T_5221 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5232 = _T_4676 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5233 = perr_ic_index_ff == 7'h5; // @[ifu_mem_ctl.scala 686:102] - wire _T_5235 = _T_5233 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5236 = _T_5232 | _T_5235; // @[ifu_mem_ctl.scala 686:81] - wire _T_5237 = _T_5236 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5247 = _T_4677 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5248 = perr_ic_index_ff == 7'h6; // @[ifu_mem_ctl.scala 686:102] - wire _T_5250 = _T_5248 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5251 = _T_5247 | _T_5250; // @[ifu_mem_ctl.scala 686:81] - wire _T_5252 = _T_5251 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5262 = _T_4678 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5263 = perr_ic_index_ff == 7'h7; // @[ifu_mem_ctl.scala 686:102] - wire _T_5265 = _T_5263 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5266 = _T_5262 | _T_5265; // @[ifu_mem_ctl.scala 686:81] - wire _T_5267 = _T_5266 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5277 = _T_4679 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5278 = perr_ic_index_ff == 7'h8; // @[ifu_mem_ctl.scala 686:102] - wire _T_5280 = _T_5278 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5281 = _T_5277 | _T_5280; // @[ifu_mem_ctl.scala 686:81] - wire _T_5282 = _T_5281 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5292 = _T_4680 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5293 = perr_ic_index_ff == 7'h9; // @[ifu_mem_ctl.scala 686:102] - wire _T_5295 = _T_5293 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5296 = _T_5292 | _T_5295; // @[ifu_mem_ctl.scala 686:81] - wire _T_5297 = _T_5296 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5307 = _T_4681 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5308 = perr_ic_index_ff == 7'ha; // @[ifu_mem_ctl.scala 686:102] - wire _T_5310 = _T_5308 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5311 = _T_5307 | _T_5310; // @[ifu_mem_ctl.scala 686:81] - wire _T_5312 = _T_5311 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5322 = _T_4682 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5323 = perr_ic_index_ff == 7'hb; // @[ifu_mem_ctl.scala 686:102] - wire _T_5325 = _T_5323 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5326 = _T_5322 | _T_5325; // @[ifu_mem_ctl.scala 686:81] - wire _T_5327 = _T_5326 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5337 = _T_4683 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5338 = perr_ic_index_ff == 7'hc; // @[ifu_mem_ctl.scala 686:102] - wire _T_5340 = _T_5338 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5341 = _T_5337 | _T_5340; // @[ifu_mem_ctl.scala 686:81] - wire _T_5342 = _T_5341 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5352 = _T_4684 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5353 = perr_ic_index_ff == 7'hd; // @[ifu_mem_ctl.scala 686:102] - wire _T_5355 = _T_5353 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5356 = _T_5352 | _T_5355; // @[ifu_mem_ctl.scala 686:81] - wire _T_5357 = _T_5356 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5367 = _T_4685 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5368 = perr_ic_index_ff == 7'he; // @[ifu_mem_ctl.scala 686:102] - wire _T_5370 = _T_5368 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5371 = _T_5367 | _T_5370; // @[ifu_mem_ctl.scala 686:81] - wire _T_5372 = _T_5371 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5382 = _T_4686 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5383 = perr_ic_index_ff == 7'hf; // @[ifu_mem_ctl.scala 686:102] - wire _T_5385 = _T_5383 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5386 = _T_5382 | _T_5385; // @[ifu_mem_ctl.scala 686:81] - wire _T_5387 = _T_5386 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5397 = _T_4687 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5398 = perr_ic_index_ff == 7'h10; // @[ifu_mem_ctl.scala 686:102] - wire _T_5400 = _T_5398 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5401 = _T_5397 | _T_5400; // @[ifu_mem_ctl.scala 686:81] - wire _T_5402 = _T_5401 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5412 = _T_4688 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5413 = perr_ic_index_ff == 7'h11; // @[ifu_mem_ctl.scala 686:102] - wire _T_5415 = _T_5413 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5416 = _T_5412 | _T_5415; // @[ifu_mem_ctl.scala 686:81] - wire _T_5417 = _T_5416 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5427 = _T_4689 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5428 = perr_ic_index_ff == 7'h12; // @[ifu_mem_ctl.scala 686:102] - wire _T_5430 = _T_5428 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5431 = _T_5427 | _T_5430; // @[ifu_mem_ctl.scala 686:81] - wire _T_5432 = _T_5431 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5442 = _T_4690 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5443 = perr_ic_index_ff == 7'h13; // @[ifu_mem_ctl.scala 686:102] - wire _T_5445 = _T_5443 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5446 = _T_5442 | _T_5445; // @[ifu_mem_ctl.scala 686:81] - wire _T_5447 = _T_5446 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5457 = _T_4691 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5458 = perr_ic_index_ff == 7'h14; // @[ifu_mem_ctl.scala 686:102] - wire _T_5460 = _T_5458 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5461 = _T_5457 | _T_5460; // @[ifu_mem_ctl.scala 686:81] - wire _T_5462 = _T_5461 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5472 = _T_4692 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5473 = perr_ic_index_ff == 7'h15; // @[ifu_mem_ctl.scala 686:102] - wire _T_5475 = _T_5473 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5476 = _T_5472 | _T_5475; // @[ifu_mem_ctl.scala 686:81] - wire _T_5477 = _T_5476 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5487 = _T_4693 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5488 = perr_ic_index_ff == 7'h16; // @[ifu_mem_ctl.scala 686:102] - wire _T_5490 = _T_5488 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5491 = _T_5487 | _T_5490; // @[ifu_mem_ctl.scala 686:81] - wire _T_5492 = _T_5491 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5502 = _T_4694 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5503 = perr_ic_index_ff == 7'h17; // @[ifu_mem_ctl.scala 686:102] - wire _T_5505 = _T_5503 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5506 = _T_5502 | _T_5505; // @[ifu_mem_ctl.scala 686:81] - wire _T_5507 = _T_5506 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5517 = _T_4695 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5518 = perr_ic_index_ff == 7'h18; // @[ifu_mem_ctl.scala 686:102] - wire _T_5520 = _T_5518 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5521 = _T_5517 | _T_5520; // @[ifu_mem_ctl.scala 686:81] - wire _T_5522 = _T_5521 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5532 = _T_4696 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5533 = perr_ic_index_ff == 7'h19; // @[ifu_mem_ctl.scala 686:102] - wire _T_5535 = _T_5533 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5536 = _T_5532 | _T_5535; // @[ifu_mem_ctl.scala 686:81] - wire _T_5537 = _T_5536 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5547 = _T_4697 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5548 = perr_ic_index_ff == 7'h1a; // @[ifu_mem_ctl.scala 686:102] - wire _T_5550 = _T_5548 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5551 = _T_5547 | _T_5550; // @[ifu_mem_ctl.scala 686:81] - wire _T_5552 = _T_5551 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5562 = _T_4698 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5563 = perr_ic_index_ff == 7'h1b; // @[ifu_mem_ctl.scala 686:102] - wire _T_5565 = _T_5563 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5566 = _T_5562 | _T_5565; // @[ifu_mem_ctl.scala 686:81] - wire _T_5567 = _T_5566 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5577 = _T_4699 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5578 = perr_ic_index_ff == 7'h1c; // @[ifu_mem_ctl.scala 686:102] - wire _T_5580 = _T_5578 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5581 = _T_5577 | _T_5580; // @[ifu_mem_ctl.scala 686:81] - wire _T_5582 = _T_5581 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5592 = _T_4700 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5593 = perr_ic_index_ff == 7'h1d; // @[ifu_mem_ctl.scala 686:102] - wire _T_5595 = _T_5593 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5596 = _T_5592 | _T_5595; // @[ifu_mem_ctl.scala 686:81] - wire _T_5597 = _T_5596 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5607 = _T_4701 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5608 = perr_ic_index_ff == 7'h1e; // @[ifu_mem_ctl.scala 686:102] - wire _T_5610 = _T_5608 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5611 = _T_5607 | _T_5610; // @[ifu_mem_ctl.scala 686:81] - wire _T_5612 = _T_5611 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5622 = _T_4702 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5623 = perr_ic_index_ff == 7'h1f; // @[ifu_mem_ctl.scala 686:102] - wire _T_5625 = _T_5623 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5626 = _T_5622 | _T_5625; // @[ifu_mem_ctl.scala 686:81] - wire _T_5627 = _T_5626 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5637 = _T_4671 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5640 = _T_5158 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5641 = _T_5637 | _T_5640; // @[ifu_mem_ctl.scala 686:81] - wire _T_5642 = _T_5641 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5652 = _T_4672 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5655 = _T_5173 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5656 = _T_5652 | _T_5655; // @[ifu_mem_ctl.scala 686:81] - wire _T_5657 = _T_5656 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5667 = _T_4673 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5670 = _T_5188 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5671 = _T_5667 | _T_5670; // @[ifu_mem_ctl.scala 686:81] - wire _T_5672 = _T_5671 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5682 = _T_4674 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5685 = _T_5203 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5686 = _T_5682 | _T_5685; // @[ifu_mem_ctl.scala 686:81] - wire _T_5687 = _T_5686 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5697 = _T_4675 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5700 = _T_5218 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5701 = _T_5697 | _T_5700; // @[ifu_mem_ctl.scala 686:81] - wire _T_5702 = _T_5701 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5712 = _T_4676 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5715 = _T_5233 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5716 = _T_5712 | _T_5715; // @[ifu_mem_ctl.scala 686:81] - wire _T_5717 = _T_5716 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5727 = _T_4677 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5730 = _T_5248 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5731 = _T_5727 | _T_5730; // @[ifu_mem_ctl.scala 686:81] - wire _T_5732 = _T_5731 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5742 = _T_4678 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5745 = _T_5263 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5746 = _T_5742 | _T_5745; // @[ifu_mem_ctl.scala 686:81] - wire _T_5747 = _T_5746 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5757 = _T_4679 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5760 = _T_5278 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5761 = _T_5757 | _T_5760; // @[ifu_mem_ctl.scala 686:81] - wire _T_5762 = _T_5761 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5772 = _T_4680 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5775 = _T_5293 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5776 = _T_5772 | _T_5775; // @[ifu_mem_ctl.scala 686:81] - wire _T_5777 = _T_5776 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5787 = _T_4681 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5790 = _T_5308 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5791 = _T_5787 | _T_5790; // @[ifu_mem_ctl.scala 686:81] - wire _T_5792 = _T_5791 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5802 = _T_4682 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5805 = _T_5323 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5806 = _T_5802 | _T_5805; // @[ifu_mem_ctl.scala 686:81] - wire _T_5807 = _T_5806 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5817 = _T_4683 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5820 = _T_5338 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5821 = _T_5817 | _T_5820; // @[ifu_mem_ctl.scala 686:81] - wire _T_5822 = _T_5821 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5832 = _T_4684 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5835 = _T_5353 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5836 = _T_5832 | _T_5835; // @[ifu_mem_ctl.scala 686:81] - wire _T_5837 = _T_5836 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5847 = _T_4685 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5850 = _T_5368 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5851 = _T_5847 | _T_5850; // @[ifu_mem_ctl.scala 686:81] - wire _T_5852 = _T_5851 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5862 = _T_4686 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5865 = _T_5383 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5866 = _T_5862 | _T_5865; // @[ifu_mem_ctl.scala 686:81] - wire _T_5867 = _T_5866 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5877 = _T_4687 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5880 = _T_5398 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5881 = _T_5877 | _T_5880; // @[ifu_mem_ctl.scala 686:81] - wire _T_5882 = _T_5881 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5892 = _T_4688 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5895 = _T_5413 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5896 = _T_5892 | _T_5895; // @[ifu_mem_ctl.scala 686:81] - wire _T_5897 = _T_5896 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5907 = _T_4689 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5910 = _T_5428 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5911 = _T_5907 | _T_5910; // @[ifu_mem_ctl.scala 686:81] - wire _T_5912 = _T_5911 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5922 = _T_4690 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5925 = _T_5443 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5926 = _T_5922 | _T_5925; // @[ifu_mem_ctl.scala 686:81] - wire _T_5927 = _T_5926 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5937 = _T_4691 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5940 = _T_5458 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5941 = _T_5937 | _T_5940; // @[ifu_mem_ctl.scala 686:81] - wire _T_5942 = _T_5941 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5952 = _T_4692 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5955 = _T_5473 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5956 = _T_5952 | _T_5955; // @[ifu_mem_ctl.scala 686:81] - wire _T_5957 = _T_5956 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5967 = _T_4693 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5970 = _T_5488 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5971 = _T_5967 | _T_5970; // @[ifu_mem_ctl.scala 686:81] - wire _T_5972 = _T_5971 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5982 = _T_4694 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_5985 = _T_5503 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_5986 = _T_5982 | _T_5985; // @[ifu_mem_ctl.scala 686:81] - wire _T_5987 = _T_5986 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_5997 = _T_4695 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6000 = _T_5518 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6001 = _T_5997 | _T_6000; // @[ifu_mem_ctl.scala 686:81] - wire _T_6002 = _T_6001 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6012 = _T_4696 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6015 = _T_5533 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6016 = _T_6012 | _T_6015; // @[ifu_mem_ctl.scala 686:81] - wire _T_6017 = _T_6016 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6027 = _T_4697 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6030 = _T_5548 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6031 = _T_6027 | _T_6030; // @[ifu_mem_ctl.scala 686:81] - wire _T_6032 = _T_6031 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6042 = _T_4698 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6045 = _T_5563 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6046 = _T_6042 | _T_6045; // @[ifu_mem_ctl.scala 686:81] - wire _T_6047 = _T_6046 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6057 = _T_4699 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6060 = _T_5578 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6061 = _T_6057 | _T_6060; // @[ifu_mem_ctl.scala 686:81] - wire _T_6062 = _T_6061 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6072 = _T_4700 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6075 = _T_5593 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6076 = _T_6072 | _T_6075; // @[ifu_mem_ctl.scala 686:81] - wire _T_6077 = _T_6076 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6087 = _T_4701 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6090 = _T_5608 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6091 = _T_6087 | _T_6090; // @[ifu_mem_ctl.scala 686:81] - wire _T_6092 = _T_6091 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6102 = _T_4702 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6105 = _T_5623 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6106 = _T_6102 | _T_6105; // @[ifu_mem_ctl.scala 686:81] - wire _T_6107 = _T_6106 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6117 = _T_4703 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6118 = perr_ic_index_ff == 7'h20; // @[ifu_mem_ctl.scala 686:102] - wire _T_6120 = _T_6118 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6121 = _T_6117 | _T_6120; // @[ifu_mem_ctl.scala 686:81] - wire _T_6122 = _T_6121 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6132 = _T_4704 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6133 = perr_ic_index_ff == 7'h21; // @[ifu_mem_ctl.scala 686:102] - wire _T_6135 = _T_6133 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6136 = _T_6132 | _T_6135; // @[ifu_mem_ctl.scala 686:81] - wire _T_6137 = _T_6136 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6147 = _T_4705 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6148 = perr_ic_index_ff == 7'h22; // @[ifu_mem_ctl.scala 686:102] - wire _T_6150 = _T_6148 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6151 = _T_6147 | _T_6150; // @[ifu_mem_ctl.scala 686:81] - wire _T_6152 = _T_6151 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6162 = _T_4706 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6163 = perr_ic_index_ff == 7'h23; // @[ifu_mem_ctl.scala 686:102] - wire _T_6165 = _T_6163 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6166 = _T_6162 | _T_6165; // @[ifu_mem_ctl.scala 686:81] - wire _T_6167 = _T_6166 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6177 = _T_4707 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6178 = perr_ic_index_ff == 7'h24; // @[ifu_mem_ctl.scala 686:102] - wire _T_6180 = _T_6178 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6181 = _T_6177 | _T_6180; // @[ifu_mem_ctl.scala 686:81] - wire _T_6182 = _T_6181 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6192 = _T_4708 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6193 = perr_ic_index_ff == 7'h25; // @[ifu_mem_ctl.scala 686:102] - wire _T_6195 = _T_6193 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6196 = _T_6192 | _T_6195; // @[ifu_mem_ctl.scala 686:81] - wire _T_6197 = _T_6196 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6207 = _T_4709 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6208 = perr_ic_index_ff == 7'h26; // @[ifu_mem_ctl.scala 686:102] - wire _T_6210 = _T_6208 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6211 = _T_6207 | _T_6210; // @[ifu_mem_ctl.scala 686:81] - wire _T_6212 = _T_6211 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6222 = _T_4710 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6223 = perr_ic_index_ff == 7'h27; // @[ifu_mem_ctl.scala 686:102] - wire _T_6225 = _T_6223 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6226 = _T_6222 | _T_6225; // @[ifu_mem_ctl.scala 686:81] - wire _T_6227 = _T_6226 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6237 = _T_4711 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6238 = perr_ic_index_ff == 7'h28; // @[ifu_mem_ctl.scala 686:102] - wire _T_6240 = _T_6238 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6241 = _T_6237 | _T_6240; // @[ifu_mem_ctl.scala 686:81] - wire _T_6242 = _T_6241 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6252 = _T_4712 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6253 = perr_ic_index_ff == 7'h29; // @[ifu_mem_ctl.scala 686:102] - wire _T_6255 = _T_6253 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6256 = _T_6252 | _T_6255; // @[ifu_mem_ctl.scala 686:81] - wire _T_6257 = _T_6256 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6267 = _T_4713 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6268 = perr_ic_index_ff == 7'h2a; // @[ifu_mem_ctl.scala 686:102] - wire _T_6270 = _T_6268 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6271 = _T_6267 | _T_6270; // @[ifu_mem_ctl.scala 686:81] - wire _T_6272 = _T_6271 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6282 = _T_4714 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6283 = perr_ic_index_ff == 7'h2b; // @[ifu_mem_ctl.scala 686:102] - wire _T_6285 = _T_6283 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6286 = _T_6282 | _T_6285; // @[ifu_mem_ctl.scala 686:81] - wire _T_6287 = _T_6286 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6297 = _T_4715 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6298 = perr_ic_index_ff == 7'h2c; // @[ifu_mem_ctl.scala 686:102] - wire _T_6300 = _T_6298 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6301 = _T_6297 | _T_6300; // @[ifu_mem_ctl.scala 686:81] - wire _T_6302 = _T_6301 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6312 = _T_4716 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6313 = perr_ic_index_ff == 7'h2d; // @[ifu_mem_ctl.scala 686:102] - wire _T_6315 = _T_6313 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6316 = _T_6312 | _T_6315; // @[ifu_mem_ctl.scala 686:81] - wire _T_6317 = _T_6316 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6327 = _T_4717 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6328 = perr_ic_index_ff == 7'h2e; // @[ifu_mem_ctl.scala 686:102] - wire _T_6330 = _T_6328 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6331 = _T_6327 | _T_6330; // @[ifu_mem_ctl.scala 686:81] - wire _T_6332 = _T_6331 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6342 = _T_4718 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6343 = perr_ic_index_ff == 7'h2f; // @[ifu_mem_ctl.scala 686:102] - wire _T_6345 = _T_6343 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6346 = _T_6342 | _T_6345; // @[ifu_mem_ctl.scala 686:81] - wire _T_6347 = _T_6346 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6357 = _T_4719 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6358 = perr_ic_index_ff == 7'h30; // @[ifu_mem_ctl.scala 686:102] - wire _T_6360 = _T_6358 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6361 = _T_6357 | _T_6360; // @[ifu_mem_ctl.scala 686:81] - wire _T_6362 = _T_6361 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6372 = _T_4720 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6373 = perr_ic_index_ff == 7'h31; // @[ifu_mem_ctl.scala 686:102] - wire _T_6375 = _T_6373 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6376 = _T_6372 | _T_6375; // @[ifu_mem_ctl.scala 686:81] - wire _T_6377 = _T_6376 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6387 = _T_4721 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6388 = perr_ic_index_ff == 7'h32; // @[ifu_mem_ctl.scala 686:102] - wire _T_6390 = _T_6388 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6391 = _T_6387 | _T_6390; // @[ifu_mem_ctl.scala 686:81] - wire _T_6392 = _T_6391 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6402 = _T_4722 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6403 = perr_ic_index_ff == 7'h33; // @[ifu_mem_ctl.scala 686:102] - wire _T_6405 = _T_6403 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6406 = _T_6402 | _T_6405; // @[ifu_mem_ctl.scala 686:81] - wire _T_6407 = _T_6406 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6417 = _T_4723 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6418 = perr_ic_index_ff == 7'h34; // @[ifu_mem_ctl.scala 686:102] - wire _T_6420 = _T_6418 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6421 = _T_6417 | _T_6420; // @[ifu_mem_ctl.scala 686:81] - wire _T_6422 = _T_6421 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6432 = _T_4724 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6433 = perr_ic_index_ff == 7'h35; // @[ifu_mem_ctl.scala 686:102] - wire _T_6435 = _T_6433 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6436 = _T_6432 | _T_6435; // @[ifu_mem_ctl.scala 686:81] - wire _T_6437 = _T_6436 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6447 = _T_4725 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6448 = perr_ic_index_ff == 7'h36; // @[ifu_mem_ctl.scala 686:102] - wire _T_6450 = _T_6448 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6451 = _T_6447 | _T_6450; // @[ifu_mem_ctl.scala 686:81] - wire _T_6452 = _T_6451 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6462 = _T_4726 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6463 = perr_ic_index_ff == 7'h37; // @[ifu_mem_ctl.scala 686:102] - wire _T_6465 = _T_6463 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6466 = _T_6462 | _T_6465; // @[ifu_mem_ctl.scala 686:81] - wire _T_6467 = _T_6466 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6477 = _T_4727 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6478 = perr_ic_index_ff == 7'h38; // @[ifu_mem_ctl.scala 686:102] - wire _T_6480 = _T_6478 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6481 = _T_6477 | _T_6480; // @[ifu_mem_ctl.scala 686:81] - wire _T_6482 = _T_6481 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6492 = _T_4728 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6493 = perr_ic_index_ff == 7'h39; // @[ifu_mem_ctl.scala 686:102] - wire _T_6495 = _T_6493 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6496 = _T_6492 | _T_6495; // @[ifu_mem_ctl.scala 686:81] - wire _T_6497 = _T_6496 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6507 = _T_4729 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6508 = perr_ic_index_ff == 7'h3a; // @[ifu_mem_ctl.scala 686:102] - wire _T_6510 = _T_6508 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6511 = _T_6507 | _T_6510; // @[ifu_mem_ctl.scala 686:81] - wire _T_6512 = _T_6511 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6522 = _T_4730 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6523 = perr_ic_index_ff == 7'h3b; // @[ifu_mem_ctl.scala 686:102] - wire _T_6525 = _T_6523 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6526 = _T_6522 | _T_6525; // @[ifu_mem_ctl.scala 686:81] - wire _T_6527 = _T_6526 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6537 = _T_4731 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6538 = perr_ic_index_ff == 7'h3c; // @[ifu_mem_ctl.scala 686:102] - wire _T_6540 = _T_6538 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6541 = _T_6537 | _T_6540; // @[ifu_mem_ctl.scala 686:81] - wire _T_6542 = _T_6541 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6552 = _T_4732 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6553 = perr_ic_index_ff == 7'h3d; // @[ifu_mem_ctl.scala 686:102] - wire _T_6555 = _T_6553 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6556 = _T_6552 | _T_6555; // @[ifu_mem_ctl.scala 686:81] - wire _T_6557 = _T_6556 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6567 = _T_4733 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6568 = perr_ic_index_ff == 7'h3e; // @[ifu_mem_ctl.scala 686:102] - wire _T_6570 = _T_6568 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6571 = _T_6567 | _T_6570; // @[ifu_mem_ctl.scala 686:81] - wire _T_6572 = _T_6571 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6582 = _T_4734 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6583 = perr_ic_index_ff == 7'h3f; // @[ifu_mem_ctl.scala 686:102] - wire _T_6585 = _T_6583 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6586 = _T_6582 | _T_6585; // @[ifu_mem_ctl.scala 686:81] - wire _T_6587 = _T_6586 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6597 = _T_4703 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6600 = _T_6118 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6601 = _T_6597 | _T_6600; // @[ifu_mem_ctl.scala 686:81] - wire _T_6602 = _T_6601 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6612 = _T_4704 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6615 = _T_6133 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6616 = _T_6612 | _T_6615; // @[ifu_mem_ctl.scala 686:81] - wire _T_6617 = _T_6616 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6627 = _T_4705 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6630 = _T_6148 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6631 = _T_6627 | _T_6630; // @[ifu_mem_ctl.scala 686:81] - wire _T_6632 = _T_6631 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6642 = _T_4706 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6645 = _T_6163 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6646 = _T_6642 | _T_6645; // @[ifu_mem_ctl.scala 686:81] - wire _T_6647 = _T_6646 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6657 = _T_4707 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6660 = _T_6178 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6661 = _T_6657 | _T_6660; // @[ifu_mem_ctl.scala 686:81] - wire _T_6662 = _T_6661 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6672 = _T_4708 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6675 = _T_6193 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6676 = _T_6672 | _T_6675; // @[ifu_mem_ctl.scala 686:81] - wire _T_6677 = _T_6676 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6687 = _T_4709 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6690 = _T_6208 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6691 = _T_6687 | _T_6690; // @[ifu_mem_ctl.scala 686:81] - wire _T_6692 = _T_6691 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6702 = _T_4710 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6705 = _T_6223 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6706 = _T_6702 | _T_6705; // @[ifu_mem_ctl.scala 686:81] - wire _T_6707 = _T_6706 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6717 = _T_4711 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6720 = _T_6238 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6721 = _T_6717 | _T_6720; // @[ifu_mem_ctl.scala 686:81] - wire _T_6722 = _T_6721 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6732 = _T_4712 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6735 = _T_6253 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6736 = _T_6732 | _T_6735; // @[ifu_mem_ctl.scala 686:81] - wire _T_6737 = _T_6736 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6747 = _T_4713 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6750 = _T_6268 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6751 = _T_6747 | _T_6750; // @[ifu_mem_ctl.scala 686:81] - wire _T_6752 = _T_6751 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6762 = _T_4714 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6765 = _T_6283 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6766 = _T_6762 | _T_6765; // @[ifu_mem_ctl.scala 686:81] - wire _T_6767 = _T_6766 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6777 = _T_4715 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6780 = _T_6298 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6781 = _T_6777 | _T_6780; // @[ifu_mem_ctl.scala 686:81] - wire _T_6782 = _T_6781 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6792 = _T_4716 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6795 = _T_6313 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6796 = _T_6792 | _T_6795; // @[ifu_mem_ctl.scala 686:81] - wire _T_6797 = _T_6796 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6807 = _T_4717 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6810 = _T_6328 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6811 = _T_6807 | _T_6810; // @[ifu_mem_ctl.scala 686:81] - wire _T_6812 = _T_6811 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6822 = _T_4718 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6825 = _T_6343 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6826 = _T_6822 | _T_6825; // @[ifu_mem_ctl.scala 686:81] - wire _T_6827 = _T_6826 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6837 = _T_4719 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6840 = _T_6358 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6841 = _T_6837 | _T_6840; // @[ifu_mem_ctl.scala 686:81] - wire _T_6842 = _T_6841 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6852 = _T_4720 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6855 = _T_6373 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6856 = _T_6852 | _T_6855; // @[ifu_mem_ctl.scala 686:81] - wire _T_6857 = _T_6856 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6867 = _T_4721 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6870 = _T_6388 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6871 = _T_6867 | _T_6870; // @[ifu_mem_ctl.scala 686:81] - wire _T_6872 = _T_6871 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6882 = _T_4722 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6885 = _T_6403 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6886 = _T_6882 | _T_6885; // @[ifu_mem_ctl.scala 686:81] - wire _T_6887 = _T_6886 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6897 = _T_4723 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6900 = _T_6418 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6901 = _T_6897 | _T_6900; // @[ifu_mem_ctl.scala 686:81] - wire _T_6902 = _T_6901 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6912 = _T_4724 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6915 = _T_6433 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6916 = _T_6912 | _T_6915; // @[ifu_mem_ctl.scala 686:81] - wire _T_6917 = _T_6916 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6927 = _T_4725 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6930 = _T_6448 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6931 = _T_6927 | _T_6930; // @[ifu_mem_ctl.scala 686:81] - wire _T_6932 = _T_6931 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6942 = _T_4726 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6945 = _T_6463 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6946 = _T_6942 | _T_6945; // @[ifu_mem_ctl.scala 686:81] - wire _T_6947 = _T_6946 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6957 = _T_4727 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6960 = _T_6478 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6961 = _T_6957 | _T_6960; // @[ifu_mem_ctl.scala 686:81] - wire _T_6962 = _T_6961 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6972 = _T_4728 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6975 = _T_6493 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6976 = _T_6972 | _T_6975; // @[ifu_mem_ctl.scala 686:81] - wire _T_6977 = _T_6976 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_6987 = _T_4729 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_6990 = _T_6508 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_6991 = _T_6987 | _T_6990; // @[ifu_mem_ctl.scala 686:81] - wire _T_6992 = _T_6991 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7002 = _T_4730 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7005 = _T_6523 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7006 = _T_7002 | _T_7005; // @[ifu_mem_ctl.scala 686:81] - wire _T_7007 = _T_7006 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7017 = _T_4731 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7020 = _T_6538 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7021 = _T_7017 | _T_7020; // @[ifu_mem_ctl.scala 686:81] - wire _T_7022 = _T_7021 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7032 = _T_4732 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7035 = _T_6553 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7036 = _T_7032 | _T_7035; // @[ifu_mem_ctl.scala 686:81] - wire _T_7037 = _T_7036 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7047 = _T_4733 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7050 = _T_6568 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7051 = _T_7047 | _T_7050; // @[ifu_mem_ctl.scala 686:81] - wire _T_7052 = _T_7051 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7062 = _T_4734 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7065 = _T_6583 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7066 = _T_7062 | _T_7065; // @[ifu_mem_ctl.scala 686:81] - wire _T_7067 = _T_7066 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7077 = _T_4735 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7078 = perr_ic_index_ff == 7'h40; // @[ifu_mem_ctl.scala 686:102] - wire _T_7080 = _T_7078 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7081 = _T_7077 | _T_7080; // @[ifu_mem_ctl.scala 686:81] - wire _T_7082 = _T_7081 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7092 = _T_4736 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7093 = perr_ic_index_ff == 7'h41; // @[ifu_mem_ctl.scala 686:102] - wire _T_7095 = _T_7093 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7096 = _T_7092 | _T_7095; // @[ifu_mem_ctl.scala 686:81] - wire _T_7097 = _T_7096 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7107 = _T_4737 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7108 = perr_ic_index_ff == 7'h42; // @[ifu_mem_ctl.scala 686:102] - wire _T_7110 = _T_7108 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7111 = _T_7107 | _T_7110; // @[ifu_mem_ctl.scala 686:81] - wire _T_7112 = _T_7111 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7122 = _T_4738 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7123 = perr_ic_index_ff == 7'h43; // @[ifu_mem_ctl.scala 686:102] - wire _T_7125 = _T_7123 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7126 = _T_7122 | _T_7125; // @[ifu_mem_ctl.scala 686:81] - wire _T_7127 = _T_7126 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7137 = _T_4739 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7138 = perr_ic_index_ff == 7'h44; // @[ifu_mem_ctl.scala 686:102] - wire _T_7140 = _T_7138 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7141 = _T_7137 | _T_7140; // @[ifu_mem_ctl.scala 686:81] - wire _T_7142 = _T_7141 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7152 = _T_4740 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7153 = perr_ic_index_ff == 7'h45; // @[ifu_mem_ctl.scala 686:102] - wire _T_7155 = _T_7153 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7156 = _T_7152 | _T_7155; // @[ifu_mem_ctl.scala 686:81] - wire _T_7157 = _T_7156 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7167 = _T_4741 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7168 = perr_ic_index_ff == 7'h46; // @[ifu_mem_ctl.scala 686:102] - wire _T_7170 = _T_7168 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7171 = _T_7167 | _T_7170; // @[ifu_mem_ctl.scala 686:81] - wire _T_7172 = _T_7171 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7182 = _T_4742 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7183 = perr_ic_index_ff == 7'h47; // @[ifu_mem_ctl.scala 686:102] - wire _T_7185 = _T_7183 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7186 = _T_7182 | _T_7185; // @[ifu_mem_ctl.scala 686:81] - wire _T_7187 = _T_7186 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7197 = _T_4743 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7198 = perr_ic_index_ff == 7'h48; // @[ifu_mem_ctl.scala 686:102] - wire _T_7200 = _T_7198 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7201 = _T_7197 | _T_7200; // @[ifu_mem_ctl.scala 686:81] - wire _T_7202 = _T_7201 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7212 = _T_4744 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7213 = perr_ic_index_ff == 7'h49; // @[ifu_mem_ctl.scala 686:102] - wire _T_7215 = _T_7213 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7216 = _T_7212 | _T_7215; // @[ifu_mem_ctl.scala 686:81] - wire _T_7217 = _T_7216 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7227 = _T_4745 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7228 = perr_ic_index_ff == 7'h4a; // @[ifu_mem_ctl.scala 686:102] - wire _T_7230 = _T_7228 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7231 = _T_7227 | _T_7230; // @[ifu_mem_ctl.scala 686:81] - wire _T_7232 = _T_7231 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7242 = _T_4746 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7243 = perr_ic_index_ff == 7'h4b; // @[ifu_mem_ctl.scala 686:102] - wire _T_7245 = _T_7243 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7246 = _T_7242 | _T_7245; // @[ifu_mem_ctl.scala 686:81] - wire _T_7247 = _T_7246 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7257 = _T_4747 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7258 = perr_ic_index_ff == 7'h4c; // @[ifu_mem_ctl.scala 686:102] - wire _T_7260 = _T_7258 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7261 = _T_7257 | _T_7260; // @[ifu_mem_ctl.scala 686:81] - wire _T_7262 = _T_7261 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7272 = _T_4748 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7273 = perr_ic_index_ff == 7'h4d; // @[ifu_mem_ctl.scala 686:102] - wire _T_7275 = _T_7273 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7276 = _T_7272 | _T_7275; // @[ifu_mem_ctl.scala 686:81] - wire _T_7277 = _T_7276 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7287 = _T_4749 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7288 = perr_ic_index_ff == 7'h4e; // @[ifu_mem_ctl.scala 686:102] - wire _T_7290 = _T_7288 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7291 = _T_7287 | _T_7290; // @[ifu_mem_ctl.scala 686:81] - wire _T_7292 = _T_7291 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7302 = _T_4750 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7303 = perr_ic_index_ff == 7'h4f; // @[ifu_mem_ctl.scala 686:102] - wire _T_7305 = _T_7303 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7306 = _T_7302 | _T_7305; // @[ifu_mem_ctl.scala 686:81] - wire _T_7307 = _T_7306 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7317 = _T_4751 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7318 = perr_ic_index_ff == 7'h50; // @[ifu_mem_ctl.scala 686:102] - wire _T_7320 = _T_7318 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7321 = _T_7317 | _T_7320; // @[ifu_mem_ctl.scala 686:81] - wire _T_7322 = _T_7321 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7332 = _T_4752 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7333 = perr_ic_index_ff == 7'h51; // @[ifu_mem_ctl.scala 686:102] - wire _T_7335 = _T_7333 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7336 = _T_7332 | _T_7335; // @[ifu_mem_ctl.scala 686:81] - wire _T_7337 = _T_7336 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7347 = _T_4753 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7348 = perr_ic_index_ff == 7'h52; // @[ifu_mem_ctl.scala 686:102] - wire _T_7350 = _T_7348 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7351 = _T_7347 | _T_7350; // @[ifu_mem_ctl.scala 686:81] - wire _T_7352 = _T_7351 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7362 = _T_4754 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7363 = perr_ic_index_ff == 7'h53; // @[ifu_mem_ctl.scala 686:102] - wire _T_7365 = _T_7363 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7366 = _T_7362 | _T_7365; // @[ifu_mem_ctl.scala 686:81] - wire _T_7367 = _T_7366 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7377 = _T_4755 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7378 = perr_ic_index_ff == 7'h54; // @[ifu_mem_ctl.scala 686:102] - wire _T_7380 = _T_7378 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7381 = _T_7377 | _T_7380; // @[ifu_mem_ctl.scala 686:81] - wire _T_7382 = _T_7381 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7392 = _T_4756 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7393 = perr_ic_index_ff == 7'h55; // @[ifu_mem_ctl.scala 686:102] - wire _T_7395 = _T_7393 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7396 = _T_7392 | _T_7395; // @[ifu_mem_ctl.scala 686:81] - wire _T_7397 = _T_7396 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7407 = _T_4757 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7408 = perr_ic_index_ff == 7'h56; // @[ifu_mem_ctl.scala 686:102] - wire _T_7410 = _T_7408 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7411 = _T_7407 | _T_7410; // @[ifu_mem_ctl.scala 686:81] - wire _T_7412 = _T_7411 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7422 = _T_4758 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7423 = perr_ic_index_ff == 7'h57; // @[ifu_mem_ctl.scala 686:102] - wire _T_7425 = _T_7423 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7426 = _T_7422 | _T_7425; // @[ifu_mem_ctl.scala 686:81] - wire _T_7427 = _T_7426 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7437 = _T_4759 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7438 = perr_ic_index_ff == 7'h58; // @[ifu_mem_ctl.scala 686:102] - wire _T_7440 = _T_7438 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7441 = _T_7437 | _T_7440; // @[ifu_mem_ctl.scala 686:81] - wire _T_7442 = _T_7441 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7452 = _T_4760 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7453 = perr_ic_index_ff == 7'h59; // @[ifu_mem_ctl.scala 686:102] - wire _T_7455 = _T_7453 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7456 = _T_7452 | _T_7455; // @[ifu_mem_ctl.scala 686:81] - wire _T_7457 = _T_7456 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7467 = _T_4761 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7468 = perr_ic_index_ff == 7'h5a; // @[ifu_mem_ctl.scala 686:102] - wire _T_7470 = _T_7468 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7471 = _T_7467 | _T_7470; // @[ifu_mem_ctl.scala 686:81] - wire _T_7472 = _T_7471 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7482 = _T_4762 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7483 = perr_ic_index_ff == 7'h5b; // @[ifu_mem_ctl.scala 686:102] - wire _T_7485 = _T_7483 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7486 = _T_7482 | _T_7485; // @[ifu_mem_ctl.scala 686:81] - wire _T_7487 = _T_7486 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7497 = _T_4763 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7498 = perr_ic_index_ff == 7'h5c; // @[ifu_mem_ctl.scala 686:102] - wire _T_7500 = _T_7498 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7501 = _T_7497 | _T_7500; // @[ifu_mem_ctl.scala 686:81] - wire _T_7502 = _T_7501 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7512 = _T_4764 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7513 = perr_ic_index_ff == 7'h5d; // @[ifu_mem_ctl.scala 686:102] - wire _T_7515 = _T_7513 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7516 = _T_7512 | _T_7515; // @[ifu_mem_ctl.scala 686:81] - wire _T_7517 = _T_7516 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7527 = _T_4765 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7528 = perr_ic_index_ff == 7'h5e; // @[ifu_mem_ctl.scala 686:102] - wire _T_7530 = _T_7528 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7531 = _T_7527 | _T_7530; // @[ifu_mem_ctl.scala 686:81] - wire _T_7532 = _T_7531 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7542 = _T_4766 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7543 = perr_ic_index_ff == 7'h5f; // @[ifu_mem_ctl.scala 686:102] - wire _T_7545 = _T_7543 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7546 = _T_7542 | _T_7545; // @[ifu_mem_ctl.scala 686:81] - wire _T_7547 = _T_7546 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7557 = _T_4735 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7560 = _T_7078 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7561 = _T_7557 | _T_7560; // @[ifu_mem_ctl.scala 686:81] - wire _T_7562 = _T_7561 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7572 = _T_4736 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7575 = _T_7093 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7576 = _T_7572 | _T_7575; // @[ifu_mem_ctl.scala 686:81] - wire _T_7577 = _T_7576 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7587 = _T_4737 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7590 = _T_7108 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7591 = _T_7587 | _T_7590; // @[ifu_mem_ctl.scala 686:81] - wire _T_7592 = _T_7591 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7602 = _T_4738 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7605 = _T_7123 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7606 = _T_7602 | _T_7605; // @[ifu_mem_ctl.scala 686:81] - wire _T_7607 = _T_7606 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7617 = _T_4739 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7620 = _T_7138 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7621 = _T_7617 | _T_7620; // @[ifu_mem_ctl.scala 686:81] - wire _T_7622 = _T_7621 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7632 = _T_4740 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7635 = _T_7153 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7636 = _T_7632 | _T_7635; // @[ifu_mem_ctl.scala 686:81] - wire _T_7637 = _T_7636 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7647 = _T_4741 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7650 = _T_7168 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7651 = _T_7647 | _T_7650; // @[ifu_mem_ctl.scala 686:81] - wire _T_7652 = _T_7651 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7662 = _T_4742 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7665 = _T_7183 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7666 = _T_7662 | _T_7665; // @[ifu_mem_ctl.scala 686:81] - wire _T_7667 = _T_7666 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7677 = _T_4743 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7680 = _T_7198 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7681 = _T_7677 | _T_7680; // @[ifu_mem_ctl.scala 686:81] - wire _T_7682 = _T_7681 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7692 = _T_4744 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7695 = _T_7213 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7696 = _T_7692 | _T_7695; // @[ifu_mem_ctl.scala 686:81] - wire _T_7697 = _T_7696 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7707 = _T_4745 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7710 = _T_7228 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7711 = _T_7707 | _T_7710; // @[ifu_mem_ctl.scala 686:81] - wire _T_7712 = _T_7711 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7722 = _T_4746 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7725 = _T_7243 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7726 = _T_7722 | _T_7725; // @[ifu_mem_ctl.scala 686:81] - wire _T_7727 = _T_7726 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7737 = _T_4747 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7740 = _T_7258 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7741 = _T_7737 | _T_7740; // @[ifu_mem_ctl.scala 686:81] - wire _T_7742 = _T_7741 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7752 = _T_4748 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7755 = _T_7273 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7756 = _T_7752 | _T_7755; // @[ifu_mem_ctl.scala 686:81] - wire _T_7757 = _T_7756 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7767 = _T_4749 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7770 = _T_7288 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7771 = _T_7767 | _T_7770; // @[ifu_mem_ctl.scala 686:81] - wire _T_7772 = _T_7771 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7782 = _T_4750 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7785 = _T_7303 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7786 = _T_7782 | _T_7785; // @[ifu_mem_ctl.scala 686:81] - wire _T_7787 = _T_7786 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7797 = _T_4751 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7800 = _T_7318 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7801 = _T_7797 | _T_7800; // @[ifu_mem_ctl.scala 686:81] - wire _T_7802 = _T_7801 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7812 = _T_4752 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7815 = _T_7333 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7816 = _T_7812 | _T_7815; // @[ifu_mem_ctl.scala 686:81] - wire _T_7817 = _T_7816 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7827 = _T_4753 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7830 = _T_7348 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7831 = _T_7827 | _T_7830; // @[ifu_mem_ctl.scala 686:81] - wire _T_7832 = _T_7831 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7842 = _T_4754 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7845 = _T_7363 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7846 = _T_7842 | _T_7845; // @[ifu_mem_ctl.scala 686:81] - wire _T_7847 = _T_7846 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7857 = _T_4755 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7860 = _T_7378 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7861 = _T_7857 | _T_7860; // @[ifu_mem_ctl.scala 686:81] - wire _T_7862 = _T_7861 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7872 = _T_4756 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7875 = _T_7393 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7876 = _T_7872 | _T_7875; // @[ifu_mem_ctl.scala 686:81] - wire _T_7877 = _T_7876 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7887 = _T_4757 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7890 = _T_7408 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7891 = _T_7887 | _T_7890; // @[ifu_mem_ctl.scala 686:81] - wire _T_7892 = _T_7891 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7902 = _T_4758 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7905 = _T_7423 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7906 = _T_7902 | _T_7905; // @[ifu_mem_ctl.scala 686:81] - wire _T_7907 = _T_7906 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7917 = _T_4759 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7920 = _T_7438 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7921 = _T_7917 | _T_7920; // @[ifu_mem_ctl.scala 686:81] - wire _T_7922 = _T_7921 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7932 = _T_4760 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7935 = _T_7453 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7936 = _T_7932 | _T_7935; // @[ifu_mem_ctl.scala 686:81] - wire _T_7937 = _T_7936 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7947 = _T_4761 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7950 = _T_7468 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7951 = _T_7947 | _T_7950; // @[ifu_mem_ctl.scala 686:81] - wire _T_7952 = _T_7951 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7962 = _T_4762 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7965 = _T_7483 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7966 = _T_7962 | _T_7965; // @[ifu_mem_ctl.scala 686:81] - wire _T_7967 = _T_7966 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7977 = _T_4763 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7980 = _T_7498 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7981 = _T_7977 | _T_7980; // @[ifu_mem_ctl.scala 686:81] - wire _T_7982 = _T_7981 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_7992 = _T_4764 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_7995 = _T_7513 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_7996 = _T_7992 | _T_7995; // @[ifu_mem_ctl.scala 686:81] - wire _T_7997 = _T_7996 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8007 = _T_4765 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8010 = _T_7528 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8011 = _T_8007 | _T_8010; // @[ifu_mem_ctl.scala 686:81] - wire _T_8012 = _T_8011 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8022 = _T_4766 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8025 = _T_7543 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8026 = _T_8022 | _T_8025; // @[ifu_mem_ctl.scala 686:81] - wire _T_8027 = _T_8026 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8037 = _T_4767 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8038 = perr_ic_index_ff == 7'h60; // @[ifu_mem_ctl.scala 686:102] - wire _T_8040 = _T_8038 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8041 = _T_8037 | _T_8040; // @[ifu_mem_ctl.scala 686:81] - wire _T_8042 = _T_8041 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8052 = _T_4768 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8053 = perr_ic_index_ff == 7'h61; // @[ifu_mem_ctl.scala 686:102] - wire _T_8055 = _T_8053 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8056 = _T_8052 | _T_8055; // @[ifu_mem_ctl.scala 686:81] - wire _T_8057 = _T_8056 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8067 = _T_4769 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8068 = perr_ic_index_ff == 7'h62; // @[ifu_mem_ctl.scala 686:102] - wire _T_8070 = _T_8068 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8071 = _T_8067 | _T_8070; // @[ifu_mem_ctl.scala 686:81] - wire _T_8072 = _T_8071 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8082 = _T_4770 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8083 = perr_ic_index_ff == 7'h63; // @[ifu_mem_ctl.scala 686:102] - wire _T_8085 = _T_8083 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8086 = _T_8082 | _T_8085; // @[ifu_mem_ctl.scala 686:81] - wire _T_8087 = _T_8086 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8097 = _T_4771 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8098 = perr_ic_index_ff == 7'h64; // @[ifu_mem_ctl.scala 686:102] - wire _T_8100 = _T_8098 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8101 = _T_8097 | _T_8100; // @[ifu_mem_ctl.scala 686:81] - wire _T_8102 = _T_8101 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8112 = _T_4772 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8113 = perr_ic_index_ff == 7'h65; // @[ifu_mem_ctl.scala 686:102] - wire _T_8115 = _T_8113 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8116 = _T_8112 | _T_8115; // @[ifu_mem_ctl.scala 686:81] - wire _T_8117 = _T_8116 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8127 = _T_4773 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8128 = perr_ic_index_ff == 7'h66; // @[ifu_mem_ctl.scala 686:102] - wire _T_8130 = _T_8128 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8131 = _T_8127 | _T_8130; // @[ifu_mem_ctl.scala 686:81] - wire _T_8132 = _T_8131 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8142 = _T_4774 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8143 = perr_ic_index_ff == 7'h67; // @[ifu_mem_ctl.scala 686:102] - wire _T_8145 = _T_8143 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8146 = _T_8142 | _T_8145; // @[ifu_mem_ctl.scala 686:81] - wire _T_8147 = _T_8146 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8157 = _T_4775 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8158 = perr_ic_index_ff == 7'h68; // @[ifu_mem_ctl.scala 686:102] - wire _T_8160 = _T_8158 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8161 = _T_8157 | _T_8160; // @[ifu_mem_ctl.scala 686:81] - wire _T_8162 = _T_8161 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8172 = _T_4776 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8173 = perr_ic_index_ff == 7'h69; // @[ifu_mem_ctl.scala 686:102] - wire _T_8175 = _T_8173 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8176 = _T_8172 | _T_8175; // @[ifu_mem_ctl.scala 686:81] - wire _T_8177 = _T_8176 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8187 = _T_4777 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8188 = perr_ic_index_ff == 7'h6a; // @[ifu_mem_ctl.scala 686:102] - wire _T_8190 = _T_8188 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8191 = _T_8187 | _T_8190; // @[ifu_mem_ctl.scala 686:81] - wire _T_8192 = _T_8191 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8202 = _T_4778 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8203 = perr_ic_index_ff == 7'h6b; // @[ifu_mem_ctl.scala 686:102] - wire _T_8205 = _T_8203 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8206 = _T_8202 | _T_8205; // @[ifu_mem_ctl.scala 686:81] - wire _T_8207 = _T_8206 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8217 = _T_4779 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8218 = perr_ic_index_ff == 7'h6c; // @[ifu_mem_ctl.scala 686:102] - wire _T_8220 = _T_8218 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8221 = _T_8217 | _T_8220; // @[ifu_mem_ctl.scala 686:81] - wire _T_8222 = _T_8221 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8232 = _T_4780 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8233 = perr_ic_index_ff == 7'h6d; // @[ifu_mem_ctl.scala 686:102] - wire _T_8235 = _T_8233 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8236 = _T_8232 | _T_8235; // @[ifu_mem_ctl.scala 686:81] - wire _T_8237 = _T_8236 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8247 = _T_4781 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8248 = perr_ic_index_ff == 7'h6e; // @[ifu_mem_ctl.scala 686:102] - wire _T_8250 = _T_8248 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8251 = _T_8247 | _T_8250; // @[ifu_mem_ctl.scala 686:81] - wire _T_8252 = _T_8251 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8262 = _T_4782 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8263 = perr_ic_index_ff == 7'h6f; // @[ifu_mem_ctl.scala 686:102] - wire _T_8265 = _T_8263 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8266 = _T_8262 | _T_8265; // @[ifu_mem_ctl.scala 686:81] - wire _T_8267 = _T_8266 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8277 = _T_4783 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8278 = perr_ic_index_ff == 7'h70; // @[ifu_mem_ctl.scala 686:102] - wire _T_8280 = _T_8278 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8281 = _T_8277 | _T_8280; // @[ifu_mem_ctl.scala 686:81] - wire _T_8282 = _T_8281 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8292 = _T_4784 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8293 = perr_ic_index_ff == 7'h71; // @[ifu_mem_ctl.scala 686:102] - wire _T_8295 = _T_8293 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8296 = _T_8292 | _T_8295; // @[ifu_mem_ctl.scala 686:81] - wire _T_8297 = _T_8296 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8307 = _T_4785 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8308 = perr_ic_index_ff == 7'h72; // @[ifu_mem_ctl.scala 686:102] - wire _T_8310 = _T_8308 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8311 = _T_8307 | _T_8310; // @[ifu_mem_ctl.scala 686:81] - wire _T_8312 = _T_8311 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8322 = _T_4786 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8323 = perr_ic_index_ff == 7'h73; // @[ifu_mem_ctl.scala 686:102] - wire _T_8325 = _T_8323 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8326 = _T_8322 | _T_8325; // @[ifu_mem_ctl.scala 686:81] - wire _T_8327 = _T_8326 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8337 = _T_4787 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8338 = perr_ic_index_ff == 7'h74; // @[ifu_mem_ctl.scala 686:102] - wire _T_8340 = _T_8338 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8341 = _T_8337 | _T_8340; // @[ifu_mem_ctl.scala 686:81] - wire _T_8342 = _T_8341 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8352 = _T_4788 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8353 = perr_ic_index_ff == 7'h75; // @[ifu_mem_ctl.scala 686:102] - wire _T_8355 = _T_8353 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8356 = _T_8352 | _T_8355; // @[ifu_mem_ctl.scala 686:81] - wire _T_8357 = _T_8356 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8367 = _T_4789 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8368 = perr_ic_index_ff == 7'h76; // @[ifu_mem_ctl.scala 686:102] - wire _T_8370 = _T_8368 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8371 = _T_8367 | _T_8370; // @[ifu_mem_ctl.scala 686:81] - wire _T_8372 = _T_8371 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8382 = _T_4790 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8383 = perr_ic_index_ff == 7'h77; // @[ifu_mem_ctl.scala 686:102] - wire _T_8385 = _T_8383 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8386 = _T_8382 | _T_8385; // @[ifu_mem_ctl.scala 686:81] - wire _T_8387 = _T_8386 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8397 = _T_4791 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8398 = perr_ic_index_ff == 7'h78; // @[ifu_mem_ctl.scala 686:102] - wire _T_8400 = _T_8398 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8401 = _T_8397 | _T_8400; // @[ifu_mem_ctl.scala 686:81] - wire _T_8402 = _T_8401 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8412 = _T_4792 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8413 = perr_ic_index_ff == 7'h79; // @[ifu_mem_ctl.scala 686:102] - wire _T_8415 = _T_8413 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8416 = _T_8412 | _T_8415; // @[ifu_mem_ctl.scala 686:81] - wire _T_8417 = _T_8416 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8427 = _T_4793 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8428 = perr_ic_index_ff == 7'h7a; // @[ifu_mem_ctl.scala 686:102] - wire _T_8430 = _T_8428 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8431 = _T_8427 | _T_8430; // @[ifu_mem_ctl.scala 686:81] - wire _T_8432 = _T_8431 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8442 = _T_4794 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8443 = perr_ic_index_ff == 7'h7b; // @[ifu_mem_ctl.scala 686:102] - wire _T_8445 = _T_8443 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8446 = _T_8442 | _T_8445; // @[ifu_mem_ctl.scala 686:81] - wire _T_8447 = _T_8446 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8457 = _T_4795 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8458 = perr_ic_index_ff == 7'h7c; // @[ifu_mem_ctl.scala 686:102] - wire _T_8460 = _T_8458 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8461 = _T_8457 | _T_8460; // @[ifu_mem_ctl.scala 686:81] - wire _T_8462 = _T_8461 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8472 = _T_4796 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8473 = perr_ic_index_ff == 7'h7d; // @[ifu_mem_ctl.scala 686:102] - wire _T_8475 = _T_8473 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8476 = _T_8472 | _T_8475; // @[ifu_mem_ctl.scala 686:81] - wire _T_8477 = _T_8476 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8487 = _T_4797 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8488 = perr_ic_index_ff == 7'h7e; // @[ifu_mem_ctl.scala 686:102] - wire _T_8490 = _T_8488 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8491 = _T_8487 | _T_8490; // @[ifu_mem_ctl.scala 686:81] - wire _T_8492 = _T_8491 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8502 = _T_4798 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8503 = perr_ic_index_ff == 7'h7f; // @[ifu_mem_ctl.scala 686:102] - wire _T_8505 = _T_8503 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8506 = _T_8502 | _T_8505; // @[ifu_mem_ctl.scala 686:81] - wire _T_8507 = _T_8506 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8517 = _T_4767 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8520 = _T_8038 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8521 = _T_8517 | _T_8520; // @[ifu_mem_ctl.scala 686:81] - wire _T_8522 = _T_8521 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8532 = _T_4768 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8535 = _T_8053 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8536 = _T_8532 | _T_8535; // @[ifu_mem_ctl.scala 686:81] - wire _T_8537 = _T_8536 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8547 = _T_4769 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8550 = _T_8068 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8551 = _T_8547 | _T_8550; // @[ifu_mem_ctl.scala 686:81] - wire _T_8552 = _T_8551 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8562 = _T_4770 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8565 = _T_8083 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8566 = _T_8562 | _T_8565; // @[ifu_mem_ctl.scala 686:81] - wire _T_8567 = _T_8566 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8577 = _T_4771 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8580 = _T_8098 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8581 = _T_8577 | _T_8580; // @[ifu_mem_ctl.scala 686:81] - wire _T_8582 = _T_8581 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8592 = _T_4772 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8595 = _T_8113 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8596 = _T_8592 | _T_8595; // @[ifu_mem_ctl.scala 686:81] - wire _T_8597 = _T_8596 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8607 = _T_4773 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8610 = _T_8128 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8611 = _T_8607 | _T_8610; // @[ifu_mem_ctl.scala 686:81] - wire _T_8612 = _T_8611 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8622 = _T_4774 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8625 = _T_8143 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8626 = _T_8622 | _T_8625; // @[ifu_mem_ctl.scala 686:81] - wire _T_8627 = _T_8626 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8637 = _T_4775 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8640 = _T_8158 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8641 = _T_8637 | _T_8640; // @[ifu_mem_ctl.scala 686:81] - wire _T_8642 = _T_8641 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8652 = _T_4776 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8655 = _T_8173 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8656 = _T_8652 | _T_8655; // @[ifu_mem_ctl.scala 686:81] - wire _T_8657 = _T_8656 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8667 = _T_4777 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8670 = _T_8188 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8671 = _T_8667 | _T_8670; // @[ifu_mem_ctl.scala 686:81] - wire _T_8672 = _T_8671 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8682 = _T_4778 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8685 = _T_8203 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8686 = _T_8682 | _T_8685; // @[ifu_mem_ctl.scala 686:81] - wire _T_8687 = _T_8686 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8697 = _T_4779 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8700 = _T_8218 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8701 = _T_8697 | _T_8700; // @[ifu_mem_ctl.scala 686:81] - wire _T_8702 = _T_8701 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8712 = _T_4780 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8715 = _T_8233 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8716 = _T_8712 | _T_8715; // @[ifu_mem_ctl.scala 686:81] - wire _T_8717 = _T_8716 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8727 = _T_4781 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8730 = _T_8248 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8731 = _T_8727 | _T_8730; // @[ifu_mem_ctl.scala 686:81] - wire _T_8732 = _T_8731 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8742 = _T_4782 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8745 = _T_8263 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8746 = _T_8742 | _T_8745; // @[ifu_mem_ctl.scala 686:81] - wire _T_8747 = _T_8746 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8757 = _T_4783 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8760 = _T_8278 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8761 = _T_8757 | _T_8760; // @[ifu_mem_ctl.scala 686:81] - wire _T_8762 = _T_8761 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8772 = _T_4784 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8775 = _T_8293 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8776 = _T_8772 | _T_8775; // @[ifu_mem_ctl.scala 686:81] - wire _T_8777 = _T_8776 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8787 = _T_4785 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8790 = _T_8308 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8791 = _T_8787 | _T_8790; // @[ifu_mem_ctl.scala 686:81] - wire _T_8792 = _T_8791 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8802 = _T_4786 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8805 = _T_8323 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8806 = _T_8802 | _T_8805; // @[ifu_mem_ctl.scala 686:81] - wire _T_8807 = _T_8806 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8817 = _T_4787 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8820 = _T_8338 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8821 = _T_8817 | _T_8820; // @[ifu_mem_ctl.scala 686:81] - wire _T_8822 = _T_8821 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8832 = _T_4788 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8835 = _T_8353 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8836 = _T_8832 | _T_8835; // @[ifu_mem_ctl.scala 686:81] - wire _T_8837 = _T_8836 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8847 = _T_4789 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8850 = _T_8368 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8851 = _T_8847 | _T_8850; // @[ifu_mem_ctl.scala 686:81] - wire _T_8852 = _T_8851 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8862 = _T_4790 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8865 = _T_8383 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8866 = _T_8862 | _T_8865; // @[ifu_mem_ctl.scala 686:81] - wire _T_8867 = _T_8866 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8877 = _T_4791 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8880 = _T_8398 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8881 = _T_8877 | _T_8880; // @[ifu_mem_ctl.scala 686:81] - wire _T_8882 = _T_8881 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8892 = _T_4792 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8895 = _T_8413 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8896 = _T_8892 | _T_8895; // @[ifu_mem_ctl.scala 686:81] - wire _T_8897 = _T_8896 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8907 = _T_4793 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8910 = _T_8428 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8911 = _T_8907 | _T_8910; // @[ifu_mem_ctl.scala 686:81] - wire _T_8912 = _T_8911 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8922 = _T_4794 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8925 = _T_8443 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8926 = _T_8922 | _T_8925; // @[ifu_mem_ctl.scala 686:81] - wire _T_8927 = _T_8926 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8937 = _T_4795 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8940 = _T_8458 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8941 = _T_8937 | _T_8940; // @[ifu_mem_ctl.scala 686:81] - wire _T_8942 = _T_8941 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8952 = _T_4796 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8955 = _T_8473 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8956 = _T_8952 | _T_8955; // @[ifu_mem_ctl.scala 686:81] - wire _T_8957 = _T_8956 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8967 = _T_4797 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8970 = _T_8488 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8971 = _T_8967 | _T_8970; // @[ifu_mem_ctl.scala 686:81] - wire _T_8972 = _T_8971 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_8982 = _T_4798 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 686:59] - wire _T_8985 = _T_8503 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 686:124] - wire _T_8986 = _T_8982 | _T_8985; // @[ifu_mem_ctl.scala 686:81] - wire _T_8987 = _T_8986 | reset_all_tags; // @[ifu_mem_ctl.scala 686:147] - wire _T_9789 = ~fetch_uncacheable_ff; // @[ifu_mem_ctl.scala 741:63] - wire _T_9790 = _T_9789 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 741:85] + wire _T_5152 = ic_valid_ff & _T_195; // @[ifu_mem_ctl.scala 693:97] + wire _T_5153 = ~perr_sel_invalidate; // @[ifu_mem_ctl.scala 693:124] + wire _T_5154 = _T_5152 & _T_5153; // @[ifu_mem_ctl.scala 693:122] + wire _T_5157 = _T_4671 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5158 = perr_ic_index_ff == 7'h0; // @[ifu_mem_ctl.scala 694:102] + wire _T_5160 = _T_5158 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5161 = _T_5157 | _T_5160; // @[ifu_mem_ctl.scala 694:81] + wire _T_5162 = _T_5161 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5172 = _T_4672 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5173 = perr_ic_index_ff == 7'h1; // @[ifu_mem_ctl.scala 694:102] + wire _T_5175 = _T_5173 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5176 = _T_5172 | _T_5175; // @[ifu_mem_ctl.scala 694:81] + wire _T_5177 = _T_5176 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5187 = _T_4673 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5188 = perr_ic_index_ff == 7'h2; // @[ifu_mem_ctl.scala 694:102] + wire _T_5190 = _T_5188 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5191 = _T_5187 | _T_5190; // @[ifu_mem_ctl.scala 694:81] + wire _T_5192 = _T_5191 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5202 = _T_4674 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5203 = perr_ic_index_ff == 7'h3; // @[ifu_mem_ctl.scala 694:102] + wire _T_5205 = _T_5203 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5206 = _T_5202 | _T_5205; // @[ifu_mem_ctl.scala 694:81] + wire _T_5207 = _T_5206 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5217 = _T_4675 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5218 = perr_ic_index_ff == 7'h4; // @[ifu_mem_ctl.scala 694:102] + wire _T_5220 = _T_5218 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5221 = _T_5217 | _T_5220; // @[ifu_mem_ctl.scala 694:81] + wire _T_5222 = _T_5221 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5232 = _T_4676 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5233 = perr_ic_index_ff == 7'h5; // @[ifu_mem_ctl.scala 694:102] + wire _T_5235 = _T_5233 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5236 = _T_5232 | _T_5235; // @[ifu_mem_ctl.scala 694:81] + wire _T_5237 = _T_5236 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5247 = _T_4677 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5248 = perr_ic_index_ff == 7'h6; // @[ifu_mem_ctl.scala 694:102] + wire _T_5250 = _T_5248 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5251 = _T_5247 | _T_5250; // @[ifu_mem_ctl.scala 694:81] + wire _T_5252 = _T_5251 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5262 = _T_4678 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5263 = perr_ic_index_ff == 7'h7; // @[ifu_mem_ctl.scala 694:102] + wire _T_5265 = _T_5263 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5266 = _T_5262 | _T_5265; // @[ifu_mem_ctl.scala 694:81] + wire _T_5267 = _T_5266 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5277 = _T_4679 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5278 = perr_ic_index_ff == 7'h8; // @[ifu_mem_ctl.scala 694:102] + wire _T_5280 = _T_5278 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5281 = _T_5277 | _T_5280; // @[ifu_mem_ctl.scala 694:81] + wire _T_5282 = _T_5281 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5292 = _T_4680 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5293 = perr_ic_index_ff == 7'h9; // @[ifu_mem_ctl.scala 694:102] + wire _T_5295 = _T_5293 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5296 = _T_5292 | _T_5295; // @[ifu_mem_ctl.scala 694:81] + wire _T_5297 = _T_5296 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5307 = _T_4681 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5308 = perr_ic_index_ff == 7'ha; // @[ifu_mem_ctl.scala 694:102] + wire _T_5310 = _T_5308 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5311 = _T_5307 | _T_5310; // @[ifu_mem_ctl.scala 694:81] + wire _T_5312 = _T_5311 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5322 = _T_4682 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5323 = perr_ic_index_ff == 7'hb; // @[ifu_mem_ctl.scala 694:102] + wire _T_5325 = _T_5323 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5326 = _T_5322 | _T_5325; // @[ifu_mem_ctl.scala 694:81] + wire _T_5327 = _T_5326 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5337 = _T_4683 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5338 = perr_ic_index_ff == 7'hc; // @[ifu_mem_ctl.scala 694:102] + wire _T_5340 = _T_5338 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5341 = _T_5337 | _T_5340; // @[ifu_mem_ctl.scala 694:81] + wire _T_5342 = _T_5341 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5352 = _T_4684 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5353 = perr_ic_index_ff == 7'hd; // @[ifu_mem_ctl.scala 694:102] + wire _T_5355 = _T_5353 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5356 = _T_5352 | _T_5355; // @[ifu_mem_ctl.scala 694:81] + wire _T_5357 = _T_5356 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5367 = _T_4685 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5368 = perr_ic_index_ff == 7'he; // @[ifu_mem_ctl.scala 694:102] + wire _T_5370 = _T_5368 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5371 = _T_5367 | _T_5370; // @[ifu_mem_ctl.scala 694:81] + wire _T_5372 = _T_5371 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5382 = _T_4686 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5383 = perr_ic_index_ff == 7'hf; // @[ifu_mem_ctl.scala 694:102] + wire _T_5385 = _T_5383 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5386 = _T_5382 | _T_5385; // @[ifu_mem_ctl.scala 694:81] + wire _T_5387 = _T_5386 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5397 = _T_4687 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5398 = perr_ic_index_ff == 7'h10; // @[ifu_mem_ctl.scala 694:102] + wire _T_5400 = _T_5398 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5401 = _T_5397 | _T_5400; // @[ifu_mem_ctl.scala 694:81] + wire _T_5402 = _T_5401 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5412 = _T_4688 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5413 = perr_ic_index_ff == 7'h11; // @[ifu_mem_ctl.scala 694:102] + wire _T_5415 = _T_5413 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5416 = _T_5412 | _T_5415; // @[ifu_mem_ctl.scala 694:81] + wire _T_5417 = _T_5416 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5427 = _T_4689 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5428 = perr_ic_index_ff == 7'h12; // @[ifu_mem_ctl.scala 694:102] + wire _T_5430 = _T_5428 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5431 = _T_5427 | _T_5430; // @[ifu_mem_ctl.scala 694:81] + wire _T_5432 = _T_5431 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5442 = _T_4690 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5443 = perr_ic_index_ff == 7'h13; // @[ifu_mem_ctl.scala 694:102] + wire _T_5445 = _T_5443 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5446 = _T_5442 | _T_5445; // @[ifu_mem_ctl.scala 694:81] + wire _T_5447 = _T_5446 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5457 = _T_4691 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5458 = perr_ic_index_ff == 7'h14; // @[ifu_mem_ctl.scala 694:102] + wire _T_5460 = _T_5458 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5461 = _T_5457 | _T_5460; // @[ifu_mem_ctl.scala 694:81] + wire _T_5462 = _T_5461 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5472 = _T_4692 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5473 = perr_ic_index_ff == 7'h15; // @[ifu_mem_ctl.scala 694:102] + wire _T_5475 = _T_5473 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5476 = _T_5472 | _T_5475; // @[ifu_mem_ctl.scala 694:81] + wire _T_5477 = _T_5476 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5487 = _T_4693 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5488 = perr_ic_index_ff == 7'h16; // @[ifu_mem_ctl.scala 694:102] + wire _T_5490 = _T_5488 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5491 = _T_5487 | _T_5490; // @[ifu_mem_ctl.scala 694:81] + wire _T_5492 = _T_5491 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5502 = _T_4694 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5503 = perr_ic_index_ff == 7'h17; // @[ifu_mem_ctl.scala 694:102] + wire _T_5505 = _T_5503 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5506 = _T_5502 | _T_5505; // @[ifu_mem_ctl.scala 694:81] + wire _T_5507 = _T_5506 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5517 = _T_4695 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5518 = perr_ic_index_ff == 7'h18; // @[ifu_mem_ctl.scala 694:102] + wire _T_5520 = _T_5518 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5521 = _T_5517 | _T_5520; // @[ifu_mem_ctl.scala 694:81] + wire _T_5522 = _T_5521 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5532 = _T_4696 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5533 = perr_ic_index_ff == 7'h19; // @[ifu_mem_ctl.scala 694:102] + wire _T_5535 = _T_5533 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5536 = _T_5532 | _T_5535; // @[ifu_mem_ctl.scala 694:81] + wire _T_5537 = _T_5536 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5547 = _T_4697 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5548 = perr_ic_index_ff == 7'h1a; // @[ifu_mem_ctl.scala 694:102] + wire _T_5550 = _T_5548 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5551 = _T_5547 | _T_5550; // @[ifu_mem_ctl.scala 694:81] + wire _T_5552 = _T_5551 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5562 = _T_4698 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5563 = perr_ic_index_ff == 7'h1b; // @[ifu_mem_ctl.scala 694:102] + wire _T_5565 = _T_5563 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5566 = _T_5562 | _T_5565; // @[ifu_mem_ctl.scala 694:81] + wire _T_5567 = _T_5566 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5577 = _T_4699 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5578 = perr_ic_index_ff == 7'h1c; // @[ifu_mem_ctl.scala 694:102] + wire _T_5580 = _T_5578 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5581 = _T_5577 | _T_5580; // @[ifu_mem_ctl.scala 694:81] + wire _T_5582 = _T_5581 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5592 = _T_4700 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5593 = perr_ic_index_ff == 7'h1d; // @[ifu_mem_ctl.scala 694:102] + wire _T_5595 = _T_5593 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5596 = _T_5592 | _T_5595; // @[ifu_mem_ctl.scala 694:81] + wire _T_5597 = _T_5596 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5607 = _T_4701 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5608 = perr_ic_index_ff == 7'h1e; // @[ifu_mem_ctl.scala 694:102] + wire _T_5610 = _T_5608 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5611 = _T_5607 | _T_5610; // @[ifu_mem_ctl.scala 694:81] + wire _T_5612 = _T_5611 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5622 = _T_4702 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5623 = perr_ic_index_ff == 7'h1f; // @[ifu_mem_ctl.scala 694:102] + wire _T_5625 = _T_5623 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5626 = _T_5622 | _T_5625; // @[ifu_mem_ctl.scala 694:81] + wire _T_5627 = _T_5626 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5637 = _T_4671 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5640 = _T_5158 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5641 = _T_5637 | _T_5640; // @[ifu_mem_ctl.scala 694:81] + wire _T_5642 = _T_5641 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5652 = _T_4672 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5655 = _T_5173 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5656 = _T_5652 | _T_5655; // @[ifu_mem_ctl.scala 694:81] + wire _T_5657 = _T_5656 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5667 = _T_4673 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5670 = _T_5188 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5671 = _T_5667 | _T_5670; // @[ifu_mem_ctl.scala 694:81] + wire _T_5672 = _T_5671 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5682 = _T_4674 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5685 = _T_5203 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5686 = _T_5682 | _T_5685; // @[ifu_mem_ctl.scala 694:81] + wire _T_5687 = _T_5686 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5697 = _T_4675 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5700 = _T_5218 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5701 = _T_5697 | _T_5700; // @[ifu_mem_ctl.scala 694:81] + wire _T_5702 = _T_5701 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5712 = _T_4676 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5715 = _T_5233 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5716 = _T_5712 | _T_5715; // @[ifu_mem_ctl.scala 694:81] + wire _T_5717 = _T_5716 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5727 = _T_4677 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5730 = _T_5248 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5731 = _T_5727 | _T_5730; // @[ifu_mem_ctl.scala 694:81] + wire _T_5732 = _T_5731 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5742 = _T_4678 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5745 = _T_5263 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5746 = _T_5742 | _T_5745; // @[ifu_mem_ctl.scala 694:81] + wire _T_5747 = _T_5746 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5757 = _T_4679 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5760 = _T_5278 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5761 = _T_5757 | _T_5760; // @[ifu_mem_ctl.scala 694:81] + wire _T_5762 = _T_5761 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5772 = _T_4680 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5775 = _T_5293 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5776 = _T_5772 | _T_5775; // @[ifu_mem_ctl.scala 694:81] + wire _T_5777 = _T_5776 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5787 = _T_4681 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5790 = _T_5308 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5791 = _T_5787 | _T_5790; // @[ifu_mem_ctl.scala 694:81] + wire _T_5792 = _T_5791 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5802 = _T_4682 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5805 = _T_5323 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5806 = _T_5802 | _T_5805; // @[ifu_mem_ctl.scala 694:81] + wire _T_5807 = _T_5806 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5817 = _T_4683 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5820 = _T_5338 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5821 = _T_5817 | _T_5820; // @[ifu_mem_ctl.scala 694:81] + wire _T_5822 = _T_5821 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5832 = _T_4684 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5835 = _T_5353 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5836 = _T_5832 | _T_5835; // @[ifu_mem_ctl.scala 694:81] + wire _T_5837 = _T_5836 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5847 = _T_4685 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5850 = _T_5368 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5851 = _T_5847 | _T_5850; // @[ifu_mem_ctl.scala 694:81] + wire _T_5852 = _T_5851 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5862 = _T_4686 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5865 = _T_5383 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5866 = _T_5862 | _T_5865; // @[ifu_mem_ctl.scala 694:81] + wire _T_5867 = _T_5866 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5877 = _T_4687 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5880 = _T_5398 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5881 = _T_5877 | _T_5880; // @[ifu_mem_ctl.scala 694:81] + wire _T_5882 = _T_5881 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5892 = _T_4688 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5895 = _T_5413 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5896 = _T_5892 | _T_5895; // @[ifu_mem_ctl.scala 694:81] + wire _T_5897 = _T_5896 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5907 = _T_4689 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5910 = _T_5428 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5911 = _T_5907 | _T_5910; // @[ifu_mem_ctl.scala 694:81] + wire _T_5912 = _T_5911 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5922 = _T_4690 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5925 = _T_5443 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5926 = _T_5922 | _T_5925; // @[ifu_mem_ctl.scala 694:81] + wire _T_5927 = _T_5926 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5937 = _T_4691 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5940 = _T_5458 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5941 = _T_5937 | _T_5940; // @[ifu_mem_ctl.scala 694:81] + wire _T_5942 = _T_5941 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5952 = _T_4692 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5955 = _T_5473 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5956 = _T_5952 | _T_5955; // @[ifu_mem_ctl.scala 694:81] + wire _T_5957 = _T_5956 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5967 = _T_4693 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5970 = _T_5488 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5971 = _T_5967 | _T_5970; // @[ifu_mem_ctl.scala 694:81] + wire _T_5972 = _T_5971 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5982 = _T_4694 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_5985 = _T_5503 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_5986 = _T_5982 | _T_5985; // @[ifu_mem_ctl.scala 694:81] + wire _T_5987 = _T_5986 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_5997 = _T_4695 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6000 = _T_5518 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6001 = _T_5997 | _T_6000; // @[ifu_mem_ctl.scala 694:81] + wire _T_6002 = _T_6001 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6012 = _T_4696 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6015 = _T_5533 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6016 = _T_6012 | _T_6015; // @[ifu_mem_ctl.scala 694:81] + wire _T_6017 = _T_6016 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6027 = _T_4697 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6030 = _T_5548 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6031 = _T_6027 | _T_6030; // @[ifu_mem_ctl.scala 694:81] + wire _T_6032 = _T_6031 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6042 = _T_4698 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6045 = _T_5563 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6046 = _T_6042 | _T_6045; // @[ifu_mem_ctl.scala 694:81] + wire _T_6047 = _T_6046 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6057 = _T_4699 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6060 = _T_5578 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6061 = _T_6057 | _T_6060; // @[ifu_mem_ctl.scala 694:81] + wire _T_6062 = _T_6061 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6072 = _T_4700 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6075 = _T_5593 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6076 = _T_6072 | _T_6075; // @[ifu_mem_ctl.scala 694:81] + wire _T_6077 = _T_6076 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6087 = _T_4701 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6090 = _T_5608 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6091 = _T_6087 | _T_6090; // @[ifu_mem_ctl.scala 694:81] + wire _T_6092 = _T_6091 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6102 = _T_4702 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6105 = _T_5623 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6106 = _T_6102 | _T_6105; // @[ifu_mem_ctl.scala 694:81] + wire _T_6107 = _T_6106 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6117 = _T_4703 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6118 = perr_ic_index_ff == 7'h20; // @[ifu_mem_ctl.scala 694:102] + wire _T_6120 = _T_6118 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6121 = _T_6117 | _T_6120; // @[ifu_mem_ctl.scala 694:81] + wire _T_6122 = _T_6121 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6132 = _T_4704 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6133 = perr_ic_index_ff == 7'h21; // @[ifu_mem_ctl.scala 694:102] + wire _T_6135 = _T_6133 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6136 = _T_6132 | _T_6135; // @[ifu_mem_ctl.scala 694:81] + wire _T_6137 = _T_6136 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6147 = _T_4705 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6148 = perr_ic_index_ff == 7'h22; // @[ifu_mem_ctl.scala 694:102] + wire _T_6150 = _T_6148 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6151 = _T_6147 | _T_6150; // @[ifu_mem_ctl.scala 694:81] + wire _T_6152 = _T_6151 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6162 = _T_4706 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6163 = perr_ic_index_ff == 7'h23; // @[ifu_mem_ctl.scala 694:102] + wire _T_6165 = _T_6163 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6166 = _T_6162 | _T_6165; // @[ifu_mem_ctl.scala 694:81] + wire _T_6167 = _T_6166 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6177 = _T_4707 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6178 = perr_ic_index_ff == 7'h24; // @[ifu_mem_ctl.scala 694:102] + wire _T_6180 = _T_6178 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6181 = _T_6177 | _T_6180; // @[ifu_mem_ctl.scala 694:81] + wire _T_6182 = _T_6181 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6192 = _T_4708 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6193 = perr_ic_index_ff == 7'h25; // @[ifu_mem_ctl.scala 694:102] + wire _T_6195 = _T_6193 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6196 = _T_6192 | _T_6195; // @[ifu_mem_ctl.scala 694:81] + wire _T_6197 = _T_6196 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6207 = _T_4709 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6208 = perr_ic_index_ff == 7'h26; // @[ifu_mem_ctl.scala 694:102] + wire _T_6210 = _T_6208 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6211 = _T_6207 | _T_6210; // @[ifu_mem_ctl.scala 694:81] + wire _T_6212 = _T_6211 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6222 = _T_4710 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6223 = perr_ic_index_ff == 7'h27; // @[ifu_mem_ctl.scala 694:102] + wire _T_6225 = _T_6223 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6226 = _T_6222 | _T_6225; // @[ifu_mem_ctl.scala 694:81] + wire _T_6227 = _T_6226 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6237 = _T_4711 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6238 = perr_ic_index_ff == 7'h28; // @[ifu_mem_ctl.scala 694:102] + wire _T_6240 = _T_6238 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6241 = _T_6237 | _T_6240; // @[ifu_mem_ctl.scala 694:81] + wire _T_6242 = _T_6241 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6252 = _T_4712 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6253 = perr_ic_index_ff == 7'h29; // @[ifu_mem_ctl.scala 694:102] + wire _T_6255 = _T_6253 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6256 = _T_6252 | _T_6255; // @[ifu_mem_ctl.scala 694:81] + wire _T_6257 = _T_6256 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6267 = _T_4713 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6268 = perr_ic_index_ff == 7'h2a; // @[ifu_mem_ctl.scala 694:102] + wire _T_6270 = _T_6268 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6271 = _T_6267 | _T_6270; // @[ifu_mem_ctl.scala 694:81] + wire _T_6272 = _T_6271 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6282 = _T_4714 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6283 = perr_ic_index_ff == 7'h2b; // @[ifu_mem_ctl.scala 694:102] + wire _T_6285 = _T_6283 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6286 = _T_6282 | _T_6285; // @[ifu_mem_ctl.scala 694:81] + wire _T_6287 = _T_6286 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6297 = _T_4715 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6298 = perr_ic_index_ff == 7'h2c; // @[ifu_mem_ctl.scala 694:102] + wire _T_6300 = _T_6298 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6301 = _T_6297 | _T_6300; // @[ifu_mem_ctl.scala 694:81] + wire _T_6302 = _T_6301 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6312 = _T_4716 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6313 = perr_ic_index_ff == 7'h2d; // @[ifu_mem_ctl.scala 694:102] + wire _T_6315 = _T_6313 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6316 = _T_6312 | _T_6315; // @[ifu_mem_ctl.scala 694:81] + wire _T_6317 = _T_6316 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6327 = _T_4717 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6328 = perr_ic_index_ff == 7'h2e; // @[ifu_mem_ctl.scala 694:102] + wire _T_6330 = _T_6328 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6331 = _T_6327 | _T_6330; // @[ifu_mem_ctl.scala 694:81] + wire _T_6332 = _T_6331 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6342 = _T_4718 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6343 = perr_ic_index_ff == 7'h2f; // @[ifu_mem_ctl.scala 694:102] + wire _T_6345 = _T_6343 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6346 = _T_6342 | _T_6345; // @[ifu_mem_ctl.scala 694:81] + wire _T_6347 = _T_6346 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6357 = _T_4719 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6358 = perr_ic_index_ff == 7'h30; // @[ifu_mem_ctl.scala 694:102] + wire _T_6360 = _T_6358 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6361 = _T_6357 | _T_6360; // @[ifu_mem_ctl.scala 694:81] + wire _T_6362 = _T_6361 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6372 = _T_4720 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6373 = perr_ic_index_ff == 7'h31; // @[ifu_mem_ctl.scala 694:102] + wire _T_6375 = _T_6373 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6376 = _T_6372 | _T_6375; // @[ifu_mem_ctl.scala 694:81] + wire _T_6377 = _T_6376 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6387 = _T_4721 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6388 = perr_ic_index_ff == 7'h32; // @[ifu_mem_ctl.scala 694:102] + wire _T_6390 = _T_6388 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6391 = _T_6387 | _T_6390; // @[ifu_mem_ctl.scala 694:81] + wire _T_6392 = _T_6391 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6402 = _T_4722 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6403 = perr_ic_index_ff == 7'h33; // @[ifu_mem_ctl.scala 694:102] + wire _T_6405 = _T_6403 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6406 = _T_6402 | _T_6405; // @[ifu_mem_ctl.scala 694:81] + wire _T_6407 = _T_6406 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6417 = _T_4723 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6418 = perr_ic_index_ff == 7'h34; // @[ifu_mem_ctl.scala 694:102] + wire _T_6420 = _T_6418 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6421 = _T_6417 | _T_6420; // @[ifu_mem_ctl.scala 694:81] + wire _T_6422 = _T_6421 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6432 = _T_4724 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6433 = perr_ic_index_ff == 7'h35; // @[ifu_mem_ctl.scala 694:102] + wire _T_6435 = _T_6433 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6436 = _T_6432 | _T_6435; // @[ifu_mem_ctl.scala 694:81] + wire _T_6437 = _T_6436 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6447 = _T_4725 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6448 = perr_ic_index_ff == 7'h36; // @[ifu_mem_ctl.scala 694:102] + wire _T_6450 = _T_6448 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6451 = _T_6447 | _T_6450; // @[ifu_mem_ctl.scala 694:81] + wire _T_6452 = _T_6451 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6462 = _T_4726 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6463 = perr_ic_index_ff == 7'h37; // @[ifu_mem_ctl.scala 694:102] + wire _T_6465 = _T_6463 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6466 = _T_6462 | _T_6465; // @[ifu_mem_ctl.scala 694:81] + wire _T_6467 = _T_6466 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6477 = _T_4727 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6478 = perr_ic_index_ff == 7'h38; // @[ifu_mem_ctl.scala 694:102] + wire _T_6480 = _T_6478 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6481 = _T_6477 | _T_6480; // @[ifu_mem_ctl.scala 694:81] + wire _T_6482 = _T_6481 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6492 = _T_4728 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6493 = perr_ic_index_ff == 7'h39; // @[ifu_mem_ctl.scala 694:102] + wire _T_6495 = _T_6493 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6496 = _T_6492 | _T_6495; // @[ifu_mem_ctl.scala 694:81] + wire _T_6497 = _T_6496 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6507 = _T_4729 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6508 = perr_ic_index_ff == 7'h3a; // @[ifu_mem_ctl.scala 694:102] + wire _T_6510 = _T_6508 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6511 = _T_6507 | _T_6510; // @[ifu_mem_ctl.scala 694:81] + wire _T_6512 = _T_6511 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6522 = _T_4730 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6523 = perr_ic_index_ff == 7'h3b; // @[ifu_mem_ctl.scala 694:102] + wire _T_6525 = _T_6523 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6526 = _T_6522 | _T_6525; // @[ifu_mem_ctl.scala 694:81] + wire _T_6527 = _T_6526 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6537 = _T_4731 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6538 = perr_ic_index_ff == 7'h3c; // @[ifu_mem_ctl.scala 694:102] + wire _T_6540 = _T_6538 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6541 = _T_6537 | _T_6540; // @[ifu_mem_ctl.scala 694:81] + wire _T_6542 = _T_6541 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6552 = _T_4732 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6553 = perr_ic_index_ff == 7'h3d; // @[ifu_mem_ctl.scala 694:102] + wire _T_6555 = _T_6553 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6556 = _T_6552 | _T_6555; // @[ifu_mem_ctl.scala 694:81] + wire _T_6557 = _T_6556 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6567 = _T_4733 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6568 = perr_ic_index_ff == 7'h3e; // @[ifu_mem_ctl.scala 694:102] + wire _T_6570 = _T_6568 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6571 = _T_6567 | _T_6570; // @[ifu_mem_ctl.scala 694:81] + wire _T_6572 = _T_6571 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6582 = _T_4734 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6583 = perr_ic_index_ff == 7'h3f; // @[ifu_mem_ctl.scala 694:102] + wire _T_6585 = _T_6583 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6586 = _T_6582 | _T_6585; // @[ifu_mem_ctl.scala 694:81] + wire _T_6587 = _T_6586 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6597 = _T_4703 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6600 = _T_6118 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6601 = _T_6597 | _T_6600; // @[ifu_mem_ctl.scala 694:81] + wire _T_6602 = _T_6601 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6612 = _T_4704 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6615 = _T_6133 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6616 = _T_6612 | _T_6615; // @[ifu_mem_ctl.scala 694:81] + wire _T_6617 = _T_6616 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6627 = _T_4705 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6630 = _T_6148 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6631 = _T_6627 | _T_6630; // @[ifu_mem_ctl.scala 694:81] + wire _T_6632 = _T_6631 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6642 = _T_4706 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6645 = _T_6163 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6646 = _T_6642 | _T_6645; // @[ifu_mem_ctl.scala 694:81] + wire _T_6647 = _T_6646 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6657 = _T_4707 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6660 = _T_6178 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6661 = _T_6657 | _T_6660; // @[ifu_mem_ctl.scala 694:81] + wire _T_6662 = _T_6661 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6672 = _T_4708 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6675 = _T_6193 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6676 = _T_6672 | _T_6675; // @[ifu_mem_ctl.scala 694:81] + wire _T_6677 = _T_6676 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6687 = _T_4709 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6690 = _T_6208 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6691 = _T_6687 | _T_6690; // @[ifu_mem_ctl.scala 694:81] + wire _T_6692 = _T_6691 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6702 = _T_4710 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6705 = _T_6223 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6706 = _T_6702 | _T_6705; // @[ifu_mem_ctl.scala 694:81] + wire _T_6707 = _T_6706 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6717 = _T_4711 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6720 = _T_6238 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6721 = _T_6717 | _T_6720; // @[ifu_mem_ctl.scala 694:81] + wire _T_6722 = _T_6721 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6732 = _T_4712 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6735 = _T_6253 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6736 = _T_6732 | _T_6735; // @[ifu_mem_ctl.scala 694:81] + wire _T_6737 = _T_6736 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6747 = _T_4713 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6750 = _T_6268 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6751 = _T_6747 | _T_6750; // @[ifu_mem_ctl.scala 694:81] + wire _T_6752 = _T_6751 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6762 = _T_4714 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6765 = _T_6283 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6766 = _T_6762 | _T_6765; // @[ifu_mem_ctl.scala 694:81] + wire _T_6767 = _T_6766 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6777 = _T_4715 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6780 = _T_6298 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6781 = _T_6777 | _T_6780; // @[ifu_mem_ctl.scala 694:81] + wire _T_6782 = _T_6781 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6792 = _T_4716 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6795 = _T_6313 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6796 = _T_6792 | _T_6795; // @[ifu_mem_ctl.scala 694:81] + wire _T_6797 = _T_6796 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6807 = _T_4717 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6810 = _T_6328 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6811 = _T_6807 | _T_6810; // @[ifu_mem_ctl.scala 694:81] + wire _T_6812 = _T_6811 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6822 = _T_4718 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6825 = _T_6343 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6826 = _T_6822 | _T_6825; // @[ifu_mem_ctl.scala 694:81] + wire _T_6827 = _T_6826 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6837 = _T_4719 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6840 = _T_6358 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6841 = _T_6837 | _T_6840; // @[ifu_mem_ctl.scala 694:81] + wire _T_6842 = _T_6841 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6852 = _T_4720 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6855 = _T_6373 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6856 = _T_6852 | _T_6855; // @[ifu_mem_ctl.scala 694:81] + wire _T_6857 = _T_6856 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6867 = _T_4721 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6870 = _T_6388 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6871 = _T_6867 | _T_6870; // @[ifu_mem_ctl.scala 694:81] + wire _T_6872 = _T_6871 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6882 = _T_4722 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6885 = _T_6403 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6886 = _T_6882 | _T_6885; // @[ifu_mem_ctl.scala 694:81] + wire _T_6887 = _T_6886 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6897 = _T_4723 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6900 = _T_6418 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6901 = _T_6897 | _T_6900; // @[ifu_mem_ctl.scala 694:81] + wire _T_6902 = _T_6901 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6912 = _T_4724 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6915 = _T_6433 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6916 = _T_6912 | _T_6915; // @[ifu_mem_ctl.scala 694:81] + wire _T_6917 = _T_6916 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6927 = _T_4725 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6930 = _T_6448 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6931 = _T_6927 | _T_6930; // @[ifu_mem_ctl.scala 694:81] + wire _T_6932 = _T_6931 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6942 = _T_4726 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6945 = _T_6463 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6946 = _T_6942 | _T_6945; // @[ifu_mem_ctl.scala 694:81] + wire _T_6947 = _T_6946 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6957 = _T_4727 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6960 = _T_6478 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6961 = _T_6957 | _T_6960; // @[ifu_mem_ctl.scala 694:81] + wire _T_6962 = _T_6961 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6972 = _T_4728 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6975 = _T_6493 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6976 = _T_6972 | _T_6975; // @[ifu_mem_ctl.scala 694:81] + wire _T_6977 = _T_6976 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_6987 = _T_4729 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_6990 = _T_6508 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_6991 = _T_6987 | _T_6990; // @[ifu_mem_ctl.scala 694:81] + wire _T_6992 = _T_6991 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7002 = _T_4730 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7005 = _T_6523 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7006 = _T_7002 | _T_7005; // @[ifu_mem_ctl.scala 694:81] + wire _T_7007 = _T_7006 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7017 = _T_4731 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7020 = _T_6538 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7021 = _T_7017 | _T_7020; // @[ifu_mem_ctl.scala 694:81] + wire _T_7022 = _T_7021 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7032 = _T_4732 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7035 = _T_6553 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7036 = _T_7032 | _T_7035; // @[ifu_mem_ctl.scala 694:81] + wire _T_7037 = _T_7036 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7047 = _T_4733 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7050 = _T_6568 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7051 = _T_7047 | _T_7050; // @[ifu_mem_ctl.scala 694:81] + wire _T_7052 = _T_7051 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7062 = _T_4734 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7065 = _T_6583 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7066 = _T_7062 | _T_7065; // @[ifu_mem_ctl.scala 694:81] + wire _T_7067 = _T_7066 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7077 = _T_4735 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7078 = perr_ic_index_ff == 7'h40; // @[ifu_mem_ctl.scala 694:102] + wire _T_7080 = _T_7078 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7081 = _T_7077 | _T_7080; // @[ifu_mem_ctl.scala 694:81] + wire _T_7082 = _T_7081 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7092 = _T_4736 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7093 = perr_ic_index_ff == 7'h41; // @[ifu_mem_ctl.scala 694:102] + wire _T_7095 = _T_7093 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7096 = _T_7092 | _T_7095; // @[ifu_mem_ctl.scala 694:81] + wire _T_7097 = _T_7096 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7107 = _T_4737 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7108 = perr_ic_index_ff == 7'h42; // @[ifu_mem_ctl.scala 694:102] + wire _T_7110 = _T_7108 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7111 = _T_7107 | _T_7110; // @[ifu_mem_ctl.scala 694:81] + wire _T_7112 = _T_7111 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7122 = _T_4738 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7123 = perr_ic_index_ff == 7'h43; // @[ifu_mem_ctl.scala 694:102] + wire _T_7125 = _T_7123 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7126 = _T_7122 | _T_7125; // @[ifu_mem_ctl.scala 694:81] + wire _T_7127 = _T_7126 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7137 = _T_4739 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7138 = perr_ic_index_ff == 7'h44; // @[ifu_mem_ctl.scala 694:102] + wire _T_7140 = _T_7138 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7141 = _T_7137 | _T_7140; // @[ifu_mem_ctl.scala 694:81] + wire _T_7142 = _T_7141 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7152 = _T_4740 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7153 = perr_ic_index_ff == 7'h45; // @[ifu_mem_ctl.scala 694:102] + wire _T_7155 = _T_7153 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7156 = _T_7152 | _T_7155; // @[ifu_mem_ctl.scala 694:81] + wire _T_7157 = _T_7156 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7167 = _T_4741 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7168 = perr_ic_index_ff == 7'h46; // @[ifu_mem_ctl.scala 694:102] + wire _T_7170 = _T_7168 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7171 = _T_7167 | _T_7170; // @[ifu_mem_ctl.scala 694:81] + wire _T_7172 = _T_7171 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7182 = _T_4742 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7183 = perr_ic_index_ff == 7'h47; // @[ifu_mem_ctl.scala 694:102] + wire _T_7185 = _T_7183 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7186 = _T_7182 | _T_7185; // @[ifu_mem_ctl.scala 694:81] + wire _T_7187 = _T_7186 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7197 = _T_4743 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7198 = perr_ic_index_ff == 7'h48; // @[ifu_mem_ctl.scala 694:102] + wire _T_7200 = _T_7198 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7201 = _T_7197 | _T_7200; // @[ifu_mem_ctl.scala 694:81] + wire _T_7202 = _T_7201 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7212 = _T_4744 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7213 = perr_ic_index_ff == 7'h49; // @[ifu_mem_ctl.scala 694:102] + wire _T_7215 = _T_7213 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7216 = _T_7212 | _T_7215; // @[ifu_mem_ctl.scala 694:81] + wire _T_7217 = _T_7216 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7227 = _T_4745 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7228 = perr_ic_index_ff == 7'h4a; // @[ifu_mem_ctl.scala 694:102] + wire _T_7230 = _T_7228 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7231 = _T_7227 | _T_7230; // @[ifu_mem_ctl.scala 694:81] + wire _T_7232 = _T_7231 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7242 = _T_4746 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7243 = perr_ic_index_ff == 7'h4b; // @[ifu_mem_ctl.scala 694:102] + wire _T_7245 = _T_7243 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7246 = _T_7242 | _T_7245; // @[ifu_mem_ctl.scala 694:81] + wire _T_7247 = _T_7246 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7257 = _T_4747 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7258 = perr_ic_index_ff == 7'h4c; // @[ifu_mem_ctl.scala 694:102] + wire _T_7260 = _T_7258 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7261 = _T_7257 | _T_7260; // @[ifu_mem_ctl.scala 694:81] + wire _T_7262 = _T_7261 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7272 = _T_4748 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7273 = perr_ic_index_ff == 7'h4d; // @[ifu_mem_ctl.scala 694:102] + wire _T_7275 = _T_7273 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7276 = _T_7272 | _T_7275; // @[ifu_mem_ctl.scala 694:81] + wire _T_7277 = _T_7276 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7287 = _T_4749 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7288 = perr_ic_index_ff == 7'h4e; // @[ifu_mem_ctl.scala 694:102] + wire _T_7290 = _T_7288 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7291 = _T_7287 | _T_7290; // @[ifu_mem_ctl.scala 694:81] + wire _T_7292 = _T_7291 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7302 = _T_4750 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7303 = perr_ic_index_ff == 7'h4f; // @[ifu_mem_ctl.scala 694:102] + wire _T_7305 = _T_7303 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7306 = _T_7302 | _T_7305; // @[ifu_mem_ctl.scala 694:81] + wire _T_7307 = _T_7306 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7317 = _T_4751 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7318 = perr_ic_index_ff == 7'h50; // @[ifu_mem_ctl.scala 694:102] + wire _T_7320 = _T_7318 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7321 = _T_7317 | _T_7320; // @[ifu_mem_ctl.scala 694:81] + wire _T_7322 = _T_7321 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7332 = _T_4752 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7333 = perr_ic_index_ff == 7'h51; // @[ifu_mem_ctl.scala 694:102] + wire _T_7335 = _T_7333 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7336 = _T_7332 | _T_7335; // @[ifu_mem_ctl.scala 694:81] + wire _T_7337 = _T_7336 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7347 = _T_4753 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7348 = perr_ic_index_ff == 7'h52; // @[ifu_mem_ctl.scala 694:102] + wire _T_7350 = _T_7348 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7351 = _T_7347 | _T_7350; // @[ifu_mem_ctl.scala 694:81] + wire _T_7352 = _T_7351 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7362 = _T_4754 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7363 = perr_ic_index_ff == 7'h53; // @[ifu_mem_ctl.scala 694:102] + wire _T_7365 = _T_7363 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7366 = _T_7362 | _T_7365; // @[ifu_mem_ctl.scala 694:81] + wire _T_7367 = _T_7366 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7377 = _T_4755 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7378 = perr_ic_index_ff == 7'h54; // @[ifu_mem_ctl.scala 694:102] + wire _T_7380 = _T_7378 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7381 = _T_7377 | _T_7380; // @[ifu_mem_ctl.scala 694:81] + wire _T_7382 = _T_7381 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7392 = _T_4756 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7393 = perr_ic_index_ff == 7'h55; // @[ifu_mem_ctl.scala 694:102] + wire _T_7395 = _T_7393 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7396 = _T_7392 | _T_7395; // @[ifu_mem_ctl.scala 694:81] + wire _T_7397 = _T_7396 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7407 = _T_4757 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7408 = perr_ic_index_ff == 7'h56; // @[ifu_mem_ctl.scala 694:102] + wire _T_7410 = _T_7408 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7411 = _T_7407 | _T_7410; // @[ifu_mem_ctl.scala 694:81] + wire _T_7412 = _T_7411 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7422 = _T_4758 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7423 = perr_ic_index_ff == 7'h57; // @[ifu_mem_ctl.scala 694:102] + wire _T_7425 = _T_7423 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7426 = _T_7422 | _T_7425; // @[ifu_mem_ctl.scala 694:81] + wire _T_7427 = _T_7426 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7437 = _T_4759 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7438 = perr_ic_index_ff == 7'h58; // @[ifu_mem_ctl.scala 694:102] + wire _T_7440 = _T_7438 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7441 = _T_7437 | _T_7440; // @[ifu_mem_ctl.scala 694:81] + wire _T_7442 = _T_7441 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7452 = _T_4760 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7453 = perr_ic_index_ff == 7'h59; // @[ifu_mem_ctl.scala 694:102] + wire _T_7455 = _T_7453 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7456 = _T_7452 | _T_7455; // @[ifu_mem_ctl.scala 694:81] + wire _T_7457 = _T_7456 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7467 = _T_4761 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7468 = perr_ic_index_ff == 7'h5a; // @[ifu_mem_ctl.scala 694:102] + wire _T_7470 = _T_7468 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7471 = _T_7467 | _T_7470; // @[ifu_mem_ctl.scala 694:81] + wire _T_7472 = _T_7471 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7482 = _T_4762 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7483 = perr_ic_index_ff == 7'h5b; // @[ifu_mem_ctl.scala 694:102] + wire _T_7485 = _T_7483 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7486 = _T_7482 | _T_7485; // @[ifu_mem_ctl.scala 694:81] + wire _T_7487 = _T_7486 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7497 = _T_4763 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7498 = perr_ic_index_ff == 7'h5c; // @[ifu_mem_ctl.scala 694:102] + wire _T_7500 = _T_7498 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7501 = _T_7497 | _T_7500; // @[ifu_mem_ctl.scala 694:81] + wire _T_7502 = _T_7501 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7512 = _T_4764 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7513 = perr_ic_index_ff == 7'h5d; // @[ifu_mem_ctl.scala 694:102] + wire _T_7515 = _T_7513 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7516 = _T_7512 | _T_7515; // @[ifu_mem_ctl.scala 694:81] + wire _T_7517 = _T_7516 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7527 = _T_4765 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7528 = perr_ic_index_ff == 7'h5e; // @[ifu_mem_ctl.scala 694:102] + wire _T_7530 = _T_7528 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7531 = _T_7527 | _T_7530; // @[ifu_mem_ctl.scala 694:81] + wire _T_7532 = _T_7531 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7542 = _T_4766 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7543 = perr_ic_index_ff == 7'h5f; // @[ifu_mem_ctl.scala 694:102] + wire _T_7545 = _T_7543 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7546 = _T_7542 | _T_7545; // @[ifu_mem_ctl.scala 694:81] + wire _T_7547 = _T_7546 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7557 = _T_4735 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7560 = _T_7078 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7561 = _T_7557 | _T_7560; // @[ifu_mem_ctl.scala 694:81] + wire _T_7562 = _T_7561 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7572 = _T_4736 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7575 = _T_7093 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7576 = _T_7572 | _T_7575; // @[ifu_mem_ctl.scala 694:81] + wire _T_7577 = _T_7576 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7587 = _T_4737 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7590 = _T_7108 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7591 = _T_7587 | _T_7590; // @[ifu_mem_ctl.scala 694:81] + wire _T_7592 = _T_7591 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7602 = _T_4738 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7605 = _T_7123 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7606 = _T_7602 | _T_7605; // @[ifu_mem_ctl.scala 694:81] + wire _T_7607 = _T_7606 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7617 = _T_4739 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7620 = _T_7138 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7621 = _T_7617 | _T_7620; // @[ifu_mem_ctl.scala 694:81] + wire _T_7622 = _T_7621 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7632 = _T_4740 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7635 = _T_7153 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7636 = _T_7632 | _T_7635; // @[ifu_mem_ctl.scala 694:81] + wire _T_7637 = _T_7636 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7647 = _T_4741 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7650 = _T_7168 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7651 = _T_7647 | _T_7650; // @[ifu_mem_ctl.scala 694:81] + wire _T_7652 = _T_7651 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7662 = _T_4742 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7665 = _T_7183 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7666 = _T_7662 | _T_7665; // @[ifu_mem_ctl.scala 694:81] + wire _T_7667 = _T_7666 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7677 = _T_4743 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7680 = _T_7198 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7681 = _T_7677 | _T_7680; // @[ifu_mem_ctl.scala 694:81] + wire _T_7682 = _T_7681 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7692 = _T_4744 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7695 = _T_7213 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7696 = _T_7692 | _T_7695; // @[ifu_mem_ctl.scala 694:81] + wire _T_7697 = _T_7696 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7707 = _T_4745 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7710 = _T_7228 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7711 = _T_7707 | _T_7710; // @[ifu_mem_ctl.scala 694:81] + wire _T_7712 = _T_7711 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7722 = _T_4746 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7725 = _T_7243 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7726 = _T_7722 | _T_7725; // @[ifu_mem_ctl.scala 694:81] + wire _T_7727 = _T_7726 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7737 = _T_4747 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7740 = _T_7258 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7741 = _T_7737 | _T_7740; // @[ifu_mem_ctl.scala 694:81] + wire _T_7742 = _T_7741 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7752 = _T_4748 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7755 = _T_7273 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7756 = _T_7752 | _T_7755; // @[ifu_mem_ctl.scala 694:81] + wire _T_7757 = _T_7756 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7767 = _T_4749 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7770 = _T_7288 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7771 = _T_7767 | _T_7770; // @[ifu_mem_ctl.scala 694:81] + wire _T_7772 = _T_7771 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7782 = _T_4750 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7785 = _T_7303 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7786 = _T_7782 | _T_7785; // @[ifu_mem_ctl.scala 694:81] + wire _T_7787 = _T_7786 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7797 = _T_4751 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7800 = _T_7318 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7801 = _T_7797 | _T_7800; // @[ifu_mem_ctl.scala 694:81] + wire _T_7802 = _T_7801 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7812 = _T_4752 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7815 = _T_7333 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7816 = _T_7812 | _T_7815; // @[ifu_mem_ctl.scala 694:81] + wire _T_7817 = _T_7816 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7827 = _T_4753 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7830 = _T_7348 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7831 = _T_7827 | _T_7830; // @[ifu_mem_ctl.scala 694:81] + wire _T_7832 = _T_7831 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7842 = _T_4754 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7845 = _T_7363 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7846 = _T_7842 | _T_7845; // @[ifu_mem_ctl.scala 694:81] + wire _T_7847 = _T_7846 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7857 = _T_4755 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7860 = _T_7378 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7861 = _T_7857 | _T_7860; // @[ifu_mem_ctl.scala 694:81] + wire _T_7862 = _T_7861 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7872 = _T_4756 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7875 = _T_7393 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7876 = _T_7872 | _T_7875; // @[ifu_mem_ctl.scala 694:81] + wire _T_7877 = _T_7876 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7887 = _T_4757 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7890 = _T_7408 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7891 = _T_7887 | _T_7890; // @[ifu_mem_ctl.scala 694:81] + wire _T_7892 = _T_7891 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7902 = _T_4758 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7905 = _T_7423 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7906 = _T_7902 | _T_7905; // @[ifu_mem_ctl.scala 694:81] + wire _T_7907 = _T_7906 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7917 = _T_4759 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7920 = _T_7438 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7921 = _T_7917 | _T_7920; // @[ifu_mem_ctl.scala 694:81] + wire _T_7922 = _T_7921 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7932 = _T_4760 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7935 = _T_7453 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7936 = _T_7932 | _T_7935; // @[ifu_mem_ctl.scala 694:81] + wire _T_7937 = _T_7936 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7947 = _T_4761 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7950 = _T_7468 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7951 = _T_7947 | _T_7950; // @[ifu_mem_ctl.scala 694:81] + wire _T_7952 = _T_7951 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7962 = _T_4762 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7965 = _T_7483 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7966 = _T_7962 | _T_7965; // @[ifu_mem_ctl.scala 694:81] + wire _T_7967 = _T_7966 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7977 = _T_4763 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7980 = _T_7498 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7981 = _T_7977 | _T_7980; // @[ifu_mem_ctl.scala 694:81] + wire _T_7982 = _T_7981 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_7992 = _T_4764 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_7995 = _T_7513 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_7996 = _T_7992 | _T_7995; // @[ifu_mem_ctl.scala 694:81] + wire _T_7997 = _T_7996 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8007 = _T_4765 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8010 = _T_7528 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8011 = _T_8007 | _T_8010; // @[ifu_mem_ctl.scala 694:81] + wire _T_8012 = _T_8011 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8022 = _T_4766 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8025 = _T_7543 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8026 = _T_8022 | _T_8025; // @[ifu_mem_ctl.scala 694:81] + wire _T_8027 = _T_8026 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8037 = _T_4767 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8038 = perr_ic_index_ff == 7'h60; // @[ifu_mem_ctl.scala 694:102] + wire _T_8040 = _T_8038 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8041 = _T_8037 | _T_8040; // @[ifu_mem_ctl.scala 694:81] + wire _T_8042 = _T_8041 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8052 = _T_4768 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8053 = perr_ic_index_ff == 7'h61; // @[ifu_mem_ctl.scala 694:102] + wire _T_8055 = _T_8053 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8056 = _T_8052 | _T_8055; // @[ifu_mem_ctl.scala 694:81] + wire _T_8057 = _T_8056 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8067 = _T_4769 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8068 = perr_ic_index_ff == 7'h62; // @[ifu_mem_ctl.scala 694:102] + wire _T_8070 = _T_8068 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8071 = _T_8067 | _T_8070; // @[ifu_mem_ctl.scala 694:81] + wire _T_8072 = _T_8071 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8082 = _T_4770 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8083 = perr_ic_index_ff == 7'h63; // @[ifu_mem_ctl.scala 694:102] + wire _T_8085 = _T_8083 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8086 = _T_8082 | _T_8085; // @[ifu_mem_ctl.scala 694:81] + wire _T_8087 = _T_8086 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8097 = _T_4771 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8098 = perr_ic_index_ff == 7'h64; // @[ifu_mem_ctl.scala 694:102] + wire _T_8100 = _T_8098 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8101 = _T_8097 | _T_8100; // @[ifu_mem_ctl.scala 694:81] + wire _T_8102 = _T_8101 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8112 = _T_4772 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8113 = perr_ic_index_ff == 7'h65; // @[ifu_mem_ctl.scala 694:102] + wire _T_8115 = _T_8113 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8116 = _T_8112 | _T_8115; // @[ifu_mem_ctl.scala 694:81] + wire _T_8117 = _T_8116 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8127 = _T_4773 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8128 = perr_ic_index_ff == 7'h66; // @[ifu_mem_ctl.scala 694:102] + wire _T_8130 = _T_8128 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8131 = _T_8127 | _T_8130; // @[ifu_mem_ctl.scala 694:81] + wire _T_8132 = _T_8131 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8142 = _T_4774 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8143 = perr_ic_index_ff == 7'h67; // @[ifu_mem_ctl.scala 694:102] + wire _T_8145 = _T_8143 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8146 = _T_8142 | _T_8145; // @[ifu_mem_ctl.scala 694:81] + wire _T_8147 = _T_8146 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8157 = _T_4775 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8158 = perr_ic_index_ff == 7'h68; // @[ifu_mem_ctl.scala 694:102] + wire _T_8160 = _T_8158 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8161 = _T_8157 | _T_8160; // @[ifu_mem_ctl.scala 694:81] + wire _T_8162 = _T_8161 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8172 = _T_4776 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8173 = perr_ic_index_ff == 7'h69; // @[ifu_mem_ctl.scala 694:102] + wire _T_8175 = _T_8173 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8176 = _T_8172 | _T_8175; // @[ifu_mem_ctl.scala 694:81] + wire _T_8177 = _T_8176 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8187 = _T_4777 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8188 = perr_ic_index_ff == 7'h6a; // @[ifu_mem_ctl.scala 694:102] + wire _T_8190 = _T_8188 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8191 = _T_8187 | _T_8190; // @[ifu_mem_ctl.scala 694:81] + wire _T_8192 = _T_8191 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8202 = _T_4778 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8203 = perr_ic_index_ff == 7'h6b; // @[ifu_mem_ctl.scala 694:102] + wire _T_8205 = _T_8203 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8206 = _T_8202 | _T_8205; // @[ifu_mem_ctl.scala 694:81] + wire _T_8207 = _T_8206 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8217 = _T_4779 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8218 = perr_ic_index_ff == 7'h6c; // @[ifu_mem_ctl.scala 694:102] + wire _T_8220 = _T_8218 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8221 = _T_8217 | _T_8220; // @[ifu_mem_ctl.scala 694:81] + wire _T_8222 = _T_8221 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8232 = _T_4780 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8233 = perr_ic_index_ff == 7'h6d; // @[ifu_mem_ctl.scala 694:102] + wire _T_8235 = _T_8233 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8236 = _T_8232 | _T_8235; // @[ifu_mem_ctl.scala 694:81] + wire _T_8237 = _T_8236 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8247 = _T_4781 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8248 = perr_ic_index_ff == 7'h6e; // @[ifu_mem_ctl.scala 694:102] + wire _T_8250 = _T_8248 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8251 = _T_8247 | _T_8250; // @[ifu_mem_ctl.scala 694:81] + wire _T_8252 = _T_8251 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8262 = _T_4782 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8263 = perr_ic_index_ff == 7'h6f; // @[ifu_mem_ctl.scala 694:102] + wire _T_8265 = _T_8263 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8266 = _T_8262 | _T_8265; // @[ifu_mem_ctl.scala 694:81] + wire _T_8267 = _T_8266 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8277 = _T_4783 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8278 = perr_ic_index_ff == 7'h70; // @[ifu_mem_ctl.scala 694:102] + wire _T_8280 = _T_8278 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8281 = _T_8277 | _T_8280; // @[ifu_mem_ctl.scala 694:81] + wire _T_8282 = _T_8281 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8292 = _T_4784 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8293 = perr_ic_index_ff == 7'h71; // @[ifu_mem_ctl.scala 694:102] + wire _T_8295 = _T_8293 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8296 = _T_8292 | _T_8295; // @[ifu_mem_ctl.scala 694:81] + wire _T_8297 = _T_8296 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8307 = _T_4785 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8308 = perr_ic_index_ff == 7'h72; // @[ifu_mem_ctl.scala 694:102] + wire _T_8310 = _T_8308 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8311 = _T_8307 | _T_8310; // @[ifu_mem_ctl.scala 694:81] + wire _T_8312 = _T_8311 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8322 = _T_4786 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8323 = perr_ic_index_ff == 7'h73; // @[ifu_mem_ctl.scala 694:102] + wire _T_8325 = _T_8323 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8326 = _T_8322 | _T_8325; // @[ifu_mem_ctl.scala 694:81] + wire _T_8327 = _T_8326 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8337 = _T_4787 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8338 = perr_ic_index_ff == 7'h74; // @[ifu_mem_ctl.scala 694:102] + wire _T_8340 = _T_8338 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8341 = _T_8337 | _T_8340; // @[ifu_mem_ctl.scala 694:81] + wire _T_8342 = _T_8341 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8352 = _T_4788 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8353 = perr_ic_index_ff == 7'h75; // @[ifu_mem_ctl.scala 694:102] + wire _T_8355 = _T_8353 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8356 = _T_8352 | _T_8355; // @[ifu_mem_ctl.scala 694:81] + wire _T_8357 = _T_8356 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8367 = _T_4789 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8368 = perr_ic_index_ff == 7'h76; // @[ifu_mem_ctl.scala 694:102] + wire _T_8370 = _T_8368 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8371 = _T_8367 | _T_8370; // @[ifu_mem_ctl.scala 694:81] + wire _T_8372 = _T_8371 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8382 = _T_4790 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8383 = perr_ic_index_ff == 7'h77; // @[ifu_mem_ctl.scala 694:102] + wire _T_8385 = _T_8383 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8386 = _T_8382 | _T_8385; // @[ifu_mem_ctl.scala 694:81] + wire _T_8387 = _T_8386 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8397 = _T_4791 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8398 = perr_ic_index_ff == 7'h78; // @[ifu_mem_ctl.scala 694:102] + wire _T_8400 = _T_8398 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8401 = _T_8397 | _T_8400; // @[ifu_mem_ctl.scala 694:81] + wire _T_8402 = _T_8401 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8412 = _T_4792 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8413 = perr_ic_index_ff == 7'h79; // @[ifu_mem_ctl.scala 694:102] + wire _T_8415 = _T_8413 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8416 = _T_8412 | _T_8415; // @[ifu_mem_ctl.scala 694:81] + wire _T_8417 = _T_8416 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8427 = _T_4793 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8428 = perr_ic_index_ff == 7'h7a; // @[ifu_mem_ctl.scala 694:102] + wire _T_8430 = _T_8428 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8431 = _T_8427 | _T_8430; // @[ifu_mem_ctl.scala 694:81] + wire _T_8432 = _T_8431 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8442 = _T_4794 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8443 = perr_ic_index_ff == 7'h7b; // @[ifu_mem_ctl.scala 694:102] + wire _T_8445 = _T_8443 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8446 = _T_8442 | _T_8445; // @[ifu_mem_ctl.scala 694:81] + wire _T_8447 = _T_8446 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8457 = _T_4795 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8458 = perr_ic_index_ff == 7'h7c; // @[ifu_mem_ctl.scala 694:102] + wire _T_8460 = _T_8458 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8461 = _T_8457 | _T_8460; // @[ifu_mem_ctl.scala 694:81] + wire _T_8462 = _T_8461 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8472 = _T_4796 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8473 = perr_ic_index_ff == 7'h7d; // @[ifu_mem_ctl.scala 694:102] + wire _T_8475 = _T_8473 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8476 = _T_8472 | _T_8475; // @[ifu_mem_ctl.scala 694:81] + wire _T_8477 = _T_8476 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8487 = _T_4797 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8488 = perr_ic_index_ff == 7'h7e; // @[ifu_mem_ctl.scala 694:102] + wire _T_8490 = _T_8488 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8491 = _T_8487 | _T_8490; // @[ifu_mem_ctl.scala 694:81] + wire _T_8492 = _T_8491 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8502 = _T_4798 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8503 = perr_ic_index_ff == 7'h7f; // @[ifu_mem_ctl.scala 694:102] + wire _T_8505 = _T_8503 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8506 = _T_8502 | _T_8505; // @[ifu_mem_ctl.scala 694:81] + wire _T_8507 = _T_8506 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8517 = _T_4767 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8520 = _T_8038 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8521 = _T_8517 | _T_8520; // @[ifu_mem_ctl.scala 694:81] + wire _T_8522 = _T_8521 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8532 = _T_4768 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8535 = _T_8053 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8536 = _T_8532 | _T_8535; // @[ifu_mem_ctl.scala 694:81] + wire _T_8537 = _T_8536 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8547 = _T_4769 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8550 = _T_8068 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8551 = _T_8547 | _T_8550; // @[ifu_mem_ctl.scala 694:81] + wire _T_8552 = _T_8551 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8562 = _T_4770 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8565 = _T_8083 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8566 = _T_8562 | _T_8565; // @[ifu_mem_ctl.scala 694:81] + wire _T_8567 = _T_8566 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8577 = _T_4771 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8580 = _T_8098 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8581 = _T_8577 | _T_8580; // @[ifu_mem_ctl.scala 694:81] + wire _T_8582 = _T_8581 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8592 = _T_4772 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8595 = _T_8113 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8596 = _T_8592 | _T_8595; // @[ifu_mem_ctl.scala 694:81] + wire _T_8597 = _T_8596 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8607 = _T_4773 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8610 = _T_8128 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8611 = _T_8607 | _T_8610; // @[ifu_mem_ctl.scala 694:81] + wire _T_8612 = _T_8611 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8622 = _T_4774 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8625 = _T_8143 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8626 = _T_8622 | _T_8625; // @[ifu_mem_ctl.scala 694:81] + wire _T_8627 = _T_8626 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8637 = _T_4775 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8640 = _T_8158 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8641 = _T_8637 | _T_8640; // @[ifu_mem_ctl.scala 694:81] + wire _T_8642 = _T_8641 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8652 = _T_4776 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8655 = _T_8173 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8656 = _T_8652 | _T_8655; // @[ifu_mem_ctl.scala 694:81] + wire _T_8657 = _T_8656 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8667 = _T_4777 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8670 = _T_8188 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8671 = _T_8667 | _T_8670; // @[ifu_mem_ctl.scala 694:81] + wire _T_8672 = _T_8671 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8682 = _T_4778 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8685 = _T_8203 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8686 = _T_8682 | _T_8685; // @[ifu_mem_ctl.scala 694:81] + wire _T_8687 = _T_8686 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8697 = _T_4779 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8700 = _T_8218 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8701 = _T_8697 | _T_8700; // @[ifu_mem_ctl.scala 694:81] + wire _T_8702 = _T_8701 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8712 = _T_4780 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8715 = _T_8233 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8716 = _T_8712 | _T_8715; // @[ifu_mem_ctl.scala 694:81] + wire _T_8717 = _T_8716 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8727 = _T_4781 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8730 = _T_8248 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8731 = _T_8727 | _T_8730; // @[ifu_mem_ctl.scala 694:81] + wire _T_8732 = _T_8731 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8742 = _T_4782 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8745 = _T_8263 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8746 = _T_8742 | _T_8745; // @[ifu_mem_ctl.scala 694:81] + wire _T_8747 = _T_8746 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8757 = _T_4783 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8760 = _T_8278 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8761 = _T_8757 | _T_8760; // @[ifu_mem_ctl.scala 694:81] + wire _T_8762 = _T_8761 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8772 = _T_4784 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8775 = _T_8293 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8776 = _T_8772 | _T_8775; // @[ifu_mem_ctl.scala 694:81] + wire _T_8777 = _T_8776 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8787 = _T_4785 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8790 = _T_8308 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8791 = _T_8787 | _T_8790; // @[ifu_mem_ctl.scala 694:81] + wire _T_8792 = _T_8791 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8802 = _T_4786 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8805 = _T_8323 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8806 = _T_8802 | _T_8805; // @[ifu_mem_ctl.scala 694:81] + wire _T_8807 = _T_8806 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8817 = _T_4787 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8820 = _T_8338 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8821 = _T_8817 | _T_8820; // @[ifu_mem_ctl.scala 694:81] + wire _T_8822 = _T_8821 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8832 = _T_4788 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8835 = _T_8353 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8836 = _T_8832 | _T_8835; // @[ifu_mem_ctl.scala 694:81] + wire _T_8837 = _T_8836 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8847 = _T_4789 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8850 = _T_8368 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8851 = _T_8847 | _T_8850; // @[ifu_mem_ctl.scala 694:81] + wire _T_8852 = _T_8851 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8862 = _T_4790 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8865 = _T_8383 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8866 = _T_8862 | _T_8865; // @[ifu_mem_ctl.scala 694:81] + wire _T_8867 = _T_8866 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8877 = _T_4791 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8880 = _T_8398 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8881 = _T_8877 | _T_8880; // @[ifu_mem_ctl.scala 694:81] + wire _T_8882 = _T_8881 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8892 = _T_4792 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8895 = _T_8413 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8896 = _T_8892 | _T_8895; // @[ifu_mem_ctl.scala 694:81] + wire _T_8897 = _T_8896 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8907 = _T_4793 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8910 = _T_8428 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8911 = _T_8907 | _T_8910; // @[ifu_mem_ctl.scala 694:81] + wire _T_8912 = _T_8911 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8922 = _T_4794 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8925 = _T_8443 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8926 = _T_8922 | _T_8925; // @[ifu_mem_ctl.scala 694:81] + wire _T_8927 = _T_8926 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8937 = _T_4795 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8940 = _T_8458 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8941 = _T_8937 | _T_8940; // @[ifu_mem_ctl.scala 694:81] + wire _T_8942 = _T_8941 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8952 = _T_4796 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8955 = _T_8473 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8956 = _T_8952 | _T_8955; // @[ifu_mem_ctl.scala 694:81] + wire _T_8957 = _T_8956 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8967 = _T_4797 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8970 = _T_8488 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8971 = _T_8967 | _T_8970; // @[ifu_mem_ctl.scala 694:81] + wire _T_8972 = _T_8971 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_8982 = _T_4798 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] + wire _T_8985 = _T_8503 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] + wire _T_8986 = _T_8982 | _T_8985; // @[ifu_mem_ctl.scala 694:81] + wire _T_8987 = _T_8986 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] + wire _T_9789 = ~fetch_uncacheable_ff; // @[ifu_mem_ctl.scala 748:63] + wire _T_9790 = _T_9789 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 748:85] wire [1:0] _T_9792 = _T_9790 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg _T_9799; // @[ifu_mem_ctl.scala 746:70] - reg _T_9800; // @[ifu_mem_ctl.scala 747:69] - reg _T_9801; // @[ifu_mem_ctl.scala 748:72] - wire _T_9802 = ~ifu_bus_arready_ff; // @[ifu_mem_ctl.scala 749:93] - wire _T_9803 = ifu_bus_arvalid_ff & _T_9802; // @[ifu_mem_ctl.scala 749:91] - reg _T_9805; // @[ifu_mem_ctl.scala 749:71] - reg _T_9806; // @[ifu_mem_ctl.scala 750:71] - wire _T_9809 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[ifu_mem_ctl.scala 757:84] - wire _T_9811 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[ifu_mem_ctl.scala 757:150] - wire _T_9813 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[ifu_mem_ctl.scala 758:63] - wire _T_9815 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[ifu_mem_ctl.scala 758:129] + reg _T_9799; // @[ifu_mem_ctl.scala 753:70] + reg _T_9800; // @[ifu_mem_ctl.scala 754:69] + reg _T_9801; // @[ifu_mem_ctl.scala 755:72] + wire _T_9802 = ~ifu_bus_arready_ff; // @[ifu_mem_ctl.scala 756:93] + wire _T_9803 = ifu_bus_arvalid_ff & _T_9802; // @[ifu_mem_ctl.scala 756:91] + reg _T_9805; // @[ifu_mem_ctl.scala 756:71] + reg _T_9806; // @[ifu_mem_ctl.scala 757:71] + wire _T_9809 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[ifu_mem_ctl.scala 764:84] + wire _T_9811 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[ifu_mem_ctl.scala 764:150] + wire _T_9813 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[ifu_mem_ctl.scala 765:63] + wire _T_9815 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[ifu_mem_ctl.scala 765:129] wire [3:0] _T_9818 = {_T_9809,_T_9811,_T_9813,_T_9815}; // @[Cat.scala 29:58] - reg _T_9826; // @[ifu_mem_ctl.scala 764:79] + reg _T_9826; // @[ifu_mem_ctl.scala 771:79] wire [31:0] _T_9836 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_9837 = _T_9836 | 32'h7fffffff; // @[ifu_mem_ctl.scala 766:65] - wire _T_9839 = _T_9837 == 32'h7fffffff; // @[ifu_mem_ctl.scala 766:96] - wire [31:0] _T_9843 = _T_9836 | 32'h3fffffff; // @[ifu_mem_ctl.scala 767:65] - wire _T_9845 = _T_9843 == 32'hffffffff; // @[ifu_mem_ctl.scala 767:96] - wire _T_9847 = _T_9839 | _T_9845; // @[ifu_mem_ctl.scala 766:162] - wire [31:0] _T_9849 = _T_9836 | 32'h1fffffff; // @[ifu_mem_ctl.scala 768:65] - wire _T_9851 = _T_9849 == 32'hbfffffff; // @[ifu_mem_ctl.scala 768:96] - wire _T_9853 = _T_9847 | _T_9851; // @[ifu_mem_ctl.scala 767:162] - wire [31:0] _T_9855 = _T_9836 | 32'hfffffff; // @[ifu_mem_ctl.scala 769:65] - wire _T_9857 = _T_9855 == 32'h8fffffff; // @[ifu_mem_ctl.scala 769:96] - wire ifc_region_acc_okay = _T_9853 | _T_9857; // @[ifu_mem_ctl.scala 768:162] - wire _T_9884 = ~ifc_region_acc_okay; // @[ifu_mem_ctl.scala 774:65] - wire _T_9885 = _T_3939 & _T_9884; // @[ifu_mem_ctl.scala 774:63] - wire ifc_region_acc_fault_memory_bf = _T_9885 & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 774:86] + wire [31:0] _T_9837 = _T_9836 | 32'h7fffffff; // @[ifu_mem_ctl.scala 774:65] + wire _T_9839 = _T_9837 == 32'h7fffffff; // @[ifu_mem_ctl.scala 774:96] + wire [31:0] _T_9843 = _T_9836 | 32'h3fffffff; // @[ifu_mem_ctl.scala 775:65] + wire _T_9845 = _T_9843 == 32'hffffffff; // @[ifu_mem_ctl.scala 775:96] + wire _T_9847 = _T_9839 | _T_9845; // @[ifu_mem_ctl.scala 774:162] + wire [31:0] _T_9849 = _T_9836 | 32'h1fffffff; // @[ifu_mem_ctl.scala 776:65] + wire _T_9851 = _T_9849 == 32'hbfffffff; // @[ifu_mem_ctl.scala 776:96] + wire _T_9853 = _T_9847 | _T_9851; // @[ifu_mem_ctl.scala 775:162] + wire [31:0] _T_9855 = _T_9836 | 32'hfffffff; // @[ifu_mem_ctl.scala 777:65] + wire _T_9857 = _T_9855 == 32'h8fffffff; // @[ifu_mem_ctl.scala 777:96] + wire ifc_region_acc_okay = _T_9853 | _T_9857; // @[ifu_mem_ctl.scala 776:162] + wire _T_9884 = ~ifc_region_acc_okay; // @[ifu_mem_ctl.scala 782:65] + wire _T_9885 = _T_3939 & _T_9884; // @[ifu_mem_ctl.scala 782:63] + wire ifc_region_acc_fault_memory_bf = _T_9885 & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 782:86] rvclkhdr rvclkhdr ( // @[lib.scala 327:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -5649,58 +5649,58 @@ module ifu_mem_ctl( .io_en(rvclkhdr_93_io_en), .io_scan_mode(rvclkhdr_93_io_scan_mode) ); - assign io_dec_mem_ctrl_ifu_pmu_ic_miss = _T_9799; // @[ifu_mem_ctl.scala 746:35] - assign io_dec_mem_ctrl_ifu_pmu_ic_hit = _T_9800; // @[ifu_mem_ctl.scala 747:34] - assign io_dec_mem_ctrl_ifu_pmu_bus_error = _T_9801; // @[ifu_mem_ctl.scala 748:37] - assign io_dec_mem_ctrl_ifu_pmu_bus_busy = _T_9805; // @[ifu_mem_ctl.scala 749:36] - assign io_dec_mem_ctrl_ifu_pmu_bus_trxn = _T_9806; // @[ifu_mem_ctl.scala 750:36] - assign io_dec_mem_ctrl_ifu_ic_error_start = _T_1200 | ic_rd_parity_final_err; // @[ifu_mem_ctl.scala 271:38] - assign io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = _T_3911 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 605:46] - assign io_dec_mem_ctrl_ifu_ic_debug_rd_data = _T_1212; // @[ifu_mem_ctl.scala 277:40] - assign io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = _T_9826; // @[ifu_mem_ctl.scala 764:46] - assign io_dec_mem_ctrl_ifu_miss_state_idle = miss_state == 3'h0; // @[ifu_mem_ctl.scala 252:39] - assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 490:23] - assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2608; // @[ifu_mem_ctl.scala 491:25] - assign io_ifu_axi_ar_bits_addr = _T_2610 & _T_2612; // @[ifu_mem_ctl.scala 492:27] - assign io_ifu_axi_ar_bits_region = ifu_ic_req_addr_f[28:25]; // @[ifu_mem_ctl.scala 495:29] - assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 497:22] - assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 592:19] - assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2497; // @[ifu_mem_ctl.scala 408:27] - assign io_iccm_correction_state = _T_2526 ? 1'h0 : _GEN_42; // @[ifu_mem_ctl.scala 443:28 ifu_mem_ctl.scala 455:32 ifu_mem_ctl.scala 462:32 ifu_mem_ctl.scala 469:32] - assign io_iccm_wren = _T_2710 | iccm_correct_ecc; // @[ifu_mem_ctl.scala 562:16] - assign io_iccm_rden = _T_2714 | _T_2715; // @[ifu_mem_ctl.scala 563:16] - assign io_iccm_wr_size = _T_2720 & io_dma_mem_ctl_dma_mem_sz; // @[ifu_mem_ctl.scala 565:19] - assign io_iccm_wr_data = _T_3092 ? _T_3093 : _T_3100; // @[ifu_mem_ctl.scala 569:19] - assign io_ic_rw_addr = _T_340 | _T_341; // @[ifu_mem_ctl.scala 261:17] - assign io_ic_tag_valid = ic_tag_valid_unq & _T_9792; // @[ifu_mem_ctl.scala 741:19] - assign io_ic_wr_en = bus_ic_wr_en & _T_3974; // @[ifu_mem_ctl.scala 628:15] - assign io_ic_rd_en = _T_3966 | _T_3971; // @[ifu_mem_ctl.scala 619:15] - assign io_ic_wr_data_0 = ic_wr_16bytes_data[70:0]; // @[ifu_mem_ctl.scala 268:17] - assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[ifu_mem_ctl.scala 268:17] - assign io_ic_debug_wr_data = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu_mem_ctl.scala 269:23] - assign io_ic_debug_addr = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[ifu_mem_ctl.scala 753:20] - assign io_ic_debug_rd_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu_mem_ctl.scala 755:21] - assign io_ic_debug_wr_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu_mem_ctl.scala 756:21] - assign io_ic_debug_tag_array = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[ifu_mem_ctl.scala 754:25] - assign io_ic_debug_way = _T_9818[1:0]; // @[ifu_mem_ctl.scala 757:19] - assign io_ic_premux_data = ic_premux_data_temp[63:0]; // @[ifu_mem_ctl.scala 309:21] - assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[ifu_mem_ctl.scala 310:25] - assign io_ifu_ic_mb_empty = _T_328 | _T_231; // @[ifu_mem_ctl.scala 251:22] - assign io_ic_dma_active = _T_11 | io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 115:20] - assign io_ic_write_stall = write_ic_16_bytes & _T_3988; // @[ifu_mem_ctl.scala 629:21] - assign io_iccm_dma_ecc_error = iccm_dma_ecc_error; // @[ifu_mem_ctl.scala 588:25] - assign io_iccm_dma_rvalid = iccm_dma_rvalid_temp; // @[ifu_mem_ctl.scala 586:22] - assign io_iccm_dma_rdata = iccm_dma_rdata_temp; // @[ifu_mem_ctl.scala 590:21] - assign io_iccm_dma_rtag = iccm_dma_rtag_temp; // @[ifu_mem_ctl.scala 581:20] - assign io_iccm_ready = _T_2706 & _T_2700; // @[ifu_mem_ctl.scala 560:17] - assign io_iccm_rd_ecc_double_err = iccm_dma_ecc_error_in & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 606:29] - assign io_iccm_dma_sb_error = _T_3 & dma_iccm_req_f; // @[ifu_mem_ctl.scala 113:24] - assign io_ic_hit_f = _T_263 | _T_264; // @[ifu_mem_ctl.scala 212:15] - assign io_ic_access_fault_f = _T_2492 & _T_319; // @[ifu_mem_ctl.scala 315:24] - assign io_ic_access_fault_type_f = io_iccm_rd_ecc_double_err ? 2'h1 : _T_1278; // @[ifu_mem_ctl.scala 316:29] - assign io_ifu_async_error_start = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu_mem_ctl.scala 114:28] - assign io_ic_fetch_val_f = {_T_1286,fetch_req_f_qual}; // @[ifu_mem_ctl.scala 319:21] - assign io_ic_data_f = ic_final_data[31:0]; // @[ifu_mem_ctl.scala 312:16] + assign io_dec_mem_ctrl_ifu_pmu_ic_miss = _T_9799; // @[ifu_mem_ctl.scala 753:35] + assign io_dec_mem_ctrl_ifu_pmu_ic_hit = _T_9800; // @[ifu_mem_ctl.scala 754:34] + assign io_dec_mem_ctrl_ifu_pmu_bus_error = _T_9801; // @[ifu_mem_ctl.scala 755:37] + assign io_dec_mem_ctrl_ifu_pmu_bus_busy = _T_9805; // @[ifu_mem_ctl.scala 756:36] + assign io_dec_mem_ctrl_ifu_pmu_bus_trxn = _T_9806; // @[ifu_mem_ctl.scala 757:36] + assign io_dec_mem_ctrl_ifu_ic_error_start = _T_1200 | ic_rd_parity_final_err; // @[ifu_mem_ctl.scala 256:38] + assign io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = _T_3911 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 613:46] + assign io_dec_mem_ctrl_ifu_ic_debug_rd_data = _T_1212; // @[ifu_mem_ctl.scala 263:40] + assign io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = _T_9826; // @[ifu_mem_ctl.scala 771:46] + assign io_dec_mem_ctrl_ifu_miss_state_idle = miss_state == 3'h0; // @[ifu_mem_ctl.scala 235:39] + assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 497:23] + assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2608; // @[ifu_mem_ctl.scala 498:25] + assign io_ifu_axi_ar_bits_addr = _T_2610 & _T_2612; // @[ifu_mem_ctl.scala 499:27] + assign io_ifu_axi_ar_bits_region = ifu_ic_req_addr_f[28:25]; // @[ifu_mem_ctl.scala 502:29] + assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 504:22] + assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 600:19] + assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2497; // @[ifu_mem_ctl.scala 395:27] + assign io_iccm_correction_state = _T_2526 ? 1'h0 : _GEN_42; // @[ifu_mem_ctl.scala 430:28 ifu_mem_ctl.scala 442:32 ifu_mem_ctl.scala 449:32 ifu_mem_ctl.scala 456:32] + assign io_iccm_wren = _T_2710 | iccm_correct_ecc; // @[ifu_mem_ctl.scala 570:16] + assign io_iccm_rden = _T_2714 | _T_2715; // @[ifu_mem_ctl.scala 571:16] + assign io_iccm_wr_size = _T_2720 & io_dma_mem_ctl_dma_mem_sz; // @[ifu_mem_ctl.scala 573:19] + assign io_iccm_wr_data = _T_3092 ? _T_3093 : _T_3100; // @[ifu_mem_ctl.scala 577:19] + assign io_ic_rw_addr = _T_340 | _T_341; // @[ifu_mem_ctl.scala 244:17] + assign io_ic_tag_valid = ic_tag_valid_unq & _T_9792; // @[ifu_mem_ctl.scala 748:19] + assign io_ic_wr_en = bus_ic_wr_en & _T_3974; // @[ifu_mem_ctl.scala 636:15] + assign io_ic_rd_en = _T_3966 | _T_3971; // @[ifu_mem_ctl.scala 627:15] + assign io_ic_wr_data_0 = ic_wr_16bytes_data[70:0]; // @[ifu_mem_ctl.scala 253:17] + assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[ifu_mem_ctl.scala 253:17] + assign io_ic_debug_wr_data = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu_mem_ctl.scala 254:23] + assign io_ic_debug_addr = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[ifu_mem_ctl.scala 760:20] + assign io_ic_debug_rd_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu_mem_ctl.scala 762:21] + assign io_ic_debug_wr_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu_mem_ctl.scala 763:21] + assign io_ic_debug_tag_array = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[ifu_mem_ctl.scala 761:25] + assign io_ic_debug_way = _T_9818[1:0]; // @[ifu_mem_ctl.scala 764:19] + assign io_ic_premux_data = ic_premux_data_temp[63:0]; // @[ifu_mem_ctl.scala 295:21] + assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[ifu_mem_ctl.scala 296:25] + assign io_ifu_ic_mb_empty = _T_328 | _T_231; // @[ifu_mem_ctl.scala 234:22] + assign io_ic_dma_active = _T_11 | io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 97:20] + assign io_ic_write_stall = write_ic_16_bytes & _T_3988; // @[ifu_mem_ctl.scala 637:21] + assign io_iccm_dma_ecc_error = iccm_dma_ecc_error; // @[ifu_mem_ctl.scala 596:25] + assign io_iccm_dma_rvalid = iccm_dma_rvalid_temp; // @[ifu_mem_ctl.scala 594:22] + assign io_iccm_dma_rdata = iccm_dma_rdata_temp; // @[ifu_mem_ctl.scala 598:21] + assign io_iccm_dma_rtag = iccm_dma_rtag_temp; // @[ifu_mem_ctl.scala 589:20] + assign io_iccm_ready = _T_2706 & _T_2700; // @[ifu_mem_ctl.scala 568:17] + assign io_iccm_rd_ecc_double_err = iccm_dma_ecc_error_in & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 614:29] + assign io_iccm_dma_sb_error = _T_3 & dma_iccm_req_f; // @[ifu_mem_ctl.scala 95:24] + assign io_ic_hit_f = _T_263 | _T_264; // @[ifu_mem_ctl.scala 195:15] + assign io_ic_access_fault_f = _T_2492 & _T_319; // @[ifu_mem_ctl.scala 301:24] + assign io_ic_access_fault_type_f = io_iccm_rd_ecc_double_err ? 2'h1 : _T_1278; // @[ifu_mem_ctl.scala 302:29] + assign io_ifu_async_error_start = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu_mem_ctl.scala 96:28] + assign io_ic_fetch_val_f = {_T_1286,fetch_req_f_qual}; // @[ifu_mem_ctl.scala 305:21] + assign io_ic_data_f = ic_final_data[31:0]; // @[ifu_mem_ctl.scala 298:16] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = ic_debug_rd_en_ff; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -43304,30 +43304,30 @@ module ifu_aln_ctl( wire rvclkhdr_11_io_clk; // @[lib.scala 352:23] wire rvclkhdr_11_io_en; // @[lib.scala 352:23] wire rvclkhdr_11_io_scan_mode; // @[lib.scala 352:23] - wire [15:0] decompressed_io_din; // @[ifu_aln_ctl.scala 338:28] - wire [31:0] decompressed_io_dout; // @[ifu_aln_ctl.scala 338:28] - reg error_stall; // @[ifu_aln_ctl.scala 100:51] - wire _T = error_stall | io_ifu_async_error_start; // @[ifu_aln_ctl.scala 98:34] - wire _T_1 = ~io_exu_flush_final; // @[ifu_aln_ctl.scala 98:64] - reg [1:0] wrptr; // @[ifu_aln_ctl.scala 101:48] - reg [1:0] rdptr; // @[ifu_aln_ctl.scala 102:48] - reg [1:0] f2val; // @[ifu_aln_ctl.scala 104:48] - reg [1:0] f1val; // @[ifu_aln_ctl.scala 105:48] - reg [1:0] f0val; // @[ifu_aln_ctl.scala 106:48] - reg q2off; // @[ifu_aln_ctl.scala 108:48] - reg q1off; // @[ifu_aln_ctl.scala 109:48] - reg q0off; // @[ifu_aln_ctl.scala 110:48] - wire _T_785 = ~error_stall; // @[ifu_aln_ctl.scala 380:55] - wire i0_shift = io_dec_aln_aln_dec_dec_i0_decode_d & _T_785; // @[ifu_aln_ctl.scala 380:53] - wire _T_186 = rdptr == 2'h0; // @[ifu_aln_ctl.scala 160:31] + wire [15:0] decompressed_io_din; // @[ifu_aln_ctl.scala 352:28] + wire [31:0] decompressed_io_dout; // @[ifu_aln_ctl.scala 352:28] + reg error_stall; // @[ifu_aln_ctl.scala 102:51] + wire _T = error_stall | io_ifu_async_error_start; // @[ifu_aln_ctl.scala 99:34] + wire _T_1 = ~io_exu_flush_final; // @[ifu_aln_ctl.scala 99:64] + reg [1:0] wrptr; // @[ifu_aln_ctl.scala 104:48] + reg [1:0] rdptr; // @[ifu_aln_ctl.scala 106:48] + reg [1:0] f2val; // @[ifu_aln_ctl.scala 108:48] + reg [1:0] f1val; // @[ifu_aln_ctl.scala 109:48] + reg [1:0] f0val; // @[ifu_aln_ctl.scala 110:48] + reg q2off; // @[ifu_aln_ctl.scala 112:48] + reg q1off; // @[ifu_aln_ctl.scala 113:48] + reg q0off; // @[ifu_aln_ctl.scala 114:48] + wire _T_785 = ~error_stall; // @[ifu_aln_ctl.scala 395:55] + wire i0_shift = io_dec_aln_aln_dec_dec_i0_decode_d & _T_785; // @[ifu_aln_ctl.scala 395:53] + wire _T_186 = rdptr == 2'h0; // @[ifu_aln_ctl.scala 169:31] wire _T_189 = _T_186 & q0off; // @[Mux.scala 27:72] - wire _T_187 = rdptr == 2'h1; // @[ifu_aln_ctl.scala 161:11] + wire _T_187 = rdptr == 2'h1; // @[ifu_aln_ctl.scala 170:11] wire _T_190 = _T_187 & q1off; // @[Mux.scala 27:72] wire _T_192 = _T_189 | _T_190; // @[Mux.scala 27:72] - wire _T_188 = rdptr == 2'h2; // @[ifu_aln_ctl.scala 162:11] + wire _T_188 = rdptr == 2'h2; // @[ifu_aln_ctl.scala 171:11] wire _T_191 = _T_188 & q2off; // @[Mux.scala 27:72] wire q0ptr = _T_192 | _T_191; // @[Mux.scala 27:72] - wire _T_202 = ~q0ptr; // @[ifu_aln_ctl.scala 166:26] + wire _T_202 = ~q0ptr; // @[ifu_aln_ctl.scala 175:26] wire [1:0] q0sel = {q0ptr,_T_202}; // @[Cat.scala 29:58] wire [2:0] qren = {_T_188,_T_187,_T_186}; // @[Cat.scala 29:58] reg [31:0] q1; // @[lib.scala 358:16] @@ -43341,85 +43341,85 @@ module ifu_aln_ctl( wire [63:0] _T_485 = {q0,q2}; // @[Cat.scala 29:58] wire [63:0] _T_488 = qren[2] ? _T_485 : 64'h0; // @[Mux.scala 27:72] wire [63:0] qeff = _T_489 | _T_488; // @[Mux.scala 27:72] - wire [31:0] q0eff = qeff[31:0]; // @[ifu_aln_ctl.scala 282:42] + wire [31:0] q0eff = qeff[31:0]; // @[ifu_aln_ctl.scala 294:42] wire [31:0] _T_496 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72] wire [15:0] _T_497 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72] wire [31:0] _GEN_0 = {{16'd0}, _T_497}; // @[Mux.scala 27:72] wire [31:0] q0final = _T_496 | _GEN_0; // @[Mux.scala 27:72] wire [31:0] _T_520 = f0val[1] ? q0final : 32'h0; // @[Mux.scala 27:72] - wire _T_513 = ~f0val[1]; // @[ifu_aln_ctl.scala 288:58] - wire _T_515 = _T_513 & f0val[0]; // @[ifu_aln_ctl.scala 288:68] + wire _T_513 = ~f0val[1]; // @[ifu_aln_ctl.scala 301:58] + wire _T_515 = _T_513 & f0val[0]; // @[ifu_aln_ctl.scala 301:68] wire _T_197 = _T_186 & q1off; // @[Mux.scala 27:72] wire _T_198 = _T_187 & q2off; // @[Mux.scala 27:72] wire _T_200 = _T_197 | _T_198; // @[Mux.scala 27:72] wire _T_199 = _T_188 & q0off; // @[Mux.scala 27:72] wire q1ptr = _T_200 | _T_199; // @[Mux.scala 27:72] - wire _T_203 = ~q1ptr; // @[ifu_aln_ctl.scala 168:26] + wire _T_203 = ~q1ptr; // @[ifu_aln_ctl.scala 177:26] wire [1:0] q1sel = {q1ptr,_T_203}; // @[Cat.scala 29:58] - wire [31:0] q1eff = qeff[63:32]; // @[ifu_aln_ctl.scala 282:29] + wire [31:0] q1eff = qeff[63:32]; // @[ifu_aln_ctl.scala 294:29] wire [15:0] _T_506 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_507 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72] wire [15:0] q1final = _T_506 | _T_507; // @[Mux.scala 27:72] wire [31:0] _T_519 = {q1final,q0final[15:0]}; // @[Cat.scala 29:58] wire [31:0] _T_521 = _T_515 ? _T_519 : 32'h0; // @[Mux.scala 27:72] wire [31:0] aligndata = _T_520 | _T_521; // @[Mux.scala 27:72] - wire first4B = aligndata[1:0] == 2'h3; // @[ifu_aln_ctl.scala 320:29] - wire first2B = ~first4B; // @[ifu_aln_ctl.scala 322:17] - wire shift_2B = i0_shift & first2B; // @[ifu_aln_ctl.scala 384:24] + wire first4B = aligndata[1:0] == 2'h3; // @[ifu_aln_ctl.scala 334:29] + wire first2B = ~first4B; // @[ifu_aln_ctl.scala 336:17] + wire shift_2B = i0_shift & first2B; // @[ifu_aln_ctl.scala 399:24] wire [1:0] _T_443 = {1'h0,f0val[1]}; // @[Cat.scala 29:58] wire [1:0] _T_448 = shift_2B ? _T_443 : 2'h0; // @[Mux.scala 27:72] - wire _T_444 = ~shift_2B; // @[ifu_aln_ctl.scala 272:18] - wire shift_4B = i0_shift & first4B; // @[ifu_aln_ctl.scala 385:24] - wire _T_445 = ~shift_4B; // @[ifu_aln_ctl.scala 272:30] - wire _T_446 = _T_444 & _T_445; // @[ifu_aln_ctl.scala 272:28] + wire _T_444 = ~shift_2B; // @[ifu_aln_ctl.scala 284:18] + wire shift_4B = i0_shift & first4B; // @[ifu_aln_ctl.scala 400:24] + wire _T_445 = ~shift_4B; // @[ifu_aln_ctl.scala 284:30] + wire _T_446 = _T_444 & _T_445; // @[ifu_aln_ctl.scala 284:28] wire [1:0] _T_449 = _T_446 ? f0val : 2'h0; // @[Mux.scala 27:72] wire [1:0] sf0val = _T_448 | _T_449; // @[Mux.scala 27:72] - wire sf0_valid = sf0val[0]; // @[ifu_aln_ctl.scala 225:22] - wire _T_351 = ~sf0_valid; // @[ifu_aln_ctl.scala 244:26] - wire _T_802 = f0val[0] & _T_513; // @[ifu_aln_ctl.scala 388:28] - wire f1_shift_2B = _T_802 & shift_4B; // @[ifu_aln_ctl.scala 388:40] + wire sf0_valid = sf0val[0]; // @[ifu_aln_ctl.scala 235:22] + wire _T_351 = ~sf0_valid; // @[ifu_aln_ctl.scala 256:26] + wire _T_802 = f0val[0] & _T_513; // @[ifu_aln_ctl.scala 403:28] + wire f1_shift_2B = _T_802 & shift_4B; // @[ifu_aln_ctl.scala 403:40] wire _T_417 = f1_shift_2B & f1val[1]; // @[Mux.scala 27:72] - wire _T_416 = ~f1_shift_2B; // @[ifu_aln_ctl.scala 265:53] + wire _T_416 = ~f1_shift_2B; // @[ifu_aln_ctl.scala 277:53] wire [1:0] _T_418 = _T_416 ? f1val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _GEN_1 = {{1'd0}, _T_417}; // @[Mux.scala 27:72] wire [1:0] sf1val = _GEN_1 | _T_418; // @[Mux.scala 27:72] - wire sf1_valid = sf1val[0]; // @[ifu_aln_ctl.scala 224:22] - wire _T_352 = _T_351 & sf1_valid; // @[ifu_aln_ctl.scala 244:37] - wire f2_valid = f2val[0]; // @[ifu_aln_ctl.scala 223:20] - wire _T_353 = _T_352 & f2_valid; // @[ifu_aln_ctl.scala 244:50] - wire ifvalid = io_ifu_fetch_val[0]; // @[ifu_aln_ctl.scala 233:30] - wire _T_354 = _T_353 & ifvalid; // @[ifu_aln_ctl.scala 244:62] - wire _T_355 = sf0_valid & sf1_valid; // @[ifu_aln_ctl.scala 245:37] - wire _T_356 = ~f2_valid; // @[ifu_aln_ctl.scala 245:52] - wire _T_357 = _T_355 & _T_356; // @[ifu_aln_ctl.scala 245:50] - wire _T_358 = _T_357 & ifvalid; // @[ifu_aln_ctl.scala 245:62] - wire fetch_to_f2 = _T_354 | _T_358; // @[ifu_aln_ctl.scala 244:74] + wire sf1_valid = sf1val[0]; // @[ifu_aln_ctl.scala 234:22] + wire _T_352 = _T_351 & sf1_valid; // @[ifu_aln_ctl.scala 256:37] + wire f2_valid = f2val[0]; // @[ifu_aln_ctl.scala 233:20] + wire _T_353 = _T_352 & f2_valid; // @[ifu_aln_ctl.scala 256:50] + wire ifvalid = io_ifu_fetch_val[0]; // @[ifu_aln_ctl.scala 244:30] + wire _T_354 = _T_353 & ifvalid; // @[ifu_aln_ctl.scala 256:62] + wire _T_355 = sf0_valid & sf1_valid; // @[ifu_aln_ctl.scala 257:37] + wire _T_356 = ~f2_valid; // @[ifu_aln_ctl.scala 257:52] + wire _T_357 = _T_355 & _T_356; // @[ifu_aln_ctl.scala 257:50] + wire _T_358 = _T_357 & ifvalid; // @[ifu_aln_ctl.scala 257:62] + wire fetch_to_f2 = _T_354 | _T_358; // @[ifu_aln_ctl.scala 256:74] reg [30:0] f2pc; // @[lib.scala 358:16] - wire _T_335 = ~sf1_valid; // @[ifu_aln_ctl.scala 240:39] - wire _T_336 = _T_351 & _T_335; // @[ifu_aln_ctl.scala 240:37] - wire _T_337 = _T_336 & f2_valid; // @[ifu_aln_ctl.scala 240:50] - wire _T_338 = _T_337 & ifvalid; // @[ifu_aln_ctl.scala 240:62] - wire _T_342 = _T_352 & _T_356; // @[ifu_aln_ctl.scala 241:50] - wire _T_343 = _T_342 & ifvalid; // @[ifu_aln_ctl.scala 241:62] - wire _T_344 = _T_338 | _T_343; // @[ifu_aln_ctl.scala 240:74] - wire _T_346 = sf0_valid & _T_335; // @[ifu_aln_ctl.scala 242:37] - wire _T_348 = _T_346 & _T_356; // @[ifu_aln_ctl.scala 242:50] - wire _T_349 = _T_348 & ifvalid; // @[ifu_aln_ctl.scala 242:62] - wire fetch_to_f1 = _T_344 | _T_349; // @[ifu_aln_ctl.scala 241:74] - wire _T_25 = fetch_to_f1 | _T_353; // @[ifu_aln_ctl.scala 129:33] + wire _T_335 = ~sf1_valid; // @[ifu_aln_ctl.scala 252:39] + wire _T_336 = _T_351 & _T_335; // @[ifu_aln_ctl.scala 252:37] + wire _T_337 = _T_336 & f2_valid; // @[ifu_aln_ctl.scala 252:50] + wire _T_338 = _T_337 & ifvalid; // @[ifu_aln_ctl.scala 252:62] + wire _T_342 = _T_352 & _T_356; // @[ifu_aln_ctl.scala 253:50] + wire _T_343 = _T_342 & ifvalid; // @[ifu_aln_ctl.scala 253:62] + wire _T_344 = _T_338 | _T_343; // @[ifu_aln_ctl.scala 252:74] + wire _T_346 = sf0_valid & _T_335; // @[ifu_aln_ctl.scala 254:37] + wire _T_348 = _T_346 & _T_356; // @[ifu_aln_ctl.scala 254:50] + wire _T_349 = _T_348 & ifvalid; // @[ifu_aln_ctl.scala 254:62] + wire fetch_to_f1 = _T_344 | _T_349; // @[ifu_aln_ctl.scala 253:74] + wire _T_25 = fetch_to_f1 | _T_353; // @[ifu_aln_ctl.scala 134:33] reg [30:0] f1pc; // @[lib.scala 358:16] - wire _T_332 = _T_336 & _T_356; // @[ifu_aln_ctl.scala 239:50] - wire fetch_to_f0 = _T_332 & ifvalid; // @[ifu_aln_ctl.scala 239:62] - wire _T_27 = fetch_to_f0 | _T_337; // @[ifu_aln_ctl.scala 130:33] - wire _T_28 = _T_27 | _T_352; // @[ifu_aln_ctl.scala 130:47] - wire _T_29 = _T_28 | shift_2B; // @[ifu_aln_ctl.scala 130:61] + wire _T_332 = _T_336 & _T_356; // @[ifu_aln_ctl.scala 251:50] + wire fetch_to_f0 = _T_332 & ifvalid; // @[ifu_aln_ctl.scala 251:62] + wire _T_27 = fetch_to_f0 | _T_337; // @[ifu_aln_ctl.scala 135:33] + wire _T_28 = _T_27 | _T_352; // @[ifu_aln_ctl.scala 135:47] + wire _T_29 = _T_28 | shift_2B; // @[ifu_aln_ctl.scala 135:61] reg [30:0] f0pc; // @[lib.scala 358:16] - wire _T_35 = wrptr == 2'h2; // @[ifu_aln_ctl.scala 133:21] - wire _T_36 = _T_35 & ifvalid; // @[ifu_aln_ctl.scala 133:29] - wire _T_37 = wrptr == 2'h1; // @[ifu_aln_ctl.scala 133:46] - wire _T_38 = _T_37 & ifvalid; // @[ifu_aln_ctl.scala 133:54] - wire _T_39 = wrptr == 2'h0; // @[ifu_aln_ctl.scala 133:71] - wire _T_40 = _T_39 & ifvalid; // @[ifu_aln_ctl.scala 133:79] + wire _T_35 = wrptr == 2'h2; // @[ifu_aln_ctl.scala 139:21] + wire _T_36 = _T_35 & ifvalid; // @[ifu_aln_ctl.scala 139:29] + wire _T_37 = wrptr == 2'h1; // @[ifu_aln_ctl.scala 139:46] + wire _T_38 = _T_37 & ifvalid; // @[ifu_aln_ctl.scala 139:54] + wire _T_39 = wrptr == 2'h0; // @[ifu_aln_ctl.scala 139:71] + wire _T_40 = _T_39 & ifvalid; // @[ifu_aln_ctl.scala 139:79] wire [2:0] qwen = {_T_36,_T_38,_T_40}; // @[Cat.scala 29:58] reg [11:0] brdata2; // @[lib.scala 358:16] reg [11:0] brdata1; // @[lib.scala 358:16] @@ -43427,18 +43427,18 @@ module ifu_aln_ctl( reg [54:0] misc2; // @[lib.scala 358:16] reg [54:0] misc1; // @[lib.scala 358:16] reg [54:0] misc0; // @[lib.scala 358:16] - wire _T_44 = qren[0] & io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 135:34] - wire _T_46 = _T_44 & _T_1; // @[ifu_aln_ctl.scala 135:55] - wire _T_49 = qren[1] & io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 136:14] - wire _T_51 = _T_49 & _T_1; // @[ifu_aln_ctl.scala 136:35] - wire _T_59 = qren[0] & io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 138:14] - wire _T_61 = _T_59 & _T_1; // @[ifu_aln_ctl.scala 138:35] - wire _T_69 = qren[2] & io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 140:14] - wire _T_71 = _T_69 & _T_1; // @[ifu_aln_ctl.scala 140:35] - wire _T_73 = ~io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 141:6] - wire _T_74 = ~io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 141:28] - wire _T_75 = _T_73 & _T_74; // @[ifu_aln_ctl.scala 141:26] - wire _T_77 = _T_75 & _T_1; // @[ifu_aln_ctl.scala 141:48] + wire _T_44 = qren[0] & io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 143:34] + wire _T_46 = _T_44 & _T_1; // @[ifu_aln_ctl.scala 143:55] + wire _T_49 = qren[1] & io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 144:14] + wire _T_51 = _T_49 & _T_1; // @[ifu_aln_ctl.scala 144:35] + wire _T_59 = qren[0] & io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 146:14] + wire _T_61 = _T_59 & _T_1; // @[ifu_aln_ctl.scala 146:35] + wire _T_69 = qren[2] & io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 148:14] + wire _T_71 = _T_69 & _T_1; // @[ifu_aln_ctl.scala 148:35] + wire _T_73 = ~io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 149:6] + wire _T_74 = ~io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 149:28] + wire _T_75 = _T_73 & _T_74; // @[ifu_aln_ctl.scala 149:26] + wire _T_77 = _T_75 & _T_1; // @[ifu_aln_ctl.scala 149:48] wire [1:0] _T_80 = _T_51 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_82 = _T_61 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_85 = _T_77 ? rdptr : 2'h0; // @[Mux.scala 27:72] @@ -43447,43 +43447,43 @@ module ifu_aln_ctl( wire [1:0] _T_88 = _T_86 | _T_82; // @[Mux.scala 27:72] wire [1:0] _GEN_3 = {{1'd0}, _T_71}; // @[Mux.scala 27:72] wire [1:0] _T_90 = _T_88 | _GEN_3; // @[Mux.scala 27:72] - wire _T_95 = qwen[0] & _T_1; // @[ifu_aln_ctl.scala 143:34] - wire _T_99 = qwen[1] & _T_1; // @[ifu_aln_ctl.scala 144:14] - wire _T_105 = ~ifvalid; // @[ifu_aln_ctl.scala 146:6] - wire _T_107 = _T_105 & _T_1; // @[ifu_aln_ctl.scala 146:15] + wire _T_95 = qwen[0] & _T_1; // @[ifu_aln_ctl.scala 152:34] + wire _T_99 = qwen[1] & _T_1; // @[ifu_aln_ctl.scala 153:14] + wire _T_105 = ~ifvalid; // @[ifu_aln_ctl.scala 155:6] + wire _T_107 = _T_105 & _T_1; // @[ifu_aln_ctl.scala 155:15] wire [1:0] _T_110 = _T_99 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_112 = _T_107 ? wrptr : 2'h0; // @[Mux.scala 27:72] wire [1:0] _GEN_4 = {{1'd0}, _T_95}; // @[Mux.scala 27:72] wire [1:0] _T_113 = _GEN_4 | _T_110; // @[Mux.scala 27:72] - wire _T_118 = ~qwen[2]; // @[ifu_aln_ctl.scala 148:26] - wire _T_120 = _T_118 & _T_188; // @[ifu_aln_ctl.scala 148:35] + wire _T_118 = ~qwen[2]; // @[ifu_aln_ctl.scala 157:26] + wire _T_120 = _T_118 & _T_188; // @[ifu_aln_ctl.scala 157:35] wire _T_795 = shift_2B & f0val[0]; // @[Mux.scala 27:72] wire _T_796 = shift_4B & _T_802; // @[Mux.scala 27:72] wire f0_shift_2B = _T_795 | _T_796; // @[Mux.scala 27:72] - wire _T_122 = q2off | f0_shift_2B; // @[ifu_aln_ctl.scala 148:74] - wire _T_126 = _T_118 & _T_187; // @[ifu_aln_ctl.scala 149:15] - wire _T_128 = q2off | f1_shift_2B; // @[ifu_aln_ctl.scala 149:54] - wire _T_132 = _T_118 & _T_186; // @[ifu_aln_ctl.scala 150:15] + wire _T_122 = q2off | f0_shift_2B; // @[ifu_aln_ctl.scala 157:74] + wire _T_126 = _T_118 & _T_187; // @[ifu_aln_ctl.scala 158:15] + wire _T_128 = q2off | f1_shift_2B; // @[ifu_aln_ctl.scala 158:54] + wire _T_132 = _T_118 & _T_186; // @[ifu_aln_ctl.scala 159:15] wire _T_134 = _T_120 & _T_122; // @[Mux.scala 27:72] wire _T_135 = _T_126 & _T_128; // @[Mux.scala 27:72] wire _T_136 = _T_132 & q2off; // @[Mux.scala 27:72] wire _T_137 = _T_134 | _T_135; // @[Mux.scala 27:72] - wire _T_141 = ~qwen[1]; // @[ifu_aln_ctl.scala 152:26] - wire _T_143 = _T_141 & _T_187; // @[ifu_aln_ctl.scala 152:35] - wire _T_145 = q1off | f0_shift_2B; // @[ifu_aln_ctl.scala 152:74] - wire _T_149 = _T_141 & _T_186; // @[ifu_aln_ctl.scala 153:15] - wire _T_151 = q1off | f1_shift_2B; // @[ifu_aln_ctl.scala 153:54] - wire _T_155 = _T_141 & _T_188; // @[ifu_aln_ctl.scala 154:15] + wire _T_141 = ~qwen[1]; // @[ifu_aln_ctl.scala 161:26] + wire _T_143 = _T_141 & _T_187; // @[ifu_aln_ctl.scala 161:35] + wire _T_145 = q1off | f0_shift_2B; // @[ifu_aln_ctl.scala 161:74] + wire _T_149 = _T_141 & _T_186; // @[ifu_aln_ctl.scala 162:15] + wire _T_151 = q1off | f1_shift_2B; // @[ifu_aln_ctl.scala 162:54] + wire _T_155 = _T_141 & _T_188; // @[ifu_aln_ctl.scala 163:15] wire _T_157 = _T_143 & _T_145; // @[Mux.scala 27:72] wire _T_158 = _T_149 & _T_151; // @[Mux.scala 27:72] wire _T_159 = _T_155 & q1off; // @[Mux.scala 27:72] wire _T_160 = _T_157 | _T_158; // @[Mux.scala 27:72] - wire _T_164 = ~qwen[0]; // @[ifu_aln_ctl.scala 156:26] - wire _T_166 = _T_164 & _T_186; // @[ifu_aln_ctl.scala 156:35] - wire _T_168 = q0off | f0_shift_2B; // @[ifu_aln_ctl.scala 156:76] - wire _T_172 = _T_164 & _T_188; // @[ifu_aln_ctl.scala 157:35] - wire _T_174 = q0off | f1_shift_2B; // @[ifu_aln_ctl.scala 157:76] - wire _T_178 = _T_164 & _T_187; // @[ifu_aln_ctl.scala 158:35] + wire _T_164 = ~qwen[0]; // @[ifu_aln_ctl.scala 165:26] + wire _T_166 = _T_164 & _T_186; // @[ifu_aln_ctl.scala 165:35] + wire _T_168 = q0off | f0_shift_2B; // @[ifu_aln_ctl.scala 165:76] + wire _T_172 = _T_164 & _T_188; // @[ifu_aln_ctl.scala 166:35] + wire _T_174 = q0off | f1_shift_2B; // @[ifu_aln_ctl.scala 166:76] + wire _T_178 = _T_164 & _T_187; // @[ifu_aln_ctl.scala 167:35] wire _T_180 = _T_166 & _T_168; // @[Mux.scala 27:72] wire _T_181 = _T_172 & _T_174; // @[Mux.scala 27:72] wire _T_182 = _T_178 & q0off; // @[Mux.scala 27:72] @@ -43498,20 +43498,20 @@ module ifu_aln_ctl( wire [109:0] _T_220 = qren[2] ? _T_217 : 110'h0; // @[Mux.scala 27:72] wire [109:0] _T_221 = _T_218 | _T_219; // @[Mux.scala 27:72] wire [109:0] misceff = _T_221 | _T_220; // @[Mux.scala 27:72] - wire [54:0] misc1eff = misceff[109:55]; // @[ifu_aln_ctl.scala 177:25] - wire [54:0] misc0eff = misceff[54:0]; // @[ifu_aln_ctl.scala 178:25] - wire f1dbecc = misc1eff[54]; // @[ifu_aln_ctl.scala 181:25] - wire f1icaf = misc1eff[53]; // @[ifu_aln_ctl.scala 182:21] - wire [1:0] f1ictype = misc1eff[52:51]; // @[ifu_aln_ctl.scala 183:26] - wire [30:0] f1prett = misc1eff[50:20]; // @[ifu_aln_ctl.scala 184:25] - wire [11:0] f1poffset = misc1eff[19:8]; // @[ifu_aln_ctl.scala 185:27] - wire [7:0] f1fghr = misc1eff[7:0]; // @[ifu_aln_ctl.scala 186:24] - wire f0dbecc = misc0eff[54]; // @[ifu_aln_ctl.scala 188:25] - wire f0icaf = misc0eff[53]; // @[ifu_aln_ctl.scala 189:21] - wire [1:0] f0ictype = misc0eff[52:51]; // @[ifu_aln_ctl.scala 190:26] - wire [30:0] f0prett = misc0eff[50:20]; // @[ifu_aln_ctl.scala 191:25] - wire [11:0] f0poffset = misc0eff[19:8]; // @[ifu_aln_ctl.scala 192:27] - wire [7:0] f0fghr = misc0eff[7:0]; // @[ifu_aln_ctl.scala 193:24] + wire [54:0] misc1eff = misceff[109:55]; // @[ifu_aln_ctl.scala 186:25] + wire [54:0] misc0eff = misceff[54:0]; // @[ifu_aln_ctl.scala 187:25] + wire f1dbecc = misc1eff[54]; // @[ifu_aln_ctl.scala 190:25] + wire f1icaf = misc1eff[53]; // @[ifu_aln_ctl.scala 191:21] + wire [1:0] f1ictype = misc1eff[52:51]; // @[ifu_aln_ctl.scala 192:26] + wire [30:0] f1prett = misc1eff[50:20]; // @[ifu_aln_ctl.scala 193:25] + wire [11:0] f1poffset = misc1eff[19:8]; // @[ifu_aln_ctl.scala 194:27] + wire [7:0] f1fghr = misc1eff[7:0]; // @[ifu_aln_ctl.scala 195:24] + wire f0dbecc = misc0eff[54]; // @[ifu_aln_ctl.scala 197:25] + wire f0icaf = misc0eff[53]; // @[ifu_aln_ctl.scala 198:21] + wire [1:0] f0ictype = misc0eff[52:51]; // @[ifu_aln_ctl.scala 199:26] + wire [30:0] f0prett = misc0eff[50:20]; // @[ifu_aln_ctl.scala 200:25] + wire [11:0] f0poffset = misc0eff[19:8]; // @[ifu_aln_ctl.scala 201:27] + wire [7:0] f0fghr = misc0eff[7:0]; // @[ifu_aln_ctl.scala 202:24] wire [5:0] _T_241 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58] wire [5:0] _T_246 = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1]}; // @[Cat.scala 29:58] wire [23:0] _T_250 = {brdata1,brdata0}; // @[Cat.scala 29:58] @@ -43522,8 +43522,8 @@ module ifu_aln_ctl( wire [23:0] _T_259 = qren[2] ? _T_256 : 24'h0; // @[Mux.scala 27:72] wire [23:0] _T_260 = _T_257 | _T_258; // @[Mux.scala 27:72] wire [23:0] brdataeff = _T_260 | _T_259; // @[Mux.scala 27:72] - wire [11:0] brdata0eff = brdataeff[11:0]; // @[ifu_aln_ctl.scala 203:43] - wire [11:0] brdata1eff = brdataeff[23:12]; // @[ifu_aln_ctl.scala 203:61] + wire [11:0] brdata0eff = brdataeff[11:0]; // @[ifu_aln_ctl.scala 213:43] + wire [11:0] brdata1eff = brdataeff[23:12]; // @[ifu_aln_ctl.scala 213:61] wire [11:0] _T_267 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72] wire [5:0] _T_268 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72] wire [11:0] _GEN_5 = {{6'd0}, _T_268}; // @[Mux.scala 27:72] @@ -43544,55 +43544,55 @@ module ifu_aln_ctl( wire [1:0] f1pc4 = {brdata1final[9],brdata1final[3]}; // @[Cat.scala 29:58] wire [1:0] f1hist0 = {brdata1final[10],brdata1final[4]}; // @[Cat.scala 29:58] wire [1:0] f1hist1 = {brdata1final[11],brdata1final[5]}; // @[Cat.scala 29:58] - wire consume_fb0 = _T_351 & f0val[0]; // @[ifu_aln_ctl.scala 227:32] - wire consume_fb1 = _T_335 & f1val[0]; // @[ifu_aln_ctl.scala 228:32] - wire _T_311 = ~consume_fb1; // @[ifu_aln_ctl.scala 230:39] - wire _T_312 = consume_fb0 & _T_311; // @[ifu_aln_ctl.scala 230:37] - wire _T_315 = consume_fb0 & consume_fb1; // @[ifu_aln_ctl.scala 231:37] - wire [30:0] f0pc_plus1 = f0pc + 31'h1; // @[ifu_aln_ctl.scala 247:25] - wire [30:0] f1pc_plus1 = f1pc + 31'h1; // @[ifu_aln_ctl.scala 249:25] + wire consume_fb0 = _T_351 & f0val[0]; // @[ifu_aln_ctl.scala 237:32] + wire consume_fb1 = _T_335 & f1val[0]; // @[ifu_aln_ctl.scala 238:32] + wire _T_311 = ~consume_fb1; // @[ifu_aln_ctl.scala 241:39] + wire _T_312 = consume_fb0 & _T_311; // @[ifu_aln_ctl.scala 241:37] + wire _T_315 = consume_fb0 & consume_fb1; // @[ifu_aln_ctl.scala 242:37] + wire [30:0] f0pc_plus1 = f0pc + 31'h1; // @[ifu_aln_ctl.scala 259:25] + wire [30:0] f1pc_plus1 = f1pc + 31'h1; // @[ifu_aln_ctl.scala 261:25] wire [30:0] _T_363 = f1_shift_2B ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12] - wire [30:0] _T_364 = _T_363 & f1pc_plus1; // @[ifu_aln_ctl.scala 251:38] + wire [30:0] _T_364 = _T_363 & f1pc_plus1; // @[ifu_aln_ctl.scala 263:38] wire [30:0] _T_367 = _T_416 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12] - wire [30:0] _T_368 = _T_367 & f1pc; // @[ifu_aln_ctl.scala 251:78] - wire [30:0] sf1pc = _T_364 | _T_368; // @[ifu_aln_ctl.scala 251:52] - wire _T_371 = ~fetch_to_f1; // @[ifu_aln_ctl.scala 255:6] - wire _T_372 = ~_T_353; // @[ifu_aln_ctl.scala 255:21] - wire _T_373 = _T_371 & _T_372; // @[ifu_aln_ctl.scala 255:19] + wire [30:0] _T_368 = _T_367 & f1pc; // @[ifu_aln_ctl.scala 263:78] + wire [30:0] sf1pc = _T_364 | _T_368; // @[ifu_aln_ctl.scala 263:52] + wire _T_371 = ~fetch_to_f1; // @[ifu_aln_ctl.scala 267:6] + wire _T_372 = ~_T_353; // @[ifu_aln_ctl.scala 267:21] + wire _T_373 = _T_371 & _T_372; // @[ifu_aln_ctl.scala 267:19] wire [30:0] _T_375 = fetch_to_f1 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_376 = _T_353 ? f2pc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_377 = _T_373 ? sf1pc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_378 = _T_375 | _T_376; // @[Mux.scala 27:72] - wire _T_384 = ~fetch_to_f0; // @[ifu_aln_ctl.scala 260:24] - wire _T_385 = ~_T_337; // @[ifu_aln_ctl.scala 260:39] - wire _T_386 = _T_384 & _T_385; // @[ifu_aln_ctl.scala 260:37] - wire _T_387 = ~_T_352; // @[ifu_aln_ctl.scala 260:54] - wire _T_388 = _T_386 & _T_387; // @[ifu_aln_ctl.scala 260:52] + wire _T_384 = ~fetch_to_f0; // @[ifu_aln_ctl.scala 272:24] + wire _T_385 = ~_T_337; // @[ifu_aln_ctl.scala 272:39] + wire _T_386 = _T_384 & _T_385; // @[ifu_aln_ctl.scala 272:37] + wire _T_387 = ~_T_352; // @[ifu_aln_ctl.scala 272:54] + wire _T_388 = _T_386 & _T_387; // @[ifu_aln_ctl.scala 272:52] wire [30:0] _T_390 = fetch_to_f0 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_391 = _T_337 ? f2pc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_392 = _T_352 ? sf1pc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_393 = _T_388 ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_394 = _T_390 | _T_391; // @[Mux.scala 27:72] wire [30:0] _T_395 = _T_394 | _T_392; // @[Mux.scala 27:72] - wire _T_399 = fetch_to_f2 & _T_1; // @[ifu_aln_ctl.scala 262:38] - wire _T_401 = ~fetch_to_f2; // @[ifu_aln_ctl.scala 263:25] - wire _T_403 = _T_401 & _T_372; // @[ifu_aln_ctl.scala 263:38] - wire _T_405 = _T_403 & _T_385; // @[ifu_aln_ctl.scala 263:53] - wire _T_407 = _T_405 & _T_1; // @[ifu_aln_ctl.scala 263:68] + wire _T_399 = fetch_to_f2 & _T_1; // @[ifu_aln_ctl.scala 274:38] + wire _T_401 = ~fetch_to_f2; // @[ifu_aln_ctl.scala 275:25] + wire _T_403 = _T_401 & _T_372; // @[ifu_aln_ctl.scala 275:38] + wire _T_405 = _T_403 & _T_385; // @[ifu_aln_ctl.scala 275:53] + wire _T_407 = _T_405 & _T_1; // @[ifu_aln_ctl.scala 275:68] wire [1:0] _T_409 = _T_399 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_410 = _T_407 ? f2val : 2'h0; // @[Mux.scala 27:72] - wire _T_422 = fetch_to_f1 & _T_1; // @[ifu_aln_ctl.scala 267:39] - wire _T_425 = _T_353 & _T_1; // @[ifu_aln_ctl.scala 268:54] - wire _T_431 = _T_373 & _T_387; // @[ifu_aln_ctl.scala 269:54] - wire _T_433 = _T_431 & _T_1; // @[ifu_aln_ctl.scala 269:69] + wire _T_422 = fetch_to_f1 & _T_1; // @[ifu_aln_ctl.scala 279:39] + wire _T_425 = _T_353 & _T_1; // @[ifu_aln_ctl.scala 280:54] + wire _T_431 = _T_373 & _T_387; // @[ifu_aln_ctl.scala 281:54] + wire _T_433 = _T_431 & _T_1; // @[ifu_aln_ctl.scala 281:69] wire [1:0] _T_435 = _T_422 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_436 = _T_425 ? f2val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_437 = _T_433 ? sf1val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_438 = _T_435 | _T_436; // @[Mux.scala 27:72] - wire _T_453 = fetch_to_f0 & _T_1; // @[ifu_aln_ctl.scala 274:38] - wire _T_456 = _T_337 & _T_1; // @[ifu_aln_ctl.scala 275:54] - wire _T_459 = _T_352 & _T_1; // @[ifu_aln_ctl.scala 276:69] - wire _T_467 = _T_388 & _T_1; // @[ifu_aln_ctl.scala 277:69] + wire _T_453 = fetch_to_f0 & _T_1; // @[ifu_aln_ctl.scala 286:38] + wire _T_456 = _T_337 & _T_1; // @[ifu_aln_ctl.scala 287:54] + wire _T_459 = _T_352 & _T_1; // @[ifu_aln_ctl.scala 288:69] + wire _T_467 = _T_388 & _T_1; // @[ifu_aln_ctl.scala 289:69] wire [1:0] _T_469 = _T_453 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_470 = _T_456 ? f2val : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_471 = _T_459 ? sf1val : 2'h0; // @[Mux.scala 27:72] @@ -43642,18 +43642,18 @@ module ifu_aln_ctl( wire [30:0] secondpc = _T_647 | _T_648; // @[Mux.scala 27:72] wire _T_657 = first4B & alignval[1]; // @[Mux.scala 27:72] wire _T_658 = first2B & alignval[0]; // @[Mux.scala 27:72] - wire _T_662 = |alignicaf; // @[ifu_aln_ctl.scala 326:74] + wire _T_662 = |alignicaf; // @[ifu_aln_ctl.scala 340:74] wire _T_665 = first4B & _T_662; // @[Mux.scala 27:72] wire _T_666 = first2B & alignicaf[0]; // @[Mux.scala 27:72] - wire _T_671 = first4B & _T_513; // @[ifu_aln_ctl.scala 328:54] - wire _T_673 = _T_671 & f0val[0]; // @[ifu_aln_ctl.scala 328:66] - wire _T_675 = ~alignicaf[0]; // @[ifu_aln_ctl.scala 328:79] - wire _T_676 = _T_673 & _T_675; // @[ifu_aln_ctl.scala 328:77] - wire _T_678 = ~aligndbecc[0]; // @[ifu_aln_ctl.scala 328:95] - wire _T_679 = _T_676 & _T_678; // @[ifu_aln_ctl.scala 328:93] - wire icaf_eff = alignicaf[1] | aligndbecc[1]; // @[ifu_aln_ctl.scala 330:31] - wire _T_684 = first4B & icaf_eff; // @[ifu_aln_ctl.scala 332:47] - wire _T_687 = |aligndbecc; // @[ifu_aln_ctl.scala 334:74] + wire _T_671 = first4B & _T_513; // @[ifu_aln_ctl.scala 342:54] + wire _T_673 = _T_671 & f0val[0]; // @[ifu_aln_ctl.scala 342:66] + wire _T_675 = ~alignicaf[0]; // @[ifu_aln_ctl.scala 342:79] + wire _T_676 = _T_673 & _T_675; // @[ifu_aln_ctl.scala 342:77] + wire _T_678 = ~aligndbecc[0]; // @[ifu_aln_ctl.scala 342:95] + wire _T_679 = _T_676 & _T_678; // @[ifu_aln_ctl.scala 342:93] + wire icaf_eff = alignicaf[1] | aligndbecc[1]; // @[ifu_aln_ctl.scala 344:31] + wire _T_684 = first4B & icaf_eff; // @[ifu_aln_ctl.scala 346:47] + wire _T_687 = |aligndbecc; // @[ifu_aln_ctl.scala 348:74] wire _T_690 = first4B & _T_687; // @[Mux.scala 27:72] wire _T_691 = first2B & aligndbecc[0]; // @[Mux.scala 27:72] wire [31:0] _T_696 = first4B ? aligndata : 32'h0; // @[Mux.scala 27:72] @@ -43666,28 +43666,28 @@ module ifu_aln_ctl( wire [4:0] firstbrtag_hash = _T_712 ^ f0pc[23:19]; // @[lib.scala 26:111] wire [4:0] _T_717 = secondpc[13:9] ^ secondpc[18:14]; // @[lib.scala 26:111] wire [4:0] secondbrtag_hash = _T_717 ^ secondpc[23:19]; // @[lib.scala 26:111] - wire _T_719 = first2B & alignbrend[0]; // @[ifu_aln_ctl.scala 350:45] - wire _T_721 = first4B & alignbrend[1]; // @[ifu_aln_ctl.scala 350:73] - wire _T_722 = _T_719 | _T_721; // @[ifu_aln_ctl.scala 350:62] - wire _T_726 = _T_657 & alignbrend[0]; // @[ifu_aln_ctl.scala 350:115] - wire _T_729 = first2B & alignret[0]; // @[ifu_aln_ctl.scala 352:49] - wire _T_731 = first4B & alignret[1]; // @[ifu_aln_ctl.scala 352:75] - wire _T_734 = first2B & alignpc4[0]; // @[ifu_aln_ctl.scala 354:29] - wire _T_736 = first4B & alignpc4[1]; // @[ifu_aln_ctl.scala 354:55] - wire i0_brp_pc4 = _T_734 | _T_736; // @[ifu_aln_ctl.scala 354:44] - wire _T_738 = first2B | alignbrend[0]; // @[ifu_aln_ctl.scala 356:53] - wire _T_744 = first2B & alignhist1[0]; // @[ifu_aln_ctl.scala 358:54] - wire _T_746 = first4B & alignhist1[1]; // @[ifu_aln_ctl.scala 358:82] - wire _T_747 = _T_744 | _T_746; // @[ifu_aln_ctl.scala 358:71] - wire _T_749 = first2B & alignhist0[0]; // @[ifu_aln_ctl.scala 359:14] - wire _T_751 = first4B & alignhist0[1]; // @[ifu_aln_ctl.scala 359:42] - wire _T_752 = _T_749 | _T_751; // @[ifu_aln_ctl.scala 359:31] - wire i0_ends_f1 = first4B & _T_515; // @[ifu_aln_ctl.scala 361:28] - wire _T_768 = io_dec_aln_aln_ib_i0_brp_valid & i0_brp_pc4; // @[ifu_aln_ctl.scala 370:77] - wire _T_769 = _T_768 & first2B; // @[ifu_aln_ctl.scala 370:91] - wire _T_770 = ~i0_brp_pc4; // @[ifu_aln_ctl.scala 370:139] - wire _T_771 = io_dec_aln_aln_ib_i0_brp_valid & _T_770; // @[ifu_aln_ctl.scala 370:137] - wire _T_772 = _T_771 & first4B; // @[ifu_aln_ctl.scala 370:151] + wire _T_719 = first2B & alignbrend[0]; // @[ifu_aln_ctl.scala 365:45] + wire _T_721 = first4B & alignbrend[1]; // @[ifu_aln_ctl.scala 365:73] + wire _T_722 = _T_719 | _T_721; // @[ifu_aln_ctl.scala 365:62] + wire _T_726 = _T_657 & alignbrend[0]; // @[ifu_aln_ctl.scala 365:115] + wire _T_729 = first2B & alignret[0]; // @[ifu_aln_ctl.scala 367:49] + wire _T_731 = first4B & alignret[1]; // @[ifu_aln_ctl.scala 367:75] + wire _T_734 = first2B & alignpc4[0]; // @[ifu_aln_ctl.scala 369:29] + wire _T_736 = first4B & alignpc4[1]; // @[ifu_aln_ctl.scala 369:55] + wire i0_brp_pc4 = _T_734 | _T_736; // @[ifu_aln_ctl.scala 369:44] + wire _T_738 = first2B | alignbrend[0]; // @[ifu_aln_ctl.scala 371:53] + wire _T_744 = first2B & alignhist1[0]; // @[ifu_aln_ctl.scala 373:54] + wire _T_746 = first4B & alignhist1[1]; // @[ifu_aln_ctl.scala 373:82] + wire _T_747 = _T_744 | _T_746; // @[ifu_aln_ctl.scala 373:71] + wire _T_749 = first2B & alignhist0[0]; // @[ifu_aln_ctl.scala 374:14] + wire _T_751 = first4B & alignhist0[1]; // @[ifu_aln_ctl.scala 374:42] + wire _T_752 = _T_749 | _T_751; // @[ifu_aln_ctl.scala 374:31] + wire i0_ends_f1 = first4B & _T_515; // @[ifu_aln_ctl.scala 376:28] + wire _T_768 = io_dec_aln_aln_ib_i0_brp_valid & i0_brp_pc4; // @[ifu_aln_ctl.scala 385:77] + wire _T_769 = _T_768 & first2B; // @[ifu_aln_ctl.scala 385:91] + wire _T_770 = ~i0_brp_pc4; // @[ifu_aln_ctl.scala 385:139] + wire _T_771 = io_dec_aln_aln_ib_i0_brp_valid & _T_770; // @[ifu_aln_ctl.scala 385:137] + wire _T_772 = _T_771 & first4B; // @[ifu_aln_ctl.scala 385:151] rvclkhdr rvclkhdr ( // @[lib.scala 352:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -43760,33 +43760,33 @@ module ifu_aln_ctl( .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - ifu_compress_ctl decompressed ( // @[ifu_aln_ctl.scala 338:28] + ifu_compress_ctl decompressed ( // @[ifu_aln_ctl.scala 352:28] .io_din(decompressed_io_din), .io_dout(decompressed_io_dout) ); - assign io_dec_aln_aln_dec_ifu_i0_cinst = aligndata[15:0]; // @[ifu_aln_ctl.scala 318:35] - assign io_dec_aln_aln_ib_ifu_i0_icaf = _T_665 | _T_666; // @[ifu_aln_ctl.scala 326:33] - assign io_dec_aln_aln_ib_ifu_i0_icaf_type = _T_679 ? f1ictype : f0ictype; // @[ifu_aln_ctl.scala 328:38] - assign io_dec_aln_aln_ib_ifu_i0_icaf_f1 = _T_684 & _T_515; // @[ifu_aln_ctl.scala 332:36] - assign io_dec_aln_aln_ib_ifu_i0_dbecc = _T_690 | _T_691; // @[ifu_aln_ctl.scala 334:34] - assign io_dec_aln_aln_ib_ifu_i0_bp_index = _T_738 ? firstpc_hash : secondpc_hash; // @[ifu_aln_ctl.scala 372:37] - assign io_dec_aln_aln_ib_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : f0fghr; // @[ifu_aln_ctl.scala 374:36] - assign io_dec_aln_aln_ib_ifu_i0_bp_btag = _T_738 ? firstbrtag_hash : secondbrtag_hash; // @[ifu_aln_ctl.scala 376:36] - assign io_dec_aln_aln_ib_ifu_i0_valid = _T_657 | _T_658; // @[ifu_aln_ctl.scala 324:34] - assign io_dec_aln_aln_ib_ifu_i0_instr = _T_696 | _T_697; // @[ifu_aln_ctl.scala 340:34] - assign io_dec_aln_aln_ib_ifu_i0_pc = f0pc; // @[ifu_aln_ctl.scala 312:31] - assign io_dec_aln_aln_ib_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[ifu_aln_ctl.scala 316:32] - assign io_dec_aln_aln_ib_i0_brp_valid = _T_722 | _T_726; // @[ifu_aln_ctl.scala 350:34] - assign io_dec_aln_aln_ib_i0_brp_bits_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[ifu_aln_ctl.scala 362:41] - assign io_dec_aln_aln_ib_i0_brp_bits_hist = {_T_747,_T_752}; // @[ifu_aln_ctl.scala 358:38] - assign io_dec_aln_aln_ib_i0_brp_bits_br_error = _T_769 | _T_772; // @[ifu_aln_ctl.scala 370:42] - assign io_dec_aln_aln_ib_i0_brp_bits_br_start_error = _T_657 & alignbrend[0]; // @[ifu_aln_ctl.scala 366:49] - assign io_dec_aln_aln_ib_i0_brp_bits_prett = i0_ends_f1 ? f1prett : f0prett; // @[ifu_aln_ctl.scala 364:39] - assign io_dec_aln_aln_ib_i0_brp_bits_way = _T_738 ? alignway[0] : alignway[1]; // @[ifu_aln_ctl.scala 356:37] - assign io_dec_aln_aln_ib_i0_brp_bits_ret = _T_729 | _T_731; // @[ifu_aln_ctl.scala 352:37] - assign io_dec_aln_ifu_pmu_instr_aligned = io_dec_aln_aln_dec_dec_i0_decode_d & _T_785; // @[ifu_aln_ctl.scala 382:36] - assign io_ifu_fb_consume1 = _T_312 & _T_1; // @[ifu_aln_ctl.scala 230:22] - assign io_ifu_fb_consume2 = _T_315 & _T_1; // @[ifu_aln_ctl.scala 231:22] + assign io_dec_aln_aln_dec_ifu_i0_cinst = aligndata[15:0]; // @[ifu_aln_ctl.scala 331:35] + assign io_dec_aln_aln_ib_ifu_i0_icaf = _T_665 | _T_666; // @[ifu_aln_ctl.scala 340:33] + assign io_dec_aln_aln_ib_ifu_i0_icaf_type = _T_679 ? f1ictype : f0ictype; // @[ifu_aln_ctl.scala 342:38] + assign io_dec_aln_aln_ib_ifu_i0_icaf_f1 = _T_684 & _T_515; // @[ifu_aln_ctl.scala 346:36] + assign io_dec_aln_aln_ib_ifu_i0_dbecc = _T_690 | _T_691; // @[ifu_aln_ctl.scala 348:34] + assign io_dec_aln_aln_ib_ifu_i0_bp_index = _T_738 ? firstpc_hash : secondpc_hash; // @[ifu_aln_ctl.scala 387:37] + assign io_dec_aln_aln_ib_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : f0fghr; // @[ifu_aln_ctl.scala 389:36] + assign io_dec_aln_aln_ib_ifu_i0_bp_btag = _T_738 ? firstbrtag_hash : secondbrtag_hash; // @[ifu_aln_ctl.scala 391:36] + assign io_dec_aln_aln_ib_ifu_i0_valid = _T_657 | _T_658; // @[ifu_aln_ctl.scala 338:34] + assign io_dec_aln_aln_ib_ifu_i0_instr = _T_696 | _T_697; // @[ifu_aln_ctl.scala 354:34] + assign io_dec_aln_aln_ib_ifu_i0_pc = f0pc; // @[ifu_aln_ctl.scala 325:31] + assign io_dec_aln_aln_ib_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[ifu_aln_ctl.scala 329:32] + assign io_dec_aln_aln_ib_i0_brp_valid = _T_722 | _T_726; // @[ifu_aln_ctl.scala 365:34] + assign io_dec_aln_aln_ib_i0_brp_bits_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[ifu_aln_ctl.scala 377:41] + assign io_dec_aln_aln_ib_i0_brp_bits_hist = {_T_747,_T_752}; // @[ifu_aln_ctl.scala 373:38] + assign io_dec_aln_aln_ib_i0_brp_bits_br_error = _T_769 | _T_772; // @[ifu_aln_ctl.scala 385:42] + assign io_dec_aln_aln_ib_i0_brp_bits_br_start_error = _T_657 & alignbrend[0]; // @[ifu_aln_ctl.scala 381:49] + assign io_dec_aln_aln_ib_i0_brp_bits_prett = i0_ends_f1 ? f1prett : f0prett; // @[ifu_aln_ctl.scala 379:39] + assign io_dec_aln_aln_ib_i0_brp_bits_way = _T_738 ? alignway[0] : alignway[1]; // @[ifu_aln_ctl.scala 371:37] + assign io_dec_aln_aln_ib_i0_brp_bits_ret = _T_729 | _T_731; // @[ifu_aln_ctl.scala 367:37] + assign io_dec_aln_ifu_pmu_instr_aligned = io_dec_aln_aln_dec_dec_i0_decode_d & _T_785; // @[ifu_aln_ctl.scala 397:36] + assign io_ifu_fb_consume1 = _T_312 & _T_1; // @[ifu_aln_ctl.scala 241:22] + assign io_ifu_fb_consume2 = _T_315 & _T_1; // @[ifu_aln_ctl.scala 242:22] assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_io_en = _T_354 | _T_358; // @[lib.scala 355:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] @@ -43823,7 +43823,7 @@ module ifu_aln_ctl( assign rvclkhdr_11_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_11_io_en = qwen[0]; // @[lib.scala 355:17] assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] - assign decompressed_io_din = aligndata[15:0]; // @[ifu_aln_ctl.scala 378:23] + assign decompressed_io_din = aligndata[15:0]; // @[ifu_aln_ctl.scala 393:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -44179,105 +44179,105 @@ module ifu_ifc_ctl( wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72] - wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[ifu_ifc_ctl.scala 77:48] - wire _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[ifu_ifc_ctl.scala 78:63] - wire _T_30 = ~_T_29; // @[ifu_ifc_ctl.scala 78:24] - wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[ifu_ifc_ctl.scala 78:109] + wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[ifu_ifc_ctl.scala 78:48] + wire _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[ifu_ifc_ctl.scala 79:63] + wire _T_30 = ~_T_29; // @[ifu_ifc_ctl.scala 79:24] + wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[ifu_ifc_ctl.scala 79:109] wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58] wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] - reg [1:0] state; // @[ifu_ifc_ctl.scala 102:45] - wire idle = state == 2'h0; // @[ifu_ifc_ctl.scala 119:17] - wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[ifu_ifc_ctl.scala 84:91] - wire _T_36 = ~_T_35; // @[ifu_ifc_ctl.scala 84:70] + reg [1:0] state; // @[ifu_ifc_ctl.scala 104:45] + wire idle = state == 2'h0; // @[ifu_ifc_ctl.scala 123:17] + wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[ifu_ifc_ctl.scala 86:91] + wire _T_36 = ~_T_35; // @[ifu_ifc_ctl.scala 86:70] wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72] - wire _T_81 = ~io_ifu_fb_consume2; // @[ifu_ifc_ctl.scala 106:38] - wire _T_82 = io_ifu_fb_consume1 & _T_81; // @[ifu_ifc_ctl.scala 106:36] - wire _T_48 = io_ifc_fetch_req_f & _T_4; // @[ifu_ifc_ctl.scala 89:32] - wire miss_f = _T_48 & _T_2; // @[ifu_ifc_ctl.scala 89:47] - wire _T_84 = _T_3 | miss_f; // @[ifu_ifc_ctl.scala 106:81] - wire _T_85 = _T_82 & _T_84; // @[ifu_ifc_ctl.scala 106:58] - wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 107:25] - wire fb_right = _T_85 | _T_86; // @[ifu_ifc_ctl.scala 106:92] - wire _T_98 = _T_2 & fb_right; // @[ifu_ifc_ctl.scala 113:16] - reg [3:0] fb_write_f; // @[ifu_ifc_ctl.scala 124:50] + wire _T_81 = ~io_ifu_fb_consume2; // @[ifu_ifc_ctl.scala 109:38] + wire _T_82 = io_ifu_fb_consume1 & _T_81; // @[ifu_ifc_ctl.scala 109:36] + wire _T_48 = io_ifc_fetch_req_f & _T_4; // @[ifu_ifc_ctl.scala 91:32] + wire miss_f = _T_48 & _T_2; // @[ifu_ifc_ctl.scala 91:47] + wire _T_84 = _T_3 | miss_f; // @[ifu_ifc_ctl.scala 109:81] + wire _T_85 = _T_82 & _T_84; // @[ifu_ifc_ctl.scala 109:58] + wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 110:25] + wire fb_right = _T_85 | _T_86; // @[ifu_ifc_ctl.scala 109:92] + wire _T_98 = _T_2 & fb_right; // @[ifu_ifc_ctl.scala 117:16] + reg [3:0] fb_write_f; // @[ifu_ifc_ctl.scala 128:50] wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58] wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72] - wire fb_right2 = io_ifu_fb_consume2 & _T_84; // @[ifu_ifc_ctl.scala 109:36] - wire _T_103 = _T_2 & fb_right2; // @[ifu_ifc_ctl.scala 114:16] + wire fb_right2 = io_ifu_fb_consume2 & _T_84; // @[ifu_ifc_ctl.scala 112:36] + wire _T_103 = _T_2 & fb_right2; // @[ifu_ifc_ctl.scala 118:16] wire [3:0] _T_106 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58] wire [3:0] _T_123 = _T_103 ? _T_106 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72] - wire _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[ifu_ifc_ctl.scala 110:56] - wire _T_92 = ~_T_91; // @[ifu_ifc_ctl.scala 110:35] - wire _T_93 = io_ifc_fetch_req_f & _T_92; // @[ifu_ifc_ctl.scala 110:33] - wire _T_94 = ~miss_f; // @[ifu_ifc_ctl.scala 110:80] - wire fb_left = _T_93 & _T_94; // @[ifu_ifc_ctl.scala 110:78] - wire _T_108 = _T_2 & fb_left; // @[ifu_ifc_ctl.scala 115:16] + wire _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[ifu_ifc_ctl.scala 113:56] + wire _T_92 = ~_T_91; // @[ifu_ifc_ctl.scala 113:35] + wire _T_93 = io_ifc_fetch_req_f & _T_92; // @[ifu_ifc_ctl.scala 113:33] + wire _T_94 = ~miss_f; // @[ifu_ifc_ctl.scala 113:80] + wire fb_left = _T_93 & _T_94; // @[ifu_ifc_ctl.scala 113:78] + wire _T_108 = _T_2 & fb_left; // @[ifu_ifc_ctl.scala 119:16] wire [3:0] _T_111 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58] wire [3:0] _T_124 = _T_108 ? _T_111 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72] - wire _T_113 = ~fb_right; // @[ifu_ifc_ctl.scala 116:18] - wire _T_114 = _T_2 & _T_113; // @[ifu_ifc_ctl.scala 116:16] - wire _T_115 = ~fb_right2; // @[ifu_ifc_ctl.scala 116:30] - wire _T_116 = _T_114 & _T_115; // @[ifu_ifc_ctl.scala 116:28] - wire _T_117 = ~fb_left; // @[ifu_ifc_ctl.scala 116:43] - wire _T_118 = _T_116 & _T_117; // @[ifu_ifc_ctl.scala 116:41] + wire _T_113 = ~fb_right; // @[ifu_ifc_ctl.scala 120:18] + wire _T_114 = _T_2 & _T_113; // @[ifu_ifc_ctl.scala 120:16] + wire _T_115 = ~fb_right2; // @[ifu_ifc_ctl.scala 120:30] + wire _T_116 = _T_114 & _T_115; // @[ifu_ifc_ctl.scala 120:28] + wire _T_117 = ~fb_left; // @[ifu_ifc_ctl.scala 120:43] + wire _T_118 = _T_116 & _T_117; // @[ifu_ifc_ctl.scala 120:41] wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72] wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72] - wire fb_full_f_ns = fb_write_ns[3]; // @[ifu_ifc_ctl.scala 122:30] - wire _T_37 = fb_full_f_ns & _T_36; // @[ifu_ifc_ctl.scala 84:68] - wire _T_38 = ~_T_37; // @[ifu_ifc_ctl.scala 84:53] - wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[ifu_ifc_ctl.scala 84:51] - wire _T_40 = ~dma_stall; // @[ifu_ifc_ctl.scala 85:5] - wire _T_41 = _T_39 & _T_40; // @[ifu_ifc_ctl.scala 84:114] - wire _T_42 = ~io_ic_write_stall; // @[ifu_ifc_ctl.scala 85:18] - wire _T_43 = _T_41 & _T_42; // @[ifu_ifc_ctl.scala 85:16] - wire _T_44 = ~io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 85:39] - wire _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[ifu_ifc_ctl.scala 91:39] - wire _T_53 = _T_51 & _T_40; // @[ifu_ifc_ctl.scala 91:61] - wire _T_55 = _T_53 & _T_94; // @[ifu_ifc_ctl.scala 91:74] - wire _T_56 = ~miss_a; // @[ifu_ifc_ctl.scala 91:86] - wire mb_empty_mod = _T_55 & _T_56; // @[ifu_ifc_ctl.scala 91:84] - wire goto_idle = io_exu_flush_final & io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 93:35] - wire _T_60 = io_exu_flush_final & _T_44; // @[ifu_ifc_ctl.scala 95:36] - wire leave_idle = _T_60 & idle; // @[ifu_ifc_ctl.scala 95:75] - wire _T_63 = ~state[1]; // @[ifu_ifc_ctl.scala 97:23] - wire _T_65 = _T_63 & state[0]; // @[ifu_ifc_ctl.scala 97:33] - wire _T_66 = _T_65 & miss_f; // @[ifu_ifc_ctl.scala 97:44] - wire _T_67 = ~goto_idle; // @[ifu_ifc_ctl.scala 97:55] - wire _T_68 = _T_66 & _T_67; // @[ifu_ifc_ctl.scala 97:53] - wire _T_70 = ~mb_empty_mod; // @[ifu_ifc_ctl.scala 98:17] - wire _T_71 = state[1] & _T_70; // @[ifu_ifc_ctl.scala 98:15] - wire _T_73 = _T_71 & _T_67; // @[ifu_ifc_ctl.scala 98:31] - wire next_state_1 = _T_68 | _T_73; // @[ifu_ifc_ctl.scala 97:67] - wire _T_75 = _T_67 & leave_idle; // @[ifu_ifc_ctl.scala 100:34] - wire _T_78 = state[0] & _T_67; // @[ifu_ifc_ctl.scala 100:60] - wire next_state_0 = _T_75 | _T_78; // @[ifu_ifc_ctl.scala 100:48] - wire wfm = state == 2'h3; // @[ifu_ifc_ctl.scala 120:16] - reg fb_full_f; // @[ifu_ifc_ctl.scala 123:52] - wire _T_136 = _T_35 | io_exu_flush_final; // @[ifu_ifc_ctl.scala 127:61] - wire _T_137 = ~_T_136; // @[ifu_ifc_ctl.scala 127:19] - wire _T_138 = fb_full_f & _T_137; // @[ifu_ifc_ctl.scala 127:17] - wire _T_139 = _T_138 | dma_stall; // @[ifu_ifc_ctl.scala 127:84] - wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[ifu_ifc_ctl.scala 126:68] + wire fb_full_f_ns = fb_write_ns[3]; // @[ifu_ifc_ctl.scala 126:30] + wire _T_37 = fb_full_f_ns & _T_36; // @[ifu_ifc_ctl.scala 86:68] + wire _T_38 = ~_T_37; // @[ifu_ifc_ctl.scala 86:53] + wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[ifu_ifc_ctl.scala 86:51] + wire _T_40 = ~dma_stall; // @[ifu_ifc_ctl.scala 87:5] + wire _T_41 = _T_39 & _T_40; // @[ifu_ifc_ctl.scala 86:114] + wire _T_42 = ~io_ic_write_stall; // @[ifu_ifc_ctl.scala 87:18] + wire _T_43 = _T_41 & _T_42; // @[ifu_ifc_ctl.scala 87:16] + wire _T_44 = ~io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 87:39] + wire _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[ifu_ifc_ctl.scala 93:39] + wire _T_53 = _T_51 & _T_40; // @[ifu_ifc_ctl.scala 93:61] + wire _T_55 = _T_53 & _T_94; // @[ifu_ifc_ctl.scala 93:74] + wire _T_56 = ~miss_a; // @[ifu_ifc_ctl.scala 93:86] + wire mb_empty_mod = _T_55 & _T_56; // @[ifu_ifc_ctl.scala 93:84] + wire goto_idle = io_exu_flush_final & io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 95:35] + wire _T_60 = io_exu_flush_final & _T_44; // @[ifu_ifc_ctl.scala 97:36] + wire leave_idle = _T_60 & idle; // @[ifu_ifc_ctl.scala 97:75] + wire _T_63 = ~state[1]; // @[ifu_ifc_ctl.scala 99:23] + wire _T_65 = _T_63 & state[0]; // @[ifu_ifc_ctl.scala 99:33] + wire _T_66 = _T_65 & miss_f; // @[ifu_ifc_ctl.scala 99:44] + wire _T_67 = ~goto_idle; // @[ifu_ifc_ctl.scala 99:55] + wire _T_68 = _T_66 & _T_67; // @[ifu_ifc_ctl.scala 99:53] + wire _T_70 = ~mb_empty_mod; // @[ifu_ifc_ctl.scala 100:17] + wire _T_71 = state[1] & _T_70; // @[ifu_ifc_ctl.scala 100:15] + wire _T_73 = _T_71 & _T_67; // @[ifu_ifc_ctl.scala 100:31] + wire next_state_1 = _T_68 | _T_73; // @[ifu_ifc_ctl.scala 99:67] + wire _T_75 = _T_67 & leave_idle; // @[ifu_ifc_ctl.scala 102:34] + wire _T_78 = state[0] & _T_67; // @[ifu_ifc_ctl.scala 102:60] + wire next_state_0 = _T_75 | _T_78; // @[ifu_ifc_ctl.scala 102:48] + wire wfm = state == 2'h3; // @[ifu_ifc_ctl.scala 124:16] + reg fb_full_f; // @[ifu_ifc_ctl.scala 127:52] + wire _T_136 = _T_35 | io_exu_flush_final; // @[ifu_ifc_ctl.scala 131:61] + wire _T_137 = ~_T_136; // @[ifu_ifc_ctl.scala 131:19] + wire _T_138 = fb_full_f & _T_137; // @[ifu_ifc_ctl.scala 131:17] + wire _T_139 = _T_138 | dma_stall; // @[ifu_ifc_ctl.scala 131:84] + wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[ifu_ifc_ctl.scala 130:68] wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58] wire iccm_acc_in_region_bf = _T_142[31:28] == 4'he; // @[lib.scala 68:47] wire iccm_acc_in_range_bf = _T_142[31:16] == 16'hee00; // @[lib.scala 71:29] - wire _T_145 = ~io_ifc_iccm_access_bf; // @[ifu_ifc_ctl.scala 133:30] - wire _T_148 = fb_full_f & _T_36; // @[ifu_ifc_ctl.scala 134:16] - wire _T_149 = _T_145 | _T_148; // @[ifu_ifc_ctl.scala 133:53] - wire _T_150 = ~io_ifc_fetch_req_bf; // @[ifu_ifc_ctl.scala 135:13] - wire _T_151 = wfm & _T_150; // @[ifu_ifc_ctl.scala 135:11] - wire _T_152 = _T_149 | _T_151; // @[ifu_ifc_ctl.scala 134:62] - wire _T_153 = _T_152 | idle; // @[ifu_ifc_ctl.scala 135:35] - wire _T_155 = _T_153 & _T_2; // @[ifu_ifc_ctl.scala 135:44] - wire _T_157 = ~iccm_acc_in_range_bf; // @[ifu_ifc_ctl.scala 137:33] + wire _T_145 = ~io_ifc_iccm_access_bf; // @[ifu_ifc_ctl.scala 138:30] + wire _T_148 = fb_full_f & _T_36; // @[ifu_ifc_ctl.scala 139:16] + wire _T_149 = _T_145 | _T_148; // @[ifu_ifc_ctl.scala 138:53] + wire _T_150 = ~io_ifc_fetch_req_bf; // @[ifu_ifc_ctl.scala 140:13] + wire _T_151 = wfm & _T_150; // @[ifu_ifc_ctl.scala 140:11] + wire _T_152 = _T_149 | _T_151; // @[ifu_ifc_ctl.scala 139:62] + wire _T_153 = _T_152 | idle; // @[ifu_ifc_ctl.scala 140:35] + wire _T_155 = _T_153 & _T_2; // @[ifu_ifc_ctl.scala 140:44] + wire _T_157 = ~iccm_acc_in_range_bf; // @[ifu_ifc_ctl.scala 142:33] wire [4:0] _T_160 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_161 = io_dec_ifc_dec_tlu_mrac_ff >> _T_160; // @[ifu_ifc_ctl.scala 138:61] - reg _T_164; // @[ifu_ifc_ctl.scala 140:57] + wire [31:0] _T_161 = io_dec_ifc_dec_tlu_mrac_ff >> _T_160; // @[ifu_ifc_ctl.scala 143:61] + reg _T_164; // @[ifu_ifc_ctl.scala 145:57] reg [30:0] _T_166; // @[lib.scala 358:16] rvclkhdr rvclkhdr ( // @[lib.scala 352:23] .io_l1clk(rvclkhdr_io_l1clk), @@ -44285,16 +44285,16 @@ module ifu_ifc_ctl( .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - assign io_dec_ifc_ifu_pmu_fetch_stall = wfm | _T_140; // @[ifu_ifc_ctl.scala 126:34] - assign io_ifc_fetch_addr_f = _T_166; // @[ifu_ifc_ctl.scala 142:23] - assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[ifu_ifc_ctl.scala 72:24] - assign io_ifc_fetch_req_f = _T_164; // @[ifu_ifc_ctl.scala 140:22] - assign io_ifc_fetch_uncacheable_bf = ~_T_161[0]; // @[ifu_ifc_ctl.scala 138:31] - assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[ifu_ifc_ctl.scala 84:23] - assign io_ifc_fetch_req_bf_raw = ~idle; // @[ifu_ifc_ctl.scala 82:27] - assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[ifu_ifc_ctl.scala 132:25] - assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[ifu_ifc_ctl.scala 137:30] - assign io_ifc_dma_access_ok = _T_155 | dma_iccm_stall_any_f; // @[ifu_ifc_ctl.scala 133:24] + assign io_dec_ifc_ifu_pmu_fetch_stall = wfm | _T_140; // @[ifu_ifc_ctl.scala 130:34] + assign io_ifc_fetch_addr_f = _T_166; // @[ifu_ifc_ctl.scala 147:23] + assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[ifu_ifc_ctl.scala 73:24] + assign io_ifc_fetch_req_f = _T_164; // @[ifu_ifc_ctl.scala 145:22] + assign io_ifc_fetch_uncacheable_bf = ~_T_161[0]; // @[ifu_ifc_ctl.scala 143:31] + assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[ifu_ifc_ctl.scala 86:23] + assign io_ifc_fetch_req_bf_raw = ~idle; // @[ifu_ifc_ctl.scala 84:27] + assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[ifu_ifc_ctl.scala 137:25] + assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[ifu_ifc_ctl.scala 142:30] + assign io_ifc_dma_access_ok = _T_155 | dma_iccm_stall_any_f; // @[ifu_ifc_ctl.scala 138:24] assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_io_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[lib.scala 355:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] @@ -51360,246 +51360,245 @@ module csr_tlu( reg [31:0] dicad0h; // @[lib.scala 358:16] wire _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2128:100] wire _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2128:71] - wire _T_756 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2132:78] - reg [31:0] _T_758; // @[Reg.scala 27:20] - wire [31:0] dicad1 = {25'h0,_T_758[6:0]}; // @[Cat.scala 29:58] - wire [38:0] _T_763 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] - wire _T_765 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2160:52] - wire _T_766 = _T_765 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2160:75] - wire _T_767 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2160:98] - wire _T_768 = _T_766 & _T_767; // @[dec_tlu_ctl.scala 2160:96] - wire _T_770 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2160:149] - wire _T_773 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2161:104] + wire _T_757 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2132:78] + reg [6:0] _T_759; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_759}; // @[Cat.scala 29:58] + wire [38:0] _T_764 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_766 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2160:52] + wire _T_767 = _T_766 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2160:75] + wire _T_768 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2160:98] + wire _T_769 = _T_767 & _T_768; // @[dec_tlu_ctl.scala 2160:96] + wire _T_771 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2160:149] + wire _T_774 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2161:104] reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2163:58] reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2164:58] - wire _T_775 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2175:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_775; // @[dec_tlu_ctl.scala 2175:40] + wire _T_776 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2175:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_776; // @[dec_tlu_ctl.scala 2175:40] reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2178:43] wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2213:42] wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2215:44] - wire _T_786 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2217:46] - wire tdata_action = _T_786 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2217:69] - wire [9:0] tdata_wrdata_r = {_T_786,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_801 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2223:99] - wire _T_802 = io_dec_csr_wen_r_mod & _T_801; // @[dec_tlu_ctl.scala 2223:70] - wire _T_803 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2223:121] - wire _T_804 = _T_802 & _T_803; // @[dec_tlu_ctl.scala 2223:112] - wire _T_806 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_0 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2223:135] - wire _T_812 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2223:121] - wire _T_813 = _T_802 & _T_812; // @[dec_tlu_ctl.scala 2223:112] - wire _T_815 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_1 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2223:135] - wire _T_821 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2223:121] - wire _T_822 = _T_802 & _T_821; // @[dec_tlu_ctl.scala 2223:112] - wire _T_824 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_2 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2223:135] - wire _T_830 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2223:121] - wire _T_831 = _T_802 & _T_830; // @[dec_tlu_ctl.scala 2223:112] - wire _T_833 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2223:138] - wire _T_834 = _T_833 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] - wire wr_mtdata1_t_r_3 = _T_831 & _T_834; // @[dec_tlu_ctl.scala 2223:135] - wire _T_840 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_843 = {io_mtdata1_t_0[9],_T_840,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_849 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_852 = {io_mtdata1_t_1[9],_T_849,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_858 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_861 = {io_mtdata1_t_2[9],_T_858,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_867 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2224:139] - wire [9:0] _T_870 = {io_mtdata1_t_3[9],_T_867,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_872; // @[dec_tlu_ctl.scala 2226:74] + wire _T_787 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2217:46] + wire tdata_action = _T_787 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2217:69] + wire [9:0] tdata_wrdata_r = {_T_787,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_802 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2223:99] + wire _T_803 = io_dec_csr_wen_r_mod & _T_802; // @[dec_tlu_ctl.scala 2223:70] + wire _T_804 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2223:121] + wire _T_805 = _T_803 & _T_804; // @[dec_tlu_ctl.scala 2223:112] + wire _T_807 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_808 = _T_807 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_0 = _T_805 & _T_808; // @[dec_tlu_ctl.scala 2223:135] + wire _T_813 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2223:121] + wire _T_814 = _T_803 & _T_813; // @[dec_tlu_ctl.scala 2223:112] + wire _T_816 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_817 = _T_816 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_1 = _T_814 & _T_817; // @[dec_tlu_ctl.scala 2223:135] + wire _T_822 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2223:121] + wire _T_823 = _T_803 & _T_822; // @[dec_tlu_ctl.scala 2223:112] + wire _T_825 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_826 = _T_825 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_2 = _T_823 & _T_826; // @[dec_tlu_ctl.scala 2223:135] + wire _T_831 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2223:121] + wire _T_832 = _T_803 & _T_831; // @[dec_tlu_ctl.scala 2223:112] + wire _T_834 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_835 = _T_834 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_3 = _T_832 & _T_835; // @[dec_tlu_ctl.scala 2223:135] + wire _T_841 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2224:139] + wire [9:0] _T_844 = {io_mtdata1_t_0[9],_T_841,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_850 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2224:139] + wire [9:0] _T_853 = {io_mtdata1_t_1[9],_T_850,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_859 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2224:139] + wire [9:0] _T_862 = {io_mtdata1_t_2[9],_T_859,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_868 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2224:139] + wire [9:0] _T_871 = {io_mtdata1_t_3[9],_T_868,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2226:74] reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2226:74] reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2226:74] - wire [31:0] _T_890 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_905 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_920 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_935 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_936 = _T_803 ? _T_890 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_937 = _T_812 ? _T_905 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_938 = _T_821 ? _T_920 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_939 = _T_830 ? _T_935 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_940 = _T_936 | _T_937; // @[Mux.scala 27:72] - wire [31:0] _T_941 = _T_940 | _T_938; // @[Mux.scala 27:72] - wire [31:0] mtdata1_tsel_out = _T_941 | _T_939; // @[Mux.scala 27:72] - wire _T_968 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2243:98] - wire _T_969 = io_dec_csr_wen_r_mod & _T_968; // @[dec_tlu_ctl.scala 2243:69] - wire _T_971 = _T_969 & _T_803; // @[dec_tlu_ctl.scala 2243:111] - wire _T_980 = _T_969 & _T_812; // @[dec_tlu_ctl.scala 2243:111] - wire _T_989 = _T_969 & _T_821; // @[dec_tlu_ctl.scala 2243:111] - wire _T_998 = _T_969 & _T_830; // @[dec_tlu_ctl.scala 2243:111] + reg [9:0] _T_876; // @[dec_tlu_ctl.scala 2226:74] + wire [31:0] _T_891 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_906 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_921 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_936 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_937 = _T_804 ? _T_891 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_938 = _T_813 ? _T_906 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_939 = _T_822 ? _T_921 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_940 = _T_831 ? _T_936 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_941 = _T_937 | _T_938; // @[Mux.scala 27:72] + wire [31:0] _T_942 = _T_941 | _T_939; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_942 | _T_940; // @[Mux.scala 27:72] + wire _T_969 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2243:98] + wire _T_970 = io_dec_csr_wen_r_mod & _T_969; // @[dec_tlu_ctl.scala 2243:69] + wire _T_972 = _T_970 & _T_804; // @[dec_tlu_ctl.scala 2243:111] + wire _T_981 = _T_970 & _T_813; // @[dec_tlu_ctl.scala 2243:111] + wire _T_990 = _T_970 & _T_822; // @[dec_tlu_ctl.scala 2243:111] + wire _T_999 = _T_970 & _T_831; // @[dec_tlu_ctl.scala 2243:111] reg [31:0] mtdata2_t_0; // @[lib.scala 358:16] reg [31:0] mtdata2_t_1; // @[lib.scala 358:16] reg [31:0] mtdata2_t_2; // @[lib.scala 358:16] reg [31:0] mtdata2_t_3; // @[lib.scala 358:16] - wire [31:0] _T_1015 = _T_803 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1016 = _T_812 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1017 = _T_821 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1018 = _T_830 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1019 = _T_1015 | _T_1016; // @[Mux.scala 27:72] - wire [31:0] _T_1020 = _T_1019 | _T_1017; // @[Mux.scala 27:72] - wire [31:0] mtdata2_tsel_out = _T_1020 | _T_1018; // @[Mux.scala 27:72] - wire [3:0] _T_1023 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1023; // @[dec_tlu_ctl.scala 2268:59] - wire _T_1025 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2274:24] + wire [31:0] _T_1016 = _T_804 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1017 = _T_813 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1018 = _T_822 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1019 = _T_831 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1020 = _T_1016 | _T_1017; // @[Mux.scala 27:72] + wire [31:0] _T_1021 = _T_1020 | _T_1018; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1021 | _T_1019; // @[Mux.scala 27:72] + wire [3:0] _T_1024 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1024; // @[dec_tlu_ctl.scala 2268:59] + wire _T_1026 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1026 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1028 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1030 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1032 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1034 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2278:96] - wire _T_1035 = io_tlu_i0_commit_cmt & _T_1034; // @[dec_tlu_ctl.scala 2278:94] - wire _T_1036 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1038 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:96] - wire _T_1039 = io_tlu_i0_commit_cmt & _T_1038; // @[dec_tlu_ctl.scala 2279:94] - wire _T_1041 = _T_1039 & _T_1034; // @[dec_tlu_ctl.scala 2279:115] - wire _T_1042 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1044 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2280:94] - wire _T_1046 = _T_1044 & _T_1034; // @[dec_tlu_ctl.scala 2280:115] - wire _T_1047 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1049 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1051 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1053 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1055 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2284:91] - wire _T_1056 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1058 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2285:105] - wire _T_1059 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1061 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2286:91] - wire _T_1062 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1064 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2287:91] - wire _T_1065 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1068 = _T_1061 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:100] - wire _T_1069 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1073 = _T_1064 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2289:101] - wire _T_1074 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1076 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2290:89] - wire _T_1077 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1079 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2291:89] - wire _T_1080 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1082 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2292:89] - wire _T_1083 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1085 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2293:89] - wire _T_1086 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1088 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2294:89] - wire _T_1089 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1091 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2295:89] - wire _T_1092 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1094 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2296:89] - wire _T_1095 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1097 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2297:89] - wire _T_1098 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1100 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2298:89] - wire _T_1101 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1103 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2299:89] - wire _T_1104 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2299:122] - wire _T_1105 = _T_1103 | _T_1104; // @[dec_tlu_ctl.scala 2299:101] - wire _T_1106 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1108 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:95] - wire _T_1109 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1111 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:97] - wire _T_1112 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1114 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2302:110] - wire _T_1115 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1119 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1121 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1123 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1125 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1127 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1129 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1131 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2310:98] - wire _T_1132 = _T_1131 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2310:120] - wire _T_1133 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1135 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2311:92] - wire _T_1136 = _T_1135 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2311:117] - wire _T_1137 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1139 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1141 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1143 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2314:97] - wire _T_1144 = _T_1143 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2314:129] - wire _T_1145 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1147 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1149 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1151 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1153 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1155 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1157 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1159 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1163 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2322:73] - wire _T_1164 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire [5:0] _T_1171 = io_mip & mie; // @[dec_tlu_ctl.scala 2323:113] - wire _T_1172 = |_T_1171; // @[dec_tlu_ctl.scala 2323:125] - wire _T_1173 = _T_1163 & _T_1172; // @[dec_tlu_ctl.scala 2323:98] - wire _T_1174 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2324:91] - wire _T_1177 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2325:94] - wire _T_1180 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2326:94] - wire _T_1183 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1185 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1187 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1189 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1191 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1194 = _T_1028 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1195 = _T_1030 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1196 = _T_1032 & _T_1035; // @[Mux.scala 27:72] - wire _T_1197 = _T_1036 & _T_1041; // @[Mux.scala 27:72] - wire _T_1198 = _T_1042 & _T_1046; // @[Mux.scala 27:72] - wire _T_1199 = _T_1047 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1200 = _T_1049 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1201 = _T_1051 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1202 = _T_1053 & _T_1055; // @[Mux.scala 27:72] - wire _T_1203 = _T_1056 & _T_1058; // @[Mux.scala 27:72] - wire _T_1204 = _T_1059 & _T_1061; // @[Mux.scala 27:72] - wire _T_1205 = _T_1062 & _T_1064; // @[Mux.scala 27:72] - wire _T_1206 = _T_1065 & _T_1068; // @[Mux.scala 27:72] - wire _T_1207 = _T_1069 & _T_1073; // @[Mux.scala 27:72] - wire _T_1208 = _T_1074 & _T_1076; // @[Mux.scala 27:72] - wire _T_1209 = _T_1077 & _T_1079; // @[Mux.scala 27:72] - wire _T_1210 = _T_1080 & _T_1082; // @[Mux.scala 27:72] - wire _T_1211 = _T_1083 & _T_1085; // @[Mux.scala 27:72] - wire _T_1212 = _T_1086 & _T_1088; // @[Mux.scala 27:72] - wire _T_1213 = _T_1089 & _T_1091; // @[Mux.scala 27:72] - wire _T_1214 = _T_1092 & _T_1094; // @[Mux.scala 27:72] - wire _T_1215 = _T_1095 & _T_1097; // @[Mux.scala 27:72] - wire _T_1216 = _T_1098 & _T_1100; // @[Mux.scala 27:72] - wire _T_1217 = _T_1101 & _T_1105; // @[Mux.scala 27:72] - wire _T_1218 = _T_1106 & _T_1108; // @[Mux.scala 27:72] - wire _T_1219 = _T_1109 & _T_1111; // @[Mux.scala 27:72] - wire _T_1220 = _T_1112 & _T_1114; // @[Mux.scala 27:72] - wire _T_1221 = _T_1115 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1223 = _T_1119 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1224 = _T_1121 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1225 = _T_1123 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1226 = _T_1125 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1227 = _T_1127 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1228 = _T_1129 & _T_1132; // @[Mux.scala 27:72] - wire _T_1229 = _T_1133 & _T_1136; // @[Mux.scala 27:72] - wire _T_1230 = _T_1137 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1231 = _T_1139 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1232 = _T_1141 & _T_1144; // @[Mux.scala 27:72] - wire _T_1233 = _T_1145 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1234 = _T_1147 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1235 = _T_1149 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1236 = _T_1151 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1237 = _T_1153 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1238 = _T_1155 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1239 = _T_1157 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1240 = _T_1159 & _T_1163; // @[Mux.scala 27:72] - wire _T_1241 = _T_1164 & _T_1173; // @[Mux.scala 27:72] - wire _T_1242 = _T_1174 & _T_1176; // @[Mux.scala 27:72] - wire _T_1243 = _T_1177 & _T_1179; // @[Mux.scala 27:72] - wire _T_1244 = _T_1180 & _T_1182; // @[Mux.scala 27:72] - wire _T_1245 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1246 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1247 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1248 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1249 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1250 = _T_1026 | _T_1194; // @[Mux.scala 27:72] - wire _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72] + wire _T_1027 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1029 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1031 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1033 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1035 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2278:96] + wire _T_1036 = io_tlu_i0_commit_cmt & _T_1035; // @[dec_tlu_ctl.scala 2278:94] + wire _T_1037 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1039 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:96] + wire _T_1040 = io_tlu_i0_commit_cmt & _T_1039; // @[dec_tlu_ctl.scala 2279:94] + wire _T_1042 = _T_1040 & _T_1035; // @[dec_tlu_ctl.scala 2279:115] + wire _T_1043 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1045 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2280:94] + wire _T_1047 = _T_1045 & _T_1035; // @[dec_tlu_ctl.scala 2280:115] + wire _T_1048 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1050 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1052 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1054 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1056 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2284:91] + wire _T_1057 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1059 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2285:105] + wire _T_1060 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1062 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2286:91] + wire _T_1063 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1065 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2287:91] + wire _T_1066 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1069 = _T_1062 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:100] + wire _T_1070 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1074 = _T_1065 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2289:101] + wire _T_1075 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1077 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2290:89] + wire _T_1078 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1080 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2291:89] + wire _T_1081 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1083 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2292:89] + wire _T_1084 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1086 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2293:89] + wire _T_1087 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1089 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2294:89] + wire _T_1090 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1092 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2295:89] + wire _T_1093 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1095 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2296:89] + wire _T_1096 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1098 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2297:89] + wire _T_1099 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1101 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2298:89] + wire _T_1102 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1104 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2299:89] + wire _T_1105 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2299:122] + wire _T_1106 = _T_1104 | _T_1105; // @[dec_tlu_ctl.scala 2299:101] + wire _T_1107 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1109 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:95] + wire _T_1110 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1112 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:97] + wire _T_1113 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1115 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2302:110] + wire _T_1116 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1120 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1122 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1124 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1126 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1128 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1130 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1132 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2310:98] + wire _T_1133 = _T_1132 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2310:120] + wire _T_1134 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1136 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2311:92] + wire _T_1137 = _T_1136 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2311:117] + wire _T_1138 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1140 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1142 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1144 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2314:97] + wire _T_1145 = _T_1144 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2314:129] + wire _T_1146 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1148 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1150 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1152 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1154 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1156 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1158 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1160 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1164 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2322:73] + wire _T_1165 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire [5:0] _T_1172 = io_mip & mie; // @[dec_tlu_ctl.scala 2323:113] + wire _T_1173 = |_T_1172; // @[dec_tlu_ctl.scala 2323:125] + wire _T_1174 = _T_1164 & _T_1173; // @[dec_tlu_ctl.scala 2323:98] + wire _T_1175 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1177 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2324:91] + wire _T_1178 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1180 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2325:94] + wire _T_1181 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1183 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2326:94] + wire _T_1184 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1186 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1188 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1190 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1192 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] + wire _T_1195 = _T_1029 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1196 = _T_1031 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1197 = _T_1033 & _T_1036; // @[Mux.scala 27:72] + wire _T_1198 = _T_1037 & _T_1042; // @[Mux.scala 27:72] + wire _T_1199 = _T_1043 & _T_1047; // @[Mux.scala 27:72] + wire _T_1200 = _T_1048 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1201 = _T_1050 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1202 = _T_1052 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1203 = _T_1054 & _T_1056; // @[Mux.scala 27:72] + wire _T_1204 = _T_1057 & _T_1059; // @[Mux.scala 27:72] + wire _T_1205 = _T_1060 & _T_1062; // @[Mux.scala 27:72] + wire _T_1206 = _T_1063 & _T_1065; // @[Mux.scala 27:72] + wire _T_1207 = _T_1066 & _T_1069; // @[Mux.scala 27:72] + wire _T_1208 = _T_1070 & _T_1074; // @[Mux.scala 27:72] + wire _T_1209 = _T_1075 & _T_1077; // @[Mux.scala 27:72] + wire _T_1210 = _T_1078 & _T_1080; // @[Mux.scala 27:72] + wire _T_1211 = _T_1081 & _T_1083; // @[Mux.scala 27:72] + wire _T_1212 = _T_1084 & _T_1086; // @[Mux.scala 27:72] + wire _T_1213 = _T_1087 & _T_1089; // @[Mux.scala 27:72] + wire _T_1214 = _T_1090 & _T_1092; // @[Mux.scala 27:72] + wire _T_1215 = _T_1093 & _T_1095; // @[Mux.scala 27:72] + wire _T_1216 = _T_1096 & _T_1098; // @[Mux.scala 27:72] + wire _T_1217 = _T_1099 & _T_1101; // @[Mux.scala 27:72] + wire _T_1218 = _T_1102 & _T_1106; // @[Mux.scala 27:72] + wire _T_1219 = _T_1107 & _T_1109; // @[Mux.scala 27:72] + wire _T_1220 = _T_1110 & _T_1112; // @[Mux.scala 27:72] + wire _T_1221 = _T_1113 & _T_1115; // @[Mux.scala 27:72] + wire _T_1222 = _T_1116 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1224 = _T_1120 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1225 = _T_1122 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1226 = _T_1124 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1227 = _T_1126 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1228 = _T_1128 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1229 = _T_1130 & _T_1133; // @[Mux.scala 27:72] + wire _T_1230 = _T_1134 & _T_1137; // @[Mux.scala 27:72] + wire _T_1231 = _T_1138 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1232 = _T_1140 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1233 = _T_1142 & _T_1145; // @[Mux.scala 27:72] + wire _T_1234 = _T_1146 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1235 = _T_1148 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1236 = _T_1150 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1237 = _T_1152 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1238 = _T_1154 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1239 = _T_1156 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1240 = _T_1158 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1241 = _T_1160 & _T_1164; // @[Mux.scala 27:72] + wire _T_1242 = _T_1165 & _T_1174; // @[Mux.scala 27:72] + wire _T_1243 = _T_1175 & _T_1177; // @[Mux.scala 27:72] + wire _T_1244 = _T_1178 & _T_1180; // @[Mux.scala 27:72] + wire _T_1245 = _T_1181 & _T_1183; // @[Mux.scala 27:72] + wire _T_1246 = _T_1184 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1247 = _T_1186 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1248 = _T_1188 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1249 = _T_1190 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1250 = _T_1192 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1251 = _T_1027 | _T_1195; // @[Mux.scala 27:72] wire _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72] wire _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72] wire _T_1254 = _T_1253 | _T_1198; // @[Mux.scala 27:72] @@ -51626,8 +51625,8 @@ module csr_tlu( wire _T_1275 = _T_1274 | _T_1219; // @[Mux.scala 27:72] wire _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72] wire _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72] - wire _T_1278 = _T_1277 | _T_1201; // @[Mux.scala 27:72] - wire _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72] + wire _T_1279 = _T_1278 | _T_1202; // @[Mux.scala 27:72] wire _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72] wire _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72] wire _T_1282 = _T_1281 | _T_1226; // @[Mux.scala 27:72] @@ -51654,122 +51653,122 @@ module csr_tlu( wire _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72] wire _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72] wire _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1025 & _T_1305; // @[dec_tlu_ctl.scala 2274:44] - wire _T_1309 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2274:24] + wire _T_1306 = _T_1305 | _T_1250; // @[Mux.scala 27:72] + wire mhpmc_inc_r_0 = _T_1026 & _T_1306; // @[dec_tlu_ctl.scala 2274:44] + wire _T_1310 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1310 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1312 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1314 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1316 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1320 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1326 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1331 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1333 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1335 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1337 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1340 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1343 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1346 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1349 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1353 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1358 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1361 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1364 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1367 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1370 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1373 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1376 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1379 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1382 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1385 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1390 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1393 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1396 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1399 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1403 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1405 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1407 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1409 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1411 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1413 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1417 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1421 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1423 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1425 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1429 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1431 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1433 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1435 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1437 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1439 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1441 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1443 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1448 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1458 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1461 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1464 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1467 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1469 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1471 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1473 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1475 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1478 = _T_1312 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1479 = _T_1314 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1480 = _T_1316 & _T_1035; // @[Mux.scala 27:72] - wire _T_1481 = _T_1320 & _T_1041; // @[Mux.scala 27:72] - wire _T_1482 = _T_1326 & _T_1046; // @[Mux.scala 27:72] - wire _T_1483 = _T_1331 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1484 = _T_1333 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1485 = _T_1335 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1486 = _T_1337 & _T_1055; // @[Mux.scala 27:72] - wire _T_1487 = _T_1340 & _T_1058; // @[Mux.scala 27:72] - wire _T_1488 = _T_1343 & _T_1061; // @[Mux.scala 27:72] - wire _T_1489 = _T_1346 & _T_1064; // @[Mux.scala 27:72] - wire _T_1490 = _T_1349 & _T_1068; // @[Mux.scala 27:72] - wire _T_1491 = _T_1353 & _T_1073; // @[Mux.scala 27:72] - wire _T_1492 = _T_1358 & _T_1076; // @[Mux.scala 27:72] - wire _T_1493 = _T_1361 & _T_1079; // @[Mux.scala 27:72] - wire _T_1494 = _T_1364 & _T_1082; // @[Mux.scala 27:72] - wire _T_1495 = _T_1367 & _T_1085; // @[Mux.scala 27:72] - wire _T_1496 = _T_1370 & _T_1088; // @[Mux.scala 27:72] - wire _T_1497 = _T_1373 & _T_1091; // @[Mux.scala 27:72] - wire _T_1498 = _T_1376 & _T_1094; // @[Mux.scala 27:72] - wire _T_1499 = _T_1379 & _T_1097; // @[Mux.scala 27:72] - wire _T_1500 = _T_1382 & _T_1100; // @[Mux.scala 27:72] - wire _T_1501 = _T_1385 & _T_1105; // @[Mux.scala 27:72] - wire _T_1502 = _T_1390 & _T_1108; // @[Mux.scala 27:72] - wire _T_1503 = _T_1393 & _T_1111; // @[Mux.scala 27:72] - wire _T_1504 = _T_1396 & _T_1114; // @[Mux.scala 27:72] - wire _T_1505 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1507 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1508 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1509 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1510 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1511 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1512 = _T_1413 & _T_1132; // @[Mux.scala 27:72] - wire _T_1513 = _T_1417 & _T_1136; // @[Mux.scala 27:72] - wire _T_1514 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1515 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1516 = _T_1425 & _T_1144; // @[Mux.scala 27:72] - wire _T_1517 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1518 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1519 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1520 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1521 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1522 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1523 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1524 = _T_1443 & _T_1163; // @[Mux.scala 27:72] - wire _T_1525 = _T_1448 & _T_1173; // @[Mux.scala 27:72] - wire _T_1526 = _T_1458 & _T_1176; // @[Mux.scala 27:72] - wire _T_1527 = _T_1461 & _T_1179; // @[Mux.scala 27:72] - wire _T_1528 = _T_1464 & _T_1182; // @[Mux.scala 27:72] - wire _T_1529 = _T_1467 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1530 = _T_1469 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1531 = _T_1471 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1532 = _T_1473 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1533 = _T_1475 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1534 = _T_1310 | _T_1478; // @[Mux.scala 27:72] - wire _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72] + wire _T_1311 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1313 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1315 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1317 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1321 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1327 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1332 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1334 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1336 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1338 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1341 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1344 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1347 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1350 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1354 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1359 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1362 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1365 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1368 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1371 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1374 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1377 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1380 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1383 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1386 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1391 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1394 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1397 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1400 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1404 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1406 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1408 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1410 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1412 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1414 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1418 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1422 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1424 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1426 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1430 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1432 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1434 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1436 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1438 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1440 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1442 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1444 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1449 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1459 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1462 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1465 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1468 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1470 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1472 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1474 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1476 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] + wire _T_1479 = _T_1313 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1480 = _T_1315 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1481 = _T_1317 & _T_1036; // @[Mux.scala 27:72] + wire _T_1482 = _T_1321 & _T_1042; // @[Mux.scala 27:72] + wire _T_1483 = _T_1327 & _T_1047; // @[Mux.scala 27:72] + wire _T_1484 = _T_1332 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1485 = _T_1334 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1486 = _T_1336 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1487 = _T_1338 & _T_1056; // @[Mux.scala 27:72] + wire _T_1488 = _T_1341 & _T_1059; // @[Mux.scala 27:72] + wire _T_1489 = _T_1344 & _T_1062; // @[Mux.scala 27:72] + wire _T_1490 = _T_1347 & _T_1065; // @[Mux.scala 27:72] + wire _T_1491 = _T_1350 & _T_1069; // @[Mux.scala 27:72] + wire _T_1492 = _T_1354 & _T_1074; // @[Mux.scala 27:72] + wire _T_1493 = _T_1359 & _T_1077; // @[Mux.scala 27:72] + wire _T_1494 = _T_1362 & _T_1080; // @[Mux.scala 27:72] + wire _T_1495 = _T_1365 & _T_1083; // @[Mux.scala 27:72] + wire _T_1496 = _T_1368 & _T_1086; // @[Mux.scala 27:72] + wire _T_1497 = _T_1371 & _T_1089; // @[Mux.scala 27:72] + wire _T_1498 = _T_1374 & _T_1092; // @[Mux.scala 27:72] + wire _T_1499 = _T_1377 & _T_1095; // @[Mux.scala 27:72] + wire _T_1500 = _T_1380 & _T_1098; // @[Mux.scala 27:72] + wire _T_1501 = _T_1383 & _T_1101; // @[Mux.scala 27:72] + wire _T_1502 = _T_1386 & _T_1106; // @[Mux.scala 27:72] + wire _T_1503 = _T_1391 & _T_1109; // @[Mux.scala 27:72] + wire _T_1504 = _T_1394 & _T_1112; // @[Mux.scala 27:72] + wire _T_1505 = _T_1397 & _T_1115; // @[Mux.scala 27:72] + wire _T_1506 = _T_1400 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1508 = _T_1404 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1509 = _T_1406 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1510 = _T_1408 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1511 = _T_1410 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1512 = _T_1412 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1513 = _T_1414 & _T_1133; // @[Mux.scala 27:72] + wire _T_1514 = _T_1418 & _T_1137; // @[Mux.scala 27:72] + wire _T_1515 = _T_1422 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1516 = _T_1424 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1517 = _T_1426 & _T_1145; // @[Mux.scala 27:72] + wire _T_1518 = _T_1430 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1519 = _T_1432 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1520 = _T_1434 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1521 = _T_1436 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1522 = _T_1438 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1523 = _T_1440 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1524 = _T_1442 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1525 = _T_1444 & _T_1164; // @[Mux.scala 27:72] + wire _T_1526 = _T_1449 & _T_1174; // @[Mux.scala 27:72] + wire _T_1527 = _T_1459 & _T_1177; // @[Mux.scala 27:72] + wire _T_1528 = _T_1462 & _T_1180; // @[Mux.scala 27:72] + wire _T_1529 = _T_1465 & _T_1183; // @[Mux.scala 27:72] + wire _T_1530 = _T_1468 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1531 = _T_1470 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1532 = _T_1472 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1533 = _T_1474 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1534 = _T_1476 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1535 = _T_1311 | _T_1479; // @[Mux.scala 27:72] wire _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72] wire _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72] wire _T_1538 = _T_1537 | _T_1482; // @[Mux.scala 27:72] @@ -51796,8 +51795,8 @@ module csr_tlu( wire _T_1559 = _T_1558 | _T_1503; // @[Mux.scala 27:72] wire _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72] wire _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72] - wire _T_1562 = _T_1561 | _T_1485; // @[Mux.scala 27:72] - wire _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72] + wire _T_1563 = _T_1562 | _T_1486; // @[Mux.scala 27:72] wire _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72] wire _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72] wire _T_1566 = _T_1565 | _T_1510; // @[Mux.scala 27:72] @@ -51824,122 +51823,122 @@ module csr_tlu( wire _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72] wire _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72] wire _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1309 & _T_1589; // @[dec_tlu_ctl.scala 2274:44] - wire _T_1593 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2274:24] + wire _T_1590 = _T_1589 | _T_1534; // @[Mux.scala 27:72] + wire mhpmc_inc_r_1 = _T_1310 & _T_1590; // @[dec_tlu_ctl.scala 2274:44] + wire _T_1594 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1594 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1596 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1598 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1600 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1604 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1610 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1615 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1617 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1619 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1621 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1624 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1627 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1630 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1633 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1637 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1642 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1645 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1648 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1651 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1654 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1657 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1660 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1663 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1666 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1669 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1674 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1677 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1680 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1683 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1687 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1689 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1691 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1693 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1695 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1697 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1701 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1705 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1707 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1709 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1713 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1715 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1717 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1719 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1721 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1723 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1725 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1727 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1732 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1742 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1745 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1748 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1751 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1753 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1755 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1757 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1759 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1762 = _T_1596 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1763 = _T_1598 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1764 = _T_1600 & _T_1035; // @[Mux.scala 27:72] - wire _T_1765 = _T_1604 & _T_1041; // @[Mux.scala 27:72] - wire _T_1766 = _T_1610 & _T_1046; // @[Mux.scala 27:72] - wire _T_1767 = _T_1615 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1768 = _T_1617 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1769 = _T_1619 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1770 = _T_1621 & _T_1055; // @[Mux.scala 27:72] - wire _T_1771 = _T_1624 & _T_1058; // @[Mux.scala 27:72] - wire _T_1772 = _T_1627 & _T_1061; // @[Mux.scala 27:72] - wire _T_1773 = _T_1630 & _T_1064; // @[Mux.scala 27:72] - wire _T_1774 = _T_1633 & _T_1068; // @[Mux.scala 27:72] - wire _T_1775 = _T_1637 & _T_1073; // @[Mux.scala 27:72] - wire _T_1776 = _T_1642 & _T_1076; // @[Mux.scala 27:72] - wire _T_1777 = _T_1645 & _T_1079; // @[Mux.scala 27:72] - wire _T_1778 = _T_1648 & _T_1082; // @[Mux.scala 27:72] - wire _T_1779 = _T_1651 & _T_1085; // @[Mux.scala 27:72] - wire _T_1780 = _T_1654 & _T_1088; // @[Mux.scala 27:72] - wire _T_1781 = _T_1657 & _T_1091; // @[Mux.scala 27:72] - wire _T_1782 = _T_1660 & _T_1094; // @[Mux.scala 27:72] - wire _T_1783 = _T_1663 & _T_1097; // @[Mux.scala 27:72] - wire _T_1784 = _T_1666 & _T_1100; // @[Mux.scala 27:72] - wire _T_1785 = _T_1669 & _T_1105; // @[Mux.scala 27:72] - wire _T_1786 = _T_1674 & _T_1108; // @[Mux.scala 27:72] - wire _T_1787 = _T_1677 & _T_1111; // @[Mux.scala 27:72] - wire _T_1788 = _T_1680 & _T_1114; // @[Mux.scala 27:72] - wire _T_1789 = _T_1683 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1791 = _T_1687 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1792 = _T_1689 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1793 = _T_1691 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1794 = _T_1693 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1795 = _T_1695 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1796 = _T_1697 & _T_1132; // @[Mux.scala 27:72] - wire _T_1797 = _T_1701 & _T_1136; // @[Mux.scala 27:72] - wire _T_1798 = _T_1705 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1799 = _T_1707 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1800 = _T_1709 & _T_1144; // @[Mux.scala 27:72] - wire _T_1801 = _T_1713 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1802 = _T_1715 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1803 = _T_1717 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1804 = _T_1719 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1805 = _T_1721 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1806 = _T_1723 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1807 = _T_1725 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1808 = _T_1727 & _T_1163; // @[Mux.scala 27:72] - wire _T_1809 = _T_1732 & _T_1173; // @[Mux.scala 27:72] - wire _T_1810 = _T_1742 & _T_1176; // @[Mux.scala 27:72] - wire _T_1811 = _T_1745 & _T_1179; // @[Mux.scala 27:72] - wire _T_1812 = _T_1748 & _T_1182; // @[Mux.scala 27:72] - wire _T_1813 = _T_1751 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1814 = _T_1753 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1815 = _T_1755 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1816 = _T_1757 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1817 = _T_1759 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1818 = _T_1594 | _T_1762; // @[Mux.scala 27:72] - wire _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72] + wire _T_1595 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1597 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1599 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1601 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1605 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1611 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1616 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1618 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1620 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1622 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1625 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1628 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1631 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1634 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1638 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1643 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1646 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1649 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1652 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1655 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1658 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1661 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1664 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1667 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1670 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1675 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1678 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1681 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1684 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1688 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1690 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1692 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1694 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1696 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1698 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1702 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1706 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1708 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1710 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1714 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1716 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1718 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1720 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1722 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1724 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1726 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1728 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1733 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1743 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1746 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1749 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1752 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1754 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1756 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1758 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1760 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] + wire _T_1763 = _T_1597 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1764 = _T_1599 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1765 = _T_1601 & _T_1036; // @[Mux.scala 27:72] + wire _T_1766 = _T_1605 & _T_1042; // @[Mux.scala 27:72] + wire _T_1767 = _T_1611 & _T_1047; // @[Mux.scala 27:72] + wire _T_1768 = _T_1616 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1769 = _T_1618 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1770 = _T_1620 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1771 = _T_1622 & _T_1056; // @[Mux.scala 27:72] + wire _T_1772 = _T_1625 & _T_1059; // @[Mux.scala 27:72] + wire _T_1773 = _T_1628 & _T_1062; // @[Mux.scala 27:72] + wire _T_1774 = _T_1631 & _T_1065; // @[Mux.scala 27:72] + wire _T_1775 = _T_1634 & _T_1069; // @[Mux.scala 27:72] + wire _T_1776 = _T_1638 & _T_1074; // @[Mux.scala 27:72] + wire _T_1777 = _T_1643 & _T_1077; // @[Mux.scala 27:72] + wire _T_1778 = _T_1646 & _T_1080; // @[Mux.scala 27:72] + wire _T_1779 = _T_1649 & _T_1083; // @[Mux.scala 27:72] + wire _T_1780 = _T_1652 & _T_1086; // @[Mux.scala 27:72] + wire _T_1781 = _T_1655 & _T_1089; // @[Mux.scala 27:72] + wire _T_1782 = _T_1658 & _T_1092; // @[Mux.scala 27:72] + wire _T_1783 = _T_1661 & _T_1095; // @[Mux.scala 27:72] + wire _T_1784 = _T_1664 & _T_1098; // @[Mux.scala 27:72] + wire _T_1785 = _T_1667 & _T_1101; // @[Mux.scala 27:72] + wire _T_1786 = _T_1670 & _T_1106; // @[Mux.scala 27:72] + wire _T_1787 = _T_1675 & _T_1109; // @[Mux.scala 27:72] + wire _T_1788 = _T_1678 & _T_1112; // @[Mux.scala 27:72] + wire _T_1789 = _T_1681 & _T_1115; // @[Mux.scala 27:72] + wire _T_1790 = _T_1684 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1792 = _T_1688 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1793 = _T_1690 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1794 = _T_1692 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1795 = _T_1694 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1796 = _T_1696 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1797 = _T_1698 & _T_1133; // @[Mux.scala 27:72] + wire _T_1798 = _T_1702 & _T_1137; // @[Mux.scala 27:72] + wire _T_1799 = _T_1706 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1800 = _T_1708 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1801 = _T_1710 & _T_1145; // @[Mux.scala 27:72] + wire _T_1802 = _T_1714 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1803 = _T_1716 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1804 = _T_1718 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1805 = _T_1720 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1806 = _T_1722 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1807 = _T_1724 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1808 = _T_1726 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1809 = _T_1728 & _T_1164; // @[Mux.scala 27:72] + wire _T_1810 = _T_1733 & _T_1174; // @[Mux.scala 27:72] + wire _T_1811 = _T_1743 & _T_1177; // @[Mux.scala 27:72] + wire _T_1812 = _T_1746 & _T_1180; // @[Mux.scala 27:72] + wire _T_1813 = _T_1749 & _T_1183; // @[Mux.scala 27:72] + wire _T_1814 = _T_1752 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1815 = _T_1754 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1816 = _T_1756 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1817 = _T_1758 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1818 = _T_1760 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1819 = _T_1595 | _T_1763; // @[Mux.scala 27:72] wire _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72] wire _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72] wire _T_1822 = _T_1821 | _T_1766; // @[Mux.scala 27:72] @@ -51966,8 +51965,8 @@ module csr_tlu( wire _T_1843 = _T_1842 | _T_1787; // @[Mux.scala 27:72] wire _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72] wire _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72] - wire _T_1846 = _T_1845 | _T_1769; // @[Mux.scala 27:72] - wire _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72] + wire _T_1847 = _T_1846 | _T_1770; // @[Mux.scala 27:72] wire _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72] wire _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72] wire _T_1850 = _T_1849 | _T_1794; // @[Mux.scala 27:72] @@ -51994,122 +51993,122 @@ module csr_tlu( wire _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72] wire _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72] wire _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1593 & _T_1873; // @[dec_tlu_ctl.scala 2274:44] - wire _T_1877 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2274:24] + wire _T_1874 = _T_1873 | _T_1818; // @[Mux.scala 27:72] + wire mhpmc_inc_r_2 = _T_1594 & _T_1874; // @[dec_tlu_ctl.scala 2274:44] + wire _T_1878 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1878 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1880 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1882 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1884 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1888 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1894 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1899 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1901 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1903 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1905 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1908 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1911 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1914 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1917 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1921 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1926 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1929 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1932 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1935 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1938 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1941 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1944 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1947 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1950 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1953 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1958 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1961 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1964 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1967 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1971 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1973 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1975 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1977 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1979 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1981 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1985 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1989 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1991 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1993 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1997 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1999 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] - wire _T_2001 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] - wire _T_2003 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] - wire _T_2005 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] - wire _T_2007 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] - wire _T_2009 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] - wire _T_2011 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] - wire _T_2016 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] - wire _T_2026 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] - wire _T_2029 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] - wire _T_2032 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] - wire _T_2035 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] - wire _T_2037 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] - wire _T_2039 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] - wire _T_2041 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] - wire _T_2043 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] - wire _T_2046 = _T_1880 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_2047 = _T_1882 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_2048 = _T_1884 & _T_1035; // @[Mux.scala 27:72] - wire _T_2049 = _T_1888 & _T_1041; // @[Mux.scala 27:72] - wire _T_2050 = _T_1894 & _T_1046; // @[Mux.scala 27:72] - wire _T_2051 = _T_1899 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_2052 = _T_1901 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_2053 = _T_1903 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_2054 = _T_1905 & _T_1055; // @[Mux.scala 27:72] - wire _T_2055 = _T_1908 & _T_1058; // @[Mux.scala 27:72] - wire _T_2056 = _T_1911 & _T_1061; // @[Mux.scala 27:72] - wire _T_2057 = _T_1914 & _T_1064; // @[Mux.scala 27:72] - wire _T_2058 = _T_1917 & _T_1068; // @[Mux.scala 27:72] - wire _T_2059 = _T_1921 & _T_1073; // @[Mux.scala 27:72] - wire _T_2060 = _T_1926 & _T_1076; // @[Mux.scala 27:72] - wire _T_2061 = _T_1929 & _T_1079; // @[Mux.scala 27:72] - wire _T_2062 = _T_1932 & _T_1082; // @[Mux.scala 27:72] - wire _T_2063 = _T_1935 & _T_1085; // @[Mux.scala 27:72] - wire _T_2064 = _T_1938 & _T_1088; // @[Mux.scala 27:72] - wire _T_2065 = _T_1941 & _T_1091; // @[Mux.scala 27:72] - wire _T_2066 = _T_1944 & _T_1094; // @[Mux.scala 27:72] - wire _T_2067 = _T_1947 & _T_1097; // @[Mux.scala 27:72] - wire _T_2068 = _T_1950 & _T_1100; // @[Mux.scala 27:72] - wire _T_2069 = _T_1953 & _T_1105; // @[Mux.scala 27:72] - wire _T_2070 = _T_1958 & _T_1108; // @[Mux.scala 27:72] - wire _T_2071 = _T_1961 & _T_1111; // @[Mux.scala 27:72] - wire _T_2072 = _T_1964 & _T_1114; // @[Mux.scala 27:72] - wire _T_2073 = _T_1967 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_2075 = _T_1971 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_2076 = _T_1973 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_2077 = _T_1975 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_2078 = _T_1977 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_2079 = _T_1979 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_2080 = _T_1981 & _T_1132; // @[Mux.scala 27:72] - wire _T_2081 = _T_1985 & _T_1136; // @[Mux.scala 27:72] - wire _T_2082 = _T_1989 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_2083 = _T_1991 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_2084 = _T_1993 & _T_1144; // @[Mux.scala 27:72] - wire _T_2085 = _T_1997 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2086 = _T_1999 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2087 = _T_2001 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_2088 = _T_2003 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2089 = _T_2005 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2090 = _T_2007 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2091 = _T_2009 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2092 = _T_2011 & _T_1163; // @[Mux.scala 27:72] - wire _T_2093 = _T_2016 & _T_1173; // @[Mux.scala 27:72] - wire _T_2094 = _T_2026 & _T_1176; // @[Mux.scala 27:72] - wire _T_2095 = _T_2029 & _T_1179; // @[Mux.scala 27:72] - wire _T_2096 = _T_2032 & _T_1182; // @[Mux.scala 27:72] - wire _T_2097 = _T_2035 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_2098 = _T_2037 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_2099 = _T_2039 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_2100 = _T_2041 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_2101 = _T_2043 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_2102 = _T_1878 | _T_2046; // @[Mux.scala 27:72] - wire _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72] + wire _T_1879 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1881 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1883 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1885 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1889 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1895 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1900 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1902 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1904 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1906 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1909 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1912 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1915 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1918 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1922 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1927 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1930 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1933 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1936 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1939 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1942 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1945 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1948 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1951 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1954 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1959 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1962 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1965 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1968 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1972 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1974 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1976 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1978 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1980 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1982 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1986 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1990 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1992 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1994 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1998 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_2000 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_2002 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_2004 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_2006 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_2008 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_2010 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_2012 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_2017 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire _T_2027 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_2030 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_2033 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_2036 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_2038 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_2040 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_2042 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_2044 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] + wire _T_2047 = _T_1881 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2048 = _T_1883 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2049 = _T_1885 & _T_1036; // @[Mux.scala 27:72] + wire _T_2050 = _T_1889 & _T_1042; // @[Mux.scala 27:72] + wire _T_2051 = _T_1895 & _T_1047; // @[Mux.scala 27:72] + wire _T_2052 = _T_1900 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2053 = _T_1902 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2054 = _T_1904 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2055 = _T_1906 & _T_1056; // @[Mux.scala 27:72] + wire _T_2056 = _T_1909 & _T_1059; // @[Mux.scala 27:72] + wire _T_2057 = _T_1912 & _T_1062; // @[Mux.scala 27:72] + wire _T_2058 = _T_1915 & _T_1065; // @[Mux.scala 27:72] + wire _T_2059 = _T_1918 & _T_1069; // @[Mux.scala 27:72] + wire _T_2060 = _T_1922 & _T_1074; // @[Mux.scala 27:72] + wire _T_2061 = _T_1927 & _T_1077; // @[Mux.scala 27:72] + wire _T_2062 = _T_1930 & _T_1080; // @[Mux.scala 27:72] + wire _T_2063 = _T_1933 & _T_1083; // @[Mux.scala 27:72] + wire _T_2064 = _T_1936 & _T_1086; // @[Mux.scala 27:72] + wire _T_2065 = _T_1939 & _T_1089; // @[Mux.scala 27:72] + wire _T_2066 = _T_1942 & _T_1092; // @[Mux.scala 27:72] + wire _T_2067 = _T_1945 & _T_1095; // @[Mux.scala 27:72] + wire _T_2068 = _T_1948 & _T_1098; // @[Mux.scala 27:72] + wire _T_2069 = _T_1951 & _T_1101; // @[Mux.scala 27:72] + wire _T_2070 = _T_1954 & _T_1106; // @[Mux.scala 27:72] + wire _T_2071 = _T_1959 & _T_1109; // @[Mux.scala 27:72] + wire _T_2072 = _T_1962 & _T_1112; // @[Mux.scala 27:72] + wire _T_2073 = _T_1965 & _T_1115; // @[Mux.scala 27:72] + wire _T_2074 = _T_1968 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2076 = _T_1972 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2077 = _T_1974 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2078 = _T_1976 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2079 = _T_1978 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2080 = _T_1980 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2081 = _T_1982 & _T_1133; // @[Mux.scala 27:72] + wire _T_2082 = _T_1986 & _T_1137; // @[Mux.scala 27:72] + wire _T_2083 = _T_1990 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2084 = _T_1992 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2085 = _T_1994 & _T_1145; // @[Mux.scala 27:72] + wire _T_2086 = _T_1998 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2087 = _T_2000 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2088 = _T_2002 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2089 = _T_2004 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2090 = _T_2006 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2091 = _T_2008 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2092 = _T_2010 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2093 = _T_2012 & _T_1164; // @[Mux.scala 27:72] + wire _T_2094 = _T_2017 & _T_1174; // @[Mux.scala 27:72] + wire _T_2095 = _T_2027 & _T_1177; // @[Mux.scala 27:72] + wire _T_2096 = _T_2030 & _T_1180; // @[Mux.scala 27:72] + wire _T_2097 = _T_2033 & _T_1183; // @[Mux.scala 27:72] + wire _T_2098 = _T_2036 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2099 = _T_2038 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2100 = _T_2040 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2101 = _T_2042 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2102 = _T_2044 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2103 = _T_1879 | _T_2047; // @[Mux.scala 27:72] wire _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72] wire _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72] wire _T_2106 = _T_2105 | _T_2050; // @[Mux.scala 27:72] @@ -52136,8 +52135,8 @@ module csr_tlu( wire _T_2127 = _T_2126 | _T_2071; // @[Mux.scala 27:72] wire _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72] wire _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72] - wire _T_2130 = _T_2129 | _T_2053; // @[Mux.scala 27:72] - wire _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72] + wire _T_2131 = _T_2130 | _T_2054; // @[Mux.scala 27:72] wire _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72] wire _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72] wire _T_2134 = _T_2133 | _T_2078; // @[Mux.scala 27:72] @@ -52164,187 +52163,187 @@ module csr_tlu( wire _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72] wire _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72] wire _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1877 & _T_2157; // @[dec_tlu_ctl.scala 2274:44] + wire _T_2158 = _T_2157 | _T_2102; // @[Mux.scala 27:72] + wire mhpmc_inc_r_3 = _T_1878 & _T_2158; // @[dec_tlu_ctl.scala 2274:44] reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2335:53] reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2336:53] reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2337:53] reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2338:53] reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2339:56] wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2342:67] - wire _T_2169 = ~_T_85; // @[dec_tlu_ctl.scala 2343:37] - wire [3:0] _T_2171 = _T_2169 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_2178 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2171 & _T_2178; // @[dec_tlu_ctl.scala 2343:86] - wire _T_2180 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2345:67] - wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2345:65] - wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2345:45] - wire _T_2185 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2346:67] - wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2346:65] - wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2346:45] - wire _T_2190 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2347:67] - wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[dec_tlu_ctl.scala 2347:65] - wire _T_2192 = ~_T_2191; // @[dec_tlu_ctl.scala 2347:45] - wire _T_2195 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2348:67] - wire _T_2196 = perfcnt_halted_d1 & _T_2195; // @[dec_tlu_ctl.scala 2348:65] - wire _T_2197 = ~_T_2196; // @[dec_tlu_ctl.scala 2348:45] - wire _T_2200 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2354:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2200; // @[dec_tlu_ctl.scala 2354:43] - wire _T_2201 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2355:23] - wire _T_2203 = _T_2201 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2355:39] - wire _T_2204 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2355:86] - wire mhpmc3_wr_en1 = _T_2203 & _T_2204; // @[dec_tlu_ctl.scala 2355:66] + wire _T_2170 = ~_T_85; // @[dec_tlu_ctl.scala 2343:37] + wire [3:0] _T_2172 = _T_2170 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2179 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2172 & _T_2179; // @[dec_tlu_ctl.scala 2343:86] + wire _T_2181 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2345:67] + wire _T_2182 = perfcnt_halted_d1 & _T_2181; // @[dec_tlu_ctl.scala 2345:65] + wire _T_2183 = ~_T_2182; // @[dec_tlu_ctl.scala 2345:45] + wire _T_2186 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2346:67] + wire _T_2187 = perfcnt_halted_d1 & _T_2186; // @[dec_tlu_ctl.scala 2346:65] + wire _T_2188 = ~_T_2187; // @[dec_tlu_ctl.scala 2346:45] + wire _T_2191 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2347:67] + wire _T_2192 = perfcnt_halted_d1 & _T_2191; // @[dec_tlu_ctl.scala 2347:65] + wire _T_2193 = ~_T_2192; // @[dec_tlu_ctl.scala 2347:45] + wire _T_2196 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2348:67] + wire _T_2197 = perfcnt_halted_d1 & _T_2196; // @[dec_tlu_ctl.scala 2348:65] + wire _T_2198 = ~_T_2197; // @[dec_tlu_ctl.scala 2348:45] + wire _T_2201 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2354:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2201; // @[dec_tlu_ctl.scala 2354:43] + wire _T_2202 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2355:23] + wire _T_2204 = _T_2202 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2355:39] + wire _T_2205 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2355:86] + wire mhpmc3_wr_en1 = _T_2204 & _T_2205; // @[dec_tlu_ctl.scala 2355:66] reg [31:0] mhpmc3h; // @[lib.scala 358:16] reg [31:0] mhpmc3; // @[lib.scala 358:16] - wire [63:0] _T_2207 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] - wire [63:0] _T_2208 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2207 + _T_2208; // @[dec_tlu_ctl.scala 2359:49] - wire _T_2216 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2364:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2216; // @[dec_tlu_ctl.scala 2364:44] - wire _T_2222 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2373:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2222; // @[dec_tlu_ctl.scala 2373:43] - wire _T_2225 = _T_2201 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2374:39] - wire _T_2226 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2374:86] - wire mhpmc4_wr_en1 = _T_2225 & _T_2226; // @[dec_tlu_ctl.scala 2374:66] + wire [63:0] _T_2208 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2209 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2208 + _T_2209; // @[dec_tlu_ctl.scala 2359:49] + wire _T_2217 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2364:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2217; // @[dec_tlu_ctl.scala 2364:44] + wire _T_2223 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2373:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2223; // @[dec_tlu_ctl.scala 2373:43] + wire _T_2226 = _T_2202 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2374:39] + wire _T_2227 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2374:86] + wire mhpmc4_wr_en1 = _T_2226 & _T_2227; // @[dec_tlu_ctl.scala 2374:66] reg [31:0] mhpmc4h; // @[lib.scala 358:16] reg [31:0] mhpmc4; // @[lib.scala 358:16] - wire [63:0] _T_2229 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] - wire [63:0] _T_2230 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2229 + _T_2230; // @[dec_tlu_ctl.scala 2379:49] - wire _T_2239 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2383:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2239; // @[dec_tlu_ctl.scala 2383:44] - wire _T_2245 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2392:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2245; // @[dec_tlu_ctl.scala 2392:43] - wire _T_2248 = _T_2201 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2393:39] - wire _T_2249 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2393:86] - wire mhpmc5_wr_en1 = _T_2248 & _T_2249; // @[dec_tlu_ctl.scala 2393:66] + wire [63:0] _T_2230 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2231 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2230 + _T_2231; // @[dec_tlu_ctl.scala 2379:49] + wire _T_2240 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2383:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2240; // @[dec_tlu_ctl.scala 2383:44] + wire _T_2246 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2392:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2246; // @[dec_tlu_ctl.scala 2392:43] + wire _T_2249 = _T_2202 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2393:39] + wire _T_2250 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2393:86] + wire mhpmc5_wr_en1 = _T_2249 & _T_2250; // @[dec_tlu_ctl.scala 2393:66] reg [31:0] mhpmc5h; // @[lib.scala 358:16] reg [31:0] mhpmc5; // @[lib.scala 358:16] - wire [63:0] _T_2252 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] - wire [63:0] _T_2253 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2252 + _T_2253; // @[dec_tlu_ctl.scala 2396:49] - wire _T_2261 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2401:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2261; // @[dec_tlu_ctl.scala 2401:44] - wire _T_2267 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2410:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2267; // @[dec_tlu_ctl.scala 2410:43] - wire _T_2270 = _T_2201 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2411:39] - wire _T_2271 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2411:86] - wire mhpmc6_wr_en1 = _T_2270 & _T_2271; // @[dec_tlu_ctl.scala 2411:66] + wire [63:0] _T_2253 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2254 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2253 + _T_2254; // @[dec_tlu_ctl.scala 2396:49] + wire _T_2262 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2401:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2262; // @[dec_tlu_ctl.scala 2401:44] + wire _T_2268 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2410:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2268; // @[dec_tlu_ctl.scala 2410:43] + wire _T_2271 = _T_2202 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2411:39] + wire _T_2272 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2411:86] + wire mhpmc6_wr_en1 = _T_2271 & _T_2272; // @[dec_tlu_ctl.scala 2411:66] reg [31:0] mhpmc6h; // @[lib.scala 358:16] reg [31:0] mhpmc6; // @[lib.scala 358:16] - wire [63:0] _T_2274 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] - wire [63:0] _T_2275 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2274 + _T_2275; // @[dec_tlu_ctl.scala 2414:49] - wire _T_2283 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2419:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2283; // @[dec_tlu_ctl.scala 2419:44] - wire _T_2289 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2430:56] - wire _T_2291 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2430:102] - wire _T_2292 = _T_2289 | _T_2291; // @[dec_tlu_ctl.scala 2430:71] - wire _T_2295 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2432:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2432:41] - wire _T_2299 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2439:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2439:41] - wire _T_2303 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2446:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2446:41] - wire _T_2307 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2453:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2307; // @[dec_tlu_ctl.scala 2453:41] - wire _T_2311 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2470:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2311; // @[dec_tlu_ctl.scala 2470:48] - wire _T_2323 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2485:51] - wire _T_2324 = _T_2323 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2485:78] - wire _T_2325 = _T_2324 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2485:104] - wire _T_2326 = _T_2325 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2485:130] - wire _T_2327 = _T_2326 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2486:32] - reg _T_2330; // @[dec_tlu_ctl.scala 2488:62] - wire _T_2331 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2489:91] - wire _T_2332 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2489:137] - wire _T_2333 = io_trigger_hit_r_d1 & _T_2332; // @[dec_tlu_ctl.scala 2489:135] - reg _T_2335; // @[dec_tlu_ctl.scala 2489:62] - reg [4:0] _T_2336; // @[dec_tlu_ctl.scala 2490:62] - reg _T_2337; // @[dec_tlu_ctl.scala 2491:62] - wire [31:0] _T_2343 = {io_core_id,4'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2352 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2357 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2370 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2383 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2395 = {io_mepc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2400 = {28'h0,mscause}; // @[Cat.scala 29:58] - wire [31:0] _T_2408 = {meivt,10'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2411 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2414 = {28'h0,meicurpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2417 = {28'h0,meicidpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2420 = {28'h0,meipt}; // @[Cat.scala 29:58] - wire [31:0] _T_2423 = {23'h0,mcgc}; // @[Cat.scala 29:58] - wire [31:0] _T_2426 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2430 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] - wire [31:0] _T_2432 = {io_dpc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2448 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2451 = {30'h0,mtsel}; // @[Cat.scala 29:58] - wire [31:0] _T_2480 = {26'h0,mfdht}; // @[Cat.scala 29:58] - wire [31:0] _T_2483 = {30'h0,mfdhs}; // @[Cat.scala 29:58] - wire [31:0] _T_2486 = {22'h0,mhpme3}; // @[Cat.scala 29:58] - wire [31:0] _T_2489 = {22'h0,mhpme4}; // @[Cat.scala 29:58] - wire [31:0] _T_2492 = {22'h0,mhpme5}; // @[Cat.scala 29:58] - wire [31:0] _T_2495 = {22'h0,mhpme6}; // @[Cat.scala 29:58] - wire [31:0] _T_2498 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire [31:0] _T_2501 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2504 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2505 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2506 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2507 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2508 = io_csr_pkt_csr_mhartid ? _T_2343 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2509 = io_csr_pkt_csr_mstatus ? _T_2352 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2510 = io_csr_pkt_csr_mtvec ? _T_2357 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2511 = io_csr_pkt_csr_mip ? _T_2370 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2512 = io_csr_pkt_csr_mie ? _T_2383 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2513 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2514 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2515 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2516 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2517 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2518 = io_csr_pkt_csr_mepc ? _T_2395 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2519 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2520 = io_csr_pkt_csr_mscause ? _T_2400 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2521 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2522 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2523 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2524 = io_csr_pkt_csr_meivt ? _T_2408 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2525 = io_csr_pkt_csr_meihap ? _T_2411 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2526 = io_csr_pkt_csr_meicurpl ? _T_2414 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2527 = io_csr_pkt_csr_meicidpl ? _T_2417 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2528 = io_csr_pkt_csr_meipt ? _T_2420 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2529 = io_csr_pkt_csr_mcgc ? _T_2423 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2530 = io_csr_pkt_csr_mfdc ? _T_2426 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2531 = io_csr_pkt_csr_dcsr ? _T_2430 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2532 = io_csr_pkt_csr_dpc ? _T_2432 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2533 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2535 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2536 = io_csr_pkt_csr_dicawics ? _T_2448 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2537 = io_csr_pkt_csr_mtsel ? _T_2451 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2538 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2540 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2541 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2542 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2551 = io_csr_pkt_csr_mfdht ? _T_2480 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2552 = io_csr_pkt_csr_mfdhs ? _T_2483 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2553 = io_csr_pkt_csr_mhpme3 ? _T_2486 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme4 ? _T_2489 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme5 ? _T_2492 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme6 ? _T_2495 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2557 = io_csr_pkt_csr_mcountinhibit ? _T_2498 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2558 = io_csr_pkt_csr_mpmc ? _T_2501 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2559 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2560 = _T_2504 | _T_2505; // @[Mux.scala 27:72] - wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] + wire [63:0] _T_2275 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2276 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2275 + _T_2276; // @[dec_tlu_ctl.scala 2414:49] + wire _T_2284 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2419:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2284; // @[dec_tlu_ctl.scala 2419:44] + wire _T_2290 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2430:56] + wire _T_2292 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2430:102] + wire _T_2293 = _T_2290 | _T_2292; // @[dec_tlu_ctl.scala 2430:71] + wire _T_2296 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2432:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2296; // @[dec_tlu_ctl.scala 2432:41] + wire _T_2300 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2439:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2300; // @[dec_tlu_ctl.scala 2439:41] + wire _T_2304 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2446:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2304; // @[dec_tlu_ctl.scala 2446:41] + wire _T_2308 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2453:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2308; // @[dec_tlu_ctl.scala 2453:41] + wire _T_2312 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2470:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2312; // @[dec_tlu_ctl.scala 2470:48] + wire _T_2324 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2485:51] + wire _T_2325 = _T_2324 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2485:78] + wire _T_2326 = _T_2325 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2485:104] + wire _T_2327 = _T_2326 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2485:130] + wire _T_2328 = _T_2327 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2486:32] + reg _T_2331; // @[dec_tlu_ctl.scala 2488:62] + wire _T_2332 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2489:91] + wire _T_2333 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2489:137] + wire _T_2334 = io_trigger_hit_r_d1 & _T_2333; // @[dec_tlu_ctl.scala 2489:135] + reg _T_2336; // @[dec_tlu_ctl.scala 2489:62] + reg [4:0] _T_2337; // @[dec_tlu_ctl.scala 2490:62] + reg _T_2338; // @[dec_tlu_ctl.scala 2491:62] + wire [31:0] _T_2344 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2353 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2358 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2371 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2384 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2396 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2401 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2409 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2412 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2415 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2418 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2421 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2424 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2427 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2431 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2433 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2449 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2452 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2481 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2484 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2487 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2490 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2493 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2496 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2499 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2502 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2505 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mhartid ? _T_2344 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_mstatus ? _T_2353 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_mtvec ? _T_2358 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mip ? _T_2371 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mie ? _T_2384 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_mepc ? _T_2396 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_mscause ? _T_2401 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_meivt ? _T_2409 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_meihap ? _T_2412 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_meicurpl ? _T_2415 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_meicidpl ? _T_2418 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_meipt ? _T_2421 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_mcgc ? _T_2424 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_mfdc ? _T_2427 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_dcsr ? _T_2431 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_dpc ? _T_2433 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_dicawics ? _T_2449 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mtsel ? _T_2452 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = io_csr_pkt_csr_mfdht ? _T_2481 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = io_csr_pkt_csr_mfdhs ? _T_2484 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme3 ? _T_2487 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme4 ? _T_2490 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme5 ? _T_2493 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = io_csr_pkt_csr_mhpme6 ? _T_2496 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = io_csr_pkt_csr_mcountinhibit ? _T_2499 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = io_csr_pkt_csr_mpmc ? _T_2502 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2561 = _T_2505 | _T_2506; // @[Mux.scala 27:72] wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] wire [31:0] _T_2564 = _T_2563 | _T_2509; // @[Mux.scala 27:72] @@ -52397,6 +52396,7 @@ module csr_tlu( wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72] wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72] wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72] + wire [31:0] _T_2614 = _T_2613 | _T_2559; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 352:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -52607,7 +52607,7 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_763,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2155:56] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_764,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2155:56] assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2158:41] assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2166:41] assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2167:41] @@ -52639,15 +52639,15 @@ module csr_tlu( assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2235:40] assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2236:40] assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2249:51] - assign io_dec_tlu_int_valid_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2491:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2335; // @[dec_tlu_ctl.scala 2489:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2330; // @[dec_tlu_ctl.scala 2488:30] + assign io_dec_tlu_int_valid_wb1 = _T_2338; // @[dec_tlu_ctl.scala 2491:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2489:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2331; // @[dec_tlu_ctl.scala 2488:30] assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2493:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2490:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2182; // @[dec_tlu_ctl.scala 2345:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2187; // @[dec_tlu_ctl.scala 2346:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2192; // @[dec_tlu_ctl.scala 2347:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2197; // @[dec_tlu_ctl.scala 2348:22] + assign io_dec_tlu_exc_cause_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2490:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2183; // @[dec_tlu_ctl.scala 2345:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2188; // @[dec_tlu_ctl.scala 2346:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2193; // @[dec_tlu_ctl.scala 2347:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2198; // @[dec_tlu_ctl.scala 2348:22] assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1718:31] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1719:31] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1721:31] @@ -52655,7 +52655,7 @@ module csr_tlu( assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1723:31] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1724:31] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1725:31] - assign io_dec_csr_rddata_d = _T_2613 | _T_2559; // @[dec_tlu_ctl.scala 2498:21] + assign io_dec_csr_rddata_d = _T_2614 | _T_2560; // @[dec_tlu_ctl.scala 2498:21] assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1768:39] assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1777:24] assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2006:19] @@ -52682,10 +52682,10 @@ module csr_tlu( assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1825:22] assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1933:16] assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2070:9] - assign io_mtdata1_t_0 = _T_872; // @[dec_tlu_ctl.scala 2226:39] - assign io_mtdata1_t_1 = _T_873; // @[dec_tlu_ctl.scala 2226:39] - assign io_mtdata1_t_2 = _T_874; // @[dec_tlu_ctl.scala 2226:39] - assign io_mtdata1_t_3 = _T_875; // @[dec_tlu_ctl.scala 2226:39] + assign io_mtdata1_t_0 = _T_873; // @[dec_tlu_ctl.scala 2226:39] + assign io_mtdata1_t_1 = _T_874; // @[dec_tlu_ctl.scala 2226:39] + assign io_mtdata1_t_2 = _T_875; // @[dec_tlu_ctl.scala 2226:39] + assign io_mtdata1_t_3 = _T_876; // @[dec_tlu_ctl.scala 2226:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 355:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] @@ -52753,16 +52753,16 @@ module csr_tlu( assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 355:17] assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_22_io_clk = clock; // @[lib.scala 354:18] - assign rvclkhdr_22_io_en = _T_971 & _T_807; // @[lib.scala 355:17] + assign rvclkhdr_22_io_en = _T_972 & _T_808; // @[lib.scala 355:17] assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_23_io_clk = clock; // @[lib.scala 354:18] - assign rvclkhdr_23_io_en = _T_980 & _T_816; // @[lib.scala 355:17] + assign rvclkhdr_23_io_en = _T_981 & _T_817; // @[lib.scala 355:17] assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_24_io_clk = clock; // @[lib.scala 354:18] - assign rvclkhdr_24_io_en = _T_989 & _T_825; // @[lib.scala 355:17] + assign rvclkhdr_24_io_en = _T_990 & _T_826; // @[lib.scala 355:17] assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_25_io_clk = clock; // @[lib.scala 354:18] - assign rvclkhdr_25_io_en = _T_998 & _T_834; // @[lib.scala 355:17] + assign rvclkhdr_25_io_en = _T_999 & _T_835; // @[lib.scala 355:17] assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_26_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 355:17] @@ -52789,7 +52789,7 @@ module csr_tlu( assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 355:17] assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] assign rvclkhdr_34_io_clk = clock; // @[lib.scala 328:17] - assign rvclkhdr_34_io_en = _T_2327 | io_clk_override; // @[lib.scala 329:16] + assign rvclkhdr_34_io_en = _T_2328 | io_clk_override; // @[lib.scala 329:16] assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -52909,7 +52909,7 @@ initial begin _RAND_40 = {1{`RANDOM}}; dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - _T_758 = _RAND_41[31:0]; + _T_759 = _RAND_41[6:0]; _RAND_42 = {1{`RANDOM}}; icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; @@ -52917,13 +52917,13 @@ initial begin _RAND_44 = {1{`RANDOM}}; mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_872 = _RAND_45[9:0]; + _T_873 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_873 = _RAND_46[9:0]; + _T_874 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_874 = _RAND_47[9:0]; + _T_875 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - _T_875 = _RAND_48[9:0]; + _T_876 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; @@ -52967,13 +52967,13 @@ initial begin _RAND_69 = {1{`RANDOM}}; mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2330 = _RAND_70[0:0]; + _T_2331 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2335 = _RAND_71[0:0]; + _T_2336 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2336 = _RAND_72[4:0]; + _T_2337 = _RAND_72[4:0]; _RAND_73 = {1{`RANDOM}}; - _T_2337 = _RAND_73[0:0]; + _T_2338 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -53099,7 +53099,7 @@ initial begin dicad0h = 32'h0; end if (reset) begin - _T_758 = 32'h0; + _T_759 = 7'h0; end if (reset) begin icache_rd_valid_f = 1'h0; @@ -53110,9 +53110,6 @@ initial begin if (reset) begin mtsel = 2'h0; end - if (reset) begin - _T_872 = 10'h0; - end if (reset) begin _T_873 = 10'h0; end @@ -53122,6 +53119,9 @@ initial begin if (reset) begin _T_875 = 10'h0; end + if (reset) begin + _T_876 = 10'h0; + end if (reset) begin mtdata2_t_0 = 32'h0; end @@ -53186,16 +53186,16 @@ initial begin mhpmc6 = 32'h0; end if (reset) begin - _T_2330 = 1'h0; + _T_2331 = 1'h0; end if (reset) begin - _T_2335 = 1'h0; + _T_2336 = 1'h0; end if (reset) begin - _T_2336 = 5'h0; + _T_2337 = 5'h0; end if (reset) begin - _T_2337 = 1'h0; + _T_2338 = 1'h0; end `endif // RANDOMIZE end // initial @@ -53526,12 +53526,12 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_758 <= 32'h0; - end else if (_T_756) begin + _T_759 <= 7'h0; + end else if (_T_757) begin if (_T_752) begin - _T_758 <= io_dec_csr_wrdata_r; + _T_759 <= io_dec_csr_wrdata_r[6:0]; end else begin - _T_758 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; + _T_759 <= io_ifu_ic_debug_rd_data[70:64]; end end end @@ -53539,14 +53539,14 @@ end // initial if (reset) begin icache_rd_valid_f <= 1'h0; end else begin - icache_rd_valid_f <= _T_768 & _T_770; + icache_rd_valid_f <= _T_769 & _T_771; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin icache_wr_valid_f <= 1'h0; end else begin - icache_wr_valid_f <= _T_663 & _T_773; + icache_wr_valid_f <= _T_663 & _T_774; end end always @(posedge io_csr_wr_clk or posedge reset) begin @@ -53556,40 +53556,40 @@ end // initial mtsel <= io_dec_csr_wrdata_r[1:0]; end end - always @(posedge io_active_clk or posedge reset) begin - if (reset) begin - _T_872 <= 10'h0; - end else if (wr_mtdata1_t_r_0) begin - _T_872 <= tdata_wrdata_r; - end else begin - _T_872 <= _T_843; - end - end always @(posedge io_active_clk or posedge reset) begin if (reset) begin _T_873 <= 10'h0; - end else if (wr_mtdata1_t_r_1) begin + end else if (wr_mtdata1_t_r_0) begin _T_873 <= tdata_wrdata_r; end else begin - _T_873 <= _T_852; + _T_873 <= _T_844; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin _T_874 <= 10'h0; - end else if (wr_mtdata1_t_r_2) begin + end else if (wr_mtdata1_t_r_1) begin _T_874 <= tdata_wrdata_r; end else begin - _T_874 <= _T_861; + _T_874 <= _T_853; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin _T_875 <= 10'h0; - end else if (wr_mtdata1_t_r_3) begin + end else if (wr_mtdata1_t_r_2) begin _T_875 <= tdata_wrdata_r; end else begin - _T_875 <= _T_870; + _T_875 <= _T_862; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_876 <= 10'h0; + end else if (wr_mtdata1_t_r_3) begin + _T_876 <= tdata_wrdata_r; + end else begin + _T_876 <= _T_871; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin @@ -53624,7 +53624,7 @@ end // initial if (reset) begin mhpme3 <= 10'h0; end else if (wr_mhpme3_r) begin - if (_T_2292) begin + if (_T_2293) begin mhpme3 <= 10'h204; end else begin mhpme3 <= io_dec_csr_wrdata_r[9:0]; @@ -53635,7 +53635,7 @@ end // initial if (reset) begin mhpme4 <= 10'h0; end else if (wr_mhpme4_r) begin - if (_T_2292) begin + if (_T_2293) begin mhpme4 <= 10'h204; end else begin mhpme4 <= io_dec_csr_wrdata_r[9:0]; @@ -53646,7 +53646,7 @@ end // initial if (reset) begin mhpme5 <= 10'h0; end else if (wr_mhpme5_r) begin - if (_T_2292) begin + if (_T_2293) begin mhpme5 <= 10'h204; end else begin mhpme5 <= io_dec_csr_wrdata_r[9:0]; @@ -53657,7 +53657,7 @@ end // initial if (reset) begin mhpme6 <= 10'h0; end else if (wr_mhpme6_r) begin - if (_T_2292) begin + if (_T_2293) begin mhpme6 <= 10'h204; end else begin mhpme6 <= io_dec_csr_wrdata_r[9:0]; @@ -53668,28 +53668,28 @@ end // initial if (reset) begin mhpmc_inc_r_d1_0 <= 1'h0; end else begin - mhpmc_inc_r_d1_0 <= _T_1025 & _T_1305; + mhpmc_inc_r_d1_0 <= _T_1026 & _T_1306; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_1 <= 1'h0; end else begin - mhpmc_inc_r_d1_1 <= _T_1309 & _T_1589; + mhpmc_inc_r_d1_1 <= _T_1310 & _T_1590; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_2 <= 1'h0; end else begin - mhpmc_inc_r_d1_2 <= _T_1593 & _T_1873; + mhpmc_inc_r_d1_2 <= _T_1594 & _T_1874; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_3 <= 1'h0; end else begin - mhpmc_inc_r_d1_3 <= _T_1877 & _T_2157; + mhpmc_inc_r_d1_3 <= _T_1878 & _T_2158; end end always @(posedge io_free_clk or posedge reset) begin @@ -53773,30 +53773,30 @@ end // initial end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2330 <= 1'h0; + _T_2331 <= 1'h0; end else begin - _T_2330 <= io_i0_valid_wb; + _T_2331 <= io_i0_valid_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2335 <= 1'h0; + _T_2336 <= 1'h0; end else begin - _T_2335 <= _T_2331 | _T_2333; + _T_2336 <= _T_2332 | _T_2334; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2336 <= 5'h0; + _T_2337 <= 5'h0; end else begin - _T_2336 <= io_exc_cause_wb; + _T_2337 <= io_exc_cause_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2337 <= 1'h0; + _T_2338 <= 1'h0; end else begin - _T_2337 <= io_interrupt_valid_r_d1; + _T_2338 <= io_interrupt_valid_r_d1; end end endmodule diff --git a/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala index 0f860ae7..84b4c230 100644 --- a/src/main/scala/dbg/dbg.scala +++ b/src/main/scala/dbg/dbg.scala @@ -235,7 +235,7 @@ class dbg extends Module with lib with RequireAsyncReset { val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted) val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0)) val command_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { - RegEnable(command_din, 0.U, command_wren) + rvdffe(command_din, command_wren,clock,io.scan_mode) } // dmcommand_reg val data0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h4".U) & (dbg_state === state_t.halted) @@ -244,7 +244,7 @@ class dbg extends Module with lib with RequireAsyncReset { val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata val data0_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) { - RegEnable(data0_din, 0.U, data0_reg_wren) + rvdffe(data0_din,data0_reg_wren,clock,io.scan_mode) } // dbg_data0_reg val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted)) @@ -450,6 +450,3 @@ class dbg extends Module with lib with RequireAsyncReset { io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type } -object dbg extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new dbg())) -} \ No newline at end of file diff --git a/src/main/scala/dec/dec_tlu_ctl.scala b/src/main/scala/dec/dec_tlu_ctl.scala index 9b7e2f7e..95f35604 100644 --- a/src/main/scala/dec/dec_tlu_ctl.scala +++ b/src/main/scala/dec/dec_tlu_ctl.scala @@ -2127,7 +2127,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm val dicad1_raw = WireInit(UInt(7.W),0.U) val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) - val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(70,64)) + val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r(6,0), io.ifu_ic_debug_rd_data(70,64)) dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} dicad1 := Cat(0.U(25.W), dicad1_raw) diff --git a/src/main/scala/dma_ctrl.scala b/src/main/scala/dma_ctrl.scala index 711fcd0c..58a8952c 100644 --- a/src/main/scala/dma_ctrl.scala +++ b/src/main/scala/dma_ctrl.scala @@ -294,7 +294,7 @@ class dma_ctrl extends Module with lib with RequireAsyncReset { num_fifo_vld := num_fifo_vld_tmp + num_fifo_vld_tmp2 - val fifo_full_spec = (num_fifo_vld_tmp2 >= DMA_BUF_DEPTH.asUInt()) + val fifo_full_spec = (num_fifo_vld >= DMA_BUF_DEPTH.asUInt()) val dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus) @@ -310,7 +310,11 @@ class dma_ctrl extends Module with lib with RequireAsyncReset { (io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)), (dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)), (dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)), - (dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)))) =/= 15.U)) | // Write byte enables not aligned for word store + (dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)), + (dma_mem_addr_int(2,0) === 4.U) -> (dma_mem_byteen(7,4)), + (dma_mem_addr_int(2,0) === 5.U) -> (dma_mem_byteen(7,5)), + (dma_mem_addr_int(2,0) === 6.U) -> (dma_mem_byteen(7,6)), + (dma_mem_addr_int(2,0) === 7.U) -> (dma_mem_byteen(7)))) =/= "hf".U)) | // Write byte enables not aligned for word store (io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store diff --git a/src/main/scala/ifu/ifu.scala b/src/main/scala/ifu/ifu.scala index 87944d78..3da88b43 100644 --- a/src/main/scala/ifu/ifu.scala +++ b/src/main/scala/ifu/ifu.scala @@ -13,16 +13,14 @@ class ifu extends Module with lib with RequireAsyncReset { val exu_flush_path_final = Input(UInt(31.W)) val free_clk = Input(Clock()) val active_clk = Input(Clock()) - val ifu_dec = new ifu_dec() - val exu_ifu = new exu_ifu() - val iccm = new iccm_mem() - val ic = new ic_mem() - // AXI Write Channel - val ifu = new axi_channels(IFU_BUS_TAG) + val ifu_dec = new ifu_dec() // IFU and DEC interconnects + val exu_ifu = new exu_ifu() // IFU and EXU interconnects + val iccm = new iccm_mem() // ICCM memory signals + val ic = new ic_mem() // I$ memory signals + val ifu = new axi_channels(IFU_BUS_TAG) // AXI Write Channel val ifu_bus_clk_en = Input(Bool()) - // DMA signals - val ifu_dma = new ifu_dma() - // ICCM + val ifu_dma = new ifu_dma() // DMA signals + // ICCM DMA signals val iccm_dma_ecc_error = Output(Bool()) val iccm_dma_rvalid = Output(Bool()) val iccm_dma_rdata = Output(UInt(64.W)) @@ -87,7 +85,8 @@ class ifu extends Module with lib with RequireAsyncReset { bp_ctl.io.exu_bp <> io.exu_ifu.exu_bp bp_ctl.io.exu_flush_final := io.exu_flush_final bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb - // mem-ctl wiring + + // mem-ctl Inputs mem_ctl.io.free_clk := io.free_clk mem_ctl.io.active_clk := io.active_clk mem_ctl.io.exu_flush_final := io.exu_flush_final @@ -110,6 +109,7 @@ class ifu extends Module with lib with RequireAsyncReset { mem_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb mem_ctl.io.scan_mode := io.scan_mode + // DMA to the ICCM io.iccm_dma_ecc_error := mem_ctl.io.iccm_dma_ecc_error io.iccm_dma_rvalid := mem_ctl.io.iccm_dma_rvalid io.iccm_dma_rdata := mem_ctl.io.iccm_dma_rdata diff --git a/src/main/scala/ifu/ifu_aln_ctl.scala b/src/main/scala/ifu/ifu_aln_ctl.scala index aab9d239..3ced6243 100644 --- a/src/main/scala/ifu/ifu_aln_ctl.scala +++ b/src/main/scala/ifu/ifu_aln_ctl.scala @@ -8,27 +8,27 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset { val io = IO(new Bundle{ val scan_mode = Input(Bool()) val active_clk = Input(Clock()) - val ifu_async_error_start = Input(Bool()) - val iccm_rd_ecc_double_err = Input(Bool()) - val ic_access_fault_f = Input(Bool()) - val ic_access_fault_type_f = Input(UInt(2.W)) - val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) - val ifu_bp_btb_target_f = Input(UInt(31.W)) - val ifu_bp_poffset_f = Input(UInt(12.W)) - val ifu_bp_hist0_f = Input(UInt(2.W)) - val ifu_bp_hist1_f = Input(UInt(2.W)) - val ifu_bp_pc4_f = Input(UInt(2.W)) - val ifu_bp_way_f = Input(UInt(2.W)) - val ifu_bp_valid_f = Input(UInt(2.W)) - val ifu_bp_ret_f = Input(UInt(2.W)) - val exu_flush_final = Input(Bool()) - val dec_aln = new dec_aln() - val ifu_fetch_data_f = Input(UInt(32.W)) - val ifu_fetch_val = Input(UInt(2.W)) - val ifu_fetch_pc = Input(UInt(31.W)) + val ifu_async_error_start = Input(Bool()) // Error coming from mem-ctl + val iccm_rd_ecc_double_err = Input(Bool()) // ICCM double error coming from mem-ctl + val ic_access_fault_f = Input(Bool()) // Access fault in I$ + val ic_access_fault_type_f = Input(UInt(2.W)) // Type of access fault occured + val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP + val ifu_bp_btb_target_f = Input(UInt(31.W)) // Target for the instruction enqueue in the FP + val ifu_bp_poffset_f = Input(UInt(12.W)) // Offset to the current PC for branch + val ifu_bp_hist0_f = Input(UInt(2.W)) // History to EXU + val ifu_bp_hist1_f = Input(UInt(2.W)) // History to EXU + val ifu_bp_pc4_f = Input(UInt(2.W)) // PC4 + val ifu_bp_way_f = Input(UInt(2.W)) // Way to help in miss prediction + val ifu_bp_valid_f = Input(UInt(2.W)) // Valid Branch prediction + val ifu_bp_ret_f = Input(UInt(2.W)) // BP ret + val exu_flush_final = Input(Bool()) // Miss prediction + val dec_aln = new dec_aln() // Data going to the dec from the ALN + val ifu_fetch_data_f = Input(UInt(32.W)) // PC of the current instruction in the FP + val ifu_fetch_val = Input(UInt(2.W)) // PC boundary i.e 'x' of 2 or 4 + val ifu_fetch_pc = Input(UInt(31.W)) // Current PC ///////////////////////////////////////////////// - val ifu_fb_consume1 = Output(Bool()) - val ifu_fb_consume2 = Output(Bool()) + val ifu_fb_consume1 = Output(Bool()) // FP used 1 + val ifu_fb_consume2 = Output(Bool()) // FP used 2 }) val MHI = 46+BHT_GHR_SIZE // 54 @@ -95,12 +95,16 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset { val shift_2B = WireInit(Bool(), 0.U) val f0_shift_2B = WireInit(Bool(), 0.U) + // Stall if there is an error in the instrucion error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final + // Flop the stall until flush error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)} + // Write Ptr of the FP val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)} + // Read Ptr of the FP val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)} - + // Fetch Instruction boundary val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)} val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)} val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)} @@ -108,30 +112,34 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset { val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)} val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)} val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)} - + // Instrution PC to the FP val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode) val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode) val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode) - + // Branch data to the FP brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode) brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode) brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode) - + // Miscalanious data to the FP including error's misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode) misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode) misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode) - + // Instruction in the FP q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode) q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode) q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode) + // Shift FP logic f2_wr_en := fetch_to_f2 f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B - + // FP read enable .. 3-bit for Implemenation of 1HMux val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U) + // FP write enable .. 3-bit for Implemenation of 1HMux qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid) + // Read Pointer calculation + // Next rdptr = # of consume + current ptr location (Rounding it from 2) rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U, (qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U, (qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U, @@ -140,6 +148,7 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset { (qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U, (!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr)) + // As there is only 1 enqueue so each time move by 1 wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U, (qwen(1) & !io.exu_flush_final).asBool -> 2.U, (qwen(2) & !io.exu_flush_final).asBool -> 0.U, @@ -166,7 +175,7 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset { val q0sel = Cat(q0ptr, !q0ptr) val q1sel = Cat(q1ptr, !q1ptr) - + // Misc data error, access-fault, type of fault, target, offset and ghr value misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f, io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f) @@ -192,10 +201,11 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset { val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE) val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0) + // Branch information brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1), io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0), io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0)) - + // Effective branch information val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0), qren(1).asBool->Cat(brdata2,brdata1), qren(2).asBool->Cat(brdata0,brdata2))) @@ -227,11 +237,13 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset { val consume_fb0 = !sf0val(0) & f0val(0) val consume_fb1 = !sf1val(0) & f1val(0) + // Depending on type of instruction and boundary determine how many FP to consume io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final io.ifu_fb_consume2 := consume_fb0 & consume_fb1 & !io.exu_flush_final ifvalid := io.ifu_fetch_val(0) + // Shift logic for each dequeue shift_f1_f0 := !sf0_valid & sf1_valid shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid @@ -285,6 +297,7 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset { q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16))) + // Alinging the data according to the boundary of PC val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0)))) alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U))) @@ -317,6 +330,7 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset { io.dec_aln.aln_dec.ifu_i0_cinst := aligndata(15,0) + // Instruction is compressed or not first4B := aligndata(1,0) === 3.U val first2B = ~first4B @@ -334,11 +348,12 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset { io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0))) val ifirst = aligndata - + // Expander from 16-bit to 32-bit val decompressed = Module(new ifu_compress_ctl()) io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout)) + // Hashing the PC val firstpc_hash = btb_addr_hash(f0pc) val secondpc_hash = btb_addr_hash(secondpc) diff --git a/src/main/scala/ifu/ifu_ifc_ctl.scala b/src/main/scala/ifu/ifu_ifc_ctl.scala index d029ec93..419ca64d 100644 --- a/src/main/scala/ifu/ifu_ifc_ctl.scala +++ b/src/main/scala/ifu/ifu_ifc_ctl.scala @@ -7,32 +7,32 @@ import chisel3.util._ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset { val io = IO(new Bundle{ - val exu_flush_final = Input(Bool()) - val exu_flush_path_final = Input(UInt(31.W)) + val exu_flush_final = Input(Bool()) // Miss Prediction for EXU + val exu_flush_path_final = Input(UInt(31.W)) // Replay PC val free_clk = Input(Clock()) val active_clk = Input(Clock()) val scan_mode = Input(Bool()) val ic_hit_f = Input(Bool()) - val ifu_ic_mb_empty = Input(Bool()) - val ifu_fb_consume1 = Input(Bool()) - val ifu_fb_consume2 = Input(Bool()) - val ifu_bp_hit_taken_f = Input(Bool()) - val ifu_bp_btb_target_f = Input(UInt(31.W)) - val ic_dma_active = Input(Bool()) + val ifu_ic_mb_empty = Input(Bool()) // Miss buffer of mem-ctl empty + val ifu_fb_consume1 = Input(Bool()) // Consume 1 fetch from FP + val ifu_fb_consume2 = Input(Bool()) // Consume 2 fetch from FP + val ifu_bp_hit_taken_f = Input(Bool()) // Branch taken from BP + val ifu_bp_btb_target_f = Input(UInt(31.W)) // Predicted PC + val ic_dma_active = Input(Bool()) // DMA for I$ val ic_write_stall = Input(Bool()) - val dec_ifc = new dec_ifc() - val dma_ifc = new dma_ifc() - val ifc_fetch_addr_f = Output(UInt(31.W)) - val ifc_fetch_addr_bf = Output(UInt(31.W)) + val dec_ifc = new dec_ifc() // DEC to IFC Bundle + val dma_ifc = new dma_ifc() // DMA to IFC Bundle + val ifc_fetch_addr_f = Output(UInt(31.W)) // Previous PC + val ifc_fetch_addr_bf = Output(UInt(31.W)) // Next PC - val ifc_fetch_req_f = Output(Bool()) + val ifc_fetch_req_f = Output(Bool()) // Fetch State - val ifc_fetch_uncacheable_bf = Output(Bool()) + val ifc_fetch_uncacheable_bf = Output(Bool()) // Fetch req for uncacheable val ifc_fetch_req_bf = Output(Bool()) val ifc_fetch_req_bf_raw = Output(Bool()) - val ifc_iccm_access_bf = Output(Bool()) - val ifc_region_acc_fault_bf = Output(Bool()) - val ifc_dma_access_ok = Output(Bool()) + val ifc_iccm_access_bf = Output(Bool()) // ICCM access + val ifc_region_acc_fault_bf = Output(Bool()) // Region access fault + val ifc_dma_access_ok = Output(Bool()) // DMA accesing }) val fetch_addr_bf = WireInit(UInt(31.W), init = 0.U) @@ -69,6 +69,7 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset { val sel_next_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f // TODO: Make an assertion for the 1H-Mux under here + // Next PC calculation io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC @@ -77,6 +78,7 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset { val address_upper = io.ifc_fetch_addr_f(30,1)+1.U fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0) + // Next PC to check from which boundary it is comming from fetch_addr_next := Cat(address_upper, fetch_addr_next_0) io.ifc_fetch_req_bf_raw := ~idle @@ -103,12 +105,14 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset { flush_fb := io.exu_flush_final + // Checking FP for PMU fb_right := ( io.ifu_fb_consume1 & !io.ifu_fb_consume2 & (!io.ifc_fetch_req_f | miss_f)) | (io.ifu_fb_consume2 & io.ifc_fetch_req_f) fb_right2 := (io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) fb_left := io.ifc_fetch_req_f & !(io.ifu_fb_consume1 | io.ifu_fb_consume2) & !miss_f + // Shifting the fb to remember the FP state fb_write_ns := Mux1H(Seq(flush_fb.asBool -> 1.U(4.W), (!flush_fb & fb_right).asBool -> Cat(0.U(1.W), fb_write_f(3,1)), (!flush_fb & fb_right2).asBool -> Cat(0.U(2.W), fb_write_f(3,2)), @@ -126,6 +130,7 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset { io.dec_ifc.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw & ((fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall)) + // Checking the next PC range and its region to access the ICCM or I$ val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE) rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U)) else (0.U, 0.U) diff --git a/src/main/scala/ifu/ifu_mem_ctl.scala b/src/main/scala/ifu/ifu_mem_ctl.scala index bd88f99f..c03d78db 100644 --- a/src/main/scala/ifu/ifu_mem_ctl.scala +++ b/src/main/scala/ifu/ifu_mem_ctl.scala @@ -54,26 +54,7 @@ class mem_ctl_io extends Bundle with lib{ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val io = IO(new mem_ctl_io) - io.ifu_axi.w.valid := 0.U - io.ifu_axi.w.bits.data := 0.U - io.ifu_axi.aw.bits.qos := 0.U - io.ifu_axi.aw.bits.addr := 0.U - io.ifu_axi.aw.bits.prot := 0.U - io.ifu_axi.aw.bits.len := 0.U - io.ifu_axi.ar.bits.lock := 0.U - io.ifu_axi.aw.bits.region := 0.U - io.ifu_axi.aw.bits.id := 0.U - io.ifu_axi.aw.valid := 0.U - io.ifu_axi.w.bits.strb := 0.U - io.ifu_axi.aw.bits.cache := 0.U - io.ifu_axi.ar.bits.qos := 0.U - io.ifu_axi.aw.bits.lock := 0.U - io.ifu_axi.b.ready := 0.U - io.ifu_axi.ar.bits.len := 0.U - io.ifu_axi.aw.bits.size := 0.U - io.ifu_axi.ar.bits.prot := 0.U - io.ifu_axi.aw.bits.burst := 0.U - io.ifu_axi.w.bits.last := 0.U + val idle_C :: crit_byp_ok_C :: hit_u_miss_C :: miss_wait_C :: crit_wrd_rdy_C :: scnd_miss_C :: stream_C :: stall_scnd_miss_C :: Nil = Enum(8) val err_stop_idle_C :: err_fetch1_C :: err_fetch2_C :: err_stop_fetch_C :: Nil = Enum(4) val err_idle_C :: ic_wff_C :: ecc_wff_C :: ecc_cor_C :: dma_sb_err_C :: Nil = Enum(5) @@ -104,6 +85,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val ic_miss_under_miss_f = WireInit(Bool(), false.B) val ic_ignore_2nd_miss_f = WireInit(Bool(), false.B) val ic_debug_rd_en_ff = WireInit(Bool(), false.B) + val debug_data_clk = rvclkhdr(clock, ic_debug_rd_en_ff, io.scan_mode) val flush_final_f = withClock(io.free_clk){RegNext(io.exu_flush_final, 0.U)} val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req @@ -120,11 +102,11 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val ifu_bp_hit_taken_q_f = io.ifu_bp_hit_taken_f & io.ic_hit_f ///////////////////////////////// MISS FSM ///////////////////////////////// switch(miss_state){ - is (idle_C){ + is (idle_C){ // Idle meaning there is not pending miss miss_nxtstate := Mux((ic_act_miss_f & !io.exu_flush_final).asBool, crit_byp_ok_C, hit_u_miss_C) miss_state_en := ic_act_miss_f & !io.dec_mem_ctrl.dec_tlu_force_halt} - is (crit_byp_ok_C){ + is (crit_byp_ok_C){ // Miss started meaning each beat is checked if, it is the critical word miss_nxtstate := Mux((io.dec_mem_ctrl.dec_tlu_force_halt | (ic_byp_hit_f & (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) & uncacheable_miss_ff)).asBool, idle_C, Mux((ic_byp_hit_f & !last_data_recieved_ff & uncacheable_miss_ff).asBool, miss_wait_C, Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & uncacheable_miss_ff).asBool, crit_wrd_rdy_C, @@ -135,35 +117,36 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C)))))))) miss_state_en := io.dec_mem_ctrl.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff) } - is (crit_wrd_rdy_C){ + is (crit_wrd_rdy_C){ // Critical word hit but not complete, its going to be available in next cycle miss_nxtstate := idle_C miss_state_en := io.exu_flush_final | flush_final_f | ic_byp_hit_f | io.dec_mem_ctrl.dec_tlu_force_halt } - is (stream_C){ + is (stream_C){ // The miss was a miss of uncacheable range miss_nxtstate := Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f)&(!(bus_ifu_wr_en_ff & last_beat)) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C) miss_state_en := io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f | (bus_ifu_wr_en_ff & last_beat) | io.dec_mem_ctrl.dec_tlu_force_halt } - is (miss_wait_C){ + is (miss_wait_C){ // Critial word hit but the miss is not complete miss_nxtstate := Mux((io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C) miss_state_en := io.exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | io.dec_mem_ctrl.dec_tlu_force_halt } - is (hit_u_miss_C){ + is (hit_u_miss_C){ // The critical word was a hit taken, or miss due to a miss predicted pc occured miss_nxtstate := Mux((ic_miss_under_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, scnd_miss_C, Mux((ic_ignore_2nd_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_mem_ctrl.dec_tlu_force_halt).asBool, stall_scnd_miss_C, idle_C)) miss_state_en := (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | io.dec_mem_ctrl.dec_tlu_force_halt } - is (scnd_miss_C){ + is (scnd_miss_C){ // Miss of the different pc occured miss_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final, Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), crit_byp_ok_C)) miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_force_halt } - is (stall_scnd_miss_C){ + is (stall_scnd_miss_C){ // Miss from the same pc occured miss_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final, Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), idle_C)) miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_force_halt } } miss_state := withClock(io.free_clk){RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)} + // Calculation all the relevant signals for the miss FSM val crit_byp_hit_f = WireInit(Bool(), 0.U) val way_status_mb_scnd_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) @@ -262,6 +245,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { sel_mb_addr_ff := withClock(io.free_clk){RegNext(sel_mb_addr, 0.U)} val ifu_bus_rdata_ff = WireInit(UInt(64.W), 0.U) val ic_miss_buff_half = WireInit(UInt(64.W), 0.U) + + // Ecc of the read data from the AXI val ic_wr_ecc = rvecc_encode_64(ifu_bus_rdata_ff) val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half) val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U) @@ -271,6 +256,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { io.dec_mem_ctrl.ifu_ic_error_start := ((if(ICACHE_ECC)io.ic.eccerr.orR()else io.ic.parerr.orR()) & ic_act_hit_f) | ic_rd_parity_final_err val ic_debug_tag_val_rd_out = WireInit(Bool(), 0.U) val ic_debug_ict_array_sel_ff = WireInit(Bool(), 0.U) + val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ic.tag_debug_rd_data(25,21),0.U(32.W),io.ic.tag_debug_rd_data(20,0), 0.U((7-ICACHE_STATUS_BITS).W), way_status, 0.U(3.W),ic_debug_tag_val_rd_out) else Cat(0.U(6.W),io.ic.tag_debug_rd_data(21),0.U(32.W),io.ic.tag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) , io.ic.debug_rd_data) @@ -395,6 +381,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { ic_miss_buff_half := Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,1.U)===i.U).asBool->ic_miss_buff_data(i))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,0.U)===i.U).asBool->ic_miss_buff_data(i)))) + // Parity check for the I$ logic ic_rd_parity_final_err := io.ic.tag_perr & sel_ic_data & !(ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f) val ifu_ic_rw_int_addr_ff = WireInit(UInt((ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO+1).W), 0.U) @@ -408,7 +395,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { io.iccm.buf_correct_ecc := iccm_correct_ecc & !dma_sb_err_state_ff dma_sb_err_state_ff := withClock(io.active_clk){RegNext(dma_sb_err_state, false.B)} - ///////////////////////////////// ERROR FSM ///////////////////////////////// + ///////////////////////////////// PARITY ERROR FSM ///////////////////////////////// val perr_nxtstate = WireInit(UInt(3.W), 0.U) val perr_state_en = WireInit(Bool(), false.B) val iccm_error_start = WireInit(Bool(), false.B) @@ -487,6 +474,26 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val bus_cmd_req_in = (ic_act_miss_f | bus_cmd_req_hold) & !bus_cmd_sent & !io.dec_mem_ctrl.dec_tlu_force_halt bus_cmd_req_hold := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)} // AXI Read-Channel + io.ifu_axi.w.valid := 0.U + io.ifu_axi.w.bits.data := 0.U + io.ifu_axi.aw.bits.qos := 0.U + io.ifu_axi.aw.bits.addr := 0.U + io.ifu_axi.aw.bits.prot := 0.U + io.ifu_axi.aw.bits.len := 0.U + io.ifu_axi.ar.bits.lock := 0.U + io.ifu_axi.aw.bits.region := 0.U + io.ifu_axi.aw.bits.id := 0.U + io.ifu_axi.aw.valid := 0.U + io.ifu_axi.w.bits.strb := 0.U + io.ifu_axi.aw.bits.cache := 0.U + io.ifu_axi.ar.bits.qos := 0.U + io.ifu_axi.aw.bits.lock := 0.U + io.ifu_axi.b.ready := 0.U + io.ifu_axi.ar.bits.len := 0.U + io.ifu_axi.aw.bits.size := 0.U + io.ifu_axi.ar.bits.prot := 0.U + io.ifu_axi.aw.bits.burst := 0.U + io.ifu_axi.w.bits.last := 0.U io.ifu_axi.ar.valid := ifu_bus_cmd_valid io.ifu_axi.ar.bits.id := bus_rd_addr_count & Fill(IFU_BUS_TAG, ifu_bus_cmd_valid) io.ifu_axi.ar.bits.addr := Cat(ifu_ic_req_addr_f, 0.U(3.W)) & Fill(32, ifu_bus_cmd_valid) @@ -516,6 +523,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val ifu_bus_arready = ifu_bus_arready_unq & bus_ifu_bus_clk_en val ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff val ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff + // Write signals to write to the bus bus_cmd_sent := ifu_bus_arvalid & ifu_bus_arready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt val bus_last_data_beat = WireInit(Bool(), false.B) val bus_inc_data_beat_cnt = bus_ifu_wr_en_ff & !bus_last_data_beat & !io.dec_mem_ctrl.dec_tlu_force_halt @@ -594,7 +602,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val ic_fetch_val_int_f = Cat(0.U(2.W), io.ic_fetch_val_f) val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0) val iccm_rdmux_data = io.iccm.rd_data_ecc - + // ICCM ECC Check logic val iccm_ecc_word_enable = (0 until 2).map(i=>((ic_fetch_val_shift_right((2*i+1),(2*i)).orR & !io.exu_flush_final & sel_iccm_data) | iccm_dma_rvalid_in) & !io.dec_mem_ctrl.dec_tlu_core_ecc_disable).reverse.reduce(Cat(_,_)) val ecc_decoded = (0 until 2).map(i=>rvecc_decode(iccm_ecc_word_enable(i), iccm_rdmux_data((39*i+31),(39*i)), iccm_rdmux_data((39*i+38),(39*i+32)), 0.U)) val iccm_corrected_ecc = Wire(Vec(2, UInt(7.W))) @@ -628,7 +636,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { io.ic.wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes) io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff))) reset_all_tags := withClock(io.active_clk){RegNext(io.dec_mem_ctrl.dec_tlu_fence_i_wb, false.B)} - + // I$ status and P-LRU val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss val ifu_status_wr_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) @@ -688,8 +696,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j => Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_)) - // Making a sudo LRU - // val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, Bool())) + // Making sudo LRU val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) if (ICACHE_NUM_WAYS == 4) { replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | @@ -762,6 +769,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { ic_debug_ict_array_sel_ff := withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)} ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic.debug_rd_en, false.B)} io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegNext(ic_debug_rd_en_ff, 0.U)} + // Memory protection each access enable with its Mask val ifc_region_acc_okay = !(Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR()) | (INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) | (INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) | diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala index 662fd32d..46baf82a 100644 --- a/src/main/scala/include/bundle.scala +++ b/src/main/scala/include/bundle.scala @@ -58,6 +58,8 @@ class ahb_out extends Bundle{ val htrans = Output(UInt(2.W)) val hwrite = Output(Bool()) // ahb bus write val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data + + } class ahb_channel extends Bundle{ val in = Input(new ahb_in) diff --git a/target/scala-2.12/classes/dbg/dbg$.class b/target/scala-2.12/classes/dbg/dbg$.class deleted file mode 100644 index 2f69190b..00000000 Binary files a/target/scala-2.12/classes/dbg/dbg$.class and /dev/null differ diff --git a/target/scala-2.12/classes/dbg/dbg$delayedInit$body.class b/target/scala-2.12/classes/dbg/dbg$delayedInit$body.class deleted file mode 100644 index 6d36f6fc..00000000 Binary files a/target/scala-2.12/classes/dbg/dbg$delayedInit$body.class and /dev/null differ diff --git a/target/scala-2.12/classes/dbg/dbg.class b/target/scala-2.12/classes/dbg/dbg.class index a3be25ad..0c3e7c94 100644 Binary files a/target/scala-2.12/classes/dbg/dbg.class and b/target/scala-2.12/classes/dbg/dbg.class differ diff --git a/target/scala-2.12/classes/dec/csr_tlu.class b/target/scala-2.12/classes/dec/csr_tlu.class index 77bbfb42..4334ea66 100644 Binary files a/target/scala-2.12/classes/dec/csr_tlu.class and b/target/scala-2.12/classes/dec/csr_tlu.class differ diff --git a/target/scala-2.12/classes/dma_ctrl.class b/target/scala-2.12/classes/dma_ctrl.class index 0eb8e37f..423241d0 100644 Binary files a/target/scala-2.12/classes/dma_ctrl.class and b/target/scala-2.12/classes/dma_ctrl.class differ diff --git a/target/scala-2.12/classes/dma_main$.class b/target/scala-2.12/classes/dma_main$.class index 625b9b87..ab62a892 100644 Binary files a/target/scala-2.12/classes/dma_main$.class and b/target/scala-2.12/classes/dma_main$.class differ diff --git a/target/scala-2.12/classes/dma_main$delayedInit$body.class b/target/scala-2.12/classes/dma_main$delayedInit$body.class index db6374b3..3d661916 100644 Binary files a/target/scala-2.12/classes/dma_main$delayedInit$body.class and b/target/scala-2.12/classes/dma_main$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/ifu/ifu$$anon$1.class b/target/scala-2.12/classes/ifu/ifu$$anon$1.class index 43a2c860..2ff63f8a 100644 Binary files a/target/scala-2.12/classes/ifu/ifu$$anon$1.class and b/target/scala-2.12/classes/ifu/ifu$$anon$1.class differ diff --git a/target/scala-2.12/classes/ifu/ifu.class b/target/scala-2.12/classes/ifu/ifu.class index 129fee89..13c420f7 100644 Binary files a/target/scala-2.12/classes/ifu/ifu.class and b/target/scala-2.12/classes/ifu/ifu.class differ diff --git a/target/scala-2.12/classes/ifu/ifu_aln_ctl.class b/target/scala-2.12/classes/ifu/ifu_aln_ctl.class index 3a7c4990..35029f57 100644 Binary files a/target/scala-2.12/classes/ifu/ifu_aln_ctl.class and b/target/scala-2.12/classes/ifu/ifu_aln_ctl.class differ diff --git a/target/scala-2.12/classes/ifu/ifu_ifc_ctl.class b/target/scala-2.12/classes/ifu/ifu_ifc_ctl.class index 02169139..48adab1e 100644 Binary files a/target/scala-2.12/classes/ifu/ifu_ifc_ctl.class and b/target/scala-2.12/classes/ifu/ifu_ifc_ctl.class differ diff --git a/target/scala-2.12/classes/ifu/ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/ifu_mem_ctl.class index c729a904..39f8c1ec 100644 Binary files a/target/scala-2.12/classes/ifu/ifu_mem_ctl.class and b/target/scala-2.12/classes/ifu/ifu_mem_ctl.class differ diff --git a/target/scala-2.12/classes/include/ahb_channel.class b/target/scala-2.12/classes/include/ahb_channel.class index 1a78dfd0..4a792968 100644 Binary files a/target/scala-2.12/classes/include/ahb_channel.class and b/target/scala-2.12/classes/include/ahb_channel.class differ diff --git a/target/scala-2.12/classes/include/aln_dec.class b/target/scala-2.12/classes/include/aln_dec.class index a320387a..93d0bb31 100644 Binary files a/target/scala-2.12/classes/include/aln_dec.class and b/target/scala-2.12/classes/include/aln_dec.class differ diff --git a/target/scala-2.12/classes/include/aln_ib.class b/target/scala-2.12/classes/include/aln_ib.class index 9d3a8a2a..83df84b4 100644 Binary files a/target/scala-2.12/classes/include/aln_ib.class and b/target/scala-2.12/classes/include/aln_ib.class differ diff --git a/target/scala-2.12/classes/include/alu_pkt_t.class b/target/scala-2.12/classes/include/alu_pkt_t.class index 36b9e9c2..819ef249 100644 Binary files a/target/scala-2.12/classes/include/alu_pkt_t.class and b/target/scala-2.12/classes/include/alu_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/axi_channels$.class b/target/scala-2.12/classes/include/axi_channels$.class index eff83ce3..82a46272 100644 Binary files a/target/scala-2.12/classes/include/axi_channels$.class and b/target/scala-2.12/classes/include/axi_channels$.class differ diff --git a/target/scala-2.12/classes/include/axi_channels.class b/target/scala-2.12/classes/include/axi_channels.class index 2a1d0d6d..49410ded 100644 Binary files a/target/scala-2.12/classes/include/axi_channels.class and b/target/scala-2.12/classes/include/axi_channels.class differ diff --git a/target/scala-2.12/classes/include/br_pkt_t.class b/target/scala-2.12/classes/include/br_pkt_t.class index 366c583d..7274cd6b 100644 Binary files a/target/scala-2.12/classes/include/br_pkt_t.class and b/target/scala-2.12/classes/include/br_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/br_tlu_pkt_t.class b/target/scala-2.12/classes/include/br_tlu_pkt_t.class index 6101bed8..e13d4cac 100644 Binary files a/target/scala-2.12/classes/include/br_tlu_pkt_t.class and b/target/scala-2.12/classes/include/br_tlu_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/cache_debug_pkt_t.class b/target/scala-2.12/classes/include/cache_debug_pkt_t.class index 9cab16ff..eca5e2e3 100644 Binary files a/target/scala-2.12/classes/include/cache_debug_pkt_t.class and b/target/scala-2.12/classes/include/cache_debug_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class b/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class index 952e7390..ebf563fd 100644 Binary files a/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class and b/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/class_pkt_t.class b/target/scala-2.12/classes/include/class_pkt_t.class index 9072a39c..3bbba0eb 100644 Binary files a/target/scala-2.12/classes/include/class_pkt_t.class and b/target/scala-2.12/classes/include/class_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/dbg_dctl.class b/target/scala-2.12/classes/include/dbg_dctl.class index ab0e4c9c..d2c23713 100644 Binary files a/target/scala-2.12/classes/include/dbg_dctl.class and b/target/scala-2.12/classes/include/dbg_dctl.class differ diff --git a/target/scala-2.12/classes/include/dbg_ib.class b/target/scala-2.12/classes/include/dbg_ib.class index 5f6d07cf..723b2fcd 100644 Binary files a/target/scala-2.12/classes/include/dbg_ib.class and b/target/scala-2.12/classes/include/dbg_ib.class differ diff --git a/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class b/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class index 17f7a7bb..9cdc8fec 100644 Binary files a/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class and b/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/dctl_busbuff.class b/target/scala-2.12/classes/include/dctl_busbuff.class index 00c7a661..d0aaad16 100644 Binary files a/target/scala-2.12/classes/include/dctl_busbuff.class and b/target/scala-2.12/classes/include/dctl_busbuff.class differ diff --git a/target/scala-2.12/classes/include/dec_aln.class b/target/scala-2.12/classes/include/dec_aln.class index a40f81cc..da7bd881 100644 Binary files a/target/scala-2.12/classes/include/dec_aln.class and b/target/scala-2.12/classes/include/dec_aln.class differ diff --git a/target/scala-2.12/classes/include/dec_alu.class b/target/scala-2.12/classes/include/dec_alu.class index e05732bc..fe721751 100644 Binary files a/target/scala-2.12/classes/include/dec_alu.class and b/target/scala-2.12/classes/include/dec_alu.class differ diff --git a/target/scala-2.12/classes/include/dec_dbg.class b/target/scala-2.12/classes/include/dec_dbg.class index 588d5ca2..ab707e90 100644 Binary files a/target/scala-2.12/classes/include/dec_dbg.class and b/target/scala-2.12/classes/include/dec_dbg.class differ diff --git a/target/scala-2.12/classes/include/dec_div.class b/target/scala-2.12/classes/include/dec_div.class index 921c00ed..1e254aa5 100644 Binary files a/target/scala-2.12/classes/include/dec_div.class and b/target/scala-2.12/classes/include/dec_div.class differ diff --git a/target/scala-2.12/classes/include/dec_exu.class b/target/scala-2.12/classes/include/dec_exu.class index 8927018e..545e3848 100644 Binary files a/target/scala-2.12/classes/include/dec_exu.class and b/target/scala-2.12/classes/include/dec_exu.class differ diff --git a/target/scala-2.12/classes/include/dec_mem_ctrl.class b/target/scala-2.12/classes/include/dec_mem_ctrl.class index 1e5cc3fc..c11d0394 100644 Binary files a/target/scala-2.12/classes/include/dec_mem_ctrl.class and b/target/scala-2.12/classes/include/dec_mem_ctrl.class differ diff --git a/target/scala-2.12/classes/include/dec_pkt_t.class b/target/scala-2.12/classes/include/dec_pkt_t.class index 4b0db307..536011d7 100644 Binary files a/target/scala-2.12/classes/include/dec_pkt_t.class and b/target/scala-2.12/classes/include/dec_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class b/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class index eed2f312..1bf57700 100644 Binary files a/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class and b/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class differ diff --git a/target/scala-2.12/classes/include/decode_exu.class b/target/scala-2.12/classes/include/decode_exu.class index 1c4f75eb..4e3abdd0 100644 Binary files a/target/scala-2.12/classes/include/decode_exu.class and b/target/scala-2.12/classes/include/decode_exu.class differ diff --git a/target/scala-2.12/classes/include/dest_pkt_t.class b/target/scala-2.12/classes/include/dest_pkt_t.class index b783e7e1..d3811f23 100644 Binary files a/target/scala-2.12/classes/include/dest_pkt_t.class and b/target/scala-2.12/classes/include/dest_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/div_pkt_t.class b/target/scala-2.12/classes/include/div_pkt_t.class index 4f926174..d168cf9d 100644 Binary files a/target/scala-2.12/classes/include/div_pkt_t.class and b/target/scala-2.12/classes/include/div_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/dma_dccm_ctl.class b/target/scala-2.12/classes/include/dma_dccm_ctl.class index 5238a4d6..78a0f31f 100644 Binary files a/target/scala-2.12/classes/include/dma_dccm_ctl.class and b/target/scala-2.12/classes/include/dma_dccm_ctl.class differ diff --git a/target/scala-2.12/classes/include/dma_ifc.class b/target/scala-2.12/classes/include/dma_ifc.class index 54ba3874..905dc456 100644 Binary files a/target/scala-2.12/classes/include/dma_ifc.class and b/target/scala-2.12/classes/include/dma_ifc.class differ diff --git a/target/scala-2.12/classes/include/dma_lsc_ctl.class b/target/scala-2.12/classes/include/dma_lsc_ctl.class index 97ec79e7..801f5017 100644 Binary files a/target/scala-2.12/classes/include/dma_lsc_ctl.class and b/target/scala-2.12/classes/include/dma_lsc_ctl.class differ diff --git a/target/scala-2.12/classes/include/dma_mem_ctl.class b/target/scala-2.12/classes/include/dma_mem_ctl.class index 8aadc72f..6f4ab11b 100644 Binary files a/target/scala-2.12/classes/include/dma_mem_ctl.class and b/target/scala-2.12/classes/include/dma_mem_ctl.class differ diff --git a/target/scala-2.12/classes/include/exu_bp.class b/target/scala-2.12/classes/include/exu_bp.class index 57ede8c0..84895175 100644 Binary files a/target/scala-2.12/classes/include/exu_bp.class and b/target/scala-2.12/classes/include/exu_bp.class differ diff --git a/target/scala-2.12/classes/include/exu_ifu.class b/target/scala-2.12/classes/include/exu_ifu.class index e9bfbcad..a0a1c151 100644 Binary files a/target/scala-2.12/classes/include/exu_ifu.class and b/target/scala-2.12/classes/include/exu_ifu.class differ diff --git a/target/scala-2.12/classes/include/gpr_exu.class b/target/scala-2.12/classes/include/gpr_exu.class index b7ee6b2f..345f00c1 100644 Binary files a/target/scala-2.12/classes/include/gpr_exu.class and b/target/scala-2.12/classes/include/gpr_exu.class differ diff --git a/target/scala-2.12/classes/include/ib_exu.class b/target/scala-2.12/classes/include/ib_exu.class index ac04b362..8eb705e7 100644 Binary files a/target/scala-2.12/classes/include/ib_exu.class and b/target/scala-2.12/classes/include/ib_exu.class differ diff --git a/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class b/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class index 17d2546d..93bb6eb7 100644 Binary files a/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class and b/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/ic_mem.class b/target/scala-2.12/classes/include/ic_mem.class index 28187f79..5eab63f1 100644 Binary files a/target/scala-2.12/classes/include/ic_mem.class and b/target/scala-2.12/classes/include/ic_mem.class differ diff --git a/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class b/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class index 0a7fb3a1..3c2e9349 100644 Binary files a/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class and b/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/iccm_mem.class b/target/scala-2.12/classes/include/iccm_mem.class index 8795d616..38e26612 100644 Binary files a/target/scala-2.12/classes/include/iccm_mem.class and b/target/scala-2.12/classes/include/iccm_mem.class differ diff --git a/target/scala-2.12/classes/include/ifu_dec.class b/target/scala-2.12/classes/include/ifu_dec.class index 6e6b7a01..c898de5e 100644 Binary files a/target/scala-2.12/classes/include/ifu_dec.class and b/target/scala-2.12/classes/include/ifu_dec.class differ diff --git a/target/scala-2.12/classes/include/ifu_dma.class b/target/scala-2.12/classes/include/ifu_dma.class index a79d8c1b..55dc5057 100644 Binary files a/target/scala-2.12/classes/include/ifu_dma.class and b/target/scala-2.12/classes/include/ifu_dma.class differ diff --git a/target/scala-2.12/classes/include/inst_pkt_t$.class b/target/scala-2.12/classes/include/inst_pkt_t$.class index 66ab955f..b54b948a 100644 Binary files a/target/scala-2.12/classes/include/inst_pkt_t$.class and b/target/scala-2.12/classes/include/inst_pkt_t$.class differ diff --git a/target/scala-2.12/classes/include/load_cam_pkt_t.class b/target/scala-2.12/classes/include/load_cam_pkt_t.class index ec2bbdf9..bf829468 100644 Binary files a/target/scala-2.12/classes/include/load_cam_pkt_t.class and b/target/scala-2.12/classes/include/load_cam_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/lsu_dec.class b/target/scala-2.12/classes/include/lsu_dec.class index 8b22202f..3f72b800 100644 Binary files a/target/scala-2.12/classes/include/lsu_dec.class and b/target/scala-2.12/classes/include/lsu_dec.class differ diff --git a/target/scala-2.12/classes/include/lsu_dma.class b/target/scala-2.12/classes/include/lsu_dma.class index d000e77b..277697ef 100644 Binary files a/target/scala-2.12/classes/include/lsu_dma.class and b/target/scala-2.12/classes/include/lsu_dma.class differ diff --git a/target/scala-2.12/classes/include/lsu_error_pkt_t.class b/target/scala-2.12/classes/include/lsu_error_pkt_t.class index e8008f8a..65165687 100644 Binary files a/target/scala-2.12/classes/include/lsu_error_pkt_t.class and b/target/scala-2.12/classes/include/lsu_error_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/lsu_exu.class b/target/scala-2.12/classes/include/lsu_exu.class index 5baae778..0c4a82ec 100644 Binary files a/target/scala-2.12/classes/include/lsu_exu.class and b/target/scala-2.12/classes/include/lsu_exu.class differ diff --git a/target/scala-2.12/classes/include/lsu_pic.class b/target/scala-2.12/classes/include/lsu_pic.class index 92b9c226..916f07ec 100644 Binary files a/target/scala-2.12/classes/include/lsu_pic.class and b/target/scala-2.12/classes/include/lsu_pic.class differ diff --git a/target/scala-2.12/classes/include/lsu_pkt_t.class b/target/scala-2.12/classes/include/lsu_pkt_t.class index 38f0a888..83755719 100644 Binary files a/target/scala-2.12/classes/include/lsu_pkt_t.class and b/target/scala-2.12/classes/include/lsu_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/lsu_tlu.class b/target/scala-2.12/classes/include/lsu_tlu.class index 9f8a4720..0f8a445e 100644 Binary files a/target/scala-2.12/classes/include/lsu_tlu.class and b/target/scala-2.12/classes/include/lsu_tlu.class differ diff --git a/target/scala-2.12/classes/include/mul_pkt_t.class b/target/scala-2.12/classes/include/mul_pkt_t.class index dd5462d6..c8a9971f 100644 Binary files a/target/scala-2.12/classes/include/mul_pkt_t.class and b/target/scala-2.12/classes/include/mul_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/predict_pkt_t.class b/target/scala-2.12/classes/include/predict_pkt_t.class index 8e7a4610..fff12097 100644 Binary files a/target/scala-2.12/classes/include/predict_pkt_t.class and b/target/scala-2.12/classes/include/predict_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/read_addr$.class b/target/scala-2.12/classes/include/read_addr$.class index 3592902e..9fb4fe0f 100644 Binary files a/target/scala-2.12/classes/include/read_addr$.class and b/target/scala-2.12/classes/include/read_addr$.class differ diff --git a/target/scala-2.12/classes/include/read_addr.class b/target/scala-2.12/classes/include/read_addr.class index 7ff97901..dc309ee8 100644 Binary files a/target/scala-2.12/classes/include/read_addr.class and b/target/scala-2.12/classes/include/read_addr.class differ diff --git a/target/scala-2.12/classes/include/read_data$.class b/target/scala-2.12/classes/include/read_data$.class index fa936f21..4223e5ea 100644 Binary files a/target/scala-2.12/classes/include/read_data$.class and b/target/scala-2.12/classes/include/read_data$.class differ diff --git a/target/scala-2.12/classes/include/read_data.class b/target/scala-2.12/classes/include/read_data.class index 8341e413..efd32d87 100644 Binary files a/target/scala-2.12/classes/include/read_data.class and b/target/scala-2.12/classes/include/read_data.class differ diff --git a/target/scala-2.12/classes/include/reg_pkt_t.class b/target/scala-2.12/classes/include/reg_pkt_t.class index 068a5a0c..8e6f95ed 100644 Binary files a/target/scala-2.12/classes/include/reg_pkt_t.class and b/target/scala-2.12/classes/include/reg_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/rets_pkt_t.class b/target/scala-2.12/classes/include/rets_pkt_t.class index 15c39b98..85ed6e9d 100644 Binary files a/target/scala-2.12/classes/include/rets_pkt_t.class and b/target/scala-2.12/classes/include/rets_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/tlu_busbuff.class b/target/scala-2.12/classes/include/tlu_busbuff.class index 364d5a5e..b2428d15 100644 Binary files a/target/scala-2.12/classes/include/tlu_busbuff.class and b/target/scala-2.12/classes/include/tlu_busbuff.class differ diff --git a/target/scala-2.12/classes/include/tlu_exu.class b/target/scala-2.12/classes/include/tlu_exu.class index 6987e9c3..f87d6743 100644 Binary files a/target/scala-2.12/classes/include/tlu_exu.class and b/target/scala-2.12/classes/include/tlu_exu.class differ diff --git a/target/scala-2.12/classes/include/trace_pkt_t.class b/target/scala-2.12/classes/include/trace_pkt_t.class index fe6d6f24..001b03a3 100644 Binary files a/target/scala-2.12/classes/include/trace_pkt_t.class and b/target/scala-2.12/classes/include/trace_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/trap_pkt_t.class b/target/scala-2.12/classes/include/trap_pkt_t.class index 0b752e61..8732e7d4 100644 Binary files a/target/scala-2.12/classes/include/trap_pkt_t.class and b/target/scala-2.12/classes/include/trap_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/trigger_pkt_t.class b/target/scala-2.12/classes/include/trigger_pkt_t.class index 7bd17e16..c2de1bff 100644 Binary files a/target/scala-2.12/classes/include/trigger_pkt_t.class and b/target/scala-2.12/classes/include/trigger_pkt_t.class differ diff --git a/target/scala-2.12/classes/include/write_addr$.class b/target/scala-2.12/classes/include/write_addr$.class index 48788efe..a4c1a305 100644 Binary files a/target/scala-2.12/classes/include/write_addr$.class and b/target/scala-2.12/classes/include/write_addr$.class differ diff --git a/target/scala-2.12/classes/include/write_addr.class b/target/scala-2.12/classes/include/write_addr.class index 9de6cddc..313ea4e0 100644 Binary files a/target/scala-2.12/classes/include/write_addr.class and b/target/scala-2.12/classes/include/write_addr.class differ diff --git a/target/scala-2.12/classes/include/write_data.class b/target/scala-2.12/classes/include/write_data.class index 5852c659..c3a308eb 100644 Binary files a/target/scala-2.12/classes/include/write_data.class and b/target/scala-2.12/classes/include/write_data.class differ diff --git a/target/scala-2.12/classes/include/write_resp$.class b/target/scala-2.12/classes/include/write_resp$.class index a784f452..96dfff2c 100644 Binary files a/target/scala-2.12/classes/include/write_resp$.class and b/target/scala-2.12/classes/include/write_resp$.class differ diff --git a/target/scala-2.12/classes/include/write_resp.class b/target/scala-2.12/classes/include/write_resp.class index 639ca934..0444641c 100644 Binary files a/target/scala-2.12/classes/include/write_resp.class and b/target/scala-2.12/classes/include/write_resp.class differ