colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Memory connection updated

This commit is contained in:
​Laraib Khan 2021-02-24 16:13:28 +05:00
parent 5d42a80edf
commit 11695f3916
9 changed files with 1303 additions and 844 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

127
mem.sv
View File

@ -15,7 +15,11 @@
// limitations under the License. // limitations under the License.
//******************************************************************************** //********************************************************************************
`include "lsu_dccm_mem.sv"
`include "ifu_ic_mem.sv"
`include "ifu_iccm_mem.sv"
module mem module mem
`include "parameter.sv"
( (
input logic clk, input logic clk,
input logic rst_l, input logic rst_l,
@ -38,12 +42,36 @@ module mem
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE //`ifdef DCCM_ENABLE
input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, //input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_TEST1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RME,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_0,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_2,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_3,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_LS,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_DS,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_SD,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RNM,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC2,
//`endif //`endif
//ICCM ports //ICCM ports
input ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, //input ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_TEST1,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RME,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_0,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_1,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_2,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_3,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_LS,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_DS,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_SD,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RNM,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_BC1,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_BC2,
input logic [ICCM_BITS-1:1] iccm_rw_addr, input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
@ -64,10 +92,49 @@ module mem
input logic ic_rd_en, input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel input logic ic_sel_premux_data, // Premux data sel
input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_TEST1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RME,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_0,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_2,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_3,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_LS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_DS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_SD,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RNM,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_BC1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_BC2,
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_TEST1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RME,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_0,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_2,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_3,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_LS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_DS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_SD,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RNM,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC2,
//input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_TEST1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RME,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_0,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_2,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_3,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_LS,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_DS,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_SD,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RNM,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC2,
// input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache. input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
@ -77,7 +144,7 @@ module mem
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ictag_debug_rd_data,// Debug icache tag. output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
@ -90,19 +157,58 @@ module mem
); );
logic active_clk; logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_TEST1;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RME;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_0;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_1;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_2;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_3;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_LS;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_DS;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_SD;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RNM;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC1;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC2;
logic active_clk;
assign ic_data_ext_in_pkt_TEST1[0] = ic_data_ext_in_pkt_0_TEST1 ;
assign ic_data_ext_in_pkt_RME[0] = ic_data_ext_in_pkt_0_RME;
assign ic_data_ext_in_pkt_RM_0[0] = ic_data_ext_in_pkt_0_RM_0;
assign ic_data_ext_in_pkt_RM_1[0] = ic_data_ext_in_pkt_0_RM_1;
assign ic_data_ext_in_pkt_RM_2[0] = ic_data_ext_in_pkt_0_RM_2;
assign ic_data_ext_in_pkt_RM_3[0] = ic_data_ext_in_pkt_0_RM_3;
assign ic_data_ext_in_pkt_LS[0] = ic_data_ext_in_pkt_0_LS;
assign ic_data_ext_in_pkt_DS[0] = ic_data_ext_in_pkt_0_DS;
assign ic_data_ext_in_pkt_SD[0] = ic_data_ext_in_pkt_0_SD;
assign ic_data_ext_in_pkt_RNM[0] = ic_data_ext_in_pkt_0_RNM;
assign ic_data_ext_in_pkt_BC1[0] = ic_data_ext_in_pkt_0_BC1;
assign ic_data_ext_in_pkt_BC2[0] = ic_data_ext_in_pkt_0_BC2;
assign ic_data_ext_in_pkt_TEST1[1] = ic_data_ext_in_pkt_1_TEST1 ;
assign ic_data_ext_in_pkt_RME[1] = ic_data_ext_in_pkt_1_RME;
assign ic_data_ext_in_pkt_RM_0[1] = ic_data_ext_in_pkt_1_RM_0;
assign ic_data_ext_in_pkt_RM_1[1] = ic_data_ext_in_pkt_1_RM_1;
assign ic_data_ext_in_pkt_RM_2[1] = ic_data_ext_in_pkt_1_RM_2;
assign ic_data_ext_in_pkt_RM_3[1] = ic_data_ext_in_pkt_1_RM_3;
assign ic_data_ext_in_pkt_LS[1] = ic_data_ext_in_pkt_1_LS;
assign ic_data_ext_in_pkt_DS[1] = ic_data_ext_in_pkt_1_DS;
assign ic_data_ext_in_pkt_SD[1] = ic_data_ext_in_pkt_1_SD;
assign ic_data_ext_in_pkt_RNM[1] = ic_data_ext_in_pkt_1_RNM;
assign ic_data_ext_in_pkt_BC1[1] = ic_data_ext_in_pkt_1_BC1;
assign ic_data_ext_in_pkt_BC2[1] = ic_data_ext_in_pkt_1_BC2;
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* ); rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
// DCCM Instantiation // DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem dccm #( lsu_dccm_mem #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH), .DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS), .DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS), .DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS), .DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE), .DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH), .DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH),
.DCCM_WIDTH_BITS(DCCM_WIDTH_BITS))( .DCCM_WIDTH_BITS(DCCM_WIDTH_BITS)) dccm (
.clk_override(dccm_clk_override), .clk_override(dccm_clk_override),
.* .*
); );
@ -142,7 +248,7 @@ else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0; assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ; assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ; assign ic_rd_data = '0 ;
assign ictag_debug_rd_data = '0 ; assign ic_tag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE ) end // else: !if( ICACHE_ENABLE )
@ -167,4 +273,3 @@ end
endmodule endmodule

471
src/main/resources/vsrc/ifu_ic_mem.sv
View File

@ -17,31 +17,11 @@
//////////////////////////////////////////////////// ////////////////////////////////////////////////////
// ICACHE DATA & TAG MODULE WRAPPER // // ICACHE DATA & TAG MODULE WRAPPER //
///////////////////////////////////////////////////// /////////////////////////////////////////////////////
module el2_ifu_ic_mem
#(
parameter ICACHE_NUM_WAYS, module ifu_ic_mem
parameter ICACHE_BANKS_WAY, `include "parameter.sv"
parameter ICACHE_INDEX_HI,
parameter ICACHE_TAG_INDEX_LO,
parameter ICACHE_TAG_LO,
parameter ICACHE_DATA_INDEX_LO,
parameter ICACHE_NUM_BYPASS,
parameter ICACHE_LN_SZ,
parameter ICACHE_BANK_HI,
parameter ICACHE_BANK_LO,
parameter ICACHE_WAYPACK,
parameter ICACHE_NUM_BYPASS_WIDTH,
parameter ICACHE_BYPASS_ENABLE,
parameter ICACHE_ECC,
parameter ICACHE_DATA_DEPTH,
parameter ICACHE_BANK_BITS,
parameter ICACHE_BEAT_ADDR_HI,
parameter ICACHE_BEAT_BITS,
parameter ICACHE_TAG_NUM_BYPASS,
parameter ICACHE_TAG_NUM_BYPASS_WIDTH,
parameter ICACHE_TAG_BYPASS_ENABLE,
parameter ICACHE_TAG_DEPTH,
)
( (
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
@ -60,35 +40,55 @@ module el2_ifu_ic_mem
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Select the pre_muxed data input logic ic_sel_premux_data, // Select the pre_muxed data
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ictag_debug_rd_data,// Debug icache tag. output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
input logic [70:0] ic_debug_wr_data, // Debug wr cache. input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // ecc error per bank output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // ecc error per bank
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid from the I$ tag valid outside (in flops). input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid from the I$ tag valid outside (in flops).
//input el2_ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc // input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] TEST1, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_TEST1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] RME, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RME,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0][3:0] RM, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_0,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] LS, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] DS, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_2,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] TEST-RNM, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_3,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] BC1, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_LS,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] BC2, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_DS,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_SD,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RNM,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC2,
//input el2_ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, // this is being driven by the top level for soc testing/etc // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_TEST1,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RME,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_0,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_1,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_2,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_3,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_LS,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_DS,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RNM,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC1,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC2,
input [ICACHE_NUM_WAYS-1:0] TEST1, //input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, // this is being driven by the top level for soc testing/etc
input [ICACHE_NUM_WAYS-1:0] RME, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_TEST1,
input [ICACHE_NUM_WAYS-1:0][3:0] RM, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RME,
input [ICACHE_NUM_WAYS-1:0] LS, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_0,
input [ICACHE_NUM_WAYS-1:0] DS, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_1,
input [ICACHE_NUM_WAYS-1:0] TEST-RNM, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_2,
input [ICACHE_NUM_WAYS-1:0] BC1, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_3,
input [ICACHE_NUM_WAYS-1:0] BC2, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_LS,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_DS,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_SD,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RNM,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC2,
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit, // ic_rd_hit[3:0] output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit, // ic_rd_hit[3:0]
output logic ic_tag_perr, // Tag Parity error output logic ic_tag_perr, // Tag Parity error
@ -98,7 +98,7 @@ module el2_ifu_ic_mem
EL2_IC_TAG #(.pt(pt)) ic_tag_inst IC_TAG ic_tag_inst
( (
.*, .*,
.ic_wr_en (ic_wr_en[ICACHE_NUM_WAYS-1:0]), .ic_wr_en (ic_wr_en[ICACHE_NUM_WAYS-1:0]),
@ -106,7 +106,7 @@ module el2_ifu_ic_mem
.ic_rw_addr (ic_rw_addr[31:3]) .ic_rw_addr (ic_rw_addr[31:3])
) ; ) ;
EL2_IC_DATA #(.pt(pt)) ic_data_inst IC_DATA ic_data_inst
( (
.*, .*,
.ic_wr_en (ic_wr_en[ICACHE_NUM_WAYS-1:0]), .ic_wr_en (ic_wr_en[ICACHE_NUM_WAYS-1:0]),
@ -120,10 +120,8 @@ module el2_ifu_ic_mem
///////////////////////////////////////////////// /////////////////////////////////////////////////
////// ICACHE DATA MODULE //////////////////// ////// ICACHE DATA MODULE ////////////////////
///////////////////////////////////////////////// /////////////////////////////////////////////////
module EL2_IC_DATA module IC_DATA
#( `include "parameter.sv"
`include "el2_param.vh"
)
( (
input logic clk, input logic clk,
input logic active_clk, input logic active_clk,
@ -134,7 +132,9 @@ module EL2_IC_DATA
input logic [ICACHE_NUM_WAYS-1:0]ic_wr_en, input logic [ICACHE_NUM_WAYS-1:0]ic_wr_en,
input logic ic_rd_en, // Read enable input logic ic_rd_en, // Read enable
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC // input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache. input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
@ -149,16 +149,31 @@ module EL2_IC_DATA
input logic ic_sel_premux_data, // Select the pre_muxed data input logic ic_sel_premux_data, // Select the pre_muxed data
input logic [ICACHE_NUM_WAYS-1:0]ic_rd_hit, input logic [ICACHE_NUM_WAYS-1:0]ic_rd_hit,
//input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_TEST1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RME,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_0,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_2,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_3,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_LS,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_DS,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_SD,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RNM,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC2,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] TEST1, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_TEST1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] RME, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RME,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0][3:0] RM, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_0,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] LS, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] DS, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_2,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] TEST-RNM, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_3,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] BC1, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_LS,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] BC2, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_DS,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RNM,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC1,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC2,
input logic scan_mode input logic scan_mode
) ; ) ;
@ -295,7 +310,8 @@ module EL2_IC_DATA
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] any_bypass_up; logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] any_bypass_up;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] any_addr_match_up; logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] any_addr_match_up;
`define EL2_IC_DATA_SRAM(depth,width) \
`define IC_DATA_SRAM(depth,width) \
ram_``depth``x``width ic_bank_sb_way_data ( \ ram_``depth``x``width ic_bank_sb_way_data ( \
.ME(ic_bank_way_clken_final_up[i][k]), \ .ME(ic_bank_way_clken_final_up[i][k]), \
.WE (ic_b_sb_wren[k][i]), \ .WE (ic_b_sb_wren[k][i]), \
@ -304,17 +320,20 @@ module EL2_IC_DATA
.Q (wb_dout_pre_up[i][k]), \ .Q (wb_dout_pre_up[i][k]), \
.CLK (clk), \ .CLK (clk), \
.ROP ( ), \ .ROP ( ), \
.TEST1(TEST1[i][k]), \ .TEST1(ic_data_ext_in_pkt_TEST1[i][k]), \
.RME(RME[i][k]), \ .RME(ic_data_ext_in_pkt_RME[i][k]), \
.RM(RM[i][k]), \ .RM_0(ic_data_ext_in_pkt_RM_0[i][k]), \
.RM_1(ic_data_ext_in_pkt_RM_1[i][k]), \
.RM_2(ic_data_ext_in_pkt_RM_2[i][k]), \
.RM_3(ic_data_ext_in_pkt_RM_3[i][k]), \
\ \
.LS(LS[i][k]), \ .LS(ic_data_ext_in_pkt_LS[i][k]), \
.DS(DS[i][k]), \ .DS(ic_data_ext_in_pkt_DS[i][k]), \
.SD(SD[i][k]), \ .SD(ic_data_ext_in_pkt_SD[i][k]), \
\ \
.TEST_RNM(TEST_RNM[i][k]), \ .RNM(ic_data_ext_in_pkt_RNM[i][k]), \
.BC1(BC1[i][k]), \ .BC1(ic_data_ext_in_pkt_BC1[i][k]), \
.BC2(BC2[i][k]) \ .BC2(ic_data_ext_in_pkt_BC2[i][k]) \
); \ ); \
if (ICACHE_BYPASS_ENABLE == 1) begin \ if (ICACHE_BYPASS_ENABLE == 1) begin \
assign wrptr_in_up[i][k] = (wrptr_up[i][k] == (ICACHE_NUM_BYPASS-1)) ? '0 : (wrptr_up[i][k] + 1'd1); \ assign wrptr_in_up[i][k] = (wrptr_up[i][k] == (ICACHE_NUM_BYPASS-1)) ? '0 : (wrptr_up[i][k] + 1'd1); \
@ -372,28 +391,28 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [ICACHE_NUM_BYPASS-1:0] [71-1:0] wb_dout_hold_up; logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [ICACHE_NUM_BYPASS-1:0] [71-1:0] wb_dout_hold_up;
if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192 if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192
`EL2_IC_DATA_SRAM(8192,71) `IC_DATA_SRAM(8192,71)
end end
else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096 else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096
`EL2_IC_DATA_SRAM(4096,71) `IC_DATA_SRAM(4096,71)
end end
else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048 else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048
`EL2_IC_DATA_SRAM(2048,71) `IC_DATA_SRAM(2048,71)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024 else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024
`EL2_IC_DATA_SRAM(1024,71) `IC_DATA_SRAM(1024,71)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512 else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512
`EL2_IC_DATA_SRAM(512,71) `IC_DATA_SRAM(512,71)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256 else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256
`EL2_IC_DATA_SRAM(256,71) `IC_DATA_SRAM(256,71)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128 else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128
`EL2_IC_DATA_SRAM(128,71) `IC_DATA_SRAM(128,71)
end end
else begin : size_64 else begin : size_64
`EL2_IC_DATA_SRAM(64,71) `IC_DATA_SRAM(64,71)
end end
end // if (ICACHE_ECC) end // if (ICACHE_ECC)
@ -401,28 +420,28 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [68-1:0] wb_dout_pre_up; // data and its bit enables logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [68-1:0] wb_dout_pre_up; // data and its bit enables
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [ICACHE_NUM_BYPASS-1:0] [68-1:0] wb_dout_hold_up; logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [ICACHE_NUM_BYPASS-1:0] [68-1:0] wb_dout_hold_up;
if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192 if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192
`EL2_IC_DATA_SRAM(8192,68) `IC_DATA_SRAM(8192,68)
end end
else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096 else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096
`EL2_IC_DATA_SRAM(4096,68) `IC_DATA_SRAM(4096,68)
end end
else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048 else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048
`EL2_IC_DATA_SRAM(2048,68) `IC_DATA_SRAM(2048,68)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024 else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024
`EL2_IC_DATA_SRAM(1024,68) `IC_DATA_SRAM(1024,68)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512 else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512
`EL2_IC_DATA_SRAM(512,68) `IC_DATA_SRAM(512,68)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256 else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256
`EL2_IC_DATA_SRAM(256,68) `IC_DATA_SRAM(256,68)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128 else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128
`EL2_IC_DATA_SRAM(128,68) `IC_DATA_SRAM(128,68)
end end
else begin : size_64 else begin : size_64
`EL2_IC_DATA_SRAM(64,68) `IC_DATA_SRAM(64,68)
end end
end // else: !if(ICACHE_ECC) end // else: !if(ICACHE_ECC)
end // block: BANKS_WAY end // block: BANKS_WAY
@ -446,7 +465,7 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
// SRAM macros // SRAM macros
`define EL2_PACKED_IC_DATA_SRAM(depth,width,waywidth) \ `define PACKED_IC_DATA_SRAM(depth,width,waywidth) \
ram_be_``depth``x``width ic_bank_sb_way_data ( \ ram_be_``depth``x``width ic_bank_sb_way_data ( \
.CLK (clk), \ .CLK (clk), \
.WE (|ic_b_sb_wren[k]), // OR of all the ways in the bank \ .WE (|ic_b_sb_wren[k]), // OR of all the ways in the bank \
@ -456,17 +475,20 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
.Q (wb_packeddout_pre[k]), \ .Q (wb_packeddout_pre[k]), \
.ME (|ic_bank_way_clken_final[k]), \ .ME (|ic_bank_way_clken_final[k]), \
.ROP ( ), \ .ROP ( ), \
.TEST1 (ic_data_ext_in_pkt[0][k].TEST1), \ .TEST1 (ic_data_ext_in_pkt_TEST1[0][k]), \
.RME (ic_data_ext_in_pkt[0][k].RME), \ .RME (ic_data_ext_in_pkt_RME[0][k]), \
.RM (ic_data_ext_in_pkt[0][k].RM), \ .RM_0 (ic_data_ext_in_pkt_RM_0[0][k]), \
.RM_1 (ic_data_ext_in_pkt_RM_1[0][k]), \
.RM_2 (ic_data_ext_in_pkt_RM_2[0][k]), \
.RM_3 (ic_data_ext_in_pkt_RM_3[0][k]), \
\ \
.LS (ic_data_ext_in_pkt[0][k].LS), \ .LS (ic_data_ext_in_pkt_LS[0][k]), \
.DS (ic_data_ext_in_pkt[0][k].DS), \ .DS (ic_data_ext_in_pkt_DS[0][k]), \
.SD (ic_data_ext_in_pkt[0][k].SD), \ .SD (ic_data_ext_in_pkt_SD[0][k]), \
\ \
.TEST_RNM (ic_data_ext_in_pkt[0][k].TEST_RNM), \ .RNM (ic_data_ext_in_pkt_RNM[0][k]), \
.BC1 (ic_data_ext_in_pkt[0][k].BC1), \ .BC1 (ic_data_ext_in_pkt_BC1[0][k]), \
.BC2 (ic_data_ext_in_pkt[0][k].BC2) \ .BC2 (ic_data_ext_in_pkt_BC2[0][k]) \
); \ ); \
\ \
if (ICACHE_BYPASS_ENABLE == 1) begin \ if (ICACHE_BYPASS_ENABLE == 1) begin \
@ -547,73 +569,73 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
// SRAMS with ECC (single/double detect; no correct) // SRAMS with ECC (single/double detect; no correct)
if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192 if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(8192,284,71) // 64b data + 7b ecc `PACKED_IC_DATA_SRAM(8192,284,71) // 64b data + 7b ecc
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(8192,142,71) `PACKED_IC_DATA_SRAM(8192,142,71)
end // block: WAYS end // block: WAYS
end // block: size_8192 end // block: size_8192
else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096 else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(4096,284,71) `PACKED_IC_DATA_SRAM(4096,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(4096,142,71) `PACKED_IC_DATA_SRAM(4096,142,71)
end // block: WAYS end // block: WAYS
end // block: size_4096 end // block: size_4096
else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048 else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(2048,284,71) `PACKED_IC_DATA_SRAM(2048,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(2048,142,71) `PACKED_IC_DATA_SRAM(2048,142,71)
end // block: WAYS end // block: WAYS
end // block: size_2048 end // block: size_2048
else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024 else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(1024,284,71) `PACKED_IC_DATA_SRAM(1024,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(1024,142,71) `PACKED_IC_DATA_SRAM(1024,142,71)
end // block: WAYS end // block: WAYS
end // block: size_1024 end // block: size_1024
else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512 else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(512,284,71) `PACKED_IC_DATA_SRAM(512,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(512,142,71) `PACKED_IC_DATA_SRAM(512,142,71)
end // block: WAYS end // block: WAYS
end // block: size_512 end // block: size_512
else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256 else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(256,284,71) `PACKED_IC_DATA_SRAM(256,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(256,142,71) `PACKED_IC_DATA_SRAM(256,142,71)
end // block: WAYS end // block: WAYS
end // block: size_256 end // block: size_256
else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128 else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(128,284,71) `PACKED_IC_DATA_SRAM(128,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(128,142,71) `PACKED_IC_DATA_SRAM(128,142,71)
end // block: WAYS end // block: WAYS
end // block: size_128 end // block: size_128
else begin : size_64 else begin : size_64
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(64,284,71) `PACKED_IC_DATA_SRAM(64,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(64,142,71) `PACKED_IC_DATA_SRAM(64,142,71)
end // block: WAYS end // block: WAYS
end // block: size_64 end // block: size_64
@ -637,73 +659,73 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
// SRAMs with parity // SRAMs with parity
if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192 if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(8192,272,68) // 64b data + 4b parity `PACKED_IC_DATA_SRAM(8192,272,68) // 64b data + 4b parity
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(8192,136,68) `PACKED_IC_DATA_SRAM(8192,136,68)
end // block: WAYS end // block: WAYS
end // block: size_8192 end // block: size_8192
else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096 else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(4096,272,68) `PACKED_IC_DATA_SRAM(4096,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(4096,136,68) `PACKED_IC_DATA_SRAM(4096,136,68)
end // block: WAYS end // block: WAYS
end // block: size_4096 end // block: size_4096
else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048 else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(2048,272,68) `PACKED_IC_DATA_SRAM(2048,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(2048,136,68) `PACKED_IC_DATA_SRAM(2048,136,68)
end // block: WAYS end // block: WAYS
end // block: size_2048 end // block: size_2048
else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024 else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(1024,272,68) `PACKED_IC_DATA_SRAM(1024,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(1024,136,68) `PACKED_IC_DATA_SRAM(1024,136,68)
end // block: WAYS end // block: WAYS
end // block: size_1024 end // block: size_1024
else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512 else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(512,272,68) `PACKED_IC_DATA_SRAM(512,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(512,136,68) `PACKED_IC_DATA_SRAM(512,136,68)
end // block: WAYS end // block: WAYS
end // block: size_512 end // block: size_512
else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256 else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(256,272,68) `PACKED_IC_DATA_SRAM(256,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(256,136,68) `PACKED_IC_DATA_SRAM(256,136,68)
end // block: WAYS end // block: WAYS
end // block: size_256 end // block: size_256
else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128 else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(128,272,68) `PACKED_IC_DATA_SRAM(128,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(128,136,68) `PACKED_IC_DATA_SRAM(128,136,68)
end // block: WAYS end // block: WAYS
end // block: size_128 end // block: size_128
else begin : size_64 else begin : size_64
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(64,272,68) `PACKED_IC_DATA_SRAM(64,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(64,136,68) `PACKED_IC_DATA_SRAM(64,136,68)
end // block: WAYS end // block: WAYS
end // block: size_64 end // block: size_64
@ -720,8 +742,8 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
if ( ICACHE_ECC ) begin : ECC1_MUX if ( ICACHE_ECC ) begin : ECC1_MUX
assign ic_bank_wr_data[1] = ic_wr_data[1][70:0]; assign ic_bank_wr_data[1] = ic_wr_data_1[70:0];
assign ic_bank_wr_data[0] = ic_wr_data[0][70:0]; assign ic_bank_wr_data[0] = ic_wr_data_0[70:0];
always_comb begin : rd_mux always_comb begin : rd_mux
wb_dout_way_pre[ICACHE_NUM_WAYS-1:0] = '0; wb_dout_way_pre[ICACHE_NUM_WAYS-1:0] = '0;
@ -772,8 +794,8 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
end // if ( ICACHE_ECC ) end // if ( ICACHE_ECC )
else begin : ECC0_MUX else begin : ECC0_MUX
assign ic_bank_wr_data[1] = ic_wr_data[1][70:0]; assign ic_bank_wr_data[1] = ic_wr_data_1[70:0];
assign ic_bank_wr_data[0] = ic_wr_data[0][70:0]; assign ic_bank_wr_data[0] = ic_wr_data_0[70:0];
always_comb begin : rd_mux always_comb begin : rd_mux
wb_dout_way_pre[ICACHE_NUM_WAYS-1:0] = '0; wb_dout_way_pre[ICACHE_NUM_WAYS-1:0] = '0;
@ -830,7 +852,7 @@ else begin : ECC0_MUX
end // else: !if( ICACHE_ECC ) end // else: !if( ICACHE_ECC )
endmodule // EL2_IC_DATA endmodule // IC_DATA
//============================================================================================================================================================= //=============================================================================================================================================================
///\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ END OF IC DATA MODULE \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ ///\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ END OF IC DATA MODULE \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/
@ -840,10 +862,8 @@ endmodule // EL2_IC_DATA
///////////////////////////////////////////////// /////////////////////////////////////////////////
////// ICACHE TAG MODULE //////////////////// ////// ICACHE TAG MODULE ////////////////////
///////////////////////////////////////////////// /////////////////////////////////////////////////
module EL2_IC_TAG module IC_TAG
#( `include "parameter.sv"
`include "el2_param.vh"
)
( (
input logic clk, input logic clk,
input logic active_clk, input logic active_clk,
@ -862,18 +882,20 @@ module EL2_IC_TAG
input logic ic_debug_wr_en, // Icache debug wr input logic ic_debug_wr_en, // Icache debug wr
input logic ic_debug_tag_array, // Debug tag array input logic ic_debug_tag_array, // Debug tag array
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
input el2_ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, // input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_TEST1,
input [ICACHE_NUM_WAYS-1:0] TEST1, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RME,
input [ICACHE_NUM_WAYS-1:0] RME, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_0,
input [ICACHE_NUM_WAYS-1:0][3:0] RM, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_1,
input [ICACHE_NUM_WAYS-1:0] LS, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_2,
input [ICACHE_NUM_WAYS-1:0] DS, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_3,
input [ICACHE_NUM_WAYS-1:0] TEST-RNM, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_LS,
input [ICACHE_NUM_WAYS-1:0] BC1, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_DS,
input [ICACHE_NUM_WAYS-1:0] BC2, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_SD,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RNM,
output logic [25:0] ictag_debug_rd_data, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC2,
output logic [25:0] ic_tag_debug_rd_data,
input logic [70:0] ic_debug_wr_data, // Debug wr cache. input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit, output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
@ -1012,7 +1034,7 @@ end // block: OTHERS
logic [ICACHE_NUM_WAYS-1:0] any_addr_match; logic [ICACHE_NUM_WAYS-1:0] any_addr_match;
logic [ICACHE_NUM_WAYS-1:0] ic_tag_clken_final; logic [ICACHE_NUM_WAYS-1:0] ic_tag_clken_final;
`define EL2_IC_TAG_SRAM(depth,width) \ `define IC_TAG_SRAM(depth,width) \
ram_``depth``x``width ic_way_tag ( \ ram_``depth``x``width ic_way_tag ( \
.ME(ic_tag_clken_final[i]), \ .ME(ic_tag_clken_final[i]), \
.WE (ic_tag_wren_q[i]), \ .WE (ic_tag_wren_q[i]), \
@ -1022,17 +1044,20 @@ end // block: OTHERS
.CLK (clk), \ .CLK (clk), \
.ROP ( ), \ .ROP ( ), \
\ \
.TEST1(ic_tag_ext_in_pkt[i].TEST1[i]), \ .TEST1(ic_tag_ext_in_pkt_TEST1[i]), \
.RME(ic_tag_ext_in_pkt[i].RME[i]), \ .RME(ic_tag_ext_in_pkt_RME[i]), \
.RM(ic_tag_ext_in_pkt[i].RM[i]), \ .RM_0(ic_tag_ext_in_pkt_RM_0[i]), \
.RM_1(ic_tag_ext_in_pkt_RM_1[i]),\
.RM_2(ic_tag_ext_in_pkt_RM_2[i]),\
.RM_3(ic_tag_ext_in_pkt_RM_3[i]), \
\ \
.LS(ic_tag_ext_in_pkt[i].LS[i]), \ .LS(ic_tag_ext_in_pkt_LS[i]), \
.DS(ic_tag_ext_in_pkt[i].DS[i]), \ .DS(ic_tag_ext_in_pkt_DS[i]), \
.SD(ic_tag_ext_in_pkt[i].SD[i]), \ .SD(ic_tag_ext_in_pkt_SD[i]), \
\ \
.TEST_RNM(ic_tag_ext_in_pkt[i].TEST_RNM[i]), \ .RNM(ic_tag_ext_in_pkt_RNM[i]), \
.BC1(ic_tag_ext_in_pkt[i].BC1[i]), \ .BC1(ic_tag_ext_in_pkt_BC1[i]), \
.BC2(ic_tag_ext_in_pkt[i].BC2[i]) \ .BC2(ic_tag_ext_in_pkt_BC2[i]) \
\ \
); \ ); \
\ \
@ -1105,28 +1130,28 @@ end // block: OTHERS
logic [ICACHE_NUM_WAYS-1:0] [ICACHE_TAG_NUM_BYPASS-1:0][25 :0] wb_dout_hold; logic [ICACHE_NUM_WAYS-1:0] [ICACHE_TAG_NUM_BYPASS-1:0][25 :0] wb_dout_hold;
if (ICACHE_TAG_DEPTH == 32) begin : size_32 if (ICACHE_TAG_DEPTH == 32) begin : size_32
`EL2_IC_TAG_SRAM(32,26) `IC_TAG_SRAM(32,26)
end // if (ICACHE_TAG_DEPTH == 32) end // if (ICACHE_TAG_DEPTH == 32)
if (ICACHE_TAG_DEPTH == 64) begin : size_64 if (ICACHE_TAG_DEPTH == 64) begin : size_64
`EL2_IC_TAG_SRAM(64,26) `IC_TAG_SRAM(64,26)
end // if (ICACHE_TAG_DEPTH == 64) end // if (ICACHE_TAG_DEPTH == 64)
if (ICACHE_TAG_DEPTH == 128) begin : size_128 if (ICACHE_TAG_DEPTH == 128) begin : size_128
`EL2_IC_TAG_SRAM(128,26) `IC_TAG_SRAM(128,26)
end // if (ICACHE_TAG_DEPTH == 128) end // if (ICACHE_TAG_DEPTH == 128)
if (ICACHE_TAG_DEPTH == 256) begin : size_256 if (ICACHE_TAG_DEPTH == 256) begin : size_256
`EL2_IC_TAG_SRAM(256,26) `IC_TAG_SRAM(256,26)
end // if (ICACHE_TAG_DEPTH == 256) end // if (ICACHE_TAG_DEPTH == 256)
if (ICACHE_TAG_DEPTH == 512) begin : size_512 if (ICACHE_TAG_DEPTH == 512) begin : size_512
`EL2_IC_TAG_SRAM(512,26) `IC_TAG_SRAM(512,26)
end // if (ICACHE_TAG_DEPTH == 512) end // if (ICACHE_TAG_DEPTH == 512)
if (ICACHE_TAG_DEPTH == 1024) begin : size_1024 if (ICACHE_TAG_DEPTH == 1024) begin : size_1024
`EL2_IC_TAG_SRAM(1024,26) `IC_TAG_SRAM(1024,26)
end // if (ICACHE_TAG_DEPTH == 1024) end // if (ICACHE_TAG_DEPTH == 1024)
if (ICACHE_TAG_DEPTH == 2048) begin : size_2048 if (ICACHE_TAG_DEPTH == 2048) begin : size_2048
`EL2_IC_TAG_SRAM(2048,26) `IC_TAG_SRAM(2048,26)
end // if (ICACHE_TAG_DEPTH == 2048) end // if (ICACHE_TAG_DEPTH == 2048)
if (ICACHE_TAG_DEPTH == 4096) begin : size_4096 if (ICACHE_TAG_DEPTH == 4096) begin : size_4096
`EL2_IC_TAG_SRAM(4096,26) `IC_TAG_SRAM(4096,26)
end // if (ICACHE_TAG_DEPTH == 4096) end // if (ICACHE_TAG_DEPTH == 4096)
assign w_tout[i][31:ICACHE_TAG_LO] = ic_tag_data_raw[i][31-ICACHE_TAG_LO:0] ; assign w_tout[i][31:ICACHE_TAG_LO] = ic_tag_data_raw[i][31-ICACHE_TAG_LO:0] ;
@ -1149,28 +1174,28 @@ end // block: OTHERS
assign ic_tag_data_raw_pre[i][25:22] = '0 ; assign ic_tag_data_raw_pre[i][25:22] = '0 ;
if (ICACHE_TAG_DEPTH == 32) begin : size_32 if (ICACHE_TAG_DEPTH == 32) begin : size_32
`EL2_IC_TAG_SRAM(32,22) `IC_TAG_SRAM(32,22)
end // if (ICACHE_TAG_DEPTH == 32) end // if (ICACHE_TAG_DEPTH == 32)
if (ICACHE_TAG_DEPTH == 64) begin : size_64 if (ICACHE_TAG_DEPTH == 64) begin : size_64
`EL2_IC_TAG_SRAM(64,22) `IC_TAG_SRAM(64,22)
end // if (ICACHE_TAG_DEPTH == 64) end // if (ICACHE_TAG_DEPTH == 64)
if (ICACHE_TAG_DEPTH == 128) begin : size_128 if (ICACHE_TAG_DEPTH == 128) begin : size_128
`EL2_IC_TAG_SRAM(128,22) `IC_TAG_SRAM(128,22)
end // if (ICACHE_TAG_DEPTH == 128) end // if (ICACHE_TAG_DEPTH == 128)
if (ICACHE_TAG_DEPTH == 256) begin : size_256 if (ICACHE_TAG_DEPTH == 256) begin : size_256
`EL2_IC_TAG_SRAM(256,22) `IC_TAG_SRAM(256,22)
end // if (ICACHE_TAG_DEPTH == 256) end // if (ICACHE_TAG_DEPTH == 256)
if (ICACHE_TAG_DEPTH == 512) begin : size_512 if (ICACHE_TAG_DEPTH == 512) begin : size_512
`EL2_IC_TAG_SRAM(512,22) `IC_TAG_SRAM(512,22)
end // if (ICACHE_TAG_DEPTH == 512) end // if (ICACHE_TAG_DEPTH == 512)
if (ICACHE_TAG_DEPTH == 1024) begin : size_1024 if (ICACHE_TAG_DEPTH == 1024) begin : size_1024
`EL2_IC_TAG_SRAM(1024,22) `IC_TAG_SRAM(1024,22)
end // if (ICACHE_TAG_DEPTH == 1024) end // if (ICACHE_TAG_DEPTH == 1024)
if (ICACHE_TAG_DEPTH == 2048) begin : size_2048 if (ICACHE_TAG_DEPTH == 2048) begin : size_2048
`EL2_IC_TAG_SRAM(2048,22) `IC_TAG_SRAM(2048,22)
end // if (ICACHE_TAG_DEPTH == 2048) end // if (ICACHE_TAG_DEPTH == 2048)
if (ICACHE_TAG_DEPTH == 4096) begin : size_4096 if (ICACHE_TAG_DEPTH == 4096) begin : size_4096
`EL2_IC_TAG_SRAM(4096,22) `IC_TAG_SRAM(4096,22)
end // if (ICACHE_TAG_DEPTH == 4096) end // if (ICACHE_TAG_DEPTH == 4096)
assign w_tout[i][31:ICACHE_TAG_LO] = ic_tag_data_raw[i][31-ICACHE_TAG_LO:0] ; assign w_tout[i][31:ICACHE_TAG_LO] = ic_tag_data_raw[i][31-ICACHE_TAG_LO:0] ;
@ -1214,7 +1239,7 @@ end // block: OTHERS
logic any_addr_match; logic any_addr_match;
logic ic_tag_clken_final; logic ic_tag_clken_final;
`define EL2_IC_TAG_PACKED_SRAM(depth,width) \ `define IC_TAG_PACKED_SRAM(depth,width) \
ram_be_``depth``x``width ic_way_tag ( \ ram_be_``depth``x``width ic_way_tag ( \
.ME ( ic_tag_clken_final), \ .ME ( ic_tag_clken_final), \
.WE (|ic_tag_wren_q[ICACHE_NUM_WAYS-1:0]), \ .WE (|ic_tag_wren_q[ICACHE_NUM_WAYS-1:0]), \
@ -1226,17 +1251,20 @@ end // block: OTHERS
.CLK (clk), \ .CLK (clk), \
.ROP ( ), \ .ROP ( ), \
\ \
.TEST1 (TEST1[0]), \ .TEST1 (ic_tag_ext_in_pkt_TEST1[0]), \
.RME (RME[0]), \ .RME (ic_tag_ext_in_pkt_RME[0]), \
.RM (RM[0]), \ .RM_0 (ic_tag_ext_in_pkt_RM_0[0]), \
.RM_1 (ic_tag_ext_in_pkt_RM_1[0]), \
.RM_2 (ic_tag_ext_in_pkt_RM_2[0]), \
.RM_3 (ic_tag_ext_in_pkt_RM_3[0]), \
\ \
.LS (LS[0]), \ .LS (ic_tag_ext_in_pkt_LS[0]), \
.DS (DS[0]), \ .DS (ic_tag_ext_in_pkt_DS[0]), \
.SD (SD[0]), \ .SD (ic_tag_ext_in_pkt_SD[0]), \
\ \
.TEST_RNM (TEST_RNM[0]), \ .RNM (ic_tag_ext_in_pkt_RNM[0]), \
.BC1 (BC1[0]), \ .BC1 (ic_tag_ext_in_pkt_BC1[0]), \
.BC2 (BC2[0]) \ .BC2 (ic_tag_ext_in_pkt_BC2[0]) \
\ \
); \ ); \
\ \
@ -1309,74 +1337,74 @@ end // block: OTHERS
end end
if (ICACHE_TAG_DEPTH == 32) begin : size_32 if (ICACHE_TAG_DEPTH == 32) begin : size_32
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(32,104) `IC_TAG_PACKED_SRAM(32,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(32,52) `IC_TAG_PACKED_SRAM(32,52)
end // block: WAYS end // block: WAYS
end // if (ICACHE_TAG_DEPTH == 32 end // if (ICACHE_TAG_DEPTH == 32
if (ICACHE_TAG_DEPTH == 64) begin : size_64 if (ICACHE_TAG_DEPTH == 64) begin : size_64
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(64,104) `IC_TAG_PACKED_SRAM(64,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(64,52) `IC_TAG_PACKED_SRAM(64,52)
end // block: WAYS end // block: WAYS
end // block: size_64 end // block: size_64
if (ICACHE_TAG_DEPTH == 128) begin : size_128 if (ICACHE_TAG_DEPTH == 128) begin : size_128
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(128,104) `IC_TAG_PACKED_SRAM(128,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(128,52) `IC_TAG_PACKED_SRAM(128,52)
end // block: WAYS end // block: WAYS
end // block: size_128 end // block: size_128
if (ICACHE_TAG_DEPTH == 256) begin : size_256 if (ICACHE_TAG_DEPTH == 256) begin : size_256
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(256,104) `IC_TAG_PACKED_SRAM(256,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(256,52) `IC_TAG_PACKED_SRAM(256,52)
end // block: WAYS end // block: WAYS
end // block: size_256 end // block: size_256
if (ICACHE_TAG_DEPTH == 512) begin : size_512 if (ICACHE_TAG_DEPTH == 512) begin : size_512
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(512,104) `IC_TAG_PACKED_SRAM(512,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(512,52) `IC_TAG_PACKED_SRAM(512,52)
end // block: WAYS end // block: WAYS
end // block: size_512 end // block: size_512
if (ICACHE_TAG_DEPTH == 1024) begin : size_1024 if (ICACHE_TAG_DEPTH == 1024) begin : size_1024
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(1024,104) `IC_TAG_PACKED_SRAM(1024,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(1024,52) `IC_TAG_PACKED_SRAM(1024,52)
end // block: WAYS end // block: WAYS
end // block: size_1024 end // block: size_1024
if (ICACHE_TAG_DEPTH == 2048) begin : size_2048 if (ICACHE_TAG_DEPTH == 2048) begin : size_2048
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(2048,104) `IC_TAG_PACKED_SRAM(2048,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(2048,52) `IC_TAG_PACKED_SRAM(2048,52)
end // block: WAYS end // block: WAYS
end // block: size_2048 end // block: size_2048
if (ICACHE_TAG_DEPTH == 4096) begin : size_4096 if (ICACHE_TAG_DEPTH == 4096) begin : size_4096
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(4096,104) `IC_TAG_PACKED_SRAM(4096,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(4096,52) `IC_TAG_PACKED_SRAM(4096,52)
end // block: WAYS end // block: WAYS
end // block: size_4096 end // block: size_4096
@ -1408,74 +1436,74 @@ end // block: OTHERS
end end
if (ICACHE_TAG_DEPTH == 32) begin : size_32 if (ICACHE_TAG_DEPTH == 32) begin : size_32
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(32,88) `IC_TAG_PACKED_SRAM(32,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(32,44) `IC_TAG_PACKED_SRAM(32,44)
end // block: WAYS end // block: WAYS
end // if (ICACHE_TAG_DEPTH == 32 end // if (ICACHE_TAG_DEPTH == 32
if (ICACHE_TAG_DEPTH == 64) begin : size_64 if (ICACHE_TAG_DEPTH == 64) begin : size_64
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(64,88) `IC_TAG_PACKED_SRAM(64,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(64,44) `IC_TAG_PACKED_SRAM(64,44)
end // block: WAYS end // block: WAYS
end // block: size_64 end // block: size_64
if (ICACHE_TAG_DEPTH == 128) begin : size_128 if (ICACHE_TAG_DEPTH == 128) begin : size_128
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(128,88) `IC_TAG_PACKED_SRAM(128,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(128,44) `IC_TAG_PACKED_SRAM(128,44)
end // block: WAYS end // block: WAYS
end // block: size_128 end // block: size_128
if (ICACHE_TAG_DEPTH == 256) begin : size_256 if (ICACHE_TAG_DEPTH == 256) begin : size_256
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(256,88) `IC_TAG_PACKED_SRAM(256,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(256,44) `IC_TAG_PACKED_SRAM(256,44)
end // block: WAYS end // block: WAYS
end // block: size_256 end // block: size_256
if (ICACHE_TAG_DEPTH == 512) begin : size_512 if (ICACHE_TAG_DEPTH == 512) begin : size_512
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(512,88) `IC_TAG_PACKED_SRAM(512,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(512,44) `IC_TAG_PACKED_SRAM(512,44)
end // block: WAYS end // block: WAYS
end // block: size_512 end // block: size_512
if (ICACHE_TAG_DEPTH == 1024) begin : size_1024 if (ICACHE_TAG_DEPTH == 1024) begin : size_1024
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(1024,88) `IC_TAG_PACKED_SRAM(1024,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(1024,44) `IC_TAG_PACKED_SRAM(1024,44)
end // block: WAYS end // block: WAYS
end // block: size_1024 end // block: size_1024
if (ICACHE_TAG_DEPTH == 2048) begin : size_2048 if (ICACHE_TAG_DEPTH == 2048) begin : size_2048
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(2048,88) `IC_TAG_PACKED_SRAM(2048,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(2048,44) `IC_TAG_PACKED_SRAM(2048,44)
end // block: WAYS end // block: WAYS
end // block: size_2048 end // block: size_2048
if (ICACHE_TAG_DEPTH == 4096) begin : size_4096 if (ICACHE_TAG_DEPTH == 4096) begin : size_4096
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(4096,88) `IC_TAG_PACKED_SRAM(4096,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(4096,44) `IC_TAG_PACKED_SRAM(4096,44)
end // block: WAYS end // block: WAYS
end // block: size_4096 end // block: size_4096
@ -1497,9 +1525,9 @@ end // block: OTHERS
always_comb begin : tag_rd_out always_comb begin : tag_rd_out
ictag_debug_rd_data[25:0] = '0; ic_tag_debug_rd_data[25:0] = '0;
for ( int j=0; j<ICACHE_NUM_WAYS; j++) begin: debug_rd_out for ( int j=0; j<ICACHE_NUM_WAYS; j++) begin: debug_rd_out
ictag_debug_rd_data[25:0] |= ICACHE_ECC ? ({26{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j] ) : {4'b0, ({22{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j][21:0])}; ic_tag_debug_rd_data[25:0] |= ICACHE_ECC ? ({26{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j] ) : {4'b0, ({22{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j][21:0])};
end end
end end
@ -1509,5 +1537,4 @@ end // block: OTHERS
end end
assign ic_tag_perr = | (ic_tag_way_perr[ICACHE_NUM_WAYS-1:0] & ic_tag_valid[ICACHE_NUM_WAYS-1:0] ) ; assign ic_tag_perr = | (ic_tag_way_perr[ICACHE_NUM_WAYS-1:0] & ic_tag_valid[ICACHE_NUM_WAYS-1:0] ) ;
endmodule // EL2_IC_TAG endmodule // IC_TAG

272
src/main/resources/vsrc/ifu_iccm_mem.sv
View File

@ -19,15 +19,10 @@
// Icache closely coupled memory --- ICCM // Icache closely coupled memory --- ICCM
//******************************************************************************** //********************************************************************************
module el2_ifu_iccm_mem module ifu_iccm_mem
#( `include "parameter.sv"
parameter ICCM_BITS,
parameter ICCM_BANK_INDEX_LO, (
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICCM_NUM_BANKS,
parameter ICCM_BANK_BITS
)(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low input logic rst_l, // reset, active low
@ -41,15 +36,20 @@ module el2_ifu_iccm_mem
input logic [2:0] iccm_wr_size, // ICCM write size input logic [2:0] iccm_wr_size, // ICCM write size
input logic [77:0] iccm_wr_data, // ICCM write data input logic [77:0] iccm_wr_data, // ICCM write data
//input el2_ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, // External packet //input ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, // External packet
input [ICCM_NUM_BANKS-1:0] TEST1, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_TEST1,
input [ICCM_NUM_BANKS-1:0] RME, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RME,
input [ICCM_NUM_BANKS-1:0][3:0] RM, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_0,
input [ICCM_NUM_BANKS-1:0] LS, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_1,
input [ICCM_NUM_BANKS-1:0] DS, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_2,
input [ICCM_NUM_BANKS-1:0] TEST-RNM, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_3,
input [ICCM_NUM_BANKS-1:0] BC1, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_LS,
input [ICCM_NUM_BANKS-1:0] BC2, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_DS,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_SD,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RNM,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_BC1,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_BC2,
output logic [63:0] iccm_rd_data, // ICCM read data output logic [63:0] iccm_rd_data, // ICCM read data
output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc
input logic scan_mode // Scan mode control input logic scan_mode // Scan mode control
@ -121,7 +121,7 @@ module el2_ifu_iccm_mem
iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO]); iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO]);
`ifdef VERILATOR `ifdef VERILATOR
el2_ram #(.depth(1<<ICCM_INDEX_BITS), .width(39)) iccm_bank ( ram #(.depth(1<<ICCM_INDEX_BITS), .width(39)) iccm_bank (
// Primary ports // Primary ports
.ME(iccm_clken[i]), .ME(iccm_clken[i]),
.CLK(clk), .CLK(clk),
@ -131,15 +131,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
`else `else
@ -155,15 +158,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -179,15 +185,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -203,15 +212,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -226,15 +238,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -249,15 +264,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -272,15 +290,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -295,15 +316,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -318,15 +342,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -341,15 +368,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -364,15 +394,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -477,5 +510,4 @@ module el2_ifu_iccm_mem
assign iccm_rd_data[63:0] = {iccm_data[63:0]}; assign iccm_rd_data[63:0] = {iccm_data[63:0]};
assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][38:0]}; assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][38:0]};
endmodule // el2_ifu_iccm_mem endmodule // ifu_iccm_mem

127
src/main/resources/vsrc/lsu_dccm_mem.sv
View File

@ -27,28 +27,25 @@
// //******************************************************************************** // //********************************************************************************
`define EL2_LOCAL_DCCM_RAM_TEST_PORTS .TEST1(TEST1[i]), \
.RME(RME[i]), \ `define LOCAL_DCCM_RAM_TEST_PORTS .TEST1(dccm_ext_in_pkt_TEST1[i]), \
.RM(RM[i][3:0]), \ .RME(dccm_ext_in_pkt_RME[i]), \
.LS(LS[i]), \ .RM_0(dccm_ext_in_pkt_RM_0[i]), \
.DS(DS[i]), \ .RM_1(dccm_ext_in_pkt_RM_1[i]), \
.SD(SD[i]), \ .RM_2(dccm_ext_in_pkt_RM_2[i]), \
.TEST_RNM(TEST_RNM[i]), \ .RM_3(dccm_ext_in_pkt_RM_3[i]), \
.BC1(BC1[i]), \ .LS(dccm_ext_in_pkt_LS[i]), \
.BC2(BC2[i]), \ .DS(dccm_ext_in_pkt_DS[i]), \
.SD(dccm_ext_in_pkt_SD[i]), \
.RNM(dccm_ext_in_pkt_RNM[i]), \
.BC1(dccm_ext_in_pkt_BC1[i]), \
.BC2(dccm_ext_in_pkt_BC2[i]), \
module el2_lsu_dccm_mem module lsu_dccm_mem
#( `include "parameter.sv"
parameter DCCM_BYTE_WIDTH, (
parameter DCCM_BITS,
parameter DCCM_NUM_BANKS,
parameter DCCM_BANK_BITS,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter DCCM_WIDTH_BITS
)(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low input logic rst_l, // reset, active low
@ -62,16 +59,20 @@ module el2_lsu_dccm_mem
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data
//input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, // the dccm packet from the soc
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_TEST1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RME,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_0,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_2,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_3,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_LS,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_DS,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_SD,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RNM,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC2,
//input el2_dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, // the dccm packet from the soc
input [ICCM_NUM_BANKS-1:0] dccm_TEST1,
input [ICCM_NUM_BANKS-1:0] RME,
input [ICCM_NUM_BANKS-1:0][3:0] RM,
input [ICCM_NUM_BANKS-1:0] LS,
input [ICCM_NUM_BANKS-1:0] DS,
input [ICCM_NUM_BANKS-1:0] TEST-RNM,
input [ICCM_NUM_BANKS-1:0] BC1,
input [ICCM_NUM_BANKS-1:0] BC2,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank
@ -79,43 +80,43 @@ module el2_lsu_dccm_mem
); );
localparam DCCM_WIDTH_BITS_INT = $clog2(DCCM_BYTE_WIDTH); //localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH);
localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS); localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS);
localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank
logic [DCCM_NUM_BANKS-1:0] wren_bank; logic [DCCM_NUM_BANKS-1:0] wren_bank;
logic [DCCM_NUM_BANKS-1:0] rden_bank; logic [DCCM_NUM_BANKS-1:0] rden_bank;
logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank; logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank;
logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)] rd_addr_even, rd_addr_odd; logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd;
logic rd_unaligned, wr_unaligned; logic rd_unaligned, wr_unaligned;
logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout; logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout;
logic [DCCM_FDATA_WIDTH-1:0] wrdata; logic [DCCM_FDATA_WIDTH-1:0] wrdata;
logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank; logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank;
logic [(DCCM_WIDTH_BITS_INT+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS_INT] dccm_rd_addr_lo_q; logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_lo_q;
logic [(DCCM_WIDTH_BITS_INT+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS_INT] dccm_rd_addr_hi_q; logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_hi_q;
logic [DCCM_NUM_BANKS-1:0] dccm_clken; logic [DCCM_NUM_BANKS-1:0] dccm_clken;
assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]); assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]); assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
// Align the read data // Align the read data
assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0]; assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0]; assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
// 8 Banks, 16KB each (2048 x 72) // 8 Banks, 16KB each (2048 x 72)
for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank
assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_wr_addr_lo[2+:DCCM_BANK_BITS] == i)); assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_wr_addr_lo[2+:DCCM_BANK_BITS] == i));
assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_rd_addr_lo[2+:DCCM_BANK_BITS] == i)); assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_rd_addr_lo[2+:DCCM_BANK_BITS] == i));
assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ?
dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS] : dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS]) : dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]) :
(((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) & rd_unaligned) ? (((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) & rd_unaligned) ?
dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS] : dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS]); dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]);
assign wr_data_bank[i] = ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? dccm_wr_data_hi[DCCM_FDATA_WIDTH-1:0] : dccm_wr_data_lo[DCCM_FDATA_WIDTH-1:0]; assign wr_data_bank[i] = ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? dccm_wr_data_hi[DCCM_FDATA_WIDTH-1:0] : dccm_wr_data_lo[DCCM_FDATA_WIDTH-1:0];
@ -125,7 +126,7 @@ module el2_lsu_dccm_mem
`ifdef VERILATOR `ifdef VERILATOR
el2_ram #(DCCM_INDEX_DEPTH,39) ram ( ram #(DCCM_INDEX_DEPTH,39) ram (
// Primary ports // Primary ports
.ME(dccm_clken[i]), .ME(dccm_clken[i]),
.CLK(clk), .CLK(clk),
@ -135,7 +136,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
`else `else
@ -151,7 +152,20 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
// .TEST1(dccm_ext_in_pkt_TEST1[i]),
// .RME(dccm_ext_in_pkt_RME[i]),
// .RM_0(dccm_ext_in_pkt_RM_0[i]),
// .RM_1(dccm_ext_in_pkt_RM_1[i]),
// .RM_2(dccm_ext_in_pkt_RM_2[i]),
// .RM_3(dccm_ext_in_pkt_RM_3[i]),
// .LS(dccm_ext_in_pkt_LS[i]),
// .DS(dccm_ext_in_pkt_DS[i]),
// .SD(dccm_ext_in_pkt_SD[i]),
// .RNM(dccm_ext_in_pkt_RNM[i]),
// .BC1(dccm_ext_in_pkt_BC1[i]),
// .BC2(dccm_ext_in_pkt_BC2[i]),
.* .*
); );
end end
@ -166,7 +180,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -181,7 +195,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -196,7 +210,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -211,7 +225,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -226,7 +240,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -241,7 +255,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -256,7 +270,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -271,7 +285,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -286,7 +300,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -295,12 +309,11 @@ module el2_lsu_dccm_mem
end : mem_bank end : mem_bank
// Flops // Flops
rvdff #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .clk(active_clk)); rvdff #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .clk(active_clk));
rvdff #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .clk(active_clk)); rvdff #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .clk(active_clk));
`undef EL2_LOCAL_DCCM_RAM_TEST_PORTS `undef LOCAL_DCCM_RAM_TEST_PORTS
endmodule // el2_lsu_dccm_mem
endmodule // lsu_dccm_mem

127
src/main/resources/vsrc/mem.sv
View File

@ -15,7 +15,11 @@
// limitations under the License. // limitations under the License.
//******************************************************************************** //********************************************************************************
`include "lsu_dccm_mem.sv"
`include "ifu_ic_mem.sv"
`include "ifu_iccm_mem.sv"
module mem module mem
`include "parameter.sv"
( (
input logic clk, input logic clk,
input logic rst_l, input logic rst_l,
@ -38,12 +42,36 @@ module mem
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE //`ifdef DCCM_ENABLE
input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, //input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_TEST1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RME,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_0,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_2,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_3,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_LS,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_DS,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_SD,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RNM,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC2,
//`endif //`endif
//ICCM ports //ICCM ports
input ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, //input ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_TEST1,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RME,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_0,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_1,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_2,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_3,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_LS,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_DS,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_SD,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RNM,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_BC1,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_BC2,
input logic [ICCM_BITS-1:1] iccm_rw_addr, input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
@ -64,10 +92,49 @@ module mem
input logic ic_rd_en, input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel input logic ic_sel_premux_data, // Premux data sel
input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_TEST1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RME,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_0,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_2,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_3,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_LS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_DS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_SD,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RNM,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_BC1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_BC2,
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_TEST1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RME,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_0,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_2,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_3,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_LS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_DS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_SD,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RNM,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC2,
//input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_TEST1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RME,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_0,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_2,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_3,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_LS,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_DS,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_SD,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RNM,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC2,
// input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache. input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
@ -77,7 +144,7 @@ module mem
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ictag_debug_rd_data,// Debug icache tag. output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
@ -90,19 +157,58 @@ module mem
); );
logic active_clk; logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_TEST1;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RME;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_0;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_1;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_2;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_3;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_LS;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_DS;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_SD;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RNM;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC1;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC2;
logic active_clk;
assign ic_data_ext_in_pkt_TEST1[0] = ic_data_ext_in_pkt_0_TEST1 ;
assign ic_data_ext_in_pkt_RME[0] = ic_data_ext_in_pkt_0_RME;
assign ic_data_ext_in_pkt_RM_0[0] = ic_data_ext_in_pkt_0_RM_0;
assign ic_data_ext_in_pkt_RM_1[0] = ic_data_ext_in_pkt_0_RM_1;
assign ic_data_ext_in_pkt_RM_2[0] = ic_data_ext_in_pkt_0_RM_2;
assign ic_data_ext_in_pkt_RM_3[0] = ic_data_ext_in_pkt_0_RM_3;
assign ic_data_ext_in_pkt_LS[0] = ic_data_ext_in_pkt_0_LS;
assign ic_data_ext_in_pkt_DS[0] = ic_data_ext_in_pkt_0_DS;
assign ic_data_ext_in_pkt_SD[0] = ic_data_ext_in_pkt_0_SD;
assign ic_data_ext_in_pkt_RNM[0] = ic_data_ext_in_pkt_0_RNM;
assign ic_data_ext_in_pkt_BC1[0] = ic_data_ext_in_pkt_0_BC1;
assign ic_data_ext_in_pkt_BC2[0] = ic_data_ext_in_pkt_0_BC2;
assign ic_data_ext_in_pkt_TEST1[1] = ic_data_ext_in_pkt_1_TEST1 ;
assign ic_data_ext_in_pkt_RME[1] = ic_data_ext_in_pkt_1_RME;
assign ic_data_ext_in_pkt_RM_0[1] = ic_data_ext_in_pkt_1_RM_0;
assign ic_data_ext_in_pkt_RM_1[1] = ic_data_ext_in_pkt_1_RM_1;
assign ic_data_ext_in_pkt_RM_2[1] = ic_data_ext_in_pkt_1_RM_2;
assign ic_data_ext_in_pkt_RM_3[1] = ic_data_ext_in_pkt_1_RM_3;
assign ic_data_ext_in_pkt_LS[1] = ic_data_ext_in_pkt_1_LS;
assign ic_data_ext_in_pkt_DS[1] = ic_data_ext_in_pkt_1_DS;
assign ic_data_ext_in_pkt_SD[1] = ic_data_ext_in_pkt_1_SD;
assign ic_data_ext_in_pkt_RNM[1] = ic_data_ext_in_pkt_1_RNM;
assign ic_data_ext_in_pkt_BC1[1] = ic_data_ext_in_pkt_1_BC1;
assign ic_data_ext_in_pkt_BC2[1] = ic_data_ext_in_pkt_1_BC2;
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* ); rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
// DCCM Instantiation // DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem dccm #( lsu_dccm_mem #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH), .DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS), .DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS), .DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS), .DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE), .DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH), .DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH),
.DCCM_WIDTH_BITS(DCCM_WIDTH_BITS))( .DCCM_WIDTH_BITS(DCCM_WIDTH_BITS)) dccm (
.clk_override(dccm_clk_override), .clk_override(dccm_clk_override),
.* .*
); );
@ -142,7 +248,7 @@ else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0; assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ; assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ; assign ic_rd_data = '0 ;
assign ictag_debug_rd_data = '0 ; assign ic_tag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE ) end // else: !if( ICACHE_ENABLE )
@ -167,4 +273,3 @@ end
endmodule endmodule

471
target/scala-2.12/classes/vsrc/ifu_ic_mem.sv
View File

@ -17,31 +17,11 @@
//////////////////////////////////////////////////// ////////////////////////////////////////////////////
// ICACHE DATA & TAG MODULE WRAPPER // // ICACHE DATA & TAG MODULE WRAPPER //
///////////////////////////////////////////////////// /////////////////////////////////////////////////////
module el2_ifu_ic_mem
#(
parameter ICACHE_NUM_WAYS, module ifu_ic_mem
parameter ICACHE_BANKS_WAY, `include "parameter.sv"
parameter ICACHE_INDEX_HI,
parameter ICACHE_TAG_INDEX_LO,
parameter ICACHE_TAG_LO,
parameter ICACHE_DATA_INDEX_LO,
parameter ICACHE_NUM_BYPASS,
parameter ICACHE_LN_SZ,
parameter ICACHE_BANK_HI,
parameter ICACHE_BANK_LO,
parameter ICACHE_WAYPACK,
parameter ICACHE_NUM_BYPASS_WIDTH,
parameter ICACHE_BYPASS_ENABLE,
parameter ICACHE_ECC,
parameter ICACHE_DATA_DEPTH,
parameter ICACHE_BANK_BITS,
parameter ICACHE_BEAT_ADDR_HI,
parameter ICACHE_BEAT_BITS,
parameter ICACHE_TAG_NUM_BYPASS,
parameter ICACHE_TAG_NUM_BYPASS_WIDTH,
parameter ICACHE_TAG_BYPASS_ENABLE,
parameter ICACHE_TAG_DEPTH,
)
( (
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
@ -60,35 +40,55 @@ module el2_ifu_ic_mem
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Select the pre_muxed data input logic ic_sel_premux_data, // Select the pre_muxed data
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ictag_debug_rd_data,// Debug icache tag. output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
input logic [70:0] ic_debug_wr_data, // Debug wr cache. input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // ecc error per bank output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // ecc error per bank
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid from the I$ tag valid outside (in flops). input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid from the I$ tag valid outside (in flops).
//input el2_ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc // input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] TEST1, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_TEST1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] RME, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RME,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0][3:0] RM, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_0,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] LS, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] DS, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_2,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] TEST-RNM, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_3,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] BC1, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_LS,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] BC2, input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_DS,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_SD,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RNM,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC2,
//input el2_ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, // this is being driven by the top level for soc testing/etc // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_TEST1,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RME,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_0,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_1,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_2,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_3,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_LS,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_DS,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RNM,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC1,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC2,
input [ICACHE_NUM_WAYS-1:0] TEST1, //input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, // this is being driven by the top level for soc testing/etc
input [ICACHE_NUM_WAYS-1:0] RME, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_TEST1,
input [ICACHE_NUM_WAYS-1:0][3:0] RM, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RME,
input [ICACHE_NUM_WAYS-1:0] LS, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_0,
input [ICACHE_NUM_WAYS-1:0] DS, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_1,
input [ICACHE_NUM_WAYS-1:0] TEST-RNM, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_2,
input [ICACHE_NUM_WAYS-1:0] BC1, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_3,
input [ICACHE_NUM_WAYS-1:0] BC2, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_LS,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_DS,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_SD,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RNM,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC2,
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit, // ic_rd_hit[3:0] output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit, // ic_rd_hit[3:0]
output logic ic_tag_perr, // Tag Parity error output logic ic_tag_perr, // Tag Parity error
@ -98,7 +98,7 @@ module el2_ifu_ic_mem
EL2_IC_TAG #(.pt(pt)) ic_tag_inst IC_TAG ic_tag_inst
( (
.*, .*,
.ic_wr_en (ic_wr_en[ICACHE_NUM_WAYS-1:0]), .ic_wr_en (ic_wr_en[ICACHE_NUM_WAYS-1:0]),
@ -106,7 +106,7 @@ module el2_ifu_ic_mem
.ic_rw_addr (ic_rw_addr[31:3]) .ic_rw_addr (ic_rw_addr[31:3])
) ; ) ;
EL2_IC_DATA #(.pt(pt)) ic_data_inst IC_DATA ic_data_inst
( (
.*, .*,
.ic_wr_en (ic_wr_en[ICACHE_NUM_WAYS-1:0]), .ic_wr_en (ic_wr_en[ICACHE_NUM_WAYS-1:0]),
@ -120,10 +120,8 @@ module el2_ifu_ic_mem
///////////////////////////////////////////////// /////////////////////////////////////////////////
////// ICACHE DATA MODULE //////////////////// ////// ICACHE DATA MODULE ////////////////////
///////////////////////////////////////////////// /////////////////////////////////////////////////
module EL2_IC_DATA module IC_DATA
#( `include "parameter.sv"
`include "el2_param.vh"
)
( (
input logic clk, input logic clk,
input logic active_clk, input logic active_clk,
@ -134,7 +132,9 @@ module EL2_IC_DATA
input logic [ICACHE_NUM_WAYS-1:0]ic_wr_en, input logic [ICACHE_NUM_WAYS-1:0]ic_wr_en,
input logic ic_rd_en, // Read enable input logic ic_rd_en, // Read enable
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC // input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache. input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
@ -149,16 +149,31 @@ module EL2_IC_DATA
input logic ic_sel_premux_data, // Select the pre_muxed data input logic ic_sel_premux_data, // Select the pre_muxed data
input logic [ICACHE_NUM_WAYS-1:0]ic_rd_hit, input logic [ICACHE_NUM_WAYS-1:0]ic_rd_hit,
//input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_TEST1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RME,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_0,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_2,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_3,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_LS,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_DS,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_SD,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RNM,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC2,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] TEST1, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_TEST1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] RME, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RME,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0][3:0] RM, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_0,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] LS, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_1,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] DS, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_2,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] TEST-RNM, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_3,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] BC1, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_LS,
input [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] BC2, // input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_DS,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RNM,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC1,
// input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC2,
input logic scan_mode input logic scan_mode
) ; ) ;
@ -295,7 +310,8 @@ module EL2_IC_DATA
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] any_bypass_up; logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] any_bypass_up;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] any_addr_match_up; logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] any_addr_match_up;
`define EL2_IC_DATA_SRAM(depth,width) \
`define IC_DATA_SRAM(depth,width) \
ram_``depth``x``width ic_bank_sb_way_data ( \ ram_``depth``x``width ic_bank_sb_way_data ( \
.ME(ic_bank_way_clken_final_up[i][k]), \ .ME(ic_bank_way_clken_final_up[i][k]), \
.WE (ic_b_sb_wren[k][i]), \ .WE (ic_b_sb_wren[k][i]), \
@ -304,17 +320,20 @@ module EL2_IC_DATA
.Q (wb_dout_pre_up[i][k]), \ .Q (wb_dout_pre_up[i][k]), \
.CLK (clk), \ .CLK (clk), \
.ROP ( ), \ .ROP ( ), \
.TEST1(TEST1[i][k]), \ .TEST1(ic_data_ext_in_pkt_TEST1[i][k]), \
.RME(RME[i][k]), \ .RME(ic_data_ext_in_pkt_RME[i][k]), \
.RM(RM[i][k]), \ .RM_0(ic_data_ext_in_pkt_RM_0[i][k]), \
.RM_1(ic_data_ext_in_pkt_RM_1[i][k]), \
.RM_2(ic_data_ext_in_pkt_RM_2[i][k]), \
.RM_3(ic_data_ext_in_pkt_RM_3[i][k]), \
\ \
.LS(LS[i][k]), \ .LS(ic_data_ext_in_pkt_LS[i][k]), \
.DS(DS[i][k]), \ .DS(ic_data_ext_in_pkt_DS[i][k]), \
.SD(SD[i][k]), \ .SD(ic_data_ext_in_pkt_SD[i][k]), \
\ \
.TEST_RNM(TEST_RNM[i][k]), \ .RNM(ic_data_ext_in_pkt_RNM[i][k]), \
.BC1(BC1[i][k]), \ .BC1(ic_data_ext_in_pkt_BC1[i][k]), \
.BC2(BC2[i][k]) \ .BC2(ic_data_ext_in_pkt_BC2[i][k]) \
); \ ); \
if (ICACHE_BYPASS_ENABLE == 1) begin \ if (ICACHE_BYPASS_ENABLE == 1) begin \
assign wrptr_in_up[i][k] = (wrptr_up[i][k] == (ICACHE_NUM_BYPASS-1)) ? '0 : (wrptr_up[i][k] + 1'd1); \ assign wrptr_in_up[i][k] = (wrptr_up[i][k] == (ICACHE_NUM_BYPASS-1)) ? '0 : (wrptr_up[i][k] + 1'd1); \
@ -372,28 +391,28 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [ICACHE_NUM_BYPASS-1:0] [71-1:0] wb_dout_hold_up; logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [ICACHE_NUM_BYPASS-1:0] [71-1:0] wb_dout_hold_up;
if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192 if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192
`EL2_IC_DATA_SRAM(8192,71) `IC_DATA_SRAM(8192,71)
end end
else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096 else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096
`EL2_IC_DATA_SRAM(4096,71) `IC_DATA_SRAM(4096,71)
end end
else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048 else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048
`EL2_IC_DATA_SRAM(2048,71) `IC_DATA_SRAM(2048,71)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024 else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024
`EL2_IC_DATA_SRAM(1024,71) `IC_DATA_SRAM(1024,71)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512 else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512
`EL2_IC_DATA_SRAM(512,71) `IC_DATA_SRAM(512,71)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256 else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256
`EL2_IC_DATA_SRAM(256,71) `IC_DATA_SRAM(256,71)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128 else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128
`EL2_IC_DATA_SRAM(128,71) `IC_DATA_SRAM(128,71)
end end
else begin : size_64 else begin : size_64
`EL2_IC_DATA_SRAM(64,71) `IC_DATA_SRAM(64,71)
end end
end // if (ICACHE_ECC) end // if (ICACHE_ECC)
@ -401,28 +420,28 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [68-1:0] wb_dout_pre_up; // data and its bit enables logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [68-1:0] wb_dout_pre_up; // data and its bit enables
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [ICACHE_NUM_BYPASS-1:0] [68-1:0] wb_dout_hold_up; logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] [ICACHE_NUM_BYPASS-1:0] [68-1:0] wb_dout_hold_up;
if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192 if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192
`EL2_IC_DATA_SRAM(8192,68) `IC_DATA_SRAM(8192,68)
end end
else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096 else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096
`EL2_IC_DATA_SRAM(4096,68) `IC_DATA_SRAM(4096,68)
end end
else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048 else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048
`EL2_IC_DATA_SRAM(2048,68) `IC_DATA_SRAM(2048,68)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024 else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024
`EL2_IC_DATA_SRAM(1024,68) `IC_DATA_SRAM(1024,68)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512 else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512
`EL2_IC_DATA_SRAM(512,68) `IC_DATA_SRAM(512,68)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256 else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256
`EL2_IC_DATA_SRAM(256,68) `IC_DATA_SRAM(256,68)
end end
else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128 else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128
`EL2_IC_DATA_SRAM(128,68) `IC_DATA_SRAM(128,68)
end end
else begin : size_64 else begin : size_64
`EL2_IC_DATA_SRAM(64,68) `IC_DATA_SRAM(64,68)
end end
end // else: !if(ICACHE_ECC) end // else: !if(ICACHE_ECC)
end // block: BANKS_WAY end // block: BANKS_WAY
@ -446,7 +465,7 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
// SRAM macros // SRAM macros
`define EL2_PACKED_IC_DATA_SRAM(depth,width,waywidth) \ `define PACKED_IC_DATA_SRAM(depth,width,waywidth) \
ram_be_``depth``x``width ic_bank_sb_way_data ( \ ram_be_``depth``x``width ic_bank_sb_way_data ( \
.CLK (clk), \ .CLK (clk), \
.WE (|ic_b_sb_wren[k]), // OR of all the ways in the bank \ .WE (|ic_b_sb_wren[k]), // OR of all the ways in the bank \
@ -456,17 +475,20 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
.Q (wb_packeddout_pre[k]), \ .Q (wb_packeddout_pre[k]), \
.ME (|ic_bank_way_clken_final[k]), \ .ME (|ic_bank_way_clken_final[k]), \
.ROP ( ), \ .ROP ( ), \
.TEST1 (ic_data_ext_in_pkt[0][k].TEST1), \ .TEST1 (ic_data_ext_in_pkt_TEST1[0][k]), \
.RME (ic_data_ext_in_pkt[0][k].RME), \ .RME (ic_data_ext_in_pkt_RME[0][k]), \
.RM (ic_data_ext_in_pkt[0][k].RM), \ .RM_0 (ic_data_ext_in_pkt_RM_0[0][k]), \
.RM_1 (ic_data_ext_in_pkt_RM_1[0][k]), \
.RM_2 (ic_data_ext_in_pkt_RM_2[0][k]), \
.RM_3 (ic_data_ext_in_pkt_RM_3[0][k]), \
\ \
.LS (ic_data_ext_in_pkt[0][k].LS), \ .LS (ic_data_ext_in_pkt_LS[0][k]), \
.DS (ic_data_ext_in_pkt[0][k].DS), \ .DS (ic_data_ext_in_pkt_DS[0][k]), \
.SD (ic_data_ext_in_pkt[0][k].SD), \ .SD (ic_data_ext_in_pkt_SD[0][k]), \
\ \
.TEST_RNM (ic_data_ext_in_pkt[0][k].TEST_RNM), \ .RNM (ic_data_ext_in_pkt_RNM[0][k]), \
.BC1 (ic_data_ext_in_pkt[0][k].BC1), \ .BC1 (ic_data_ext_in_pkt_BC1[0][k]), \
.BC2 (ic_data_ext_in_pkt[0][k].BC2) \ .BC2 (ic_data_ext_in_pkt_BC2[0][k]) \
); \ ); \
\ \
if (ICACHE_BYPASS_ENABLE == 1) begin \ if (ICACHE_BYPASS_ENABLE == 1) begin \
@ -547,73 +569,73 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
// SRAMS with ECC (single/double detect; no correct) // SRAMS with ECC (single/double detect; no correct)
if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192 if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(8192,284,71) // 64b data + 7b ecc `PACKED_IC_DATA_SRAM(8192,284,71) // 64b data + 7b ecc
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(8192,142,71) `PACKED_IC_DATA_SRAM(8192,142,71)
end // block: WAYS end // block: WAYS
end // block: size_8192 end // block: size_8192
else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096 else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(4096,284,71) `PACKED_IC_DATA_SRAM(4096,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(4096,142,71) `PACKED_IC_DATA_SRAM(4096,142,71)
end // block: WAYS end // block: WAYS
end // block: size_4096 end // block: size_4096
else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048 else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(2048,284,71) `PACKED_IC_DATA_SRAM(2048,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(2048,142,71) `PACKED_IC_DATA_SRAM(2048,142,71)
end // block: WAYS end // block: WAYS
end // block: size_2048 end // block: size_2048
else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024 else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(1024,284,71) `PACKED_IC_DATA_SRAM(1024,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(1024,142,71) `PACKED_IC_DATA_SRAM(1024,142,71)
end // block: WAYS end // block: WAYS
end // block: size_1024 end // block: size_1024
else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512 else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(512,284,71) `PACKED_IC_DATA_SRAM(512,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(512,142,71) `PACKED_IC_DATA_SRAM(512,142,71)
end // block: WAYS end // block: WAYS
end // block: size_512 end // block: size_512
else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256 else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(256,284,71) `PACKED_IC_DATA_SRAM(256,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(256,142,71) `PACKED_IC_DATA_SRAM(256,142,71)
end // block: WAYS end // block: WAYS
end // block: size_256 end // block: size_256
else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128 else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(128,284,71) `PACKED_IC_DATA_SRAM(128,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(128,142,71) `PACKED_IC_DATA_SRAM(128,142,71)
end // block: WAYS end // block: WAYS
end // block: size_128 end // block: size_128
else begin : size_64 else begin : size_64
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(64,284,71) `PACKED_IC_DATA_SRAM(64,284,71)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(64,142,71) `PACKED_IC_DATA_SRAM(64,142,71)
end // block: WAYS end // block: WAYS
end // block: size_64 end // block: size_64
@ -637,73 +659,73 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
// SRAMs with parity // SRAMs with parity
if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192 if ($clog2(ICACHE_DATA_DEPTH) == 13 ) begin : size_8192
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(8192,272,68) // 64b data + 4b parity `PACKED_IC_DATA_SRAM(8192,272,68) // 64b data + 4b parity
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(8192,136,68) `PACKED_IC_DATA_SRAM(8192,136,68)
end // block: WAYS end // block: WAYS
end // block: size_8192 end // block: size_8192
else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096 else if ($clog2(ICACHE_DATA_DEPTH) == 12 ) begin : size_4096
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(4096,272,68) `PACKED_IC_DATA_SRAM(4096,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(4096,136,68) `PACKED_IC_DATA_SRAM(4096,136,68)
end // block: WAYS end // block: WAYS
end // block: size_4096 end // block: size_4096
else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048 else if ($clog2(ICACHE_DATA_DEPTH) == 11 ) begin : size_2048
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(2048,272,68) `PACKED_IC_DATA_SRAM(2048,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(2048,136,68) `PACKED_IC_DATA_SRAM(2048,136,68)
end // block: WAYS end // block: WAYS
end // block: size_2048 end // block: size_2048
else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024 else if ( $clog2(ICACHE_DATA_DEPTH) == 10 ) begin : size_1024
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(1024,272,68) `PACKED_IC_DATA_SRAM(1024,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(1024,136,68) `PACKED_IC_DATA_SRAM(1024,136,68)
end // block: WAYS end // block: WAYS
end // block: size_1024 end // block: size_1024
else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512 else if ( $clog2(ICACHE_DATA_DEPTH) == 9 ) begin : size_512
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(512,272,68) `PACKED_IC_DATA_SRAM(512,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(512,136,68) `PACKED_IC_DATA_SRAM(512,136,68)
end // block: WAYS end // block: WAYS
end // block: size_512 end // block: size_512
else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256 else if ( $clog2(ICACHE_DATA_DEPTH) == 8 ) begin : size_256
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(256,272,68) `PACKED_IC_DATA_SRAM(256,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(256,136,68) `PACKED_IC_DATA_SRAM(256,136,68)
end // block: WAYS end // block: WAYS
end // block: size_256 end // block: size_256
else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128 else if ( $clog2(ICACHE_DATA_DEPTH) == 7 ) begin : size_128
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(128,272,68) `PACKED_IC_DATA_SRAM(128,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(128,136,68) `PACKED_IC_DATA_SRAM(128,136,68)
end // block: WAYS end // block: WAYS
end // block: size_128 end // block: size_128
else begin : size_64 else begin : size_64
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(64,272,68) `PACKED_IC_DATA_SRAM(64,272,68)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_PACKED_IC_DATA_SRAM(64,136,68) `PACKED_IC_DATA_SRAM(64,136,68)
end // block: WAYS end // block: WAYS
end // block: size_64 end // block: size_64
@ -720,8 +742,8 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
if ( ICACHE_ECC ) begin : ECC1_MUX if ( ICACHE_ECC ) begin : ECC1_MUX
assign ic_bank_wr_data[1] = ic_wr_data[1][70:0]; assign ic_bank_wr_data[1] = ic_wr_data_1[70:0];
assign ic_bank_wr_data[0] = ic_wr_data[0][70:0]; assign ic_bank_wr_data[0] = ic_wr_data_0[70:0];
always_comb begin : rd_mux always_comb begin : rd_mux
wb_dout_way_pre[ICACHE_NUM_WAYS-1:0] = '0; wb_dout_way_pre[ICACHE_NUM_WAYS-1:0] = '0;
@ -772,8 +794,8 @@ if (ICACHE_BYPASS_ENABLE == 1) begin \
end // if ( ICACHE_ECC ) end // if ( ICACHE_ECC )
else begin : ECC0_MUX else begin : ECC0_MUX
assign ic_bank_wr_data[1] = ic_wr_data[1][70:0]; assign ic_bank_wr_data[1] = ic_wr_data_1[70:0];
assign ic_bank_wr_data[0] = ic_wr_data[0][70:0]; assign ic_bank_wr_data[0] = ic_wr_data_0[70:0];
always_comb begin : rd_mux always_comb begin : rd_mux
wb_dout_way_pre[ICACHE_NUM_WAYS-1:0] = '0; wb_dout_way_pre[ICACHE_NUM_WAYS-1:0] = '0;
@ -830,7 +852,7 @@ else begin : ECC0_MUX
end // else: !if( ICACHE_ECC ) end // else: !if( ICACHE_ECC )
endmodule // EL2_IC_DATA endmodule // IC_DATA
//============================================================================================================================================================= //=============================================================================================================================================================
///\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ END OF IC DATA MODULE \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ ///\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ END OF IC DATA MODULE \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/
@ -840,10 +862,8 @@ endmodule // EL2_IC_DATA
///////////////////////////////////////////////// /////////////////////////////////////////////////
////// ICACHE TAG MODULE //////////////////// ////// ICACHE TAG MODULE ////////////////////
///////////////////////////////////////////////// /////////////////////////////////////////////////
module EL2_IC_TAG module IC_TAG
#( `include "parameter.sv"
`include "el2_param.vh"
)
( (
input logic clk, input logic clk,
input logic active_clk, input logic active_clk,
@ -862,18 +882,20 @@ module EL2_IC_TAG
input logic ic_debug_wr_en, // Icache debug wr input logic ic_debug_wr_en, // Icache debug wr
input logic ic_debug_tag_array, // Debug tag array input logic ic_debug_tag_array, // Debug tag array
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
input el2_ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, // input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_TEST1,
input [ICACHE_NUM_WAYS-1:0] TEST1, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RME,
input [ICACHE_NUM_WAYS-1:0] RME, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_0,
input [ICACHE_NUM_WAYS-1:0][3:0] RM, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_1,
input [ICACHE_NUM_WAYS-1:0] LS, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_2,
input [ICACHE_NUM_WAYS-1:0] DS, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_3,
input [ICACHE_NUM_WAYS-1:0] TEST-RNM, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_LS,
input [ICACHE_NUM_WAYS-1:0] BC1, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_DS,
input [ICACHE_NUM_WAYS-1:0] BC2, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_SD,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RNM,
output logic [25:0] ictag_debug_rd_data, input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC2,
output logic [25:0] ic_tag_debug_rd_data,
input logic [70:0] ic_debug_wr_data, // Debug wr cache. input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit, output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
@ -1012,7 +1034,7 @@ end // block: OTHERS
logic [ICACHE_NUM_WAYS-1:0] any_addr_match; logic [ICACHE_NUM_WAYS-1:0] any_addr_match;
logic [ICACHE_NUM_WAYS-1:0] ic_tag_clken_final; logic [ICACHE_NUM_WAYS-1:0] ic_tag_clken_final;
`define EL2_IC_TAG_SRAM(depth,width) \ `define IC_TAG_SRAM(depth,width) \
ram_``depth``x``width ic_way_tag ( \ ram_``depth``x``width ic_way_tag ( \
.ME(ic_tag_clken_final[i]), \ .ME(ic_tag_clken_final[i]), \
.WE (ic_tag_wren_q[i]), \ .WE (ic_tag_wren_q[i]), \
@ -1022,17 +1044,20 @@ end // block: OTHERS
.CLK (clk), \ .CLK (clk), \
.ROP ( ), \ .ROP ( ), \
\ \
.TEST1(ic_tag_ext_in_pkt[i].TEST1[i]), \ .TEST1(ic_tag_ext_in_pkt_TEST1[i]), \
.RME(ic_tag_ext_in_pkt[i].RME[i]), \ .RME(ic_tag_ext_in_pkt_RME[i]), \
.RM(ic_tag_ext_in_pkt[i].RM[i]), \ .RM_0(ic_tag_ext_in_pkt_RM_0[i]), \
.RM_1(ic_tag_ext_in_pkt_RM_1[i]),\
.RM_2(ic_tag_ext_in_pkt_RM_2[i]),\
.RM_3(ic_tag_ext_in_pkt_RM_3[i]), \
\ \
.LS(ic_tag_ext_in_pkt[i].LS[i]), \ .LS(ic_tag_ext_in_pkt_LS[i]), \
.DS(ic_tag_ext_in_pkt[i].DS[i]), \ .DS(ic_tag_ext_in_pkt_DS[i]), \
.SD(ic_tag_ext_in_pkt[i].SD[i]), \ .SD(ic_tag_ext_in_pkt_SD[i]), \
\ \
.TEST_RNM(ic_tag_ext_in_pkt[i].TEST_RNM[i]), \ .RNM(ic_tag_ext_in_pkt_RNM[i]), \
.BC1(ic_tag_ext_in_pkt[i].BC1[i]), \ .BC1(ic_tag_ext_in_pkt_BC1[i]), \
.BC2(ic_tag_ext_in_pkt[i].BC2[i]) \ .BC2(ic_tag_ext_in_pkt_BC2[i]) \
\ \
); \ ); \
\ \
@ -1105,28 +1130,28 @@ end // block: OTHERS
logic [ICACHE_NUM_WAYS-1:0] [ICACHE_TAG_NUM_BYPASS-1:0][25 :0] wb_dout_hold; logic [ICACHE_NUM_WAYS-1:0] [ICACHE_TAG_NUM_BYPASS-1:0][25 :0] wb_dout_hold;
if (ICACHE_TAG_DEPTH == 32) begin : size_32 if (ICACHE_TAG_DEPTH == 32) begin : size_32
`EL2_IC_TAG_SRAM(32,26) `IC_TAG_SRAM(32,26)
end // if (ICACHE_TAG_DEPTH == 32) end // if (ICACHE_TAG_DEPTH == 32)
if (ICACHE_TAG_DEPTH == 64) begin : size_64 if (ICACHE_TAG_DEPTH == 64) begin : size_64
`EL2_IC_TAG_SRAM(64,26) `IC_TAG_SRAM(64,26)
end // if (ICACHE_TAG_DEPTH == 64) end // if (ICACHE_TAG_DEPTH == 64)
if (ICACHE_TAG_DEPTH == 128) begin : size_128 if (ICACHE_TAG_DEPTH == 128) begin : size_128
`EL2_IC_TAG_SRAM(128,26) `IC_TAG_SRAM(128,26)
end // if (ICACHE_TAG_DEPTH == 128) end // if (ICACHE_TAG_DEPTH == 128)
if (ICACHE_TAG_DEPTH == 256) begin : size_256 if (ICACHE_TAG_DEPTH == 256) begin : size_256
`EL2_IC_TAG_SRAM(256,26) `IC_TAG_SRAM(256,26)
end // if (ICACHE_TAG_DEPTH == 256) end // if (ICACHE_TAG_DEPTH == 256)
if (ICACHE_TAG_DEPTH == 512) begin : size_512 if (ICACHE_TAG_DEPTH == 512) begin : size_512
`EL2_IC_TAG_SRAM(512,26) `IC_TAG_SRAM(512,26)
end // if (ICACHE_TAG_DEPTH == 512) end // if (ICACHE_TAG_DEPTH == 512)
if (ICACHE_TAG_DEPTH == 1024) begin : size_1024 if (ICACHE_TAG_DEPTH == 1024) begin : size_1024
`EL2_IC_TAG_SRAM(1024,26) `IC_TAG_SRAM(1024,26)
end // if (ICACHE_TAG_DEPTH == 1024) end // if (ICACHE_TAG_DEPTH == 1024)
if (ICACHE_TAG_DEPTH == 2048) begin : size_2048 if (ICACHE_TAG_DEPTH == 2048) begin : size_2048
`EL2_IC_TAG_SRAM(2048,26) `IC_TAG_SRAM(2048,26)
end // if (ICACHE_TAG_DEPTH == 2048) end // if (ICACHE_TAG_DEPTH == 2048)
if (ICACHE_TAG_DEPTH == 4096) begin : size_4096 if (ICACHE_TAG_DEPTH == 4096) begin : size_4096
`EL2_IC_TAG_SRAM(4096,26) `IC_TAG_SRAM(4096,26)
end // if (ICACHE_TAG_DEPTH == 4096) end // if (ICACHE_TAG_DEPTH == 4096)
assign w_tout[i][31:ICACHE_TAG_LO] = ic_tag_data_raw[i][31-ICACHE_TAG_LO:0] ; assign w_tout[i][31:ICACHE_TAG_LO] = ic_tag_data_raw[i][31-ICACHE_TAG_LO:0] ;
@ -1149,28 +1174,28 @@ end // block: OTHERS
assign ic_tag_data_raw_pre[i][25:22] = '0 ; assign ic_tag_data_raw_pre[i][25:22] = '0 ;
if (ICACHE_TAG_DEPTH == 32) begin : size_32 if (ICACHE_TAG_DEPTH == 32) begin : size_32
`EL2_IC_TAG_SRAM(32,22) `IC_TAG_SRAM(32,22)
end // if (ICACHE_TAG_DEPTH == 32) end // if (ICACHE_TAG_DEPTH == 32)
if (ICACHE_TAG_DEPTH == 64) begin : size_64 if (ICACHE_TAG_DEPTH == 64) begin : size_64
`EL2_IC_TAG_SRAM(64,22) `IC_TAG_SRAM(64,22)
end // if (ICACHE_TAG_DEPTH == 64) end // if (ICACHE_TAG_DEPTH == 64)
if (ICACHE_TAG_DEPTH == 128) begin : size_128 if (ICACHE_TAG_DEPTH == 128) begin : size_128
`EL2_IC_TAG_SRAM(128,22) `IC_TAG_SRAM(128,22)
end // if (ICACHE_TAG_DEPTH == 128) end // if (ICACHE_TAG_DEPTH == 128)
if (ICACHE_TAG_DEPTH == 256) begin : size_256 if (ICACHE_TAG_DEPTH == 256) begin : size_256
`EL2_IC_TAG_SRAM(256,22) `IC_TAG_SRAM(256,22)
end // if (ICACHE_TAG_DEPTH == 256) end // if (ICACHE_TAG_DEPTH == 256)
if (ICACHE_TAG_DEPTH == 512) begin : size_512 if (ICACHE_TAG_DEPTH == 512) begin : size_512
`EL2_IC_TAG_SRAM(512,22) `IC_TAG_SRAM(512,22)
end // if (ICACHE_TAG_DEPTH == 512) end // if (ICACHE_TAG_DEPTH == 512)
if (ICACHE_TAG_DEPTH == 1024) begin : size_1024 if (ICACHE_TAG_DEPTH == 1024) begin : size_1024
`EL2_IC_TAG_SRAM(1024,22) `IC_TAG_SRAM(1024,22)
end // if (ICACHE_TAG_DEPTH == 1024) end // if (ICACHE_TAG_DEPTH == 1024)
if (ICACHE_TAG_DEPTH == 2048) begin : size_2048 if (ICACHE_TAG_DEPTH == 2048) begin : size_2048
`EL2_IC_TAG_SRAM(2048,22) `IC_TAG_SRAM(2048,22)
end // if (ICACHE_TAG_DEPTH == 2048) end // if (ICACHE_TAG_DEPTH == 2048)
if (ICACHE_TAG_DEPTH == 4096) begin : size_4096 if (ICACHE_TAG_DEPTH == 4096) begin : size_4096
`EL2_IC_TAG_SRAM(4096,22) `IC_TAG_SRAM(4096,22)
end // if (ICACHE_TAG_DEPTH == 4096) end // if (ICACHE_TAG_DEPTH == 4096)
assign w_tout[i][31:ICACHE_TAG_LO] = ic_tag_data_raw[i][31-ICACHE_TAG_LO:0] ; assign w_tout[i][31:ICACHE_TAG_LO] = ic_tag_data_raw[i][31-ICACHE_TAG_LO:0] ;
@ -1214,7 +1239,7 @@ end // block: OTHERS
logic any_addr_match; logic any_addr_match;
logic ic_tag_clken_final; logic ic_tag_clken_final;
`define EL2_IC_TAG_PACKED_SRAM(depth,width) \ `define IC_TAG_PACKED_SRAM(depth,width) \
ram_be_``depth``x``width ic_way_tag ( \ ram_be_``depth``x``width ic_way_tag ( \
.ME ( ic_tag_clken_final), \ .ME ( ic_tag_clken_final), \
.WE (|ic_tag_wren_q[ICACHE_NUM_WAYS-1:0]), \ .WE (|ic_tag_wren_q[ICACHE_NUM_WAYS-1:0]), \
@ -1226,17 +1251,20 @@ end // block: OTHERS
.CLK (clk), \ .CLK (clk), \
.ROP ( ), \ .ROP ( ), \
\ \
.TEST1 (TEST1[0]), \ .TEST1 (ic_tag_ext_in_pkt_TEST1[0]), \
.RME (RME[0]), \ .RME (ic_tag_ext_in_pkt_RME[0]), \
.RM (RM[0]), \ .RM_0 (ic_tag_ext_in_pkt_RM_0[0]), \
.RM_1 (ic_tag_ext_in_pkt_RM_1[0]), \
.RM_2 (ic_tag_ext_in_pkt_RM_2[0]), \
.RM_3 (ic_tag_ext_in_pkt_RM_3[0]), \
\ \
.LS (LS[0]), \ .LS (ic_tag_ext_in_pkt_LS[0]), \
.DS (DS[0]), \ .DS (ic_tag_ext_in_pkt_DS[0]), \
.SD (SD[0]), \ .SD (ic_tag_ext_in_pkt_SD[0]), \
\ \
.TEST_RNM (TEST_RNM[0]), \ .RNM (ic_tag_ext_in_pkt_RNM[0]), \
.BC1 (BC1[0]), \ .BC1 (ic_tag_ext_in_pkt_BC1[0]), \
.BC2 (BC2[0]) \ .BC2 (ic_tag_ext_in_pkt_BC2[0]) \
\ \
); \ ); \
\ \
@ -1309,74 +1337,74 @@ end // block: OTHERS
end end
if (ICACHE_TAG_DEPTH == 32) begin : size_32 if (ICACHE_TAG_DEPTH == 32) begin : size_32
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(32,104) `IC_TAG_PACKED_SRAM(32,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(32,52) `IC_TAG_PACKED_SRAM(32,52)
end // block: WAYS end // block: WAYS
end // if (ICACHE_TAG_DEPTH == 32 end // if (ICACHE_TAG_DEPTH == 32
if (ICACHE_TAG_DEPTH == 64) begin : size_64 if (ICACHE_TAG_DEPTH == 64) begin : size_64
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(64,104) `IC_TAG_PACKED_SRAM(64,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(64,52) `IC_TAG_PACKED_SRAM(64,52)
end // block: WAYS end // block: WAYS
end // block: size_64 end // block: size_64
if (ICACHE_TAG_DEPTH == 128) begin : size_128 if (ICACHE_TAG_DEPTH == 128) begin : size_128
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(128,104) `IC_TAG_PACKED_SRAM(128,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(128,52) `IC_TAG_PACKED_SRAM(128,52)
end // block: WAYS end // block: WAYS
end // block: size_128 end // block: size_128
if (ICACHE_TAG_DEPTH == 256) begin : size_256 if (ICACHE_TAG_DEPTH == 256) begin : size_256
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(256,104) `IC_TAG_PACKED_SRAM(256,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(256,52) `IC_TAG_PACKED_SRAM(256,52)
end // block: WAYS end // block: WAYS
end // block: size_256 end // block: size_256
if (ICACHE_TAG_DEPTH == 512) begin : size_512 if (ICACHE_TAG_DEPTH == 512) begin : size_512
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(512,104) `IC_TAG_PACKED_SRAM(512,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(512,52) `IC_TAG_PACKED_SRAM(512,52)
end // block: WAYS end // block: WAYS
end // block: size_512 end // block: size_512
if (ICACHE_TAG_DEPTH == 1024) begin : size_1024 if (ICACHE_TAG_DEPTH == 1024) begin : size_1024
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(1024,104) `IC_TAG_PACKED_SRAM(1024,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(1024,52) `IC_TAG_PACKED_SRAM(1024,52)
end // block: WAYS end // block: WAYS
end // block: size_1024 end // block: size_1024
if (ICACHE_TAG_DEPTH == 2048) begin : size_2048 if (ICACHE_TAG_DEPTH == 2048) begin : size_2048
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(2048,104) `IC_TAG_PACKED_SRAM(2048,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(2048,52) `IC_TAG_PACKED_SRAM(2048,52)
end // block: WAYS end // block: WAYS
end // block: size_2048 end // block: size_2048
if (ICACHE_TAG_DEPTH == 4096) begin : size_4096 if (ICACHE_TAG_DEPTH == 4096) begin : size_4096
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(4096,104) `IC_TAG_PACKED_SRAM(4096,104)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(4096,52) `IC_TAG_PACKED_SRAM(4096,52)
end // block: WAYS end // block: WAYS
end // block: size_4096 end // block: size_4096
@ -1408,74 +1436,74 @@ end // block: OTHERS
end end
if (ICACHE_TAG_DEPTH == 32) begin : size_32 if (ICACHE_TAG_DEPTH == 32) begin : size_32
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(32,88) `IC_TAG_PACKED_SRAM(32,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(32,44) `IC_TAG_PACKED_SRAM(32,44)
end // block: WAYS end // block: WAYS
end // if (ICACHE_TAG_DEPTH == 32 end // if (ICACHE_TAG_DEPTH == 32
if (ICACHE_TAG_DEPTH == 64) begin : size_64 if (ICACHE_TAG_DEPTH == 64) begin : size_64
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(64,88) `IC_TAG_PACKED_SRAM(64,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(64,44) `IC_TAG_PACKED_SRAM(64,44)
end // block: WAYS end // block: WAYS
end // block: size_64 end // block: size_64
if (ICACHE_TAG_DEPTH == 128) begin : size_128 if (ICACHE_TAG_DEPTH == 128) begin : size_128
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(128,88) `IC_TAG_PACKED_SRAM(128,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(128,44) `IC_TAG_PACKED_SRAM(128,44)
end // block: WAYS end // block: WAYS
end // block: size_128 end // block: size_128
if (ICACHE_TAG_DEPTH == 256) begin : size_256 if (ICACHE_TAG_DEPTH == 256) begin : size_256
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(256,88) `IC_TAG_PACKED_SRAM(256,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(256,44) `IC_TAG_PACKED_SRAM(256,44)
end // block: WAYS end // block: WAYS
end // block: size_256 end // block: size_256
if (ICACHE_TAG_DEPTH == 512) begin : size_512 if (ICACHE_TAG_DEPTH == 512) begin : size_512
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(512,88) `IC_TAG_PACKED_SRAM(512,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(512,44) `IC_TAG_PACKED_SRAM(512,44)
end // block: WAYS end // block: WAYS
end // block: size_512 end // block: size_512
if (ICACHE_TAG_DEPTH == 1024) begin : size_1024 if (ICACHE_TAG_DEPTH == 1024) begin : size_1024
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(1024,88) `IC_TAG_PACKED_SRAM(1024,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(1024,44) `IC_TAG_PACKED_SRAM(1024,44)
end // block: WAYS end // block: WAYS
end // block: size_1024 end // block: size_1024
if (ICACHE_TAG_DEPTH == 2048) begin : size_2048 if (ICACHE_TAG_DEPTH == 2048) begin : size_2048
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(2048,88) `IC_TAG_PACKED_SRAM(2048,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(2048,44) `IC_TAG_PACKED_SRAM(2048,44)
end // block: WAYS end // block: WAYS
end // block: size_2048 end // block: size_2048
if (ICACHE_TAG_DEPTH == 4096) begin : size_4096 if (ICACHE_TAG_DEPTH == 4096) begin : size_4096
if (ICACHE_NUM_WAYS == 4) begin : WAYS if (ICACHE_NUM_WAYS == 4) begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(4096,88) `IC_TAG_PACKED_SRAM(4096,88)
end // block: WAYS end // block: WAYS
else begin : WAYS else begin : WAYS
`EL2_IC_TAG_PACKED_SRAM(4096,44) `IC_TAG_PACKED_SRAM(4096,44)
end // block: WAYS end // block: WAYS
end // block: size_4096 end // block: size_4096
@ -1497,9 +1525,9 @@ end // block: OTHERS
always_comb begin : tag_rd_out always_comb begin : tag_rd_out
ictag_debug_rd_data[25:0] = '0; ic_tag_debug_rd_data[25:0] = '0;
for ( int j=0; j<ICACHE_NUM_WAYS; j++) begin: debug_rd_out for ( int j=0; j<ICACHE_NUM_WAYS; j++) begin: debug_rd_out
ictag_debug_rd_data[25:0] |= ICACHE_ECC ? ({26{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j] ) : {4'b0, ({22{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j][21:0])}; ic_tag_debug_rd_data[25:0] |= ICACHE_ECC ? ({26{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j] ) : {4'b0, ({22{ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j][21:0])};
end end
end end
@ -1509,5 +1537,4 @@ end // block: OTHERS
end end
assign ic_tag_perr = | (ic_tag_way_perr[ICACHE_NUM_WAYS-1:0] & ic_tag_valid[ICACHE_NUM_WAYS-1:0] ) ; assign ic_tag_perr = | (ic_tag_way_perr[ICACHE_NUM_WAYS-1:0] & ic_tag_valid[ICACHE_NUM_WAYS-1:0] ) ;
endmodule // EL2_IC_TAG endmodule // IC_TAG

272
target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv
View File

@ -19,15 +19,10 @@
// Icache closely coupled memory --- ICCM // Icache closely coupled memory --- ICCM
//******************************************************************************** //********************************************************************************
module el2_ifu_iccm_mem module ifu_iccm_mem
#( `include "parameter.sv"
parameter ICCM_BITS,
parameter ICCM_BANK_INDEX_LO, (
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICCM_NUM_BANKS,
parameter ICCM_BANK_BITS
)(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low input logic rst_l, // reset, active low
@ -41,15 +36,20 @@ module el2_ifu_iccm_mem
input logic [2:0] iccm_wr_size, // ICCM write size input logic [2:0] iccm_wr_size, // ICCM write size
input logic [77:0] iccm_wr_data, // ICCM write data input logic [77:0] iccm_wr_data, // ICCM write data
//input el2_ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, // External packet //input ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, // External packet
input [ICCM_NUM_BANKS-1:0] TEST1, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_TEST1,
input [ICCM_NUM_BANKS-1:0] RME, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RME,
input [ICCM_NUM_BANKS-1:0][3:0] RM, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_0,
input [ICCM_NUM_BANKS-1:0] LS, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_1,
input [ICCM_NUM_BANKS-1:0] DS, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_2,
input [ICCM_NUM_BANKS-1:0] TEST-RNM, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_3,
input [ICCM_NUM_BANKS-1:0] BC1, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_LS,
input [ICCM_NUM_BANKS-1:0] BC2, input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_DS,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_SD,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RNM,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_BC1,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_BC2,
output logic [63:0] iccm_rd_data, // ICCM read data output logic [63:0] iccm_rd_data, // ICCM read data
output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc
input logic scan_mode // Scan mode control input logic scan_mode // Scan mode control
@ -121,7 +121,7 @@ module el2_ifu_iccm_mem
iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO]); iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO]);
`ifdef VERILATOR `ifdef VERILATOR
el2_ram #(.depth(1<<ICCM_INDEX_BITS), .width(39)) iccm_bank ( ram #(.depth(1<<ICCM_INDEX_BITS), .width(39)) iccm_bank (
// Primary ports // Primary ports
.ME(iccm_clken[i]), .ME(iccm_clken[i]),
.CLK(clk), .CLK(clk),
@ -131,15 +131,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
`else `else
@ -155,15 +158,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -179,15 +185,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -203,15 +212,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -226,15 +238,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -249,15 +264,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -272,15 +290,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -295,15 +316,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -318,15 +342,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -341,15 +368,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -364,15 +394,18 @@ module el2_ifu_iccm_mem
.Q(iccm_bank_dout[i][38:0]), .Q(iccm_bank_dout[i][38:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
.TEST1(TEST1[i]), .TEST1(iccm_ext_in_pkt_TEST1[i]),
.RME(RME[i]), .RME(iccm_ext_in_pkt_RME[i]),
.RM(RM[i][3:0]), .RM_0(iccm_ext_in_pkt_RM_0[i]),
.LS(LS[i]), .RM_1(iccm_ext_in_pkt_RM_1[i]),
.DS(DS[i]), .RM_2(iccm_ext_in_pkt_RM_2[i]),
.SD(SD[i]) , .RM_3(iccm_ext_in_pkt_RM_3[i]),
.TEST_RNM(TEST_RNM[i]), .LS(iccm_ext_in_pkt_LS[i]),
.BC1(BC1[i]), .DS(iccm_ext_in_pkt_DS[i]),
.BC2(BC2[i]) .SD(iccm_ext_in_pkt_SD[i]) ,
.RNM(iccm_ext_in_pkt_RNM[i]),
.BC1(iccm_ext_in_pkt_BC1[i]),
.BC2(iccm_ext_in_pkt_BC2[i])
); );
end // block: iccm end // block: iccm
@ -477,5 +510,4 @@ module el2_ifu_iccm_mem
assign iccm_rd_data[63:0] = {iccm_data[63:0]}; assign iccm_rd_data[63:0] = {iccm_data[63:0]};
assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][38:0]}; assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][38:0]};
endmodule // el2_ifu_iccm_mem endmodule // ifu_iccm_mem

127
target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv
View File

@ -27,28 +27,25 @@
// //******************************************************************************** // //********************************************************************************
`define EL2_LOCAL_DCCM_RAM_TEST_PORTS .TEST1(TEST1[i]), \
.RME(RME[i]), \ `define LOCAL_DCCM_RAM_TEST_PORTS .TEST1(dccm_ext_in_pkt_TEST1[i]), \
.RM(RM[i][3:0]), \ .RME(dccm_ext_in_pkt_RME[i]), \
.LS(LS[i]), \ .RM_0(dccm_ext_in_pkt_RM_0[i]), \
.DS(DS[i]), \ .RM_1(dccm_ext_in_pkt_RM_1[i]), \
.SD(SD[i]), \ .RM_2(dccm_ext_in_pkt_RM_2[i]), \
.TEST_RNM(TEST_RNM[i]), \ .RM_3(dccm_ext_in_pkt_RM_3[i]), \
.BC1(BC1[i]), \ .LS(dccm_ext_in_pkt_LS[i]), \
.BC2(BC2[i]), \ .DS(dccm_ext_in_pkt_DS[i]), \
.SD(dccm_ext_in_pkt_SD[i]), \
.RNM(dccm_ext_in_pkt_RNM[i]), \
.BC1(dccm_ext_in_pkt_BC1[i]), \
.BC2(dccm_ext_in_pkt_BC2[i]), \
module el2_lsu_dccm_mem module lsu_dccm_mem
#( `include "parameter.sv"
parameter DCCM_BYTE_WIDTH, (
parameter DCCM_BITS,
parameter DCCM_NUM_BANKS,
parameter DCCM_BANK_BITS,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter DCCM_WIDTH_BITS
)(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low input logic rst_l, // reset, active low
@ -62,16 +59,20 @@ module el2_lsu_dccm_mem
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data
//input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, // the dccm packet from the soc
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_TEST1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RME,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_0,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_2,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_3,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_LS,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_DS,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_SD,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RNM,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC2,
//input el2_dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, // the dccm packet from the soc
input [ICCM_NUM_BANKS-1:0] dccm_TEST1,
input [ICCM_NUM_BANKS-1:0] RME,
input [ICCM_NUM_BANKS-1:0][3:0] RM,
input [ICCM_NUM_BANKS-1:0] LS,
input [ICCM_NUM_BANKS-1:0] DS,
input [ICCM_NUM_BANKS-1:0] TEST-RNM,
input [ICCM_NUM_BANKS-1:0] BC1,
input [ICCM_NUM_BANKS-1:0] BC2,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank
@ -79,43 +80,43 @@ module el2_lsu_dccm_mem
); );
localparam DCCM_WIDTH_BITS_INT = $clog2(DCCM_BYTE_WIDTH); //localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH);
localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS); localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS);
localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank
logic [DCCM_NUM_BANKS-1:0] wren_bank; logic [DCCM_NUM_BANKS-1:0] wren_bank;
logic [DCCM_NUM_BANKS-1:0] rden_bank; logic [DCCM_NUM_BANKS-1:0] rden_bank;
logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank; logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank;
logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)] rd_addr_even, rd_addr_odd; logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd;
logic rd_unaligned, wr_unaligned; logic rd_unaligned, wr_unaligned;
logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout; logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout;
logic [DCCM_FDATA_WIDTH-1:0] wrdata; logic [DCCM_FDATA_WIDTH-1:0] wrdata;
logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank; logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank;
logic [(DCCM_WIDTH_BITS_INT+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS_INT] dccm_rd_addr_lo_q; logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_lo_q;
logic [(DCCM_WIDTH_BITS_INT+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS_INT] dccm_rd_addr_hi_q; logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_hi_q;
logic [DCCM_NUM_BANKS-1:0] dccm_clken; logic [DCCM_NUM_BANKS-1:0] dccm_clken;
assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]); assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]); assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
// Align the read data // Align the read data
assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0]; assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0]; assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
// 8 Banks, 16KB each (2048 x 72) // 8 Banks, 16KB each (2048 x 72)
for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank
assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_wr_addr_lo[2+:DCCM_BANK_BITS] == i)); assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_wr_addr_lo[2+:DCCM_BANK_BITS] == i));
assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_rd_addr_lo[2+:DCCM_BANK_BITS] == i)); assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_rd_addr_lo[2+:DCCM_BANK_BITS] == i));
assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ?
dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS] : dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS]) : dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]) :
(((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) & rd_unaligned) ? (((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) & rd_unaligned) ?
dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS] : dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS_INT)+:DCCM_INDEX_BITS]); dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]);
assign wr_data_bank[i] = ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? dccm_wr_data_hi[DCCM_FDATA_WIDTH-1:0] : dccm_wr_data_lo[DCCM_FDATA_WIDTH-1:0]; assign wr_data_bank[i] = ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? dccm_wr_data_hi[DCCM_FDATA_WIDTH-1:0] : dccm_wr_data_lo[DCCM_FDATA_WIDTH-1:0];
@ -125,7 +126,7 @@ module el2_lsu_dccm_mem
`ifdef VERILATOR `ifdef VERILATOR
el2_ram #(DCCM_INDEX_DEPTH,39) ram ( ram #(DCCM_INDEX_DEPTH,39) ram (
// Primary ports // Primary ports
.ME(dccm_clken[i]), .ME(dccm_clken[i]),
.CLK(clk), .CLK(clk),
@ -135,7 +136,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
`else `else
@ -151,7 +152,20 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
// .TEST1(dccm_ext_in_pkt_TEST1[i]),
// .RME(dccm_ext_in_pkt_RME[i]),
// .RM_0(dccm_ext_in_pkt_RM_0[i]),
// .RM_1(dccm_ext_in_pkt_RM_1[i]),
// .RM_2(dccm_ext_in_pkt_RM_2[i]),
// .RM_3(dccm_ext_in_pkt_RM_3[i]),
// .LS(dccm_ext_in_pkt_LS[i]),
// .DS(dccm_ext_in_pkt_DS[i]),
// .SD(dccm_ext_in_pkt_SD[i]),
// .RNM(dccm_ext_in_pkt_RNM[i]),
// .BC1(dccm_ext_in_pkt_BC1[i]),
// .BC2(dccm_ext_in_pkt_BC2[i]),
.* .*
); );
end end
@ -166,7 +180,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -181,7 +195,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -196,7 +210,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -211,7 +225,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -226,7 +240,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -241,7 +255,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -256,7 +270,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -271,7 +285,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -286,7 +300,7 @@ module el2_lsu_dccm_mem
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]), .Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ), .ROP ( ),
// These are used by SoC // These are used by SoC
`EL2_LOCAL_DCCM_RAM_TEST_PORTS `LOCAL_DCCM_RAM_TEST_PORTS
.* .*
); );
end end
@ -295,12 +309,11 @@ module el2_lsu_dccm_mem
end : mem_bank end : mem_bank
// Flops // Flops
rvdff #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .clk(active_clk)); rvdff #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .clk(active_clk));
rvdff #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS_INT+:DCCM_BANK_BITS]), .clk(active_clk)); rvdff #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .clk(active_clk));
`undef EL2_LOCAL_DCCM_RAM_TEST_PORTS `undef LOCAL_DCCM_RAM_TEST_PORTS
endmodule // el2_lsu_dccm_mem
endmodule // lsu_dccm_mem

127
target/scala-2.12/classes/vsrc/mem.sv
View File

@ -15,7 +15,11 @@
// limitations under the License. // limitations under the License.
//******************************************************************************** //********************************************************************************
`include "lsu_dccm_mem.sv"
`include "ifu_ic_mem.sv"
`include "ifu_iccm_mem.sv"
module mem module mem
`include "parameter.sv"
( (
input logic clk, input logic clk,
input logic rst_l, input logic rst_l,
@ -38,12 +42,36 @@ module mem
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE //`ifdef DCCM_ENABLE
input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, //input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_TEST1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RME,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_0,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_2,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_3,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_LS,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_DS,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_SD,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RNM,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC1,
input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC2,
//`endif //`endif
//ICCM ports //ICCM ports
input ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, //input ccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_TEST1,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RME,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_0,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_1,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_2,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RM_3,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_LS,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_DS,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_SD,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_RNM,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_BC1,
input [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt_BC2,
input logic [ICCM_BITS-1:1] iccm_rw_addr, input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
@ -64,10 +92,49 @@ module mem
input logic ic_rd_en, input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel input logic ic_sel_premux_data, // Premux data sel
input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_TEST1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RME,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_0,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_2,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RM_3,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_LS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_DS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_SD,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_RNM,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_BC1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_0_BC2,
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_TEST1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RME,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_0,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_2,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RM_3,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_LS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_DS,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_SD,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_RNM,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC1,
input [ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_1_BC2,
//input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_TEST1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RME,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_0,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_2,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RM_3,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_LS,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_DS,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_SD,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_RNM,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC1,
input [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt_BC2,
// input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache. input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
@ -77,7 +144,7 @@ module mem
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ictag_debug_rd_data,// Debug icache tag. output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
@ -90,19 +157,58 @@ module mem
); );
logic active_clk; logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_TEST1;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RME;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_0;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_1;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_2;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RM_3;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_LS;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_DS;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_SD;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_RNM;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC1;
logic [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt_BC2;
logic active_clk;
assign ic_data_ext_in_pkt_TEST1[0] = ic_data_ext_in_pkt_0_TEST1 ;
assign ic_data_ext_in_pkt_RME[0] = ic_data_ext_in_pkt_0_RME;
assign ic_data_ext_in_pkt_RM_0[0] = ic_data_ext_in_pkt_0_RM_0;
assign ic_data_ext_in_pkt_RM_1[0] = ic_data_ext_in_pkt_0_RM_1;
assign ic_data_ext_in_pkt_RM_2[0] = ic_data_ext_in_pkt_0_RM_2;
assign ic_data_ext_in_pkt_RM_3[0] = ic_data_ext_in_pkt_0_RM_3;
assign ic_data_ext_in_pkt_LS[0] = ic_data_ext_in_pkt_0_LS;
assign ic_data_ext_in_pkt_DS[0] = ic_data_ext_in_pkt_0_DS;
assign ic_data_ext_in_pkt_SD[0] = ic_data_ext_in_pkt_0_SD;
assign ic_data_ext_in_pkt_RNM[0] = ic_data_ext_in_pkt_0_RNM;
assign ic_data_ext_in_pkt_BC1[0] = ic_data_ext_in_pkt_0_BC1;
assign ic_data_ext_in_pkt_BC2[0] = ic_data_ext_in_pkt_0_BC2;
assign ic_data_ext_in_pkt_TEST1[1] = ic_data_ext_in_pkt_1_TEST1 ;
assign ic_data_ext_in_pkt_RME[1] = ic_data_ext_in_pkt_1_RME;
assign ic_data_ext_in_pkt_RM_0[1] = ic_data_ext_in_pkt_1_RM_0;
assign ic_data_ext_in_pkt_RM_1[1] = ic_data_ext_in_pkt_1_RM_1;
assign ic_data_ext_in_pkt_RM_2[1] = ic_data_ext_in_pkt_1_RM_2;
assign ic_data_ext_in_pkt_RM_3[1] = ic_data_ext_in_pkt_1_RM_3;
assign ic_data_ext_in_pkt_LS[1] = ic_data_ext_in_pkt_1_LS;
assign ic_data_ext_in_pkt_DS[1] = ic_data_ext_in_pkt_1_DS;
assign ic_data_ext_in_pkt_SD[1] = ic_data_ext_in_pkt_1_SD;
assign ic_data_ext_in_pkt_RNM[1] = ic_data_ext_in_pkt_1_RNM;
assign ic_data_ext_in_pkt_BC1[1] = ic_data_ext_in_pkt_1_BC1;
assign ic_data_ext_in_pkt_BC2[1] = ic_data_ext_in_pkt_1_BC2;
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* ); rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
// DCCM Instantiation // DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem dccm #( lsu_dccm_mem #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH), .DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS), .DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS), .DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS), .DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE), .DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH), .DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH),
.DCCM_WIDTH_BITS(DCCM_WIDTH_BITS))( .DCCM_WIDTH_BITS(DCCM_WIDTH_BITS)) dccm (
.clk_override(dccm_clk_override), .clk_override(dccm_clk_override),
.* .*
); );
@ -142,7 +248,7 @@ else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0; assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ; assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ; assign ic_rd_data = '0 ;
assign ictag_debug_rd_data = '0 ; assign ic_tag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE ) end // else: !if( ICACHE_ENABLE )
@ -167,4 +273,3 @@ end
endmodule endmodule