From 11c09dc85b58bacca7a84da502d6a68eb2c818a6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Thu, 4 Feb 2021 18:00:41 +0500 Subject: [PATCH] Debug rvoclk corrected --- quasar.fir | 1320 +++++++++++------------ quasar.v | 167 +-- src/main/scala/dbg/dbg.scala | 4 +- target/scala-2.12/classes/dbg/dbg.class | Bin 307393 -> 307393 bytes 4 files changed, 688 insertions(+), 803 deletions(-) diff --git a/quasar.fir b/quasar.fir index 081fa19a..22ff9506 100644 --- a/quasar.fir +++ b/quasar.fir @@ -88017,54 +88017,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_715 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_715 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_715 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_716 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_716 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_716 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - module dbg : input clock : Clock input reset : AsyncReset @@ -88184,18 +88136,6 @@ circuit quasar : node _T_10 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 116:83] node _T_11 = or(_T_9, _T_10) @[dbg.scala 116:71] node sb_free_clken = or(_T_11, io.clk_override) @[dbg.scala 116:106] - inst rvclkhdr of rvclkhdr_707 @[lib.scala 343:22] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[lib.scala 344:17] - rvclkhdr.io.en <= dbg_free_clken @[lib.scala 345:16] - rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23] - inst rvclkhdr_1 of rvclkhdr_708 @[lib.scala 343:22] - rvclkhdr_1.clock <= clock - rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_1.io.en <= sb_free_clken @[lib.scala 345:16] - rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23] node _T_12 = asUInt(io.dbg_rst_l) @[dbg.scala 121:51] node _T_13 = bits(dmcontrol_reg, 0, 0) @[dbg.scala 121:70] node _T_14 = or(_T_13, io.scan_mode) @[dbg.scala 121:74] @@ -88226,16 +88166,16 @@ circuit quasar : node _T_35 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 128:62] node _T_36 = and(sbcs_wren, _T_35) @[dbg.scala 128:44] node sbcs_sbbusyerror_din = not(_T_36) @[dbg.scala 128:32] - reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg temp_sbcs_22 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_sbbusyerror_wren : @[Reg.scala 28:19] temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg temp_sbcs_21 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_sbbusy_wren : @[Reg.scala 28:19] temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_37 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 134:31] - reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg temp_sbcs_20 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_wren : @[Reg.scala 28:19] temp_sbcs_20 <= _T_37 @[Reg.scala 28:23] skip @[Reg.scala 28:19] @@ -88245,12 +88185,12 @@ circuit quasar : node _T_41 = bits(io.dmi_reg_wdata, 17, 15) @[dbg.scala 136:80] node _T_42 = cat(_T_38, _T_40) @[Cat.scala 29:58] node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58] - reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg temp_sbcs_19_15 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_wren : @[Reg.scala 28:19] temp_sbcs_19_15 <= _T_43 @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_44 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 138:31] - reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg temp_sbcs_14_12 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbcs_sberror_wren : @[Reg.scala 28:19] temp_sbcs_14_12 <= _T_44 @[Reg.scala 28:23] skip @[Reg.scala 28:19] @@ -88341,22 +88281,22 @@ circuit quasar : node _T_118 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 158:118] node _T_119 = and(_T_117, _T_118) @[dbg.scala 158:104] node sbdata1_din = or(_T_115, _T_119) @[dbg.scala 158:74] - inst rvclkhdr_2 of rvclkhdr_709 @[lib.scala 409:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= dbg_dm_rst_l - rvclkhdr_2.io.clk <= clock @[lib.scala 411:18] - rvclkhdr_2.io.en <= sbdata0_reg_wren @[lib.scala 412:17] - rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] + inst rvclkhdr of rvclkhdr_707 @[lib.scala 409:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= dbg_dm_rst_l + rvclkhdr.io.clk <= clock @[lib.scala 411:18] + rvclkhdr.io.en <= sbdata0_reg_wren @[lib.scala 412:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] reg sbdata0_reg : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbdata0_reg_wren : @[Reg.scala 28:19] sbdata0_reg <= sbdata0_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - inst rvclkhdr_3 of rvclkhdr_710 @[lib.scala 409:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= dbg_dm_rst_l - rvclkhdr_3.io.clk <= clock @[lib.scala 411:18] - rvclkhdr_3.io.en <= sbdata1_reg_wren @[lib.scala 412:17] - rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] + inst rvclkhdr_1 of rvclkhdr_708 @[lib.scala 409:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= dbg_dm_rst_l + rvclkhdr_1.io.clk <= clock @[lib.scala 411:18] + rvclkhdr_1.io.en <= sbdata1_reg_wren @[lib.scala 412:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] reg sbdata1_reg : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbdata1_reg_wren : @[Reg.scala 28:19] sbdata1_reg <= sbdata1_din @[Reg.scala 28:23] @@ -88375,12 +88315,12 @@ circuit quasar : node _T_129 = tail(_T_128, 1) @[dbg.scala 166:54] node _T_130 = and(_T_126, _T_129) @[dbg.scala 166:36] node sbaddress0_reg_din = or(_T_124, _T_130) @[dbg.scala 165:81] - inst rvclkhdr_4 of rvclkhdr_711 @[lib.scala 409:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= dbg_dm_rst_l - rvclkhdr_4.io.clk <= clock @[lib.scala 411:18] - rvclkhdr_4.io.en <= sbaddress0_reg_wren @[lib.scala 412:17] - rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] + inst rvclkhdr_2 of rvclkhdr_709 @[lib.scala 409:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= dbg_dm_rst_l + rvclkhdr_2.io.clk <= clock @[lib.scala 411:18] + rvclkhdr_2.io.en <= sbaddress0_reg_wren @[lib.scala 412:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] reg _T_131 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sbaddress0_reg_wren : @[Reg.scala 28:19] _T_131 <= sbaddress0_reg_din @[Reg.scala 28:23] @@ -88414,12 +88354,12 @@ circuit quasar : node _T_152 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 177:83] node _T_153 = cat(_T_150, _T_151) @[Cat.scala 29:58] node _T_154 = cat(_T_153, _T_152) @[Cat.scala 29:58] - reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg dm_temp : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when dmcontrol_wren : @[Reg.scala 28:19] dm_temp <= _T_154 @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_155 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 179:31] - reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (io.dbg_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg dm_temp_0 : UInt, clock with : (reset => (io.dbg_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when dmcontrol_wren : @[Reg.scala 28:19] dm_temp_0 <= _T_155 @[Reg.scala 28:23] skip @[Reg.scala 28:19] @@ -88432,7 +88372,7 @@ circuit quasar : node _T_162 = cat(_T_161, _T_157) @[Cat.scala 29:58] node temp = cat(_T_162, _T_160) @[Cat.scala 29:58] dmcontrol_reg <= temp @[dbg.scala 181:18] - reg _T_163 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 184:12] + reg _T_163 : UInt<1>, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 184:12] _T_163 <= dmcontrol_wren @[dbg.scala 184:12] dmcontrol_wren_Q <= _T_163 @[dbg.scala 183:21] node _T_164 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15] @@ -88481,17 +88421,17 @@ circuit quasar : node _T_200 = not(_T_199) @[dbg.scala 196:23] dmstatus_running <= _T_200 @[dbg.scala 196:20] node _T_201 = bits(dmstatus_resumeack_wren, 0, 0) @[dbg.scala 199:74] - reg _T_202 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_202 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_201 : @[Reg.scala 28:19] _T_202 <= dmstatus_resumeack_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] dmstatus_resumeack <= _T_202 @[dbg.scala 198:22] node _T_203 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 201:37] node _T_204 = and(io.dec_tlu_dbg_halted, _T_203) @[dbg.scala 201:35] - reg _T_205 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 201:12] + reg _T_205 : UInt<1>, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 201:12] _T_205 <= _T_204 @[dbg.scala 201:12] dmstatus_halted <= _T_205 @[dbg.scala 200:22] - reg _T_206 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_206 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when dmstatus_haveresetn_wren : @[Reg.scala 28:19] _T_206 <= UInt<1>("h01") @[Reg.scala 28:23] skip @[Reg.scala 28:19] @@ -88609,11 +88549,11 @@ circuit quasar : node _T_309 = mux(abstractcs_error_sel1, UInt<3>("h02"), _T_308) @[Mux.scala 98:16] node _T_310 = mux(abstractcs_error_sel0, UInt<3>("h01"), _T_309) @[Mux.scala 98:16] abstractcs_error_din <= _T_310 @[dbg.scala 224:25] - reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg abs_temp_12 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when abstractcs_busy_wren : @[Reg.scala 28:19] abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] - reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 236:12] + reg abs_temp_10_8 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 236:12] abs_temp_10_8 <= abstractcs_error_din @[dbg.scala 236:12] node _T_311 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58] node _T_312 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58] @@ -88627,7 +88567,7 @@ circuit quasar : node _T_319 = eq(_T_318, UInt<1>("h00")) @[dbg.scala 240:103] node abstractauto_reg_wren = and(_T_317, _T_319) @[dbg.scala 240:101] node _T_320 = bits(io.dmi_reg_wdata, 1, 0) @[dbg.scala 242:31] - reg abstractauto_reg : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg abstractauto_reg : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when abstractauto_reg_wren : @[Reg.scala 28:19] abstractauto_reg <= _T_320 @[Reg.scala 28:23] skip @[Reg.scala 28:19] @@ -88679,27 +88619,27 @@ circuit quasar : node temp_command_din_15_0 = mux(command_wren, _T_358, _T_359) @[dbg.scala 253:37] node _T_360 = cat(temp_command_din_31_16, temp_command_din_15_0) @[Cat.scala 29:58] command_din <= _T_360 @[dbg.scala 255:19] - reg _T_361 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 257:12] + reg _T_361 : UInt<1>, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 257:12] _T_361 <= execute_command_ns @[dbg.scala 257:12] execute_command <= _T_361 @[dbg.scala 256:19] node _T_362 = bits(command_din, 31, 16) @[dbg.scala 260:23] - inst rvclkhdr_5 of rvclkhdr_712 @[lib.scala 409:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= dbg_dm_rst_l - rvclkhdr_5.io.clk <= clock @[lib.scala 411:18] - rvclkhdr_5.io.en <= command_wren @[lib.scala 412:17] - rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] + inst rvclkhdr_3 of rvclkhdr_710 @[lib.scala 409:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= dbg_dm_rst_l + rvclkhdr_3.io.clk <= clock @[lib.scala 411:18] + rvclkhdr_3.io.en <= command_wren @[lib.scala 412:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] reg temp_command_reg_31_16 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when command_wren : @[Reg.scala 28:19] temp_command_reg_31_16 <= _T_362 @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_363 = bits(command_din, 15, 0) @[dbg.scala 262:23] - inst rvclkhdr_6 of rvclkhdr_713 @[lib.scala 409:23] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= dbg_dm_rst_l - rvclkhdr_6.io.clk <= clock @[lib.scala 411:18] - rvclkhdr_6.io.en <= command_regno_wren @[lib.scala 412:17] - rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] + inst rvclkhdr_4 of rvclkhdr_711 @[lib.scala 409:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= dbg_dm_rst_l + rvclkhdr_4.io.clk <= clock @[lib.scala 411:18] + rvclkhdr_4.io.en <= command_regno_wren @[lib.scala 412:17] + rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] reg temp_command_reg_15_0 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when command_regno_wren : @[Reg.scala 28:19] temp_command_reg_15_0 <= _T_363 @[Reg.scala 28:23] @@ -88733,12 +88673,12 @@ circuit quasar : node _T_386 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 272:45] node _T_387 = and(_T_385, _T_386) @[dbg.scala 272:31] node data0_din = or(_T_383, _T_387) @[dbg.scala 271:52] - inst rvclkhdr_7 of rvclkhdr_714 @[lib.scala 409:23] - rvclkhdr_7.clock <= clock - rvclkhdr_7.reset <= dbg_dm_rst_l - rvclkhdr_7.io.clk <= clock @[lib.scala 411:18] - rvclkhdr_7.io.en <= data0_reg_wren @[lib.scala 412:17] - rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] + inst rvclkhdr_5 of rvclkhdr_712 @[lib.scala 409:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= dbg_dm_rst_l + rvclkhdr_5.io.clk <= clock @[lib.scala 411:18] + rvclkhdr_5.io.en <= data0_reg_wren @[lib.scala 412:17] + rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] reg data0_reg : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when data0_reg_wren : @[Reg.scala 28:19] data0_reg <= data0_din @[Reg.scala 28:23] @@ -88770,22 +88710,22 @@ circuit quasar : node _T_409 = bits(dbg_cmd_next_addr, 31, 0) @[dbg.scala 281:111] node _T_410 = and(_T_408, _T_409) @[dbg.scala 281:92] node data1_din = or(_T_406, _T_410) @[dbg.scala 281:64] - inst rvclkhdr_8 of rvclkhdr_715 @[lib.scala 409:23] - rvclkhdr_8.clock <= clock - rvclkhdr_8.reset <= dbg_dm_rst_l - rvclkhdr_8.io.clk <= clock @[lib.scala 411:18] - rvclkhdr_8.io.en <= data1_reg_wren @[lib.scala 412:17] - rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] + inst rvclkhdr_6 of rvclkhdr_713 @[lib.scala 409:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= dbg_dm_rst_l + rvclkhdr_6.io.clk <= clock @[lib.scala 411:18] + rvclkhdr_6.io.en <= data1_reg_wren @[lib.scala 412:17] + rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] reg _T_411 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when data1_reg_wren : @[Reg.scala 28:19] _T_411 <= data1_din @[Reg.scala 28:23] skip @[Reg.scala 28:19] abmem_addr <= _T_411 @[dbg.scala 282:16] - reg sb_abmem_cmd_done : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg sb_abmem_cmd_done : UInt<1>, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sb_abmem_cmd_done_en : @[Reg.scala 28:19] sb_abmem_cmd_done <= sb_abmem_cmd_done_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - reg sb_abmem_data_done : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg sb_abmem_data_done : UInt<1>, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sb_abmem_data_done_en : @[Reg.scala 28:19] sb_abmem_data_done <= sb_abmem_data_done_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] @@ -89065,17 +89005,17 @@ circuit quasar : node _T_595 = asUInt(dbg_dm_rst_l) @[dbg.scala 385:68] node _T_596 = and(_T_595, temp_rst) @[dbg.scala 385:71] node _T_597 = asAsyncReset(_T_596) @[dbg.scala 385:95] - reg _T_598 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_597, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_598 : UInt, clock with : (reset => (_T_597, UInt<1>("h00"))) @[Reg.scala 27:20] when dbg_state_en : @[Reg.scala 28:19] _T_598 <= dbg_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] dbg_state <= _T_598 @[dbg.scala 385:13] - inst rvclkhdr_9 of rvclkhdr_716 @[lib.scala 409:23] - rvclkhdr_9.clock <= clock - rvclkhdr_9.reset <= dbg_dm_rst_l - rvclkhdr_9.io.clk <= clock @[lib.scala 411:18] - rvclkhdr_9.io.en <= io.dmi_reg_en @[lib.scala 412:17] - rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] + inst rvclkhdr_7 of rvclkhdr_714 @[lib.scala 409:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= dbg_dm_rst_l + rvclkhdr_7.io.clk <= clock @[lib.scala 411:18] + rvclkhdr_7.io.en <= io.dmi_reg_en @[lib.scala 412:17] + rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 413:24] reg _T_599 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when io.dmi_reg_en : @[Reg.scala 28:19] _T_599 <= dmi_reg_rdata_din @[Reg.scala 28:23] @@ -89304,7 +89244,7 @@ circuit quasar : node _T_733 = and(_T_730, _T_732) @[dbg.scala 480:44] sbaddress0_reg_wren1 <= _T_733 @[dbg.scala 480:28] skip @[Conditional.scala 39:67] - reg _T_734 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_734 : UInt, clock with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] when sb_state_en : @[Reg.scala 28:19] _T_734 <= sb_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] @@ -89505,6 +89445,54 @@ circuit quasar : node _T_878 = or(_T_872, _T_877) @[dbg.scala 558:123] sb_bus_rdata <= _T_878 @[dbg.scala 556:16] + extmodule gated_latch_715 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_715 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_715 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_716 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_716 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_716 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_717 : output Q : Clock input CK : Clock @@ -89673,54 +89661,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_724 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_724 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_724 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_725 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_725 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_725 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - module exu_alu_ctl : input clock : Clock input reset : AsyncReset @@ -89832,7 +89772,7 @@ circuit quasar : node _T_15 = and(io.enable, io.dec_alu.dec_i0_alu_decode_d) @[exu_alu_ctl.scala 135:43] node _T_16 = bits(_T_15, 0, 0) @[lib.scala 8:44] node _T_17 = bits(io.scan_mode, 0, 0) @[exu_alu_ctl.scala 135:95] - inst rvclkhdr of rvclkhdr_725 @[lib.scala 409:23] + inst rvclkhdr of rvclkhdr_723 @[lib.scala 409:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 411:18] @@ -91030,6 +90970,54 @@ circuit quasar : io.predict_p_out.bits.ataken <= actual_taken @[exu_alu_ctl.scala 360:35] io.predict_p_out.bits.hist <= newhist @[exu_alu_ctl.scala 361:35] + extmodule gated_latch_724 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_724 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_724 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_725 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_725 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_725 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_726 : output Q : Clock input CK : Clock @@ -91102,54 +91090,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_729 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_729 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_729 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_730 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_730 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_730 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - module exu_mul_ctl : input clock : Clock input reset : AsyncReset @@ -91226,7 +91166,7 @@ circuit quasar : node _T_7 = asSInt(_T_6) @[exu_mul_ctl.scala 124:71] rs2_ext_in <= _T_7 @[exu_mul_ctl.scala 124:14] node _T_8 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 126:52] - inst rvclkhdr of rvclkhdr_726 @[lib.scala 409:23] + inst rvclkhdr of rvclkhdr_724 @[lib.scala 409:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 411:18] @@ -91238,7 +91178,7 @@ circuit quasar : skip @[Reg.scala 28:19] low_x <= _T_9 @[exu_mul_ctl.scala 126:9] node _T_10 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 127:44] - inst rvclkhdr_1 of rvclkhdr_727 @[lib.scala 436:23] + inst rvclkhdr_1 of rvclkhdr_725 @[lib.scala 436:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 438:18] @@ -91250,7 +91190,7 @@ circuit quasar : skip @[Reg.scala 28:19] rs1_x <= _T_11 @[exu_mul_ctl.scala 127:9] node _T_12 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 128:45] - inst rvclkhdr_2 of rvclkhdr_728 @[lib.scala 436:23] + inst rvclkhdr_2 of rvclkhdr_726 @[lib.scala 436:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 438:18] @@ -131163,7 +131103,7 @@ circuit quasar : node _T_39756 = or(_T_39755, _T_39741) @[Mux.scala 27:72] wire bitmanip_d : UInt<32> @[Mux.scala 27:72] bitmanip_d <= _T_39756 @[Mux.scala 27:72] - inst rvclkhdr_3 of rvclkhdr_729 @[lib.scala 409:23] + inst rvclkhdr_3 of rvclkhdr_727 @[lib.scala 409:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 411:18] @@ -131173,7 +131113,7 @@ circuit quasar : when io.mul_p.valid : @[Reg.scala 28:19] bitmanip_sel_x <= bitmanip_sel_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] - inst rvclkhdr_4 of rvclkhdr_730 @[lib.scala 409:23] + inst rvclkhdr_4 of rvclkhdr_728 @[lib.scala 409:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[lib.scala 411:18] @@ -131942,6 +131882,54 @@ circuit quasar : node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 954:31] io.cls <= _T_347 @[exu_div_ctl.scala 954:25] + extmodule gated_latch_729 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_729 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_729 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_730 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_730 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_730 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_731 : output Q : Clock input CK : Clock @@ -132158,54 +132146,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_740 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_740 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_740 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_741 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_741 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_741 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - module exu_div_new_4bit_fullshortq : input clock : Clock input reset : AsyncReset @@ -133891,7 +133831,7 @@ circuit quasar : node _T_1517 = cat(_T_1516, _T_1511) @[Cat.scala 29:58] node _T_1518 = cat(_T_1517, _T_1515) @[Cat.scala 29:58] b_ff <= _T_1518 @[exu_div_ctl.scala 927:23] - inst rvclkhdr of rvclkhdr_731 @[lib.scala 409:23] + inst rvclkhdr of rvclkhdr_729 @[lib.scala 409:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 411:18] @@ -133902,7 +133842,7 @@ circuit quasar : _T_1519 <= valid_ff_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] valid_ff <= _T_1519 @[exu_div_ctl.scala 928:23] - inst rvclkhdr_1 of rvclkhdr_732 @[lib.scala 409:23] + inst rvclkhdr_1 of rvclkhdr_730 @[lib.scala 409:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 411:18] @@ -133913,7 +133853,7 @@ circuit quasar : _T_1520 <= control_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] control_ff <= _T_1520 @[exu_div_ctl.scala 929:23] - inst rvclkhdr_2 of rvclkhdr_733 @[lib.scala 409:23] + inst rvclkhdr_2 of rvclkhdr_731 @[lib.scala 409:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 411:18] @@ -133924,7 +133864,7 @@ circuit quasar : _T_1521 <= by_zero_case @[Reg.scala 28:23] skip @[Reg.scala 28:19] by_zero_case_ff <= _T_1521 @[exu_div_ctl.scala 930:23] - inst rvclkhdr_3 of rvclkhdr_734 @[lib.scala 409:23] + inst rvclkhdr_3 of rvclkhdr_732 @[lib.scala 409:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 411:18] @@ -133935,7 +133875,7 @@ circuit quasar : _T_1522 <= shortq_enable @[Reg.scala 28:23] skip @[Reg.scala 28:19] shortq_enable_ff <= _T_1522 @[exu_div_ctl.scala 931:23] - inst rvclkhdr_4 of rvclkhdr_735 @[lib.scala 409:23] + inst rvclkhdr_4 of rvclkhdr_733 @[lib.scala 409:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[lib.scala 411:18] @@ -133946,7 +133886,7 @@ circuit quasar : _T_1523 <= shortq_shift @[Reg.scala 28:23] skip @[Reg.scala 28:19] shortq_shift_ff <= _T_1523 @[exu_div_ctl.scala 932:23] - inst rvclkhdr_5 of rvclkhdr_736 @[lib.scala 409:23] + inst rvclkhdr_5 of rvclkhdr_734 @[lib.scala 409:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[lib.scala 411:18] @@ -133957,7 +133897,7 @@ circuit quasar : _T_1524 <= finish @[Reg.scala 28:23] skip @[Reg.scala 28:19] finish_ff <= _T_1524 @[exu_div_ctl.scala 933:23] - inst rvclkhdr_6 of rvclkhdr_737 @[lib.scala 409:23] + inst rvclkhdr_6 of rvclkhdr_735 @[lib.scala 409:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 411:18] @@ -133968,7 +133908,7 @@ circuit quasar : _T_1525 <= count_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] count_ff <= _T_1525 @[exu_div_ctl.scala 934:23] - inst rvclkhdr_7 of rvclkhdr_738 @[lib.scala 409:23] + inst rvclkhdr_7 of rvclkhdr_736 @[lib.scala 409:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 411:18] @@ -133980,7 +133920,7 @@ circuit quasar : skip @[Reg.scala 28:19] a_ff <= _T_1526 @[exu_div_ctl.scala 936:23] node _T_1527 = bits(b_in, 32, 0) @[exu_div_ctl.scala 937:37] - inst rvclkhdr_8 of rvclkhdr_739 @[lib.scala 409:23] + inst rvclkhdr_8 of rvclkhdr_737 @[lib.scala 409:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 411:18] @@ -133991,7 +133931,7 @@ circuit quasar : _T_1528 <= _T_1527 @[Reg.scala 28:23] skip @[Reg.scala 28:19] b_ff1 <= _T_1528 @[exu_div_ctl.scala 937:23] - inst rvclkhdr_9 of rvclkhdr_740 @[lib.scala 409:23] + inst rvclkhdr_9 of rvclkhdr_738 @[lib.scala 409:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 411:18] @@ -134002,7 +133942,7 @@ circuit quasar : _T_1529 <= r_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] r_ff <= _T_1529 @[exu_div_ctl.scala 938:23] - inst rvclkhdr_10 of rvclkhdr_741 @[lib.scala 409:23] + inst rvclkhdr_10 of rvclkhdr_739 @[lib.scala 409:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 411:18] @@ -134133,7 +134073,7 @@ circuit quasar : i0_predict_p_x.bits.misp <= _T_9.bits.misp @[exu.scala 65:55] i0_predict_p_x.valid <= _T_9.valid @[exu.scala 65:55] node _T_10 = bits(x_data_en_q2, 0, 0) @[exu.scala 66:79] - inst rvclkhdr of rvclkhdr_717 @[lib.scala 409:23] + inst rvclkhdr of rvclkhdr_715 @[lib.scala 409:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 411:18] @@ -134144,7 +134084,7 @@ circuit quasar : predpipe_x <= predpipe_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_11 = bits(r_data_en_q2, 0, 0) @[exu.scala 67:88] - inst rvclkhdr_1 of rvclkhdr_718 @[lib.scala 409:23] + inst rvclkhdr_1 of rvclkhdr_716 @[lib.scala 409:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 411:18] @@ -134155,7 +134095,7 @@ circuit quasar : predpipe_r <= predpipe_x @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 68:86] - inst rvclkhdr_2 of rvclkhdr_719 @[lib.scala 409:23] + inst rvclkhdr_2 of rvclkhdr_717 @[lib.scala 409:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 411:18] @@ -134166,7 +134106,7 @@ circuit quasar : ghr_x <= ghr_x_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 69:75] - inst rvclkhdr_3 of rvclkhdr_720 @[lib.scala 409:23] + inst rvclkhdr_3 of rvclkhdr_718 @[lib.scala 409:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 411:18] @@ -134177,7 +134117,7 @@ circuit quasar : i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_14 = bits(x_ctl_en, 0, 0) @[exu.scala 70:66] - inst rvclkhdr_4 of rvclkhdr_721 @[lib.scala 409:23] + inst rvclkhdr_4 of rvclkhdr_719 @[lib.scala 409:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[lib.scala 411:18] @@ -134188,7 +134128,7 @@ circuit quasar : i0_flush_upper_x <= i0_flush_upper_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_15 = bits(x_ctl_en, 0, 0) @[exu.scala 71:84] - inst rvclkhdr_5 of rvclkhdr_722 @[lib.scala 409:23] + inst rvclkhdr_5 of rvclkhdr_720 @[lib.scala 409:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[lib.scala 411:18] @@ -134199,7 +134139,7 @@ circuit quasar : i0_taken_x <= i0_taken_d @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_16 = bits(x_ctl_en, 0, 0) @[exu.scala 72:84] - inst rvclkhdr_6 of rvclkhdr_723 @[lib.scala 409:23] + inst rvclkhdr_6 of rvclkhdr_721 @[lib.scala 409:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 411:18] @@ -134390,7 +134330,7 @@ circuit quasar : wire i0_rs1_d : UInt<32> @[Mux.scala 27:72] i0_rs1_d <= _T_105 @[Mux.scala 27:72] node _T_106 = bits(x_data_en_q1, 0, 0) @[exu.scala 105:88] - inst rvclkhdr_7 of rvclkhdr_724 @[lib.scala 409:23] + inst rvclkhdr_7 of rvclkhdr_722 @[lib.scala 409:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 411:18] @@ -134986,6 +134926,54 @@ circuit quasar : _T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60] io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50] + extmodule gated_latch_740 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_740 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_740 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_741 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_741 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_741 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_742 : output Q : Clock input CK : Clock @@ -135034,54 +135022,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_744 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_744 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_744 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_745 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_745 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_745 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - module lsu_lsc_ctl : input clock : Clock input reset : AsyncReset @@ -135286,7 +135226,7 @@ circuit quasar : node _T_106 = or(_T_105, io.clk_override) @[lsu_lsc_ctl.scala 184:113] node _T_107 = bits(_T_106, 0, 0) @[lib.scala 8:44] node _T_108 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] - inst rvclkhdr of rvclkhdr_742 @[lib.scala 422:23] + inst rvclkhdr of rvclkhdr_740 @[lib.scala 422:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 424:18] @@ -135547,7 +135487,7 @@ circuit quasar : node _T_169 = or(_T_168, io.clk_override) @[lsu_lsc_ctl.scala 230:87] node _T_170 = bits(_T_169, 0, 0) @[lib.scala 8:44] node _T_171 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] - inst rvclkhdr_1 of rvclkhdr_743 @[lib.scala 409:23] + inst rvclkhdr_1 of rvclkhdr_741 @[lib.scala 409:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 411:18] @@ -135563,7 +135503,7 @@ circuit quasar : node _T_175 = or(_T_174, io.clk_override) @[lsu_lsc_ctl.scala 231:87] node _T_176 = bits(_T_175, 0, 0) @[lib.scala 8:44] node _T_177 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] - inst rvclkhdr_2 of rvclkhdr_744 @[lib.scala 409:23] + inst rvclkhdr_2 of rvclkhdr_742 @[lib.scala 409:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 411:18] @@ -135593,7 +135533,7 @@ circuit quasar : addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 237:66] node _T_184 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 238:77] node _T_185 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] - inst rvclkhdr_3 of rvclkhdr_745 @[lib.scala 409:23] + inst rvclkhdr_3 of rvclkhdr_743 @[lib.scala 409:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 411:18] @@ -135710,6 +135650,54 @@ circuit quasar : node _T_283 = or(_T_278, _T_282) @[lsu_lsc_ctl.scala 277:144] io.lsu_result_corr_r <= _T_283 @[lsu_lsc_ctl.scala 274:27] + extmodule gated_latch_744 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_744 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_744 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_745 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_745 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_745 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_746 : output Q : Clock input CK : Clock @@ -135758,54 +135746,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_748 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_748 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_748 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_749 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_749 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_749 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - module lsu_dccm_ctl : input clock : Clock input reset : AsyncReset @@ -136692,7 +136632,7 @@ circuit quasar : node _T_815 = or(_T_814, io.clk_override) @[lsu_dccm_ctl.scala 157:145] node _T_816 = bits(_T_815, 0, 0) @[lib.scala 8:44] node _T_817 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] - inst rvclkhdr of rvclkhdr_746 @[lib.scala 409:23] + inst rvclkhdr of rvclkhdr_744 @[lib.scala 409:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 411:18] @@ -137385,7 +137325,7 @@ circuit quasar : node _T_1433 = or(_T_1432, io.clk_override) @[lsu_dccm_ctl.scala 262:343] node _T_1434 = bits(_T_1433, 0, 0) @[lib.scala 8:44] node _T_1435 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44] - inst rvclkhdr_1 of rvclkhdr_747 @[lib.scala 409:23] + inst rvclkhdr_1 of rvclkhdr_745 @[lib.scala 409:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 411:18] @@ -137943,7 +137883,7 @@ circuit quasar : node _T_1945 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 285:90] node _T_1946 = bits(_T_1945, 0, 0) @[lib.scala 8:44] node _T_1947 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 285:128] - inst rvclkhdr_2 of rvclkhdr_748 @[lib.scala 409:23] + inst rvclkhdr_2 of rvclkhdr_746 @[lib.scala 409:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 411:18] @@ -137958,7 +137898,7 @@ circuit quasar : node _T_1950 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 286:90] node _T_1951 = bits(_T_1950, 0, 0) @[lib.scala 8:44] node _T_1952 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 286:128] - inst rvclkhdr_3 of rvclkhdr_749 @[lib.scala 409:23] + inst rvclkhdr_3 of rvclkhdr_747 @[lib.scala 409:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 411:18] @@ -137970,6 +137910,54 @@ circuit quasar : skip @[Reg.scala 28:19] ld_sec_addr_lo_r_ff <= _T_1953 @[lsu_dccm_ctl.scala 286:25] + extmodule gated_latch_748 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_748 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_748 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_749 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_749 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_749 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_750 : output Q : Clock input CK : Clock @@ -138114,54 +138102,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_756 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_756 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_756 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_757 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_757 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_757 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - module lsu_stbuf : input clock : Clock input reset : AsyncReset @@ -138989,7 +138929,7 @@ circuit quasar : stbuf_byteen[3] <= _T_661 @[lsu_stbuf.scala 165:18] node _T_662 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 169:59] node _T_663 = bits(_T_662, 0, 0) @[lsu_stbuf.scala 169:69] - inst rvclkhdr of rvclkhdr_750 @[lib.scala 409:23] + inst rvclkhdr of rvclkhdr_748 @[lib.scala 409:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 411:18] @@ -139002,7 +138942,7 @@ circuit quasar : stbuf_addr[0] <= _T_664 @[lsu_stbuf.scala 169:21] node _T_665 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 170:59] node _T_666 = bits(_T_665, 0, 0) @[lsu_stbuf.scala 170:69] - inst rvclkhdr_1 of rvclkhdr_751 @[lib.scala 409:23] + inst rvclkhdr_1 of rvclkhdr_749 @[lib.scala 409:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 411:18] @@ -139015,7 +138955,7 @@ circuit quasar : stbuf_data[0] <= _T_667 @[lsu_stbuf.scala 170:21] node _T_668 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 169:59] node _T_669 = bits(_T_668, 0, 0) @[lsu_stbuf.scala 169:69] - inst rvclkhdr_2 of rvclkhdr_752 @[lib.scala 409:23] + inst rvclkhdr_2 of rvclkhdr_750 @[lib.scala 409:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 411:18] @@ -139028,7 +138968,7 @@ circuit quasar : stbuf_addr[1] <= _T_670 @[lsu_stbuf.scala 169:21] node _T_671 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 170:59] node _T_672 = bits(_T_671, 0, 0) @[lsu_stbuf.scala 170:69] - inst rvclkhdr_3 of rvclkhdr_753 @[lib.scala 409:23] + inst rvclkhdr_3 of rvclkhdr_751 @[lib.scala 409:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 411:18] @@ -139041,7 +138981,7 @@ circuit quasar : stbuf_data[1] <= _T_673 @[lsu_stbuf.scala 170:21] node _T_674 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 169:59] node _T_675 = bits(_T_674, 0, 0) @[lsu_stbuf.scala 169:69] - inst rvclkhdr_4 of rvclkhdr_754 @[lib.scala 409:23] + inst rvclkhdr_4 of rvclkhdr_752 @[lib.scala 409:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[lib.scala 411:18] @@ -139054,7 +138994,7 @@ circuit quasar : stbuf_addr[2] <= _T_676 @[lsu_stbuf.scala 169:21] node _T_677 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 170:59] node _T_678 = bits(_T_677, 0, 0) @[lsu_stbuf.scala 170:69] - inst rvclkhdr_5 of rvclkhdr_755 @[lib.scala 409:23] + inst rvclkhdr_5 of rvclkhdr_753 @[lib.scala 409:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[lib.scala 411:18] @@ -139067,7 +139007,7 @@ circuit quasar : stbuf_data[2] <= _T_679 @[lsu_stbuf.scala 170:21] node _T_680 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 169:59] node _T_681 = bits(_T_680, 0, 0) @[lsu_stbuf.scala 169:69] - inst rvclkhdr_6 of rvclkhdr_756 @[lib.scala 409:23] + inst rvclkhdr_6 of rvclkhdr_754 @[lib.scala 409:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 411:18] @@ -139080,7 +139020,7 @@ circuit quasar : stbuf_addr[3] <= _T_682 @[lsu_stbuf.scala 169:21] node _T_683 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 170:59] node _T_684 = bits(_T_683, 0, 0) @[lsu_stbuf.scala 170:69] - inst rvclkhdr_7 of rvclkhdr_757 @[lib.scala 409:23] + inst rvclkhdr_7 of rvclkhdr_755 @[lib.scala 409:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 411:18] @@ -139837,6 +139777,54 @@ circuit quasar : node _T_1311 = cat(_T_1310, _T_1309) @[Cat.scala 29:58] io.stbuf_fwddata_hi_m <= _T_1311 @[lsu_stbuf.scala 272:25] + extmodule gated_latch_756 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_756 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_756 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_757 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_757 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_757 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_758 : output Q : Clock input CK : Clock @@ -139885,54 +139873,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_760 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_760 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_760 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_761 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_761 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_761 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - module lsu_ecc : input clock : Clock input reset : AsyncReset @@ -141449,7 +141389,7 @@ circuit quasar : _T_1152 <= single_ecc_error_hi_any @[lsu_ecc.scala 143:72] io.single_ecc_error_hi_r <= _T_1152 @[lsu_ecc.scala 143:62] node _T_1153 = or(io.lsu_single_ecc_error_m, io.clk_override) @[lsu_ecc.scala 144:87] - inst rvclkhdr of rvclkhdr_758 @[lib.scala 409:23] + inst rvclkhdr of rvclkhdr_756 @[lib.scala 409:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 411:18] @@ -141461,7 +141401,7 @@ circuit quasar : skip @[Reg.scala 28:19] io.sec_data_hi_r <= _T_1154 @[lsu_ecc.scala 144:34] node _T_1155 = or(io.lsu_single_ecc_error_m, io.clk_override) @[lsu_ecc.scala 145:87] - inst rvclkhdr_1 of rvclkhdr_759 @[lib.scala 409:23] + inst rvclkhdr_1 of rvclkhdr_757 @[lib.scala 409:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 411:18] @@ -141489,7 +141429,7 @@ circuit quasar : io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 153:28] io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 154:28] node _T_1165 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_ecc.scala 156:75] - inst rvclkhdr_2 of rvclkhdr_760 @[lib.scala 409:23] + inst rvclkhdr_2 of rvclkhdr_758 @[lib.scala 409:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 411:18] @@ -141501,7 +141441,7 @@ circuit quasar : skip @[Reg.scala 28:19] io.sec_data_hi_r_ff <= _T_1166 @[lsu_ecc.scala 156:23] node _T_1167 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_ecc.scala 157:75] - inst rvclkhdr_3 of rvclkhdr_761 @[lib.scala 409:23] + inst rvclkhdr_3 of rvclkhdr_759 @[lib.scala 409:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 411:18] @@ -142780,7 +142720,7 @@ circuit quasar : node _T_1118 = cat(_T_1117, _T_311) @[Cat.scala 29:58] io.lsu_trigger_match_m <= _T_1118 @[lsu_trigger.scala 20:25] - extmodule gated_latch_762 : + extmodule gated_latch_760 : output Q : Clock input CK : Clock input EN : UInt<1> @@ -142789,12 +142729,12 @@ circuit quasar : defname = gated_latch - module rvclkhdr_762 : + module rvclkhdr_760 : input clock : Clock input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_762 @[lib.scala 334:26] + inst clkhdr of gated_latch_760 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid @@ -142804,7 +142744,7 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_763 : + extmodule gated_latch_761 : output Q : Clock input CK : Clock input EN : UInt<1> @@ -142813,12 +142753,12 @@ circuit quasar : defname = gated_latch - module rvclkhdr_763 : + module rvclkhdr_761 : input clock : Clock input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_763 @[lib.scala 334:26] + inst clkhdr of gated_latch_761 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid @@ -142901,7 +142841,7 @@ circuit quasar : node _T_36 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:67] io.lsu_bus_ibuf_c1_clk <= clock @[lsu_clkdomain.scala 94:26] node _T_37 = bits(io.lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 95:69] - inst rvclkhdr of rvclkhdr_762 @[lib.scala 343:22] + inst rvclkhdr of rvclkhdr_760 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] @@ -142911,7 +142851,7 @@ circuit quasar : node _T_38 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 96:66] io.lsu_bus_buf_c1_clk <= clock @[lsu_clkdomain.scala 96:26] node _T_39 = bits(io.lsu_busm_clken, 0, 0) @[lsu_clkdomain.scala 97:62] - inst rvclkhdr_1 of rvclkhdr_763 @[lib.scala 343:22] + inst rvclkhdr_1 of rvclkhdr_761 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] @@ -142921,6 +142861,54 @@ circuit quasar : node _T_40 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 98:63] io.lsu_free_c2_clk <= clock @[lsu_clkdomain.scala 98:26] + extmodule gated_latch_762 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_762 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_762 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_763 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_763 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_763 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_764 : output Q : Clock input CK : Clock @@ -143161,54 +143149,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_774 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_774 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_774 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_775 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_775 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_775 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - module lsu_bus_buffer : input clock : Clock input reset : AsyncReset @@ -144505,7 +144445,7 @@ circuit quasar : when ibuf_wr_en : @[Reg.scala 28:19] ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - inst rvclkhdr of rvclkhdr_764 @[lib.scala 409:23] + inst rvclkhdr of rvclkhdr_762 @[lib.scala 409:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 411:18] @@ -144521,7 +144461,7 @@ circuit quasar : _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 257:15] - inst rvclkhdr_1 of rvclkhdr_765 @[lib.scala 409:23] + inst rvclkhdr_1 of rvclkhdr_763 @[lib.scala 409:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 411:18] @@ -145511,7 +145451,7 @@ circuit quasar : when _T_1789 : @[Reg.scala 28:19] obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - inst rvclkhdr_2 of rvclkhdr_766 @[lib.scala 409:23] + inst rvclkhdr_2 of rvclkhdr_764 @[lib.scala 409:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 411:18] @@ -145522,7 +145462,7 @@ circuit quasar : _T_1790 <= obuf_addr_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] obuf_addr <= _T_1790 @[lsu_bus_buffer.scala 365:13] - inst rvclkhdr_3 of rvclkhdr_767 @[lib.scala 409:23] + inst rvclkhdr_3 of rvclkhdr_765 @[lib.scala 409:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 411:18] @@ -148685,7 +148625,7 @@ circuit quasar : buf_sz[2] <= _T_4364 @[lsu_bus_buffer.scala 529:10] buf_sz[3] <= _T_4366 @[lsu_bus_buffer.scala 529:10] node _T_4367 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 530:80] - inst rvclkhdr_4 of rvclkhdr_768 @[lib.scala 409:23] + inst rvclkhdr_4 of rvclkhdr_766 @[lib.scala 409:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[lib.scala 411:18] @@ -148696,7 +148636,7 @@ circuit quasar : _T_4368 <= buf_addr_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_4369 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 530:80] - inst rvclkhdr_5 of rvclkhdr_769 @[lib.scala 409:23] + inst rvclkhdr_5 of rvclkhdr_767 @[lib.scala 409:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[lib.scala 411:18] @@ -148707,7 +148647,7 @@ circuit quasar : _T_4370 <= buf_addr_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_4371 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 530:80] - inst rvclkhdr_6 of rvclkhdr_770 @[lib.scala 409:23] + inst rvclkhdr_6 of rvclkhdr_768 @[lib.scala 409:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 411:18] @@ -148718,7 +148658,7 @@ circuit quasar : _T_4372 <= buf_addr_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_4373 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 530:80] - inst rvclkhdr_7 of rvclkhdr_771 @[lib.scala 409:23] + inst rvclkhdr_7 of rvclkhdr_769 @[lib.scala 409:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 411:18] @@ -148756,7 +148696,7 @@ circuit quasar : buf_byteen[1] <= _T_4378 @[lsu_bus_buffer.scala 531:14] buf_byteen[2] <= _T_4380 @[lsu_bus_buffer.scala 531:14] buf_byteen[3] <= _T_4382 @[lsu_bus_buffer.scala 531:14] - inst rvclkhdr_8 of rvclkhdr_772 @[lib.scala 409:23] + inst rvclkhdr_8 of rvclkhdr_770 @[lib.scala 409:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 411:18] @@ -148766,7 +148706,7 @@ circuit quasar : when buf_data_en[0] : @[Reg.scala 28:19] _T_4383 <= buf_data_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - inst rvclkhdr_9 of rvclkhdr_773 @[lib.scala 409:23] + inst rvclkhdr_9 of rvclkhdr_771 @[lib.scala 409:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 411:18] @@ -148776,7 +148716,7 @@ circuit quasar : when buf_data_en[1] : @[Reg.scala 28:19] _T_4384 <= buf_data_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - inst rvclkhdr_10 of rvclkhdr_774 @[lib.scala 409:23] + inst rvclkhdr_10 of rvclkhdr_772 @[lib.scala 409:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 411:18] @@ -148786,7 +148726,7 @@ circuit quasar : when buf_data_en[2] : @[Reg.scala 28:19] _T_4385 <= buf_data_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - inst rvclkhdr_11 of rvclkhdr_775 @[lib.scala 409:23] + inst rvclkhdr_11 of rvclkhdr_773 @[lib.scala 409:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset rvclkhdr_11.io.clk <= clock @[lib.scala 411:18] @@ -150800,6 +150740,54 @@ circuit quasar : _T_95 <= lsu_raw_fwd_lo_m @[lsu.scala 352:67] lsu_raw_fwd_lo_r <= _T_95 @[lsu.scala 352:57] + extmodule gated_latch_774 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_774 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_774 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_775 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_775 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_775 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_776 : output Q : Clock input CK : Clock @@ -150872,54 +150860,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_779 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_779 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_779 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_780 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_780 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_780 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - module pic_ctrl : input clock : Clock input reset : AsyncReset @@ -151125,14 +151065,14 @@ circuit quasar : node _T_27 = and(raddr_config_gw_base_match, picm_rden_ff) @[pic_ctrl.scala 130:108] node _T_28 = or(_T_26, _T_27) @[pic_ctrl.scala 130:76] node gw_config_c1_clken = or(_T_28, io.clk_override) @[pic_ctrl.scala 130:124] - inst rvclkhdr of rvclkhdr_776 @[lib.scala 343:22] + inst rvclkhdr of rvclkhdr_774 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= pic_raddr_c1_clken @[lib.scala 345:16] rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23] pic_raddr_c1_clk <= rvclkhdr.io.l1clk @[pic_ctrl.scala 133:21] - inst rvclkhdr_1 of rvclkhdr_777 @[lib.scala 343:22] + inst rvclkhdr_1 of rvclkhdr_775 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] @@ -151140,7 +151080,7 @@ circuit quasar : rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23] pic_data_c1_clk <= rvclkhdr_1.io.l1clk @[pic_ctrl.scala 134:21] node _T_29 = bits(pic_pri_c1_clken, 0, 0) @[pic_ctrl.scala 135:56] - inst rvclkhdr_2 of rvclkhdr_778 @[lib.scala 343:22] + inst rvclkhdr_2 of rvclkhdr_776 @[lib.scala 343:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] @@ -151148,7 +151088,7 @@ circuit quasar : rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23] pic_pri_c1_clk <= rvclkhdr_2.io.l1clk @[pic_ctrl.scala 135:21] node _T_30 = bits(pic_int_c1_clken, 0, 0) @[pic_ctrl.scala 136:56] - inst rvclkhdr_3 of rvclkhdr_779 @[lib.scala 343:22] + inst rvclkhdr_3 of rvclkhdr_777 @[lib.scala 343:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 344:17] @@ -151157,7 +151097,7 @@ circuit quasar : pic_int_c1_clk <= rvclkhdr_3.io.l1clk @[pic_ctrl.scala 136:21] node _T_31 = or(gw_config_c1_clken, io.io_clk_override) @[pic_ctrl.scala 137:59] node _T_32 = bits(_T_31, 0, 0) @[pic_ctrl.scala 137:81] - inst rvclkhdr_4 of rvclkhdr_780 @[lib.scala 343:22] + inst rvclkhdr_4 of rvclkhdr_778 @[lib.scala 343:22] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[lib.scala 344:17] @@ -155096,6 +155036,54 @@ circuit quasar : mask <= UInt<4>("h02") @[pic_ctrl.scala 406:44] skip @[Conditional.scala 39:67] + extmodule gated_latch_779 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_779 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_779 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_780 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_780 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_780 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_781 : output Q : Clock input CK : Clock @@ -155360,54 +155348,6 @@ circuit quasar : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - extmodule gated_latch_792 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_792 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_792 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - - extmodule gated_latch_793 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = gated_latch - - - module rvclkhdr_793 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of gated_latch_793 @[lib.scala 334:26] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[lib.scala 335:14] - clkhdr.CK <= io.clk @[lib.scala 336:18] - clkhdr.EN <= io.en @[lib.scala 337:18] - clkhdr.SE <= io.scan_mode @[lib.scala 338:18] - module dma_ctrl : input clock : Clock input reset : AsyncReset @@ -156337,7 +156277,7 @@ circuit quasar : node _T_789 = cat(_T_788, _T_757) @[Cat.scala 29:58] fifo_done_bus <= _T_789 @[dma_ctrl.scala 150:20] node _T_790 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 151:84] - inst rvclkhdr of rvclkhdr_781 @[lib.scala 409:23] + inst rvclkhdr of rvclkhdr_779 @[lib.scala 409:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 411:18] @@ -156349,7 +156289,7 @@ circuit quasar : skip @[Reg.scala 28:19] fifo_addr[0] <= _T_791 @[dma_ctrl.scala 151:49] node _T_792 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 151:84] - inst rvclkhdr_1 of rvclkhdr_782 @[lib.scala 409:23] + inst rvclkhdr_1 of rvclkhdr_780 @[lib.scala 409:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 411:18] @@ -156361,7 +156301,7 @@ circuit quasar : skip @[Reg.scala 28:19] fifo_addr[1] <= _T_793 @[dma_ctrl.scala 151:49] node _T_794 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 151:84] - inst rvclkhdr_2 of rvclkhdr_783 @[lib.scala 409:23] + inst rvclkhdr_2 of rvclkhdr_781 @[lib.scala 409:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 411:18] @@ -156373,7 +156313,7 @@ circuit quasar : skip @[Reg.scala 28:19] fifo_addr[2] <= _T_795 @[dma_ctrl.scala 151:49] node _T_796 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 151:84] - inst rvclkhdr_3 of rvclkhdr_784 @[lib.scala 409:23] + inst rvclkhdr_3 of rvclkhdr_782 @[lib.scala 409:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 411:18] @@ -156385,7 +156325,7 @@ circuit quasar : skip @[Reg.scala 28:19] fifo_addr[3] <= _T_797 @[dma_ctrl.scala 151:49] node _T_798 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 151:84] - inst rvclkhdr_4 of rvclkhdr_785 @[lib.scala 409:23] + inst rvclkhdr_4 of rvclkhdr_783 @[lib.scala 409:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[lib.scala 411:18] @@ -156562,7 +156502,7 @@ circuit quasar : node fifo_dbg = cat(_T_873, _T_862) @[Cat.scala 29:58] wire fifo_data : UInt<64>[5] @[dma_ctrl.scala 158:23] node _T_874 = bits(fifo_data_en, 0, 0) @[dma_ctrl.scala 159:88] - inst rvclkhdr_5 of rvclkhdr_786 @[lib.scala 409:23] + inst rvclkhdr_5 of rvclkhdr_784 @[lib.scala 409:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[lib.scala 411:18] @@ -156574,7 +156514,7 @@ circuit quasar : skip @[Reg.scala 28:19] fifo_data[0] <= _T_875 @[dma_ctrl.scala 159:49] node _T_876 = bits(fifo_data_en, 1, 1) @[dma_ctrl.scala 159:88] - inst rvclkhdr_6 of rvclkhdr_787 @[lib.scala 409:23] + inst rvclkhdr_6 of rvclkhdr_785 @[lib.scala 409:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 411:18] @@ -156586,7 +156526,7 @@ circuit quasar : skip @[Reg.scala 28:19] fifo_data[1] <= _T_877 @[dma_ctrl.scala 159:49] node _T_878 = bits(fifo_data_en, 2, 2) @[dma_ctrl.scala 159:88] - inst rvclkhdr_7 of rvclkhdr_788 @[lib.scala 409:23] + inst rvclkhdr_7 of rvclkhdr_786 @[lib.scala 409:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 411:18] @@ -156598,7 +156538,7 @@ circuit quasar : skip @[Reg.scala 28:19] fifo_data[2] <= _T_879 @[dma_ctrl.scala 159:49] node _T_880 = bits(fifo_data_en, 3, 3) @[dma_ctrl.scala 159:88] - inst rvclkhdr_8 of rvclkhdr_789 @[lib.scala 409:23] + inst rvclkhdr_8 of rvclkhdr_787 @[lib.scala 409:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 411:18] @@ -156610,7 +156550,7 @@ circuit quasar : skip @[Reg.scala 28:19] fifo_data[3] <= _T_881 @[dma_ctrl.scala 159:49] node _T_882 = bits(fifo_data_en, 4, 4) @[dma_ctrl.scala 159:88] - inst rvclkhdr_9 of rvclkhdr_790 @[lib.scala 409:23] + inst rvclkhdr_9 of rvclkhdr_788 @[lib.scala 409:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 411:18] @@ -157225,7 +157165,7 @@ circuit quasar : wrbuf_sz <= io.dma_axi.aw.bits.size @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_1271 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 330:60] - inst rvclkhdr_10 of rvclkhdr_791 @[lib.scala 409:23] + inst rvclkhdr_10 of rvclkhdr_789 @[lib.scala 409:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 411:18] @@ -157236,7 +157176,7 @@ circuit quasar : wrbuf_addr <= io.dma_axi.aw.bits.addr @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_1272 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 331:64] - inst rvclkhdr_11 of rvclkhdr_792 @[lib.scala 409:23] + inst rvclkhdr_11 of rvclkhdr_790 @[lib.scala 409:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset rvclkhdr_11.io.clk <= clock @[lib.scala 411:18] @@ -157278,7 +157218,7 @@ circuit quasar : rdbuf_sz <= io.dma_axi.ar.bits.size @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_1284 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 342:60] - inst rvclkhdr_12 of rvclkhdr_793 @[lib.scala 409:23] + inst rvclkhdr_12 of rvclkhdr_791 @[lib.scala 409:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[lib.scala 411:18] diff --git a/quasar.v b/quasar.v index f9f79ad8..7ff52ea4 100644 --- a/quasar.v +++ b/quasar.v @@ -51735,7 +51735,6 @@ module csr_tlu( input [30:0] io_dec_tlu_i0_pc_r, input io_dec_tlu_i0_valid_r, input io_dec_csr_any_unq_d, - output io_dec_tlu_misc_clk_override, output io_dec_tlu_picio_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, @@ -53309,7 +53308,6 @@ module csr_tlu( assign io_dec_tlu_perfcnt1 = perf_csrs_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 2437:29] assign io_dec_tlu_perfcnt2 = perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 2438:29] assign io_dec_tlu_perfcnt3 = perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 2439:29] - assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1757:39] assign io_dec_tlu_picio_clk_override = mcgc[9]; // @[dec_tlu_ctl.scala 1756:39] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1758:39] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1760:39] @@ -55146,7 +55144,6 @@ module dec_tlu_ctl( output [31:0] io_dec_tlu_mtval_wb1, output io_dec_tlu_pipelining_disable, output io_dec_tlu_trace_disable, - output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, output io_dec_tlu_pic_clk_override, @@ -55443,7 +55440,6 @@ module dec_tlu_ctl( wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 283:23] wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 283:23] wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 283:23] - wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 283:23] wire csr_io_dec_tlu_picio_clk_override; // @[dec_tlu_ctl.scala 283:23] wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 283:23] wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 283:23] @@ -56507,7 +56503,6 @@ module dec_tlu_ctl( .io_dec_tlu_i0_pc_r(csr_io_dec_tlu_i0_pc_r), .io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r), .io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d), - .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), .io_dec_tlu_picio_clk_override(csr_io_dec_tlu_picio_clk_override), .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), @@ -56858,7 +56853,6 @@ module dec_tlu_ctl( assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 886:46] assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 902:46] assign io_dec_tlu_trace_disable = csr_io_dec_tlu_trace_disable; // @[dec_tlu_ctl.scala 911:49] - assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 892:46] assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 894:46] assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 896:46] assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 898:46] @@ -58536,7 +58530,6 @@ module dec( input io_dbg_halt_req, input io_dbg_resume_req, output io_dec_tlu_dbg_halted, - output io_dec_tlu_debug_mode, output io_dec_tlu_resume_ack, output io_dec_tlu_mpc_halted_only, output [31:0] io_dec_dbg_rddata, @@ -58592,7 +58585,6 @@ module dec( output [4:0] io_trace_rv_trace_pkt_rv_i_ecause_ip, output io_trace_rv_trace_pkt_rv_i_interrupt_ip, output [31:0] io_trace_rv_trace_pkt_rv_i_tval_ip, - output io_dec_tlu_misc_clk_override, output io_dec_tlu_lsu_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_picio_clk_override, @@ -59174,7 +59166,6 @@ module dec( wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 133:19] wire tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 133:19] wire tlu_io_dec_tlu_trace_disable; // @[dec.scala 133:19] - wire tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 133:19] wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 133:19] wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 133:19] wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 133:19] @@ -59650,7 +59641,6 @@ module dec( .io_dec_tlu_mtval_wb1(tlu_io_dec_tlu_mtval_wb1), .io_dec_tlu_pipelining_disable(tlu_io_dec_tlu_pipelining_disable), .io_dec_tlu_trace_disable(tlu_io_dec_tlu_trace_disable), - .io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override), .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), @@ -59740,7 +59730,6 @@ module dec( assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[dec.scala 286:29] assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[dec.scala 287:29] assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[dec.scala 276:28] - assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[dec.scala 277:28] assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[dec.scala 278:28] assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 279:51] assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[dec.scala 322:21] @@ -59795,7 +59784,6 @@ module dec( assign io_trace_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 316:40] assign io_trace_rv_trace_pkt_rv_i_interrupt_ip = tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 317:43] assign io_trace_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 318:38] - assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 298:35] assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 300:36] assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 302:36] assign io_dec_tlu_picio_clk_override = tlu_io_dec_tlu_picio_clk_override; // @[dec.scala 305:36] @@ -60141,7 +60129,6 @@ module dbg( input io_core_dbg_cmd_fail, output io_dbg_halt_req, output io_dbg_resume_req, - input io_dec_tlu_debug_mode, input io_dec_tlu_dbg_halted, input io_dec_tlu_mpc_halted_only, input io_dec_tlu_resume_ack, @@ -60180,7 +60167,6 @@ module dbg( input io_dbg_dma_dma_dbg_ready, input io_dbg_bus_clk_en, input io_dbg_rst_l, - input io_clk_override, input io_scan_mode ); `ifdef RANDOMIZE_REG_INIT @@ -60257,23 +60243,6 @@ module dbg( wire [3:0] sb_abmem_cmd_size; wire dmcontrol_wren_Q; wire [31:0] abstractcs_reg; - wire _T = io_dmi_reg_en | execute_command; // @[dbg.scala 114:39] - wire _T_1 = dbg_state != 4'h0; // @[dbg.scala 114:70] - wire _T_2 = _T | _T_1; // @[dbg.scala 114:57] - wire _T_3 = _T_2 | dbg_state_en; // @[dbg.scala 114:88] - wire _T_4 = _T_3 | io_dec_tlu_dbg_halted; // @[dbg.scala 114:103] - wire _T_5 = _T_4 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 114:127] - wire _T_6 = _T_5 | io_dec_tlu_debug_mode; // @[dbg.scala 115:32] - wire _T_7 = _T_6 | io_dbg_halt_req; // @[dbg.scala 115:56] - wire _T_9 = _T | sb_state_en; // @[dbg.scala 116:57] - wire _T_10 = sb_state != 4'h0; // @[dbg.scala 116:83] - wire _T_11 = _T_9 | _T_10; // @[dbg.scala 116:71] - wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_io_en; // @[lib.scala 343:22] - wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] - wire rvclkhdr_1_io_en; // @[lib.scala 343:22] wire _T_14 = dmcontrol_reg[0] | io_scan_mode; // @[dbg.scala 121:74] wire dbg_dm_rst_l = io_dbg_rst_l & _T_14; // @[dbg.scala 121:103] wire _T_17 = ~dmcontrol_reg[1]; // @[dbg.scala 122:32] @@ -60344,13 +60313,13 @@ module dbg( wire [31:0] _T_115 = _T_114 & io_dmi_reg_wdata; // @[dbg.scala 158:55] wire [31:0] _T_119 = _T_110 & sb_bus_rdata[63:32]; // @[dbg.scala 158:104] wire [31:0] sbdata1_din = _T_115 | _T_119; // @[dbg.scala 158:74] - wire rvclkhdr_2_io_l1clk; // @[lib.scala 409:23] - wire rvclkhdr_2_io_clk; // @[lib.scala 409:23] - wire rvclkhdr_2_io_en; // @[lib.scala 409:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 409:23] + wire rvclkhdr_io_clk; // @[lib.scala 409:23] + wire rvclkhdr_io_en; // @[lib.scala 409:23] reg [31:0] sbdata0_reg; // @[Reg.scala 27:20] - wire rvclkhdr_3_io_l1clk; // @[lib.scala 409:23] - wire rvclkhdr_3_io_clk; // @[lib.scala 409:23] - wire rvclkhdr_3_io_en; // @[lib.scala 409:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 409:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 409:23] + wire rvclkhdr_1_io_en; // @[lib.scala 409:23] reg [31:0] sbdata1_reg; // @[Reg.scala 27:20] wire sbaddress0_reg_wren0 = _T_96 & _T_28; // @[dbg.scala 163:64] wire sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[dbg.scala 164:52] @@ -60361,9 +60330,9 @@ module dbg( wire [31:0] _T_129 = sbaddress0_reg + _T_127; // @[dbg.scala 166:54] wire [31:0] _T_130 = _T_126 & _T_129; // @[dbg.scala 166:36] wire [31:0] sbaddress0_reg_din = _T_124 | _T_130; // @[dbg.scala 165:81] - wire rvclkhdr_4_io_l1clk; // @[lib.scala 409:23] - wire rvclkhdr_4_io_clk; // @[lib.scala 409:23] - wire rvclkhdr_4_io_en; // @[lib.scala 409:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 409:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 409:23] + wire rvclkhdr_2_io_en; // @[lib.scala 409:23] reg [31:0] _T_131; // @[Reg.scala 27:20] wire sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[dbg.scala 170:94] wire _T_136 = ~io_dmi_reg_wr_en; // @[dbg.scala 171:45] @@ -60489,13 +60458,13 @@ module dbg( wire [15:0] temp_command_din_31_16 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:19],command_postexec_din,command_transfer_din,io_dmi_reg_wdata[16]}; // @[Cat.scala 29:58] wire [15:0] temp_command_din_15_0 = command_wren ? io_dmi_reg_wdata[15:0] : dbg_cmd_next_addr[15:0]; // @[dbg.scala 253:37] reg _T_361; // @[dbg.scala 257:12] - wire rvclkhdr_5_io_l1clk; // @[lib.scala 409:23] - wire rvclkhdr_5_io_clk; // @[lib.scala 409:23] - wire rvclkhdr_5_io_en; // @[lib.scala 409:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 409:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 409:23] + wire rvclkhdr_3_io_en; // @[lib.scala 409:23] reg [15:0] temp_command_reg_31_16; // @[Reg.scala 27:20] - wire rvclkhdr_6_io_l1clk; // @[lib.scala 409:23] - wire rvclkhdr_6_io_clk; // @[lib.scala 409:23] - wire rvclkhdr_6_io_en; // @[lib.scala 409:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 409:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 409:23] + wire rvclkhdr_4_io_en; // @[lib.scala 409:23] reg [15:0] temp_command_reg_15_0; // @[Reg.scala 27:20] wire _T_367 = _T_96 & _T_219; // @[dbg.scala 266:58] wire _T_368 = dbg_state == 4'h2; // @[dbg.scala 266:102] @@ -60515,9 +60484,9 @@ module dbg( wire [31:0] _T_385 = data0_reg_wren2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_387 = _T_385 & sb_bus_rdata[31:0]; // @[dbg.scala 272:31] wire [31:0] data0_din = _T_383 | _T_387; // @[dbg.scala 271:52] - wire rvclkhdr_7_io_l1clk; // @[lib.scala 409:23] - wire rvclkhdr_7_io_clk; // @[lib.scala 409:23] - wire rvclkhdr_7_io_en; // @[lib.scala 409:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 409:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 409:23] + wire rvclkhdr_5_io_en; // @[lib.scala 409:23] reg [31:0] data0_reg; // @[Reg.scala 27:20] wire _T_390 = _T_96 & _T_221; // @[dbg.scala 277:59] wire _T_392 = _T_390 & _T_368; // @[dbg.scala 277:92] @@ -60531,9 +60500,9 @@ module dbg( wire [31:0] _T_408 = data1_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_410 = _T_408 & dbg_cmd_next_addr; // @[dbg.scala 281:92] wire [31:0] data1_din = _T_406 | _T_410; // @[dbg.scala 281:64] - wire rvclkhdr_8_io_l1clk; // @[lib.scala 409:23] - wire rvclkhdr_8_io_clk; // @[lib.scala 409:23] - wire rvclkhdr_8_io_en; // @[lib.scala 409:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 409:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 409:23] + wire rvclkhdr_6_io_en; // @[lib.scala 409:23] reg [31:0] _T_411; // @[Reg.scala 27:20] reg sb_abmem_cmd_done; // @[Reg.scala 27:20] reg sb_abmem_data_done; // @[Reg.scala 27:20] @@ -60699,9 +60668,9 @@ module dbg( wire _T_595 = io_dbg_rst_l & _T_14; // @[dbg.scala 385:68] wire _T_597 = _T_595 & reset; // @[dbg.scala 385:95] reg [3:0] _T_598; // @[Reg.scala 27:20] - wire rvclkhdr_9_io_l1clk; // @[lib.scala 409:23] - wire rvclkhdr_9_io_clk; // @[lib.scala 409:23] - wire rvclkhdr_9_io_en; // @[lib.scala 409:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 409:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 409:23] + wire rvclkhdr_7_io_en; // @[lib.scala 409:23] reg [31:0] _T_599; // @[Reg.scala 27:20] wire _T_600 = abmem_addr_in_dccm_region | abmem_addr_in_iccm_region; // @[dbg.scala 392:58] wire abmem_addr_core_local = _T_600 | abmem_addr_in_pic_region; // @[dbg.scala 392:86] @@ -60883,12 +60852,12 @@ module dbg( wire [63:0] _T_871 = _T_805 & _T_870; // @[dbg.scala 558:40] wire [63:0] _T_872 = _T_862 | _T_871; // @[dbg.scala 557:121] wire [63:0] _T_877 = _T_812 & io_sb_axi_r_bits_data; // @[dbg.scala 559:40] - rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + rvclkhdr rvclkhdr ( // @[lib.scala 409:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) ); - rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 409:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en) @@ -60923,16 +60892,6 @@ module dbg( .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en) ); - rvclkhdr rvclkhdr_8 ( // @[lib.scala 409:23] - .io_l1clk(rvclkhdr_8_io_l1clk), - .io_clk(rvclkhdr_8_io_clk), - .io_en(rvclkhdr_8_io_en) - ); - rvclkhdr rvclkhdr_9 ( // @[lib.scala 409:23] - .io_l1clk(rvclkhdr_9_io_l1clk), - .io_clk(rvclkhdr_9_io_clk), - .io_en(rvclkhdr_9_io_en) - ); assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 405:21] assign io_dbg_core_rst_l = _T_17 | io_scan_mode; // @[dbg.scala 122:28] assign io_dbg_halt_req = _T_412 ? dmcontrol_reg[31] : _GEN_90; // @[dbg.scala 294:25 dbg.scala 306:23 dbg.scala 311:23 dbg.scala 321:29 dbg.scala 326:23 dbg.scala 331:23 dbg.scala 336:23 dbg.scala 345:29 dbg.scala 352:25 dbg.scala 359:29 dbg.scala 364:29 dbg.scala 369:23] @@ -61002,27 +60961,23 @@ module dbg( assign sb_abmem_cmd_size = {{1'd0}, _T_737}; // @[dbg.scala 488:34] assign dmcontrol_wren_Q = _T_163; // @[dbg.scala 183:21] assign abstractcs_reg = {_T_313,_T_311}; // @[dbg.scala 238:20] - assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_io_en = _T_7 | io_clk_override; // @[lib.scala 345:16] - assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_1_io_en = _T_11 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_io_clk = clock; // @[lib.scala 411:18] + assign rvclkhdr_io_en = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 412:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 411:18] + assign rvclkhdr_1_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 412:17] assign rvclkhdr_2_io_clk = clock; // @[lib.scala 411:18] - assign rvclkhdr_2_io_en = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 412:17] + assign rvclkhdr_2_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 412:17] assign rvclkhdr_3_io_clk = clock; // @[lib.scala 411:18] - assign rvclkhdr_3_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 412:17] + assign rvclkhdr_3_io_en = command_wren; // @[lib.scala 412:17] assign rvclkhdr_4_io_clk = clock; // @[lib.scala 411:18] - assign rvclkhdr_4_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 412:17] + assign rvclkhdr_4_io_en = command_wren | _T_344; // @[lib.scala 412:17] assign rvclkhdr_5_io_clk = clock; // @[lib.scala 411:18] - assign rvclkhdr_5_io_en = command_wren; // @[lib.scala 412:17] + assign rvclkhdr_5_io_en = _T_376 | data0_reg_wren2; // @[lib.scala 412:17] assign rvclkhdr_6_io_clk = clock; // @[lib.scala 411:18] - assign rvclkhdr_6_io_en = command_wren | _T_344; // @[lib.scala 412:17] - assign rvclkhdr_7_io_clk = clock; // @[lib.scala 411:18] - assign rvclkhdr_7_io_en = _T_376 | data0_reg_wren2; // @[lib.scala 412:17] - assign rvclkhdr_8_io_clk = clock; // @[lib.scala 411:18] - assign rvclkhdr_8_io_en = data1_reg_wren0 | data1_reg_wren1; // @[lib.scala 412:17] + assign rvclkhdr_6_io_en = data1_reg_wren0 | data1_reg_wren1; // @[lib.scala 412:17] assign dbg_nxtstate = _T_412 ? _T_415 : _GEN_88; // @[dbg.scala 290:25 dbg.scala 304:23 dbg.scala 309:23 dbg.scala 314:20 dbg.scala 324:23 dbg.scala 329:23 dbg.scala 334:23 dbg.scala 343:29 dbg.scala 348:25 dbg.scala 355:29 dbg.scala 367:20] - assign rvclkhdr_9_io_clk = clock; // @[lib.scala 411:18] - assign rvclkhdr_9_io_en = io_dmi_reg_en; // @[lib.scala 412:17] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 411:18] + assign rvclkhdr_7_io_en = io_dmi_reg_en; // @[lib.scala 412:17] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -61200,35 +61155,35 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin temp_sbcs_22 <= 1'h0; end else if (sbcs_sbbusyerror_wren) begin temp_sbcs_22 <= sbcs_sbbusyerror_din; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin temp_sbcs_21 <= 1'h0; end else if (sbcs_sbbusy_wren) begin temp_sbcs_21 <= sbcs_sbbusy_din; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin temp_sbcs_20 <= 1'h0; end else if (sbcs_wren) begin temp_sbcs_20 <= io_dmi_reg_wdata[20]; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin temp_sbcs_19_15 <= 5'h0; end else if (sbcs_wren) begin temp_sbcs_19_15 <= _T_43; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin temp_sbcs_14_12 <= 3'h0; end else if (sbcs_sberror_wren) begin @@ -61284,49 +61239,49 @@ end // initial _T_131 <= sbaddress0_reg_din; end end - always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin dm_temp <= 4'h0; end else if (dmcontrol_wren) begin dm_temp <= _T_154; end end - always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin + always @(posedge clock or posedge io_dbg_rst_l) begin if (io_dbg_rst_l) begin dm_temp_0 <= 1'h0; end else if (dmcontrol_wren) begin dm_temp_0 <= io_dmi_reg_wdata[0]; end end - always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin _T_163 <= 1'h0; end else begin _T_163 <= _T_144 & io_dmi_reg_wr_en; end end - always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin _T_202 <= 1'h0; end else if (dmstatus_resumeack_wren) begin _T_202 <= _T_184; end end - always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin _T_205 <= 1'h0; end else begin _T_205 <= io_dec_tlu_dbg_halted & _T_203; end end - always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + always @(posedge clock or posedge reset) begin if (reset) begin _T_206 <= 1'h0; end else begin _T_206 <= dmstatus_haveresetn_wren | _T_206; end end - always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin abs_temp_12 <= 1'h0; end else if (abstractcs_busy_wren) begin @@ -61339,7 +61294,7 @@ end // initial end end end - always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin abs_temp_10_8 <= 3'h0; end else if (abstractcs_error_sel0) begin @@ -61360,14 +61315,14 @@ end // initial abs_temp_10_8 <= abstractcs_reg[10:8]; end end - always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin abstractauto_reg <= 2'h0; end else if (abstractauto_reg_wren) begin abstractauto_reg <= io_dmi_reg_wdata[1:0]; end end - always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin _T_361 <= 1'h0; end else begin @@ -61402,7 +61357,7 @@ end // initial _T_411 <= data1_din; end end - always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin sb_abmem_cmd_done <= 1'h0; end else if (sb_abmem_cmd_done_en) begin @@ -61423,7 +61378,7 @@ end // initial end end end - always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin sb_abmem_data_done <= 1'h0; end else if (sb_abmem_data_done_en) begin @@ -61444,7 +61399,7 @@ end // initial end end end - always @(posedge rvclkhdr_io_l1clk or posedge _T_597) begin + always @(posedge clock or posedge _T_597) begin if (_T_597) begin _T_598 <= 4'h0; end else if (dbg_state_en) begin @@ -61502,7 +61457,7 @@ end // initial _T_599 <= dmi_reg_rdata_din; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin + always @(posedge clock or posedge dbg_dm_rst_l) begin if (dbg_dm_rst_l) begin _T_734 <= 4'h0; end else if (sb_state_en) begin @@ -82471,7 +82426,6 @@ module quasar( wire dec_io_dbg_halt_req; // @[quasar.scala 77:19] wire dec_io_dbg_resume_req; // @[quasar.scala 77:19] wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 77:19] - wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 77:19] wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 77:19] wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 77:19] wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 77:19] @@ -82527,7 +82481,6 @@ module quasar( wire [4:0] dec_io_trace_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 77:19] wire dec_io_trace_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 77:19] wire [31:0] dec_io_trace_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 77:19] - wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 77:19] wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 77:19] wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 77:19] wire dec_io_dec_tlu_picio_clk_override; // @[quasar.scala 77:19] @@ -82728,7 +82681,6 @@ module quasar( wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 78:19] wire dbg_io_dbg_halt_req; // @[quasar.scala 78:19] wire dbg_io_dbg_resume_req; // @[quasar.scala 78:19] - wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 78:19] wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 78:19] wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 78:19] wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 78:19] @@ -82767,7 +82719,6 @@ module quasar( wire dbg_io_dbg_dma_dma_dbg_ready; // @[quasar.scala 78:19] wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 78:19] wire dbg_io_dbg_rst_l; // @[quasar.scala 78:19] - wire dbg_io_clk_override; // @[quasar.scala 78:19] wire dbg_io_scan_mode; // @[quasar.scala 78:19] wire exu_clock; // @[quasar.scala 79:19] wire exu_reset; // @[quasar.scala 79:19] @@ -83305,7 +83256,6 @@ module quasar( .io_dbg_halt_req(dec_io_dbg_halt_req), .io_dbg_resume_req(dec_io_dbg_resume_req), .io_dec_tlu_dbg_halted(dec_io_dec_tlu_dbg_halted), - .io_dec_tlu_debug_mode(dec_io_dec_tlu_debug_mode), .io_dec_tlu_resume_ack(dec_io_dec_tlu_resume_ack), .io_dec_tlu_mpc_halted_only(dec_io_dec_tlu_mpc_halted_only), .io_dec_dbg_rddata(dec_io_dec_dbg_rddata), @@ -83361,7 +83311,6 @@ module quasar( .io_trace_rv_trace_pkt_rv_i_ecause_ip(dec_io_trace_rv_trace_pkt_rv_i_ecause_ip), .io_trace_rv_trace_pkt_rv_i_interrupt_ip(dec_io_trace_rv_trace_pkt_rv_i_interrupt_ip), .io_trace_rv_trace_pkt_rv_i_tval_ip(dec_io_trace_rv_trace_pkt_rv_i_tval_ip), - .io_dec_tlu_misc_clk_override(dec_io_dec_tlu_misc_clk_override), .io_dec_tlu_lsu_clk_override(dec_io_dec_tlu_lsu_clk_override), .io_dec_tlu_pic_clk_override(dec_io_dec_tlu_pic_clk_override), .io_dec_tlu_picio_clk_override(dec_io_dec_tlu_picio_clk_override), @@ -83564,7 +83513,6 @@ module quasar( .io_core_dbg_cmd_fail(dbg_io_core_dbg_cmd_fail), .io_dbg_halt_req(dbg_io_dbg_halt_req), .io_dbg_resume_req(dbg_io_dbg_resume_req), - .io_dec_tlu_debug_mode(dbg_io_dec_tlu_debug_mode), .io_dec_tlu_dbg_halted(dbg_io_dec_tlu_dbg_halted), .io_dec_tlu_mpc_halted_only(dbg_io_dec_tlu_mpc_halted_only), .io_dec_tlu_resume_ack(dbg_io_dec_tlu_resume_ack), @@ -83603,7 +83551,6 @@ module quasar( .io_dbg_dma_dma_dbg_ready(dbg_io_dbg_dma_dma_dbg_ready), .io_dbg_bus_clk_en(dbg_io_dbg_bus_clk_en), .io_dbg_rst_l(dbg_io_dbg_rst_l), - .io_clk_override(dbg_io_clk_override), .io_scan_mode(dbg_io_scan_mode) ); exu exu ( // @[quasar.scala 79:19] @@ -84333,7 +84280,6 @@ module quasar( assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 195:26] assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 196:28] assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 197:28] - assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 198:29] assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 199:29] assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 200:34] assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 201:29] @@ -84352,7 +84298,6 @@ module quasar( assign dbg_io_dbg_dma_dma_dbg_ready = dma_ctrl_io_dbg_dma_dma_dbg_ready; // @[quasar.scala 221:23] assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 206:25] assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 207:20] - assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 208:23] assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 209:20] assign exu_clock = io_active_l2clk; // @[quasar.scala 170:13] assign exu_reset = io_core_rst_l; // @[quasar.scala 169:13] diff --git a/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala index 128e7896..3a5a2d91 100644 --- a/src/main/scala/dbg/dbg.scala +++ b/src/main/scala/dbg/dbg.scala @@ -115,8 +115,8 @@ class dbg extends Module with lib with RequireAsyncReset { io.dec_tlu_mpc_halted_only | io.dec_tlu_debug_mode | io.dbg_halt_req | io.clk_override val sb_free_clken = io.dmi_reg_en | execute_command | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override; - val dbg_free_clk = rvclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc - val sb_free_clk = rvclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc + val dbg_free_clk = rvoclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc + val sb_free_clk = rvoclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc val dbg_dm_rst_l = (io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)).asAsyncReset() io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool() | io.scan_mode diff --git a/target/scala-2.12/classes/dbg/dbg.class b/target/scala-2.12/classes/dbg/dbg.class index ac6aee480b41b3febbb3b4662dff43694b1f3b3b..58f89393c88b019c294e6b35efb622ae398ba90e 100644 GIT binary patch delta 51 zcmV-30L=fv;S#~&60lg(1APU4lUveX0ZD_q(ucd!0k^x-0{l(^Ntd`G19JgMhb$rk Jw=5zAm5z7V72*H@ delta 51 zcmV-30L=fv;S#~&60lg(19k;>lUveX0V{*M(ucd!0k^x-0{l(^E0?$-19Jf@hb$rk Jw=5zAm5y#?6?y;w