diff --git a/.idea/.gitignore b/.idea/.gitignore new file mode 100644 index 00000000..26d33521 --- /dev/null +++ b/.idea/.gitignore @@ -0,0 +1,3 @@ +# Default ignored files +/shelf/ +/workspace.xml diff --git a/.idea/codeStyles/Project.xml b/.idea/codeStyles/Project.xml new file mode 100644 index 00000000..919ce1f1 --- /dev/null +++ b/.idea/codeStyles/Project.xml @@ -0,0 +1,7 @@ + + + + + + \ No newline at end of file diff --git a/.idea/codeStyles/codeStyleConfig.xml b/.idea/codeStyles/codeStyleConfig.xml new file mode 100644 index 00000000..a55e7a17 --- /dev/null +++ b/.idea/codeStyles/codeStyleConfig.xml @@ -0,0 +1,5 @@ + + + + \ No newline at end of file diff --git a/.idea/compiler.xml b/.idea/compiler.xml new file mode 100644 index 00000000..4394bdd6 --- /dev/null +++ b/.idea/compiler.xml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__com_github_nscala_time_nscala_time_2_12_2_22_0_jar.xml b/.idea/libraries/sbt__com_github_nscala_time_nscala_time_2_12_2_22_0_jar.xml new file mode 100644 index 00000000..d56d55ba --- /dev/null +++ b/.idea/libraries/sbt__com_github_nscala_time_nscala_time_2_12_2_22_0_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__com_github_scopt_scopt_2_12_3_7_1_jar.xml b/.idea/libraries/sbt__com_github_scopt_scopt_2_12_3_7_1_jar.xml new file mode 100644 index 00000000..45d80edf --- /dev/null +++ b/.idea/libraries/sbt__com_github_scopt_scopt_2_12_3_7_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__com_google_protobuf_protobuf_java_3_9_0_jar.xml b/.idea/libraries/sbt__com_google_protobuf_protobuf_java_3_9_0_jar.xml new file mode 100644 index 00000000..7e06c9f1 --- /dev/null +++ b/.idea/libraries/sbt__com_google_protobuf_protobuf_java_3_9_0_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__com_lihaoyi_utest_2_12_0_6_6_jar.xml b/.idea/libraries/sbt__com_lihaoyi_utest_2_12_0_6_6_jar.xml new file mode 100644 index 00000000..82d46fb2 --- /dev/null +++ b/.idea/libraries/sbt__com_lihaoyi_utest_2_12_0_6_6_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__com_thoughtworks_paranamer_paranamer_2_8_jar.xml b/.idea/libraries/sbt__com_thoughtworks_paranamer_paranamer_2_8_jar.xml new file mode 100644 index 00000000..ffb2cb32 --- /dev/null +++ b/.idea/libraries/sbt__com_thoughtworks_paranamer_paranamer_2_8_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__edu_berkeley_cs_chisel3_2_12_3_3_1_jar.xml b/.idea/libraries/sbt__edu_berkeley_cs_chisel3_2_12_3_3_1_jar.xml new file mode 100644 index 00000000..79841c23 --- /dev/null +++ b/.idea/libraries/sbt__edu_berkeley_cs_chisel3_2_12_3_3_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__edu_berkeley_cs_chisel3_core_2_12_3_3_1_jar.xml b/.idea/libraries/sbt__edu_berkeley_cs_chisel3_core_2_12_3_3_1_jar.xml new file mode 100644 index 00000000..5878ea5c --- /dev/null +++ b/.idea/libraries/sbt__edu_berkeley_cs_chisel3_core_2_12_3_3_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__edu_berkeley_cs_chisel3_macros_2_12_3_3_1_jar.xml b/.idea/libraries/sbt__edu_berkeley_cs_chisel3_macros_2_12_3_3_1_jar.xml new file mode 100644 index 00000000..3365a7f8 --- /dev/null +++ b/.idea/libraries/sbt__edu_berkeley_cs_chisel3_macros_2_12_3_3_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__edu_berkeley_cs_chisel_iotesters_2_12_1_4_1_jar.xml b/.idea/libraries/sbt__edu_berkeley_cs_chisel_iotesters_2_12_1_4_1_jar.xml new file mode 100644 index 00000000..cb05281b --- /dev/null +++ b/.idea/libraries/sbt__edu_berkeley_cs_chisel_iotesters_2_12_1_4_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__edu_berkeley_cs_chiseltest_2_12_0_2_1_jar.xml b/.idea/libraries/sbt__edu_berkeley_cs_chiseltest_2_12_0_2_1_jar.xml new file mode 100644 index 00000000..2d332937 --- /dev/null +++ b/.idea/libraries/sbt__edu_berkeley_cs_chiseltest_2_12_0_2_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__edu_berkeley_cs_firrtl_2_12_1_3_1_jar.xml b/.idea/libraries/sbt__edu_berkeley_cs_firrtl_2_12_1_3_1_jar.xml new file mode 100644 index 00000000..c8cb07f7 --- /dev/null +++ b/.idea/libraries/sbt__edu_berkeley_cs_firrtl_2_12_1_3_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__edu_berkeley_cs_firrtl_interpreter_2_12_1_3_1_jar.xml b/.idea/libraries/sbt__edu_berkeley_cs_firrtl_interpreter_2_12_1_3_1_jar.xml new file mode 100644 index 00000000..1758a80a --- /dev/null +++ b/.idea/libraries/sbt__edu_berkeley_cs_firrtl_interpreter_2_12_1_3_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__edu_berkeley_cs_treadle_2_12_1_2_1_jar.xml b/.idea/libraries/sbt__edu_berkeley_cs_treadle_2_12_1_2_1_jar.xml new file mode 100644 index 00000000..03f4e628 --- /dev/null +++ b/.idea/libraries/sbt__edu_berkeley_cs_treadle_2_12_1_2_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__joda_time_joda_time_2_10_1_jar.xml b/.idea/libraries/sbt__joda_time_joda_time_2_10_1_jar.xml new file mode 100644 index 00000000..0682bdf8 --- /dev/null +++ b/.idea/libraries/sbt__joda_time_joda_time_2_10_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__junit_junit_4_13_jar.xml b/.idea/libraries/sbt__junit_junit_4_13_jar.xml new file mode 100644 index 00000000..8f6ec208 --- /dev/null +++ b/.idea/libraries/sbt__junit_junit_4_13_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__net_jcazevedo_moultingyaml_2_12_0_4_2_jar.xml b/.idea/libraries/sbt__net_jcazevedo_moultingyaml_2_12_0_4_2_jar.xml new file mode 100644 index 00000000..cadbf25d --- /dev/null +++ b/.idea/libraries/sbt__net_jcazevedo_moultingyaml_2_12_0_4_2_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_antlr_antlr4_runtime_4_7_1_jar.xml b/.idea/libraries/sbt__org_antlr_antlr4_runtime_4_7_1_jar.xml new file mode 100644 index 00000000..dc77190b --- /dev/null +++ b/.idea/libraries/sbt__org_antlr_antlr4_runtime_4_7_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_apache_commons_commons_lang3_3_9_jar.xml b/.idea/libraries/sbt__org_apache_commons_commons_lang3_3_9_jar.xml new file mode 100644 index 00000000..cb89d0cf --- /dev/null +++ b/.idea/libraries/sbt__org_apache_commons_commons_lang3_3_9_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_apache_commons_commons_text_1_8_jar.xml b/.idea/libraries/sbt__org_apache_commons_commons_text_1_8_jar.xml new file mode 100644 index 00000000..31a0fdec --- /dev/null +++ b/.idea/libraries/sbt__org_apache_commons_commons_text_1_8_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_fusesource_jansi_jansi_1_11_jar.xml b/.idea/libraries/sbt__org_fusesource_jansi_jansi_1_11_jar.xml new file mode 100644 index 00000000..0d83386d --- /dev/null +++ b/.idea/libraries/sbt__org_fusesource_jansi_jansi_1_11_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_hamcrest_hamcrest_core_1_3_jar.xml b/.idea/libraries/sbt__org_hamcrest_hamcrest_core_1_3_jar.xml new file mode 100644 index 00000000..65cc396a --- /dev/null +++ b/.idea/libraries/sbt__org_hamcrest_hamcrest_core_1_3_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_joda_joda_convert_2_2_0_jar.xml b/.idea/libraries/sbt__org_joda_joda_convert_2_2_0_jar.xml new file mode 100644 index 00000000..740ab90f --- /dev/null +++ b/.idea/libraries/sbt__org_joda_joda_convert_2_2_0_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_json4s_json4s_ast_2_12_3_6_8_jar.xml b/.idea/libraries/sbt__org_json4s_json4s_ast_2_12_3_6_8_jar.xml new file mode 100644 index 00000000..b3326cde --- /dev/null +++ b/.idea/libraries/sbt__org_json4s_json4s_ast_2_12_3_6_8_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_json4s_json4s_core_2_12_3_6_8_jar.xml b/.idea/libraries/sbt__org_json4s_json4s_core_2_12_3_6_8_jar.xml new file mode 100644 index 00000000..30512d9a --- /dev/null +++ b/.idea/libraries/sbt__org_json4s_json4s_core_2_12_3_6_8_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_json4s_json4s_native_2_12_3_6_8_jar.xml b/.idea/libraries/sbt__org_json4s_json4s_native_2_12_3_6_8_jar.xml new file mode 100644 index 00000000..692cebb7 --- /dev/null +++ b/.idea/libraries/sbt__org_json4s_json4s_native_2_12_3_6_8_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_json4s_json4s_scalap_2_12_3_6_8_jar.xml b/.idea/libraries/sbt__org_json4s_json4s_scalap_2_12_3_6_8_jar.xml new file mode 100644 index 00000000..75d91e6e --- /dev/null +++ b/.idea/libraries/sbt__org_json4s_json4s_scalap_2_12_3_6_8_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_portable_scala_portable_scala_reflect_2_12_0_1_0_jar.xml b/.idea/libraries/sbt__org_portable_scala_portable_scala_reflect_2_12_0_1_0_jar.xml new file mode 100644 index 00000000..c2cadfc1 --- /dev/null +++ b/.idea/libraries/sbt__org_portable_scala_portable_scala_reflect_2_12_0_1_0_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_scala_lang_modules_scala_jline_2_12_1_jar.xml b/.idea/libraries/sbt__org_scala_lang_modules_scala_jline_2_12_1_jar.xml new file mode 100644 index 00000000..86a8a20b --- /dev/null +++ b/.idea/libraries/sbt__org_scala_lang_modules_scala_jline_2_12_1_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_scala_lang_modules_scala_xml_2_12_1_2_0_jar.xml b/.idea/libraries/sbt__org_scala_lang_modules_scala_xml_2_12_1_2_0_jar.xml new file mode 100644 index 00000000..dc24486f --- /dev/null +++ b/.idea/libraries/sbt__org_scala_lang_modules_scala_xml_2_12_1_2_0_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_scala_lang_scala_library_2_12_10_jar.xml b/.idea/libraries/sbt__org_scala_lang_scala_library_2_12_10_jar.xml new file mode 100644 index 00000000..c4e3584a --- /dev/null +++ b/.idea/libraries/sbt__org_scala_lang_scala_library_2_12_10_jar.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_scala_lang_scala_reflect_2_12_10_jar.xml b/.idea/libraries/sbt__org_scala_lang_scala_reflect_2_12_10_jar.xml new file mode 100644 index 00000000..ea3f85d3 --- /dev/null +++ b/.idea/libraries/sbt__org_scala_lang_scala_reflect_2_12_10_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_scala_sbt_test_interface_1_0_jar.xml b/.idea/libraries/sbt__org_scala_sbt_test_interface_1_0_jar.xml new file mode 100644 index 00000000..cbdd0382 --- /dev/null +++ b/.idea/libraries/sbt__org_scala_sbt_test_interface_1_0_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_scalacheck_scalacheck_2_12_1_14_3_jar.xml b/.idea/libraries/sbt__org_scalacheck_scalacheck_2_12_1_14_3_jar.xml new file mode 100644 index 00000000..b0e9ff6a --- /dev/null +++ b/.idea/libraries/sbt__org_scalacheck_scalacheck_2_12_1_14_3_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_scalactic_scalactic_2_12_3_0_8_jar.xml b/.idea/libraries/sbt__org_scalactic_scalactic_2_12_3_0_8_jar.xml new file mode 100644 index 00000000..d4334d86 --- /dev/null +++ b/.idea/libraries/sbt__org_scalactic_scalactic_2_12_3_0_8_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_scalatest_scalatest_2_12_3_0_8_jar.xml b/.idea/libraries/sbt__org_scalatest_scalatest_2_12_3_0_8_jar.xml new file mode 100644 index 00000000..cb38ac92 --- /dev/null +++ b/.idea/libraries/sbt__org_scalatest_scalatest_2_12_3_0_8_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml b/.idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml new file mode 100644 index 00000000..071fd46c --- /dev/null +++ b/.idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/misc.xml b/.idea/misc.xml new file mode 100644 index 00000000..b85c8a3d --- /dev/null +++ b/.idea/misc.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/.idea/modules.xml b/.idea/modules.xml new file mode 100644 index 00000000..4f1654a6 --- /dev/null +++ b/.idea/modules.xml @@ -0,0 +1,9 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/modules/Quasar-build.iml b/.idea/modules/Quasar-build.iml new file mode 100644 index 00000000..e91f2adb --- /dev/null +++ b/.idea/modules/Quasar-build.iml @@ -0,0 +1,114 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/modules/Quasar.iml b/.idea/modules/Quasar.iml new file mode 100644 index 00000000..875b1741 --- /dev/null +++ b/.idea/modules/Quasar.iml @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/sbt.xml b/.idea/sbt.xml new file mode 100644 index 00000000..fffb6e32 --- /dev/null +++ b/.idea/sbt.xml @@ -0,0 +1,17 @@ + + + + + + \ No newline at end of file diff --git a/.idea/scala_compiler.xml b/.idea/scala_compiler.xml new file mode 100644 index 00000000..bd930e1f --- /dev/null +++ b/.idea/scala_compiler.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/vcs.xml b/.idea/vcs.xml new file mode 100644 index 00000000..35eb1ddf --- /dev/null +++ b/.idea/vcs.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/design/firrtl_black_box_resource_files.f b/design/firrtl_black_box_resource_files.f index 283e8643..8bc80b66 100644 --- a/design/firrtl_black_box_resource_files.f +++ b/design/firrtl_black_box_resource_files.f @@ -1,3 +1,3 @@ -/home/waleedbinehsan/Downloads/Quasar/design/gated_latch.v -/home/waleedbinehsan/Downloads/Quasar/design/dmi_wrapper.sv -/home/waleedbinehsan/Downloads/Quasar/design/mem.sv \ No newline at end of file +/home/waleedbinehsan/Desktop/Quasar/design/gated_latch.v +/home/waleedbinehsan/Desktop/Quasar/design/dmi_wrapper.sv +/home/waleedbinehsan/Desktop/Quasar/design/mem.sv \ No newline at end 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a/design/project/target/config-classes/$ef9cc2bd073163b715b8.class b/design/project/target/config-classes/$ef9cc2bd073163b715b8.class new file mode 100644 index 00000000..3fdc18dd Binary files /dev/null and b/design/project/target/config-classes/$ef9cc2bd073163b715b8.class differ diff --git a/design/project/target/streams/_global/update/_global/streams/out b/design/project/target/streams/_global/update/_global/streams/out index c2ecb3a4..d3e0dc25 100644 --- a/design/project/target/streams/_global/update/_global/streams/out +++ b/design/project/target/streams/_global/update/_global/streams/out @@ -1,3 +1,3 @@ -[debug] "not up to date. inChanged = true, force = false -[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Downloads/Quasar/design/project/"), "design-build")... -[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Downloads/Quasar/design/project/"), "design-build") +[debug] "not up to date. inChanged = false, force = false +[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/design/project/"), "design-build")... +[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/design/project/"), "design-build") diff --git a/design/project/target/streams/compile/_global/_global/compileOutputs/previous b/design/project/target/streams/compile/_global/_global/compileOutputs/previous index c5b56d08..e8309c76 100644 --- a/design/project/target/streams/compile/_global/_global/compileOutputs/previous +++ b/design/project/target/streams/compile/_global/_global/compileOutputs/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Downloads/Quasar/design/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]] \ No newline at end of file +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/Quasar/design/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/design/project/target/streams/compile/compileIncremental/_global/streams/out b/design/project/target/streams/compile/compileIncremental/_global/streams/out index a24bed6f..6db8e09d 100644 --- a/design/project/target/streams/compile/compileIncremental/_global/streams/out +++ b/design/project/target/streams/compile/compileIncremental/_global/streams/out @@ -1 +1 @@ -[debug] Full compilation, no sources in previous analysis. +[debug] Full compilation, no sources in previous analysis. diff --git a/design/project/target/streams/compile/copyResources/_global/streams/out b/design/project/target/streams/compile/copyResources/_global/streams/out index 49995276..f25042f2 100644 --- a/design/project/target/streams/compile/copyResources/_global/streams/out +++ b/design/project/target/streams/compile/copyResources/_global/streams/out @@ -1,2 +1,2 @@ -[debug] Copy resource mappings: -[debug] +[debug] Copy resource mappings:  +[debug]   diff --git a/design/project/target/streams/compile/exportedProducts/_global/streams/export b/design/project/target/streams/compile/exportedProducts/_global/streams/export index 43c010d9..0e8df8de 100644 --- a/design/project/target/streams/compile/exportedProducts/_global/streams/export +++ b/design/project/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Downloads/Quasar/design/project/target/scala-2.12/sbt-1.0/classes +/home/waleedbinehsan/Desktop/Quasar/design/project/target/scala-2.12/sbt-1.0/classes diff --git a/design/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/design/project/target/streams/runtime/dependencyClasspath/_global/streams/export index 35f7bf40..34113cc8 100644 --- a/design/project/target/streams/runtime/dependencyClasspath/_global/streams/export +++ b/design/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Downloads/Quasar/design/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes +/home/waleedbinehsan/Desktop/Quasar/design/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes diff --git a/design/project/target/streams/runtime/exportedProducts/_global/streams/export b/design/project/target/streams/runtime/exportedProducts/_global/streams/export index 43c010d9..0e8df8de 100644 --- a/design/project/target/streams/runtime/exportedProducts/_global/streams/export +++ b/design/project/target/streams/runtime/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Downloads/Quasar/design/project/target/scala-2.12/sbt-1.0/classes +/home/waleedbinehsan/Desktop/Quasar/design/project/target/scala-2.12/sbt-1.0/classes diff --git a/design/project/target/streams/runtime/fullClasspath/_global/streams/export b/design/project/target/streams/runtime/fullClasspath/_global/streams/export index 35f7bf40..34113cc8 100644 --- a/design/project/target/streams/runtime/fullClasspath/_global/streams/export +++ b/design/project/target/streams/runtime/fullClasspath/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Downloads/Quasar/design/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes +/home/waleedbinehsan/Desktop/Quasar/design/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes diff --git a/design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export index 43c010d9..0e8df8de 100644 --- a/design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export +++ b/design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export @@ -1 +1 @@ -/home/waleedbinehsan/Downloads/Quasar/design/project/target/scala-2.12/sbt-1.0/classes +/home/waleedbinehsan/Desktop/Quasar/design/project/target/scala-2.12/sbt-1.0/classes diff --git a/design/quasar_wrapper.fir b/design/quasar_wrapper.fir index f737f225..876f1a9c 100644 --- a/design/quasar_wrapper.fir +++ b/design/quasar_wrapper.fir @@ -71689,32 +71689,32 @@ circuit quasar_wrapper : mitcnt1 <= UInt<1>("h00") wire mitcnt0 : UInt<32> mitcnt0 <= UInt<1>("h00") - node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2655:36] - node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2656:36] - io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2658:31] - io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2659:31] - node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2666:72] - node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2666:49] - node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2668:37] - node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2668:56] - node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2668:85] - node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2668:76] - node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2668:53] - node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2668:112] - node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2668:147] - node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2668:138] - node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2668:109] - node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2668:173] - node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2668:171] - node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2669:35] - node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2669:35] - node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2670:44] - node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2670:74] - node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2670:60] - node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2670:29] - node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2671:59] - node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2671:76] - node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2671:93] + node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2649:36] + node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2650:36] + io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2652:31] + io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2653:31] + node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2660:72] + node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2660:49] + node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2662:37] + node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2662:56] + node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2662:85] + node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2662:76] + node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2662:53] + node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2662:112] + node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2662:147] + node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2662:138] + node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2662:109] + node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2662:173] + node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2662:171] + node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2663:35] + node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2663:35] + node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2664:44] + node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2664:74] + node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2664:60] + node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2664:29] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2665:59] + node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2665:76] + node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2665:93] inst rvclkhdr of rvclkhdr_712 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -71723,34 +71723,34 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_18 <= mitcnt0_ns @[lib.scala 374:16] - mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2671:25] - node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2678:72] - node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2678:49] - node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2680:37] - node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2680:56] - node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2680:85] - node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2680:76] - node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2680:53] - node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2680:112] - node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2680:147] - node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2680:138] - node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2680:109] - node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2680:173] - node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2680:171] + mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2665:25] + node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2672:72] + node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2672:49] + node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2674:37] + node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2674:56] + node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2674:85] + node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2674:76] + node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2674:53] + node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2674:112] + node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2674:147] + node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2674:138] + node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2674:109] + node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2674:173] + node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2674:171] node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2683:68] - node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2683:60] - node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2683:72] + node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2677:68] + node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2677:60] + node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2677:72] node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58] - node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2683:35] - node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2683:35] - node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2684:45] - node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2684:75] - node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2684:61] - node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2684:30] - node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2685:60] - node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2685:77] - node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2685:94] + node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2677:35] + node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2677:35] + node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2678:45] + node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2678:75] + node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2678:61] + node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2678:30] + node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2679:60] + node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2679:77] + node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2679:94] inst rvclkhdr_1 of rvclkhdr_713 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -71759,11 +71759,11 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_42 <= mitcnt1_ns @[lib.scala 374:16] - mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2685:25] - node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2692:70] - node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2692:47] - node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2693:38] - node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2693:71] + mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2679:25] + node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2686:70] + node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2686:47] + node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2687:38] + node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2687:71] inst rvclkhdr_2 of rvclkhdr_714 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -71772,12 +71772,12 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mitb0_b <= _T_44 @[lib.scala 374:16] - node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2694:22] - mitb0 <= _T_46 @[dec_tlu_ctl.scala 2694:19] - node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2701:69] - node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2701:47] - node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2702:29] - node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2702:62] + node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2688:22] + mitb0 <= _T_46 @[dec_tlu_ctl.scala 2688:19] + node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2695:69] + node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2695:47] + node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2696:29] + node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2696:62] inst rvclkhdr_3 of rvclkhdr_715 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -71786,55 +71786,55 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mitb1_b <= _T_48 @[lib.scala 374:16] - node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2703:18] - mitb1 <= _T_50 @[dec_tlu_ctl.scala 2703:15] - node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2714:72] - node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2714:49] - node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2715:45] - node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2715:72] - node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2715:86] - node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2715:31] - node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2717:41] - node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2717:30] - reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2718:60] - mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2718:60] - node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2719:78] - reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2719:67] - _T_57 <= _T_56 @[dec_tlu_ctl.scala 2719:67] - node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2719:90] + node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2697:18] + mitb1 <= _T_50 @[dec_tlu_ctl.scala 2697:15] + node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2708:72] + node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2708:49] + node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2709:45] + node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2709:72] + node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2709:86] + node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2709:31] + node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2711:41] + node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2711:30] + reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2712:60] + mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2712:60] + node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2713:78] + reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2713:67] + _T_57 <= _T_56 @[dec_tlu_ctl.scala 2713:67] + node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2713:90] node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58] - mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2719:31] - node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2729:71] - node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2729:49] - node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2730:45] - node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2730:71] - node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2730:85] - node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2730:31] - node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2731:40] - node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2731:29] - reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2732:55] - mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2732:55] - node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2733:63] - reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2733:52] - _T_66 <= _T_65 @[dec_tlu_ctl.scala 2733:52] - node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2733:75] + mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2713:31] + node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2723:71] + node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2723:49] + node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2724:45] + node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2724:71] + node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2724:85] + node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2724:31] + node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2725:40] + node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2725:29] + reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2726:55] + mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2726:55] + node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2727:63] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2727:52] + _T_66 <= _T_65 @[dec_tlu_ctl.scala 2727:52] + node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2727:75] node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58] - mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2733:16] - node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2735:51] - node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2735:68] - node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2735:83] - node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2735:98] - node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2735:115] - io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2735:33] - node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2737:25] - node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2737:44] - node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2738:32] - node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2739:30] - node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2740:30] - node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2741:32] + mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2727:16] + node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2729:51] + node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2729:68] + node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2729:83] + node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2729:98] + node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2729:115] + io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2729:33] + node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2731:25] + node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2731:44] + node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2732:32] + node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2733:30] + node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2734:30] + node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2735:32] node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58] - node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2742:32] + node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2736:32] node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58] node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72] @@ -71850,7 +71850,7 @@ circuit quasar_wrapper : node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72] wire _T_96 : UInt<32> @[Mux.scala 27:72] _T_96 <= _T_95 @[Mux.scala 27:72] - io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2736:33] + io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2730:33] extmodule gated_latch_716 : output Q : Clock @@ -72833,8 +72833,8 @@ circuit quasar_wrapper : perfcnt_halted <= UInt<1>("h00") wire mhpmc3_incr : UInt<64> mhpmc3_incr <= UInt<1>("h00") - wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1376:41] - wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1377:65] + wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1370:41] + wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1371:65] wire wr_meicpct_r : UInt<1> wr_meicpct_r <= UInt<1>("h00") wire force_halt_ctr_f : UInt<32> @@ -72909,48 +72909,48 @@ circuit quasar_wrapper : mpmc <= UInt<1>("h00") wire dicad1 : UInt<32> dicad1 <= UInt<1>("h00") - node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1431:45] - node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1431:43] - node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1431:68] - node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1431:66] - io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1431:23] - node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1432:64] - node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1432:71] - node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1432:42] - node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1435:28] - node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1435:39] - node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1438:5] - node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1438:19] - node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1438:44] - node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1438:68] - node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1438:68] + node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1425:45] + node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1425:43] + node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1425:68] + node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1425:66] + io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1425:23] + node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1426:64] + node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1426:71] + node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1426:42] + node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1429:28] + node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1429:39] + node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1432:5] + node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1432:19] + node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1432:44] + node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1432:68] + node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1432:68] node _T_12 = cat(_T_11, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1439:18] - node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1439:43] - node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1439:76] + node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1433:18] + node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1433:43] + node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1433:76] node _T_16 = cat(_T_15, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1440:17] - node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1440:15] - node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1440:41] - node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1440:70] + node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1434:17] + node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1434:15] + node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1434:41] + node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1434:70] node _T_21 = cat(UInt<1>("h01"), _T_20) @[Cat.scala 29:58] - node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1441:26] - node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1441:50] + node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1435:26] + node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1435:50] node _T_24 = cat(_T_23, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1442:20] - node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1442:18] - node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1442:44] - node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1442:77] - node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1442:101] + node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1436:20] + node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1436:18] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1436:44] + node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1436:77] + node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1436:101] node _T_30 = cat(_T_28, _T_29) @[Cat.scala 29:58] - node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1443:5] - node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1443:21] - node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1443:19] - node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1443:46] - node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1443:44] - node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1443:59] - node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1443:57] - node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1443:81] + node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1437:5] + node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1437:21] + node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1437:19] + node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1437:46] + node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1437:44] + node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1437:59] + node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1437:57] + node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1437:81] node _T_39 = mux(_T_9, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] node _T_40 = mux(_T_14, _T_16, UInt<1>("h00")) @[Mux.scala 27:72] node _T_41 = mux(_T_19, _T_21, UInt<1>("h00")) @[Mux.scala 27:72] @@ -72964,23 +72964,23 @@ circuit quasar_wrapper : node _T_49 = or(_T_48, _T_44) @[Mux.scala 27:72] wire mstatus_ns : UInt<2> @[Mux.scala 27:72] mstatus_ns <= _T_49 @[Mux.scala 27:72] - node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1446:33] - node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1446:33] - node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1446:50] - node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1446:90] - node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1446:81] - node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1446:47] - io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1446:20] - reg _T_56 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1448:11] - _T_56 <= mstatus_ns @[dec_tlu_ctl.scala 1448:11] - io.mstatus <= _T_56 @[dec_tlu_ctl.scala 1447:13] - node _T_57 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1457:62] - node _T_58 = eq(_T_57, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1457:69] - node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_58) @[dec_tlu_ctl.scala 1457:40] - node _T_59 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1458:40] - node _T_60 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1458:68] + node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1440:33] + node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1440:33] + node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1440:50] + node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1440:90] + node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1440:81] + node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1440:47] + io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1440:20] + reg _T_56 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1442:11] + _T_56 <= mstatus_ns @[dec_tlu_ctl.scala 1442:11] + io.mstatus <= _T_56 @[dec_tlu_ctl.scala 1441:13] + node _T_57 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1451:62] + node _T_58 = eq(_T_57, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1451:69] + node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_58) @[dec_tlu_ctl.scala 1451:40] + node _T_59 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1452:40] + node _T_60 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1452:68] node mtvec_ns = cat(_T_59, _T_60) @[Cat.scala 29:58] - node _T_61 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1459:42] + node _T_61 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1453:42] inst rvclkhdr of rvclkhdr_720 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -72989,57 +72989,57 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_62 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_62 <= mtvec_ns @[lib.scala 374:16] - io.mtvec <= _T_62 @[dec_tlu_ctl.scala 1459:11] - node _T_63 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1471:30] - node ce_int = or(_T_63, mice_ce_req) @[dec_tlu_ctl.scala 1471:46] + io.mtvec <= _T_62 @[dec_tlu_ctl.scala 1453:11] + node _T_63 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1465:30] + node ce_int = or(_T_63, mice_ce_req) @[dec_tlu_ctl.scala 1465:46] node _T_64 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58] node _T_65 = cat(_T_64, io.soft_int_sync) @[Cat.scala 29:58] node _T_66 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58] node _T_67 = cat(_T_66, io.dec_timer_t1_pulse) @[Cat.scala 29:58] node mip_ns = cat(_T_67, _T_65) @[Cat.scala 29:58] - reg _T_68 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1475:11] - _T_68 <= mip_ns @[dec_tlu_ctl.scala 1475:11] - io.mip <= _T_68 @[dec_tlu_ctl.scala 1474:9] - node _T_69 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1487:60] - node _T_70 = eq(_T_69, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1487:67] - node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_70) @[dec_tlu_ctl.scala 1487:38] - node _T_71 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1488:28] - node _T_72 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1488:59] - node _T_73 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1488:88] - node _T_74 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1488:113] - node _T_75 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1488:137] + reg _T_68 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1469:11] + _T_68 <= mip_ns @[dec_tlu_ctl.scala 1469:11] + io.mip <= _T_68 @[dec_tlu_ctl.scala 1468:9] + node _T_69 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1481:60] + node _T_70 = eq(_T_69, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1481:67] + node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_70) @[dec_tlu_ctl.scala 1481:38] + node _T_71 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1482:28] + node _T_72 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1482:59] + node _T_73 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1482:88] + node _T_74 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1482:113] + node _T_75 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1482:137] node _T_76 = cat(_T_74, _T_75) @[Cat.scala 29:58] node _T_77 = cat(_T_72, _T_73) @[Cat.scala 29:58] node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58] - node _T_79 = mux(_T_71, _T_78, mie) @[dec_tlu_ctl.scala 1488:18] - io.mie_ns <= _T_79 @[dec_tlu_ctl.scala 1488:12] - reg _T_80 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1490:11] - _T_80 <= io.mie_ns @[dec_tlu_ctl.scala 1490:11] - mie <= _T_80 @[dec_tlu_ctl.scala 1489:6] - node _T_81 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1497:63] - node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_81) @[dec_tlu_ctl.scala 1497:54] - node _T_82 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1499:64] - node _T_83 = eq(_T_82, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1499:71] - node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_83) @[dec_tlu_ctl.scala 1499:42] - node _T_84 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1501:80] - node _T_85 = and(io.dec_tlu_dbg_halted, _T_84) @[dec_tlu_ctl.scala 1501:71] - node _T_86 = or(kill_ebreak_count_r, _T_85) @[dec_tlu_ctl.scala 1501:46] - node _T_87 = or(_T_86, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1501:94] - node _T_88 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1501:136] - node _T_89 = or(_T_87, _T_88) @[dec_tlu_ctl.scala 1501:121] - node mcyclel_cout_in = not(_T_89) @[dec_tlu_ctl.scala 1501:24] + node _T_79 = mux(_T_71, _T_78, mie) @[dec_tlu_ctl.scala 1482:18] + io.mie_ns <= _T_79 @[dec_tlu_ctl.scala 1482:12] + reg _T_80 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1484:11] + _T_80 <= io.mie_ns @[dec_tlu_ctl.scala 1484:11] + mie <= _T_80 @[dec_tlu_ctl.scala 1483:6] + node _T_81 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1491:63] + node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_81) @[dec_tlu_ctl.scala 1491:54] + node _T_82 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1493:64] + node _T_83 = eq(_T_82, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1493:71] + node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_83) @[dec_tlu_ctl.scala 1493:42] + node _T_84 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1495:80] + node _T_85 = and(io.dec_tlu_dbg_halted, _T_84) @[dec_tlu_ctl.scala 1495:71] + node _T_86 = or(kill_ebreak_count_r, _T_85) @[dec_tlu_ctl.scala 1495:46] + node _T_87 = or(_T_86, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1495:94] + node _T_88 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1495:136] + node _T_89 = or(_T_87, _T_88) @[dec_tlu_ctl.scala 1495:121] + node mcyclel_cout_in = not(_T_89) @[dec_tlu_ctl.scala 1495:24] wire mcyclel_inc : UInt<33> mcyclel_inc <= UInt<1>("h00") node _T_90 = cat(UInt<31>("h00"), mcyclel_cout_in) @[Cat.scala 29:58] - node _T_91 = add(mcyclel, _T_90) @[dec_tlu_ctl.scala 1505:25] - mcyclel_inc <= _T_91 @[dec_tlu_ctl.scala 1505:14] - node _T_92 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1506:36] - node _T_93 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1506:76] - node mcyclel_ns = mux(_T_92, io.dec_csr_wrdata_r, _T_93) @[dec_tlu_ctl.scala 1506:22] - node _T_94 = bits(mcyclel_inc, 32, 32) @[dec_tlu_ctl.scala 1507:32] - node mcyclel_cout = bits(_T_94, 0, 0) @[dec_tlu_ctl.scala 1507:37] - node _T_95 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1508:46] - node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 1508:72] + node _T_91 = add(mcyclel, _T_90) @[dec_tlu_ctl.scala 1499:25] + mcyclel_inc <= _T_91 @[dec_tlu_ctl.scala 1499:14] + node _T_92 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1500:36] + node _T_93 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1500:76] + node mcyclel_ns = mux(_T_92, io.dec_csr_wrdata_r, _T_93) @[dec_tlu_ctl.scala 1500:22] + node _T_94 = bits(mcyclel_inc, 32, 32) @[dec_tlu_ctl.scala 1501:32] + node mcyclel_cout = bits(_T_94, 0, 0) @[dec_tlu_ctl.scala 1501:37] + node _T_95 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1502:46] + node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 1502:72] inst rvclkhdr_1 of rvclkhdr_721 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -73048,22 +73048,22 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_97 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_97 <= mcyclel_ns @[lib.scala 374:16] - mcyclel <= _T_97 @[dec_tlu_ctl.scala 1508:10] - node _T_98 = eq(wr_mcycleh_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1509:71] - node _T_99 = and(mcyclel_cout, _T_98) @[dec_tlu_ctl.scala 1509:69] - reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1509:54] - mcyclel_cout_f <= _T_99 @[dec_tlu_ctl.scala 1509:54] - node _T_100 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1515:61] - node _T_101 = eq(_T_100, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1515:68] - node _T_102 = and(io.dec_csr_wen_r_mod, _T_101) @[dec_tlu_ctl.scala 1515:39] - wr_mcycleh_r <= _T_102 @[dec_tlu_ctl.scala 1515:15] + mcyclel <= _T_97 @[dec_tlu_ctl.scala 1502:10] + node _T_98 = eq(wr_mcycleh_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1503:71] + node _T_99 = and(mcyclel_cout, _T_98) @[dec_tlu_ctl.scala 1503:69] + reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1503:54] + mcyclel_cout_f <= _T_99 @[dec_tlu_ctl.scala 1503:54] + node _T_100 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1509:61] + node _T_101 = eq(_T_100, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1509:68] + node _T_102 = and(io.dec_csr_wen_r_mod, _T_101) @[dec_tlu_ctl.scala 1509:39] + wr_mcycleh_r <= _T_102 @[dec_tlu_ctl.scala 1509:15] node _T_103 = cat(UInt<31>("h00"), mcyclel_cout_f) @[Cat.scala 29:58] - node _T_104 = add(mcycleh, _T_103) @[dec_tlu_ctl.scala 1517:28] - node mcycleh_inc = tail(_T_104, 1) @[dec_tlu_ctl.scala 1517:28] - node _T_105 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1518:36] - node mcycleh_ns = mux(_T_105, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1518:22] - node _T_106 = or(wr_mcycleh_r, mcyclel_cout_f) @[dec_tlu_ctl.scala 1520:46] - node _T_107 = bits(_T_106, 0, 0) @[dec_tlu_ctl.scala 1520:64] + node _T_104 = add(mcycleh, _T_103) @[dec_tlu_ctl.scala 1511:28] + node mcycleh_inc = tail(_T_104, 1) @[dec_tlu_ctl.scala 1511:28] + node _T_105 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1512:36] + node mcycleh_ns = mux(_T_105, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1512:22] + node _T_106 = or(wr_mcycleh_r, mcyclel_cout_f) @[dec_tlu_ctl.scala 1514:46] + node _T_107 = bits(_T_106, 0, 0) @[dec_tlu_ctl.scala 1514:64] inst rvclkhdr_2 of rvclkhdr_722 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -73072,28 +73072,28 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_108 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_108 <= mcycleh_ns @[lib.scala 374:16] - mcycleh <= _T_108 @[dec_tlu_ctl.scala 1520:10] - node _T_109 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1534:72] - node _T_110 = or(_T_109, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1534:85] - node _T_111 = or(_T_110, io.illegal_r) @[dec_tlu_ctl.scala 1534:113] - node _T_112 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1534:143] - node _T_113 = or(_T_111, _T_112) @[dec_tlu_ctl.scala 1534:128] - node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 1534:148] - node _T_115 = not(_T_114) @[dec_tlu_ctl.scala 1534:58] - node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_115) @[dec_tlu_ctl.scala 1534:56] - node _T_116 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1536:66] - node _T_117 = eq(_T_116, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1536:73] - node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_117) @[dec_tlu_ctl.scala 1536:44] + mcycleh <= _T_108 @[dec_tlu_ctl.scala 1514:10] + node _T_109 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1528:72] + node _T_110 = or(_T_109, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1528:85] + node _T_111 = or(_T_110, io.illegal_r) @[dec_tlu_ctl.scala 1528:113] + node _T_112 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1528:143] + node _T_113 = or(_T_111, _T_112) @[dec_tlu_ctl.scala 1528:128] + node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 1528:148] + node _T_115 = not(_T_114) @[dec_tlu_ctl.scala 1528:58] + node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_115) @[dec_tlu_ctl.scala 1528:56] + node _T_116 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1530:66] + node _T_117 = eq(_T_116, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1530:73] + node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_117) @[dec_tlu_ctl.scala 1530:44] node _T_118 = cat(UInt<31>("h00"), i0_valid_no_ebreak_ecall_r) @[Cat.scala 29:58] - node _T_119 = add(minstretl, _T_118) @[dec_tlu_ctl.scala 1538:29] - minstretl_inc <= _T_119 @[dec_tlu_ctl.scala 1538:16] - node minstretl_cout = bits(minstretl_inc, 32, 32) @[dec_tlu_ctl.scala 1539:36] - node _T_120 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[dec_tlu_ctl.scala 1540:52] - node minstret_enable = bits(_T_120, 0, 0) @[dec_tlu_ctl.scala 1540:70] - node _T_121 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1542:40] - node _T_122 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1542:83] - node minstretl_ns = mux(_T_121, io.dec_csr_wrdata_r, _T_122) @[dec_tlu_ctl.scala 1542:24] - node _T_123 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1543:51] + node _T_119 = add(minstretl, _T_118) @[dec_tlu_ctl.scala 1532:29] + minstretl_inc <= _T_119 @[dec_tlu_ctl.scala 1532:16] + node minstretl_cout = bits(minstretl_inc, 32, 32) @[dec_tlu_ctl.scala 1533:36] + node _T_120 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[dec_tlu_ctl.scala 1534:52] + node minstret_enable = bits(_T_120, 0, 0) @[dec_tlu_ctl.scala 1534:70] + node _T_121 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1536:40] + node _T_122 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1536:83] + node minstretl_ns = mux(_T_121, io.dec_csr_wrdata_r, _T_122) @[dec_tlu_ctl.scala 1536:24] + node _T_123 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1537:51] inst rvclkhdr_3 of rvclkhdr_723 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -73102,26 +73102,26 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_124 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_124 <= minstretl_ns @[lib.scala 374:16] - minstretl <= _T_124 @[dec_tlu_ctl.scala 1543:12] - reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1544:56] - minstret_enable_f <= minstret_enable @[dec_tlu_ctl.scala 1544:56] - node _T_125 = not(wr_minstreth_r) @[dec_tlu_ctl.scala 1545:75] - node _T_126 = and(minstretl_cout, _T_125) @[dec_tlu_ctl.scala 1545:73] - reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1545:56] - minstretl_cout_f <= _T_126 @[dec_tlu_ctl.scala 1545:56] - node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1553:64] - node _T_128 = eq(_T_127, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1553:71] - node _T_129 = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1553:42] - node _T_130 = bits(_T_129, 0, 0) @[dec_tlu_ctl.scala 1553:87] - wr_minstreth_r <= _T_130 @[dec_tlu_ctl.scala 1553:17] + minstretl <= _T_124 @[dec_tlu_ctl.scala 1537:12] + reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1538:56] + minstret_enable_f <= minstret_enable @[dec_tlu_ctl.scala 1538:56] + node _T_125 = not(wr_minstreth_r) @[dec_tlu_ctl.scala 1539:75] + node _T_126 = and(minstretl_cout, _T_125) @[dec_tlu_ctl.scala 1539:73] + reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1539:56] + minstretl_cout_f <= _T_126 @[dec_tlu_ctl.scala 1539:56] + node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1547:64] + node _T_128 = eq(_T_127, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1547:71] + node _T_129 = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1547:42] + node _T_130 = bits(_T_129, 0, 0) @[dec_tlu_ctl.scala 1547:87] + wr_minstreth_r <= _T_130 @[dec_tlu_ctl.scala 1547:17] node _T_131 = cat(UInt<31>("h00"), minstretl_cout_f) @[Cat.scala 29:58] - node _T_132 = add(minstreth, _T_131) @[dec_tlu_ctl.scala 1556:29] - node _T_133 = tail(_T_132, 1) @[dec_tlu_ctl.scala 1556:29] - minstreth_inc <= _T_133 @[dec_tlu_ctl.scala 1556:16] - node _T_134 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1557:41] - node minstreth_ns = mux(_T_134, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1557:25] - node _T_135 = or(minstret_enable_f, wr_minstreth_r) @[dec_tlu_ctl.scala 1559:55] - node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 1559:73] + node _T_132 = add(minstreth, _T_131) @[dec_tlu_ctl.scala 1550:29] + node _T_133 = tail(_T_132, 1) @[dec_tlu_ctl.scala 1550:29] + minstreth_inc <= _T_133 @[dec_tlu_ctl.scala 1550:16] + node _T_134 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1551:41] + node minstreth_ns = mux(_T_134, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1551:25] + node _T_135 = or(minstret_enable_f, wr_minstreth_r) @[dec_tlu_ctl.scala 1553:55] + node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 1553:73] inst rvclkhdr_4 of rvclkhdr_724 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -73130,11 +73130,11 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_137 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_137 <= minstreth_ns @[lib.scala 374:16] - minstreth <= _T_137 @[dec_tlu_ctl.scala 1559:12] - node _T_138 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1567:65] - node _T_139 = eq(_T_138, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1567:72] - node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_139) @[dec_tlu_ctl.scala 1567:43] - node _T_140 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1569:55] + minstreth <= _T_137 @[dec_tlu_ctl.scala 1553:12] + node _T_138 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1561:65] + node _T_139 = eq(_T_138, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1561:72] + node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_139) @[dec_tlu_ctl.scala 1561:43] + node _T_140 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1563:55] inst rvclkhdr_5 of rvclkhdr_725 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -73143,24 +73143,24 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_141 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_141 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mscratch <= _T_141 @[dec_tlu_ctl.scala 1569:11] - node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1578:22] - node _T_143 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1578:47] - node _T_144 = and(_T_142, _T_143) @[dec_tlu_ctl.scala 1578:45] - node sel_exu_npc_r = and(_T_144, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1578:72] - node _T_145 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1579:24] - node _T_146 = and(_T_145, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1579:47] - node _T_147 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1579:75] - node sel_flush_npc_r = and(_T_146, _T_147) @[dec_tlu_ctl.scala 1579:73] - node _T_148 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1580:23] - node _T_149 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1580:40] - node sel_hold_npc_r = and(_T_148, _T_149) @[dec_tlu_ctl.scala 1580:38] - node _T_150 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1583:26] - node _T_151 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1584:13] - node _T_152 = and(_T_151, io.reset_delayed) @[dec_tlu_ctl.scala 1584:35] - node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 1584:55] - node _T_154 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1585:28] - node _T_155 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1586:27] + mscratch <= _T_141 @[dec_tlu_ctl.scala 1563:11] + node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1572:22] + node _T_143 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1572:47] + node _T_144 = and(_T_142, _T_143) @[dec_tlu_ctl.scala 1572:45] + node sel_exu_npc_r = and(_T_144, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1572:72] + node _T_145 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1573:24] + node _T_146 = and(_T_145, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1573:47] + node _T_147 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1573:75] + node sel_flush_npc_r = and(_T_146, _T_147) @[dec_tlu_ctl.scala 1573:73] + node _T_148 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1574:23] + node _T_149 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1574:40] + node sel_hold_npc_r = and(_T_148, _T_149) @[dec_tlu_ctl.scala 1574:38] + node _T_150 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1577:26] + node _T_151 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1578:13] + node _T_152 = and(_T_151, io.reset_delayed) @[dec_tlu_ctl.scala 1578:35] + node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 1578:55] + node _T_154 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1579:28] + node _T_155 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1580:27] node _T_156 = mux(_T_150, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_157 = mux(_T_153, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72] node _T_158 = mux(_T_154, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73170,10 +73170,10 @@ circuit quasar_wrapper : node _T_162 = or(_T_161, _T_159) @[Mux.scala 27:72] wire _T_163 : UInt<31> @[Mux.scala 27:72] _T_163 <= _T_162 @[Mux.scala 27:72] - io.npc_r <= _T_163 @[dec_tlu_ctl.scala 1582:11] - node _T_164 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1588:48] - node _T_165 = or(_T_164, io.reset_delayed) @[dec_tlu_ctl.scala 1588:66] - node _T_166 = bits(_T_165, 0, 0) @[dec_tlu_ctl.scala 1588:86] + io.npc_r <= _T_163 @[dec_tlu_ctl.scala 1576:11] + node _T_164 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1582:48] + node _T_165 = or(_T_164, io.reset_delayed) @[dec_tlu_ctl.scala 1582:66] + node _T_166 = bits(_T_165, 0, 0) @[dec_tlu_ctl.scala 1582:86] inst rvclkhdr_6 of rvclkhdr_726 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -73182,11 +73182,11 @@ circuit quasar_wrapper : rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_167 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_167 <= io.npc_r @[lib.scala 374:16] - io.npc_r_d1 <= _T_167 @[dec_tlu_ctl.scala 1588:14] - node _T_168 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1591:21] - node _T_169 = and(_T_168, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1591:44] - node pc0_valid_r = bits(_T_169, 0, 0) @[dec_tlu_ctl.scala 1591:69] - node _T_170 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1595:22] + io.npc_r_d1 <= _T_167 @[dec_tlu_ctl.scala 1582:14] + node _T_168 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1585:21] + node _T_169 = and(_T_168, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1585:44] + node pc0_valid_r = bits(_T_169, 0, 0) @[dec_tlu_ctl.scala 1585:69] + node _T_170 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1589:22] node _T_171 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_172 = mux(_T_170, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_173 = or(_T_171, _T_172) @[Mux.scala 27:72] @@ -73200,22 +73200,22 @@ circuit quasar_wrapper : rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_174 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_174 <= pc_r @[lib.scala 374:16] - pc_r_d1 <= _T_174 @[dec_tlu_ctl.scala 1597:10] - node _T_175 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1599:61] - node _T_176 = eq(_T_175, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1599:68] - node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_176) @[dec_tlu_ctl.scala 1599:39] - node _T_177 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1602:27] - node _T_178 = or(_T_177, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1602:48] - node _T_179 = bits(_T_178, 0, 0) @[dec_tlu_ctl.scala 1602:80] - node _T_180 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1603:25] - node _T_181 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1604:15] - node _T_182 = and(wr_mepc_r, _T_181) @[dec_tlu_ctl.scala 1604:13] - node _T_183 = bits(_T_182, 0, 0) @[dec_tlu_ctl.scala 1604:39] - node _T_184 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1604:104] - node _T_185 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1605:3] - node _T_186 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1605:16] - node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 1605:14] - node _T_188 = bits(_T_187, 0, 0) @[dec_tlu_ctl.scala 1605:40] + pc_r_d1 <= _T_174 @[dec_tlu_ctl.scala 1591:10] + node _T_175 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1593:61] + node _T_176 = eq(_T_175, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1593:68] + node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_176) @[dec_tlu_ctl.scala 1593:39] + node _T_177 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1596:27] + node _T_178 = or(_T_177, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1596:48] + node _T_179 = bits(_T_178, 0, 0) @[dec_tlu_ctl.scala 1596:80] + node _T_180 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1597:25] + node _T_181 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1598:15] + node _T_182 = and(wr_mepc_r, _T_181) @[dec_tlu_ctl.scala 1598:13] + node _T_183 = bits(_T_182, 0, 0) @[dec_tlu_ctl.scala 1598:39] + node _T_184 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1598:104] + node _T_185 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1599:3] + node _T_186 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1599:16] + node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 1599:14] + node _T_188 = bits(_T_187, 0, 0) @[dec_tlu_ctl.scala 1599:40] node _T_189 = mux(_T_179, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_190 = mux(_T_180, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_191 = mux(_T_183, _T_184, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73225,42 +73225,42 @@ circuit quasar_wrapper : node _T_195 = or(_T_194, _T_192) @[Mux.scala 27:72] wire mepc_ns : UInt<31> @[Mux.scala 27:72] mepc_ns <= _T_195 @[Mux.scala 27:72] - reg _T_196 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1607:47] - _T_196 <= mepc_ns @[dec_tlu_ctl.scala 1607:47] - io.mepc <= _T_196 @[dec_tlu_ctl.scala 1607:10] - node _T_197 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1614:65] - node _T_198 = eq(_T_197, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1614:72] - node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_198) @[dec_tlu_ctl.scala 1614:43] - node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1615:53] - node mcause_sel_nmi_store = and(_T_199, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1615:67] - node _T_200 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1616:52] - node mcause_sel_nmi_load = and(_T_200, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1616:66] - node _T_201 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1617:51] - node _T_202 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1617:84] - node mcause_sel_nmi_ext = and(_T_201, _T_202) @[dec_tlu_ctl.scala 1617:65] - node _T_203 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1623:53] - node _T_204 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1623:76] - node _T_205 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1623:99] - node _T_206 = not(_T_205) @[dec_tlu_ctl.scala 1623:82] - node _T_207 = and(_T_204, _T_206) @[dec_tlu_ctl.scala 1623:80] + reg _T_196 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1601:47] + _T_196 <= mepc_ns @[dec_tlu_ctl.scala 1601:47] + io.mepc <= _T_196 @[dec_tlu_ctl.scala 1601:10] + node _T_197 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1608:65] + node _T_198 = eq(_T_197, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1608:72] + node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_198) @[dec_tlu_ctl.scala 1608:43] + node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1609:53] + node mcause_sel_nmi_store = and(_T_199, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1609:67] + node _T_200 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1610:52] + node mcause_sel_nmi_load = and(_T_200, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1610:66] + node _T_201 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1611:51] + node _T_202 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1611:84] + node mcause_sel_nmi_ext = and(_T_201, _T_202) @[dec_tlu_ctl.scala 1611:65] + node _T_203 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1617:53] + node _T_204 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1617:76] + node _T_205 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1617:99] + node _T_206 = not(_T_205) @[dec_tlu_ctl.scala 1617:82] + node _T_207 = and(_T_204, _T_206) @[dec_tlu_ctl.scala 1617:80] node mcause_fir_error_type = cat(_T_203, _T_207) @[Cat.scala 29:58] - node _T_208 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1626:52] - node _T_209 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1627:51] - node _T_210 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1628:50] + node _T_208 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1620:52] + node _T_209 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1621:51] + node _T_210 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1622:50] node _T_211 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58] node _T_212 = cat(_T_211, mcause_fir_error_type) @[Cat.scala 29:58] - node _T_213 = not(io.take_nmi) @[dec_tlu_ctl.scala 1629:56] - node _T_214 = and(io.exc_or_int_valid_r, _T_213) @[dec_tlu_ctl.scala 1629:54] - node _T_215 = bits(_T_214, 0, 0) @[dec_tlu_ctl.scala 1629:70] + node _T_213 = not(io.take_nmi) @[dec_tlu_ctl.scala 1623:56] + node _T_214 = and(io.exc_or_int_valid_r, _T_213) @[dec_tlu_ctl.scala 1623:54] + node _T_215 = bits(_T_214, 0, 0) @[dec_tlu_ctl.scala 1623:70] node _T_216 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58] node _T_217 = cat(_T_216, io.exc_cause_r) @[Cat.scala 29:58] - node _T_218 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1630:46] - node _T_219 = and(wr_mcause_r, _T_218) @[dec_tlu_ctl.scala 1630:44] - node _T_220 = bits(_T_219, 0, 0) @[dec_tlu_ctl.scala 1630:70] - node _T_221 = not(wr_mcause_r) @[dec_tlu_ctl.scala 1631:32] - node _T_222 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1631:47] - node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 1631:45] - node _T_224 = bits(_T_223, 0, 0) @[dec_tlu_ctl.scala 1631:71] + node _T_218 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1624:46] + node _T_219 = and(wr_mcause_r, _T_218) @[dec_tlu_ctl.scala 1624:44] + node _T_220 = bits(_T_219, 0, 0) @[dec_tlu_ctl.scala 1624:70] + node _T_221 = not(wr_mcause_r) @[dec_tlu_ctl.scala 1625:32] + node _T_222 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1625:47] + node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 1625:45] + node _T_224 = bits(_T_223, 0, 0) @[dec_tlu_ctl.scala 1625:71] node _T_225 = mux(_T_208, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_226 = mux(_T_209, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_227 = mux(_T_210, _T_212, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73274,19 +73274,19 @@ circuit quasar_wrapper : node _T_235 = or(_T_234, _T_230) @[Mux.scala 27:72] wire mcause_ns : UInt<32> @[Mux.scala 27:72] mcause_ns <= _T_235 @[Mux.scala 27:72] - reg _T_236 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1633:49] - _T_236 <= mcause_ns @[dec_tlu_ctl.scala 1633:49] - mcause <= _T_236 @[dec_tlu_ctl.scala 1633:12] - node _T_237 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1640:64] - node _T_238 = eq(_T_237, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1640:71] - node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_238) @[dec_tlu_ctl.scala 1640:42] - node _T_239 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1642:56] + reg _T_236 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1627:49] + _T_236 <= mcause_ns @[dec_tlu_ctl.scala 1627:49] + mcause <= _T_236 @[dec_tlu_ctl.scala 1627:12] + node _T_237 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1634:64] + node _T_238 = eq(_T_237, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1634:71] + node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_238) @[dec_tlu_ctl.scala 1634:42] + node _T_239 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1636:56] node _T_240 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58] - node ifu_mscause = mux(_T_239, UInt<4>("h09"), _T_240) @[dec_tlu_ctl.scala 1642:24] - node _T_241 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1645:36] - node _T_242 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1646:40] - node _T_243 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1647:32] - node _T_244 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1648:34] + node ifu_mscause = mux(_T_239, UInt<4>("h09"), _T_240) @[dec_tlu_ctl.scala 1636:24] + node _T_241 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1639:36] + node _T_242 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1640:40] + node _T_243 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1641:32] + node _T_244 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1642:34] node _T_245 = mux(_T_241, io.lsu_error_pkt_r.bits.mscause, UInt<1>("h00")) @[Mux.scala 27:72] node _T_246 = mux(_T_242, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_247 = mux(_T_243, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -73296,15 +73296,15 @@ circuit quasar_wrapper : node _T_251 = or(_T_250, _T_248) @[Mux.scala 27:72] wire mscause_type : UInt<4> @[Mux.scala 27:72] mscause_type <= _T_251 @[Mux.scala 27:72] - node _T_252 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1652:48] - node _T_253 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1653:40] - node _T_254 = and(wr_mscause_r, _T_253) @[dec_tlu_ctl.scala 1653:38] - node _T_255 = bits(_T_254, 0, 0) @[dec_tlu_ctl.scala 1653:64] - node _T_256 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1653:103] - node _T_257 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1654:25] - node _T_258 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1654:41] - node _T_259 = and(_T_257, _T_258) @[dec_tlu_ctl.scala 1654:39] - node _T_260 = bits(_T_259, 0, 0) @[dec_tlu_ctl.scala 1654:65] + node _T_252 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1646:48] + node _T_253 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1647:40] + node _T_254 = and(wr_mscause_r, _T_253) @[dec_tlu_ctl.scala 1647:38] + node _T_255 = bits(_T_254, 0, 0) @[dec_tlu_ctl.scala 1647:64] + node _T_256 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1647:103] + node _T_257 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1648:25] + node _T_258 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1648:41] + node _T_259 = and(_T_257, _T_258) @[dec_tlu_ctl.scala 1648:39] + node _T_260 = bits(_T_259, 0, 0) @[dec_tlu_ctl.scala 1648:65] node _T_261 = mux(_T_252, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72] node _T_262 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72] node _T_263 = mux(_T_260, mscause, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73312,60 +73312,60 @@ circuit quasar_wrapper : node _T_265 = or(_T_264, _T_263) @[Mux.scala 27:72] wire mscause_ns : UInt<4> @[Mux.scala 27:72] mscause_ns <= _T_265 @[Mux.scala 27:72] - reg _T_266 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1656:47] - _T_266 <= mscause_ns @[dec_tlu_ctl.scala 1656:47] - mscause <= _T_266 @[dec_tlu_ctl.scala 1656:10] - node _T_267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1663:62] - node _T_268 = eq(_T_267, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1663:69] - node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_268) @[dec_tlu_ctl.scala 1663:40] - node _T_269 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1664:83] - node _T_270 = and(io.inst_acc_r, _T_269) @[dec_tlu_ctl.scala 1664:81] - node _T_271 = or(io.ebreak_r, _T_270) @[dec_tlu_ctl.scala 1664:64] - node _T_272 = or(_T_271, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1664:106] - node _T_273 = and(io.exc_or_int_valid_r, _T_272) @[dec_tlu_ctl.scala 1664:49] - node _T_274 = not(io.take_nmi) @[dec_tlu_ctl.scala 1664:140] - node mtval_capture_pc_r = and(_T_273, _T_274) @[dec_tlu_ctl.scala 1664:138] - node _T_275 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1665:72] - node _T_276 = and(io.exc_or_int_valid_r, _T_275) @[dec_tlu_ctl.scala 1665:55] - node _T_277 = not(io.take_nmi) @[dec_tlu_ctl.scala 1665:98] - node mtval_capture_pc_plus2_r = and(_T_276, _T_277) @[dec_tlu_ctl.scala 1665:96] - node _T_278 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1666:51] - node _T_279 = not(io.take_nmi) @[dec_tlu_ctl.scala 1666:68] - node mtval_capture_inst_r = and(_T_278, _T_279) @[dec_tlu_ctl.scala 1666:66] - node _T_280 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1667:50] - node _T_281 = not(io.take_nmi) @[dec_tlu_ctl.scala 1667:73] - node mtval_capture_lsu_r = and(_T_280, _T_281) @[dec_tlu_ctl.scala 1667:71] - node _T_282 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1668:46] - node _T_283 = and(io.exc_or_int_valid_r, _T_282) @[dec_tlu_ctl.scala 1668:44] - node _T_284 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1668:68] - node _T_285 = and(_T_283, _T_284) @[dec_tlu_ctl.scala 1668:66] - node _T_286 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1668:92] - node _T_287 = and(_T_285, _T_286) @[dec_tlu_ctl.scala 1668:90] - node _T_288 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1668:115] - node mtval_clear_r = and(_T_287, _T_288) @[dec_tlu_ctl.scala 1668:113] - node _T_289 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1672:25] + reg _T_266 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1650:47] + _T_266 <= mscause_ns @[dec_tlu_ctl.scala 1650:47] + mscause <= _T_266 @[dec_tlu_ctl.scala 1650:10] + node _T_267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1657:62] + node _T_268 = eq(_T_267, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1657:69] + node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_268) @[dec_tlu_ctl.scala 1657:40] + node _T_269 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1658:83] + node _T_270 = and(io.inst_acc_r, _T_269) @[dec_tlu_ctl.scala 1658:81] + node _T_271 = or(io.ebreak_r, _T_270) @[dec_tlu_ctl.scala 1658:64] + node _T_272 = or(_T_271, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1658:106] + node _T_273 = and(io.exc_or_int_valid_r, _T_272) @[dec_tlu_ctl.scala 1658:49] + node _T_274 = not(io.take_nmi) @[dec_tlu_ctl.scala 1658:140] + node mtval_capture_pc_r = and(_T_273, _T_274) @[dec_tlu_ctl.scala 1658:138] + node _T_275 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1659:72] + node _T_276 = and(io.exc_or_int_valid_r, _T_275) @[dec_tlu_ctl.scala 1659:55] + node _T_277 = not(io.take_nmi) @[dec_tlu_ctl.scala 1659:98] + node mtval_capture_pc_plus2_r = and(_T_276, _T_277) @[dec_tlu_ctl.scala 1659:96] + node _T_278 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1660:51] + node _T_279 = not(io.take_nmi) @[dec_tlu_ctl.scala 1660:68] + node mtval_capture_inst_r = and(_T_278, _T_279) @[dec_tlu_ctl.scala 1660:66] + node _T_280 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1661:50] + node _T_281 = not(io.take_nmi) @[dec_tlu_ctl.scala 1661:73] + node mtval_capture_lsu_r = and(_T_280, _T_281) @[dec_tlu_ctl.scala 1661:71] + node _T_282 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1662:46] + node _T_283 = and(io.exc_or_int_valid_r, _T_282) @[dec_tlu_ctl.scala 1662:44] + node _T_284 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1662:68] + node _T_285 = and(_T_283, _T_284) @[dec_tlu_ctl.scala 1662:66] + node _T_286 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1662:92] + node _T_287 = and(_T_285, _T_286) @[dec_tlu_ctl.scala 1662:90] + node _T_288 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1662:115] + node mtval_clear_r = and(_T_287, _T_288) @[dec_tlu_ctl.scala 1662:113] + node _T_289 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1666:25] node _T_290 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_291 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1673:31] - node _T_292 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1673:83] - node _T_293 = tail(_T_292, 1) @[dec_tlu_ctl.scala 1673:83] + node _T_291 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1667:31] + node _T_292 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1667:83] + node _T_293 = tail(_T_292, 1) @[dec_tlu_ctl.scala 1667:83] node _T_294 = cat(_T_293, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_295 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1674:27] - node _T_296 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1675:26] - node _T_297 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1676:18] - node _T_298 = and(wr_mtval_r, _T_297) @[dec_tlu_ctl.scala 1676:16] - node _T_299 = bits(_T_298, 0, 0) @[dec_tlu_ctl.scala 1676:48] - node _T_300 = not(io.take_nmi) @[dec_tlu_ctl.scala 1677:5] - node _T_301 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1677:20] - node _T_302 = and(_T_300, _T_301) @[dec_tlu_ctl.scala 1677:18] - node _T_303 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1677:34] - node _T_304 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 1677:32] - node _T_305 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1677:56] - node _T_306 = and(_T_304, _T_305) @[dec_tlu_ctl.scala 1677:54] - node _T_307 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1677:80] - node _T_308 = and(_T_306, _T_307) @[dec_tlu_ctl.scala 1677:78] - node _T_309 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1677:97] - node _T_310 = and(_T_308, _T_309) @[dec_tlu_ctl.scala 1677:95] - node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 1677:119] + node _T_295 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1668:27] + node _T_296 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1669:26] + node _T_297 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1670:18] + node _T_298 = and(wr_mtval_r, _T_297) @[dec_tlu_ctl.scala 1670:16] + node _T_299 = bits(_T_298, 0, 0) @[dec_tlu_ctl.scala 1670:48] + node _T_300 = not(io.take_nmi) @[dec_tlu_ctl.scala 1671:5] + node _T_301 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1671:20] + node _T_302 = and(_T_300, _T_301) @[dec_tlu_ctl.scala 1671:18] + node _T_303 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1671:34] + node _T_304 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 1671:32] + node _T_305 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1671:56] + node _T_306 = and(_T_304, _T_305) @[dec_tlu_ctl.scala 1671:54] + node _T_307 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1671:80] + node _T_308 = and(_T_306, _T_307) @[dec_tlu_ctl.scala 1671:78] + node _T_309 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1671:97] + node _T_310 = and(_T_308, _T_309) @[dec_tlu_ctl.scala 1671:95] + node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 1671:119] node _T_312 = mux(_T_289, _T_290, UInt<1>("h00")) @[Mux.scala 27:72] node _T_313 = mux(_T_291, _T_294, UInt<1>("h00")) @[Mux.scala 27:72] node _T_314 = mux(_T_295, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73379,14 +73379,14 @@ circuit quasar_wrapper : node _T_322 = or(_T_321, _T_317) @[Mux.scala 27:72] wire mtval_ns : UInt<32> @[Mux.scala 27:72] mtval_ns <= _T_322 @[Mux.scala 27:72] - reg _T_323 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1679:46] - _T_323 <= mtval_ns @[dec_tlu_ctl.scala 1679:46] - mtval <= _T_323 @[dec_tlu_ctl.scala 1679:8] - node _T_324 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1694:61] - node _T_325 = eq(_T_324, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1694:68] - node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_325) @[dec_tlu_ctl.scala 1694:39] - node _T_326 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1696:39] - node _T_327 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1696:55] + reg _T_323 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1673:46] + _T_323 <= mtval_ns @[dec_tlu_ctl.scala 1673:46] + mtval <= _T_323 @[dec_tlu_ctl.scala 1673:8] + node _T_324 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1688:61] + node _T_325 = eq(_T_324, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1688:68] + node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_325) @[dec_tlu_ctl.scala 1688:39] + node _T_326 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1690:39] + node _T_327 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1690:55] inst rvclkhdr_8 of rvclkhdr_728 @[lib.scala 368:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -73395,26 +73395,26 @@ circuit quasar_wrapper : rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mcgc <= _T_326 @[lib.scala 374:16] - node _T_328 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1698:38] - io.dec_tlu_misc_clk_override <= _T_328 @[dec_tlu_ctl.scala 1698:31] - node _T_329 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1699:38] - io.dec_tlu_dec_clk_override <= _T_329 @[dec_tlu_ctl.scala 1699:31] - node _T_330 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1700:38] - io.dec_tlu_ifu_clk_override <= _T_330 @[dec_tlu_ctl.scala 1700:31] - node _T_331 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1701:38] - io.dec_tlu_lsu_clk_override <= _T_331 @[dec_tlu_ctl.scala 1701:31] - node _T_332 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1702:38] - io.dec_tlu_bus_clk_override <= _T_332 @[dec_tlu_ctl.scala 1702:31] - node _T_333 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1703:38] - io.dec_tlu_pic_clk_override <= _T_333 @[dec_tlu_ctl.scala 1703:31] - node _T_334 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1704:38] - io.dec_tlu_dccm_clk_override <= _T_334 @[dec_tlu_ctl.scala 1704:31] - node _T_335 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1705:38] - io.dec_tlu_icm_clk_override <= _T_335 @[dec_tlu_ctl.scala 1705:31] - node _T_336 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1724:61] - node _T_337 = eq(_T_336, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1724:68] - node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_337) @[dec_tlu_ctl.scala 1724:39] - node _T_338 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1728:39] + node _T_328 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1692:38] + io.dec_tlu_misc_clk_override <= _T_328 @[dec_tlu_ctl.scala 1692:31] + node _T_329 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1693:38] + io.dec_tlu_dec_clk_override <= _T_329 @[dec_tlu_ctl.scala 1693:31] + node _T_330 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1694:38] + io.dec_tlu_ifu_clk_override <= _T_330 @[dec_tlu_ctl.scala 1694:31] + node _T_331 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1695:38] + io.dec_tlu_lsu_clk_override <= _T_331 @[dec_tlu_ctl.scala 1695:31] + node _T_332 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1696:38] + io.dec_tlu_bus_clk_override <= _T_332 @[dec_tlu_ctl.scala 1696:31] + node _T_333 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1697:38] + io.dec_tlu_pic_clk_override <= _T_333 @[dec_tlu_ctl.scala 1697:31] + node _T_334 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1698:38] + io.dec_tlu_dccm_clk_override <= _T_334 @[dec_tlu_ctl.scala 1698:31] + node _T_335 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1699:38] + io.dec_tlu_icm_clk_override <= _T_335 @[dec_tlu_ctl.scala 1699:31] + node _T_336 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1718:61] + node _T_337 = eq(_T_336, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1718:68] + node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_337) @[dec_tlu_ctl.scala 1718:39] + node _T_338 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1722:39] inst rvclkhdr_9 of rvclkhdr_729 @[lib.scala 368:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -73423,123 +73423,123 @@ circuit quasar_wrapper : rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_339 <= mfdc_ns @[lib.scala 374:16] - mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1728:11] - node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1737:39] - node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1737:19] - node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1737:66] + mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1722:11] + node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1731:39] + node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1731:19] + node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1731:66] node _T_343 = cat(_T_341, _T_342) @[Cat.scala 29:58] - mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1737:12] - node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1738:28] - node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1738:19] - node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1738:54] + mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1731:12] + node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1732:28] + node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1732:19] + node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1732:54] node _T_347 = cat(_T_345, UInt<4>("h00")) @[Cat.scala 29:58] node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58] - mfdc <= _T_348 @[dec_tlu_ctl.scala 1738:12] - node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1742:46] - io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1742:39] - node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1743:46] - io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1743:39] - node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1744:46] - io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1744:39] - node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1745:46] - io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1745:39] - node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1746:46] - io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1746:39] - node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1747:46] - io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1747:39] - node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1748:46] - io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1748:39] - node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1757:70] - node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1757:77] - node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1757:48] - node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1757:89] - node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1757:87] - node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1757:113] - node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1757:111] - io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1757:24] - node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1764:61] - node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1764:68] - node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1764:39] - node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:39] - node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1767:64] - node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1767:91] - node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1767:71] - node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1767:69] - node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:41] - node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1768:66] - node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1768:93] - node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1768:73] - node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1768:71] - node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:41] - node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1769:66] - node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1769:93] - node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1769:73] - node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1769:71] - node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:41] - node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1770:66] - node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1770:93] - node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1770:73] - node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1770:71] - node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:41] - node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1771:66] - node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1771:93] - node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1771:73] - node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1771:71] - node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:41] - node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1772:66] - node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1772:93] - node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1772:73] - node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1772:71] - node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:41] - node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1773:66] - node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1773:93] - node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1773:73] - node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1773:71] - node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:41] - node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1774:66] - node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1774:93] - node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1774:73] - node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1774:71] - node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:41] - node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1775:66] - node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1775:93] - node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1775:73] - node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1775:71] - node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:41] - node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1776:66] - node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1776:93] - node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1776:73] - node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1776:71] - node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:41] - node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1777:66] - node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1777:93] - node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1777:73] - node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1777:71] - node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:41] - node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1778:66] - node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1778:93] - node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1778:73] - node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1778:70] - node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:41] - node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1779:66] - node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1779:93] - node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1779:73] - node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1779:70] - node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:41] - node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1780:66] - node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1780:93] - node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1780:73] - node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1780:70] - node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:41] - node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1781:66] - node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1781:93] - node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1781:73] - node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1781:70] - node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:41] - node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1782:66] - node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1782:93] - node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1782:73] - node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1782:70] + mfdc <= _T_348 @[dec_tlu_ctl.scala 1732:12] + node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1736:46] + io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1736:39] + node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1737:46] + io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1737:39] + node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1738:46] + io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1738:39] + node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1739:46] + io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1739:39] + node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1740:46] + io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1740:39] + node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1741:46] + io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1741:39] + node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1742:46] + io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1742:39] + node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1751:70] + node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1751:77] + node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1751:48] + node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1751:89] + node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1751:87] + node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1751:113] + node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1751:111] + io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1751:24] + node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1758:61] + node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1758:68] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1758:39] + node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1761:39] + node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1761:64] + node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1761:91] + node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1761:71] + node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1761:69] + node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1762:41] + node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1762:66] + node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1762:93] + node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1762:73] + node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1762:71] + node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1763:41] + node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1763:66] + node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1763:93] + node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1763:73] + node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1763:71] + node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1764:41] + node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1764:66] + node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1764:93] + node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1764:73] + node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1764:71] + node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1765:41] + node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1765:66] + node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1765:93] + node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1765:73] + node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1765:71] + node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1766:41] + node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1766:66] + node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1766:93] + node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1766:73] + node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1766:71] + node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1767:41] + node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1767:66] + node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1767:93] + node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1767:73] + node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1767:71] + node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1768:41] + node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1768:66] + node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1768:93] + node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1768:73] + node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1768:71] + node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1769:41] + node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1769:66] + node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1769:93] + node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1769:73] + node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1769:71] + node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1770:41] + node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1770:66] + node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1770:93] + node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1770:73] + node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1770:71] + node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1771:41] + node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1771:66] + node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1771:93] + node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1771:73] + node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1771:71] + node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1772:41] + node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1772:66] + node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1772:93] + node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1772:73] + node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1772:70] + node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1773:41] + node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1773:66] + node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1773:93] + node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1773:73] + node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1773:70] + node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1774:41] + node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1774:66] + node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1774:93] + node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1774:73] + node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1774:70] + node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1775:41] + node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1775:66] + node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1775:93] + node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1775:73] + node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1775:70] + node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1776:41] + node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1776:66] + node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1776:93] + node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1776:73] + node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1776:70] node _T_445 = cat(_T_440, _T_444) @[Cat.scala 29:58] node _T_446 = cat(_T_435, _T_439) @[Cat.scala 29:58] node _T_447 = cat(_T_446, _T_445) @[Cat.scala 29:58] @@ -73571,7 +73571,7 @@ circuit quasar_wrapper : node _T_473 = cat(_T_472, _T_469) @[Cat.scala 29:58] node _T_474 = cat(_T_473, _T_466) @[Cat.scala 29:58] node mrac_in = cat(_T_474, _T_459) @[Cat.scala 29:58] - node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1785:38] + node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1779:38] inst rvclkhdr_10 of rvclkhdr_730 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset @@ -73580,21 +73580,21 @@ circuit quasar_wrapper : rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mrac <= mrac_in @[lib.scala 374:16] - io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1787:21] - node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1795:62] - node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1795:69] - node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1795:40] - node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1805:59] - node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1805:57] - node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1805:35] - io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1805:22] - node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1807:49] - node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1807:86] - node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1807:84] - node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1807:111] - node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1807:109] - mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1807:12] - node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1809:64] + io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1781:21] + node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1789:62] + node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1789:69] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1789:40] + node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1799:59] + node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1799:57] + node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1799:35] + io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1799:22] + node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1801:49] + node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1801:86] + node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1801:84] + node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1801:111] + node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1801:109] + mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1801:12] + node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1803:64] inst rvclkhdr_11 of rvclkhdr_731 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset @@ -73603,54 +73603,54 @@ circuit quasar_wrapper : rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mdseac <= io.lsu_imprecise_error_addr_any @[lib.scala 374:16] - node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1818:61] - node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1818:68] - node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1818:39] - node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1822:51] - node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1822:30] - node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1822:57] - node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1822:55] - node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1822:89] - node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1822:87] - io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1822:17] + node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1812:61] + node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1812:68] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1812:39] + node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1816:51] + node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1816:30] + node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1816:57] + node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1816:55] + node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1816:89] + node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1816:87] + io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1816:17] wire fw_halted_ns : UInt<1> fw_halted_ns <= UInt<1>("h00") - reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1824:48] - fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1824:48] - node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1825:34] - node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1825:49] - node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1825:47] - fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1825:15] - node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1826:29] - node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1826:57] - node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1826:37] - node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1826:62] - node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1826:18] - mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1826:12] - reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1828:44] - _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1828:44] - mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1828:9] - node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1831:10] - mpmc <= _T_504 @[dec_tlu_ctl.scala 1831:7] - node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:40] - node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1840:48] - node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1840:92] - node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1840:19] - node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1842:63] - node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1842:70] - node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1842:41] + reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1818:48] + fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1818:48] + node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1819:34] + node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1819:49] + node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1819:47] + fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1819:15] + node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1820:29] + node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1820:57] + node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1820:37] + node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1820:62] + node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1820:18] + mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1820:12] + reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1822:44] + _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1822:44] + mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1822:9] + node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1825:10] + mpmc <= _T_504 @[dec_tlu_ctl.scala 1825:7] + node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1834:40] + node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1834:48] + node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1834:92] + node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1834:19] + node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1836:63] + node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1836:70] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1836:41] node _T_510 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] - node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1843:23] - node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1843:23] - micect_inc <= _T_512 @[dec_tlu_ctl.scala 1843:13] - node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1844:35] - node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1844:75] + node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1837:23] + node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1837:23] + micect_inc <= _T_512 @[dec_tlu_ctl.scala 1837:13] + node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1838:35] + node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1838:75] node _T_515 = cat(csr_sat, _T_514) @[Cat.scala 29:58] - node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1844:95] + node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1838:95] node _T_517 = cat(_T_516, micect_inc) @[Cat.scala 29:58] - node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1844:22] - node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1846:42] - node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1846:61] + node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1838:22] + node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1840:42] + node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1840:61] inst rvclkhdr_12 of rvclkhdr_732 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset @@ -73659,32 +73659,32 @@ circuit quasar_wrapper : rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_520 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_520 <= micect_ns @[lib.scala 374:16] - micect <= _T_520 @[dec_tlu_ctl.scala 1846:9] - node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1848:48] - node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1848:39] - node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1848:79] + micect <= _T_520 @[dec_tlu_ctl.scala 1840:9] + node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1842:48] + node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1842:39] + node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1842:79] node _T_524 = cat(UInt<5>("h00"), _T_523) @[Cat.scala 29:58] - node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1848:57] - node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1848:88] - mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1848:14] - node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1857:69] - node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1857:76] - node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1857:47] - node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1858:26] - node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1858:70] + node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1842:57] + node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1842:88] + mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1842:14] + node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1851:69] + node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1851:76] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1851:47] + node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1852:26] + node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1852:70] node _T_531 = cat(UInt<26>("h00"), _T_530) @[Cat.scala 29:58] - node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1858:33] - node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1858:33] - miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1858:15] - node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1859:45] - node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1859:85] + node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1852:33] + node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1852:33] + miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1852:15] + node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1853:45] + node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1853:85] node _T_536 = cat(csr_sat, _T_535) @[Cat.scala 29:58] - node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1859:107] + node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1853:107] node _T_538 = cat(_T_537, miccmect_inc) @[Cat.scala 29:58] - node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1859:30] - node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1861:48] - node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1861:69] - node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1861:93] + node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1853:30] + node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1855:48] + node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1855:69] + node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1855:93] inst rvclkhdr_13 of rvclkhdr_733 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset @@ -73693,30 +73693,30 @@ circuit quasar_wrapper : rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_542 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_542 <= miccmect_ns @[lib.scala 374:16] - miccmect <= _T_542 @[dec_tlu_ctl.scala 1861:11] - node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1863:51] - node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1863:40] - node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1863:84] + miccmect <= _T_542 @[dec_tlu_ctl.scala 1855:11] + node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1857:51] + node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1857:40] + node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1857:84] node _T_546 = cat(UInt<5>("h00"), _T_545) @[Cat.scala 29:58] - node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1863:60] - node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1863:93] - miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1863:15] - node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1872:69] - node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1872:76] - node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1872:47] - node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1873:26] + node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1857:60] + node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1857:93] + miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1857:15] + node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1866:69] + node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1866:76] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1866:47] + node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1867:26] node _T_552 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] - node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1873:33] - node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1873:33] - mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1873:15] - node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1874:45] - node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1874:85] + node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1867:33] + node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1867:33] + mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1867:15] + node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1868:45] + node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1868:85] node _T_557 = cat(csr_sat, _T_556) @[Cat.scala 29:58] - node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1874:107] + node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1868:107] node _T_559 = cat(_T_558, mdccmect_inc) @[Cat.scala 29:58] - node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1874:30] - node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1876:49] - node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1876:81] + node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1868:30] + node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1870:49] + node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1870:81] inst rvclkhdr_14 of rvclkhdr_734 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset @@ -73725,67 +73725,67 @@ circuit quasar_wrapper : rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_562 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_562 <= mdccmect_ns @[lib.scala 374:16] - mdccmect <= _T_562 @[dec_tlu_ctl.scala 1876:11] - node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1878:52] - node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1878:41] - node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1878:85] + mdccmect <= _T_562 @[dec_tlu_ctl.scala 1870:11] + node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1872:52] + node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1872:41] + node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1872:85] node _T_566 = cat(UInt<5>("h00"), _T_565) @[Cat.scala 29:58] - node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1878:61] - node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1878:94] - mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1878:16] - node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1888:62] - node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1888:69] - node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1888:40] - node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1890:32] - node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1890:59] - node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1890:20] - reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1892:43] - _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1892:43] - mfdht <= _T_573 @[dec_tlu_ctl.scala 1892:8] - node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1901:62] - node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1901:69] - node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1901:40] - node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1903:32] - node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1903:60] - node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1904:43] - node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1904:41] - node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1904:65] - node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1904:78] - node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1904:98] + node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1872:61] + node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1872:94] + mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1872:16] + node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1882:62] + node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1882:69] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1882:40] + node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1884:32] + node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1884:59] + node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1884:20] + reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1886:43] + _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1886:43] + mfdht <= _T_573 @[dec_tlu_ctl.scala 1886:8] + node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1895:62] + node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1895:69] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1895:40] + node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1897:32] + node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1897:60] + node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1898:43] + node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1898:41] + node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1898:65] + node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1898:78] + node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1898:98] node _T_583 = cat(_T_581, _T_582) @[Cat.scala 29:58] - node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1904:21] - node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1903:20] - node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1906:71] - node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1906:92] + node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1898:21] + node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1897:20] + node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1900:71] + node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1900:92] reg _T_587 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_586 : @[Reg.scala 28:19] _T_587 <= mfdhs_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mfdhs <= _T_587 @[dec_tlu_ctl.scala 1906:8] - node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1908:47] - node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1908:74] - node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1908:74] - node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1909:48] - node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1909:27] - node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1908:26] - node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1911:81] + mfdhs <= _T_587 @[dec_tlu_ctl.scala 1900:8] + node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1902:47] + node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1902:74] + node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1902:74] + node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1903:48] + node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1903:27] + node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1902:26] + node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1905:81] reg _T_594 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_593 : @[Reg.scala 28:19] _T_594 <= force_halt_ctr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1911:19] - node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1913:24] - node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1913:79] - node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1913:71] - node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1913:48] - node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1913:87] - node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1913:28] - io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1913:16] - node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62] - node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1921:69] - node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1921:40] - node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1923:40] - node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1923:59] + force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1905:19] + node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1907:24] + node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1907:79] + node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1907:71] + node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1907:48] + node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1907:87] + node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1907:28] + io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1907:16] + node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1915:62] + node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1915:69] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1915:40] + node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1917:40] + node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1917:59] inst rvclkhdr_15 of rvclkhdr_735 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset @@ -73794,7 +73794,7 @@ circuit quasar_wrapper : rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] meivt <= _T_603 @[lib.scala 374:16] - node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1935:49] + node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1929:49] inst rvclkhdr_16 of rvclkhdr_736 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset @@ -73804,62 +73804,62 @@ circuit quasar_wrapper : reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] meihap <= io.pic_claimid @[lib.scala 374:16] node _T_606 = cat(meivt, meihap) @[Cat.scala 29:58] - io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1936:20] - node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1945:65] - node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1945:72] - node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1945:43] - node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1946:38] - node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1946:65] - node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1946:23] - reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1948:46] - _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1948:46] - meicurpl <= _T_611 @[dec_tlu_ctl.scala 1948:11] - io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1950:22] - node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1960:66] - node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1960:73] - node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1960:44] - node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1960:88] - node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1962:37] - node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1963:38] - node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1963:65] - node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1963:23] - node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1962:23] - reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1965:44] - _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1965:44] - meicidpl <= _T_619 @[dec_tlu_ctl.scala 1965:11] - node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1972:62] - node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1972:69] - node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1972:40] - node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1972:83] - wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1972:15] - node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1981:62] - node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 1981:69] - node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 1981:40] - node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 1982:32] - node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1982:59] - node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 1982:20] - reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1984:43] - _T_628 <= meipt_ns @[dec_tlu_ctl.scala 1984:43] - meipt <= _T_628 @[dec_tlu_ctl.scala 1984:8] - io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 1986:19] - node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2012:89] - node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2012:66] - node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2015:31] - node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2015:29] - node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2015:63] - node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2015:61] - node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2015:98] - node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2015:96] - node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2015:118] - node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2016:48] - node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2016:46] - node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2016:80] - node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2016:78] - node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2016:114] - node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2017:77] - node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2017:75] - node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2017:111] - node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2018:108] + io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1930:20] + node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1939:65] + node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1939:72] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1939:43] + node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1940:38] + node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1940:65] + node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1940:23] + reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1942:46] + _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1942:46] + meicurpl <= _T_611 @[dec_tlu_ctl.scala 1942:11] + io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1944:22] + node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1954:66] + node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1954:73] + node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1954:44] + node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1954:88] + node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1956:37] + node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1957:38] + node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1957:65] + node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1957:23] + node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1956:23] + reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1959:44] + _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1959:44] + meicidpl <= _T_619 @[dec_tlu_ctl.scala 1959:11] + node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1966:62] + node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1966:69] + node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1966:40] + node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1966:83] + wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1966:15] + node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1975:62] + node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 1975:69] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 1975:40] + node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 1976:32] + node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1976:59] + node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 1976:20] + reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1978:43] + _T_628 <= meipt_ns @[dec_tlu_ctl.scala 1978:43] + meipt <= _T_628 @[dec_tlu_ctl.scala 1978:8] + io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 1980:19] + node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2006:89] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2006:66] + node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2009:31] + node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2009:29] + node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2009:63] + node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2009:61] + node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2009:98] + node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2009:96] + node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2009:118] + node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2010:48] + node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2010:46] + node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2010:80] + node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2010:78] + node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2010:114] + node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2011:77] + node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2011:75] + node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2011:111] + node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2012:108] node _T_646 = mux(_T_636, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_647 = mux(_T_641, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_648 = mux(_T_644, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -73869,30 +73869,30 @@ circuit quasar_wrapper : node _T_652 = or(_T_651, _T_649) @[Mux.scala 27:72] wire dcsr_cause : UInt<3> @[Mux.scala 27:72] dcsr_cause <= _T_652 @[Mux.scala 27:72] - node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2020:46] - node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2020:91] - node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2020:98] - node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2020:69] - node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2026:69] - node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2026:75] - node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2026:59] - node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2027:59] - node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2027:78] - node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2027:56] - node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2029:48] - node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2030:44] - node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2030:64] - node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2030:91] + node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2014:46] + node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2014:91] + node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2014:98] + node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2014:69] + node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2020:69] + node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2020:75] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2020:59] + node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2021:59] + node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2021:78] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2021:56] + node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2023:48] + node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2024:44] + node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2024:64] + node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2024:91] node _T_663 = cat(_T_662, UInt<2>("h03")) @[Cat.scala 29:58] node _T_664 = cat(_T_661, dcsr_cause) @[Cat.scala 29:58] node _T_665 = cat(_T_664, _T_663) @[Cat.scala 29:58] - node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2031:18] - node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2031:49] - node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2031:84] - node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2031:110] - node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2031:154] - node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2031:145] - node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2031:178] + node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2025:18] + node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2025:49] + node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2025:84] + node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2025:110] + node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2025:154] + node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2025:145] + node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2025:178] node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58] node _T_674 = cat(UInt<2>("h00"), _T_671) @[Cat.scala 29:58] node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58] @@ -73901,17 +73901,17 @@ circuit quasar_wrapper : node _T_678 = cat(_T_677, _T_668) @[Cat.scala 29:58] node _T_679 = cat(_T_678, _T_676) @[Cat.scala 29:58] node _T_680 = cat(_T_679, _T_675) @[Cat.scala 29:58] - node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2031:211] - node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2031:245] + node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2025:211] + node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2025:245] node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58] node _T_684 = cat(_T_681, nmi_in_debug_mode) @[Cat.scala 29:58] node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58] - node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2031:7] - node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2030:19] - node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2033:54] - node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2033:66] - node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2033:94] - node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2033:109] + node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2025:7] + node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2024:19] + node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2027:54] + node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2027:66] + node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2027:94] + node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2027:109] inst rvclkhdr_17 of rvclkhdr_737 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset @@ -73920,25 +73920,25 @@ circuit quasar_wrapper : rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_691 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_691 <= dcsr_ns @[lib.scala 374:16] - io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2033:10] - node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2041:45] - node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2041:90] - node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2041:97] - node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2041:68] - node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2042:44] - node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2042:42] - node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2042:67] - node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2042:65] - node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2046:21] - node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2046:39] - node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2046:37] - node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2046:56] - node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2046:68] - node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2046:97] - node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2047:68] - node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2048:33] - node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2048:49] - node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2048:68] + io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2027:10] + node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2035:45] + node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2035:90] + node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2035:97] + node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2035:68] + node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2036:44] + node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2036:42] + node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2036:67] + node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2036:65] + node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2040:21] + node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2040:39] + node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2040:37] + node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2040:56] + node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2040:68] + node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2040:97] + node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2041:68] + node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2042:33] + node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2042:49] + node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2042:68] node _T_708 = mux(_T_702, _T_703, UInt<1>("h00")) @[Mux.scala 27:72] node _T_709 = mux(_T_704, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_710 = mux(_T_707, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73946,9 +73946,9 @@ circuit quasar_wrapper : node _T_712 = or(_T_711, _T_710) @[Mux.scala 27:72] wire dpc_ns : UInt<31> @[Mux.scala 27:72] dpc_ns <= _T_712 @[Mux.scala 27:72] - node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2050:36] - node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2050:53] - node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2050:72] + node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2044:36] + node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2044:53] + node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2044:72] inst rvclkhdr_18 of rvclkhdr_738 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset @@ -73957,17 +73957,17 @@ circuit quasar_wrapper : rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_716 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_716 <= dpc_ns @[lib.scala 374:16] - io.dpc <= _T_716 @[dec_tlu_ctl.scala 2050:9] - node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2064:43] - node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2064:68] - node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2064:96] + io.dpc <= _T_716 @[dec_tlu_ctl.scala 2044:9] + node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2058:43] + node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2058:68] + node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2058:96] node _T_720 = cat(_T_717, _T_718) @[Cat.scala 29:58] node dicawics_ns = cat(_T_720, _T_719) @[Cat.scala 29:58] - node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2065:50] - node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2065:95] - node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2065:102] - node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2065:73] - node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2067:50] + node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2059:50] + node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2059:95] + node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2059:102] + node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2059:73] + node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2061:50] inst rvclkhdr_19 of rvclkhdr_739 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset @@ -73976,14 +73976,14 @@ circuit quasar_wrapper : rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicawics <= dicawics_ns @[lib.scala 374:16] - node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2083:48] - node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2083:93] - node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2083:100] - node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2083:71] - node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2084:34] - node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2084:21] - node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2086:46] - node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2086:79] + node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2077:48] + node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2077:93] + node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2077:100] + node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2077:71] + node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2078:34] + node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2078:21] + node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2080:46] + node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2080:79] inst rvclkhdr_20 of rvclkhdr_740 @[lib.scala 368:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset @@ -73992,15 +73992,15 @@ circuit quasar_wrapper : rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0 <= dicad0_ns @[lib.scala 374:16] - node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2096:49] - node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2096:94] - node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2096:101] - node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2096:72] - node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2098:36] - node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2098:88] - node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2098:22] - node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2100:48] - node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2100:81] + node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2090:49] + node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2090:94] + node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2090:101] + node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2090:72] + node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2092:36] + node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2092:88] + node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2092:22] + node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2094:48] + node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2094:81] inst rvclkhdr_21 of rvclkhdr_741 @[lib.scala 368:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset @@ -74011,73 +74011,73 @@ circuit quasar_wrapper : dicad0h <= dicad0h_ns @[lib.scala 374:16] wire _T_738 : UInt<7> _T_738 <= UInt<1>("h00") - node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2108:48] - node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2108:93] - node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2108:100] - node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2108:71] - node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2110:34] - node _T_744 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2110:86] - node _T_745 = mux(_T_743, io.dec_csr_wrdata_r, _T_744) @[dec_tlu_ctl.scala 2110:21] - node _T_746 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2113:78] - node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2113:111] + node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2102:48] + node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2102:93] + node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2102:100] + node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2102:71] + node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2104:34] + node _T_744 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2104:86] + node _T_745 = mux(_T_743, io.dec_csr_wrdata_r, _T_744) @[dec_tlu_ctl.scala 2104:21] + node _T_746 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2107:78] + node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2107:111] reg _T_748 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_747 : @[Reg.scala 28:19] _T_748 <= _T_745 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_738 <= _T_748 @[dec_tlu_ctl.scala 2113:13] + _T_738 <= _T_748 @[dec_tlu_ctl.scala 2107:13] node _T_749 = cat(UInt<25>("h00"), _T_738) @[Cat.scala 29:58] - dicad1 <= _T_749 @[dec_tlu_ctl.scala 2114:9] - node _T_750 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2136:69] - node _T_751 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2136:83] - node _T_752 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2136:97] + dicad1 <= _T_749 @[dec_tlu_ctl.scala 2108:9] + node _T_750 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2130:69] + node _T_751 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2130:83] + node _T_752 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2130:97] node _T_753 = cat(_T_750, _T_751) @[Cat.scala 29:58] node _T_754 = cat(_T_753, _T_752) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_754 @[dec_tlu_ctl.scala 2136:56] - io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2139:41] - node _T_755 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2141:52] - node _T_756 = and(_T_755, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2141:75] - node _T_757 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2141:98] - node _T_758 = and(_T_756, _T_757) @[dec_tlu_ctl.scala 2141:96] - node _T_759 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2141:142] - node _T_760 = eq(_T_759, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2141:149] - node icache_rd_valid = and(_T_758, _T_760) @[dec_tlu_ctl.scala 2141:120] - node _T_761 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2142:52] - node _T_762 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2142:97] - node _T_763 = eq(_T_762, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2142:104] - node icache_wr_valid = and(_T_761, _T_763) @[dec_tlu_ctl.scala 2142:75] - reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2144:58] - icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2144:58] - reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2145:58] - icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2145:58] - io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2147:41] - io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2148:41] - node _T_764 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2156:62] - node _T_765 = eq(_T_764, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2156:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_765) @[dec_tlu_ctl.scala 2156:40] - node _T_766 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2157:32] - node _T_767 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2157:59] - node mtsel_ns = mux(_T_766, _T_767, mtsel) @[dec_tlu_ctl.scala 2157:20] - reg _T_768 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2159:43] - _T_768 <= mtsel_ns @[dec_tlu_ctl.scala 2159:43] - mtsel <= _T_768 @[dec_tlu_ctl.scala 2159:8] - node _T_769 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2194:38] - node _T_770 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2194:64] - node _T_771 = not(_T_770) @[dec_tlu_ctl.scala 2194:44] - node tdata_load = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2194:42] - node _T_772 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2196:40] - node _T_773 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2196:66] - node _T_774 = not(_T_773) @[dec_tlu_ctl.scala 2196:46] - node tdata_opcode = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2196:44] - node _T_775 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2198:41] - node _T_776 = and(_T_775, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2198:46] - node _T_777 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2198:90] - node tdata_action = and(_T_776, _T_777) @[dec_tlu_ctl.scala 2198:69] - node _T_778 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2200:47] - node _T_779 = and(_T_778, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2200:52] - node _T_780 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2200:94] - node _T_781 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2200:136] - node _T_782 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2201:43] - node _T_783 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2201:83] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_754 @[dec_tlu_ctl.scala 2130:56] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2133:41] + node _T_755 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2135:52] + node _T_756 = and(_T_755, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2135:75] + node _T_757 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2135:98] + node _T_758 = and(_T_756, _T_757) @[dec_tlu_ctl.scala 2135:96] + node _T_759 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2135:142] + node _T_760 = eq(_T_759, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2135:149] + node icache_rd_valid = and(_T_758, _T_760) @[dec_tlu_ctl.scala 2135:120] + node _T_761 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2136:52] + node _T_762 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2136:97] + node _T_763 = eq(_T_762, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2136:104] + node icache_wr_valid = and(_T_761, _T_763) @[dec_tlu_ctl.scala 2136:75] + reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2138:58] + icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2138:58] + reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2139:58] + icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2139:58] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2141:41] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2142:41] + node _T_764 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2150:62] + node _T_765 = eq(_T_764, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2150:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_765) @[dec_tlu_ctl.scala 2150:40] + node _T_766 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2151:32] + node _T_767 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2151:59] + node mtsel_ns = mux(_T_766, _T_767, mtsel) @[dec_tlu_ctl.scala 2151:20] + reg _T_768 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2153:43] + _T_768 <= mtsel_ns @[dec_tlu_ctl.scala 2153:43] + mtsel <= _T_768 @[dec_tlu_ctl.scala 2153:8] + node _T_769 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2188:38] + node _T_770 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2188:64] + node _T_771 = not(_T_770) @[dec_tlu_ctl.scala 2188:44] + node tdata_load = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2188:42] + node _T_772 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2190:40] + node _T_773 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2190:66] + node _T_774 = not(_T_773) @[dec_tlu_ctl.scala 2190:46] + node tdata_opcode = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2190:44] + node _T_775 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2192:41] + node _T_776 = and(_T_775, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2192:46] + node _T_777 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2192:90] + node tdata_action = and(_T_776, _T_777) @[dec_tlu_ctl.scala 2192:69] + node _T_778 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2194:47] + node _T_779 = and(_T_778, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2194:52] + node _T_780 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2194:94] + node _T_781 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2194:136] + node _T_782 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2195:43] + node _T_783 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2195:83] node _T_784 = cat(_T_783, tdata_load) @[Cat.scala 29:58] node _T_785 = cat(_T_782, tdata_opcode) @[Cat.scala 29:58] node _T_786 = cat(_T_785, _T_784) @[Cat.scala 29:58] @@ -74085,106 +74085,106 @@ circuit quasar_wrapper : node _T_788 = cat(_T_779, _T_780) @[Cat.scala 29:58] node _T_789 = cat(_T_788, _T_787) @[Cat.scala 29:58] node tdata_wrdata_r = cat(_T_789, _T_786) @[Cat.scala 29:58] - node _T_790 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_791 = eq(_T_790, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_792 = and(io.dec_csr_wen_r_mod, _T_791) @[dec_tlu_ctl.scala 2204:70] - node _T_793 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2204:121] - node _T_794 = and(_T_792, _T_793) @[dec_tlu_ctl.scala 2204:112] - node _T_795 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_796 = not(_T_795) @[dec_tlu_ctl.scala 2204:138] - node _T_797 = or(_T_796, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_798 = and(_T_794, _T_797) @[dec_tlu_ctl.scala 2204:135] - node _T_799 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_800 = eq(_T_799, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_801 = and(io.dec_csr_wen_r_mod, _T_800) @[dec_tlu_ctl.scala 2204:70] - node _T_802 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2204:121] - node _T_803 = and(_T_801, _T_802) @[dec_tlu_ctl.scala 2204:112] - node _T_804 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_805 = not(_T_804) @[dec_tlu_ctl.scala 2204:138] - node _T_806 = or(_T_805, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_807 = and(_T_803, _T_806) @[dec_tlu_ctl.scala 2204:135] - node _T_808 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_809 = eq(_T_808, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_810 = and(io.dec_csr_wen_r_mod, _T_809) @[dec_tlu_ctl.scala 2204:70] - node _T_811 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2204:121] - node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 2204:112] - node _T_813 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_814 = not(_T_813) @[dec_tlu_ctl.scala 2204:138] - node _T_815 = or(_T_814, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_816 = and(_T_812, _T_815) @[dec_tlu_ctl.scala 2204:135] - node _T_817 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2204:92] - node _T_818 = eq(_T_817, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2204:99] - node _T_819 = and(io.dec_csr_wen_r_mod, _T_818) @[dec_tlu_ctl.scala 2204:70] - node _T_820 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2204:121] - node _T_821 = and(_T_819, _T_820) @[dec_tlu_ctl.scala 2204:112] - node _T_822 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2204:154] - node _T_823 = not(_T_822) @[dec_tlu_ctl.scala 2204:138] - node _T_824 = or(_T_823, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2204:170] - node _T_825 = and(_T_821, _T_824) @[dec_tlu_ctl.scala 2204:135] - wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[0] <= _T_798 @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[1] <= _T_807 @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[2] <= _T_816 @[dec_tlu_ctl.scala 2204:42] - wr_mtdata1_t_r[3] <= _T_825 @[dec_tlu_ctl.scala 2204:42] - node _T_826 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_827 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_828 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2205:135] - node _T_829 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_830 = or(_T_828, _T_829) @[dec_tlu_ctl.scala 2205:139] - node _T_831 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_790 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2198:92] + node _T_791 = eq(_T_790, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2198:99] + node _T_792 = and(io.dec_csr_wen_r_mod, _T_791) @[dec_tlu_ctl.scala 2198:70] + node _T_793 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2198:121] + node _T_794 = and(_T_792, _T_793) @[dec_tlu_ctl.scala 2198:112] + node _T_795 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2198:154] + node _T_796 = not(_T_795) @[dec_tlu_ctl.scala 2198:138] + node _T_797 = or(_T_796, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2198:170] + node _T_798 = and(_T_794, _T_797) @[dec_tlu_ctl.scala 2198:135] + node _T_799 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2198:92] + node _T_800 = eq(_T_799, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2198:99] + node _T_801 = and(io.dec_csr_wen_r_mod, _T_800) @[dec_tlu_ctl.scala 2198:70] + node _T_802 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2198:121] + node _T_803 = and(_T_801, _T_802) @[dec_tlu_ctl.scala 2198:112] + node _T_804 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2198:154] + node _T_805 = not(_T_804) @[dec_tlu_ctl.scala 2198:138] + node _T_806 = or(_T_805, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2198:170] + node _T_807 = and(_T_803, _T_806) @[dec_tlu_ctl.scala 2198:135] + node _T_808 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2198:92] + node _T_809 = eq(_T_808, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2198:99] + node _T_810 = and(io.dec_csr_wen_r_mod, _T_809) @[dec_tlu_ctl.scala 2198:70] + node _T_811 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2198:121] + node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 2198:112] + node _T_813 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2198:154] + node _T_814 = not(_T_813) @[dec_tlu_ctl.scala 2198:138] + node _T_815 = or(_T_814, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2198:170] + node _T_816 = and(_T_812, _T_815) @[dec_tlu_ctl.scala 2198:135] + node _T_817 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2198:92] + node _T_818 = eq(_T_817, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2198:99] + node _T_819 = and(io.dec_csr_wen_r_mod, _T_818) @[dec_tlu_ctl.scala 2198:70] + node _T_820 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2198:121] + node _T_821 = and(_T_819, _T_820) @[dec_tlu_ctl.scala 2198:112] + node _T_822 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2198:154] + node _T_823 = not(_T_822) @[dec_tlu_ctl.scala 2198:138] + node _T_824 = or(_T_823, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2198:170] + node _T_825 = and(_T_821, _T_824) @[dec_tlu_ctl.scala 2198:135] + wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2198:42] + wr_mtdata1_t_r[0] <= _T_798 @[dec_tlu_ctl.scala 2198:42] + wr_mtdata1_t_r[1] <= _T_807 @[dec_tlu_ctl.scala 2198:42] + wr_mtdata1_t_r[2] <= _T_816 @[dec_tlu_ctl.scala 2198:42] + wr_mtdata1_t_r[3] <= _T_825 @[dec_tlu_ctl.scala 2198:42] + node _T_826 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2199:68] + node _T_827 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2199:111] + node _T_828 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2199:135] + node _T_829 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2199:156] + node _T_830 = or(_T_828, _T_829) @[dec_tlu_ctl.scala 2199:139] + node _T_831 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2199:176] node _T_832 = cat(_T_827, _T_830) @[Cat.scala 29:58] node _T_833 = cat(_T_832, _T_831) @[Cat.scala 29:58] - node _T_834 = mux(_T_826, tdata_wrdata_r, _T_833) @[dec_tlu_ctl.scala 2205:49] - node _T_835 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_836 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_837 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2205:135] - node _T_838 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_839 = or(_T_837, _T_838) @[dec_tlu_ctl.scala 2205:139] - node _T_840 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_834 = mux(_T_826, tdata_wrdata_r, _T_833) @[dec_tlu_ctl.scala 2199:49] + node _T_835 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2199:68] + node _T_836 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2199:111] + node _T_837 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2199:135] + node _T_838 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2199:156] + node _T_839 = or(_T_837, _T_838) @[dec_tlu_ctl.scala 2199:139] + node _T_840 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2199:176] node _T_841 = cat(_T_836, _T_839) @[Cat.scala 29:58] node _T_842 = cat(_T_841, _T_840) @[Cat.scala 29:58] - node _T_843 = mux(_T_835, tdata_wrdata_r, _T_842) @[dec_tlu_ctl.scala 2205:49] - node _T_844 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_845 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_846 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2205:135] - node _T_847 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_848 = or(_T_846, _T_847) @[dec_tlu_ctl.scala 2205:139] - node _T_849 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_843 = mux(_T_835, tdata_wrdata_r, _T_842) @[dec_tlu_ctl.scala 2199:49] + node _T_844 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2199:68] + node _T_845 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2199:111] + node _T_846 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2199:135] + node _T_847 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2199:156] + node _T_848 = or(_T_846, _T_847) @[dec_tlu_ctl.scala 2199:139] + node _T_849 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2199:176] node _T_850 = cat(_T_845, _T_848) @[Cat.scala 29:58] node _T_851 = cat(_T_850, _T_849) @[Cat.scala 29:58] - node _T_852 = mux(_T_844, tdata_wrdata_r, _T_851) @[dec_tlu_ctl.scala 2205:49] - node _T_853 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2205:68] - node _T_854 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2205:111] - node _T_855 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2205:135] - node _T_856 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2205:156] - node _T_857 = or(_T_855, _T_856) @[dec_tlu_ctl.scala 2205:139] - node _T_858 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2205:176] + node _T_852 = mux(_T_844, tdata_wrdata_r, _T_851) @[dec_tlu_ctl.scala 2199:49] + node _T_853 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2199:68] + node _T_854 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2199:111] + node _T_855 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2199:135] + node _T_856 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2199:156] + node _T_857 = or(_T_855, _T_856) @[dec_tlu_ctl.scala 2199:139] + node _T_858 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2199:176] node _T_859 = cat(_T_854, _T_857) @[Cat.scala 29:58] node _T_860 = cat(_T_859, _T_858) @[Cat.scala 29:58] - node _T_861 = mux(_T_853, tdata_wrdata_r, _T_860) @[dec_tlu_ctl.scala 2205:49] - wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[0] <= _T_834 @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[1] <= _T_843 @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[2] <= _T_852 @[dec_tlu_ctl.scala 2205:40] - mtdata1_t_ns[3] <= _T_861 @[dec_tlu_ctl.scala 2205:40] - reg _T_862 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_862 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[0] <= _T_862 @[dec_tlu_ctl.scala 2207:39] - reg _T_863 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_863 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[1] <= _T_863 @[dec_tlu_ctl.scala 2207:39] - reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_864 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[2] <= _T_864 @[dec_tlu_ctl.scala 2207:39] - reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2207:74] - _T_865 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2207:74] - io.mtdata1_t[3] <= _T_865 @[dec_tlu_ctl.scala 2207:39] - node _T_866 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2210:58] - node _T_867 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_868 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_869 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_870 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_871 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_861 = mux(_T_853, tdata_wrdata_r, _T_860) @[dec_tlu_ctl.scala 2199:49] + wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2199:40] + mtdata1_t_ns[0] <= _T_834 @[dec_tlu_ctl.scala 2199:40] + mtdata1_t_ns[1] <= _T_843 @[dec_tlu_ctl.scala 2199:40] + mtdata1_t_ns[2] <= _T_852 @[dec_tlu_ctl.scala 2199:40] + mtdata1_t_ns[3] <= _T_861 @[dec_tlu_ctl.scala 2199:40] + reg _T_862 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2201:74] + _T_862 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2201:74] + io.mtdata1_t[0] <= _T_862 @[dec_tlu_ctl.scala 2201:39] + reg _T_863 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2201:74] + _T_863 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2201:74] + io.mtdata1_t[1] <= _T_863 @[dec_tlu_ctl.scala 2201:39] + reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2201:74] + _T_864 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2201:74] + io.mtdata1_t[2] <= _T_864 @[dec_tlu_ctl.scala 2201:39] + reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2201:74] + _T_865 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2201:74] + io.mtdata1_t[3] <= _T_865 @[dec_tlu_ctl.scala 2201:39] + node _T_866 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2204:58] + node _T_867 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2204:104] + node _T_868 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2204:142] + node _T_869 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2204:174] + node _T_870 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2204:206] + node _T_871 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2204:238] node _T_872 = cat(UInt<3>("h00"), _T_871) @[Cat.scala 29:58] node _T_873 = cat(_T_869, UInt<3>("h00")) @[Cat.scala 29:58] node _T_874 = cat(_T_873, _T_870) @[Cat.scala 29:58] @@ -74194,12 +74194,12 @@ circuit quasar_wrapper : node _T_878 = cat(_T_877, UInt<6>("h01f")) @[Cat.scala 29:58] node _T_879 = cat(_T_878, _T_876) @[Cat.scala 29:58] node _T_880 = cat(_T_879, _T_875) @[Cat.scala 29:58] - node _T_881 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2210:58] - node _T_882 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_883 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_884 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_885 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_886 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_881 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2204:58] + node _T_882 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2204:104] + node _T_883 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2204:142] + node _T_884 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2204:174] + node _T_885 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2204:206] + node _T_886 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2204:238] node _T_887 = cat(UInt<3>("h00"), _T_886) @[Cat.scala 29:58] node _T_888 = cat(_T_884, UInt<3>("h00")) @[Cat.scala 29:58] node _T_889 = cat(_T_888, _T_885) @[Cat.scala 29:58] @@ -74209,12 +74209,12 @@ circuit quasar_wrapper : node _T_893 = cat(_T_892, UInt<6>("h01f")) @[Cat.scala 29:58] node _T_894 = cat(_T_893, _T_891) @[Cat.scala 29:58] node _T_895 = cat(_T_894, _T_890) @[Cat.scala 29:58] - node _T_896 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2210:58] - node _T_897 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_898 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_899 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_900 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_901 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_896 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2204:58] + node _T_897 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2204:104] + node _T_898 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2204:142] + node _T_899 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2204:174] + node _T_900 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2204:206] + node _T_901 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2204:238] node _T_902 = cat(UInt<3>("h00"), _T_901) @[Cat.scala 29:58] node _T_903 = cat(_T_899, UInt<3>("h00")) @[Cat.scala 29:58] node _T_904 = cat(_T_903, _T_900) @[Cat.scala 29:58] @@ -74224,12 +74224,12 @@ circuit quasar_wrapper : node _T_908 = cat(_T_907, UInt<6>("h01f")) @[Cat.scala 29:58] node _T_909 = cat(_T_908, _T_906) @[Cat.scala 29:58] node _T_910 = cat(_T_909, _T_905) @[Cat.scala 29:58] - node _T_911 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2210:58] - node _T_912 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2210:104] - node _T_913 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2210:142] - node _T_914 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2210:174] - node _T_915 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2210:206] - node _T_916 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2210:238] + node _T_911 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2204:58] + node _T_912 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2204:104] + node _T_913 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2204:142] + node _T_914 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2204:174] + node _T_915 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2204:206] + node _T_916 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2204:238] node _T_917 = cat(UInt<3>("h00"), _T_916) @[Cat.scala 29:58] node _T_918 = cat(_T_914, UInt<3>("h00")) @[Cat.scala 29:58] node _T_919 = cat(_T_918, _T_915) @[Cat.scala 29:58] @@ -74248,96 +74248,96 @@ circuit quasar_wrapper : node _T_932 = or(_T_931, _T_929) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] mtdata1_tsel_out <= _T_932 @[Mux.scala 27:72] - node _T_933 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[0].select <= _T_933 @[dec_tlu_ctl.scala 2212:40] - node _T_934 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[0].match_pkt <= _T_934 @[dec_tlu_ctl.scala 2213:43] - node _T_935 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[0].store <= _T_935 @[dec_tlu_ctl.scala 2214:40] - node _T_936 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[0].load <= _T_936 @[dec_tlu_ctl.scala 2215:40] - node _T_937 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[0].execute <= _T_937 @[dec_tlu_ctl.scala 2216:40] - node _T_938 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[0].m <= _T_938 @[dec_tlu_ctl.scala 2217:40] - node _T_939 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[1].select <= _T_939 @[dec_tlu_ctl.scala 2212:40] - node _T_940 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[1].match_pkt <= _T_940 @[dec_tlu_ctl.scala 2213:43] - node _T_941 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[1].store <= _T_941 @[dec_tlu_ctl.scala 2214:40] - node _T_942 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[1].load <= _T_942 @[dec_tlu_ctl.scala 2215:40] - node _T_943 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[1].execute <= _T_943 @[dec_tlu_ctl.scala 2216:40] - node _T_944 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[1].m <= _T_944 @[dec_tlu_ctl.scala 2217:40] - node _T_945 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[2].select <= _T_945 @[dec_tlu_ctl.scala 2212:40] - node _T_946 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[2].match_pkt <= _T_946 @[dec_tlu_ctl.scala 2213:43] - node _T_947 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[2].store <= _T_947 @[dec_tlu_ctl.scala 2214:40] - node _T_948 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[2].load <= _T_948 @[dec_tlu_ctl.scala 2215:40] - node _T_949 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[2].execute <= _T_949 @[dec_tlu_ctl.scala 2216:40] - node _T_950 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[2].m <= _T_950 @[dec_tlu_ctl.scala 2217:40] - node _T_951 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2212:58] - io.trigger_pkt_any[3].select <= _T_951 @[dec_tlu_ctl.scala 2212:40] - node _T_952 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2213:61] - io.trigger_pkt_any[3].match_pkt <= _T_952 @[dec_tlu_ctl.scala 2213:43] - node _T_953 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2214:58] - io.trigger_pkt_any[3].store <= _T_953 @[dec_tlu_ctl.scala 2214:40] - node _T_954 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2215:58] - io.trigger_pkt_any[3].load <= _T_954 @[dec_tlu_ctl.scala 2215:40] - node _T_955 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2216:58] - io.trigger_pkt_any[3].execute <= _T_955 @[dec_tlu_ctl.scala 2216:40] - node _T_956 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2217:58] - io.trigger_pkt_any[3].m <= _T_956 @[dec_tlu_ctl.scala 2217:40] - node _T_957 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_958 = eq(_T_957, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_959 = and(io.dec_csr_wen_r_mod, _T_958) @[dec_tlu_ctl.scala 2224:69] - node _T_960 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2224:120] - node _T_961 = and(_T_959, _T_960) @[dec_tlu_ctl.scala 2224:111] - node _T_962 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_963 = not(_T_962) @[dec_tlu_ctl.scala 2224:137] - node _T_964 = or(_T_963, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_965 = and(_T_961, _T_964) @[dec_tlu_ctl.scala 2224:134] - node _T_966 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_967 = eq(_T_966, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_968 = and(io.dec_csr_wen_r_mod, _T_967) @[dec_tlu_ctl.scala 2224:69] - node _T_969 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2224:120] - node _T_970 = and(_T_968, _T_969) @[dec_tlu_ctl.scala 2224:111] - node _T_971 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_972 = not(_T_971) @[dec_tlu_ctl.scala 2224:137] - node _T_973 = or(_T_972, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_974 = and(_T_970, _T_973) @[dec_tlu_ctl.scala 2224:134] - node _T_975 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_976 = eq(_T_975, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_977 = and(io.dec_csr_wen_r_mod, _T_976) @[dec_tlu_ctl.scala 2224:69] - node _T_978 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2224:120] - node _T_979 = and(_T_977, _T_978) @[dec_tlu_ctl.scala 2224:111] - node _T_980 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_981 = not(_T_980) @[dec_tlu_ctl.scala 2224:137] - node _T_982 = or(_T_981, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_983 = and(_T_979, _T_982) @[dec_tlu_ctl.scala 2224:134] - node _T_984 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2224:91] - node _T_985 = eq(_T_984, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2224:98] - node _T_986 = and(io.dec_csr_wen_r_mod, _T_985) @[dec_tlu_ctl.scala 2224:69] - node _T_987 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2224:120] - node _T_988 = and(_T_986, _T_987) @[dec_tlu_ctl.scala 2224:111] - node _T_989 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:153] - node _T_990 = not(_T_989) @[dec_tlu_ctl.scala 2224:137] - node _T_991 = or(_T_990, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2224:169] - node _T_992 = and(_T_988, _T_991) @[dec_tlu_ctl.scala 2224:134] - wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[0] <= _T_965 @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[1] <= _T_974 @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[2] <= _T_983 @[dec_tlu_ctl.scala 2224:42] - wr_mtdata2_t_r[3] <= _T_992 @[dec_tlu_ctl.scala 2224:42] - node _T_993 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2225:84] + node _T_933 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2206:58] + io.trigger_pkt_any[0].select <= _T_933 @[dec_tlu_ctl.scala 2206:40] + node _T_934 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2207:61] + io.trigger_pkt_any[0].match_pkt <= _T_934 @[dec_tlu_ctl.scala 2207:43] + node _T_935 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2208:58] + io.trigger_pkt_any[0].store <= _T_935 @[dec_tlu_ctl.scala 2208:40] + node _T_936 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2209:58] + io.trigger_pkt_any[0].load <= _T_936 @[dec_tlu_ctl.scala 2209:40] + node _T_937 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2210:58] + io.trigger_pkt_any[0].execute <= _T_937 @[dec_tlu_ctl.scala 2210:40] + node _T_938 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2211:58] + io.trigger_pkt_any[0].m <= _T_938 @[dec_tlu_ctl.scala 2211:40] + node _T_939 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2206:58] + io.trigger_pkt_any[1].select <= _T_939 @[dec_tlu_ctl.scala 2206:40] + node _T_940 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2207:61] + io.trigger_pkt_any[1].match_pkt <= _T_940 @[dec_tlu_ctl.scala 2207:43] + node _T_941 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2208:58] + io.trigger_pkt_any[1].store <= _T_941 @[dec_tlu_ctl.scala 2208:40] + node _T_942 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2209:58] + io.trigger_pkt_any[1].load <= _T_942 @[dec_tlu_ctl.scala 2209:40] + node _T_943 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2210:58] + io.trigger_pkt_any[1].execute <= _T_943 @[dec_tlu_ctl.scala 2210:40] + node _T_944 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2211:58] + io.trigger_pkt_any[1].m <= _T_944 @[dec_tlu_ctl.scala 2211:40] + node _T_945 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2206:58] + io.trigger_pkt_any[2].select <= _T_945 @[dec_tlu_ctl.scala 2206:40] + node _T_946 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2207:61] + io.trigger_pkt_any[2].match_pkt <= _T_946 @[dec_tlu_ctl.scala 2207:43] + node _T_947 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2208:58] + io.trigger_pkt_any[2].store <= _T_947 @[dec_tlu_ctl.scala 2208:40] + node _T_948 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2209:58] + io.trigger_pkt_any[2].load <= _T_948 @[dec_tlu_ctl.scala 2209:40] + node _T_949 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2210:58] + io.trigger_pkt_any[2].execute <= _T_949 @[dec_tlu_ctl.scala 2210:40] + node _T_950 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2211:58] + io.trigger_pkt_any[2].m <= _T_950 @[dec_tlu_ctl.scala 2211:40] + node _T_951 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2206:58] + io.trigger_pkt_any[3].select <= _T_951 @[dec_tlu_ctl.scala 2206:40] + node _T_952 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2207:61] + io.trigger_pkt_any[3].match_pkt <= _T_952 @[dec_tlu_ctl.scala 2207:43] + node _T_953 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2208:58] + io.trigger_pkt_any[3].store <= _T_953 @[dec_tlu_ctl.scala 2208:40] + node _T_954 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2209:58] + io.trigger_pkt_any[3].load <= _T_954 @[dec_tlu_ctl.scala 2209:40] + node _T_955 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2210:58] + io.trigger_pkt_any[3].execute <= _T_955 @[dec_tlu_ctl.scala 2210:40] + node _T_956 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2211:58] + io.trigger_pkt_any[3].m <= _T_956 @[dec_tlu_ctl.scala 2211:40] + node _T_957 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2218:91] + node _T_958 = eq(_T_957, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2218:98] + node _T_959 = and(io.dec_csr_wen_r_mod, _T_958) @[dec_tlu_ctl.scala 2218:69] + node _T_960 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2218:120] + node _T_961 = and(_T_959, _T_960) @[dec_tlu_ctl.scala 2218:111] + node _T_962 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2218:153] + node _T_963 = not(_T_962) @[dec_tlu_ctl.scala 2218:137] + node _T_964 = or(_T_963, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:169] + node _T_965 = and(_T_961, _T_964) @[dec_tlu_ctl.scala 2218:134] + node _T_966 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2218:91] + node _T_967 = eq(_T_966, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2218:98] + node _T_968 = and(io.dec_csr_wen_r_mod, _T_967) @[dec_tlu_ctl.scala 2218:69] + node _T_969 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2218:120] + node _T_970 = and(_T_968, _T_969) @[dec_tlu_ctl.scala 2218:111] + node _T_971 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2218:153] + node _T_972 = not(_T_971) @[dec_tlu_ctl.scala 2218:137] + node _T_973 = or(_T_972, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:169] + node _T_974 = and(_T_970, _T_973) @[dec_tlu_ctl.scala 2218:134] + node _T_975 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2218:91] + node _T_976 = eq(_T_975, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2218:98] + node _T_977 = and(io.dec_csr_wen_r_mod, _T_976) @[dec_tlu_ctl.scala 2218:69] + node _T_978 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2218:120] + node _T_979 = and(_T_977, _T_978) @[dec_tlu_ctl.scala 2218:111] + node _T_980 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2218:153] + node _T_981 = not(_T_980) @[dec_tlu_ctl.scala 2218:137] + node _T_982 = or(_T_981, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:169] + node _T_983 = and(_T_979, _T_982) @[dec_tlu_ctl.scala 2218:134] + node _T_984 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2218:91] + node _T_985 = eq(_T_984, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2218:98] + node _T_986 = and(io.dec_csr_wen_r_mod, _T_985) @[dec_tlu_ctl.scala 2218:69] + node _T_987 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2218:120] + node _T_988 = and(_T_986, _T_987) @[dec_tlu_ctl.scala 2218:111] + node _T_989 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2218:153] + node _T_990 = not(_T_989) @[dec_tlu_ctl.scala 2218:137] + node _T_991 = or(_T_990, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:169] + node _T_992 = and(_T_988, _T_991) @[dec_tlu_ctl.scala 2218:134] + wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2218:42] + wr_mtdata2_t_r[0] <= _T_965 @[dec_tlu_ctl.scala 2218:42] + wr_mtdata2_t_r[1] <= _T_974 @[dec_tlu_ctl.scala 2218:42] + wr_mtdata2_t_r[2] <= _T_983 @[dec_tlu_ctl.scala 2218:42] + wr_mtdata2_t_r[3] <= _T_992 @[dec_tlu_ctl.scala 2218:42] + node _T_993 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2219:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset @@ -74346,8 +74346,8 @@ circuit quasar_wrapper : rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_994 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_994 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[0] <= _T_994 @[dec_tlu_ctl.scala 2225:36] - node _T_995 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2225:84] + mtdata2_t[0] <= _T_994 @[dec_tlu_ctl.scala 2219:36] + node _T_995 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2219:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset @@ -74356,8 +74356,8 @@ circuit quasar_wrapper : rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_996 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_996 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[1] <= _T_996 @[dec_tlu_ctl.scala 2225:36] - node _T_997 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2225:84] + mtdata2_t[1] <= _T_996 @[dec_tlu_ctl.scala 2219:36] + node _T_997 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2219:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset @@ -74366,8 +74366,8 @@ circuit quasar_wrapper : rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_998 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_998 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[2] <= _T_998 @[dec_tlu_ctl.scala 2225:36] - node _T_999 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2225:84] + mtdata2_t[2] <= _T_998 @[dec_tlu_ctl.scala 2219:36] + node _T_999 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2219:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset @@ -74376,11 +74376,11 @@ circuit quasar_wrapper : rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_1000 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_1000 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[3] <= _T_1000 @[dec_tlu_ctl.scala 2225:36] - node _T_1001 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:57] - node _T_1002 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:57] - node _T_1003 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:57] - node _T_1004 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:57] + mtdata2_t[3] <= _T_1000 @[dec_tlu_ctl.scala 2219:36] + node _T_1001 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2223:57] + node _T_1002 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2223:57] + node _T_1003 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2223:57] + node _T_1004 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2223:57] node _T_1005 = mux(_T_1001, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1006 = mux(_T_1002, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1007 = mux(_T_1003, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -74390,188 +74390,188 @@ circuit quasar_wrapper : node _T_1011 = or(_T_1010, _T_1008) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] mtdata2_tsel_out <= _T_1011 @[Mux.scala 27:72] - io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2230:51] - io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2230:51] - io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2230:51] - io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2230:51] - mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2240:15] - mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2241:15] - mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2242:15] - mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2243:15] + io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2224:51] + io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2224:51] + io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2224:51] + io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2224:51] + mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2234:15] + mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2235:15] + mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2236:15] + mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2237:15] node _T_1012 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] node _T_1013 = mux(_T_1012, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1013) @[dec_tlu_ctl.scala 2249:59] - wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2250:24] - wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2251:27] - node _T_1014 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2255:38] - node _T_1015 = not(_T_1014) @[dec_tlu_ctl.scala 2255:24] - node _T_1016 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1017 = bits(_T_1016, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1018 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1019 = bits(_T_1018, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1020 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1021 = bits(_T_1020, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1022 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1023 = bits(_T_1022, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1024 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1025 = and(io.tlu_i0_commit_cmt, _T_1024) @[dec_tlu_ctl.scala 2259:94] - node _T_1026 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1028 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1029 = and(io.tlu_i0_commit_cmt, _T_1028) @[dec_tlu_ctl.scala 2260:94] - node _T_1030 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1031 = and(_T_1029, _T_1030) @[dec_tlu_ctl.scala 2260:115] - node _T_1032 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1034 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1036 = and(_T_1034, _T_1035) @[dec_tlu_ctl.scala 2261:115] - node _T_1037 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1039 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1040 = bits(_T_1039, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1041 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1042 = bits(_T_1041, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1043 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1045 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1046 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1047 = bits(_T_1046, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1048 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1049 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1051 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1052 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1054 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1055 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1056 = bits(_T_1055, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1057 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1058 = and(_T_1057, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1062 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1063 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2270:101] - node _T_1064 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1065 = bits(_T_1064, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1066 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1067 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1068 = bits(_T_1067, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1069 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1070 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1073 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1074 = bits(_T_1073, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1075 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1076 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1077 = bits(_T_1076, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1078 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1079 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1080 = bits(_T_1079, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1081 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1082 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1083 = bits(_T_1082, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1084 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1085 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1086 = bits(_T_1085, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1087 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1088 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1089 = bits(_T_1088, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1090 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1091 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1092 = bits(_T_1091, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1093 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1095 = or(_T_1093, _T_1094) @[dec_tlu_ctl.scala 2280:101] - node _T_1096 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1098 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1099 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1101 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1102 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1104 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1105 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1106 = bits(_T_1105, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1107 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1111 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1112 = bits(_T_1111, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1113 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1115 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1117 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1119 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1121 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1122 = or(_T_1121, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1123 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1125 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1126 = or(_T_1125, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1127 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1129 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1131 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1132 = bits(_T_1131, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1133 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1134 = and(_T_1133, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1135 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1136 = bits(_T_1135, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1137 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1139 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1141 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1143 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1144 = bits(_T_1143, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1147 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1149 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1151 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_1153 = not(_T_1152) @[dec_tlu_ctl.scala 2303:73] - node _T_1154 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1156 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_1158 = not(_T_1157) @[dec_tlu_ctl.scala 2304:73] - node _T_1159 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_1160 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_1161 = and(_T_1159, _T_1160) @[dec_tlu_ctl.scala 2304:113] - node _T_1162 = orr(_T_1161) @[dec_tlu_ctl.scala 2304:125] - node _T_1163 = and(_T_1158, _T_1162) @[dec_tlu_ctl.scala 2304:98] - node _T_1164 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1166 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_1167 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1169 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_1170 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_1171 = bits(_T_1170, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1172 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_1173 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_1174 = bits(_T_1173, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1175 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1177 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1179 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_1180 = bits(_T_1179, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1181 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1013) @[dec_tlu_ctl.scala 2243:59] + wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2244:24] + wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2245:27] + node _T_1014 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2249:38] + node _T_1015 = not(_T_1014) @[dec_tlu_ctl.scala 2249:24] + node _T_1016 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2250:34] + node _T_1017 = bits(_T_1016, 0, 0) @[dec_tlu_ctl.scala 2250:62] + node _T_1018 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2251:34] + node _T_1019 = bits(_T_1018, 0, 0) @[dec_tlu_ctl.scala 2251:62] + node _T_1020 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2252:34] + node _T_1021 = bits(_T_1020, 0, 0) @[dec_tlu_ctl.scala 2252:62] + node _T_1022 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2253:34] + node _T_1023 = bits(_T_1022, 0, 0) @[dec_tlu_ctl.scala 2253:62] + node _T_1024 = not(io.illegal_r) @[dec_tlu_ctl.scala 2253:96] + node _T_1025 = and(io.tlu_i0_commit_cmt, _T_1024) @[dec_tlu_ctl.scala 2253:94] + node _T_1026 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2254:34] + node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2254:62] + node _T_1028 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2254:96] + node _T_1029 = and(io.tlu_i0_commit_cmt, _T_1028) @[dec_tlu_ctl.scala 2254:94] + node _T_1030 = not(io.illegal_r) @[dec_tlu_ctl.scala 2254:117] + node _T_1031 = and(_T_1029, _T_1030) @[dec_tlu_ctl.scala 2254:115] + node _T_1032 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2255:34] + node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2255:62] + node _T_1034 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2255:94] + node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2255:117] + node _T_1036 = and(_T_1034, _T_1035) @[dec_tlu_ctl.scala 2255:115] + node _T_1037 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2256:34] + node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1039 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2257:34] + node _T_1040 = bits(_T_1039, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1041 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2258:34] + node _T_1042 = bits(_T_1041, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1043 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2259:34] + node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1045 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2259:91] + node _T_1046 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2260:34] + node _T_1047 = bits(_T_1046, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1048 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2260:105] + node _T_1049 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2261:34] + node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1051 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2261:91] + node _T_1052 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2262:34] + node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1054 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2262:91] + node _T_1055 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2263:34] + node _T_1056 = bits(_T_1055, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1057 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2263:91] + node _T_1058 = and(_T_1057, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2263:100] + node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2264:91] + node _T_1062 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2264:142] + node _T_1063 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2264:101] + node _T_1064 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2265:34] + node _T_1065 = bits(_T_1064, 0, 0) @[dec_tlu_ctl.scala 2265:59] + node _T_1066 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2265:89] + node _T_1067 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2266:34] + node _T_1068 = bits(_T_1067, 0, 0) @[dec_tlu_ctl.scala 2266:59] + node _T_1069 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2266:89] + node _T_1070 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2267:34] + node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2267:59] + node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2267:89] + node _T_1073 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2268:34] + node _T_1074 = bits(_T_1073, 0, 0) @[dec_tlu_ctl.scala 2268:59] + node _T_1075 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2268:89] + node _T_1076 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2269:34] + node _T_1077 = bits(_T_1076, 0, 0) @[dec_tlu_ctl.scala 2269:59] + node _T_1078 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2269:89] + node _T_1079 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2270:34] + node _T_1080 = bits(_T_1079, 0, 0) @[dec_tlu_ctl.scala 2270:59] + node _T_1081 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2270:89] + node _T_1082 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2271:34] + node _T_1083 = bits(_T_1082, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1084 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2271:89] + node _T_1085 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2272:34] + node _T_1086 = bits(_T_1085, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1087 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2272:89] + node _T_1088 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2273:34] + node _T_1089 = bits(_T_1088, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1090 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2273:89] + node _T_1091 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2274:34] + node _T_1092 = bits(_T_1091, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1093 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2274:89] + node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2274:122] + node _T_1095 = or(_T_1093, _T_1094) @[dec_tlu_ctl.scala 2274:101] + node _T_1096 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2275:34] + node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1098 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2275:95] + node _T_1099 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2276:34] + node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1101 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2276:97] + node _T_1102 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2277:34] + node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1104 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2277:110] + node _T_1105 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2278:34] + node _T_1106 = bits(_T_1105, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1107 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2279:34] + node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2280:34] + node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1111 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2281:34] + node _T_1112 = bits(_T_1111, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1113 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2282:34] + node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1115 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2283:34] + node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1117 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2284:34] + node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1119 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2285:34] + node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1121 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2285:98] + node _T_1122 = or(_T_1121, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2285:120] + node _T_1123 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2286:34] + node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1125 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2286:92] + node _T_1126 = or(_T_1125, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2286:117] + node _T_1127 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2287:34] + node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1129 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2288:34] + node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1131 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2289:34] + node _T_1132 = bits(_T_1131, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1133 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2289:97] + node _T_1134 = and(_T_1133, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2289:129] + node _T_1135 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2290:34] + node _T_1136 = bits(_T_1135, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1137 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2291:34] + node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1139 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2292:34] + node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1141 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2293:34] + node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1143 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2294:34] + node _T_1144 = bits(_T_1143, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2295:34] + node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1147 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2296:34] + node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1149 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2297:34] + node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1151 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2297:84] + node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2297:84] + node _T_1153 = not(_T_1152) @[dec_tlu_ctl.scala 2297:73] + node _T_1154 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2298:34] + node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1156 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2298:84] + node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2298:84] + node _T_1158 = not(_T_1157) @[dec_tlu_ctl.scala 2298:73] + node _T_1159 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2298:107] + node _T_1160 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2298:118] + node _T_1161 = and(_T_1159, _T_1160) @[dec_tlu_ctl.scala 2298:113] + node _T_1162 = orr(_T_1161) @[dec_tlu_ctl.scala 2298:125] + node _T_1163 = and(_T_1158, _T_1162) @[dec_tlu_ctl.scala 2298:98] + node _T_1164 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2299:34] + node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1166 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2299:91] + node _T_1167 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2300:34] + node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1169 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2300:94] + node _T_1170 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2301:34] + node _T_1171 = bits(_T_1170, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1172 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2301:94] + node _T_1173 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2303:34] + node _T_1174 = bits(_T_1173, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1175 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2304:34] + node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1177 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2305:34] + node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1179 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2306:34] + node _T_1180 = bits(_T_1179, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1181 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2307:34] + node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2307:62] node _T_1183 = mux(_T_1017, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1184 = mux(_T_1019, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1185 = mux(_T_1021, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] @@ -74687,177 +74687,177 @@ circuit quasar_wrapper : node _T_1295 = or(_T_1294, _T_1239) @[Mux.scala 27:72] wire _T_1296 : UInt<1> @[Mux.scala 27:72] _T_1296 <= _T_1295 @[Mux.scala 27:72] - node _T_1297 = and(_T_1015, _T_1296) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[0] <= _T_1297 @[dec_tlu_ctl.scala 2255:19] - node _T_1298 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2255:38] - node _T_1299 = not(_T_1298) @[dec_tlu_ctl.scala 2255:24] - node _T_1300 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1301 = bits(_T_1300, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1302 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1303 = bits(_T_1302, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1304 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1305 = bits(_T_1304, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1306 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1307 = bits(_T_1306, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1308 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1309 = and(io.tlu_i0_commit_cmt, _T_1308) @[dec_tlu_ctl.scala 2259:94] - node _T_1310 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1312 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1313 = and(io.tlu_i0_commit_cmt, _T_1312) @[dec_tlu_ctl.scala 2260:94] - node _T_1314 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1315 = and(_T_1313, _T_1314) @[dec_tlu_ctl.scala 2260:115] - node _T_1316 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1318 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1320 = and(_T_1318, _T_1319) @[dec_tlu_ctl.scala 2261:115] - node _T_1321 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1323 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1324 = bits(_T_1323, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1325 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1326 = bits(_T_1325, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1327 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1329 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1330 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1331 = bits(_T_1330, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1332 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1333 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1335 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1336 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1338 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1339 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1340 = bits(_T_1339, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1341 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1342 = and(_T_1341, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1346 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1347 = and(_T_1345, _T_1346) @[dec_tlu_ctl.scala 2270:101] - node _T_1348 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1349 = bits(_T_1348, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1350 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1351 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1352 = bits(_T_1351, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1353 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1354 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1357 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1358 = bits(_T_1357, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1359 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1360 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1361 = bits(_T_1360, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1362 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1363 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1364 = bits(_T_1363, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1365 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1366 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1367 = bits(_T_1366, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1368 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1369 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1370 = bits(_T_1369, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1371 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1372 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1373 = bits(_T_1372, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1374 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1375 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1376 = bits(_T_1375, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1377 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1379 = or(_T_1377, _T_1378) @[dec_tlu_ctl.scala 2280:101] - node _T_1380 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1382 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1383 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1385 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1386 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1388 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1389 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1390 = bits(_T_1389, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1391 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1395 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1396 = bits(_T_1395, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1397 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1399 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1401 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1403 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1405 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1406 = or(_T_1405, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1407 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1409 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1410 = or(_T_1409, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1411 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1413 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1415 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1416 = bits(_T_1415, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1417 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1418 = and(_T_1417, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1419 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1420 = bits(_T_1419, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1421 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1423 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1425 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1427 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1428 = bits(_T_1427, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1431 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1433 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1435 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_1437 = not(_T_1436) @[dec_tlu_ctl.scala 2303:73] - node _T_1438 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1440 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_1442 = not(_T_1441) @[dec_tlu_ctl.scala 2304:73] - node _T_1443 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_1444 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_1445 = and(_T_1443, _T_1444) @[dec_tlu_ctl.scala 2304:113] - node _T_1446 = orr(_T_1445) @[dec_tlu_ctl.scala 2304:125] - node _T_1447 = and(_T_1442, _T_1446) @[dec_tlu_ctl.scala 2304:98] - node _T_1448 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1450 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_1451 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1453 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_1454 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_1455 = bits(_T_1454, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1456 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_1457 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_1458 = bits(_T_1457, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1459 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1461 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1463 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_1464 = bits(_T_1463, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1465 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1297 = and(_T_1015, _T_1296) @[dec_tlu_ctl.scala 2249:44] + mhpmc_inc_r[0] <= _T_1297 @[dec_tlu_ctl.scala 2249:19] + node _T_1298 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2249:38] + node _T_1299 = not(_T_1298) @[dec_tlu_ctl.scala 2249:24] + node _T_1300 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2250:34] + node _T_1301 = bits(_T_1300, 0, 0) @[dec_tlu_ctl.scala 2250:62] + node _T_1302 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2251:34] + node _T_1303 = bits(_T_1302, 0, 0) @[dec_tlu_ctl.scala 2251:62] + node _T_1304 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2252:34] + node _T_1305 = bits(_T_1304, 0, 0) @[dec_tlu_ctl.scala 2252:62] + node _T_1306 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2253:34] + node _T_1307 = bits(_T_1306, 0, 0) @[dec_tlu_ctl.scala 2253:62] + node _T_1308 = not(io.illegal_r) @[dec_tlu_ctl.scala 2253:96] + node _T_1309 = and(io.tlu_i0_commit_cmt, _T_1308) @[dec_tlu_ctl.scala 2253:94] + node _T_1310 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2254:34] + node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2254:62] + node _T_1312 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2254:96] + node _T_1313 = and(io.tlu_i0_commit_cmt, _T_1312) @[dec_tlu_ctl.scala 2254:94] + node _T_1314 = not(io.illegal_r) @[dec_tlu_ctl.scala 2254:117] + node _T_1315 = and(_T_1313, _T_1314) @[dec_tlu_ctl.scala 2254:115] + node _T_1316 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2255:34] + node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2255:62] + node _T_1318 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2255:94] + node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2255:117] + node _T_1320 = and(_T_1318, _T_1319) @[dec_tlu_ctl.scala 2255:115] + node _T_1321 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2256:34] + node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1323 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2257:34] + node _T_1324 = bits(_T_1323, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1325 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2258:34] + node _T_1326 = bits(_T_1325, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1327 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2259:34] + node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1329 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2259:91] + node _T_1330 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2260:34] + node _T_1331 = bits(_T_1330, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1332 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2260:105] + node _T_1333 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2261:34] + node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1335 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2261:91] + node _T_1336 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2262:34] + node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1338 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2262:91] + node _T_1339 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2263:34] + node _T_1340 = bits(_T_1339, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1341 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2263:91] + node _T_1342 = and(_T_1341, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2263:100] + node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2264:91] + node _T_1346 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2264:142] + node _T_1347 = and(_T_1345, _T_1346) @[dec_tlu_ctl.scala 2264:101] + node _T_1348 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2265:34] + node _T_1349 = bits(_T_1348, 0, 0) @[dec_tlu_ctl.scala 2265:59] + node _T_1350 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2265:89] + node _T_1351 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2266:34] + node _T_1352 = bits(_T_1351, 0, 0) @[dec_tlu_ctl.scala 2266:59] + node _T_1353 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2266:89] + node _T_1354 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2267:34] + node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2267:59] + node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2267:89] + node _T_1357 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2268:34] + node _T_1358 = bits(_T_1357, 0, 0) @[dec_tlu_ctl.scala 2268:59] + node _T_1359 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2268:89] + node _T_1360 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2269:34] + node _T_1361 = bits(_T_1360, 0, 0) @[dec_tlu_ctl.scala 2269:59] + node _T_1362 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2269:89] + node _T_1363 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2270:34] + node _T_1364 = bits(_T_1363, 0, 0) @[dec_tlu_ctl.scala 2270:59] + node _T_1365 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2270:89] + node _T_1366 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2271:34] + node _T_1367 = bits(_T_1366, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1368 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2271:89] + node _T_1369 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2272:34] + node _T_1370 = bits(_T_1369, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1371 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2272:89] + node _T_1372 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2273:34] + node _T_1373 = bits(_T_1372, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1374 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2273:89] + node _T_1375 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2274:34] + node _T_1376 = bits(_T_1375, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1377 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2274:89] + node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2274:122] + node _T_1379 = or(_T_1377, _T_1378) @[dec_tlu_ctl.scala 2274:101] + node _T_1380 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2275:34] + node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1382 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2275:95] + node _T_1383 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2276:34] + node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1385 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2276:97] + node _T_1386 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2277:34] + node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1388 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2277:110] + node _T_1389 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2278:34] + node _T_1390 = bits(_T_1389, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1391 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2279:34] + node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2280:34] + node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1395 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2281:34] + node _T_1396 = bits(_T_1395, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1397 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2282:34] + node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1399 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2283:34] + node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1401 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2284:34] + node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1403 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2285:34] + node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1405 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2285:98] + node _T_1406 = or(_T_1405, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2285:120] + node _T_1407 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2286:34] + node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1409 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2286:92] + node _T_1410 = or(_T_1409, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2286:117] + node _T_1411 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2287:34] + node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2288:34] + node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1415 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2289:34] + node _T_1416 = bits(_T_1415, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1417 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2289:97] + node _T_1418 = and(_T_1417, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2289:129] + node _T_1419 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2290:34] + node _T_1420 = bits(_T_1419, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2291:34] + node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2292:34] + node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2293:34] + node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1427 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2294:34] + node _T_1428 = bits(_T_1427, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2295:34] + node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2296:34] + node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2297:34] + node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1435 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2297:84] + node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2297:84] + node _T_1437 = not(_T_1436) @[dec_tlu_ctl.scala 2297:73] + node _T_1438 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2298:34] + node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1440 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2298:84] + node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2298:84] + node _T_1442 = not(_T_1441) @[dec_tlu_ctl.scala 2298:73] + node _T_1443 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2298:107] + node _T_1444 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2298:118] + node _T_1445 = and(_T_1443, _T_1444) @[dec_tlu_ctl.scala 2298:113] + node _T_1446 = orr(_T_1445) @[dec_tlu_ctl.scala 2298:125] + node _T_1447 = and(_T_1442, _T_1446) @[dec_tlu_ctl.scala 2298:98] + node _T_1448 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2299:34] + node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1450 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2299:91] + node _T_1451 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2300:34] + node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1453 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2300:94] + node _T_1454 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2301:34] + node _T_1455 = bits(_T_1454, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1456 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2301:94] + node _T_1457 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2303:34] + node _T_1458 = bits(_T_1457, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1459 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2304:34] + node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1461 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2305:34] + node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1463 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2306:34] + node _T_1464 = bits(_T_1463, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1465 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2307:34] + node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2307:62] node _T_1467 = mux(_T_1301, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1468 = mux(_T_1303, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1469 = mux(_T_1305, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] @@ -74973,177 +74973,177 @@ circuit quasar_wrapper : node _T_1579 = or(_T_1578, _T_1523) @[Mux.scala 27:72] wire _T_1580 : UInt<1> @[Mux.scala 27:72] _T_1580 <= _T_1579 @[Mux.scala 27:72] - node _T_1581 = and(_T_1299, _T_1580) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[1] <= _T_1581 @[dec_tlu_ctl.scala 2255:19] - node _T_1582 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2255:38] - node _T_1583 = not(_T_1582) @[dec_tlu_ctl.scala 2255:24] - node _T_1584 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1585 = bits(_T_1584, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1586 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1587 = bits(_T_1586, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1588 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1589 = bits(_T_1588, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1590 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1591 = bits(_T_1590, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1592 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1593 = and(io.tlu_i0_commit_cmt, _T_1592) @[dec_tlu_ctl.scala 2259:94] - node _T_1594 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1596 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1597 = and(io.tlu_i0_commit_cmt, _T_1596) @[dec_tlu_ctl.scala 2260:94] - node _T_1598 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1599 = and(_T_1597, _T_1598) @[dec_tlu_ctl.scala 2260:115] - node _T_1600 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1602 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1604 = and(_T_1602, _T_1603) @[dec_tlu_ctl.scala 2261:115] - node _T_1605 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1607 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1608 = bits(_T_1607, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1609 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1610 = bits(_T_1609, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1611 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1613 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1614 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1615 = bits(_T_1614, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1616 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1617 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1619 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1620 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1622 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1623 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1624 = bits(_T_1623, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1625 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1626 = and(_T_1625, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1630 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1631 = and(_T_1629, _T_1630) @[dec_tlu_ctl.scala 2270:101] - node _T_1632 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1633 = bits(_T_1632, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1634 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1635 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1636 = bits(_T_1635, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1637 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1638 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1641 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1642 = bits(_T_1641, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1643 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1644 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1645 = bits(_T_1644, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1646 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1647 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1648 = bits(_T_1647, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1649 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1650 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1651 = bits(_T_1650, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1652 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1653 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1654 = bits(_T_1653, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1655 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1656 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1657 = bits(_T_1656, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1658 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1659 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1660 = bits(_T_1659, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1661 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1663 = or(_T_1661, _T_1662) @[dec_tlu_ctl.scala 2280:101] - node _T_1664 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1666 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1667 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1669 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1670 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1672 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1673 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1674 = bits(_T_1673, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1675 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1679 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1680 = bits(_T_1679, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1681 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1683 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1685 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1687 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1689 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1690 = or(_T_1689, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1691 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1693 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1694 = or(_T_1693, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1695 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1697 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1699 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1700 = bits(_T_1699, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1701 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1702 = and(_T_1701, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1703 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1704 = bits(_T_1703, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1705 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1707 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1709 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1711 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1712 = bits(_T_1711, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1715 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1717 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1719 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_1721 = not(_T_1720) @[dec_tlu_ctl.scala 2303:73] - node _T_1722 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1724 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_1726 = not(_T_1725) @[dec_tlu_ctl.scala 2304:73] - node _T_1727 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_1728 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_1729 = and(_T_1727, _T_1728) @[dec_tlu_ctl.scala 2304:113] - node _T_1730 = orr(_T_1729) @[dec_tlu_ctl.scala 2304:125] - node _T_1731 = and(_T_1726, _T_1730) @[dec_tlu_ctl.scala 2304:98] - node _T_1732 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1734 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_1735 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1737 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_1738 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_1739 = bits(_T_1738, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1740 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_1741 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_1742 = bits(_T_1741, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1743 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1745 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1747 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_1748 = bits(_T_1747, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1581 = and(_T_1299, _T_1580) @[dec_tlu_ctl.scala 2249:44] + mhpmc_inc_r[1] <= _T_1581 @[dec_tlu_ctl.scala 2249:19] + node _T_1582 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2249:38] + node _T_1583 = not(_T_1582) @[dec_tlu_ctl.scala 2249:24] + node _T_1584 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2250:34] + node _T_1585 = bits(_T_1584, 0, 0) @[dec_tlu_ctl.scala 2250:62] + node _T_1586 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2251:34] + node _T_1587 = bits(_T_1586, 0, 0) @[dec_tlu_ctl.scala 2251:62] + node _T_1588 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2252:34] + node _T_1589 = bits(_T_1588, 0, 0) @[dec_tlu_ctl.scala 2252:62] + node _T_1590 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2253:34] + node _T_1591 = bits(_T_1590, 0, 0) @[dec_tlu_ctl.scala 2253:62] + node _T_1592 = not(io.illegal_r) @[dec_tlu_ctl.scala 2253:96] + node _T_1593 = and(io.tlu_i0_commit_cmt, _T_1592) @[dec_tlu_ctl.scala 2253:94] + node _T_1594 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2254:34] + node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2254:62] + node _T_1596 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2254:96] + node _T_1597 = and(io.tlu_i0_commit_cmt, _T_1596) @[dec_tlu_ctl.scala 2254:94] + node _T_1598 = not(io.illegal_r) @[dec_tlu_ctl.scala 2254:117] + node _T_1599 = and(_T_1597, _T_1598) @[dec_tlu_ctl.scala 2254:115] + node _T_1600 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2255:34] + node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2255:62] + node _T_1602 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2255:94] + node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2255:117] + node _T_1604 = and(_T_1602, _T_1603) @[dec_tlu_ctl.scala 2255:115] + node _T_1605 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2256:34] + node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1607 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2257:34] + node _T_1608 = bits(_T_1607, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1609 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2258:34] + node _T_1610 = bits(_T_1609, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1611 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2259:34] + node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1613 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2259:91] + node _T_1614 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2260:34] + node _T_1615 = bits(_T_1614, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1616 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2260:105] + node _T_1617 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2261:34] + node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1619 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2261:91] + node _T_1620 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2262:34] + node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1622 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2262:91] + node _T_1623 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2263:34] + node _T_1624 = bits(_T_1623, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1625 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2263:91] + node _T_1626 = and(_T_1625, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2263:100] + node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2264:91] + node _T_1630 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2264:142] + node _T_1631 = and(_T_1629, _T_1630) @[dec_tlu_ctl.scala 2264:101] + node _T_1632 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2265:34] + node _T_1633 = bits(_T_1632, 0, 0) @[dec_tlu_ctl.scala 2265:59] + node _T_1634 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2265:89] + node _T_1635 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2266:34] + node _T_1636 = bits(_T_1635, 0, 0) @[dec_tlu_ctl.scala 2266:59] + node _T_1637 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2266:89] + node _T_1638 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2267:34] + node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2267:59] + node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2267:89] + node _T_1641 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2268:34] + node _T_1642 = bits(_T_1641, 0, 0) @[dec_tlu_ctl.scala 2268:59] + node _T_1643 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2268:89] + node _T_1644 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2269:34] + node _T_1645 = bits(_T_1644, 0, 0) @[dec_tlu_ctl.scala 2269:59] + node _T_1646 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2269:89] + node _T_1647 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2270:34] + node _T_1648 = bits(_T_1647, 0, 0) @[dec_tlu_ctl.scala 2270:59] + node _T_1649 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2270:89] + node _T_1650 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2271:34] + node _T_1651 = bits(_T_1650, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1652 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2271:89] + node _T_1653 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2272:34] + node _T_1654 = bits(_T_1653, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1655 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2272:89] + node _T_1656 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2273:34] + node _T_1657 = bits(_T_1656, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1658 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2273:89] + node _T_1659 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2274:34] + node _T_1660 = bits(_T_1659, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1661 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2274:89] + node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2274:122] + node _T_1663 = or(_T_1661, _T_1662) @[dec_tlu_ctl.scala 2274:101] + node _T_1664 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2275:34] + node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1666 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2275:95] + node _T_1667 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2276:34] + node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1669 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2276:97] + node _T_1670 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2277:34] + node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1672 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2277:110] + node _T_1673 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2278:34] + node _T_1674 = bits(_T_1673, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1675 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2279:34] + node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2280:34] + node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1679 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2281:34] + node _T_1680 = bits(_T_1679, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1681 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2282:34] + node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1683 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2283:34] + node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1685 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2284:34] + node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1687 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2285:34] + node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1689 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2285:98] + node _T_1690 = or(_T_1689, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2285:120] + node _T_1691 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2286:34] + node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1693 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2286:92] + node _T_1694 = or(_T_1693, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2286:117] + node _T_1695 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2287:34] + node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1697 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2288:34] + node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1699 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2289:34] + node _T_1700 = bits(_T_1699, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1701 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2289:97] + node _T_1702 = and(_T_1701, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2289:129] + node _T_1703 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2290:34] + node _T_1704 = bits(_T_1703, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1705 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2291:34] + node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1707 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2292:34] + node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1709 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2293:34] + node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1711 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2294:34] + node _T_1712 = bits(_T_1711, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2295:34] + node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1715 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2296:34] + node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_1717 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2297:34] + node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_1719 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2297:84] + node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2297:84] + node _T_1721 = not(_T_1720) @[dec_tlu_ctl.scala 2297:73] + node _T_1722 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2298:34] + node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_1724 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2298:84] + node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2298:84] + node _T_1726 = not(_T_1725) @[dec_tlu_ctl.scala 2298:73] + node _T_1727 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2298:107] + node _T_1728 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2298:118] + node _T_1729 = and(_T_1727, _T_1728) @[dec_tlu_ctl.scala 2298:113] + node _T_1730 = orr(_T_1729) @[dec_tlu_ctl.scala 2298:125] + node _T_1731 = and(_T_1726, _T_1730) @[dec_tlu_ctl.scala 2298:98] + node _T_1732 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2299:34] + node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1734 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2299:91] + node _T_1735 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2300:34] + node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1737 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2300:94] + node _T_1738 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2301:34] + node _T_1739 = bits(_T_1738, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1740 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2301:94] + node _T_1741 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2303:34] + node _T_1742 = bits(_T_1741, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1743 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2304:34] + node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1745 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2305:34] + node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1747 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2306:34] + node _T_1748 = bits(_T_1747, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2307:34] + node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2307:62] node _T_1751 = mux(_T_1585, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1752 = mux(_T_1587, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1753 = mux(_T_1589, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] @@ -75259,177 +75259,177 @@ circuit quasar_wrapper : node _T_1863 = or(_T_1862, _T_1807) @[Mux.scala 27:72] wire _T_1864 : UInt<1> @[Mux.scala 27:72] _T_1864 <= _T_1863 @[Mux.scala 27:72] - node _T_1865 = and(_T_1583, _T_1864) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[2] <= _T_1865 @[dec_tlu_ctl.scala 2255:19] - node _T_1866 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2255:38] - node _T_1867 = not(_T_1866) @[dec_tlu_ctl.scala 2255:24] - node _T_1868 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2256:34] - node _T_1869 = bits(_T_1868, 0, 0) @[dec_tlu_ctl.scala 2256:62] - node _T_1870 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2257:34] - node _T_1871 = bits(_T_1870, 0, 0) @[dec_tlu_ctl.scala 2257:62] - node _T_1872 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2258:34] - node _T_1873 = bits(_T_1872, 0, 0) @[dec_tlu_ctl.scala 2258:62] - node _T_1874 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2259:34] - node _T_1875 = bits(_T_1874, 0, 0) @[dec_tlu_ctl.scala 2259:62] - node _T_1876 = not(io.illegal_r) @[dec_tlu_ctl.scala 2259:96] - node _T_1877 = and(io.tlu_i0_commit_cmt, _T_1876) @[dec_tlu_ctl.scala 2259:94] - node _T_1878 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2260:34] - node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2260:62] - node _T_1880 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2260:96] - node _T_1881 = and(io.tlu_i0_commit_cmt, _T_1880) @[dec_tlu_ctl.scala 2260:94] - node _T_1882 = not(io.illegal_r) @[dec_tlu_ctl.scala 2260:117] - node _T_1883 = and(_T_1881, _T_1882) @[dec_tlu_ctl.scala 2260:115] - node _T_1884 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2261:34] - node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2261:62] - node _T_1886 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2261:94] - node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2261:117] - node _T_1888 = and(_T_1886, _T_1887) @[dec_tlu_ctl.scala 2261:115] - node _T_1889 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2262:34] - node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2262:62] - node _T_1891 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2263:34] - node _T_1892 = bits(_T_1891, 0, 0) @[dec_tlu_ctl.scala 2263:62] - node _T_1893 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2264:34] - node _T_1894 = bits(_T_1893, 0, 0) @[dec_tlu_ctl.scala 2264:62] - node _T_1895 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2265:34] - node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2265:62] - node _T_1897 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2265:91] - node _T_1898 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2266:34] - node _T_1899 = bits(_T_1898, 0, 0) @[dec_tlu_ctl.scala 2266:62] - node _T_1900 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2266:105] - node _T_1901 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2267:34] - node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2267:62] - node _T_1903 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2267:91] - node _T_1904 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2268:34] - node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2268:62] - node _T_1906 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2268:91] - node _T_1907 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2269:34] - node _T_1908 = bits(_T_1907, 0, 0) @[dec_tlu_ctl.scala 2269:62] - node _T_1909 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2269:91] - node _T_1910 = and(_T_1909, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2269:100] - node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2270:34] - node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2270:62] - node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2270:91] - node _T_1914 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2270:142] - node _T_1915 = and(_T_1913, _T_1914) @[dec_tlu_ctl.scala 2270:101] - node _T_1916 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2271:34] - node _T_1917 = bits(_T_1916, 0, 0) @[dec_tlu_ctl.scala 2271:59] - node _T_1918 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2271:89] - node _T_1919 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2272:34] - node _T_1920 = bits(_T_1919, 0, 0) @[dec_tlu_ctl.scala 2272:59] - node _T_1921 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2272:89] - node _T_1922 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2273:34] - node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2273:59] - node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2273:89] - node _T_1925 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2274:34] - node _T_1926 = bits(_T_1925, 0, 0) @[dec_tlu_ctl.scala 2274:59] - node _T_1927 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2274:89] - node _T_1928 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2275:34] - node _T_1929 = bits(_T_1928, 0, 0) @[dec_tlu_ctl.scala 2275:59] - node _T_1930 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2275:89] - node _T_1931 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2276:34] - node _T_1932 = bits(_T_1931, 0, 0) @[dec_tlu_ctl.scala 2276:59] - node _T_1933 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2276:89] - node _T_1934 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2277:34] - node _T_1935 = bits(_T_1934, 0, 0) @[dec_tlu_ctl.scala 2277:59] - node _T_1936 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2277:89] - node _T_1937 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2278:34] - node _T_1938 = bits(_T_1937, 0, 0) @[dec_tlu_ctl.scala 2278:59] - node _T_1939 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2278:89] - node _T_1940 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2279:34] - node _T_1941 = bits(_T_1940, 0, 0) @[dec_tlu_ctl.scala 2279:59] - node _T_1942 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2279:89] - node _T_1943 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2280:34] - node _T_1944 = bits(_T_1943, 0, 0) @[dec_tlu_ctl.scala 2280:59] - node _T_1945 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2280:89] - node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2280:122] - node _T_1947 = or(_T_1945, _T_1946) @[dec_tlu_ctl.scala 2280:101] - node _T_1948 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2281:34] - node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1950 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2281:95] - node _T_1951 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2282:34] - node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1953 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2282:97] - node _T_1954 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2283:34] - node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1956 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:110] - node _T_1957 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2284:34] - node _T_1958 = bits(_T_1957, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2285:34] - node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2286:34] - node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1963 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2287:34] - node _T_1964 = bits(_T_1963, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1965 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2288:34] - node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1967 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2289:34] - node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1969 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2290:34] - node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1971 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2291:34] - node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1973 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2291:98] - node _T_1974 = or(_T_1973, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2291:120] - node _T_1975 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2292:34] - node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1977 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2292:92] - node _T_1978 = or(_T_1977, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2292:117] - node _T_1979 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2293:34] - node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1981 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2294:34] - node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2294:62] - node _T_1983 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2295:34] - node _T_1984 = bits(_T_1983, 0, 0) @[dec_tlu_ctl.scala 2295:62] - node _T_1985 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2295:97] - node _T_1986 = and(_T_1985, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2295:129] - node _T_1987 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2296:34] - node _T_1988 = bits(_T_1987, 0, 0) @[dec_tlu_ctl.scala 2296:62] - node _T_1989 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2297:34] - node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2297:62] - node _T_1991 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2298:34] - node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1993 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2299:34] - node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2300:34] - node _T_1996 = bits(_T_1995, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2301:34] - node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1999 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2302:34] - node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_2001 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2303:34] - node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_2003 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2303:84] - node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2303:84] - node _T_2005 = not(_T_2004) @[dec_tlu_ctl.scala 2303:73] - node _T_2006 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2304:34] - node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_2008 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2304:84] - node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2304:84] - node _T_2010 = not(_T_2009) @[dec_tlu_ctl.scala 2304:73] - node _T_2011 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2304:107] - node _T_2012 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2304:118] - node _T_2013 = and(_T_2011, _T_2012) @[dec_tlu_ctl.scala 2304:113] - node _T_2014 = orr(_T_2013) @[dec_tlu_ctl.scala 2304:125] - node _T_2015 = and(_T_2010, _T_2014) @[dec_tlu_ctl.scala 2304:98] - node _T_2016 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2305:34] - node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_2018 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2305:91] - node _T_2019 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2306:34] - node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_2021 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2306:94] - node _T_2022 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2307:34] - node _T_2023 = bits(_T_2022, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_2024 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2307:94] - node _T_2025 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2309:34] - node _T_2026 = bits(_T_2025, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_2027 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2310:34] - node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_2029 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2311:34] - node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_2031 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2312:34] - node _T_2032 = bits(_T_2031, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_2033 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2313:34] - node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1865 = and(_T_1583, _T_1864) @[dec_tlu_ctl.scala 2249:44] + mhpmc_inc_r[2] <= _T_1865 @[dec_tlu_ctl.scala 2249:19] + node _T_1866 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2249:38] + node _T_1867 = not(_T_1866) @[dec_tlu_ctl.scala 2249:24] + node _T_1868 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2250:34] + node _T_1869 = bits(_T_1868, 0, 0) @[dec_tlu_ctl.scala 2250:62] + node _T_1870 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2251:34] + node _T_1871 = bits(_T_1870, 0, 0) @[dec_tlu_ctl.scala 2251:62] + node _T_1872 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2252:34] + node _T_1873 = bits(_T_1872, 0, 0) @[dec_tlu_ctl.scala 2252:62] + node _T_1874 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2253:34] + node _T_1875 = bits(_T_1874, 0, 0) @[dec_tlu_ctl.scala 2253:62] + node _T_1876 = not(io.illegal_r) @[dec_tlu_ctl.scala 2253:96] + node _T_1877 = and(io.tlu_i0_commit_cmt, _T_1876) @[dec_tlu_ctl.scala 2253:94] + node _T_1878 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2254:34] + node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2254:62] + node _T_1880 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2254:96] + node _T_1881 = and(io.tlu_i0_commit_cmt, _T_1880) @[dec_tlu_ctl.scala 2254:94] + node _T_1882 = not(io.illegal_r) @[dec_tlu_ctl.scala 2254:117] + node _T_1883 = and(_T_1881, _T_1882) @[dec_tlu_ctl.scala 2254:115] + node _T_1884 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2255:34] + node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2255:62] + node _T_1886 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2255:94] + node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2255:117] + node _T_1888 = and(_T_1886, _T_1887) @[dec_tlu_ctl.scala 2255:115] + node _T_1889 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2256:34] + node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2256:62] + node _T_1891 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2257:34] + node _T_1892 = bits(_T_1891, 0, 0) @[dec_tlu_ctl.scala 2257:62] + node _T_1893 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2258:34] + node _T_1894 = bits(_T_1893, 0, 0) @[dec_tlu_ctl.scala 2258:62] + node _T_1895 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2259:34] + node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2259:62] + node _T_1897 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2259:91] + node _T_1898 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2260:34] + node _T_1899 = bits(_T_1898, 0, 0) @[dec_tlu_ctl.scala 2260:62] + node _T_1900 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2260:105] + node _T_1901 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2261:34] + node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2261:62] + node _T_1903 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2261:91] + node _T_1904 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2262:34] + node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2262:62] + node _T_1906 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2262:91] + node _T_1907 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2263:34] + node _T_1908 = bits(_T_1907, 0, 0) @[dec_tlu_ctl.scala 2263:62] + node _T_1909 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2263:91] + node _T_1910 = and(_T_1909, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2263:100] + node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2264:34] + node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2264:62] + node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2264:91] + node _T_1914 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2264:142] + node _T_1915 = and(_T_1913, _T_1914) @[dec_tlu_ctl.scala 2264:101] + node _T_1916 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2265:34] + node _T_1917 = bits(_T_1916, 0, 0) @[dec_tlu_ctl.scala 2265:59] + node _T_1918 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2265:89] + node _T_1919 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2266:34] + node _T_1920 = bits(_T_1919, 0, 0) @[dec_tlu_ctl.scala 2266:59] + node _T_1921 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2266:89] + node _T_1922 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2267:34] + node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2267:59] + node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2267:89] + node _T_1925 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2268:34] + node _T_1926 = bits(_T_1925, 0, 0) @[dec_tlu_ctl.scala 2268:59] + node _T_1927 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2268:89] + node _T_1928 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2269:34] + node _T_1929 = bits(_T_1928, 0, 0) @[dec_tlu_ctl.scala 2269:59] + node _T_1930 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2269:89] + node _T_1931 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2270:34] + node _T_1932 = bits(_T_1931, 0, 0) @[dec_tlu_ctl.scala 2270:59] + node _T_1933 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2270:89] + node _T_1934 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2271:34] + node _T_1935 = bits(_T_1934, 0, 0) @[dec_tlu_ctl.scala 2271:59] + node _T_1936 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2271:89] + node _T_1937 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2272:34] + node _T_1938 = bits(_T_1937, 0, 0) @[dec_tlu_ctl.scala 2272:59] + node _T_1939 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2272:89] + node _T_1940 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2273:34] + node _T_1941 = bits(_T_1940, 0, 0) @[dec_tlu_ctl.scala 2273:59] + node _T_1942 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2273:89] + node _T_1943 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2274:34] + node _T_1944 = bits(_T_1943, 0, 0) @[dec_tlu_ctl.scala 2274:59] + node _T_1945 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2274:89] + node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2274:122] + node _T_1947 = or(_T_1945, _T_1946) @[dec_tlu_ctl.scala 2274:101] + node _T_1948 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2275:34] + node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1950 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2275:95] + node _T_1951 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2276:34] + node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1953 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2276:97] + node _T_1954 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2277:34] + node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1956 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2277:110] + node _T_1957 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2278:34] + node _T_1958 = bits(_T_1957, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2279:34] + node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2280:34] + node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1963 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2281:34] + node _T_1964 = bits(_T_1963, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1965 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2282:34] + node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1967 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2283:34] + node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1969 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2284:34] + node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1971 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2285:34] + node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1973 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2285:98] + node _T_1974 = or(_T_1973, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2285:120] + node _T_1975 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2286:34] + node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1977 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2286:92] + node _T_1978 = or(_T_1977, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2286:117] + node _T_1979 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2287:34] + node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1981 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2288:34] + node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1983 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2289:34] + node _T_1984 = bits(_T_1983, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1985 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2289:97] + node _T_1986 = and(_T_1985, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2289:129] + node _T_1987 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2290:34] + node _T_1988 = bits(_T_1987, 0, 0) @[dec_tlu_ctl.scala 2290:62] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2291:34] + node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2291:62] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2292:34] + node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2292:62] + node _T_1993 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2293:34] + node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2293:62] + node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2294:34] + node _T_1996 = bits(_T_1995, 0, 0) @[dec_tlu_ctl.scala 2294:62] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2295:34] + node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2295:62] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2296:34] + node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2296:62] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2297:34] + node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2297:62] + node _T_2003 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2297:84] + node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2297:84] + node _T_2005 = not(_T_2004) @[dec_tlu_ctl.scala 2297:73] + node _T_2006 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2298:34] + node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2298:62] + node _T_2008 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2298:84] + node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2298:84] + node _T_2010 = not(_T_2009) @[dec_tlu_ctl.scala 2298:73] + node _T_2011 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2298:107] + node _T_2012 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2298:118] + node _T_2013 = and(_T_2011, _T_2012) @[dec_tlu_ctl.scala 2298:113] + node _T_2014 = orr(_T_2013) @[dec_tlu_ctl.scala 2298:125] + node _T_2015 = and(_T_2010, _T_2014) @[dec_tlu_ctl.scala 2298:98] + node _T_2016 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2299:34] + node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_2018 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2299:91] + node _T_2019 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2300:34] + node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_2021 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2300:94] + node _T_2022 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2301:34] + node _T_2023 = bits(_T_2022, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_2024 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2301:94] + node _T_2025 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2303:34] + node _T_2026 = bits(_T_2025, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_2027 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2304:34] + node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_2029 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2305:34] + node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_2031 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2306:34] + node _T_2032 = bits(_T_2031, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_2033 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2307:34] + node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2307:62] node _T_2035 = mux(_T_1869, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2036 = mux(_T_1871, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2037 = mux(_T_1873, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] @@ -75545,83 +75545,83 @@ circuit quasar_wrapper : node _T_2147 = or(_T_2146, _T_2091) @[Mux.scala 27:72] wire _T_2148 : UInt<1> @[Mux.scala 27:72] _T_2148 <= _T_2147 @[Mux.scala 27:72] - node _T_2149 = and(_T_1867, _T_2148) @[dec_tlu_ctl.scala 2255:44] - mhpmc_inc_r[3] <= _T_2149 @[dec_tlu_ctl.scala 2255:19] - reg _T_2150 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2316:53] - _T_2150 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2316:53] - mhpmc_inc_r_d1[0] <= _T_2150 @[dec_tlu_ctl.scala 2316:20] - reg _T_2151 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2317:53] - _T_2151 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2317:53] - mhpmc_inc_r_d1[1] <= _T_2151 @[dec_tlu_ctl.scala 2317:20] - reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2318:53] - _T_2152 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2318:53] - mhpmc_inc_r_d1[2] <= _T_2152 @[dec_tlu_ctl.scala 2318:20] - reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2319:53] - _T_2153 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2319:53] - mhpmc_inc_r_d1[3] <= _T_2153 @[dec_tlu_ctl.scala 2319:20] - reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2320:56] - perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2320:56] - node _T_2154 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2323:53] - node _T_2155 = and(io.dec_tlu_dbg_halted, _T_2154) @[dec_tlu_ctl.scala 2323:44] - node _T_2156 = or(_T_2155, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2323:67] - perfcnt_halted <= _T_2156 @[dec_tlu_ctl.scala 2323:17] - node _T_2157 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2324:70] - node _T_2158 = and(io.dec_tlu_dbg_halted, _T_2157) @[dec_tlu_ctl.scala 2324:61] - node _T_2159 = not(_T_2158) @[dec_tlu_ctl.scala 2324:37] + node _T_2149 = and(_T_1867, _T_2148) @[dec_tlu_ctl.scala 2249:44] + mhpmc_inc_r[3] <= _T_2149 @[dec_tlu_ctl.scala 2249:19] + reg _T_2150 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2310:53] + _T_2150 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2310:53] + mhpmc_inc_r_d1[0] <= _T_2150 @[dec_tlu_ctl.scala 2310:20] + reg _T_2151 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2311:53] + _T_2151 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2311:53] + mhpmc_inc_r_d1[1] <= _T_2151 @[dec_tlu_ctl.scala 2311:20] + reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2312:53] + _T_2152 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2312:53] + mhpmc_inc_r_d1[2] <= _T_2152 @[dec_tlu_ctl.scala 2312:20] + reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2313:53] + _T_2153 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2313:53] + mhpmc_inc_r_d1[3] <= _T_2153 @[dec_tlu_ctl.scala 2313:20] + reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2314:56] + perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2314:56] + node _T_2154 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2317:53] + node _T_2155 = and(io.dec_tlu_dbg_halted, _T_2154) @[dec_tlu_ctl.scala 2317:44] + node _T_2156 = or(_T_2155, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2317:67] + perfcnt_halted <= _T_2156 @[dec_tlu_ctl.scala 2317:17] + node _T_2157 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2318:70] + node _T_2158 = and(io.dec_tlu_dbg_halted, _T_2157) @[dec_tlu_ctl.scala 2318:61] + node _T_2159 = not(_T_2158) @[dec_tlu_ctl.scala 2318:37] node _T_2160 = bits(_T_2159, 0, 0) @[Bitwise.scala 72:15] node _T_2161 = mux(_T_2160, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2162 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2324:104] - node _T_2163 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2324:120] - node _T_2164 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2324:136] - node _T_2165 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2324:152] + node _T_2162 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2318:104] + node _T_2163 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2318:120] + node _T_2164 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2318:136] + node _T_2165 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2318:152] node _T_2166 = cat(_T_2164, _T_2165) @[Cat.scala 29:58] node _T_2167 = cat(_T_2162, _T_2163) @[Cat.scala 29:58] node _T_2168 = cat(_T_2167, _T_2166) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2161, _T_2168) @[dec_tlu_ctl.scala 2324:86] - node _T_2169 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2326:88] - node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2326:67] - node _T_2171 = and(perfcnt_halted_d1, _T_2170) @[dec_tlu_ctl.scala 2326:65] - node _T_2172 = not(_T_2171) @[dec_tlu_ctl.scala 2326:45] - node _T_2173 = and(mhpmc_inc_r_d1[0], _T_2172) @[dec_tlu_ctl.scala 2326:43] - io.dec_tlu_perfcnt0 <= _T_2173 @[dec_tlu_ctl.scala 2326:22] - node _T_2174 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2327:88] - node _T_2175 = not(_T_2174) @[dec_tlu_ctl.scala 2327:67] - node _T_2176 = and(perfcnt_halted_d1, _T_2175) @[dec_tlu_ctl.scala 2327:65] - node _T_2177 = not(_T_2176) @[dec_tlu_ctl.scala 2327:45] - node _T_2178 = and(mhpmc_inc_r_d1[1], _T_2177) @[dec_tlu_ctl.scala 2327:43] - io.dec_tlu_perfcnt1 <= _T_2178 @[dec_tlu_ctl.scala 2327:22] - node _T_2179 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2328:88] - node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2328:67] - node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2328:65] - node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2328:45] - node _T_2183 = and(mhpmc_inc_r_d1[2], _T_2182) @[dec_tlu_ctl.scala 2328:43] - io.dec_tlu_perfcnt2 <= _T_2183 @[dec_tlu_ctl.scala 2328:22] - node _T_2184 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2329:88] - node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2329:67] - node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2329:65] - node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2329:45] - node _T_2188 = and(mhpmc_inc_r_d1[3], _T_2187) @[dec_tlu_ctl.scala 2329:43] - io.dec_tlu_perfcnt3 <= _T_2188 @[dec_tlu_ctl.scala 2329:22] - node _T_2189 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2335:65] - node _T_2190 = eq(_T_2189, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2335:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2190) @[dec_tlu_ctl.scala 2335:43] - node _T_2191 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2336:23] - node _T_2192 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2336:61] - node _T_2193 = or(_T_2191, _T_2192) @[dec_tlu_ctl.scala 2336:39] - node _T_2194 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2336:86] - node mhpmc3_wr_en1 = and(_T_2193, _T_2194) @[dec_tlu_ctl.scala 2336:66] - node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2337:36] - node _T_2195 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2340:28] - node _T_2196 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2340:41] + node perfcnt_during_sleep = and(_T_2161, _T_2168) @[dec_tlu_ctl.scala 2318:86] + node _T_2169 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2320:88] + node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2320:67] + node _T_2171 = and(perfcnt_halted_d1, _T_2170) @[dec_tlu_ctl.scala 2320:65] + node _T_2172 = not(_T_2171) @[dec_tlu_ctl.scala 2320:45] + node _T_2173 = and(mhpmc_inc_r_d1[0], _T_2172) @[dec_tlu_ctl.scala 2320:43] + io.dec_tlu_perfcnt0 <= _T_2173 @[dec_tlu_ctl.scala 2320:22] + node _T_2174 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2321:88] + node _T_2175 = not(_T_2174) @[dec_tlu_ctl.scala 2321:67] + node _T_2176 = and(perfcnt_halted_d1, _T_2175) @[dec_tlu_ctl.scala 2321:65] + node _T_2177 = not(_T_2176) @[dec_tlu_ctl.scala 2321:45] + node _T_2178 = and(mhpmc_inc_r_d1[1], _T_2177) @[dec_tlu_ctl.scala 2321:43] + io.dec_tlu_perfcnt1 <= _T_2178 @[dec_tlu_ctl.scala 2321:22] + node _T_2179 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2322:88] + node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2322:67] + node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2322:65] + node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2322:45] + node _T_2183 = and(mhpmc_inc_r_d1[2], _T_2182) @[dec_tlu_ctl.scala 2322:43] + io.dec_tlu_perfcnt2 <= _T_2183 @[dec_tlu_ctl.scala 2322:22] + node _T_2184 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2323:88] + node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2323:67] + node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2323:65] + node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2323:45] + node _T_2188 = and(mhpmc_inc_r_d1[3], _T_2187) @[dec_tlu_ctl.scala 2323:43] + io.dec_tlu_perfcnt3 <= _T_2188 @[dec_tlu_ctl.scala 2323:22] + node _T_2189 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2329:65] + node _T_2190 = eq(_T_2189, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2329:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2190) @[dec_tlu_ctl.scala 2329:43] + node _T_2191 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2330:23] + node _T_2192 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2330:61] + node _T_2193 = or(_T_2191, _T_2192) @[dec_tlu_ctl.scala 2330:39] + node _T_2194 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2330:86] + node mhpmc3_wr_en1 = and(_T_2193, _T_2194) @[dec_tlu_ctl.scala 2330:66] + node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2331:36] + node _T_2195 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2334:28] + node _T_2196 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2334:41] node _T_2197 = cat(_T_2195, _T_2196) @[Cat.scala 29:58] node _T_2198 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2199 = add(_T_2197, _T_2198) @[dec_tlu_ctl.scala 2340:49] - node _T_2200 = tail(_T_2199, 1) @[dec_tlu_ctl.scala 2340:49] - mhpmc3_incr <= _T_2200 @[dec_tlu_ctl.scala 2340:14] - node _T_2201 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2341:36] - node _T_2202 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2341:76] - node mhpmc3_ns = mux(_T_2201, io.dec_csr_wrdata_r, _T_2202) @[dec_tlu_ctl.scala 2341:21] - node _T_2203 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2343:42] + node _T_2199 = add(_T_2197, _T_2198) @[dec_tlu_ctl.scala 2334:49] + node _T_2200 = tail(_T_2199, 1) @[dec_tlu_ctl.scala 2334:49] + mhpmc3_incr <= _T_2200 @[dec_tlu_ctl.scala 2334:14] + node _T_2201 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2335:36] + node _T_2202 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2335:76] + node mhpmc3_ns = mux(_T_2201, io.dec_csr_wrdata_r, _T_2202) @[dec_tlu_ctl.scala 2335:21] + node _T_2203 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2337:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset @@ -75630,15 +75630,15 @@ circuit quasar_wrapper : rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_2204 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_2204 <= mhpmc3_ns @[lib.scala 374:16] - mhpmc3 <= _T_2204 @[dec_tlu_ctl.scala 2343:9] - node _T_2205 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2345:66] - node _T_2206 = eq(_T_2205, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2345:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2206) @[dec_tlu_ctl.scala 2345:44] - node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2346:38] - node _T_2207 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2347:38] - node _T_2208 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2347:78] - node mhpmc3h_ns = mux(_T_2207, io.dec_csr_wrdata_r, _T_2208) @[dec_tlu_ctl.scala 2347:22] - node _T_2209 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2349:46] + mhpmc3 <= _T_2204 @[dec_tlu_ctl.scala 2337:9] + node _T_2205 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2339:66] + node _T_2206 = eq(_T_2205, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2339:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2206) @[dec_tlu_ctl.scala 2339:44] + node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2340:38] + node _T_2207 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2341:38] + node _T_2208 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2341:78] + node mhpmc3h_ns = mux(_T_2207, io.dec_csr_wrdata_r, _T_2208) @[dec_tlu_ctl.scala 2341:22] + node _T_2209 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2343:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset @@ -75647,28 +75647,28 @@ circuit quasar_wrapper : rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_2210 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_2210 <= mhpmc3h_ns @[lib.scala 374:16] - mhpmc3h <= _T_2210 @[dec_tlu_ctl.scala 2349:10] - node _T_2211 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] - node _T_2212 = eq(_T_2211, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2354:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2212) @[dec_tlu_ctl.scala 2354:43] - node _T_2213 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] - node _T_2214 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2355:61] - node _T_2215 = or(_T_2213, _T_2214) @[dec_tlu_ctl.scala 2355:39] - node _T_2216 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2355:86] - node mhpmc4_wr_en1 = and(_T_2215, _T_2216) @[dec_tlu_ctl.scala 2355:66] - node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2356:36] - node _T_2217 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2360:28] - node _T_2218 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2360:41] + mhpmc3h <= _T_2210 @[dec_tlu_ctl.scala 2343:10] + node _T_2211 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2348:65] + node _T_2212 = eq(_T_2211, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2348:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2212) @[dec_tlu_ctl.scala 2348:43] + node _T_2213 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2349:23] + node _T_2214 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2349:61] + node _T_2215 = or(_T_2213, _T_2214) @[dec_tlu_ctl.scala 2349:39] + node _T_2216 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2349:86] + node mhpmc4_wr_en1 = and(_T_2215, _T_2216) @[dec_tlu_ctl.scala 2349:66] + node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2350:36] + node _T_2217 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2354:28] + node _T_2218 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2354:41] node _T_2219 = cat(_T_2217, _T_2218) @[Cat.scala 29:58] node _T_2220 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2221 = add(_T_2219, _T_2220) @[dec_tlu_ctl.scala 2360:49] - node _T_2222 = tail(_T_2221, 1) @[dec_tlu_ctl.scala 2360:49] - mhpmc4_incr <= _T_2222 @[dec_tlu_ctl.scala 2360:14] - node _T_2223 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2361:36] - node _T_2224 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2361:63] - node _T_2225 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2361:82] - node mhpmc4_ns = mux(_T_2223, _T_2224, _T_2225) @[dec_tlu_ctl.scala 2361:21] - node _T_2226 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:43] + node _T_2221 = add(_T_2219, _T_2220) @[dec_tlu_ctl.scala 2354:49] + node _T_2222 = tail(_T_2221, 1) @[dec_tlu_ctl.scala 2354:49] + mhpmc4_incr <= _T_2222 @[dec_tlu_ctl.scala 2354:14] + node _T_2223 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2355:36] + node _T_2224 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2355:63] + node _T_2225 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2355:82] + node mhpmc4_ns = mux(_T_2223, _T_2224, _T_2225) @[dec_tlu_ctl.scala 2355:21] + node _T_2226 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2356:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset @@ -75677,15 +75677,15 @@ circuit quasar_wrapper : rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_2227 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_2227 <= mhpmc4_ns @[lib.scala 374:16] - mhpmc4 <= _T_2227 @[dec_tlu_ctl.scala 2362:9] - node _T_2228 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] - node _T_2229 = eq(_T_2228, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2364:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2229) @[dec_tlu_ctl.scala 2364:44] - node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2365:38] - node _T_2230 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] - node _T_2231 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] - node mhpmc4h_ns = mux(_T_2230, io.dec_csr_wrdata_r, _T_2231) @[dec_tlu_ctl.scala 2366:22] - node _T_2232 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] + mhpmc4 <= _T_2227 @[dec_tlu_ctl.scala 2356:9] + node _T_2228 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2358:66] + node _T_2229 = eq(_T_2228, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2358:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2229) @[dec_tlu_ctl.scala 2358:44] + node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2359:38] + node _T_2230 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2360:38] + node _T_2231 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2360:78] + node mhpmc4h_ns = mux(_T_2230, io.dec_csr_wrdata_r, _T_2231) @[dec_tlu_ctl.scala 2360:22] + node _T_2232 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2361:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset @@ -75694,27 +75694,27 @@ circuit quasar_wrapper : rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_2233 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_2233 <= mhpmc4h_ns @[lib.scala 374:16] - mhpmc4h <= _T_2233 @[dec_tlu_ctl.scala 2367:10] - node _T_2234 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] - node _T_2235 = eq(_T_2234, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2373:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2235) @[dec_tlu_ctl.scala 2373:43] - node _T_2236 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] - node _T_2237 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2374:61] - node _T_2238 = or(_T_2236, _T_2237) @[dec_tlu_ctl.scala 2374:39] - node _T_2239 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2374:86] - node mhpmc5_wr_en1 = and(_T_2238, _T_2239) @[dec_tlu_ctl.scala 2374:66] - node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2375:36] - node _T_2240 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2377:28] - node _T_2241 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2377:41] + mhpmc4h <= _T_2233 @[dec_tlu_ctl.scala 2361:10] + node _T_2234 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2367:65] + node _T_2235 = eq(_T_2234, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2367:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2235) @[dec_tlu_ctl.scala 2367:43] + node _T_2236 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2368:23] + node _T_2237 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2368:61] + node _T_2238 = or(_T_2236, _T_2237) @[dec_tlu_ctl.scala 2368:39] + node _T_2239 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2368:86] + node mhpmc5_wr_en1 = and(_T_2238, _T_2239) @[dec_tlu_ctl.scala 2368:66] + node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2369:36] + node _T_2240 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2371:28] + node _T_2241 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2371:41] node _T_2242 = cat(_T_2240, _T_2241) @[Cat.scala 29:58] node _T_2243 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2244 = add(_T_2242, _T_2243) @[dec_tlu_ctl.scala 2377:49] - node _T_2245 = tail(_T_2244, 1) @[dec_tlu_ctl.scala 2377:49] - mhpmc5_incr <= _T_2245 @[dec_tlu_ctl.scala 2377:14] - node _T_2246 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2378:36] - node _T_2247 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2378:76] - node mhpmc5_ns = mux(_T_2246, io.dec_csr_wrdata_r, _T_2247) @[dec_tlu_ctl.scala 2378:21] - node _T_2248 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] + node _T_2244 = add(_T_2242, _T_2243) @[dec_tlu_ctl.scala 2371:49] + node _T_2245 = tail(_T_2244, 1) @[dec_tlu_ctl.scala 2371:49] + mhpmc5_incr <= _T_2245 @[dec_tlu_ctl.scala 2371:14] + node _T_2246 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2372:36] + node _T_2247 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2372:76] + node mhpmc5_ns = mux(_T_2246, io.dec_csr_wrdata_r, _T_2247) @[dec_tlu_ctl.scala 2372:21] + node _T_2248 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2374:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset @@ -75723,15 +75723,15 @@ circuit quasar_wrapper : rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_2249 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_2249 <= mhpmc5_ns @[lib.scala 374:16] - mhpmc5 <= _T_2249 @[dec_tlu_ctl.scala 2380:9] - node _T_2250 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] - node _T_2251 = eq(_T_2250, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2382:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2251) @[dec_tlu_ctl.scala 2382:44] - node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2383:38] - node _T_2252 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] - node _T_2253 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] - node mhpmc5h_ns = mux(_T_2252, io.dec_csr_wrdata_r, _T_2253) @[dec_tlu_ctl.scala 2384:22] - node _T_2254 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] + mhpmc5 <= _T_2249 @[dec_tlu_ctl.scala 2374:9] + node _T_2250 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2376:66] + node _T_2251 = eq(_T_2250, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2376:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2251) @[dec_tlu_ctl.scala 2376:44] + node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2377:38] + node _T_2252 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2378:38] + node _T_2253 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2378:78] + node mhpmc5h_ns = mux(_T_2252, io.dec_csr_wrdata_r, _T_2253) @[dec_tlu_ctl.scala 2378:22] + node _T_2254 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset @@ -75740,27 +75740,27 @@ circuit quasar_wrapper : rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_2255 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_2255 <= mhpmc5h_ns @[lib.scala 374:16] - mhpmc5h <= _T_2255 @[dec_tlu_ctl.scala 2386:10] - node _T_2256 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] - node _T_2257 = eq(_T_2256, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2391:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2257) @[dec_tlu_ctl.scala 2391:43] - node _T_2258 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] - node _T_2259 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2392:61] - node _T_2260 = or(_T_2258, _T_2259) @[dec_tlu_ctl.scala 2392:39] - node _T_2261 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2392:86] - node mhpmc6_wr_en1 = and(_T_2260, _T_2261) @[dec_tlu_ctl.scala 2392:66] - node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2393:36] - node _T_2262 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2395:28] - node _T_2263 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2395:41] + mhpmc5h <= _T_2255 @[dec_tlu_ctl.scala 2380:10] + node _T_2256 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2385:65] + node _T_2257 = eq(_T_2256, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2385:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2257) @[dec_tlu_ctl.scala 2385:43] + node _T_2258 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2386:23] + node _T_2259 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2386:61] + node _T_2260 = or(_T_2258, _T_2259) @[dec_tlu_ctl.scala 2386:39] + node _T_2261 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2386:86] + node mhpmc6_wr_en1 = and(_T_2260, _T_2261) @[dec_tlu_ctl.scala 2386:66] + node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2387:36] + node _T_2262 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2389:28] + node _T_2263 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2389:41] node _T_2264 = cat(_T_2262, _T_2263) @[Cat.scala 29:58] node _T_2265 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2266 = add(_T_2264, _T_2265) @[dec_tlu_ctl.scala 2395:49] - node _T_2267 = tail(_T_2266, 1) @[dec_tlu_ctl.scala 2395:49] - mhpmc6_incr <= _T_2267 @[dec_tlu_ctl.scala 2395:14] - node _T_2268 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] - node _T_2269 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] - node mhpmc6_ns = mux(_T_2268, io.dec_csr_wrdata_r, _T_2269) @[dec_tlu_ctl.scala 2396:21] - node _T_2270 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] + node _T_2266 = add(_T_2264, _T_2265) @[dec_tlu_ctl.scala 2389:49] + node _T_2267 = tail(_T_2266, 1) @[dec_tlu_ctl.scala 2389:49] + mhpmc6_incr <= _T_2267 @[dec_tlu_ctl.scala 2389:14] + node _T_2268 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2390:36] + node _T_2269 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2390:76] + node mhpmc6_ns = mux(_T_2268, io.dec_csr_wrdata_r, _T_2269) @[dec_tlu_ctl.scala 2390:21] + node _T_2270 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2392:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset @@ -75769,15 +75769,15 @@ circuit quasar_wrapper : rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_2271 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_2271 <= mhpmc6_ns @[lib.scala 374:16] - mhpmc6 <= _T_2271 @[dec_tlu_ctl.scala 2398:9] - node _T_2272 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] - node _T_2273 = eq(_T_2272, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2400:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2273) @[dec_tlu_ctl.scala 2400:44] - node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2401:38] - node _T_2274 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] - node _T_2275 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] - node mhpmc6h_ns = mux(_T_2274, io.dec_csr_wrdata_r, _T_2275) @[dec_tlu_ctl.scala 2402:22] - node _T_2276 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] + mhpmc6 <= _T_2271 @[dec_tlu_ctl.scala 2392:9] + node _T_2272 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2394:66] + node _T_2273 = eq(_T_2272, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2394:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2273) @[dec_tlu_ctl.scala 2394:44] + node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2395:38] + node _T_2274 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:38] + node _T_2275 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2396:78] + node mhpmc6h_ns = mux(_T_2274, io.dec_csr_wrdata_r, _T_2275) @[dec_tlu_ctl.scala 2396:22] + node _T_2276 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset @@ -75786,134 +75786,134 @@ circuit quasar_wrapper : rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_2277 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_2277 <= mhpmc6h_ns @[lib.scala 374:16] - mhpmc6h <= _T_2277 @[dec_tlu_ctl.scala 2404:10] - node _T_2278 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:50] - node _T_2279 = gt(_T_2278, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2411:56] - node _T_2280 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2411:93] - node _T_2281 = orr(_T_2280) @[dec_tlu_ctl.scala 2411:102] - node _T_2282 = or(_T_2279, _T_2281) @[dec_tlu_ctl.scala 2411:71] - node _T_2283 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2411:141] - node event_saturate_r = mux(_T_2282, UInt<10>("h0204"), _T_2283) @[dec_tlu_ctl.scala 2411:28] - node _T_2284 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2413:63] - node _T_2285 = eq(_T_2284, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2413:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2285) @[dec_tlu_ctl.scala 2413:41] - node _T_2286 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2415:80] + mhpmc6h <= _T_2277 @[dec_tlu_ctl.scala 2398:10] + node _T_2278 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2405:50] + node _T_2279 = gt(_T_2278, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2405:56] + node _T_2280 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2405:93] + node _T_2281 = orr(_T_2280) @[dec_tlu_ctl.scala 2405:102] + node _T_2282 = or(_T_2279, _T_2281) @[dec_tlu_ctl.scala 2405:71] + node _T_2283 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2405:141] + node event_saturate_r = mux(_T_2282, UInt<10>("h0204"), _T_2283) @[dec_tlu_ctl.scala 2405:28] + node _T_2284 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2407:63] + node _T_2285 = eq(_T_2284, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2407:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2285) @[dec_tlu_ctl.scala 2407:41] + node _T_2286 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2409:80] reg _T_2287 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2286 : @[Reg.scala 28:19] _T_2287 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2287 @[dec_tlu_ctl.scala 2415:9] - node _T_2288 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2420:63] - node _T_2289 = eq(_T_2288, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2420:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2289) @[dec_tlu_ctl.scala 2420:41] - node _T_2290 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2421:80] + mhpme3 <= _T_2287 @[dec_tlu_ctl.scala 2409:9] + node _T_2288 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2414:63] + node _T_2289 = eq(_T_2288, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2414:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2289) @[dec_tlu_ctl.scala 2414:41] + node _T_2290 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2415:80] reg _T_2291 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2290 : @[Reg.scala 28:19] _T_2291 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2291 @[dec_tlu_ctl.scala 2421:9] - node _T_2292 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2427:63] - node _T_2293 = eq(_T_2292, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2427:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2293) @[dec_tlu_ctl.scala 2427:41] - node _T_2294 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2428:80] + mhpme4 <= _T_2291 @[dec_tlu_ctl.scala 2415:9] + node _T_2292 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2421:63] + node _T_2293 = eq(_T_2292, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2421:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2293) @[dec_tlu_ctl.scala 2421:41] + node _T_2294 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2422:80] reg _T_2295 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2294 : @[Reg.scala 28:19] _T_2295 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2295 @[dec_tlu_ctl.scala 2428:9] - node _T_2296 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2434:63] - node _T_2297 = eq(_T_2296, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2434:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2297) @[dec_tlu_ctl.scala 2434:41] - node _T_2298 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2435:80] + mhpme5 <= _T_2295 @[dec_tlu_ctl.scala 2422:9] + node _T_2296 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2428:63] + node _T_2297 = eq(_T_2296, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2428:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2297) @[dec_tlu_ctl.scala 2428:41] + node _T_2298 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2429:80] reg _T_2299 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2298 : @[Reg.scala 28:19] _T_2299 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2299 @[dec_tlu_ctl.scala 2435:9] - node _T_2300 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2451:70] - node _T_2301 = eq(_T_2300, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2451:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2301) @[dec_tlu_ctl.scala 2451:48] - node _T_2302 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2453:54] + mhpme6 <= _T_2299 @[dec_tlu_ctl.scala 2429:9] + node _T_2300 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2445:70] + node _T_2301 = eq(_T_2300, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2445:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2301) @[dec_tlu_ctl.scala 2445:48] + node _T_2302 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2447:54] wire temp_ncount0 : UInt<1> temp_ncount0 <= _T_2302 - node _T_2303 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2454:54] + node _T_2303 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2448:54] wire temp_ncount1 : UInt<1> temp_ncount1 <= _T_2303 - node _T_2304 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2455:55] + node _T_2304 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2449:55] wire temp_ncount6_2 : UInt<5> temp_ncount6_2 <= _T_2304 - node _T_2305 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2456:74] - node _T_2306 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2456:103] + node _T_2305 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2450:74] + node _T_2306 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2450:103] reg _T_2307 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2306 : @[Reg.scala 28:19] _T_2307 <= _T_2305 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2307 @[dec_tlu_ctl.scala 2456:17] - node _T_2308 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2458:72] - node _T_2309 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2458:99] + temp_ncount6_2 <= _T_2307 @[dec_tlu_ctl.scala 2450:17] + node _T_2308 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2452:72] + node _T_2309 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2452:99] reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2309 : @[Reg.scala 28:19] _T_2310 <= _T_2308 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2310 @[dec_tlu_ctl.scala 2458:15] + temp_ncount0 <= _T_2310 @[dec_tlu_ctl.scala 2452:15] node _T_2311 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] node _T_2312 = cat(_T_2311, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2312 @[dec_tlu_ctl.scala 2459:16] - node _T_2313 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2466:51] - node _T_2314 = or(_T_2313, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2466:78] - node _T_2315 = or(_T_2314, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2466:104] - node _T_2316 = or(_T_2315, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2466:130] - node _T_2317 = or(_T_2316, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2467:32] - node _T_2318 = or(_T_2317, io.clk_override) @[dec_tlu_ctl.scala 2467:59] - node _T_2319 = bits(_T_2318, 0, 0) @[dec_tlu_ctl.scala 2467:78] + mcountinhibit <= _T_2312 @[dec_tlu_ctl.scala 2453:16] + node _T_2313 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2460:51] + node _T_2314 = or(_T_2313, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2460:78] + node _T_2315 = or(_T_2314, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2460:104] + node _T_2316 = or(_T_2315, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2460:130] + node _T_2317 = or(_T_2316, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2461:32] + node _T_2318 = or(_T_2317, io.clk_override) @[dec_tlu_ctl.scala 2461:59] + node _T_2319 = bits(_T_2318, 0, 0) @[dec_tlu_ctl.scala 2461:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] rvclkhdr_34.io.en <= _T_2319 @[lib.scala 345:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg _T_2320 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2469:62] - _T_2320 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2469:62] - io.dec_tlu_i0_valid_wb1 <= _T_2320 @[dec_tlu_ctl.scala 2469:30] - node _T_2321 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2470:91] - node _T_2322 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2470:137] - node _T_2323 = and(io.trigger_hit_r_d1, _T_2322) @[dec_tlu_ctl.scala 2470:135] - node _T_2324 = or(_T_2321, _T_2323) @[dec_tlu_ctl.scala 2470:112] - reg _T_2325 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2470:62] - _T_2325 <= _T_2324 @[dec_tlu_ctl.scala 2470:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2325 @[dec_tlu_ctl.scala 2470:30] - reg _T_2326 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2471:62] - _T_2326 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2471:62] - io.dec_tlu_exc_cause_wb1 <= _T_2326 @[dec_tlu_ctl.scala 2471:30] - reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2472:62] - _T_2327 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2472:62] - io.dec_tlu_int_valid_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2472:30] - io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2474:24] - node _T_2328 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2480:61] - node _T_2329 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2481:42] - node _T_2330 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2482:40] - node _T_2331 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2483:39] - node _T_2332 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2484:40] + reg _T_2320 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2463:62] + _T_2320 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2463:62] + io.dec_tlu_i0_valid_wb1 <= _T_2320 @[dec_tlu_ctl.scala 2463:30] + node _T_2321 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2464:91] + node _T_2322 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2464:137] + node _T_2323 = and(io.trigger_hit_r_d1, _T_2322) @[dec_tlu_ctl.scala 2464:135] + node _T_2324 = or(_T_2321, _T_2323) @[dec_tlu_ctl.scala 2464:112] + reg _T_2325 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2464:62] + _T_2325 <= _T_2324 @[dec_tlu_ctl.scala 2464:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2325 @[dec_tlu_ctl.scala 2464:30] + reg _T_2326 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2465:62] + _T_2326 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2465:62] + io.dec_tlu_exc_cause_wb1 <= _T_2326 @[dec_tlu_ctl.scala 2465:30] + reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2466:62] + _T_2327 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2466:62] + io.dec_tlu_int_valid_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2466:30] + io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2468:24] + node _T_2328 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2474:61] + node _T_2329 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2475:42] + node _T_2330 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2476:40] + node _T_2331 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2477:39] + node _T_2332 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2478:40] node _T_2333 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2334 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:40] - node _T_2335 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2485:103] - node _T_2336 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2485:128] + node _T_2334 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2479:40] + node _T_2335 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2479:103] + node _T_2336 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2479:128] node _T_2337 = cat(UInt<3>("h00"), _T_2336) @[Cat.scala 29:58] node _T_2338 = cat(_T_2337, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2339 = cat(UInt<3>("h00"), _T_2335) @[Cat.scala 29:58] node _T_2340 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] node _T_2341 = cat(_T_2340, _T_2339) @[Cat.scala 29:58] node _T_2342 = cat(_T_2341, _T_2338) @[Cat.scala 29:58] - node _T_2343 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:38] - node _T_2344 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2486:70] - node _T_2345 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2486:96] + node _T_2343 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2480:38] + node _T_2344 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2480:70] + node _T_2345 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2480:96] node _T_2346 = cat(_T_2344, UInt<1>("h00")) @[Cat.scala 29:58] node _T_2347 = cat(_T_2346, _T_2345) @[Cat.scala 29:58] - node _T_2348 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2487:36] - node _T_2349 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2487:78] - node _T_2350 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2487:102] - node _T_2351 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2487:123] - node _T_2352 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2487:144] + node _T_2348 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2481:36] + node _T_2349 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2481:78] + node _T_2350 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2481:102] + node _T_2351 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2481:123] + node _T_2352 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2481:144] node _T_2353 = cat(_T_2352, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2354 = cat(_T_2351, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2355 = cat(_T_2354, _T_2353) @[Cat.scala 29:58] @@ -75922,11 +75922,11 @@ circuit quasar_wrapper : node _T_2358 = cat(_T_2357, UInt<16>("h00")) @[Cat.scala 29:58] node _T_2359 = cat(_T_2358, _T_2356) @[Cat.scala 29:58] node _T_2360 = cat(_T_2359, _T_2355) @[Cat.scala 29:58] - node _T_2361 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2488:36] - node _T_2362 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2488:75] - node _T_2363 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2488:96] - node _T_2364 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2488:114] - node _T_2365 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2488:132] + node _T_2361 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2482:36] + node _T_2362 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2482:75] + node _T_2363 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2482:96] + node _T_2364 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2482:114] + node _T_2365 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2482:132] node _T_2366 = cat(_T_2365, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2367 = cat(_T_2364, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2368 = cat(_T_2367, _T_2366) @[Cat.scala 29:58] @@ -75935,130 +75935,130 @@ circuit quasar_wrapper : node _T_2371 = cat(_T_2370, UInt<16>("h00")) @[Cat.scala 29:58] node _T_2372 = cat(_T_2371, _T_2369) @[Cat.scala 29:58] node _T_2373 = cat(_T_2372, _T_2368) @[Cat.scala 29:58] - node _T_2374 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2489:40] - node _T_2375 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2489:65] - node _T_2376 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2490:40] - node _T_2377 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2490:69] - node _T_2378 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2491:42] - node _T_2379 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2491:72] - node _T_2380 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2492:42] - node _T_2381 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2492:72] - node _T_2382 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2493:41] - node _T_2383 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2493:66] - node _T_2384 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2494:37] + node _T_2374 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2483:40] + node _T_2375 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2483:65] + node _T_2376 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2484:40] + node _T_2377 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2484:69] + node _T_2378 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2485:42] + node _T_2379 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2485:72] + node _T_2380 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2486:42] + node _T_2381 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2486:72] + node _T_2382 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2487:41] + node _T_2383 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2487:66] + node _T_2384 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2488:37] node _T_2385 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2386 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2495:39] - node _T_2387 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2495:64] - node _T_2388 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2496:40] - node _T_2389 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2496:80] + node _T_2386 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2489:39] + node _T_2387 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2489:64] + node _T_2388 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2490:40] + node _T_2389 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2490:80] node _T_2390 = cat(UInt<28>("h00"), _T_2389) @[Cat.scala 29:58] - node _T_2391 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2497:38] - node _T_2392 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2497:63] - node _T_2393 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2498:37] - node _T_2394 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2498:62] - node _T_2395 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2499:39] - node _T_2396 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2499:64] - node _T_2397 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2500:38] + node _T_2391 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2491:38] + node _T_2392 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2491:63] + node _T_2393 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2492:37] + node _T_2394 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2492:62] + node _T_2395 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2493:39] + node _T_2396 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2493:64] + node _T_2397 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2494:38] node _T_2398 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2399 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2501:39] + node _T_2399 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2495:39] node _T_2400 = cat(meivt, meihap) @[Cat.scala 29:58] node _T_2401 = cat(_T_2400, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2402 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2502:41] - node _T_2403 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2502:81] + node _T_2402 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2496:41] + node _T_2403 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2496:81] node _T_2404 = cat(UInt<28>("h00"), _T_2403) @[Cat.scala 29:58] - node _T_2405 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2503:41] - node _T_2406 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2503:81] + node _T_2405 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2497:41] + node _T_2406 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2497:81] node _T_2407 = cat(UInt<28>("h00"), _T_2406) @[Cat.scala 29:58] - node _T_2408 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2504:38] - node _T_2409 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2504:78] + node _T_2408 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2498:38] + node _T_2409 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2498:78] node _T_2410 = cat(UInt<28>("h00"), _T_2409) @[Cat.scala 29:58] - node _T_2411 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2505:37] - node _T_2412 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2505:77] + node _T_2411 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2499:37] + node _T_2412 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2499:77] node _T_2413 = cat(UInt<23>("h00"), _T_2412) @[Cat.scala 29:58] - node _T_2414 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2506:37] - node _T_2415 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2506:77] + node _T_2414 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2500:37] + node _T_2415 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2500:77] node _T_2416 = cat(UInt<13>("h00"), _T_2415) @[Cat.scala 29:58] - node _T_2417 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2507:37] - node _T_2418 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2507:85] + node _T_2417 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2501:37] + node _T_2418 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2501:85] node _T_2419 = cat(UInt<16>("h04000"), _T_2418) @[Cat.scala 29:58] node _T_2420 = cat(_T_2419, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2421 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2508:36] + node _T_2421 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2502:36] node _T_2422 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2423 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2509:39] - node _T_2424 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2509:64] - node _T_2425 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2510:40] - node _T_2426 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2510:65] - node _T_2427 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2511:39] - node _T_2428 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2511:64] - node _T_2429 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2512:41] - node _T_2430 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2512:80] - node _T_2431 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2512:104] - node _T_2432 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2512:131] + node _T_2423 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2503:39] + node _T_2424 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2503:64] + node _T_2425 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2504:40] + node _T_2426 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2504:65] + node _T_2427 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2505:39] + node _T_2428 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2505:64] + node _T_2429 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2506:41] + node _T_2430 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2506:80] + node _T_2431 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2506:104] + node _T_2432 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2506:131] node _T_2433 = cat(UInt<3>("h00"), _T_2432) @[Cat.scala 29:58] node _T_2434 = cat(_T_2433, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2435 = cat(UInt<2>("h00"), _T_2431) @[Cat.scala 29:58] node _T_2436 = cat(UInt<7>("h00"), _T_2430) @[Cat.scala 29:58] node _T_2437 = cat(_T_2436, _T_2435) @[Cat.scala 29:58] node _T_2438 = cat(_T_2437, _T_2434) @[Cat.scala 29:58] - node _T_2439 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2513:38] - node _T_2440 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2513:78] + node _T_2439 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2507:38] + node _T_2440 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2507:78] node _T_2441 = cat(UInt<30>("h00"), _T_2440) @[Cat.scala 29:58] - node _T_2442 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2514:40] - node _T_2443 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2514:74] - node _T_2444 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2515:40] - node _T_2445 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2515:74] - node _T_2446 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2516:39] - node _T_2447 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2516:64] - node _T_2448 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2517:41] - node _T_2449 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2517:66] - node _T_2450 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2518:41] - node _T_2451 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2518:66] - node _T_2452 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2519:39] - node _T_2453 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2519:64] - node _T_2454 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2520:39] - node _T_2455 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2520:64] - node _T_2456 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2521:39] - node _T_2457 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2521:64] - node _T_2458 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2522:39] - node _T_2459 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2522:64] - node _T_2460 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2523:40] - node _T_2461 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2523:65] - node _T_2462 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2524:40] - node _T_2463 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2524:65] - node _T_2464 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2525:40] - node _T_2465 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2525:65] - node _T_2466 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2526:40] - node _T_2467 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2526:65] - node _T_2468 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2527:38] - node _T_2469 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2527:78] + node _T_2442 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2508:40] + node _T_2443 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2508:74] + node _T_2444 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2509:40] + node _T_2445 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2509:74] + node _T_2446 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2510:39] + node _T_2447 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2510:64] + node _T_2448 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2511:41] + node _T_2449 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2511:66] + node _T_2450 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2512:41] + node _T_2451 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2512:66] + node _T_2452 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2513:39] + node _T_2453 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2513:64] + node _T_2454 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2514:39] + node _T_2455 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2514:64] + node _T_2456 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2515:39] + node _T_2457 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2515:64] + node _T_2458 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2516:39] + node _T_2459 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2516:64] + node _T_2460 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2517:40] + node _T_2461 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2517:65] + node _T_2462 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2518:40] + node _T_2463 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2518:65] + node _T_2464 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2519:40] + node _T_2465 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2519:65] + node _T_2466 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2520:40] + node _T_2467 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2520:65] + node _T_2468 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2521:38] + node _T_2469 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2521:78] node _T_2470 = cat(UInt<26>("h00"), _T_2469) @[Cat.scala 29:58] - node _T_2471 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2528:38] - node _T_2472 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2528:78] + node _T_2471 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2522:38] + node _T_2472 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2522:78] node _T_2473 = cat(UInt<30>("h00"), _T_2472) @[Cat.scala 29:58] - node _T_2474 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2529:39] - node _T_2475 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2529:79] + node _T_2474 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2523:39] + node _T_2475 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2523:79] node _T_2476 = cat(UInt<22>("h00"), _T_2475) @[Cat.scala 29:58] - node _T_2477 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2530:39] - node _T_2478 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2530:79] + node _T_2477 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2524:39] + node _T_2478 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2524:79] node _T_2479 = cat(UInt<22>("h00"), _T_2478) @[Cat.scala 29:58] - node _T_2480 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2531:39] - node _T_2481 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2531:78] + node _T_2480 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2525:39] + node _T_2481 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2525:78] node _T_2482 = cat(UInt<22>("h00"), _T_2481) @[Cat.scala 29:58] - node _T_2483 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2532:39] - node _T_2484 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2532:78] + node _T_2483 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2526:39] + node _T_2484 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2526:78] node _T_2485 = cat(UInt<22>("h00"), _T_2484) @[Cat.scala 29:58] - node _T_2486 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2533:46] - node _T_2487 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2533:86] + node _T_2486 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2527:46] + node _T_2487 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2527:86] node _T_2488 = cat(UInt<25>("h00"), _T_2487) @[Cat.scala 29:58] - node _T_2489 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2534:37] + node _T_2489 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2528:37] node _T_2490 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] node _T_2491 = cat(_T_2490, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2492 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2535:37] - node _T_2493 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2535:76] + node _T_2492 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2529:37] + node _T_2493 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2529:76] node _T_2494 = mux(_T_2328, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2495 = mux(_T_2329, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2496 = mux(_T_2330, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2497 = mux(_T_2331, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2497 = mux(_T_2331, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2498 = mux(_T_2332, _T_2333, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2499 = mux(_T_2334, _T_2342, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2500 = mux(_T_2343, _T_2347, UInt<1>("h00")) @[Mux.scala 27:72] @@ -76168,1695 +76168,1695 @@ circuit quasar_wrapper : node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72] wire _T_2605 : UInt @[Mux.scala 27:72] _T_2605 <= _T_2604 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2605 @[dec_tlu_ctl.scala 2479:21] + io.dec_csr_rddata_d <= _T_2605 @[dec_tlu_ctl.scala 2473:21] module dec_decode_csr_read : input clock : Clock input reset : AsyncReset output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} - node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2551:198] - node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2551:198] - node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2551:198] - node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2553:57] - node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2551:198] - node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2551:198] - node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2554:57] - node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2551:198] - node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2551:198] - node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2555:57] - node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2551:198] - node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2551:198] - node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2556:57] - node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2551:198] - node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2557:57] - node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2551:198] - node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2551:198] - node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2551:198] - node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2558:57] - node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2551:198] - node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2551:198] - node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2551:198] - node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2559:57] - node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2551:198] - node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2560:65] - node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2551:198] - node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2551:198] - node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2551:198] - node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2561:65] - node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2551:198] - node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2551:198] - node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2551:198] - node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2551:198] - node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2562:57] - node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2551:198] - node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2551:198] - node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2551:198] - node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2551:198] - node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2551:198] - node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2563:57] - node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2551:198] - node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2551:198] - node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2551:198] - node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2551:198] - node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2551:198] - node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2564:57] - node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2551:198] - node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2551:198] - node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2551:198] - node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2551:198] - node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2551:198] - node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2565:57] - node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2551:198] - node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2551:198] - node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2551:198] - node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2566:57] - node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2551:198] - node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2551:198] - node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2567:57] - node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2551:198] - node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2551:198] - node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2568:57] - node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2551:198] - node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2569:57] - node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2551:198] - node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2551:198] - node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2570:57] - node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2551:198] - node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2551:198] - node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2551:198] - node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2551:198] - node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2571:57] - node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2551:198] - node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2551:198] - node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2551:198] - node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2572:57] - node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2551:198] - node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2551:198] - node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2573:57] - node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2551:198] - node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2574:57] - node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2551:198] - node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2551:198] - node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2551:198] - node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2551:198] - node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2575:57] - node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2551:198] - node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2551:198] - node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2576:57] - node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2551:198] - node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2577:57] - node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2551:198] - node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2551:198] - node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2578:57] - node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2551:198] - node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2551:198] - node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2551:198] - node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2579:57] - node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2551:198] - node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2551:198] - node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2580:57] - node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2551:198] - node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2551:198] - node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2551:198] - node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2581:57] - node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2551:198] - node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2551:198] - node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2551:198] - node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2582:65] - node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2551:198] - node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2551:198] - node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2551:198] - node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2583:57] - node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2551:198] - node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2551:198] - node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2584:57] - node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2551:198] - node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2551:198] - node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2585:57] - node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2551:198] - node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2551:198] - node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2551:198] - node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2551:198] - node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2586:57] - node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2551:198] - node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2551:198] - node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2551:198] - node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2551:198] - node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2551:198] - node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2587:57] - node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2551:198] - node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2551:198] - node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2551:198] - node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2551:198] - node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2588:57] - node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2551:198] - node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2551:198] - node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2551:198] - node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2551:198] - node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2551:198] - node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2589:57] - node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2551:198] - node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2551:198] - node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2551:198] - node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2551:198] - node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2590:57] - node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2551:198] - node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2551:198] - node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2551:198] - node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2551:198] - node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2551:198] - node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2591:57] - node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2551:198] - node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2551:198] - node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2551:198] - node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2551:198] - node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2592:57] - node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2551:198] - node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2551:198] - node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2551:198] - node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2551:198] - node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2551:198] - node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2593:57] - node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2551:198] - node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2551:198] - node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2551:198] - node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2551:198] - node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2594:57] - node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2551:198] - node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2551:198] - node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2551:198] - node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2551:198] - node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2595:57] - node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2551:198] - node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2551:198] - node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2551:198] - node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2551:198] - node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2596:57] - node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2551:198] - node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2551:198] - node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2551:198] - node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2551:198] - node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2597:57] - node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2551:198] - node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2551:198] - node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2551:198] - node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2551:198] - node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2598:49] - node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2551:198] - node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2551:198] - node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2551:198] - node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2599:57] - node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2551:198] - node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2551:198] - node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2551:198] - node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2600:57] - node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2551:198] - node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2551:198] - node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2551:198] - node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2601:57] - node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2551:198] - node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2551:198] - node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2551:198] - node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2602:57] - node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2551:198] - node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2551:198] - node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2551:198] - node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2603:57] - node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2551:198] - node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2551:198] - node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2604:57] - node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2551:198] - node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2551:198] - node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2551:198] - node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2605:57] - node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2551:198] - node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2551:198] - node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2551:198] - node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2551:198] - node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2606:57] - node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2551:198] - node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2551:198] - node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2607:57] - node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2551:198] - node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2551:198] - node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2608:57] - node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2551:198] - node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2551:198] - node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2551:198] - node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2609:57] - node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2551:198] - node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2551:198] - node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2610:57] - node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2551:198] - node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2551:198] - node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2611:57] - node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2551:198] - node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2551:198] - node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2551:198] - node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2612:57] - node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2551:198] - node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2551:198] - node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2613:57] - node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2551:198] - node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2551:198] - node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2551:198] - node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2551:198] - node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2614:57] - node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2551:198] - node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2551:198] - node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2615:57] - node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2551:198] - node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2551:198] - node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2551:198] - node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2616:57] - node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2551:198] - node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2551:198] - node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2551:198] - node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2617:57] - node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2551:198] - node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2551:198] - node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2551:198] - node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2551:198] - io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2618:57] - node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2551:198] - node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2551:198] - node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2551:198] - node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2551:198] - node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2551:198] - node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2551:198] - node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2551:198] - node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2551:198] - node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2551:198] - node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2619:81] - node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2551:198] - node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2551:198] - node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2551:198] - node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2551:198] - node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2551:198] - node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2619:121] - node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2551:198] - node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2551:198] - node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2551:198] - node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2551:198] - node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2619:155] - node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2551:198] - node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2551:198] - node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2551:198] - node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2551:198] - node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2620:97] - node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2551:198] - node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2551:198] - node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2551:198] - node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2551:198] - node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2551:198] - node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2620:137] - io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2619:34] - node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2551:198] - node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2551:198] - node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2551:198] - node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2551:198] - node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2551:198] - node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2551:198] - node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2551:198] - node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2551:198] - node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2621:81] - node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2551:198] - node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2551:198] - node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2551:198] - node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2621:121] - node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2551:198] - node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2551:198] - node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2551:198] - node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2621:162] - node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2551:198] - node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2551:198] - node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2551:198] - node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2551:198] - node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2551:198] - node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2551:198] - node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2622:105] - node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2551:198] - node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2551:198] - node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2551:198] - node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2551:198] - node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2551:198] - node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2622:145] - node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2551:198] - node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2551:198] - node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2551:198] - node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2551:198] - node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2622:178] - io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2621:30] - node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2551:198] - node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2551:198] - node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2551:198] - node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2551:198] - node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2551:198] - node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2551:198] - node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2551:198] - node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2551:198] - node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2551:198] - node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2551:198] - node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2551:198] - node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2551:198] - node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2551:198] - node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2551:198] - node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2551:198] - node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2551:198] - node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2551:198] - node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2551:198] - node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2551:198] - node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2624:81] - node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2551:198] - node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2551:198] - node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2551:198] - node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2551:198] - node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2551:198] - node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2551:198] - node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2551:198] - node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2551:198] - node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2624:129] - node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2551:198] - node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2551:198] - node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2551:198] - node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2551:198] - node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2551:198] - node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2551:198] - node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2551:198] - node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2551:198] - node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2551:198] - node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2625:105] - node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2551:198] - node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2551:198] - node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2551:198] - node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2551:198] - node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2551:198] - node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2551:198] - node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2625:153] - node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2551:198] - node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2551:198] - node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2551:198] - node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2551:198] - node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2551:198] - node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2551:198] - node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2551:198] - node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2551:198] - node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2551:198] - node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2551:198] - node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2551:198] - node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2626:105] - node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2551:198] - node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2551:198] - node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2551:198] - node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2551:198] - node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2551:198] - node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2551:198] - node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2551:198] - node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2551:198] - node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2551:198] - node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2626:153] - node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2551:198] - node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2551:198] - node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2551:198] - node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2551:198] - node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2551:198] - node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2551:198] - node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2551:198] - node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2551:198] - node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2551:198] - node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2627:105] - node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2551:198] - node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2551:198] - node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2551:198] - node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2551:198] - node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2551:198] - node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2551:198] - node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2551:198] - node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2551:198] - node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2551:198] - node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2627:161] - node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2551:198] - node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2551:198] - node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2551:198] - node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2551:198] - node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2551:198] - node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2551:198] - node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2551:198] - node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2628:105] - node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2551:198] - node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2551:198] - node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2551:198] - node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2551:198] - node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2551:198] - node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2551:198] - node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2551:198] - node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2551:198] - node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2551:198] - node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2551:198] - node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2628:161] - node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2551:198] - node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2551:198] - node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2551:198] - node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2551:198] - node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2551:198] - node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2551:198] - node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2551:198] - node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2551:198] - node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2551:198] - node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2629:97] - node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2551:198] - node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2551:198] - node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2551:198] - node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2551:198] - node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2551:198] - node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2551:198] - node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2551:198] - node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2551:198] - node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2551:198] - node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2629:153] - node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2551:198] - node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2551:198] - node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2551:198] - node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2551:198] - node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2551:198] - node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2551:198] - node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2551:198] - node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2551:198] - node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2551:198] - node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2630:105] - node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:106] - node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2551:198] - node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2551:198] - node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2551:198] - node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2551:198] - node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2551:198] - node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2551:198] - node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2551:198] - node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2551:198] - node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2630:161] - node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2551:198] - node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2551:198] - node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2551:198] - node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2551:198] - node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2551:198] - node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2551:198] - node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2551:198] - node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2551:198] - node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2631:105] - node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2551:198] - node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2551:198] - node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2551:198] - node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2551:198] - node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2551:198] - node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2551:198] - node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2551:198] - node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2551:198] - node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2551:198] - node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2631:161] - node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:106] - node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2551:198] - node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2551:198] - node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2551:198] - node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2551:198] - node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2551:198] - node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2551:198] - node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2632:105] - node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2551:198] - node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2551:198] - node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2551:198] - node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2551:198] - node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2551:198] - node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2551:198] - node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2551:198] - node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2551:198] - node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2551:198] - node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2632:161] - node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2551:198] - node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2551:198] - node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2551:198] - node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2551:198] - node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2551:198] - node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2551:198] - node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2551:198] - node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2551:198] - node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2633:105] - node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2551:198] - node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2551:198] - node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2551:198] - node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2551:198] - node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2551:198] - node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2551:198] - node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2551:198] - node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2551:198] - node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2551:198] - node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2633:161] - node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:106] - node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:106] - node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2551:198] - node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2551:198] - node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2551:198] - node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2551:198] - node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2551:198] - node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2551:198] - node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2551:198] - node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2551:198] - node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2551:198] - node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2551:198] - node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2634:105] - node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:106] - node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2551:198] - node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2551:198] - node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2551:198] - node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2551:198] - node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2551:198] - node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2551:198] - node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2634:153] - node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:106] - node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2551:149] - node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2551:198] - node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2551:198] - node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2551:198] - node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2551:198] - node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2551:198] - node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2551:198] - node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2551:198] - node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2551:198] - node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2551:198] - node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2635:113] - node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:149] - node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:149] - node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2551:149] - node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2551:185] - node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:165] - node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2551:198] - node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2551:198] - node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2551:198] - node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2551:198] - node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2551:198] - node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2551:198] - node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2551:198] - node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2551:198] - node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2551:198] - node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2635:161] - node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2551:198] - node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2551:198] - node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2551:198] - node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2551:198] - node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2551:198] - node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2551:198] - node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2551:198] - node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2636:97] - node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2551:106] - node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2551:198] - node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2551:198] - node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2551:198] - node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2551:198] - node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2551:198] - node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2551:198] - node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2636:153] - node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:149] - node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2551:149] - node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:106] - node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2551:198] - node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2551:198] - node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2551:198] - node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2551:198] - node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2551:198] - node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2551:198] - node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2551:198] - node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2637:113] - node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2551:106] - node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2551:149] - node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2551:106] - node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2551:106] - node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2551:149] - node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2551:149] - node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2551:129] - node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2551:106] - node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2551:198] - node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2551:198] - node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2551:198] - node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2551:198] - node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2551:198] - node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2551:198] - node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2637:169] - io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2624:26] + node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2545:198] + node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2545:198] + node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2545:198] + node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2547:57] + node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2545:198] + node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2545:198] + node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2548:57] + node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2545:198] + node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2545:198] + node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2549:57] + node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2545:198] + node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2545:198] + node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2550:57] + node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2545:198] + node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2551:57] + node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2545:198] + node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2545:198] + node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2545:198] + node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2552:57] + node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2545:198] + node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2545:198] + node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2545:198] + node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2553:57] + node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2545:198] + node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2554:65] + node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2545:198] + node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2545:198] + node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2545:198] + node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2555:65] + node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2545:198] + node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2545:198] + node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2545:198] + node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2545:198] + node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2556:57] + node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2545:198] + node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2545:198] + node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2545:198] + node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2545:198] + node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2545:198] + node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2557:57] + node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2545:198] + node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2545:198] + node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2545:198] + node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2545:198] + node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2545:198] + node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2558:57] + node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2545:198] + node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2545:198] + node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2545:198] + node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2545:198] + node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2545:198] + node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2559:57] + node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2545:198] + node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2545:198] + node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2545:198] + node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2560:57] + node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2545:198] + node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2545:198] + node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2561:57] + node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2545:198] + node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2545:198] + node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2562:57] + node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2545:198] + node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2563:57] + node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2545:198] + node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2545:198] + node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2564:57] + node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2545:198] + node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2545:198] + node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2545:198] + node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2545:198] + node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2565:57] + node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2545:198] + node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2545:198] + node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2545:198] + node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2566:57] + node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2545:198] + node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2545:198] + node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2567:57] + node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2545:198] + node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2568:57] + node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2545:198] + node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2545:198] + node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2545:198] + node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2545:198] + node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2569:57] + node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2545:198] + node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2545:198] + node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2570:57] + node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2545:198] + node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2571:57] + node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2545:198] + node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2545:198] + node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2572:57] + node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2545:198] + node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2545:198] + node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2545:198] + node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2573:57] + node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2545:198] + node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2545:198] + node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2574:57] + node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2545:198] + node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2545:198] + node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2545:198] + node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2575:57] + node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2545:198] + node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2545:198] + node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2545:198] + node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2576:65] + node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2545:198] + node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2545:198] + node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2545:198] + node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2577:57] + node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2545:198] + node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2545:198] + node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2578:57] + node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2545:198] + node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2545:198] + node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2579:57] + node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2545:198] + node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2545:198] + node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2545:198] + node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2545:198] + node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2580:57] + node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2545:198] + node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2545:198] + node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2545:198] + node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2545:198] + node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2545:198] + node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2581:57] + node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2545:198] + node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2545:198] + node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2545:198] + node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2545:198] + node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2582:57] + node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2545:198] + node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2545:198] + node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2545:198] + node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2545:198] + node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2545:198] + node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2583:57] + node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2545:198] + node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2545:198] + node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2545:198] + node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2545:198] + node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2584:57] + node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2545:198] + node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2545:198] + node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2545:198] + node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2545:198] + node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2545:198] + node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2585:57] + node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2545:198] + node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2545:198] + node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2545:198] + node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2545:198] + node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2586:57] + node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2545:198] + node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2545:198] + node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2545:198] + node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2545:198] + node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2545:198] + node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2587:57] + node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2545:198] + node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2545:198] + node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2545:198] + node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2545:198] + node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2588:57] + node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2545:198] + node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2545:198] + node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2545:198] + node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2545:198] + node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2589:57] + node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2545:198] + node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2545:198] + node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2545:198] + node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2545:198] + node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2590:57] + node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2545:198] + node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2545:198] + node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2545:198] + node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2545:198] + node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2591:57] + node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2545:198] + node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2545:198] + node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2545:198] + node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2545:198] + node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2592:49] + node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2545:198] + node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2545:198] + node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2545:198] + node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2593:57] + node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2545:198] + node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2545:198] + node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2545:198] + node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2594:57] + node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2545:198] + node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2545:198] + node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2545:198] + node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2595:57] + node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2545:198] + node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2545:198] + node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2545:198] + node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2596:57] + node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2545:198] + node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2545:198] + node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2545:198] + node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2597:57] + node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2545:198] + node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2545:198] + node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2598:57] + node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2545:198] + node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2545:198] + node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2545:198] + node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2599:57] + node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2545:198] + node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2545:198] + node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2545:198] + node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2545:198] + node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2600:57] + node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2545:198] + node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2545:198] + node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2601:57] + node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2545:198] + node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2545:198] + node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2602:57] + node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2545:198] + node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2545:198] + node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2545:198] + node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2603:57] + node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2545:198] + node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2545:198] + node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2604:57] + node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2545:198] + node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2545:198] + node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2605:57] + node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2545:198] + node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2545:198] + node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2545:198] + node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2606:57] + node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2545:198] + node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2545:198] + node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2607:57] + node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2545:198] + node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2545:198] + node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2545:198] + node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2545:198] + node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2608:57] + node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2545:198] + node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2545:198] + node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2609:57] + node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2545:198] + node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2545:198] + node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2545:198] + node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2610:57] + node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2545:198] + node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2545:198] + node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2545:198] + node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2611:57] + node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2545:198] + node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2545:198] + node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2545:198] + node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2545:198] + io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2612:57] + node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2545:198] + node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2545:198] + node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2545:198] + node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2545:198] + node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2545:198] + node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2545:198] + node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2545:198] + node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2545:198] + node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2545:198] + node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2613:81] + node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2545:198] + node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2545:198] + node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2545:198] + node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2545:198] + node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2545:198] + node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2613:121] + node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2545:198] + node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2545:198] + node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2545:198] + node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2545:198] + node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2613:155] + node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2545:198] + node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2545:198] + node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2545:198] + node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2545:198] + node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2614:97] + node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2545:198] + node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2545:198] + node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2545:198] + node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2545:198] + node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2545:198] + node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2614:137] + io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2613:34] + node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2545:198] + node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2545:198] + node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2545:198] + node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2545:198] + node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2545:198] + node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2545:198] + node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2545:198] + node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2545:198] + node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2615:81] + node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2545:198] + node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2545:198] + node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2545:198] + node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2615:121] + node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2545:198] + node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2545:198] + node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2545:198] + node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2615:162] + node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2545:198] + node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2545:198] + node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2545:198] + node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2545:198] + node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2545:198] + node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2545:198] + node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2616:105] + node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2545:198] + node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2545:198] + node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2545:198] + node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2545:198] + node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2545:198] + node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2616:145] + node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2545:198] + node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2545:198] + node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2545:198] + node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2545:198] + node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2616:178] + io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2615:30] + node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2545:198] + node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2545:198] + node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2545:198] + node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2545:198] + node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2545:198] + node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2545:198] + node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2545:198] + node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2545:198] + node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2545:198] + node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2545:198] + node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2545:198] + node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2545:198] + node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2545:198] + node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2545:198] + node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2545:198] + node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2545:198] + node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2545:198] + node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2545:198] + node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2545:198] + node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2618:81] + node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2545:198] + node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2545:198] + node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2545:198] + node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2545:198] + node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2545:198] + node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2545:198] + node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2545:198] + node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2545:198] + node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2618:129] + node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2545:198] + node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2545:198] + node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2545:198] + node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2545:198] + node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2545:198] + node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2545:198] + node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2545:198] + node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2545:198] + node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2545:198] + node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2619:105] + node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2545:198] + node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2545:198] + node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2545:198] + node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2545:198] + node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2545:198] + node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2545:198] + node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2619:153] + node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2545:198] + node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2545:198] + node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2545:198] + node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2545:198] + node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2545:198] + node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2545:198] + node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2545:198] + node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2545:198] + node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2545:198] + node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2545:198] + node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2545:198] + node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2620:105] + node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2545:198] + node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2545:198] + node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2545:198] + node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2545:198] + node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2545:198] + node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2545:198] + node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2545:198] + node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2545:198] + node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2545:198] + node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2620:153] + node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2545:198] + node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2545:198] + node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2545:198] + node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2545:198] + node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2545:198] + node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2545:198] + node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2545:198] + node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2545:198] + node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2545:198] + node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2621:105] + node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2545:198] + node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2545:198] + node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2545:198] + node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2545:198] + node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2545:198] + node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2545:198] + node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2545:198] + node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2545:198] + node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2545:198] + node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2621:161] + node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2545:198] + node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2545:198] + node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2545:198] + node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2545:198] + node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2545:198] + node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2545:198] + node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2545:198] + node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2622:105] + node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2545:198] + node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2545:198] + node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2545:198] + node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2545:198] + node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2545:198] + node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2545:198] + node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2545:198] + node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2545:198] + node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2545:198] + node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2545:198] + node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2622:161] + node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2545:198] + node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2545:198] + node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2545:198] + node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2545:198] + node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2545:198] + node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2545:198] + node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2545:198] + node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2545:198] + node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2545:198] + node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2623:97] + node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2545:198] + node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2545:198] + node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2545:198] + node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2545:198] + node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2545:198] + node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2545:198] + node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2545:198] + node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2545:198] + node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2545:198] + node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2623:153] + node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2545:198] + node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2545:198] + node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2545:198] + node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2545:198] + node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2545:198] + node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2545:198] + node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2545:198] + node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2545:198] + node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2545:198] + node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2624:105] + node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:106] + node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2545:198] + node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2545:198] + node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2545:198] + node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2545:198] + node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2545:198] + node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2545:198] + node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2545:198] + node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2545:198] + node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2624:161] + node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2545:198] + node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2545:198] + node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2545:198] + node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2545:198] + node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2545:198] + node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2545:198] + node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2545:198] + node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2545:198] + node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2625:105] + node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2545:198] + node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2545:198] + node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2545:198] + node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2545:198] + node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2545:198] + node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2545:198] + node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2545:198] + node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2545:198] + node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2545:198] + node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2625:161] + node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:106] + node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2545:198] + node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2545:198] + node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2545:198] + node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2545:198] + node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2545:198] + node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2545:198] + node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2626:105] + node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2545:198] + node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2545:198] + node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2545:198] + node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2545:198] + node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2545:198] + node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2545:198] + node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2545:198] + node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2545:198] + node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2545:198] + node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2626:161] + node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2545:198] + node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2545:198] + node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2545:198] + node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2545:198] + node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2545:198] + node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2545:198] + node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2545:198] + node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2545:198] + node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2627:105] + node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2545:198] + node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2545:198] + node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2545:198] + node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2545:198] + node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2545:198] + node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2545:198] + node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2545:198] + node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2545:198] + node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2545:198] + node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2627:161] + node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:106] + node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:106] + node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2545:198] + node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2545:198] + node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2545:198] + node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2545:198] + node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2545:198] + node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2545:198] + node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2545:198] + node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2545:198] + node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2545:198] + node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2545:198] + node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2628:105] + node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:106] + node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2545:198] + node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2545:198] + node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2545:198] + node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2545:198] + node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2545:198] + node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2545:198] + node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2628:153] + node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:106] + node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2545:149] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2545:198] + node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2545:198] + node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2545:198] + node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2545:198] + node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2545:198] + node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2545:198] + node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2545:198] + node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2545:198] + node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2545:198] + node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2629:113] + node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:149] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:149] + node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2545:149] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2545:185] + node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:165] + node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2545:198] + node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2545:198] + node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2545:198] + node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2545:198] + node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2545:198] + node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2545:198] + node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2545:198] + node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2545:198] + node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2545:198] + node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2629:161] + node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2545:198] + node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2545:198] + node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2545:198] + node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2545:198] + node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2545:198] + node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2545:198] + node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2545:198] + node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2630:97] + node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2545:106] + node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2545:198] + node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2545:198] + node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2545:198] + node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2545:198] + node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2545:198] + node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2545:198] + node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2630:153] + node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:149] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2545:149] + node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:106] + node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2545:198] + node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2545:198] + node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2545:198] + node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2545:198] + node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2545:198] + node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2545:198] + node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2545:198] + node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2631:113] + node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2545:106] + node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2545:149] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2545:106] + node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2545:106] + node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2545:149] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2545:149] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2545:129] + node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2545:106] + node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2545:198] + node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2545:198] + node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2545:198] + node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2545:198] + node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2545:198] + node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2545:198] + node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2631:169] + io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2618:26] module dec_tlu_ctl : input clock : Clock input reset : AsyncReset output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}, flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip tlu_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, flip tlu_mem : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} - wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 156:67] + wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 150:67] wire pause_expired_wb : UInt<1> pause_expired_wb <= UInt<1>("h00") wire take_nmi_r_d1 : UInt<1> @@ -78083,30 +78083,30 @@ circuit quasar_wrapper : mtvec <= UInt<1>("h00") wire mip : UInt<6> mip <= UInt<1>("h00") - wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 271:41] + wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 265:41] wire dec_tlu_mpc_halted_only_ns : UInt<1> dec_tlu_mpc_halted_only_ns <= UInt<1>("h00") - node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 274:39] - node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 274:57] - dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 274:36] - inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 275:32] + node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 268:39] + node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 268:57] + dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 268:36] + inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 269:32] int_timers.clock <= clock int_timers.reset <= reset - int_timers.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 276:73] - int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 277:73] - int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 278:49] - int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 279:49] - int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 280:49] - int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 281:49] - int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 282:73] - int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 283:73] - int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 284:73] - int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 285:73] - int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 286:73] - int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 287:73] - int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 288:57] - int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 289:49] - int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 290:48] + int_timers.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 270:73] + int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 271:73] + int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 272:49] + int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 273:49] + int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 274:49] + int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 275:49] + int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 276:73] + int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 277:73] + int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 278:73] + int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 279:73] + int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 280:73] + int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 281:73] + int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 282:57] + int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 283:49] + int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 284:48] node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58] node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58] node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58] @@ -78117,841 +78117,841 @@ circuit quasar_wrapper : _T_8 <= _T_7 @[lib.scala 37:81] reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:58] syncro_ff <= _T_8 @[lib.scala 37:58] - node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 302:76] - node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 303:68] - node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 304:68] - node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 305:64] - node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 306:66] - node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 307:52] - node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 308:56] - node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 311:64] - node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 311:80] + node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 296:76] + node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 297:68] + node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 298:68] + node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 299:64] + node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 300:66] + node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 301:52] + node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 302:56] + node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 305:64] + node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 305:80] inst rvclkhdr of rvclkhdr_716 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= _T_10 @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 312:71] - node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 312:92] - node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 312:108] + node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 306:71] + node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 306:92] + node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 306:108] inst rvclkhdr_1 of rvclkhdr_717 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= _T_13 @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 315:39] - node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 316:55] - node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 316:74] - node _T_16 = or(_T_15, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 316:94] - node _T_17 = or(_T_16, reset_delayed) @[dec_tlu_ctl.scala 316:117] - node _T_18 = or(_T_17, pause_expired_r) @[dec_tlu_ctl.scala 316:133] - node _T_19 = or(_T_18, pause_expired_wb) @[dec_tlu_ctl.scala 316:151] - node _T_20 = or(_T_19, ic_perr_r) @[dec_tlu_ctl.scala 316:170] - node _T_21 = or(_T_20, ic_perr_r_d1) @[dec_tlu_ctl.scala 316:182] - node _T_22 = or(_T_21, iccm_sbecc_r) @[dec_tlu_ctl.scala 316:197] - node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 316:212] - node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 316:230] - node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 318:55] - node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 318:71] + node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 309:39] + node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 310:55] + node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 310:74] + node _T_16 = or(_T_15, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 310:94] + node _T_17 = or(_T_16, reset_delayed) @[dec_tlu_ctl.scala 310:117] + node _T_18 = or(_T_17, pause_expired_r) @[dec_tlu_ctl.scala 310:133] + node _T_19 = or(_T_18, pause_expired_wb) @[dec_tlu_ctl.scala 310:151] + node _T_20 = or(_T_19, ic_perr_r) @[dec_tlu_ctl.scala 310:170] + node _T_21 = or(_T_20, ic_perr_r_d1) @[dec_tlu_ctl.scala 310:182] + node _T_22 = or(_T_21, iccm_sbecc_r) @[dec_tlu_ctl.scala 310:197] + node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 310:212] + node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 310:230] + node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 312:55] + node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 312:71] inst rvclkhdr_2 of rvclkhdr_718 @[lib.scala 343:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] rvclkhdr_2.io.en <= _T_25 @[lib.scala 345:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 319:55] - node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 319:73] + node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 313:55] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 313:73] inst rvclkhdr_3 of rvclkhdr_719 @[lib.scala 343:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 344:17] rvclkhdr_3.io.en <= _T_27 @[lib.scala 345:16] rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 321:90] - iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 321:90] - reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 322:122] - _T_28 <= ic_perr_r @[dec_tlu_ctl.scala 322:122] - ic_perr_r_d1 <= _T_28 @[dec_tlu_ctl.scala 322:89] - reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 323:114] - _T_29 <= iccm_sbecc_r @[dec_tlu_ctl.scala 323:114] - iccm_sbecc_r_d1 <= _T_29 @[dec_tlu_ctl.scala 323:81] - reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 324:138] - _T_30 <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 324:138] - e5_valid <= _T_30 @[dec_tlu_ctl.scala 324:105] - reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 325:90] - _T_31 <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 325:90] - debug_mode_status <= _T_31 @[dec_tlu_ctl.scala 325:57] - reg lsu_pmu_load_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 326:82] - lsu_pmu_load_external_r <= io.lsu_tlu.lsu_pmu_load_external_m @[dec_tlu_ctl.scala 326:82] - reg lsu_pmu_store_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 327:74] - lsu_pmu_store_external_r <= io.lsu_tlu.lsu_pmu_store_external_m @[dec_tlu_ctl.scala 327:74] - reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 328:90] - tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[dec_tlu_ctl.scala 328:90] - reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 329:74] - _T_32 <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 329:74] - io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[dec_tlu_ctl.scala 329:41] - reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 330:74] - internal_dbg_halt_mode_f2 <= debug_mode_status @[dec_tlu_ctl.scala 330:74] - reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 331:74] - _T_33 <= force_halt @[dec_tlu_ctl.scala 331:74] - io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 331:41] - io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 333:37] - reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 334:106] - reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 334:106] - reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 335:98] - reset_detected <= reset_detect @[dec_tlu_ctl.scala 335:98] - node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 336:89] - reset_delayed <= _T_34 @[dec_tlu_ctl.scala 336:73] - reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 338:81] - nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 338:81] - reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 339:73] - nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 339:73] - reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:73] - nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 340:73] - reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:73] - nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 341:73] - node _T_35 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 345:32] - node _T_36 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 345:96] - node nmi_lsu_detected = and(_T_35, _T_36) @[dec_tlu_ctl.scala 345:49] - node _T_37 = not(nmi_int_delayed) @[dec_tlu_ctl.scala 347:45] - node _T_38 = and(nmi_int_sync, _T_37) @[dec_tlu_ctl.scala 347:43] - node _T_39 = or(_T_38, nmi_lsu_detected) @[dec_tlu_ctl.scala 347:63] - node _T_40 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 347:106] - node _T_41 = and(nmi_int_detected_f, _T_40) @[dec_tlu_ctl.scala 347:104] - node _T_42 = or(_T_39, _T_41) @[dec_tlu_ctl.scala 347:82] - node _T_43 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 347:165] - node _T_44 = and(take_ext_int_start_d3, _T_43) @[dec_tlu_ctl.scala 347:146] - node _T_45 = or(_T_42, _T_44) @[dec_tlu_ctl.scala 347:122] - nmi_int_detected <= _T_45 @[dec_tlu_ctl.scala 347:26] - node _T_46 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 349:48] - node _T_47 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 349:119] - node _T_48 = and(nmi_int_detected_f, _T_47) @[dec_tlu_ctl.scala 349:117] - node _T_49 = not(_T_48) @[dec_tlu_ctl.scala 349:96] - node _T_50 = and(_T_46, _T_49) @[dec_tlu_ctl.scala 349:94] - node _T_51 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 349:161] - node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[dec_tlu_ctl.scala 349:159] - node _T_53 = or(_T_50, _T_52) @[dec_tlu_ctl.scala 349:136] - nmi_lsu_load_type <= _T_53 @[dec_tlu_ctl.scala 349:27] - node _T_54 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 350:49] - node _T_55 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 350:121] - node _T_56 = and(nmi_int_detected_f, _T_55) @[dec_tlu_ctl.scala 350:119] - node _T_57 = not(_T_56) @[dec_tlu_ctl.scala 350:98] - node _T_58 = and(_T_54, _T_57) @[dec_tlu_ctl.scala 350:96] - node _T_59 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 350:164] - node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[dec_tlu_ctl.scala 350:162] - node _T_61 = or(_T_58, _T_60) @[dec_tlu_ctl.scala 350:138] - nmi_lsu_store_type <= _T_61 @[dec_tlu_ctl.scala 350:28] - node _T_62 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 357:72] - node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[dec_tlu_ctl.scala 357:70] - reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 358:74] - mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[dec_tlu_ctl.scala 358:74] - reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 359:74] - mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[dec_tlu_ctl.scala 359:74] - reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 360:114] - _T_63 <= mpc_halt_state_ns @[dec_tlu_ctl.scala 360:114] - mpc_halt_state_f <= _T_63 @[dec_tlu_ctl.scala 360:81] - reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 361:106] - mpc_run_state_f <= mpc_run_state_ns @[dec_tlu_ctl.scala 361:106] - reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 362:90] - debug_brkpt_status_f <= debug_brkpt_status_ns @[dec_tlu_ctl.scala 362:90] - reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 363:90] - mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[dec_tlu_ctl.scala 363:90] - reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 364:90] - mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[dec_tlu_ctl.scala 364:90] - reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 365:114] - _T_64 <= dbg_halt_state_ns @[dec_tlu_ctl.scala 365:114] - dbg_halt_state_f <= _T_64 @[dec_tlu_ctl.scala 365:81] - reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 366:106] - dbg_run_state_f <= dbg_run_state_ns @[dec_tlu_ctl.scala 366:106] - reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 367:82] - _T_65 <= dec_tlu_mpc_halted_only_ns @[dec_tlu_ctl.scala 367:82] - io.dec_tlu_mpc_halted_only <= _T_65 @[dec_tlu_ctl.scala 367:49] - node _T_66 = not(mpc_debug_halt_req_sync_f) @[dec_tlu_ctl.scala 371:71] - node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[dec_tlu_ctl.scala 371:69] - node _T_67 = not(mpc_debug_run_req_sync_f) @[dec_tlu_ctl.scala 372:70] - node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[dec_tlu_ctl.scala 372:68] - node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[dec_tlu_ctl.scala 374:48] - node _T_69 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 374:99] - node _T_70 = and(reset_delayed, _T_69) @[dec_tlu_ctl.scala 374:97] - node _T_71 = or(_T_68, _T_70) @[dec_tlu_ctl.scala 374:80] - node _T_72 = not(mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 374:125] - node _T_73 = and(_T_71, _T_72) @[dec_tlu_ctl.scala 374:123] - mpc_halt_state_ns <= _T_73 @[dec_tlu_ctl.scala 374:27] - node _T_74 = not(mpc_debug_run_ack_f) @[dec_tlu_ctl.scala 375:80] - node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[dec_tlu_ctl.scala 375:78] - node _T_76 = or(mpc_run_state_f, _T_75) @[dec_tlu_ctl.scala 375:46] - node _T_77 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 375:133] - node _T_78 = and(debug_mode_status, _T_77) @[dec_tlu_ctl.scala 375:131] - node _T_79 = and(_T_76, _T_78) @[dec_tlu_ctl.scala 375:103] - mpc_run_state_ns <= _T_79 @[dec_tlu_ctl.scala 375:26] - node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 377:70] - node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 377:96] - node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 377:121] - node _T_83 = or(dbg_halt_state_f, _T_82) @[dec_tlu_ctl.scala 377:48] - node _T_84 = not(io.dbg_resume_req) @[dec_tlu_ctl.scala 377:153] - node _T_85 = and(_T_83, _T_84) @[dec_tlu_ctl.scala 377:151] - dbg_halt_state_ns <= _T_85 @[dec_tlu_ctl.scala 377:27] - node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[dec_tlu_ctl.scala 378:46] - node _T_87 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 378:97] - node _T_88 = and(debug_mode_status, _T_87) @[dec_tlu_ctl.scala 378:95] - node _T_89 = and(_T_86, _T_88) @[dec_tlu_ctl.scala 378:67] - dbg_run_state_ns <= _T_89 @[dec_tlu_ctl.scala 378:26] - node _T_90 = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 381:39] - node _T_91 = and(_T_90, mpc_halt_state_f) @[dec_tlu_ctl.scala 381:57] - dec_tlu_mpc_halted_only_ns <= _T_91 @[dec_tlu_ctl.scala 381:36] - node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 384:59] - node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[dec_tlu_ctl.scala 385:53] - node _T_93 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 385:105] - node _T_94 = and(internal_dbg_halt_mode, _T_93) @[dec_tlu_ctl.scala 385:103] - node _T_95 = and(_T_92, _T_94) @[dec_tlu_ctl.scala 385:77] - debug_brkpt_status_ns <= _T_95 @[dec_tlu_ctl.scala 385:31] - node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[dec_tlu_ctl.scala 388:51] - node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 388:78] - node _T_98 = and(_T_97, core_empty) @[dec_tlu_ctl.scala 388:104] - mpc_debug_halt_ack_ns <= _T_98 @[dec_tlu_ctl.scala 388:31] - node _T_99 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 389:59] - node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[dec_tlu_ctl.scala 389:57] - node _T_101 = not(mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 389:80] - node _T_102 = and(_T_100, _T_101) @[dec_tlu_ctl.scala 389:78] - node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 389:129] - node _T_104 = or(_T_102, _T_103) @[dec_tlu_ctl.scala 389:106] - mpc_debug_run_ack_ns <= _T_104 @[dec_tlu_ctl.scala 389:30] - io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[dec_tlu_ctl.scala 392:31] - io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[dec_tlu_ctl.scala 393:31] - io.debug_brkpt_status <= debug_brkpt_status_f @[dec_tlu_ctl.scala 394:31] - node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 397:53] - node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[dec_tlu_ctl.scala 397:74] - node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 398:48] - node _T_107 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 398:71] - node _T_108 = and(_T_106, _T_107) @[dec_tlu_ctl.scala 398:69] - dbg_halt_req_final <= _T_108 @[dec_tlu_ctl.scala 398:28] - node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 401:50] - node _T_110 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 401:95] - node _T_111 = and(reset_delayed, _T_110) @[dec_tlu_ctl.scala 401:93] - node _T_112 = or(_T_109, _T_111) @[dec_tlu_ctl.scala 401:76] - node _T_113 = not(debug_mode_status) @[dec_tlu_ctl.scala 401:121] - node _T_114 = and(_T_112, _T_113) @[dec_tlu_ctl.scala 401:119] - node _T_115 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 401:149] - node debug_halt_req = and(_T_114, _T_115) @[dec_tlu_ctl.scala 401:147] - node _T_116 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 403:32] - node _T_117 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 403:75] - node _T_118 = and(mpc_run_state_ns, _T_117) @[dec_tlu_ctl.scala 403:73] - node _T_119 = not(mpc_halt_state_ns) @[dec_tlu_ctl.scala 403:117] - node _T_120 = and(dbg_run_state_ns, _T_119) @[dec_tlu_ctl.scala 403:115] - node _T_121 = or(_T_118, _T_120) @[dec_tlu_ctl.scala 403:95] - node debug_resume_req = and(_T_116, _T_121) @[dec_tlu_ctl.scala 403:52] - node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 408:43] - node _T_123 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 408:66] - node _T_124 = and(_T_122, _T_123) @[dec_tlu_ctl.scala 408:64] - node _T_125 = not(mret_r) @[dec_tlu_ctl.scala 408:89] - node _T_126 = and(_T_124, _T_125) @[dec_tlu_ctl.scala 408:87] - node _T_127 = not(halt_taken_f) @[dec_tlu_ctl.scala 408:99] - node _T_128 = and(_T_126, _T_127) @[dec_tlu_ctl.scala 408:97] - node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[dec_tlu_ctl.scala 408:115] - node _T_130 = and(_T_128, _T_129) @[dec_tlu_ctl.scala 408:113] - node _T_131 = not(take_reset) @[dec_tlu_ctl.scala 408:145] - node take_halt = and(_T_130, _T_131) @[dec_tlu_ctl.scala 408:143] - node _T_132 = not(dec_tlu_flush_pause_r_d1) @[dec_tlu_ctl.scala 411:56] - node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[dec_tlu_ctl.scala 411:54] - node _T_134 = not(take_ext_int_start_d1) @[dec_tlu_ctl.scala 411:84] - node _T_135 = and(_T_133, _T_134) @[dec_tlu_ctl.scala 411:82] - node _T_136 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 411:126] - node _T_137 = and(halt_taken_f, _T_136) @[dec_tlu_ctl.scala 411:124] - node _T_138 = not(pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 411:146] - node _T_139 = and(_T_137, _T_138) @[dec_tlu_ctl.scala 411:144] - node _T_140 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 411:169] - node _T_141 = and(_T_139, _T_140) @[dec_tlu_ctl.scala 411:167] - node halt_taken = or(_T_135, _T_141) @[dec_tlu_ctl.scala 411:108] - node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[dec_tlu_ctl.scala 415:53] - node _T_143 = and(_T_142, io.tlu_mem.ifu_miss_state_idle) @[dec_tlu_ctl.scala 415:70] - node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 415:103] - node _T_145 = not(debug_halt_req) @[dec_tlu_ctl.scala 415:129] - node _T_146 = and(_T_144, _T_145) @[dec_tlu_ctl.scala 415:127] - node _T_147 = not(debug_halt_req_d1) @[dec_tlu_ctl.scala 415:147] - node _T_148 = and(_T_146, _T_147) @[dec_tlu_ctl.scala 415:145] - node _T_149 = not(io.dec_div_active) @[dec_tlu_ctl.scala 415:168] - node _T_150 = and(_T_148, _T_149) @[dec_tlu_ctl.scala 415:166] - node _T_151 = or(force_halt, _T_150) @[dec_tlu_ctl.scala 415:34] - core_empty <= _T_151 @[dec_tlu_ctl.scala 415:20] - node _T_152 = not(debug_mode_status) @[dec_tlu_ctl.scala 421:37] - node _T_153 = and(_T_152, debug_halt_req) @[dec_tlu_ctl.scala 421:63] - node _T_154 = or(_T_153, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 421:81] - node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 421:107] - node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 421:132] - node _T_156 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 424:111] - node _T_157 = not(_T_156) @[dec_tlu_ctl.scala 424:106] - node _T_158 = and(debug_resume_req_f, _T_157) @[dec_tlu_ctl.scala 424:104] - node _T_159 = not(_T_158) @[dec_tlu_ctl.scala 424:83] - node _T_160 = and(debug_mode_status, _T_159) @[dec_tlu_ctl.scala 424:81] - node _T_161 = or(debug_halt_req_ns, _T_160) @[dec_tlu_ctl.scala 424:53] - internal_dbg_halt_mode <= _T_161 @[dec_tlu_ctl.scala 424:32] - node _T_162 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 426:67] - node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[dec_tlu_ctl.scala 426:65] - node _T_163 = and(debug_halt_req_f, core_empty) @[dec_tlu_ctl.scala 431:48] - node _T_164 = and(_T_163, halt_taken) @[dec_tlu_ctl.scala 431:61] - node _T_165 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 431:97] - node _T_166 = and(dbg_tlu_halted_f, _T_165) @[dec_tlu_ctl.scala 431:95] - node dbg_tlu_halted = or(_T_164, _T_166) @[dec_tlu_ctl.scala 431:75] - node _T_167 = not(dbg_tlu_halted) @[dec_tlu_ctl.scala 432:73] - node _T_168 = and(debug_halt_req_f, _T_167) @[dec_tlu_ctl.scala 432:71] - node _T_169 = or(enter_debug_halt_req, _T_168) @[dec_tlu_ctl.scala 432:51] - debug_halt_req_ns <= _T_169 @[dec_tlu_ctl.scala 432:27] - node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 433:49] - node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[dec_tlu_ctl.scala 433:68] - node _T_171 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 435:61] - node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[dec_tlu_ctl.scala 435:59] - node _T_173 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 435:90] - node _T_174 = and(_T_172, _T_173) @[dec_tlu_ctl.scala 435:84] - node _T_175 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 435:104] - node dcsr_single_step_done = and(_T_174, _T_175) @[dec_tlu_ctl.scala 435:102] - node _T_176 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 437:66] - node _T_177 = and(debug_resume_req_f, _T_176) @[dec_tlu_ctl.scala 437:60] - node _T_178 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 437:111] - node _T_179 = and(dcsr_single_step_running_f, _T_178) @[dec_tlu_ctl.scala 437:109] - node dcsr_single_step_running = or(_T_177, _T_179) @[dec_tlu_ctl.scala 437:79] - node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 439:53] - node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 442:57] - node _T_181 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 442:112] - node _T_182 = and(request_debug_mode_r_d1, _T_181) @[dec_tlu_ctl.scala 442:110] - node request_debug_mode_r = or(_T_180, _T_182) @[dec_tlu_ctl.scala 442:83] - node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 444:64] - node _T_184 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 444:95] - node request_debug_mode_done = and(_T_183, _T_184) @[dec_tlu_ctl.scala 444:93] - reg _T_185 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 447:82] - _T_185 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec_tlu_ctl.scala 447:82] - dec_tlu_flush_noredir_r_d1 <= _T_185 @[dec_tlu_ctl.scala 447:49] - reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 448:122] - _T_186 <= halt_taken @[dec_tlu_ctl.scala 448:122] - halt_taken_f <= _T_186 @[dec_tlu_ctl.scala 448:89] - reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 449:114] - _T_187 <= io.lsu_idle_any @[dec_tlu_ctl.scala 449:114] - lsu_idle_any_f <= _T_187 @[dec_tlu_ctl.scala 449:81] - reg _T_188 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 450:98] - _T_188 <= io.tlu_mem.ifu_miss_state_idle @[dec_tlu_ctl.scala 450:98] - ifu_miss_state_idle_f <= _T_188 @[dec_tlu_ctl.scala 450:65] - reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 451:114] - _T_189 <= dbg_tlu_halted @[dec_tlu_ctl.scala 451:114] - dbg_tlu_halted_f <= _T_189 @[dec_tlu_ctl.scala 451:81] - reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 452:98] - _T_190 <= resume_ack_ns @[dec_tlu_ctl.scala 452:98] - io.dec_tlu_resume_ack <= _T_190 @[dec_tlu_ctl.scala 452:65] - reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 453:114] - _T_191 <= debug_halt_req_ns @[dec_tlu_ctl.scala 453:114] - debug_halt_req_f <= _T_191 @[dec_tlu_ctl.scala 453:81] - reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 454:106] - _T_192 <= debug_resume_req @[dec_tlu_ctl.scala 454:106] - debug_resume_req_f <= _T_192 @[dec_tlu_ctl.scala 454:73] - reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 455:90] - _T_193 <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 455:90] - trigger_hit_dmode_r_d1 <= _T_193 @[dec_tlu_ctl.scala 455:57] - reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 456:90] - _T_194 <= dcsr_single_step_done @[dec_tlu_ctl.scala 456:90] - dcsr_single_step_done_f <= _T_194 @[dec_tlu_ctl.scala 456:57] - reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 457:114] - _T_195 <= debug_halt_req @[dec_tlu_ctl.scala 457:114] - debug_halt_req_d1 <= _T_195 @[dec_tlu_ctl.scala 457:81] - reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 458:90] - dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 458:90] - reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 459:98] - dec_pause_state_f <= io.dec_pause_state @[dec_tlu_ctl.scala 459:98] - reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 460:82] - _T_196 <= request_debug_mode_r @[dec_tlu_ctl.scala 460:82] - request_debug_mode_r_d1 <= _T_196 @[dec_tlu_ctl.scala 460:49] - reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 461:74] - _T_197 <= request_debug_mode_done @[dec_tlu_ctl.scala 461:74] - request_debug_mode_done_f <= _T_197 @[dec_tlu_ctl.scala 461:41] - reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 462:66] - _T_198 <= dcsr_single_step_running @[dec_tlu_ctl.scala 462:66] - dcsr_single_step_running_f <= _T_198 @[dec_tlu_ctl.scala 462:33] - reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 463:74] - _T_199 <= io.dec_tlu_flush_pause_r @[dec_tlu_ctl.scala 463:74] - dec_tlu_flush_pause_r_d1 <= _T_199 @[dec_tlu_ctl.scala 463:41] - reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 464:98] - _T_200 <= dbg_halt_req_held_ns @[dec_tlu_ctl.scala 464:98] - dbg_halt_req_held <= _T_200 @[dec_tlu_ctl.scala 464:65] - io.dec_tlu_debug_stall <= debug_halt_req_f @[dec_tlu_ctl.scala 467:41] - io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 468:41] - io.dec_tlu_debug_mode <= debug_mode_status @[dec_tlu_ctl.scala 469:41] - dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 470:41] - node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[dec_tlu_ctl.scala 473:71] - node _T_202 = or(take_halt, _T_201) @[dec_tlu_ctl.scala 473:58] - node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[dec_tlu_ctl.scala 473:97] - node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[dec_tlu_ctl.scala 473:144] - node _T_205 = or(_T_203, _T_204) @[dec_tlu_ctl.scala 473:124] - node _T_206 = or(_T_205, take_ext_int_start) @[dec_tlu_ctl.scala 473:167] - io.tlu_ifc.dec_tlu_flush_noredir_wb <= _T_206 @[dec_tlu_ctl.scala 473:45] - io.dec_tlu_flush_extint <= take_ext_int_start @[dec_tlu_ctl.scala 475:33] - node _T_207 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 478:61] - node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[dec_tlu_ctl.scala 478:59] - node _T_209 = not(take_ext_int_start) @[dec_tlu_ctl.scala 478:82] - node _T_210 = and(_T_208, _T_209) @[dec_tlu_ctl.scala 478:80] - io.dec_tlu_flush_pause_r <= _T_210 @[dec_tlu_ctl.scala 478:34] - node _T_211 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 480:28] - node _T_212 = and(_T_211, dec_pause_state_f) @[dec_tlu_ctl.scala 480:48] - node _T_213 = or(ext_int_ready, ce_int_ready) @[dec_tlu_ctl.scala 480:86] - node _T_214 = or(_T_213, timer_int_ready) @[dec_tlu_ctl.scala 480:101] - node _T_215 = or(_T_214, soft_int_ready) @[dec_tlu_ctl.scala 480:119] - node _T_216 = or(_T_215, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 480:136] - node _T_217 = or(_T_216, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 480:160] - node _T_218 = or(_T_217, nmi_int_detected) @[dec_tlu_ctl.scala 480:184] - node _T_219 = or(_T_218, ext_int_freeze_d1) @[dec_tlu_ctl.scala 480:203] - node _T_220 = not(_T_219) @[dec_tlu_ctl.scala 480:70] - node _T_221 = and(_T_212, _T_220) @[dec_tlu_ctl.scala 480:68] - node _T_222 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 480:226] - node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 480:224] - node _T_224 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 480:250] - node _T_225 = and(_T_223, _T_224) @[dec_tlu_ctl.scala 480:248] - node _T_226 = not(pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 480:270] - node _T_227 = and(_T_225, _T_226) @[dec_tlu_ctl.scala 480:268] - node _T_228 = not(halt_taken_f) @[dec_tlu_ctl.scala 480:291] - node _T_229 = and(_T_227, _T_228) @[dec_tlu_ctl.scala 480:289] - pause_expired_r <= _T_229 @[dec_tlu_ctl.scala 480:25] - node _T_230 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 482:88] - node _T_231 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_230) @[dec_tlu_ctl.scala 482:82] - node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[dec_tlu_ctl.scala 482:125] - node _T_233 = and(_T_231, _T_232) @[dec_tlu_ctl.scala 482:100] - node _T_234 = not(io.tlu_ifc.dec_tlu_flush_noredir_wb) @[dec_tlu_ctl.scala 482:155] - node _T_235 = and(_T_233, _T_234) @[dec_tlu_ctl.scala 482:153] - io.tlu_bp.dec_tlu_flush_leak_one_wb <= _T_235 @[dec_tlu_ctl.scala 482:45] - node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 483:93] - node _T_237 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_236) @[dec_tlu_ctl.scala 483:77] - io.tlu_mem.dec_tlu_flush_err_wb <= _T_237 @[dec_tlu_ctl.scala 483:41] - io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[dec_tlu_ctl.scala 486:29] - node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[dec_tlu_ctl.scala 487:42] - io.dec_dbg_cmd_fail <= _T_238 @[dec_tlu_ctl.scala 487:29] - node _T_239 = bits(mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 500:48] - node _T_240 = bits(mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 500:75] - node _T_241 = bits(mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 500:102] - node _T_242 = bits(mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 500:129] + reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 315:90] + iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 315:90] + reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 316:122] + _T_28 <= ic_perr_r @[dec_tlu_ctl.scala 316:122] + ic_perr_r_d1 <= _T_28 @[dec_tlu_ctl.scala 316:89] + reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 317:114] + _T_29 <= iccm_sbecc_r @[dec_tlu_ctl.scala 317:114] + iccm_sbecc_r_d1 <= _T_29 @[dec_tlu_ctl.scala 317:81] + reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 318:138] + _T_30 <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 318:138] + e5_valid <= _T_30 @[dec_tlu_ctl.scala 318:105] + reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 319:90] + _T_31 <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 319:90] + debug_mode_status <= _T_31 @[dec_tlu_ctl.scala 319:57] + reg lsu_pmu_load_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 320:82] + lsu_pmu_load_external_r <= io.lsu_tlu.lsu_pmu_load_external_m @[dec_tlu_ctl.scala 320:82] + reg lsu_pmu_store_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 321:74] + lsu_pmu_store_external_r <= io.lsu_tlu.lsu_pmu_store_external_m @[dec_tlu_ctl.scala 321:74] + reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 322:90] + tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[dec_tlu_ctl.scala 322:90] + reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 323:74] + _T_32 <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 323:74] + io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[dec_tlu_ctl.scala 323:41] + reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 324:74] + internal_dbg_halt_mode_f2 <= debug_mode_status @[dec_tlu_ctl.scala 324:74] + reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 325:74] + _T_33 <= force_halt @[dec_tlu_ctl.scala 325:74] + io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 325:41] + io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 327:37] + reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 328:106] + reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 328:106] + reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 329:98] + reset_detected <= reset_detect @[dec_tlu_ctl.scala 329:98] + node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 330:89] + reset_delayed <= _T_34 @[dec_tlu_ctl.scala 330:73] + reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 332:81] + nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 332:81] + reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 333:73] + nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 333:73] + reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 334:73] + nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 334:73] + reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 335:73] + nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 335:73] + node _T_35 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 339:32] + node _T_36 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 339:96] + node nmi_lsu_detected = and(_T_35, _T_36) @[dec_tlu_ctl.scala 339:49] + node _T_37 = not(nmi_int_delayed) @[dec_tlu_ctl.scala 341:45] + node _T_38 = and(nmi_int_sync, _T_37) @[dec_tlu_ctl.scala 341:43] + node _T_39 = or(_T_38, nmi_lsu_detected) @[dec_tlu_ctl.scala 341:63] + node _T_40 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 341:106] + node _T_41 = and(nmi_int_detected_f, _T_40) @[dec_tlu_ctl.scala 341:104] + node _T_42 = or(_T_39, _T_41) @[dec_tlu_ctl.scala 341:82] + node _T_43 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 341:165] + node _T_44 = and(take_ext_int_start_d3, _T_43) @[dec_tlu_ctl.scala 341:146] + node _T_45 = or(_T_42, _T_44) @[dec_tlu_ctl.scala 341:122] + nmi_int_detected <= _T_45 @[dec_tlu_ctl.scala 341:26] + node _T_46 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 343:48] + node _T_47 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 343:119] + node _T_48 = and(nmi_int_detected_f, _T_47) @[dec_tlu_ctl.scala 343:117] + node _T_49 = not(_T_48) @[dec_tlu_ctl.scala 343:96] + node _T_50 = and(_T_46, _T_49) @[dec_tlu_ctl.scala 343:94] + node _T_51 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 343:161] + node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[dec_tlu_ctl.scala 343:159] + node _T_53 = or(_T_50, _T_52) @[dec_tlu_ctl.scala 343:136] + nmi_lsu_load_type <= _T_53 @[dec_tlu_ctl.scala 343:27] + node _T_54 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 344:49] + node _T_55 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 344:121] + node _T_56 = and(nmi_int_detected_f, _T_55) @[dec_tlu_ctl.scala 344:119] + node _T_57 = not(_T_56) @[dec_tlu_ctl.scala 344:98] + node _T_58 = and(_T_54, _T_57) @[dec_tlu_ctl.scala 344:96] + node _T_59 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 344:164] + node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[dec_tlu_ctl.scala 344:162] + node _T_61 = or(_T_58, _T_60) @[dec_tlu_ctl.scala 344:138] + nmi_lsu_store_type <= _T_61 @[dec_tlu_ctl.scala 344:28] + node _T_62 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 351:72] + node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[dec_tlu_ctl.scala 351:70] + reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 352:74] + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[dec_tlu_ctl.scala 352:74] + reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 353:74] + mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[dec_tlu_ctl.scala 353:74] + reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 354:114] + _T_63 <= mpc_halt_state_ns @[dec_tlu_ctl.scala 354:114] + mpc_halt_state_f <= _T_63 @[dec_tlu_ctl.scala 354:81] + reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 355:106] + mpc_run_state_f <= mpc_run_state_ns @[dec_tlu_ctl.scala 355:106] + reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 356:90] + debug_brkpt_status_f <= debug_brkpt_status_ns @[dec_tlu_ctl.scala 356:90] + reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 357:90] + mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[dec_tlu_ctl.scala 357:90] + reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 358:90] + mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[dec_tlu_ctl.scala 358:90] + reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 359:114] + _T_64 <= dbg_halt_state_ns @[dec_tlu_ctl.scala 359:114] + dbg_halt_state_f <= _T_64 @[dec_tlu_ctl.scala 359:81] + reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 360:106] + dbg_run_state_f <= dbg_run_state_ns @[dec_tlu_ctl.scala 360:106] + reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 361:82] + _T_65 <= dec_tlu_mpc_halted_only_ns @[dec_tlu_ctl.scala 361:82] + io.dec_tlu_mpc_halted_only <= _T_65 @[dec_tlu_ctl.scala 361:49] + node _T_66 = not(mpc_debug_halt_req_sync_f) @[dec_tlu_ctl.scala 365:71] + node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[dec_tlu_ctl.scala 365:69] + node _T_67 = not(mpc_debug_run_req_sync_f) @[dec_tlu_ctl.scala 366:70] + node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[dec_tlu_ctl.scala 366:68] + node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[dec_tlu_ctl.scala 368:48] + node _T_69 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 368:99] + node _T_70 = and(reset_delayed, _T_69) @[dec_tlu_ctl.scala 368:97] + node _T_71 = or(_T_68, _T_70) @[dec_tlu_ctl.scala 368:80] + node _T_72 = not(mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 368:125] + node _T_73 = and(_T_71, _T_72) @[dec_tlu_ctl.scala 368:123] + mpc_halt_state_ns <= _T_73 @[dec_tlu_ctl.scala 368:27] + node _T_74 = not(mpc_debug_run_ack_f) @[dec_tlu_ctl.scala 369:80] + node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[dec_tlu_ctl.scala 369:78] + node _T_76 = or(mpc_run_state_f, _T_75) @[dec_tlu_ctl.scala 369:46] + node _T_77 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 369:133] + node _T_78 = and(debug_mode_status, _T_77) @[dec_tlu_ctl.scala 369:131] + node _T_79 = and(_T_76, _T_78) @[dec_tlu_ctl.scala 369:103] + mpc_run_state_ns <= _T_79 @[dec_tlu_ctl.scala 369:26] + node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 371:70] + node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 371:96] + node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 371:121] + node _T_83 = or(dbg_halt_state_f, _T_82) @[dec_tlu_ctl.scala 371:48] + node _T_84 = not(io.dbg_resume_req) @[dec_tlu_ctl.scala 371:153] + node _T_85 = and(_T_83, _T_84) @[dec_tlu_ctl.scala 371:151] + dbg_halt_state_ns <= _T_85 @[dec_tlu_ctl.scala 371:27] + node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[dec_tlu_ctl.scala 372:46] + node _T_87 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 372:97] + node _T_88 = and(debug_mode_status, _T_87) @[dec_tlu_ctl.scala 372:95] + node _T_89 = and(_T_86, _T_88) @[dec_tlu_ctl.scala 372:67] + dbg_run_state_ns <= _T_89 @[dec_tlu_ctl.scala 372:26] + node _T_90 = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 375:39] + node _T_91 = and(_T_90, mpc_halt_state_f) @[dec_tlu_ctl.scala 375:57] + dec_tlu_mpc_halted_only_ns <= _T_91 @[dec_tlu_ctl.scala 375:36] + node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 378:59] + node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[dec_tlu_ctl.scala 379:53] + node _T_93 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 379:105] + node _T_94 = and(internal_dbg_halt_mode, _T_93) @[dec_tlu_ctl.scala 379:103] + node _T_95 = and(_T_92, _T_94) @[dec_tlu_ctl.scala 379:77] + debug_brkpt_status_ns <= _T_95 @[dec_tlu_ctl.scala 379:31] + node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[dec_tlu_ctl.scala 382:51] + node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 382:78] + node _T_98 = and(_T_97, core_empty) @[dec_tlu_ctl.scala 382:104] + mpc_debug_halt_ack_ns <= _T_98 @[dec_tlu_ctl.scala 382:31] + node _T_99 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 383:59] + node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[dec_tlu_ctl.scala 383:57] + node _T_101 = not(mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 383:80] + node _T_102 = and(_T_100, _T_101) @[dec_tlu_ctl.scala 383:78] + node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 383:129] + node _T_104 = or(_T_102, _T_103) @[dec_tlu_ctl.scala 383:106] + mpc_debug_run_ack_ns <= _T_104 @[dec_tlu_ctl.scala 383:30] + io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[dec_tlu_ctl.scala 386:31] + io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[dec_tlu_ctl.scala 387:31] + io.debug_brkpt_status <= debug_brkpt_status_f @[dec_tlu_ctl.scala 388:31] + node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 391:53] + node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[dec_tlu_ctl.scala 391:74] + node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 392:48] + node _T_107 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 392:71] + node _T_108 = and(_T_106, _T_107) @[dec_tlu_ctl.scala 392:69] + dbg_halt_req_final <= _T_108 @[dec_tlu_ctl.scala 392:28] + node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 395:50] + node _T_110 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 395:95] + node _T_111 = and(reset_delayed, _T_110) @[dec_tlu_ctl.scala 395:93] + node _T_112 = or(_T_109, _T_111) @[dec_tlu_ctl.scala 395:76] + node _T_113 = not(debug_mode_status) @[dec_tlu_ctl.scala 395:121] + node _T_114 = and(_T_112, _T_113) @[dec_tlu_ctl.scala 395:119] + node _T_115 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 395:149] + node debug_halt_req = and(_T_114, _T_115) @[dec_tlu_ctl.scala 395:147] + node _T_116 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 397:32] + node _T_117 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 397:75] + node _T_118 = and(mpc_run_state_ns, _T_117) @[dec_tlu_ctl.scala 397:73] + node _T_119 = not(mpc_halt_state_ns) @[dec_tlu_ctl.scala 397:117] + node _T_120 = and(dbg_run_state_ns, _T_119) @[dec_tlu_ctl.scala 397:115] + node _T_121 = or(_T_118, _T_120) @[dec_tlu_ctl.scala 397:95] + node debug_resume_req = and(_T_116, _T_121) @[dec_tlu_ctl.scala 397:52] + node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 402:43] + node _T_123 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 402:66] + node _T_124 = and(_T_122, _T_123) @[dec_tlu_ctl.scala 402:64] + node _T_125 = not(mret_r) @[dec_tlu_ctl.scala 402:89] + node _T_126 = and(_T_124, _T_125) @[dec_tlu_ctl.scala 402:87] + node _T_127 = not(halt_taken_f) @[dec_tlu_ctl.scala 402:99] + node _T_128 = and(_T_126, _T_127) @[dec_tlu_ctl.scala 402:97] + node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[dec_tlu_ctl.scala 402:115] + node _T_130 = and(_T_128, _T_129) @[dec_tlu_ctl.scala 402:113] + node _T_131 = not(take_reset) @[dec_tlu_ctl.scala 402:145] + node take_halt = and(_T_130, _T_131) @[dec_tlu_ctl.scala 402:143] + node _T_132 = not(dec_tlu_flush_pause_r_d1) @[dec_tlu_ctl.scala 405:56] + node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[dec_tlu_ctl.scala 405:54] + node _T_134 = not(take_ext_int_start_d1) @[dec_tlu_ctl.scala 405:84] + node _T_135 = and(_T_133, _T_134) @[dec_tlu_ctl.scala 405:82] + node _T_136 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 405:126] + node _T_137 = and(halt_taken_f, _T_136) @[dec_tlu_ctl.scala 405:124] + node _T_138 = not(pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 405:146] + node _T_139 = and(_T_137, _T_138) @[dec_tlu_ctl.scala 405:144] + node _T_140 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 405:169] + node _T_141 = and(_T_139, _T_140) @[dec_tlu_ctl.scala 405:167] + node halt_taken = or(_T_135, _T_141) @[dec_tlu_ctl.scala 405:108] + node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[dec_tlu_ctl.scala 409:53] + node _T_143 = and(_T_142, io.tlu_mem.ifu_miss_state_idle) @[dec_tlu_ctl.scala 409:70] + node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 409:103] + node _T_145 = not(debug_halt_req) @[dec_tlu_ctl.scala 409:129] + node _T_146 = and(_T_144, _T_145) @[dec_tlu_ctl.scala 409:127] + node _T_147 = not(debug_halt_req_d1) @[dec_tlu_ctl.scala 409:147] + node _T_148 = and(_T_146, _T_147) @[dec_tlu_ctl.scala 409:145] + node _T_149 = not(io.dec_div_active) @[dec_tlu_ctl.scala 409:168] + node _T_150 = and(_T_148, _T_149) @[dec_tlu_ctl.scala 409:166] + node _T_151 = or(force_halt, _T_150) @[dec_tlu_ctl.scala 409:34] + core_empty <= _T_151 @[dec_tlu_ctl.scala 409:20] + node _T_152 = not(debug_mode_status) @[dec_tlu_ctl.scala 415:37] + node _T_153 = and(_T_152, debug_halt_req) @[dec_tlu_ctl.scala 415:63] + node _T_154 = or(_T_153, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 415:81] + node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 415:107] + node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 415:132] + node _T_156 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 418:111] + node _T_157 = not(_T_156) @[dec_tlu_ctl.scala 418:106] + node _T_158 = and(debug_resume_req_f, _T_157) @[dec_tlu_ctl.scala 418:104] + node _T_159 = not(_T_158) @[dec_tlu_ctl.scala 418:83] + node _T_160 = and(debug_mode_status, _T_159) @[dec_tlu_ctl.scala 418:81] + node _T_161 = or(debug_halt_req_ns, _T_160) @[dec_tlu_ctl.scala 418:53] + internal_dbg_halt_mode <= _T_161 @[dec_tlu_ctl.scala 418:32] + node _T_162 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 420:67] + node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[dec_tlu_ctl.scala 420:65] + node _T_163 = and(debug_halt_req_f, core_empty) @[dec_tlu_ctl.scala 425:48] + node _T_164 = and(_T_163, halt_taken) @[dec_tlu_ctl.scala 425:61] + node _T_165 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 425:97] + node _T_166 = and(dbg_tlu_halted_f, _T_165) @[dec_tlu_ctl.scala 425:95] + node dbg_tlu_halted = or(_T_164, _T_166) @[dec_tlu_ctl.scala 425:75] + node _T_167 = not(dbg_tlu_halted) @[dec_tlu_ctl.scala 426:73] + node _T_168 = and(debug_halt_req_f, _T_167) @[dec_tlu_ctl.scala 426:71] + node _T_169 = or(enter_debug_halt_req, _T_168) @[dec_tlu_ctl.scala 426:51] + debug_halt_req_ns <= _T_169 @[dec_tlu_ctl.scala 426:27] + node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 427:49] + node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[dec_tlu_ctl.scala 427:68] + node _T_171 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 429:61] + node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[dec_tlu_ctl.scala 429:59] + node _T_173 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 429:90] + node _T_174 = and(_T_172, _T_173) @[dec_tlu_ctl.scala 429:84] + node _T_175 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 429:104] + node dcsr_single_step_done = and(_T_174, _T_175) @[dec_tlu_ctl.scala 429:102] + node _T_176 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 431:66] + node _T_177 = and(debug_resume_req_f, _T_176) @[dec_tlu_ctl.scala 431:60] + node _T_178 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 431:111] + node _T_179 = and(dcsr_single_step_running_f, _T_178) @[dec_tlu_ctl.scala 431:109] + node dcsr_single_step_running = or(_T_177, _T_179) @[dec_tlu_ctl.scala 431:79] + node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 433:53] + node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 436:57] + node _T_181 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 436:112] + node _T_182 = and(request_debug_mode_r_d1, _T_181) @[dec_tlu_ctl.scala 436:110] + node request_debug_mode_r = or(_T_180, _T_182) @[dec_tlu_ctl.scala 436:83] + node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 438:64] + node _T_184 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 438:95] + node request_debug_mode_done = and(_T_183, _T_184) @[dec_tlu_ctl.scala 438:93] + reg _T_185 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 441:82] + _T_185 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec_tlu_ctl.scala 441:82] + dec_tlu_flush_noredir_r_d1 <= _T_185 @[dec_tlu_ctl.scala 441:49] + reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 442:122] + _T_186 <= halt_taken @[dec_tlu_ctl.scala 442:122] + halt_taken_f <= _T_186 @[dec_tlu_ctl.scala 442:89] + reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 443:114] + _T_187 <= io.lsu_idle_any @[dec_tlu_ctl.scala 443:114] + lsu_idle_any_f <= _T_187 @[dec_tlu_ctl.scala 443:81] + reg _T_188 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 444:98] + _T_188 <= io.tlu_mem.ifu_miss_state_idle @[dec_tlu_ctl.scala 444:98] + ifu_miss_state_idle_f <= _T_188 @[dec_tlu_ctl.scala 444:65] + reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 445:114] + _T_189 <= dbg_tlu_halted @[dec_tlu_ctl.scala 445:114] + dbg_tlu_halted_f <= _T_189 @[dec_tlu_ctl.scala 445:81] + reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 446:98] + _T_190 <= resume_ack_ns @[dec_tlu_ctl.scala 446:98] + io.dec_tlu_resume_ack <= _T_190 @[dec_tlu_ctl.scala 446:65] + reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 447:114] + _T_191 <= debug_halt_req_ns @[dec_tlu_ctl.scala 447:114] + debug_halt_req_f <= _T_191 @[dec_tlu_ctl.scala 447:81] + reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 448:106] + _T_192 <= debug_resume_req @[dec_tlu_ctl.scala 448:106] + debug_resume_req_f <= _T_192 @[dec_tlu_ctl.scala 448:73] + reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 449:90] + _T_193 <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 449:90] + trigger_hit_dmode_r_d1 <= _T_193 @[dec_tlu_ctl.scala 449:57] + reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 450:90] + _T_194 <= dcsr_single_step_done @[dec_tlu_ctl.scala 450:90] + dcsr_single_step_done_f <= _T_194 @[dec_tlu_ctl.scala 450:57] + reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 451:114] + _T_195 <= debug_halt_req @[dec_tlu_ctl.scala 451:114] + debug_halt_req_d1 <= _T_195 @[dec_tlu_ctl.scala 451:81] + reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 452:90] + dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 452:90] + reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 453:98] + dec_pause_state_f <= io.dec_pause_state @[dec_tlu_ctl.scala 453:98] + reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 454:82] + _T_196 <= request_debug_mode_r @[dec_tlu_ctl.scala 454:82] + request_debug_mode_r_d1 <= _T_196 @[dec_tlu_ctl.scala 454:49] + reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 455:74] + _T_197 <= request_debug_mode_done @[dec_tlu_ctl.scala 455:74] + request_debug_mode_done_f <= _T_197 @[dec_tlu_ctl.scala 455:41] + reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 456:66] + _T_198 <= dcsr_single_step_running @[dec_tlu_ctl.scala 456:66] + dcsr_single_step_running_f <= _T_198 @[dec_tlu_ctl.scala 456:33] + reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 457:74] + _T_199 <= io.dec_tlu_flush_pause_r @[dec_tlu_ctl.scala 457:74] + dec_tlu_flush_pause_r_d1 <= _T_199 @[dec_tlu_ctl.scala 457:41] + reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 458:98] + _T_200 <= dbg_halt_req_held_ns @[dec_tlu_ctl.scala 458:98] + dbg_halt_req_held <= _T_200 @[dec_tlu_ctl.scala 458:65] + io.dec_tlu_debug_stall <= debug_halt_req_f @[dec_tlu_ctl.scala 461:41] + io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 462:41] + io.dec_tlu_debug_mode <= debug_mode_status @[dec_tlu_ctl.scala 463:41] + dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 464:41] + node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[dec_tlu_ctl.scala 467:71] + node _T_202 = or(take_halt, _T_201) @[dec_tlu_ctl.scala 467:58] + node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[dec_tlu_ctl.scala 467:97] + node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[dec_tlu_ctl.scala 467:144] + node _T_205 = or(_T_203, _T_204) @[dec_tlu_ctl.scala 467:124] + node _T_206 = or(_T_205, take_ext_int_start) @[dec_tlu_ctl.scala 467:167] + io.tlu_ifc.dec_tlu_flush_noredir_wb <= _T_206 @[dec_tlu_ctl.scala 467:45] + io.dec_tlu_flush_extint <= take_ext_int_start @[dec_tlu_ctl.scala 469:33] + node _T_207 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 472:61] + node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[dec_tlu_ctl.scala 472:59] + node _T_209 = not(take_ext_int_start) @[dec_tlu_ctl.scala 472:82] + node _T_210 = and(_T_208, _T_209) @[dec_tlu_ctl.scala 472:80] + io.dec_tlu_flush_pause_r <= _T_210 @[dec_tlu_ctl.scala 472:34] + node _T_211 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 474:28] + node _T_212 = and(_T_211, dec_pause_state_f) @[dec_tlu_ctl.scala 474:48] + node _T_213 = or(ext_int_ready, ce_int_ready) @[dec_tlu_ctl.scala 474:86] + node _T_214 = or(_T_213, timer_int_ready) @[dec_tlu_ctl.scala 474:101] + node _T_215 = or(_T_214, soft_int_ready) @[dec_tlu_ctl.scala 474:119] + node _T_216 = or(_T_215, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 474:136] + node _T_217 = or(_T_216, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 474:160] + node _T_218 = or(_T_217, nmi_int_detected) @[dec_tlu_ctl.scala 474:184] + node _T_219 = or(_T_218, ext_int_freeze_d1) @[dec_tlu_ctl.scala 474:203] + node _T_220 = not(_T_219) @[dec_tlu_ctl.scala 474:70] + node _T_221 = and(_T_212, _T_220) @[dec_tlu_ctl.scala 474:68] + node _T_222 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 474:226] + node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 474:224] + node _T_224 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 474:250] + node _T_225 = and(_T_223, _T_224) @[dec_tlu_ctl.scala 474:248] + node _T_226 = not(pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 474:270] + node _T_227 = and(_T_225, _T_226) @[dec_tlu_ctl.scala 474:268] + node _T_228 = not(halt_taken_f) @[dec_tlu_ctl.scala 474:291] + node _T_229 = and(_T_227, _T_228) @[dec_tlu_ctl.scala 474:289] + pause_expired_r <= _T_229 @[dec_tlu_ctl.scala 474:25] + node _T_230 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 476:88] + node _T_231 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_230) @[dec_tlu_ctl.scala 476:82] + node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[dec_tlu_ctl.scala 476:125] + node _T_233 = and(_T_231, _T_232) @[dec_tlu_ctl.scala 476:100] + node _T_234 = not(io.tlu_ifc.dec_tlu_flush_noredir_wb) @[dec_tlu_ctl.scala 476:155] + node _T_235 = and(_T_233, _T_234) @[dec_tlu_ctl.scala 476:153] + io.tlu_bp.dec_tlu_flush_leak_one_wb <= _T_235 @[dec_tlu_ctl.scala 476:45] + node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 477:93] + node _T_237 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_236) @[dec_tlu_ctl.scala 477:77] + io.tlu_mem.dec_tlu_flush_err_wb <= _T_237 @[dec_tlu_ctl.scala 477:41] + io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[dec_tlu_ctl.scala 480:29] + node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[dec_tlu_ctl.scala 481:42] + io.dec_dbg_cmd_fail <= _T_238 @[dec_tlu_ctl.scala 481:29] + node _T_239 = bits(mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 494:48] + node _T_240 = bits(mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 494:75] + node _T_241 = bits(mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 494:102] + node _T_242 = bits(mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 494:129] node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58] node _T_244 = cat(_T_239, _T_240) @[Cat.scala 29:58] node trigger_execute = cat(_T_244, _T_243) @[Cat.scala 29:58] - node _T_245 = bits(mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 501:52] - node _T_246 = bits(mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 501:79] - node _T_247 = bits(mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 501:106] - node _T_248 = bits(mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 501:133] + node _T_245 = bits(mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 495:52] + node _T_246 = bits(mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 495:79] + node _T_247 = bits(mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 495:106] + node _T_248 = bits(mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 495:133] node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] node _T_250 = cat(_T_245, _T_246) @[Cat.scala 29:58] node trigger_data = cat(_T_250, _T_249) @[Cat.scala 29:58] - node _T_251 = bits(mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 502:52] - node _T_252 = bits(mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 502:79] - node _T_253 = bits(mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 502:106] - node _T_254 = bits(mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 502:133] + node _T_251 = bits(mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 496:52] + node _T_252 = bits(mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 496:79] + node _T_253 = bits(mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 496:106] + node _T_254 = bits(mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 496:133] node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58] node _T_256 = cat(_T_251, _T_252) @[Cat.scala 29:58] node trigger_store = cat(_T_256, _T_255) @[Cat.scala 29:58] - node _T_257 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 505:45] - node _T_258 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:71] - node _T_259 = or(_T_257, _T_258) @[dec_tlu_ctl.scala 505:62] - node _T_260 = bits(mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 505:100] - node _T_261 = and(_T_259, _T_260) @[dec_tlu_ctl.scala 505:86] - node _T_262 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 505:133] - node _T_263 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:159] - node _T_264 = or(_T_262, _T_263) @[dec_tlu_ctl.scala 505:150] - node _T_265 = bits(mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 505:188] - node _T_266 = and(_T_264, _T_265) @[dec_tlu_ctl.scala 505:174] - node _T_267 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 505:222] - node _T_268 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:248] - node _T_269 = or(_T_267, _T_268) @[dec_tlu_ctl.scala 505:239] - node _T_270 = bits(mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 505:277] - node _T_271 = and(_T_269, _T_270) @[dec_tlu_ctl.scala 505:263] - node _T_272 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 505:311] - node _T_273 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 505:337] - node _T_274 = or(_T_272, _T_273) @[dec_tlu_ctl.scala 505:328] - node _T_275 = bits(mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 505:366] - node _T_276 = and(_T_274, _T_275) @[dec_tlu_ctl.scala 505:352] + node _T_257 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 499:45] + node _T_258 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 499:71] + node _T_259 = or(_T_257, _T_258) @[dec_tlu_ctl.scala 499:62] + node _T_260 = bits(mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 499:100] + node _T_261 = and(_T_259, _T_260) @[dec_tlu_ctl.scala 499:86] + node _T_262 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 499:133] + node _T_263 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 499:159] + node _T_264 = or(_T_262, _T_263) @[dec_tlu_ctl.scala 499:150] + node _T_265 = bits(mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 499:188] + node _T_266 = and(_T_264, _T_265) @[dec_tlu_ctl.scala 499:174] + node _T_267 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 499:222] + node _T_268 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 499:248] + node _T_269 = or(_T_267, _T_268) @[dec_tlu_ctl.scala 499:239] + node _T_270 = bits(mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 499:277] + node _T_271 = and(_T_269, _T_270) @[dec_tlu_ctl.scala 499:263] + node _T_272 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 499:311] + node _T_273 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 499:337] + node _T_274 = or(_T_272, _T_273) @[dec_tlu_ctl.scala 499:328] + node _T_275 = bits(mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 499:366] + node _T_276 = and(_T_274, _T_275) @[dec_tlu_ctl.scala 499:352] node _T_277 = cat(_T_271, _T_276) @[Cat.scala 29:58] node _T_278 = cat(_T_261, _T_266) @[Cat.scala 29:58] node trigger_enabled = cat(_T_278, _T_277) @[Cat.scala 29:58] - node _T_279 = and(trigger_execute, trigger_data) @[dec_tlu_ctl.scala 508:57] + node _T_279 = and(trigger_execute, trigger_data) @[dec_tlu_ctl.scala 502:57] node _T_280 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15] node _T_281 = mux(_T_280, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_282 = and(_T_279, _T_281) @[dec_tlu_ctl.scala 508:72] - node _T_283 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 508:137] + node _T_282 = and(_T_279, _T_281) @[dec_tlu_ctl.scala 502:72] + node _T_283 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 502:137] node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15] node _T_285 = mux(_T_284, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_286 = or(_T_282, _T_285) @[dec_tlu_ctl.scala 508:98] - node i0_iside_trigger_has_pri_r = not(_T_286) @[dec_tlu_ctl.scala 508:38] - node _T_287 = and(trigger_store, trigger_data) @[dec_tlu_ctl.scala 511:51] + node _T_286 = or(_T_282, _T_285) @[dec_tlu_ctl.scala 502:98] + node i0_iside_trigger_has_pri_r = not(_T_286) @[dec_tlu_ctl.scala 502:38] + node _T_287 = and(trigger_store, trigger_data) @[dec_tlu_ctl.scala 505:51] node _T_288 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15] node _T_289 = mux(_T_288, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_290 = and(_T_287, _T_289) @[dec_tlu_ctl.scala 511:66] - node i0_lsu_trigger_has_pri_r = not(_T_290) @[dec_tlu_ctl.scala 511:35] + node _T_290 = and(_T_287, _T_289) @[dec_tlu_ctl.scala 505:66] + node i0_lsu_trigger_has_pri_r = not(_T_290) @[dec_tlu_ctl.scala 505:35] node _T_291 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15] node _T_292 = mux(_T_291, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[dec_tlu_ctl.scala 516:84] - node _T_294 = and(_T_292, _T_293) @[dec_tlu_ctl.scala 516:53] - node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 516:90] - node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 516:119] - node i0trigger_qual_r = and(_T_296, trigger_enabled) @[dec_tlu_ctl.scala 516:146] - node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 518:58] + node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[dec_tlu_ctl.scala 510:84] + node _T_294 = and(_T_292, _T_293) @[dec_tlu_ctl.scala 510:53] + node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 510:90] + node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 510:119] + node i0trigger_qual_r = and(_T_296, trigger_enabled) @[dec_tlu_ctl.scala 510:146] + node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 512:58] node _T_298 = bits(_T_297, 0, 0) @[Bitwise.scala 72:15] node _T_299 = mux(_T_298, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_300 = not(_T_299) @[dec_tlu_ctl.scala 518:23] - node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[dec_tlu_ctl.scala 518:84] - node _T_301 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 521:53] - node _T_302 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 521:73] - node _T_303 = not(_T_302) @[dec_tlu_ctl.scala 521:60] - node _T_304 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 521:103] - node _T_305 = or(_T_303, _T_304) @[dec_tlu_ctl.scala 521:89] - node _T_306 = and(_T_301, _T_305) @[dec_tlu_ctl.scala 521:57] - node _T_307 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 521:121] - node _T_308 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 521:141] - node _T_309 = not(_T_308) @[dec_tlu_ctl.scala 521:128] - node _T_310 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 521:171] - node _T_311 = or(_T_309, _T_310) @[dec_tlu_ctl.scala 521:157] - node _T_312 = and(_T_307, _T_311) @[dec_tlu_ctl.scala 521:125] - node _T_313 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 521:189] - node _T_314 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 521:209] - node _T_315 = not(_T_314) @[dec_tlu_ctl.scala 521:196] - node _T_316 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 521:239] - node _T_317 = or(_T_315, _T_316) @[dec_tlu_ctl.scala 521:225] - node _T_318 = and(_T_313, _T_317) @[dec_tlu_ctl.scala 521:193] - node _T_319 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 521:257] - node _T_320 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 521:277] - node _T_321 = not(_T_320) @[dec_tlu_ctl.scala 521:264] - node _T_322 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 521:307] - node _T_323 = or(_T_321, _T_322) @[dec_tlu_ctl.scala 521:293] - node _T_324 = and(_T_319, _T_323) @[dec_tlu_ctl.scala 521:261] + node _T_300 = not(_T_299) @[dec_tlu_ctl.scala 512:23] + node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[dec_tlu_ctl.scala 512:84] + node _T_301 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 515:53] + node _T_302 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 515:73] + node _T_303 = not(_T_302) @[dec_tlu_ctl.scala 515:60] + node _T_304 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 515:103] + node _T_305 = or(_T_303, _T_304) @[dec_tlu_ctl.scala 515:89] + node _T_306 = and(_T_301, _T_305) @[dec_tlu_ctl.scala 515:57] + node _T_307 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 515:121] + node _T_308 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 515:141] + node _T_309 = not(_T_308) @[dec_tlu_ctl.scala 515:128] + node _T_310 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 515:171] + node _T_311 = or(_T_309, _T_310) @[dec_tlu_ctl.scala 515:157] + node _T_312 = and(_T_307, _T_311) @[dec_tlu_ctl.scala 515:125] + node _T_313 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 515:189] + node _T_314 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 515:209] + node _T_315 = not(_T_314) @[dec_tlu_ctl.scala 515:196] + node _T_316 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 515:239] + node _T_317 = or(_T_315, _T_316) @[dec_tlu_ctl.scala 515:225] + node _T_318 = and(_T_313, _T_317) @[dec_tlu_ctl.scala 515:193] + node _T_319 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 515:257] + node _T_320 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 515:277] + node _T_321 = not(_T_320) @[dec_tlu_ctl.scala 515:264] + node _T_322 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 515:307] + node _T_323 = or(_T_321, _T_322) @[dec_tlu_ctl.scala 515:293] + node _T_324 = and(_T_319, _T_323) @[dec_tlu_ctl.scala 515:261] node _T_325 = cat(_T_318, _T_324) @[Cat.scala 29:58] node _T_326 = cat(_T_306, _T_312) @[Cat.scala 29:58] node i0_trigger_chain_masked_r = cat(_T_326, _T_325) @[Cat.scala 29:58] - node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 524:57] - i0_trigger_hit_r <= i0_trigger_hit_raw_r @[dec_tlu_ctl.scala 526:25] - node _T_327 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 530:44] - node _T_328 = bits(mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 530:75] - node _T_329 = and(_T_327, _T_328) @[dec_tlu_ctl.scala 530:61] - node _T_330 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 530:104] - node _T_331 = bits(mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 530:135] - node _T_332 = and(_T_330, _T_331) @[dec_tlu_ctl.scala 530:121] - node _T_333 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 530:164] - node _T_334 = bits(mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 530:195] - node _T_335 = and(_T_333, _T_334) @[dec_tlu_ctl.scala 530:181] - node _T_336 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 530:224] - node _T_337 = bits(mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 530:255] - node _T_338 = and(_T_336, _T_337) @[dec_tlu_ctl.scala 530:241] + node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 518:57] + i0_trigger_hit_r <= i0_trigger_hit_raw_r @[dec_tlu_ctl.scala 520:25] + node _T_327 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 524:44] + node _T_328 = bits(mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 524:75] + node _T_329 = and(_T_327, _T_328) @[dec_tlu_ctl.scala 524:61] + node _T_330 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 524:104] + node _T_331 = bits(mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 524:135] + node _T_332 = and(_T_330, _T_331) @[dec_tlu_ctl.scala 524:121] + node _T_333 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 524:164] + node _T_334 = bits(mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 524:195] + node _T_335 = and(_T_333, _T_334) @[dec_tlu_ctl.scala 524:181] + node _T_336 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 524:224] + node _T_337 = bits(mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 524:255] + node _T_338 = and(_T_336, _T_337) @[dec_tlu_ctl.scala 524:241] node _T_339 = cat(_T_335, _T_338) @[Cat.scala 29:58] node _T_340 = cat(_T_329, _T_332) @[Cat.scala 29:58] node trigger_action = cat(_T_340, _T_339) @[Cat.scala 29:58] node _T_341 = bits(i0_trigger_hit_r, 0, 0) @[Bitwise.scala 72:15] node _T_342 = mux(_T_341, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 533:56] - node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[dec_tlu_ctl.scala 536:57] - node i0_trigger_action_r = orr(_T_343) @[dec_tlu_ctl.scala 536:75] - node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[dec_tlu_ctl.scala 538:45] - trigger_hit_dmode_r <= _T_344 @[dec_tlu_ctl.scala 538:24] - node _T_345 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 540:55] - node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[dec_tlu_ctl.scala 540:53] - node _T_346 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 565:62] - node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[dec_tlu_ctl.scala 565:60] - node _T_348 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 565:87] - node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[dec_tlu_ctl.scala 565:85] - node _T_349 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 566:60] - node _T_350 = and(i_cpu_run_req_sync, _T_349) @[dec_tlu_ctl.scala 566:58] - node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 566:83] - node _T_352 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 566:107] - node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[dec_tlu_ctl.scala 566:105] - reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 568:81] - i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[dec_tlu_ctl.scala 568:81] - reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 569:81] - i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[dec_tlu_ctl.scala 569:81] - reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 570:82] - _T_353 <= cpu_halt_status @[dec_tlu_ctl.scala 570:82] - io.o_cpu_halt_status <= _T_353 @[dec_tlu_ctl.scala 570:49] - reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 571:82] - _T_354 <= cpu_halt_ack @[dec_tlu_ctl.scala 571:82] - io.o_cpu_halt_ack <= _T_354 @[dec_tlu_ctl.scala 571:49] - reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 572:82] - _T_355 <= cpu_run_ack @[dec_tlu_ctl.scala 572:82] - io.o_cpu_run_ack <= _T_355 @[dec_tlu_ctl.scala 572:49] - reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 573:70] - internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 573:70] - reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 574:82] - _T_356 <= pmu_fw_halt_req_ns @[dec_tlu_ctl.scala 574:82] - pmu_fw_halt_req_f <= _T_356 @[dec_tlu_ctl.scala 574:49] - reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 575:74] - _T_357 <= pmu_fw_tlu_halted @[dec_tlu_ctl.scala 575:74] - pmu_fw_tlu_halted_f <= _T_357 @[dec_tlu_ctl.scala 575:41] - reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 576:74] - _T_358 <= int_timer0_int_hold @[dec_tlu_ctl.scala 576:74] - int_timer0_int_hold_f <= _T_358 @[dec_tlu_ctl.scala 576:41] - reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 577:74] - _T_359 <= int_timer1_int_hold @[dec_tlu_ctl.scala 577:74] - int_timer1_int_hold_f <= _T_359 @[dec_tlu_ctl.scala 577:41] - node _T_360 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 581:52] - node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[dec_tlu_ctl.scala 581:50] - node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 582:48] - node _T_361 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 583:72] - node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[dec_tlu_ctl.scala 583:70] - node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[dec_tlu_ctl.scala 583:49] - node _T_364 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 583:95] - node _T_365 = and(_T_363, _T_364) @[dec_tlu_ctl.scala 583:93] - pmu_fw_halt_req_ns <= _T_365 @[dec_tlu_ctl.scala 583:23] - node _T_366 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 584:85] - node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[dec_tlu_ctl.scala 584:83] - node _T_368 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 584:105] - node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 584:103] - node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[dec_tlu_ctl.scala 584:52] - internal_pmu_fw_halt_mode <= _T_370 @[dec_tlu_ctl.scala 584:30] - node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 587:45] - node _T_372 = and(_T_371, halt_taken) @[dec_tlu_ctl.scala 587:58] - node _T_373 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 587:73] - node _T_374 = and(_T_372, _T_373) @[dec_tlu_ctl.scala 587:71] - node _T_375 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 587:121] - node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[dec_tlu_ctl.scala 587:119] - node _T_377 = or(_T_374, _T_376) @[dec_tlu_ctl.scala 587:96] - node _T_378 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 587:143] - node _T_379 = and(_T_377, _T_378) @[dec_tlu_ctl.scala 587:141] - pmu_fw_tlu_halted <= _T_379 @[dec_tlu_ctl.scala 587:22] - node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 589:38] - cpu_halt_ack <= _T_380 @[dec_tlu_ctl.scala 589:17] - node _T_381 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 590:46] - node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[dec_tlu_ctl.scala 590:44] - node _T_383 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 590:91] - node _T_384 = and(io.o_cpu_halt_status, _T_383) @[dec_tlu_ctl.scala 590:89] - node _T_385 = not(debug_mode_status) @[dec_tlu_ctl.scala 590:111] - node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 590:109] - node _T_387 = or(_T_382, _T_386) @[dec_tlu_ctl.scala 590:65] - cpu_halt_status <= _T_387 @[dec_tlu_ctl.scala 590:20] - node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 591:41] - node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 591:88] - node _T_390 = or(_T_388, _T_389) @[dec_tlu_ctl.scala 591:68] - cpu_run_ack <= _T_390 @[dec_tlu_ctl.scala 591:16] - io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 593:27] - node _T_391 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 596:66] - node _T_392 = or(_T_391, soft_int_ready) @[dec_tlu_ctl.scala 596:84] - node _T_393 = or(_T_392, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 596:101] - node _T_394 = or(_T_393, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 596:125] - node _T_395 = and(io.dec_pic.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 596:172] - node _T_396 = or(_T_394, _T_395) @[dec_tlu_ctl.scala 596:149] - node _T_397 = and(_T_396, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 596:191] - node _T_398 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 596:216] - node _T_399 = and(_T_397, _T_398) @[dec_tlu_ctl.scala 596:214] - node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[dec_tlu_ctl.scala 596:45] - i_cpu_run_req_d1 <= _T_400 @[dec_tlu_ctl.scala 596:21] - reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 602:89] - _T_401 <= mdseac_locked_ns @[dec_tlu_ctl.scala 602:89] - mdseac_locked_f <= _T_401 @[dec_tlu_ctl.scala 602:57] - reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 603:72] - lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 603:72] - node _T_402 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 605:57] - node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[dec_tlu_ctl.scala 605:55] - lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 606:21] - node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 607:40] - node _T_404 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 607:64] - node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 607:62] - node _T_406 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 607:84] - node lsu_exc_valid_r = and(_T_405, _T_406) @[dec_tlu_ctl.scala 607:82] - reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 609:74] - _T_407 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 609:74] - lsu_exc_valid_r_d1 <= _T_407 @[dec_tlu_ctl.scala 609:41] - reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 610:73] - lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 610:73] - node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 611:40] - node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[dec_tlu_ctl.scala 611:38] - node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 612:38] - node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 613:38] - node _T_409 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 617:49] - node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[dec_tlu_ctl.scala 617:47] - node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 617:70] - node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 617:105] - node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[dec_tlu_ctl.scala 617:67] - node _T_413 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 620:52] - node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[dec_tlu_ctl.scala 620:50] - node _T_415 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 620:65] - node _T_416 = and(_T_414, _T_415) @[dec_tlu_ctl.scala 620:63] - node _T_417 = not(inst_acc_r) @[dec_tlu_ctl.scala 620:82] - node _T_418 = and(_T_416, _T_417) @[dec_tlu_ctl.scala 620:79] - node _T_419 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 620:96] - node _T_420 = and(_T_418, _T_419) @[dec_tlu_ctl.scala 620:94] - node _T_421 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 620:121] - node _T_422 = and(_T_420, _T_421) @[dec_tlu_ctl.scala 620:119] - node _T_423 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 620:148] - node tlu_i0_commit_cmt = and(_T_422, _T_423) @[dec_tlu_ctl.scala 620:146] - node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 623:38] - node _T_425 = or(_T_424, inst_acc_r) @[dec_tlu_ctl.scala 623:53] - node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 623:79] - node _T_427 = or(_T_425, _T_426) @[dec_tlu_ctl.scala 623:66] - node _T_428 = or(_T_427, i0_trigger_hit_r) @[dec_tlu_ctl.scala 623:104] - tlu_i0_kill_writeb_r <= _T_428 @[dec_tlu_ctl.scala 623:25] - io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 624:37] - node _T_429 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 629:44] - node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[dec_tlu_ctl.scala 629:42] - node _T_431 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 629:98] - node _T_432 = and(_T_430, _T_431) @[dec_tlu_ctl.scala 629:66] - node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 629:154] - node _T_434 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 629:175] - node _T_435 = and(_T_433, _T_434) @[dec_tlu_ctl.scala 629:173] - node _T_436 = or(_T_432, _T_435) @[dec_tlu_ctl.scala 629:137] - node _T_437 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 629:199] - node _T_438 = and(_T_436, _T_437) @[dec_tlu_ctl.scala 629:196] - node _T_439 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 629:220] - node _T_440 = and(_T_438, _T_439) @[dec_tlu_ctl.scala 629:217] - rfpc_i0_r <= _T_440 @[dec_tlu_ctl.scala 629:14] - node _T_441 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 632:70] - node _T_442 = and(iccm_repair_state_d1, _T_441) @[dec_tlu_ctl.scala 632:68] - node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[dec_tlu_ctl.scala 632:44] - iccm_repair_state_ns <= _T_443 @[dec_tlu_ctl.scala 632:25] - node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 638:52] - node _T_445 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 638:88] - node _T_446 = or(_T_445, mret_r) @[dec_tlu_ctl.scala 638:98] - node _T_447 = or(_T_446, take_reset) @[dec_tlu_ctl.scala 638:107] - node _T_448 = or(_T_447, illegal_r) @[dec_tlu_ctl.scala 638:120] - node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 638:176] - node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[dec_tlu_ctl.scala 638:153] - node _T_451 = or(_T_448, _T_450) @[dec_tlu_ctl.scala 638:132] - node _T_452 = not(_T_451) @[dec_tlu_ctl.scala 638:77] - node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[dec_tlu_ctl.scala 638:75] - node _T_453 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 641:59] - node _T_454 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 641:85] - node dec_tlu_br0_error_r = and(_T_453, _T_454) @[dec_tlu_ctl.scala 641:83] - node _T_455 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 642:71] - node _T_456 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 642:97] - node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[dec_tlu_ctl.scala 642:95] - node _T_457 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 643:55] - node _T_458 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 643:81] - node _T_459 = and(_T_457, _T_458) @[dec_tlu_ctl.scala 643:79] - node _T_460 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 643:106] - node _T_461 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 643:135] - node _T_462 = or(_T_460, _T_461) @[dec_tlu_ctl.scala 643:133] - node dec_tlu_br0_v_r = and(_T_459, _T_462) @[dec_tlu_ctl.scala 643:103] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 646:65] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 647:57] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 648:57] - io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 649:57] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 650:65] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 651:65] - node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 654:52] - node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 654:65] - node _T_465 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 654:91] - node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 654:89] - node _T_467 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 654:116] - node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 654:111] - node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 654:109] - node _T_470 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 654:133] - node _T_471 = and(_T_469, _T_470) @[dec_tlu_ctl.scala 654:131] - ebreak_r <= _T_471 @[dec_tlu_ctl.scala 654:14] - node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 655:52] - node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 655:65] - node _T_474 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 655:91] - node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 655:89] - node _T_476 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 655:111] - node _T_477 = and(_T_475, _T_476) @[dec_tlu_ctl.scala 655:109] - ecall_r <= _T_477 @[dec_tlu_ctl.scala 655:14] - node _T_478 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 656:18] - node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 656:47] - node _T_480 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 656:73] - node _T_481 = and(_T_479, _T_480) @[dec_tlu_ctl.scala 656:71] - node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 656:93] - node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 656:91] - illegal_r <= _T_483 @[dec_tlu_ctl.scala 656:14] - node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 657:58] - node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 657:71] - node _T_486 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 657:97] - node _T_487 = and(_T_485, _T_486) @[dec_tlu_ctl.scala 657:95] - node _T_488 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 657:117] - node _T_489 = and(_T_487, _T_488) @[dec_tlu_ctl.scala 657:115] - mret_r <= _T_489 @[dec_tlu_ctl.scala 657:20] - node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 659:50] - node _T_491 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 659:76] - node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 659:74] - node _T_493 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 659:97] - node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 659:95] - fence_i_r <= _T_494 @[dec_tlu_ctl.scala 659:17] - node _T_495 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 660:53] - node _T_496 = and(io.tlu_mem.ifu_ic_error_start, _T_495) @[dec_tlu_ctl.scala 660:51] - node _T_497 = not(debug_mode_status) @[dec_tlu_ctl.scala 660:75] - node _T_498 = or(_T_497, dcsr_single_step_running) @[dec_tlu_ctl.scala 660:101] - node _T_499 = and(_T_496, _T_498) @[dec_tlu_ctl.scala 660:72] - node _T_500 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 660:131] - node _T_501 = and(_T_499, _T_500) @[dec_tlu_ctl.scala 660:129] - ic_perr_r <= _T_501 @[dec_tlu_ctl.scala 660:17] - node _T_502 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 661:61] - node _T_503 = and(io.tlu_mem.ifu_iccm_rd_ecc_single_err, _T_502) @[dec_tlu_ctl.scala 661:59] - node _T_504 = not(debug_mode_status) @[dec_tlu_ctl.scala 661:83] - node _T_505 = or(_T_504, dcsr_single_step_running) @[dec_tlu_ctl.scala 661:109] - node _T_506 = and(_T_503, _T_505) @[dec_tlu_ctl.scala 661:80] - node _T_507 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 661:139] - node _T_508 = and(_T_506, _T_507) @[dec_tlu_ctl.scala 661:137] - iccm_sbecc_r <= _T_508 @[dec_tlu_ctl.scala 661:17] - node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 662:49] - inst_acc_r_raw <= _T_509 @[dec_tlu_ctl.scala 662:20] - node _T_510 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 663:35] - node _T_511 = and(inst_acc_r_raw, _T_510) @[dec_tlu_ctl.scala 663:33] - node _T_512 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 663:48] - node _T_513 = and(_T_511, _T_512) @[dec_tlu_ctl.scala 663:46] - inst_acc_r <= _T_513 @[dec_tlu_ctl.scala 663:15] - node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 666:64] - node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 666:77] - node _T_516 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 666:103] - node _T_517 = and(_T_515, _T_516) @[dec_tlu_ctl.scala 666:101] - node _T_518 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 666:127] - node _T_519 = and(_T_517, _T_518) @[dec_tlu_ctl.scala 666:121] - node _T_520 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 666:144] - node _T_521 = and(_T_519, _T_520) @[dec_tlu_ctl.scala 666:142] - ebreak_to_debug_mode_r <= _T_521 @[dec_tlu_ctl.scala 666:27] - reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 668:64] - _T_522 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 668:64] - ebreak_to_debug_mode_r_d1 <= _T_522 @[dec_tlu_ctl.scala 668:34] - io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 669:39] - node _T_523 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 682:41] - node _T_524 = or(_T_523, illegal_r) @[dec_tlu_ctl.scala 682:51] - node _T_525 = or(_T_524, inst_acc_r) @[dec_tlu_ctl.scala 682:63] - node _T_526 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 682:79] - node _T_527 = and(_T_525, _T_526) @[dec_tlu_ctl.scala 682:77] - node _T_528 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 682:92] - node i0_exception_valid_r = and(_T_527, _T_528) @[dec_tlu_ctl.scala 682:90] - node _T_529 = not(take_nmi) @[dec_tlu_ctl.scala 691:33] - node _T_530 = and(take_ext_int, _T_529) @[dec_tlu_ctl.scala 691:31] - node _T_531 = bits(_T_530, 0, 0) @[dec_tlu_ctl.scala 691:44] - node _T_532 = not(take_nmi) @[dec_tlu_ctl.scala 692:27] - node _T_533 = and(take_timer_int, _T_532) @[dec_tlu_ctl.scala 692:25] - node _T_534 = bits(_T_533, 0, 0) @[dec_tlu_ctl.scala 692:38] - node _T_535 = not(take_nmi) @[dec_tlu_ctl.scala 693:26] - node _T_536 = and(take_soft_int, _T_535) @[dec_tlu_ctl.scala 693:24] - node _T_537 = bits(_T_536, 0, 0) @[dec_tlu_ctl.scala 693:37] - node _T_538 = not(take_nmi) @[dec_tlu_ctl.scala 694:32] - node _T_539 = and(take_int_timer0_int, _T_538) @[dec_tlu_ctl.scala 694:30] - node _T_540 = bits(_T_539, 0, 0) @[dec_tlu_ctl.scala 694:43] - node _T_541 = not(take_nmi) @[dec_tlu_ctl.scala 695:32] - node _T_542 = and(take_int_timer1_int, _T_541) @[dec_tlu_ctl.scala 695:30] - node _T_543 = bits(_T_542, 0, 0) @[dec_tlu_ctl.scala 695:43] - node _T_544 = not(take_nmi) @[dec_tlu_ctl.scala 696:24] - node _T_545 = and(take_ce_int, _T_544) @[dec_tlu_ctl.scala 696:22] - node _T_546 = bits(_T_545, 0, 0) @[dec_tlu_ctl.scala 696:35] - node _T_547 = not(take_nmi) @[dec_tlu_ctl.scala 697:22] - node _T_548 = and(illegal_r, _T_547) @[dec_tlu_ctl.scala 697:20] - node _T_549 = bits(_T_548, 0, 0) @[dec_tlu_ctl.scala 697:33] - node _T_550 = not(take_nmi) @[dec_tlu_ctl.scala 698:21] - node _T_551 = and(ecall_r, _T_550) @[dec_tlu_ctl.scala 698:19] - node _T_552 = bits(_T_551, 0, 0) @[dec_tlu_ctl.scala 698:32] - node _T_553 = not(take_nmi) @[dec_tlu_ctl.scala 699:24] - node _T_554 = and(inst_acc_r, _T_553) @[dec_tlu_ctl.scala 699:22] - node _T_555 = bits(_T_554, 0, 0) @[dec_tlu_ctl.scala 699:35] - node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[dec_tlu_ctl.scala 700:20] - node _T_557 = not(take_nmi) @[dec_tlu_ctl.scala 700:42] - node _T_558 = and(_T_556, _T_557) @[dec_tlu_ctl.scala 700:40] - node _T_559 = bits(_T_558, 0, 0) @[dec_tlu_ctl.scala 700:53] - node _T_560 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 701:25] - node _T_561 = and(lsu_exc_ma_r, _T_560) @[dec_tlu_ctl.scala 701:23] - node _T_562 = not(take_nmi) @[dec_tlu_ctl.scala 701:41] - node _T_563 = and(_T_561, _T_562) @[dec_tlu_ctl.scala 701:39] - node _T_564 = bits(_T_563, 0, 0) @[dec_tlu_ctl.scala 701:52] - node _T_565 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 702:26] - node _T_566 = and(lsu_exc_acc_r, _T_565) @[dec_tlu_ctl.scala 702:24] - node _T_567 = not(take_nmi) @[dec_tlu_ctl.scala 702:42] - node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 702:40] - node _T_569 = bits(_T_568, 0, 0) @[dec_tlu_ctl.scala 702:53] - node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 703:23] - node _T_571 = not(take_nmi) @[dec_tlu_ctl.scala 703:40] - node _T_572 = and(_T_570, _T_571) @[dec_tlu_ctl.scala 703:38] - node _T_573 = bits(_T_572, 0, 0) @[dec_tlu_ctl.scala 703:51] - node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 704:24] - node _T_575 = not(take_nmi) @[dec_tlu_ctl.scala 704:41] - node _T_576 = and(_T_574, _T_575) @[dec_tlu_ctl.scala 704:39] - node _T_577 = bits(_T_576, 0, 0) @[dec_tlu_ctl.scala 704:52] + node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 527:56] + node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[dec_tlu_ctl.scala 530:57] + node i0_trigger_action_r = orr(_T_343) @[dec_tlu_ctl.scala 530:75] + node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[dec_tlu_ctl.scala 532:45] + trigger_hit_dmode_r <= _T_344 @[dec_tlu_ctl.scala 532:24] + node _T_345 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 534:55] + node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[dec_tlu_ctl.scala 534:53] + node _T_346 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 559:62] + node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[dec_tlu_ctl.scala 559:60] + node _T_348 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 559:87] + node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[dec_tlu_ctl.scala 559:85] + node _T_349 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 560:60] + node _T_350 = and(i_cpu_run_req_sync, _T_349) @[dec_tlu_ctl.scala 560:58] + node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 560:83] + node _T_352 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 560:107] + node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[dec_tlu_ctl.scala 560:105] + reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 562:81] + i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[dec_tlu_ctl.scala 562:81] + reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 563:81] + i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[dec_tlu_ctl.scala 563:81] + reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 564:82] + _T_353 <= cpu_halt_status @[dec_tlu_ctl.scala 564:82] + io.o_cpu_halt_status <= _T_353 @[dec_tlu_ctl.scala 564:49] + reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 565:82] + _T_354 <= cpu_halt_ack @[dec_tlu_ctl.scala 565:82] + io.o_cpu_halt_ack <= _T_354 @[dec_tlu_ctl.scala 565:49] + reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 566:82] + _T_355 <= cpu_run_ack @[dec_tlu_ctl.scala 566:82] + io.o_cpu_run_ack <= _T_355 @[dec_tlu_ctl.scala 566:49] + reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 567:70] + internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 567:70] + reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 568:82] + _T_356 <= pmu_fw_halt_req_ns @[dec_tlu_ctl.scala 568:82] + pmu_fw_halt_req_f <= _T_356 @[dec_tlu_ctl.scala 568:49] + reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 569:74] + _T_357 <= pmu_fw_tlu_halted @[dec_tlu_ctl.scala 569:74] + pmu_fw_tlu_halted_f <= _T_357 @[dec_tlu_ctl.scala 569:41] + reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 570:74] + _T_358 <= int_timer0_int_hold @[dec_tlu_ctl.scala 570:74] + int_timer0_int_hold_f <= _T_358 @[dec_tlu_ctl.scala 570:41] + reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 571:74] + _T_359 <= int_timer1_int_hold @[dec_tlu_ctl.scala 571:74] + int_timer1_int_hold_f <= _T_359 @[dec_tlu_ctl.scala 571:41] + node _T_360 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 575:52] + node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[dec_tlu_ctl.scala 575:50] + node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 576:48] + node _T_361 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 577:72] + node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[dec_tlu_ctl.scala 577:70] + node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[dec_tlu_ctl.scala 577:49] + node _T_364 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 577:95] + node _T_365 = and(_T_363, _T_364) @[dec_tlu_ctl.scala 577:93] + pmu_fw_halt_req_ns <= _T_365 @[dec_tlu_ctl.scala 577:23] + node _T_366 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 578:85] + node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[dec_tlu_ctl.scala 578:83] + node _T_368 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 578:105] + node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 578:103] + node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[dec_tlu_ctl.scala 578:52] + internal_pmu_fw_halt_mode <= _T_370 @[dec_tlu_ctl.scala 578:30] + node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 581:45] + node _T_372 = and(_T_371, halt_taken) @[dec_tlu_ctl.scala 581:58] + node _T_373 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 581:73] + node _T_374 = and(_T_372, _T_373) @[dec_tlu_ctl.scala 581:71] + node _T_375 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 581:121] + node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[dec_tlu_ctl.scala 581:119] + node _T_377 = or(_T_374, _T_376) @[dec_tlu_ctl.scala 581:96] + node _T_378 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 581:143] + node _T_379 = and(_T_377, _T_378) @[dec_tlu_ctl.scala 581:141] + pmu_fw_tlu_halted <= _T_379 @[dec_tlu_ctl.scala 581:22] + node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 583:38] + cpu_halt_ack <= _T_380 @[dec_tlu_ctl.scala 583:17] + node _T_381 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 584:46] + node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[dec_tlu_ctl.scala 584:44] + node _T_383 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 584:91] + node _T_384 = and(io.o_cpu_halt_status, _T_383) @[dec_tlu_ctl.scala 584:89] + node _T_385 = not(debug_mode_status) @[dec_tlu_ctl.scala 584:111] + node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 584:109] + node _T_387 = or(_T_382, _T_386) @[dec_tlu_ctl.scala 584:65] + cpu_halt_status <= _T_387 @[dec_tlu_ctl.scala 584:20] + node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 585:41] + node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 585:88] + node _T_390 = or(_T_388, _T_389) @[dec_tlu_ctl.scala 585:68] + cpu_run_ack <= _T_390 @[dec_tlu_ctl.scala 585:16] + io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 587:27] + node _T_391 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 590:66] + node _T_392 = or(_T_391, soft_int_ready) @[dec_tlu_ctl.scala 590:84] + node _T_393 = or(_T_392, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 590:101] + node _T_394 = or(_T_393, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 590:125] + node _T_395 = and(io.dec_pic.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 590:172] + node _T_396 = or(_T_394, _T_395) @[dec_tlu_ctl.scala 590:149] + node _T_397 = and(_T_396, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 590:191] + node _T_398 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 590:216] + node _T_399 = and(_T_397, _T_398) @[dec_tlu_ctl.scala 590:214] + node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[dec_tlu_ctl.scala 590:45] + i_cpu_run_req_d1 <= _T_400 @[dec_tlu_ctl.scala 590:21] + reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 596:89] + _T_401 <= mdseac_locked_ns @[dec_tlu_ctl.scala 596:89] + mdseac_locked_f <= _T_401 @[dec_tlu_ctl.scala 596:57] + reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 597:72] + lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 597:72] + node _T_402 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 599:57] + node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[dec_tlu_ctl.scala 599:55] + lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 600:21] + node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 601:40] + node _T_404 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 601:64] + node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 601:62] + node _T_406 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 601:84] + node lsu_exc_valid_r = and(_T_405, _T_406) @[dec_tlu_ctl.scala 601:82] + reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 603:74] + _T_407 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 603:74] + lsu_exc_valid_r_d1 <= _T_407 @[dec_tlu_ctl.scala 603:41] + reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 604:73] + lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 604:73] + node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 605:40] + node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[dec_tlu_ctl.scala 605:38] + node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 606:38] + node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 607:38] + node _T_409 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 611:49] + node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[dec_tlu_ctl.scala 611:47] + node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 611:70] + node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 611:105] + node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[dec_tlu_ctl.scala 611:67] + node _T_413 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 614:52] + node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[dec_tlu_ctl.scala 614:50] + node _T_415 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 614:65] + node _T_416 = and(_T_414, _T_415) @[dec_tlu_ctl.scala 614:63] + node _T_417 = not(inst_acc_r) @[dec_tlu_ctl.scala 614:82] + node _T_418 = and(_T_416, _T_417) @[dec_tlu_ctl.scala 614:79] + node _T_419 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 614:96] + node _T_420 = and(_T_418, _T_419) @[dec_tlu_ctl.scala 614:94] + node _T_421 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 614:121] + node _T_422 = and(_T_420, _T_421) @[dec_tlu_ctl.scala 614:119] + node _T_423 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 614:148] + node tlu_i0_commit_cmt = and(_T_422, _T_423) @[dec_tlu_ctl.scala 614:146] + node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 617:38] + node _T_425 = or(_T_424, inst_acc_r) @[dec_tlu_ctl.scala 617:53] + node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 617:79] + node _T_427 = or(_T_425, _T_426) @[dec_tlu_ctl.scala 617:66] + node _T_428 = or(_T_427, i0_trigger_hit_r) @[dec_tlu_ctl.scala 617:104] + tlu_i0_kill_writeb_r <= _T_428 @[dec_tlu_ctl.scala 617:25] + io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 618:37] + node _T_429 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 623:44] + node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[dec_tlu_ctl.scala 623:42] + node _T_431 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 623:98] + node _T_432 = and(_T_430, _T_431) @[dec_tlu_ctl.scala 623:66] + node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 623:154] + node _T_434 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 623:175] + node _T_435 = and(_T_433, _T_434) @[dec_tlu_ctl.scala 623:173] + node _T_436 = or(_T_432, _T_435) @[dec_tlu_ctl.scala 623:137] + node _T_437 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 623:199] + node _T_438 = and(_T_436, _T_437) @[dec_tlu_ctl.scala 623:196] + node _T_439 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 623:220] + node _T_440 = and(_T_438, _T_439) @[dec_tlu_ctl.scala 623:217] + rfpc_i0_r <= _T_440 @[dec_tlu_ctl.scala 623:14] + node _T_441 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 626:70] + node _T_442 = and(iccm_repair_state_d1, _T_441) @[dec_tlu_ctl.scala 626:68] + node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[dec_tlu_ctl.scala 626:44] + iccm_repair_state_ns <= _T_443 @[dec_tlu_ctl.scala 626:25] + node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 632:52] + node _T_445 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 632:88] + node _T_446 = or(_T_445, mret_r) @[dec_tlu_ctl.scala 632:98] + node _T_447 = or(_T_446, take_reset) @[dec_tlu_ctl.scala 632:107] + node _T_448 = or(_T_447, illegal_r) @[dec_tlu_ctl.scala 632:120] + node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 632:176] + node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[dec_tlu_ctl.scala 632:153] + node _T_451 = or(_T_448, _T_450) @[dec_tlu_ctl.scala 632:132] + node _T_452 = not(_T_451) @[dec_tlu_ctl.scala 632:77] + node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[dec_tlu_ctl.scala 632:75] + node _T_453 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 635:59] + node _T_454 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 635:85] + node dec_tlu_br0_error_r = and(_T_453, _T_454) @[dec_tlu_ctl.scala 635:83] + node _T_455 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 636:71] + node _T_456 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 636:97] + node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[dec_tlu_ctl.scala 636:95] + node _T_457 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 637:55] + node _T_458 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 637:81] + node _T_459 = and(_T_457, _T_458) @[dec_tlu_ctl.scala 637:79] + node _T_460 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 637:106] + node _T_461 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 637:135] + node _T_462 = or(_T_460, _T_461) @[dec_tlu_ctl.scala 637:133] + node dec_tlu_br0_v_r = and(_T_459, _T_462) @[dec_tlu_ctl.scala 637:103] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 640:65] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 641:57] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 642:57] + io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 643:57] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 644:65] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 645:65] + node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 648:52] + node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 648:65] + node _T_465 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 648:91] + node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 648:89] + node _T_467 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 648:116] + node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 648:111] + node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 648:109] + node _T_470 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 648:133] + node _T_471 = and(_T_469, _T_470) @[dec_tlu_ctl.scala 648:131] + ebreak_r <= _T_471 @[dec_tlu_ctl.scala 648:14] + node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 649:52] + node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 649:65] + node _T_474 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 649:91] + node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 649:89] + node _T_476 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 649:111] + node _T_477 = and(_T_475, _T_476) @[dec_tlu_ctl.scala 649:109] + ecall_r <= _T_477 @[dec_tlu_ctl.scala 649:14] + node _T_478 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 650:18] + node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 650:47] + node _T_480 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 650:73] + node _T_481 = and(_T_479, _T_480) @[dec_tlu_ctl.scala 650:71] + node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 650:93] + node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 650:91] + illegal_r <= _T_483 @[dec_tlu_ctl.scala 650:14] + node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 651:58] + node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 651:71] + node _T_486 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 651:97] + node _T_487 = and(_T_485, _T_486) @[dec_tlu_ctl.scala 651:95] + node _T_488 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 651:117] + node _T_489 = and(_T_487, _T_488) @[dec_tlu_ctl.scala 651:115] + mret_r <= _T_489 @[dec_tlu_ctl.scala 651:20] + node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 653:50] + node _T_491 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 653:76] + node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 653:74] + node _T_493 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 653:97] + node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 653:95] + fence_i_r <= _T_494 @[dec_tlu_ctl.scala 653:17] + node _T_495 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 654:53] + node _T_496 = and(io.tlu_mem.ifu_ic_error_start, _T_495) @[dec_tlu_ctl.scala 654:51] + node _T_497 = not(debug_mode_status) @[dec_tlu_ctl.scala 654:75] + node _T_498 = or(_T_497, dcsr_single_step_running) @[dec_tlu_ctl.scala 654:101] + node _T_499 = and(_T_496, _T_498) @[dec_tlu_ctl.scala 654:72] + node _T_500 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 654:131] + node _T_501 = and(_T_499, _T_500) @[dec_tlu_ctl.scala 654:129] + ic_perr_r <= _T_501 @[dec_tlu_ctl.scala 654:17] + node _T_502 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 655:61] + node _T_503 = and(io.tlu_mem.ifu_iccm_rd_ecc_single_err, _T_502) @[dec_tlu_ctl.scala 655:59] + node _T_504 = not(debug_mode_status) @[dec_tlu_ctl.scala 655:83] + node _T_505 = or(_T_504, dcsr_single_step_running) @[dec_tlu_ctl.scala 655:109] + node _T_506 = and(_T_503, _T_505) @[dec_tlu_ctl.scala 655:80] + node _T_507 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 655:139] + node _T_508 = and(_T_506, _T_507) @[dec_tlu_ctl.scala 655:137] + iccm_sbecc_r <= _T_508 @[dec_tlu_ctl.scala 655:17] + node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 656:49] + inst_acc_r_raw <= _T_509 @[dec_tlu_ctl.scala 656:20] + node _T_510 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 657:35] + node _T_511 = and(inst_acc_r_raw, _T_510) @[dec_tlu_ctl.scala 657:33] + node _T_512 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 657:48] + node _T_513 = and(_T_511, _T_512) @[dec_tlu_ctl.scala 657:46] + inst_acc_r <= _T_513 @[dec_tlu_ctl.scala 657:15] + node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 660:64] + node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 660:77] + node _T_516 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 660:103] + node _T_517 = and(_T_515, _T_516) @[dec_tlu_ctl.scala 660:101] + node _T_518 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 660:127] + node _T_519 = and(_T_517, _T_518) @[dec_tlu_ctl.scala 660:121] + node _T_520 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 660:144] + node _T_521 = and(_T_519, _T_520) @[dec_tlu_ctl.scala 660:142] + ebreak_to_debug_mode_r <= _T_521 @[dec_tlu_ctl.scala 660:27] + reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 662:64] + _T_522 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 662:64] + ebreak_to_debug_mode_r_d1 <= _T_522 @[dec_tlu_ctl.scala 662:34] + io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 663:39] + node _T_523 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 676:41] + node _T_524 = or(_T_523, illegal_r) @[dec_tlu_ctl.scala 676:51] + node _T_525 = or(_T_524, inst_acc_r) @[dec_tlu_ctl.scala 676:63] + node _T_526 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 676:79] + node _T_527 = and(_T_525, _T_526) @[dec_tlu_ctl.scala 676:77] + node _T_528 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 676:92] + node i0_exception_valid_r = and(_T_527, _T_528) @[dec_tlu_ctl.scala 676:90] + node _T_529 = not(take_nmi) @[dec_tlu_ctl.scala 685:33] + node _T_530 = and(take_ext_int, _T_529) @[dec_tlu_ctl.scala 685:31] + node _T_531 = bits(_T_530, 0, 0) @[dec_tlu_ctl.scala 685:44] + node _T_532 = not(take_nmi) @[dec_tlu_ctl.scala 686:27] + node _T_533 = and(take_timer_int, _T_532) @[dec_tlu_ctl.scala 686:25] + node _T_534 = bits(_T_533, 0, 0) @[dec_tlu_ctl.scala 686:38] + node _T_535 = not(take_nmi) @[dec_tlu_ctl.scala 687:26] + node _T_536 = and(take_soft_int, _T_535) @[dec_tlu_ctl.scala 687:24] + node _T_537 = bits(_T_536, 0, 0) @[dec_tlu_ctl.scala 687:37] + node _T_538 = not(take_nmi) @[dec_tlu_ctl.scala 688:32] + node _T_539 = and(take_int_timer0_int, _T_538) @[dec_tlu_ctl.scala 688:30] + node _T_540 = bits(_T_539, 0, 0) @[dec_tlu_ctl.scala 688:43] + node _T_541 = not(take_nmi) @[dec_tlu_ctl.scala 689:32] + node _T_542 = and(take_int_timer1_int, _T_541) @[dec_tlu_ctl.scala 689:30] + node _T_543 = bits(_T_542, 0, 0) @[dec_tlu_ctl.scala 689:43] + node _T_544 = not(take_nmi) @[dec_tlu_ctl.scala 690:24] + node _T_545 = and(take_ce_int, _T_544) @[dec_tlu_ctl.scala 690:22] + node _T_546 = bits(_T_545, 0, 0) @[dec_tlu_ctl.scala 690:35] + node _T_547 = not(take_nmi) @[dec_tlu_ctl.scala 691:22] + node _T_548 = and(illegal_r, _T_547) @[dec_tlu_ctl.scala 691:20] + node _T_549 = bits(_T_548, 0, 0) @[dec_tlu_ctl.scala 691:33] + node _T_550 = not(take_nmi) @[dec_tlu_ctl.scala 692:21] + node _T_551 = and(ecall_r, _T_550) @[dec_tlu_ctl.scala 692:19] + node _T_552 = bits(_T_551, 0, 0) @[dec_tlu_ctl.scala 692:32] + node _T_553 = not(take_nmi) @[dec_tlu_ctl.scala 693:24] + node _T_554 = and(inst_acc_r, _T_553) @[dec_tlu_ctl.scala 693:22] + node _T_555 = bits(_T_554, 0, 0) @[dec_tlu_ctl.scala 693:35] + node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[dec_tlu_ctl.scala 694:20] + node _T_557 = not(take_nmi) @[dec_tlu_ctl.scala 694:42] + node _T_558 = and(_T_556, _T_557) @[dec_tlu_ctl.scala 694:40] + node _T_559 = bits(_T_558, 0, 0) @[dec_tlu_ctl.scala 694:53] + node _T_560 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 695:25] + node _T_561 = and(lsu_exc_ma_r, _T_560) @[dec_tlu_ctl.scala 695:23] + node _T_562 = not(take_nmi) @[dec_tlu_ctl.scala 695:41] + node _T_563 = and(_T_561, _T_562) @[dec_tlu_ctl.scala 695:39] + node _T_564 = bits(_T_563, 0, 0) @[dec_tlu_ctl.scala 695:52] + node _T_565 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 696:26] + node _T_566 = and(lsu_exc_acc_r, _T_565) @[dec_tlu_ctl.scala 696:24] + node _T_567 = not(take_nmi) @[dec_tlu_ctl.scala 696:42] + node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 696:40] + node _T_569 = bits(_T_568, 0, 0) @[dec_tlu_ctl.scala 696:53] + node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 697:23] + node _T_571 = not(take_nmi) @[dec_tlu_ctl.scala 697:40] + node _T_572 = and(_T_570, _T_571) @[dec_tlu_ctl.scala 697:38] + node _T_573 = bits(_T_572, 0, 0) @[dec_tlu_ctl.scala 697:51] + node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 698:24] + node _T_575 = not(take_nmi) @[dec_tlu_ctl.scala 698:41] + node _T_576 = and(_T_574, _T_575) @[dec_tlu_ctl.scala 698:39] + node _T_577 = bits(_T_576, 0, 0) @[dec_tlu_ctl.scala 698:52] node _T_578 = mux(_T_531, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_579 = mux(_T_534, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_580 = mux(_T_537, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -78981,281 +78981,281 @@ circuit quasar_wrapper : node _T_604 = or(_T_603, _T_591) @[Mux.scala 27:72] wire exc_cause_r : UInt<5> @[Mux.scala 27:72] exc_cause_r <= _T_604 @[Mux.scala 27:72] - node _T_605 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 715:23] - node _T_606 = and(_T_605, mstatus_mie_ns) @[dec_tlu_ctl.scala 715:48] - node _T_607 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 715:70] - node _T_608 = and(_T_606, _T_607) @[dec_tlu_ctl.scala 715:65] - node _T_609 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 715:91] - node _T_610 = and(_T_608, _T_609) @[dec_tlu_ctl.scala 715:83] - mhwakeup_ready <= _T_610 @[dec_tlu_ctl.scala 715:20] - node _T_611 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 716:23] - node _T_612 = and(_T_611, mstatus_mie_ns) @[dec_tlu_ctl.scala 716:48] - node _T_613 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 716:70] - node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 716:65] - node _T_615 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 716:91] - node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 716:83] - node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 716:104] - node _T_618 = and(_T_616, _T_617) @[dec_tlu_ctl.scala 716:102] - ext_int_ready <= _T_618 @[dec_tlu_ctl.scala 716:20] - node _T_619 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 717:23] - node _T_620 = and(_T_619, mstatus_mie_ns) @[dec_tlu_ctl.scala 717:48] - node _T_621 = bits(mip, 5, 5) @[dec_tlu_ctl.scala 717:70] - node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 717:65] - node _T_623 = bits(mie_ns, 5, 5) @[dec_tlu_ctl.scala 717:91] - node _T_624 = and(_T_622, _T_623) @[dec_tlu_ctl.scala 717:83] - ce_int_ready <= _T_624 @[dec_tlu_ctl.scala 717:20] - node _T_625 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 718:23] - node _T_626 = and(_T_625, mstatus_mie_ns) @[dec_tlu_ctl.scala 718:48] - node _T_627 = bits(mip, 0, 0) @[dec_tlu_ctl.scala 718:70] - node _T_628 = and(_T_626, _T_627) @[dec_tlu_ctl.scala 718:65] - node _T_629 = bits(mie_ns, 0, 0) @[dec_tlu_ctl.scala 718:91] - node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 718:83] - soft_int_ready <= _T_630 @[dec_tlu_ctl.scala 718:20] - node _T_631 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 719:23] - node _T_632 = and(_T_631, mstatus_mie_ns) @[dec_tlu_ctl.scala 719:48] - node _T_633 = bits(mip, 1, 1) @[dec_tlu_ctl.scala 719:70] - node _T_634 = and(_T_632, _T_633) @[dec_tlu_ctl.scala 719:65] - node _T_635 = bits(mie_ns, 1, 1) @[dec_tlu_ctl.scala 719:91] - node _T_636 = and(_T_634, _T_635) @[dec_tlu_ctl.scala 719:83] - timer_int_ready <= _T_636 @[dec_tlu_ctl.scala 719:20] - node _T_637 = bits(mie_ns, 4, 4) @[dec_tlu_ctl.scala 722:57] - node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[dec_tlu_ctl.scala 722:49] - node _T_638 = bits(mip, 4, 4) @[dec_tlu_ctl.scala 723:34] - node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[dec_tlu_ctl.scala 723:47] - node _T_639 = bits(mie_ns, 3, 3) @[dec_tlu_ctl.scala 724:57] - node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[dec_tlu_ctl.scala 724:49] - node _T_640 = bits(mip, 3, 3) @[dec_tlu_ctl.scala 725:34] - node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[dec_tlu_ctl.scala 725:47] - node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[dec_tlu_ctl.scala 729:52] - node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 729:74] - node int_timer_stalled = or(_T_642, mret_r) @[dec_tlu_ctl.scala 729:98] - node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 731:72] - node _T_644 = and(int_timer0_int_ready, _T_643) @[dec_tlu_ctl.scala 731:49] - node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 731:121] - node _T_646 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 731:147] - node _T_647 = and(_T_645, _T_646) @[dec_tlu_ctl.scala 731:145] - node _T_648 = not(take_ext_int_start) @[dec_tlu_ctl.scala 731:168] - node _T_649 = and(_T_647, _T_648) @[dec_tlu_ctl.scala 731:166] - node _T_650 = not(debug_mode_status) @[dec_tlu_ctl.scala 731:190] - node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 731:188] - node _T_652 = or(_T_644, _T_651) @[dec_tlu_ctl.scala 731:94] - int_timer0_int_hold <= _T_652 @[dec_tlu_ctl.scala 731:24] - node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 732:72] - node _T_654 = and(int_timer1_int_ready, _T_653) @[dec_tlu_ctl.scala 732:49] - node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 732:121] - node _T_656 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 732:147] - node _T_657 = and(_T_655, _T_656) @[dec_tlu_ctl.scala 732:145] - node _T_658 = not(take_ext_int_start) @[dec_tlu_ctl.scala 732:168] - node _T_659 = and(_T_657, _T_658) @[dec_tlu_ctl.scala 732:166] - node _T_660 = not(debug_mode_status) @[dec_tlu_ctl.scala 732:190] - node _T_661 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 732:188] - node _T_662 = or(_T_654, _T_661) @[dec_tlu_ctl.scala 732:94] - int_timer1_int_hold <= _T_662 @[dec_tlu_ctl.scala 732:24] - node _T_663 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 734:59] - node _T_664 = and(debug_mode_status, _T_663) @[dec_tlu_ctl.scala 734:57] - internal_dbg_halt_timers <= _T_664 @[dec_tlu_ctl.scala 734:29] - node _T_665 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 736:55] - node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 736:81] - node _T_667 = and(internal_dbg_halt_mode, _T_666) @[dec_tlu_ctl.scala 736:52] - node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 736:107] - node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 736:135] - node _T_670 = or(_T_669, take_nmi) @[dec_tlu_ctl.scala 736:155] - node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 736:166] - node _T_672 = or(_T_671, synchronous_flush_r) @[dec_tlu_ctl.scala 736:191] - node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 736:214] - node _T_674 = or(_T_673, mret_r) @[dec_tlu_ctl.scala 736:238] - node block_interrupts = or(_T_674, ext_int_freeze_d1) @[dec_tlu_ctl.scala 736:247] - reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 740:74] - _T_675 <= take_ext_int_start @[dec_tlu_ctl.scala 740:74] - take_ext_int_start_d1 <= _T_675 @[dec_tlu_ctl.scala 740:41] - reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 741:74] - _T_676 <= take_ext_int_start_d1 @[dec_tlu_ctl.scala 741:74] - take_ext_int_start_d2 <= _T_676 @[dec_tlu_ctl.scala 741:41] - reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 742:74] - _T_677 <= take_ext_int_start_d2 @[dec_tlu_ctl.scala 742:74] - take_ext_int_start_d3 <= _T_677 @[dec_tlu_ctl.scala 742:41] - reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 743:90] - _T_678 <= ext_int_freeze @[dec_tlu_ctl.scala 743:90] - ext_int_freeze_d1 <= _T_678 @[dec_tlu_ctl.scala 743:57] - node _T_679 = not(block_interrupts) @[dec_tlu_ctl.scala 744:68] - node _T_680 = and(ext_int_ready, _T_679) @[dec_tlu_ctl.scala 744:66] - take_ext_int_start <= _T_680 @[dec_tlu_ctl.scala 744:49] - node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[dec_tlu_ctl.scala 746:46] - node _T_682 = or(_T_681, take_ext_int_start_d2) @[dec_tlu_ctl.scala 746:70] - node _T_683 = or(_T_682, take_ext_int_start_d3) @[dec_tlu_ctl.scala 746:94] - ext_int_freeze <= _T_683 @[dec_tlu_ctl.scala 746:24] - node _T_684 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 747:67] - node _T_685 = not(_T_684) @[dec_tlu_ctl.scala 747:49] - node _T_686 = and(take_ext_int_start_d3, _T_685) @[dec_tlu_ctl.scala 747:47] - take_ext_int <= _T_686 @[dec_tlu_ctl.scala 747:22] - node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 748:49] - fast_int_meicpct <= _T_687 @[dec_tlu_ctl.scala 748:26] - ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 749:41] - node _T_688 = not(ext_int_ready) @[dec_tlu_ctl.scala 762:35] - node _T_689 = and(ce_int_ready, _T_688) @[dec_tlu_ctl.scala 762:33] - node _T_690 = not(block_interrupts) @[dec_tlu_ctl.scala 762:52] - node _T_691 = and(_T_689, _T_690) @[dec_tlu_ctl.scala 762:50] - take_ce_int <= _T_691 @[dec_tlu_ctl.scala 762:17] - node _T_692 = not(ext_int_ready) @[dec_tlu_ctl.scala 763:38] - node _T_693 = and(soft_int_ready, _T_692) @[dec_tlu_ctl.scala 763:36] - node _T_694 = not(ce_int_ready) @[dec_tlu_ctl.scala 763:55] - node _T_695 = and(_T_693, _T_694) @[dec_tlu_ctl.scala 763:53] - node _T_696 = not(block_interrupts) @[dec_tlu_ctl.scala 763:71] - node _T_697 = and(_T_695, _T_696) @[dec_tlu_ctl.scala 763:69] - take_soft_int <= _T_697 @[dec_tlu_ctl.scala 763:18] - node _T_698 = not(soft_int_ready) @[dec_tlu_ctl.scala 764:40] - node _T_699 = and(timer_int_ready, _T_698) @[dec_tlu_ctl.scala 764:38] - node _T_700 = not(ext_int_ready) @[dec_tlu_ctl.scala 764:58] - node _T_701 = and(_T_699, _T_700) @[dec_tlu_ctl.scala 764:56] - node _T_702 = not(ce_int_ready) @[dec_tlu_ctl.scala 764:75] - node _T_703 = and(_T_701, _T_702) @[dec_tlu_ctl.scala 764:73] - node _T_704 = not(block_interrupts) @[dec_tlu_ctl.scala 764:91] - node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 764:89] - take_timer_int <= _T_705 @[dec_tlu_ctl.scala 764:19] - node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 765:49] - node _T_707 = and(_T_706, int_timer0_int_possible) @[dec_tlu_ctl.scala 765:74] - node _T_708 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 765:102] - node _T_709 = and(_T_707, _T_708) @[dec_tlu_ctl.scala 765:100] - node _T_710 = not(timer_int_ready) @[dec_tlu_ctl.scala 765:129] - node _T_711 = and(_T_709, _T_710) @[dec_tlu_ctl.scala 765:127] - node _T_712 = not(soft_int_ready) @[dec_tlu_ctl.scala 765:148] - node _T_713 = and(_T_711, _T_712) @[dec_tlu_ctl.scala 765:146] - node _T_714 = not(ext_int_ready) @[dec_tlu_ctl.scala 765:166] - node _T_715 = and(_T_713, _T_714) @[dec_tlu_ctl.scala 765:164] - node _T_716 = not(ce_int_ready) @[dec_tlu_ctl.scala 765:183] - node _T_717 = and(_T_715, _T_716) @[dec_tlu_ctl.scala 765:181] - node _T_718 = not(block_interrupts) @[dec_tlu_ctl.scala 765:199] - node _T_719 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 765:197] - take_int_timer0_int <= _T_719 @[dec_tlu_ctl.scala 765:24] - node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 766:49] - node _T_721 = and(_T_720, int_timer1_int_possible) @[dec_tlu_ctl.scala 766:74] - node _T_722 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 766:102] - node _T_723 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 766:100] - node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 766:152] - node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 766:129] - node _T_726 = and(_T_723, _T_725) @[dec_tlu_ctl.scala 766:127] - node _T_727 = not(timer_int_ready) @[dec_tlu_ctl.scala 766:179] - node _T_728 = and(_T_726, _T_727) @[dec_tlu_ctl.scala 766:177] - node _T_729 = not(soft_int_ready) @[dec_tlu_ctl.scala 766:198] - node _T_730 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 766:196] - node _T_731 = not(ext_int_ready) @[dec_tlu_ctl.scala 766:216] - node _T_732 = and(_T_730, _T_731) @[dec_tlu_ctl.scala 766:214] - node _T_733 = not(ce_int_ready) @[dec_tlu_ctl.scala 766:233] - node _T_734 = and(_T_732, _T_733) @[dec_tlu_ctl.scala 766:231] - node _T_735 = not(block_interrupts) @[dec_tlu_ctl.scala 766:249] - node _T_736 = and(_T_734, _T_735) @[dec_tlu_ctl.scala 766:247] - take_int_timer1_int <= _T_736 @[dec_tlu_ctl.scala 766:24] - node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 767:32] - take_reset <= _T_737 @[dec_tlu_ctl.scala 767:15] - node _T_738 = not(internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 768:35] - node _T_739 = and(nmi_int_detected, _T_738) @[dec_tlu_ctl.scala 768:33] - node _T_740 = not(internal_dbg_halt_mode) @[dec_tlu_ctl.scala 768:65] - node _T_741 = bits(dcsr, 11, 11) @[dec_tlu_ctl.scala 768:125] - node _T_742 = and(dcsr_single_step_running_f, _T_741) @[dec_tlu_ctl.scala 768:119] - node _T_743 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 768:141] - node _T_744 = and(_T_742, _T_743) @[dec_tlu_ctl.scala 768:139] - node _T_745 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 768:166] - node _T_746 = and(_T_744, _T_745) @[dec_tlu_ctl.scala 768:164] - node _T_747 = or(_T_740, _T_746) @[dec_tlu_ctl.scala 768:89] - node _T_748 = and(_T_739, _T_747) @[dec_tlu_ctl.scala 768:62] - node _T_749 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 768:195] - node _T_750 = and(_T_748, _T_749) @[dec_tlu_ctl.scala 768:193] - node _T_751 = not(mret_r) @[dec_tlu_ctl.scala 768:218] - node _T_752 = and(_T_750, _T_751) @[dec_tlu_ctl.scala 768:216] - node _T_753 = not(take_reset) @[dec_tlu_ctl.scala 768:228] - node _T_754 = and(_T_752, _T_753) @[dec_tlu_ctl.scala 768:226] - node _T_755 = not(ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 768:242] - node _T_756 = and(_T_754, _T_755) @[dec_tlu_ctl.scala 768:240] - node _T_757 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 768:269] - node _T_758 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 768:332] - node _T_759 = and(take_ext_int_start_d3, _T_758) @[dec_tlu_ctl.scala 768:313] - node _T_760 = or(_T_757, _T_759) @[dec_tlu_ctl.scala 768:288] - node _T_761 = and(_T_756, _T_760) @[dec_tlu_ctl.scala 768:266] - take_nmi <= _T_761 @[dec_tlu_ctl.scala 768:13] - node _T_762 = or(take_ext_int, take_timer_int) @[dec_tlu_ctl.scala 771:38] - node _T_763 = or(_T_762, take_soft_int) @[dec_tlu_ctl.scala 771:55] - node _T_764 = or(_T_763, take_nmi) @[dec_tlu_ctl.scala 771:71] - node _T_765 = or(_T_764, take_ce_int) @[dec_tlu_ctl.scala 771:82] - node _T_766 = or(_T_765, take_int_timer0_int) @[dec_tlu_ctl.scala 771:96] - node _T_767 = or(_T_766, take_int_timer1_int) @[dec_tlu_ctl.scala 771:118] - interrupt_valid_r <= _T_767 @[dec_tlu_ctl.scala 771:22] - node _T_768 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 776:34] + node _T_605 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 709:23] + node _T_606 = and(_T_605, mstatus_mie_ns) @[dec_tlu_ctl.scala 709:48] + node _T_607 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 709:70] + node _T_608 = and(_T_606, _T_607) @[dec_tlu_ctl.scala 709:65] + node _T_609 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 709:91] + node _T_610 = and(_T_608, _T_609) @[dec_tlu_ctl.scala 709:83] + mhwakeup_ready <= _T_610 @[dec_tlu_ctl.scala 709:20] + node _T_611 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 710:23] + node _T_612 = and(_T_611, mstatus_mie_ns) @[dec_tlu_ctl.scala 710:48] + node _T_613 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 710:70] + node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 710:65] + node _T_615 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 710:91] + node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 710:83] + node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 710:104] + node _T_618 = and(_T_616, _T_617) @[dec_tlu_ctl.scala 710:102] + ext_int_ready <= _T_618 @[dec_tlu_ctl.scala 710:20] + node _T_619 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 711:23] + node _T_620 = and(_T_619, mstatus_mie_ns) @[dec_tlu_ctl.scala 711:48] + node _T_621 = bits(mip, 5, 5) @[dec_tlu_ctl.scala 711:70] + node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 711:65] + node _T_623 = bits(mie_ns, 5, 5) @[dec_tlu_ctl.scala 711:91] + node _T_624 = and(_T_622, _T_623) @[dec_tlu_ctl.scala 711:83] + ce_int_ready <= _T_624 @[dec_tlu_ctl.scala 711:20] + node _T_625 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 712:23] + node _T_626 = and(_T_625, mstatus_mie_ns) @[dec_tlu_ctl.scala 712:48] + node _T_627 = bits(mip, 0, 0) @[dec_tlu_ctl.scala 712:70] + node _T_628 = and(_T_626, _T_627) @[dec_tlu_ctl.scala 712:65] + node _T_629 = bits(mie_ns, 0, 0) @[dec_tlu_ctl.scala 712:91] + node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 712:83] + soft_int_ready <= _T_630 @[dec_tlu_ctl.scala 712:20] + node _T_631 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 713:23] + node _T_632 = and(_T_631, mstatus_mie_ns) @[dec_tlu_ctl.scala 713:48] + node _T_633 = bits(mip, 1, 1) @[dec_tlu_ctl.scala 713:70] + node _T_634 = and(_T_632, _T_633) @[dec_tlu_ctl.scala 713:65] + node _T_635 = bits(mie_ns, 1, 1) @[dec_tlu_ctl.scala 713:91] + node _T_636 = and(_T_634, _T_635) @[dec_tlu_ctl.scala 713:83] + timer_int_ready <= _T_636 @[dec_tlu_ctl.scala 713:20] + node _T_637 = bits(mie_ns, 4, 4) @[dec_tlu_ctl.scala 716:57] + node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[dec_tlu_ctl.scala 716:49] + node _T_638 = bits(mip, 4, 4) @[dec_tlu_ctl.scala 717:34] + node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[dec_tlu_ctl.scala 717:47] + node _T_639 = bits(mie_ns, 3, 3) @[dec_tlu_ctl.scala 718:57] + node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[dec_tlu_ctl.scala 718:49] + node _T_640 = bits(mip, 3, 3) @[dec_tlu_ctl.scala 719:34] + node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[dec_tlu_ctl.scala 719:47] + node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[dec_tlu_ctl.scala 723:52] + node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 723:74] + node int_timer_stalled = or(_T_642, mret_r) @[dec_tlu_ctl.scala 723:98] + node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 725:72] + node _T_644 = and(int_timer0_int_ready, _T_643) @[dec_tlu_ctl.scala 725:49] + node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 725:121] + node _T_646 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 725:147] + node _T_647 = and(_T_645, _T_646) @[dec_tlu_ctl.scala 725:145] + node _T_648 = not(take_ext_int_start) @[dec_tlu_ctl.scala 725:168] + node _T_649 = and(_T_647, _T_648) @[dec_tlu_ctl.scala 725:166] + node _T_650 = not(debug_mode_status) @[dec_tlu_ctl.scala 725:190] + node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 725:188] + node _T_652 = or(_T_644, _T_651) @[dec_tlu_ctl.scala 725:94] + int_timer0_int_hold <= _T_652 @[dec_tlu_ctl.scala 725:24] + node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 726:72] + node _T_654 = and(int_timer1_int_ready, _T_653) @[dec_tlu_ctl.scala 726:49] + node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 726:121] + node _T_656 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 726:147] + node _T_657 = and(_T_655, _T_656) @[dec_tlu_ctl.scala 726:145] + node _T_658 = not(take_ext_int_start) @[dec_tlu_ctl.scala 726:168] + node _T_659 = and(_T_657, _T_658) @[dec_tlu_ctl.scala 726:166] + node _T_660 = not(debug_mode_status) @[dec_tlu_ctl.scala 726:190] + node _T_661 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 726:188] + node _T_662 = or(_T_654, _T_661) @[dec_tlu_ctl.scala 726:94] + int_timer1_int_hold <= _T_662 @[dec_tlu_ctl.scala 726:24] + node _T_663 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 728:59] + node _T_664 = and(debug_mode_status, _T_663) @[dec_tlu_ctl.scala 728:57] + internal_dbg_halt_timers <= _T_664 @[dec_tlu_ctl.scala 728:29] + node _T_665 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 730:55] + node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 730:81] + node _T_667 = and(internal_dbg_halt_mode, _T_666) @[dec_tlu_ctl.scala 730:52] + node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 730:107] + node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 730:135] + node _T_670 = or(_T_669, take_nmi) @[dec_tlu_ctl.scala 730:155] + node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 730:166] + node _T_672 = or(_T_671, synchronous_flush_r) @[dec_tlu_ctl.scala 730:191] + node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 730:214] + node _T_674 = or(_T_673, mret_r) @[dec_tlu_ctl.scala 730:238] + node block_interrupts = or(_T_674, ext_int_freeze_d1) @[dec_tlu_ctl.scala 730:247] + reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 734:74] + _T_675 <= take_ext_int_start @[dec_tlu_ctl.scala 734:74] + take_ext_int_start_d1 <= _T_675 @[dec_tlu_ctl.scala 734:41] + reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 735:74] + _T_676 <= take_ext_int_start_d1 @[dec_tlu_ctl.scala 735:74] + take_ext_int_start_d2 <= _T_676 @[dec_tlu_ctl.scala 735:41] + reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 736:74] + _T_677 <= take_ext_int_start_d2 @[dec_tlu_ctl.scala 736:74] + take_ext_int_start_d3 <= _T_677 @[dec_tlu_ctl.scala 736:41] + reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 737:90] + _T_678 <= ext_int_freeze @[dec_tlu_ctl.scala 737:90] + ext_int_freeze_d1 <= _T_678 @[dec_tlu_ctl.scala 737:57] + node _T_679 = not(block_interrupts) @[dec_tlu_ctl.scala 738:68] + node _T_680 = and(ext_int_ready, _T_679) @[dec_tlu_ctl.scala 738:66] + take_ext_int_start <= _T_680 @[dec_tlu_ctl.scala 738:49] + node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[dec_tlu_ctl.scala 740:46] + node _T_682 = or(_T_681, take_ext_int_start_d2) @[dec_tlu_ctl.scala 740:70] + node _T_683 = or(_T_682, take_ext_int_start_d3) @[dec_tlu_ctl.scala 740:94] + ext_int_freeze <= _T_683 @[dec_tlu_ctl.scala 740:24] + node _T_684 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 741:67] + node _T_685 = not(_T_684) @[dec_tlu_ctl.scala 741:49] + node _T_686 = and(take_ext_int_start_d3, _T_685) @[dec_tlu_ctl.scala 741:47] + take_ext_int <= _T_686 @[dec_tlu_ctl.scala 741:22] + node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 742:49] + fast_int_meicpct <= _T_687 @[dec_tlu_ctl.scala 742:26] + ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 743:41] + node _T_688 = not(ext_int_ready) @[dec_tlu_ctl.scala 756:35] + node _T_689 = and(ce_int_ready, _T_688) @[dec_tlu_ctl.scala 756:33] + node _T_690 = not(block_interrupts) @[dec_tlu_ctl.scala 756:52] + node _T_691 = and(_T_689, _T_690) @[dec_tlu_ctl.scala 756:50] + take_ce_int <= _T_691 @[dec_tlu_ctl.scala 756:17] + node _T_692 = not(ext_int_ready) @[dec_tlu_ctl.scala 757:38] + node _T_693 = and(soft_int_ready, _T_692) @[dec_tlu_ctl.scala 757:36] + node _T_694 = not(ce_int_ready) @[dec_tlu_ctl.scala 757:55] + node _T_695 = and(_T_693, _T_694) @[dec_tlu_ctl.scala 757:53] + node _T_696 = not(block_interrupts) @[dec_tlu_ctl.scala 757:71] + node _T_697 = and(_T_695, _T_696) @[dec_tlu_ctl.scala 757:69] + take_soft_int <= _T_697 @[dec_tlu_ctl.scala 757:18] + node _T_698 = not(soft_int_ready) @[dec_tlu_ctl.scala 758:40] + node _T_699 = and(timer_int_ready, _T_698) @[dec_tlu_ctl.scala 758:38] + node _T_700 = not(ext_int_ready) @[dec_tlu_ctl.scala 758:58] + node _T_701 = and(_T_699, _T_700) @[dec_tlu_ctl.scala 758:56] + node _T_702 = not(ce_int_ready) @[dec_tlu_ctl.scala 758:75] + node _T_703 = and(_T_701, _T_702) @[dec_tlu_ctl.scala 758:73] + node _T_704 = not(block_interrupts) @[dec_tlu_ctl.scala 758:91] + node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 758:89] + take_timer_int <= _T_705 @[dec_tlu_ctl.scala 758:19] + node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 759:49] + node _T_707 = and(_T_706, int_timer0_int_possible) @[dec_tlu_ctl.scala 759:74] + node _T_708 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 759:102] + node _T_709 = and(_T_707, _T_708) @[dec_tlu_ctl.scala 759:100] + node _T_710 = not(timer_int_ready) @[dec_tlu_ctl.scala 759:129] + node _T_711 = and(_T_709, _T_710) @[dec_tlu_ctl.scala 759:127] + node _T_712 = not(soft_int_ready) @[dec_tlu_ctl.scala 759:148] + node _T_713 = and(_T_711, _T_712) @[dec_tlu_ctl.scala 759:146] + node _T_714 = not(ext_int_ready) @[dec_tlu_ctl.scala 759:166] + node _T_715 = and(_T_713, _T_714) @[dec_tlu_ctl.scala 759:164] + node _T_716 = not(ce_int_ready) @[dec_tlu_ctl.scala 759:183] + node _T_717 = and(_T_715, _T_716) @[dec_tlu_ctl.scala 759:181] + node _T_718 = not(block_interrupts) @[dec_tlu_ctl.scala 759:199] + node _T_719 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 759:197] + take_int_timer0_int <= _T_719 @[dec_tlu_ctl.scala 759:24] + node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 760:49] + node _T_721 = and(_T_720, int_timer1_int_possible) @[dec_tlu_ctl.scala 760:74] + node _T_722 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 760:102] + node _T_723 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 760:100] + node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 760:152] + node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 760:129] + node _T_726 = and(_T_723, _T_725) @[dec_tlu_ctl.scala 760:127] + node _T_727 = not(timer_int_ready) @[dec_tlu_ctl.scala 760:179] + node _T_728 = and(_T_726, _T_727) @[dec_tlu_ctl.scala 760:177] + node _T_729 = not(soft_int_ready) @[dec_tlu_ctl.scala 760:198] + node _T_730 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 760:196] + node _T_731 = not(ext_int_ready) @[dec_tlu_ctl.scala 760:216] + node _T_732 = and(_T_730, _T_731) @[dec_tlu_ctl.scala 760:214] + node _T_733 = not(ce_int_ready) @[dec_tlu_ctl.scala 760:233] + node _T_734 = and(_T_732, _T_733) @[dec_tlu_ctl.scala 760:231] + node _T_735 = not(block_interrupts) @[dec_tlu_ctl.scala 760:249] + node _T_736 = and(_T_734, _T_735) @[dec_tlu_ctl.scala 760:247] + take_int_timer1_int <= _T_736 @[dec_tlu_ctl.scala 760:24] + node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 761:32] + take_reset <= _T_737 @[dec_tlu_ctl.scala 761:15] + node _T_738 = not(internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 762:35] + node _T_739 = and(nmi_int_detected, _T_738) @[dec_tlu_ctl.scala 762:33] + node _T_740 = not(internal_dbg_halt_mode) @[dec_tlu_ctl.scala 762:65] + node _T_741 = bits(dcsr, 11, 11) @[dec_tlu_ctl.scala 762:125] + node _T_742 = and(dcsr_single_step_running_f, _T_741) @[dec_tlu_ctl.scala 762:119] + node _T_743 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 762:141] + node _T_744 = and(_T_742, _T_743) @[dec_tlu_ctl.scala 762:139] + node _T_745 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 762:166] + node _T_746 = and(_T_744, _T_745) @[dec_tlu_ctl.scala 762:164] + node _T_747 = or(_T_740, _T_746) @[dec_tlu_ctl.scala 762:89] + node _T_748 = and(_T_739, _T_747) @[dec_tlu_ctl.scala 762:62] + node _T_749 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 762:195] + node _T_750 = and(_T_748, _T_749) @[dec_tlu_ctl.scala 762:193] + node _T_751 = not(mret_r) @[dec_tlu_ctl.scala 762:218] + node _T_752 = and(_T_750, _T_751) @[dec_tlu_ctl.scala 762:216] + node _T_753 = not(take_reset) @[dec_tlu_ctl.scala 762:228] + node _T_754 = and(_T_752, _T_753) @[dec_tlu_ctl.scala 762:226] + node _T_755 = not(ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 762:242] + node _T_756 = and(_T_754, _T_755) @[dec_tlu_ctl.scala 762:240] + node _T_757 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 762:269] + node _T_758 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 762:332] + node _T_759 = and(take_ext_int_start_d3, _T_758) @[dec_tlu_ctl.scala 762:313] + node _T_760 = or(_T_757, _T_759) @[dec_tlu_ctl.scala 762:288] + node _T_761 = and(_T_756, _T_760) @[dec_tlu_ctl.scala 762:266] + take_nmi <= _T_761 @[dec_tlu_ctl.scala 762:13] + node _T_762 = or(take_ext_int, take_timer_int) @[dec_tlu_ctl.scala 765:38] + node _T_763 = or(_T_762, take_soft_int) @[dec_tlu_ctl.scala 765:55] + node _T_764 = or(_T_763, take_nmi) @[dec_tlu_ctl.scala 765:71] + node _T_765 = or(_T_764, take_ce_int) @[dec_tlu_ctl.scala 765:82] + node _T_766 = or(_T_765, take_int_timer0_int) @[dec_tlu_ctl.scala 765:96] + node _T_767 = or(_T_766, take_int_timer1_int) @[dec_tlu_ctl.scala 765:118] + interrupt_valid_r <= _T_767 @[dec_tlu_ctl.scala 765:22] + node _T_768 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 770:34] node _T_769 = cat(_T_768, UInt<1>("h00")) @[Cat.scala 29:58] node _T_770 = cat(UInt<25>("h00"), exc_cause_r) @[Cat.scala 29:58] node _T_771 = cat(_T_770, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_772 = add(_T_769, _T_771) @[dec_tlu_ctl.scala 776:51] - node vectored_path = tail(_T_772, 1) @[dec_tlu_ctl.scala 776:51] - node _T_773 = bits(take_nmi, 0, 0) @[dec_tlu_ctl.scala 777:38] - node _T_774 = bits(mtvec, 0, 0) @[dec_tlu_ctl.scala 777:67] - node _T_775 = eq(_T_774, UInt<1>("h01")) @[dec_tlu_ctl.scala 777:71] - node _T_776 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 777:104] + node _T_772 = add(_T_769, _T_771) @[dec_tlu_ctl.scala 770:51] + node vectored_path = tail(_T_772, 1) @[dec_tlu_ctl.scala 770:51] + node _T_773 = bits(take_nmi, 0, 0) @[dec_tlu_ctl.scala 771:38] + node _T_774 = bits(mtvec, 0, 0) @[dec_tlu_ctl.scala 771:67] + node _T_775 = eq(_T_774, UInt<1>("h01")) @[dec_tlu_ctl.scala 771:71] + node _T_776 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 771:104] node _T_777 = cat(_T_776, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_778 = mux(_T_775, vectored_path, _T_777) @[dec_tlu_ctl.scala 777:61] - node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[dec_tlu_ctl.scala 777:28] - node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[dec_tlu_ctl.scala 778:36] - node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 778:48] - node _T_781 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 778:96] - node _T_782 = and(i_cpu_run_req_d1, _T_781) @[dec_tlu_ctl.scala 778:94] - node _T_783 = or(_T_780, _T_782) @[dec_tlu_ctl.scala 778:74] - node _T_784 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 778:131] - node _T_785 = and(rfpc_i0_r, _T_784) @[dec_tlu_ctl.scala 778:129] - node sel_npc_r = or(_T_783, _T_785) @[dec_tlu_ctl.scala 778:116] - node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 779:43] - node sel_npc_resume = or(_T_786, pause_expired_r) @[dec_tlu_ctl.scala 779:66] - node _T_787 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 780:65] - node _T_788 = not(_T_787) @[dec_tlu_ctl.scala 780:47] - node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[dec_tlu_ctl.scala 780:45] - node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[dec_tlu_ctl.scala 781:49] - node _T_790 = or(_T_789, lsu_exc_valid_r) @[dec_tlu_ctl.scala 781:61] - node _T_791 = or(_T_790, fence_i_r) @[dec_tlu_ctl.scala 781:79] - node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 781:91] - node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 781:108] - node _T_794 = or(_T_793, debug_resume_req_f) @[dec_tlu_ctl.scala 781:135] - node _T_795 = or(_T_794, sel_npc_resume) @[dec_tlu_ctl.scala 781:157] - node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 781:175] - node _T_797 = or(_T_796, i0_trigger_hit_r) @[dec_tlu_ctl.scala 781:201] - synchronous_flush_r <= _T_797 @[dec_tlu_ctl.scala 781:25] - node _T_798 = or(interrupt_valid_r, mret_r) @[dec_tlu_ctl.scala 782:43] - node _T_799 = or(_T_798, synchronous_flush_r) @[dec_tlu_ctl.scala 782:52] - node _T_800 = or(_T_799, take_halt) @[dec_tlu_ctl.scala 782:74] - node _T_801 = or(_T_800, take_reset) @[dec_tlu_ctl.scala 782:86] - node _T_802 = or(_T_801, take_ext_int_start) @[dec_tlu_ctl.scala 782:99] - tlu_flush_lower_r <= _T_802 @[dec_tlu_ctl.scala 782:22] - node _T_803 = bits(take_reset, 0, 0) @[dec_tlu_ctl.scala 784:42] - node _T_804 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 785:72] - node _T_805 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 786:66] - node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 786:84] - node _T_807 = and(_T_805, _T_806) @[dec_tlu_ctl.scala 786:73] - node _T_808 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 787:66] - node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 787:84] - node _T_810 = and(_T_808, _T_809) @[dec_tlu_ctl.scala 787:73] - node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 787:114] - node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 787:91] - node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 787:132] - node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 787:121] - node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 788:75] - node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 788:96] - node _T_817 = and(_T_815, _T_816) @[dec_tlu_ctl.scala 788:82] - node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 789:80] - node _T_819 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 789:120] - node _T_820 = and(i0_trigger_hit_r, _T_819) @[dec_tlu_ctl.scala 789:118] - node _T_821 = or(_T_818, _T_820) @[dec_tlu_ctl.scala 789:98] - node _T_822 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 789:145] - node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 789:143] - node _T_824 = not(sel_fir_addr) @[dec_tlu_ctl.scala 789:166] - node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 789:164] - node _T_826 = bits(_T_825, 0, 0) @[dec_tlu_ctl.scala 789:181] - node _T_827 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 789:205] + node _T_778 = mux(_T_775, vectored_path, _T_777) @[dec_tlu_ctl.scala 771:61] + node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[dec_tlu_ctl.scala 771:28] + node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[dec_tlu_ctl.scala 772:36] + node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 772:48] + node _T_781 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 772:96] + node _T_782 = and(i_cpu_run_req_d1, _T_781) @[dec_tlu_ctl.scala 772:94] + node _T_783 = or(_T_780, _T_782) @[dec_tlu_ctl.scala 772:74] + node _T_784 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 772:131] + node _T_785 = and(rfpc_i0_r, _T_784) @[dec_tlu_ctl.scala 772:129] + node sel_npc_r = or(_T_783, _T_785) @[dec_tlu_ctl.scala 772:116] + node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 773:43] + node sel_npc_resume = or(_T_786, pause_expired_r) @[dec_tlu_ctl.scala 773:66] + node _T_787 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 774:65] + node _T_788 = not(_T_787) @[dec_tlu_ctl.scala 774:47] + node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[dec_tlu_ctl.scala 774:45] + node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[dec_tlu_ctl.scala 775:49] + node _T_790 = or(_T_789, lsu_exc_valid_r) @[dec_tlu_ctl.scala 775:61] + node _T_791 = or(_T_790, fence_i_r) @[dec_tlu_ctl.scala 775:79] + node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 775:91] + node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 775:108] + node _T_794 = or(_T_793, debug_resume_req_f) @[dec_tlu_ctl.scala 775:135] + node _T_795 = or(_T_794, sel_npc_resume) @[dec_tlu_ctl.scala 775:157] + node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 775:175] + node _T_797 = or(_T_796, i0_trigger_hit_r) @[dec_tlu_ctl.scala 775:201] + synchronous_flush_r <= _T_797 @[dec_tlu_ctl.scala 775:25] + node _T_798 = or(interrupt_valid_r, mret_r) @[dec_tlu_ctl.scala 776:43] + node _T_799 = or(_T_798, synchronous_flush_r) @[dec_tlu_ctl.scala 776:52] + node _T_800 = or(_T_799, take_halt) @[dec_tlu_ctl.scala 776:74] + node _T_801 = or(_T_800, take_reset) @[dec_tlu_ctl.scala 776:86] + node _T_802 = or(_T_801, take_ext_int_start) @[dec_tlu_ctl.scala 776:99] + tlu_flush_lower_r <= _T_802 @[dec_tlu_ctl.scala 776:22] + node _T_803 = bits(take_reset, 0, 0) @[dec_tlu_ctl.scala 778:42] + node _T_804 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 779:72] + node _T_805 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 780:66] + node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 780:84] + node _T_807 = and(_T_805, _T_806) @[dec_tlu_ctl.scala 780:73] + node _T_808 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 781:66] + node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 781:84] + node _T_810 = and(_T_808, _T_809) @[dec_tlu_ctl.scala 781:73] + node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 781:114] + node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 781:91] + node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 781:132] + node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 781:121] + node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 782:75] + node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 782:96] + node _T_817 = and(_T_815, _T_816) @[dec_tlu_ctl.scala 782:82] + node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 783:80] + node _T_819 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 783:120] + node _T_820 = and(i0_trigger_hit_r, _T_819) @[dec_tlu_ctl.scala 783:118] + node _T_821 = or(_T_818, _T_820) @[dec_tlu_ctl.scala 783:98] + node _T_822 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 783:145] + node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 783:143] + node _T_824 = not(sel_fir_addr) @[dec_tlu_ctl.scala 783:166] + node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 783:164] + node _T_826 = bits(_T_825, 0, 0) @[dec_tlu_ctl.scala 783:181] + node _T_827 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 783:205] node _T_828 = cat(_T_827, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_829 = not(take_nmi) @[dec_tlu_ctl.scala 790:58] - node _T_830 = and(_T_829, mret_r) @[dec_tlu_ctl.scala 790:68] - node _T_831 = bits(_T_830, 0, 0) @[dec_tlu_ctl.scala 790:78] - node _T_832 = not(take_nmi) @[dec_tlu_ctl.scala 791:58] - node _T_833 = and(_T_832, debug_resume_req_f) @[dec_tlu_ctl.scala 791:68] - node _T_834 = bits(_T_833, 0, 0) @[dec_tlu_ctl.scala 791:90] - node _T_835 = not(take_nmi) @[dec_tlu_ctl.scala 792:58] - node _T_836 = and(_T_835, sel_npc_resume) @[dec_tlu_ctl.scala 792:68] - node _T_837 = bits(_T_836, 0, 0) @[dec_tlu_ctl.scala 792:86] + node _T_829 = not(take_nmi) @[dec_tlu_ctl.scala 784:58] + node _T_830 = and(_T_829, mret_r) @[dec_tlu_ctl.scala 784:68] + node _T_831 = bits(_T_830, 0, 0) @[dec_tlu_ctl.scala 784:78] + node _T_832 = not(take_nmi) @[dec_tlu_ctl.scala 785:58] + node _T_833 = and(_T_832, debug_resume_req_f) @[dec_tlu_ctl.scala 785:68] + node _T_834 = bits(_T_833, 0, 0) @[dec_tlu_ctl.scala 785:90] + node _T_835 = not(take_nmi) @[dec_tlu_ctl.scala 786:58] + node _T_836 = and(_T_835, sel_npc_resume) @[dec_tlu_ctl.scala 786:68] + node _T_837 = bits(_T_836, 0, 0) @[dec_tlu_ctl.scala 786:86] node _T_838 = mux(_T_804, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72] node _T_839 = mux(_T_807, npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_840 = mux(_T_814, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] @@ -79273,461 +79273,461 @@ circuit quasar_wrapper : node _T_852 = or(_T_851, _T_845) @[Mux.scala 27:72] wire _T_853 : UInt<31> @[Mux.scala 27:72] _T_853 <= _T_852 @[Mux.scala 27:72] - node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[dec_tlu_ctl.scala 784:30] - reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 795:64] - tlu_flush_path_r_d1 <= tlu_flush_path_r @[dec_tlu_ctl.scala 795:64] - io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 797:41] - io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 798:49] - io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 799:49] - node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[dec_tlu_ctl.scala 802:45] - node _T_855 = or(_T_854, interrupt_valid_r) @[dec_tlu_ctl.scala 802:68] - node _T_856 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 802:110] - node _T_857 = and(i0_trigger_hit_r, _T_856) @[dec_tlu_ctl.scala 802:108] - node exc_or_int_valid_r = or(_T_855, _T_857) @[dec_tlu_ctl.scala 802:88] - reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 804:91] - _T_858 <= interrupt_valid_r @[dec_tlu_ctl.scala 804:91] - interrupt_valid_r_d1 <= _T_858 @[dec_tlu_ctl.scala 804:57] - reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 805:75] - i0_exception_valid_r_d1 <= i0_exception_valid_r @[dec_tlu_ctl.scala 805:75] - reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 806:91] - _T_859 <= exc_or_int_valid_r @[dec_tlu_ctl.scala 806:91] - exc_or_int_valid_r_d1 <= _T_859 @[dec_tlu_ctl.scala 806:57] - reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 807:91] - exc_cause_wb <= exc_cause_r @[dec_tlu_ctl.scala 807:91] - node _T_860 = not(illegal_r) @[dec_tlu_ctl.scala 808:121] - node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[dec_tlu_ctl.scala 808:119] - reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 808:99] - i0_valid_wb <= _T_861 @[dec_tlu_ctl.scala 808:99] - reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 809:83] - trigger_hit_r_d1 <= i0_trigger_hit_r @[dec_tlu_ctl.scala 809:83] - reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 810:107] - _T_862 <= take_nmi @[dec_tlu_ctl.scala 810:107] - take_nmi_r_d1 <= _T_862 @[dec_tlu_ctl.scala 810:73] - reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 811:91] - _T_863 <= pause_expired_r @[dec_tlu_ctl.scala 811:91] - pause_expired_wb <= _T_863 @[dec_tlu_ctl.scala 811:57] - inst csr of csr_tlu @[dec_tlu_ctl.scala 813:15] + node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[dec_tlu_ctl.scala 778:30] + reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 789:64] + tlu_flush_path_r_d1 <= tlu_flush_path_r @[dec_tlu_ctl.scala 789:64] + io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 791:41] + io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 792:49] + io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 793:49] + node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[dec_tlu_ctl.scala 796:45] + node _T_855 = or(_T_854, interrupt_valid_r) @[dec_tlu_ctl.scala 796:68] + node _T_856 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 796:110] + node _T_857 = and(i0_trigger_hit_r, _T_856) @[dec_tlu_ctl.scala 796:108] + node exc_or_int_valid_r = or(_T_855, _T_857) @[dec_tlu_ctl.scala 796:88] + reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 798:91] + _T_858 <= interrupt_valid_r @[dec_tlu_ctl.scala 798:91] + interrupt_valid_r_d1 <= _T_858 @[dec_tlu_ctl.scala 798:57] + reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 799:75] + i0_exception_valid_r_d1 <= i0_exception_valid_r @[dec_tlu_ctl.scala 799:75] + reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 800:91] + _T_859 <= exc_or_int_valid_r @[dec_tlu_ctl.scala 800:91] + exc_or_int_valid_r_d1 <= _T_859 @[dec_tlu_ctl.scala 800:57] + reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 801:91] + exc_cause_wb <= exc_cause_r @[dec_tlu_ctl.scala 801:91] + node _T_860 = not(illegal_r) @[dec_tlu_ctl.scala 802:121] + node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[dec_tlu_ctl.scala 802:119] + reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 802:99] + i0_valid_wb <= _T_861 @[dec_tlu_ctl.scala 802:99] + reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 803:83] + trigger_hit_r_d1 <= i0_trigger_hit_r @[dec_tlu_ctl.scala 803:83] + reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 804:107] + _T_862 <= take_nmi @[dec_tlu_ctl.scala 804:107] + take_nmi_r_d1 <= _T_862 @[dec_tlu_ctl.scala 804:73] + reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 805:91] + _T_863 <= pause_expired_r @[dec_tlu_ctl.scala 805:91] + pause_expired_wb <= _T_863 @[dec_tlu_ctl.scala 805:57] + inst csr of csr_tlu @[dec_tlu_ctl.scala 807:15] csr.clock <= clock csr.reset <= reset - csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 814:44] - csr.io.active_clk <= io.active_clk @[dec_tlu_ctl.scala 815:44] - csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 816:44] - csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 817:44] - csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 818:44] - csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 819:44] - csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 820:44] - csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 821:44] - csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 822:44] - csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 823:44] - csr.io.dma_iccm_stall_any <= io.tlu_dma.dma_iccm_stall_any @[dec_tlu_ctl.scala 824:44] - csr.io.dma_dccm_stall_any <= io.tlu_dma.dma_dccm_stall_any @[dec_tlu_ctl.scala 825:44] - csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 826:44] - csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 827:44] - csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 828:44] - csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 829:44] - csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 830:44] - csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 831:44] - csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 831:44] - csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 831:44] - csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 831:44] - csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 831:44] - csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 831:44] - csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 831:44] - csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 831:44] - csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 831:44] - csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 831:44] - csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 832:44] - csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 833:44] - csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 834:44] - csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 835:44] - csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 836:44] - csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 837:44] - csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 838:44] - csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 839:44] - csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 840:44] - csr.io.dma_pmu_dccm_write <= io.tlu_dma.dma_pmu_dccm_write @[dec_tlu_ctl.scala 841:44] - csr.io.dma_pmu_dccm_read <= io.tlu_dma.dma_pmu_dccm_read @[dec_tlu_ctl.scala 842:44] - csr.io.dma_pmu_any_write <= io.tlu_dma.dma_pmu_any_write @[dec_tlu_ctl.scala 843:44] - csr.io.dma_pmu_any_read <= io.tlu_dma.dma_pmu_any_read @[dec_tlu_ctl.scala 844:44] - csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 845:44] - csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 846:44] - csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 847:44] - csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 848:44] - csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 849:44] - csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 850:44] - csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 851:44] - csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 852:44] - csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 853:44] - csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 854:44] - csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 855:44] - csr.io.pic_pl <= io.dec_pic.pic_pl @[dec_tlu_ctl.scala 856:44] - csr.io.pic_claimid <= io.dec_pic.pic_claimid @[dec_tlu_ctl.scala 857:44] - csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 858:44] - csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 859:44] - csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 860:44] - csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 861:44] - csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 862:44] - csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 863:44] - csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 863:44] - csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 863:44] - csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 863:44] - csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 863:44] - csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 863:44] - csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 864:44] - csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 865:44] - csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 866:44] - csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 867:44] - csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 868:44] - csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 869:44] - csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 870:44] - io.dec_pic.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 871:44] - io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 872:44] - io.dec_pic.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 873:44] - io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 874:44] - io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 875:44] - io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 876:44] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 877:44] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 877:44] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 877:44] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 877:44] - io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 878:40] - io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 878:40] - io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 879:40] - io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 880:40] - io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 881:40] - io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 882:40] - io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 883:40] - io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 884:40] - io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 885:40] - io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 886:40] - io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 887:40] - io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 888:40] - io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 889:40] - io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 890:40] - io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 891:40] - io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 892:40] - io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 893:40] - io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 894:40] - io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 895:40] - io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 896:48] - io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 897:52] - io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 898:47] - io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 899:52] - io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 900:48] - io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 901:52] - io.tlu_dma.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 902:48] - csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 903:44] - csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 904:44] - csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 904:44] - csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 904:44] - csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 904:44] - csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 904:44] - csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 904:44] - csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 905:44] - csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 906:44] - csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 907:44] - csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 908:44] - csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 909:44] - csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 910:44] - csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 911:44] - csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 914:39] - csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 915:39] - csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[dec_tlu_ctl.scala 916:39] - csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 917:39] - csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 918:39] - csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 919:39] - csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 920:39] - csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 921:39] - csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 922:39] - csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[dec_tlu_ctl.scala 923:39] - csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 924:39] - csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 925:39] - csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 926:39] - csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 927:39] - csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 928:39] - csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 929:39] - csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 930:39] - csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 931:39] - csr.io.i0_exception_valid_r <= i0_exception_valid_r @[dec_tlu_ctl.scala 932:39] - csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 933:39] - csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 934:39] - csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[dec_tlu_ctl.scala 935:39] - csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 936:39] - csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 937:39] - csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 938:39] - csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 939:39] - csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 940:39] - csr.io.exc_cause_r <= exc_cause_r @[dec_tlu_ctl.scala 941:39] - csr.io.i0_valid_wb <= i0_valid_wb @[dec_tlu_ctl.scala 942:39] - csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 943:39] - csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 944:39] - csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 945:39] - csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 946:39] - csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[dec_tlu_ctl.scala 947:39] - csr.io.exc_cause_wb <= exc_cause_wb @[dec_tlu_ctl.scala 948:39] - csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 949:39] - csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 950:39] - csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 951:39] - csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 952:39] - csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 953:39] - csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 954:39] - csr.io.mdseac_locked_f <= mdseac_locked_f @[dec_tlu_ctl.scala 955:39] - csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 956:39] - csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 957:39] - csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[dec_tlu_ctl.scala 958:39] - csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[dec_tlu_ctl.scala 959:39] - csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[dec_tlu_ctl.scala 960:39] - csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[dec_tlu_ctl.scala 961:39] - csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 962:39] - csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 963:39] - csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 964:39] - csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 965:39] - csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 966:65] - csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 967:49] - csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 968:49] - csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[dec_tlu_ctl.scala 969:49] - csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 970:49] - csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 971:39] - csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 972:73] - csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 973:39] - csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 974:39] - csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 975:39] - csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 976:39] - csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 977:39] - csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 978:39] - csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 979:39] - csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 980:39] - csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 981:39] - csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 982:39] - csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 983:39] - csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 984:39] - csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 985:39] - csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 986:39] - csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 987:39] - csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 988:39] - csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 989:39] - csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 989:39] - npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 991:31] - npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 992:31] - mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 993:31] - mepc <= csr.io.mepc @[dec_tlu_ctl.scala 994:31] - mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 995:31] - force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 996:31] - dpc <= csr.io.dpc @[dec_tlu_ctl.scala 997:31] - mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 998:31] - dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 999:31] - fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 1000:31] - mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 1001:31] - dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 1002:31] - mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 1003:31] - mip <= csr.io.mip @[dec_tlu_ctl.scala 1004:31] - mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 1005:31] - mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 1005:31] - mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 1005:31] - mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 1005:31] - inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1006:22] + csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 808:44] + csr.io.active_clk <= io.active_clk @[dec_tlu_ctl.scala 809:44] + csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 810:44] + csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 811:44] + csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 812:44] + csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 813:44] + csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 814:44] + csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 815:44] + csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 816:44] + csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 817:44] + csr.io.dma_iccm_stall_any <= io.tlu_dma.dma_iccm_stall_any @[dec_tlu_ctl.scala 818:44] + csr.io.dma_dccm_stall_any <= io.tlu_dma.dma_dccm_stall_any @[dec_tlu_ctl.scala 819:44] + csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 820:44] + csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 821:44] + csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 822:44] + csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 823:44] + csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 824:44] + csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 825:44] + csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 825:44] + csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 825:44] + csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 825:44] + csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 825:44] + csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 825:44] + csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 825:44] + csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 825:44] + csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 825:44] + csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 825:44] + csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 826:44] + csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 827:44] + csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 828:44] + csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 829:44] + csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 830:44] + csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 831:44] + csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 832:44] + csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 833:44] + csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 834:44] + csr.io.dma_pmu_dccm_write <= io.tlu_dma.dma_pmu_dccm_write @[dec_tlu_ctl.scala 835:44] + csr.io.dma_pmu_dccm_read <= io.tlu_dma.dma_pmu_dccm_read @[dec_tlu_ctl.scala 836:44] + csr.io.dma_pmu_any_write <= io.tlu_dma.dma_pmu_any_write @[dec_tlu_ctl.scala 837:44] + csr.io.dma_pmu_any_read <= io.tlu_dma.dma_pmu_any_read @[dec_tlu_ctl.scala 838:44] + csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 839:44] + csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 840:44] + csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 841:44] + csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 842:44] + csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 843:44] + csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 844:44] + csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 845:44] + csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 846:44] + csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 847:44] + csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 848:44] + csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 849:44] + csr.io.pic_pl <= io.dec_pic.pic_pl @[dec_tlu_ctl.scala 850:44] + csr.io.pic_claimid <= io.dec_pic.pic_claimid @[dec_tlu_ctl.scala 851:44] + csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 852:44] + csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 853:44] + csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 854:44] + csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 855:44] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 856:44] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 857:44] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 857:44] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 857:44] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 857:44] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 857:44] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 857:44] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 858:44] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 859:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 860:44] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 861:44] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 862:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 863:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 864:44] + io.dec_pic.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 865:44] + io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 866:44] + io.dec_pic.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 867:44] + io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 868:44] + io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 869:44] + io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 870:44] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 871:44] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 871:44] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 871:44] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 871:44] + io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 872:40] + io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 872:40] + io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 873:40] + io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 874:40] + io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 875:40] + io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 876:40] + io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 877:40] + io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 878:40] + io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 879:40] + io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 880:40] + io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 881:40] + io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 882:40] + io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 883:40] + io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 884:40] + io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 885:40] + io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 886:40] + io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 887:40] + io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 888:40] + io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 889:40] + io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 890:48] + io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 891:52] + io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 892:47] + io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 893:52] + io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 894:48] + io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 895:52] + io.tlu_dma.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 896:48] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 897:44] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 898:44] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 898:44] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 898:44] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 898:44] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 898:44] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 898:44] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 899:44] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 900:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 901:44] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 902:44] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 903:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 904:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 905:44] + csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 908:39] + csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 909:39] + csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[dec_tlu_ctl.scala 910:39] + csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 911:39] + csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 912:39] + csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 913:39] + csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 914:39] + csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 915:39] + csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 916:39] + csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[dec_tlu_ctl.scala 917:39] + csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 918:39] + csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 919:39] + csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 920:39] + csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 921:39] + csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 922:39] + csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 923:39] + csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 924:39] + csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 925:39] + csr.io.i0_exception_valid_r <= i0_exception_valid_r @[dec_tlu_ctl.scala 926:39] + csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 927:39] + csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 928:39] + csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[dec_tlu_ctl.scala 929:39] + csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 930:39] + csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 931:39] + csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 932:39] + csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 933:39] + csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 934:39] + csr.io.exc_cause_r <= exc_cause_r @[dec_tlu_ctl.scala 935:39] + csr.io.i0_valid_wb <= i0_valid_wb @[dec_tlu_ctl.scala 936:39] + csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 937:39] + csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 938:39] + csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 939:39] + csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 940:39] + csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[dec_tlu_ctl.scala 941:39] + csr.io.exc_cause_wb <= exc_cause_wb @[dec_tlu_ctl.scala 942:39] + csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 943:39] + csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 944:39] + csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 945:39] + csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 946:39] + csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 947:39] + csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 948:39] + csr.io.mdseac_locked_f <= mdseac_locked_f @[dec_tlu_ctl.scala 949:39] + csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 950:39] + csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 951:39] + csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[dec_tlu_ctl.scala 952:39] + csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[dec_tlu_ctl.scala 953:39] + csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[dec_tlu_ctl.scala 954:39] + csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[dec_tlu_ctl.scala 955:39] + csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 956:39] + csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 957:39] + csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 958:39] + csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 959:39] + csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 960:65] + csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 961:49] + csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 962:49] + csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[dec_tlu_ctl.scala 963:49] + csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 964:49] + csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 965:39] + csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 966:73] + csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 967:39] + csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 968:39] + csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 969:39] + csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 970:39] + csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 971:39] + csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 972:39] + csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 973:39] + csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 974:39] + csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 975:39] + csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 976:39] + csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 977:39] + csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 978:39] + csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 979:39] + csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 980:39] + csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 981:39] + csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 982:39] + csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 983:39] + csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 983:39] + npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 985:31] + npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 986:31] + mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 987:31] + mepc <= csr.io.mepc @[dec_tlu_ctl.scala 988:31] + mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 989:31] + force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 990:31] + dpc <= csr.io.dpc @[dec_tlu_ctl.scala 991:31] + mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 992:31] + dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 993:31] + fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 994:31] + mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 995:31] + dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 996:31] + mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 997:31] + mip <= csr.io.mip @[dec_tlu_ctl.scala 998:31] + mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 999:31] + mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 999:31] + mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 999:31] + mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 999:31] + inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1000:22] csr_read.clock <= clock csr_read.reset <= reset - csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1007:37] - csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1008:16] - csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1008:16] - csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1008:16] - csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1008:16] - node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1010:42] - node _T_865 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1010:67] - node _T_866 = and(_T_864, _T_865) @[dec_tlu_ctl.scala 1010:65] - io.dec_tlu_presync_d <= _T_866 @[dec_tlu_ctl.scala 1010:23] - node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1011:43] - io.dec_tlu_postsync_d <= _T_867 @[dec_tlu_ctl.scala 1011:23] - node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1014:50] - node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1014:72] - node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1014:92] - node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1014:112] - node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1014:134] - node _T_873 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1014:159] - node conditionally_illegal = and(_T_872, _T_873) @[dec_tlu_ctl.scala 1014:157] - node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1015:55] - node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1015:73] - node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1015:92] - node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1015:115] - node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1015:136] - node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1015:158] - node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1015:179] - node _T_881 = not(_T_880) @[dec_tlu_ctl.scala 1015:36] - node _T_882 = or(_T_881, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1015:201] - node _T_883 = and(csr_pkt.legal, _T_882) @[dec_tlu_ctl.scala 1015:33] - node _T_884 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1015:223] - node _T_885 = and(_T_883, _T_884) @[dec_tlu_ctl.scala 1015:221] - node _T_886 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1015:243] - node valid_csr = and(_T_885, _T_886) @[dec_tlu_ctl.scala 1015:241] - node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1017:46] - node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1017:107] - node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1017:129] - node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1017:150] - node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1017:172] - node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1017:193] - node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[dec_tlu_ctl.scala 1017:82] - node _T_894 = not(_T_893) @[dec_tlu_ctl.scala 1017:59] - node _T_895 = and(_T_887, _T_894) @[dec_tlu_ctl.scala 1017:57] - io.dec_csr_legal_d <= _T_895 @[dec_tlu_ctl.scala 1017:20] + csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1001:37] + csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1002:16] + csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1002:16] + csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1002:16] + csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1002:16] + node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1004:42] + node _T_865 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1004:67] + node _T_866 = and(_T_864, _T_865) @[dec_tlu_ctl.scala 1004:65] + io.dec_tlu_presync_d <= _T_866 @[dec_tlu_ctl.scala 1004:23] + node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1005:43] + io.dec_tlu_postsync_d <= _T_867 @[dec_tlu_ctl.scala 1005:23] + node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1008:50] + node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1008:72] + node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1008:92] + node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1008:112] + node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1008:134] + node _T_873 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1008:159] + node conditionally_illegal = and(_T_872, _T_873) @[dec_tlu_ctl.scala 1008:157] + node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1009:55] + node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1009:73] + node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1009:92] + node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1009:115] + node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1009:136] + node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1009:158] + node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1009:179] + node _T_881 = not(_T_880) @[dec_tlu_ctl.scala 1009:36] + node _T_882 = or(_T_881, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1009:201] + node _T_883 = and(csr_pkt.legal, _T_882) @[dec_tlu_ctl.scala 1009:33] + node _T_884 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1009:223] + node _T_885 = and(_T_883, _T_884) @[dec_tlu_ctl.scala 1009:221] + node _T_886 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1009:243] + node valid_csr = and(_T_885, _T_886) @[dec_tlu_ctl.scala 1009:241] + node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1011:46] + node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1011:107] + node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1011:129] + node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1011:150] + node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1011:172] + node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1011:193] + node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[dec_tlu_ctl.scala 1011:82] + node _T_894 = not(_T_893) @[dec_tlu_ctl.scala 1011:59] + node _T_895 = and(_T_887, _T_894) @[dec_tlu_ctl.scala 1011:57] + io.dec_csr_legal_d <= _T_895 @[dec_tlu_ctl.scala 1011:20] module dec_trigger : input clock : Clock @@ -114324,7 +114324,8 @@ circuit quasar_wrapper : pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 211:29] pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 212:31] pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 213:33] - pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 214:34] + node _T_12 = cat(io.extintsrc_req, UInt<1>("h00")) @[Cat.scala 29:58] + pic_ctrl_inst.io.extintsrc_req <= _T_12 @[quasar.scala 214:34] lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 215:28] pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 215:28] pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 215:28] @@ -114597,322 +114598,322 @@ circuit quasar_wrapper : io.dma_ahb.sig.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 269:28] io.dma_ahb.sig.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 269:28] io.dma_ahb.sig.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 269:28] - wire _T_12 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 271:36] - _T_12.r.bits.last <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.r.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36] - _T_12.r.bits.data <= UInt<64>("h00") @[quasar.scala 271:36] - _T_12.r.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.r.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.r.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36] - _T_12.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36] - _T_12.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36] - _T_12.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36] - _T_12.ar.bits.size <= UInt<3>("h00") @[quasar.scala 271:36] - _T_12.ar.bits.len <= UInt<8>("h00") @[quasar.scala 271:36] - _T_12.ar.bits.region <= UInt<4>("h00") @[quasar.scala 271:36] - _T_12.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36] - _T_12.ar.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.ar.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.ar.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.b.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.b.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36] - _T_12.b.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.b.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.w.bits.last <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.w.bits.strb <= UInt<8>("h00") @[quasar.scala 271:36] - _T_12.w.bits.data <= UInt<64>("h00") @[quasar.scala 271:36] - _T_12.w.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.w.ready <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36] - _T_12.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36] - _T_12.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36] - _T_12.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36] - _T_12.aw.bits.size <= UInt<3>("h00") @[quasar.scala 271:36] - _T_12.aw.bits.len <= UInt<8>("h00") @[quasar.scala 271:36] - _T_12.aw.bits.region <= UInt<4>("h00") @[quasar.scala 271:36] - _T_12.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36] - _T_12.aw.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.aw.valid <= UInt<1>("h00") @[quasar.scala 271:36] - _T_12.aw.ready <= UInt<1>("h00") @[quasar.scala 271:36] - io.dma_axi.r.bits.last <= _T_12.r.bits.last @[quasar.scala 271:21] - io.dma_axi.r.bits.resp <= _T_12.r.bits.resp @[quasar.scala 271:21] - io.dma_axi.r.bits.data <= _T_12.r.bits.data @[quasar.scala 271:21] - io.dma_axi.r.bits.id <= _T_12.r.bits.id @[quasar.scala 271:21] - io.dma_axi.r.valid <= _T_12.r.valid @[quasar.scala 271:21] - _T_12.r.ready <= io.dma_axi.r.ready @[quasar.scala 271:21] - _T_12.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 271:21] - _T_12.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 271:21] - _T_12.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 271:21] - _T_12.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 271:21] - _T_12.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 271:21] - _T_12.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 271:21] - _T_12.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 271:21] - _T_12.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 271:21] - _T_12.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 271:21] - _T_12.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 271:21] - _T_12.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 271:21] - io.dma_axi.ar.ready <= _T_12.ar.ready @[quasar.scala 271:21] - io.dma_axi.b.bits.id <= _T_12.b.bits.id @[quasar.scala 271:21] - io.dma_axi.b.bits.resp <= _T_12.b.bits.resp @[quasar.scala 271:21] - io.dma_axi.b.valid <= _T_12.b.valid @[quasar.scala 271:21] - _T_12.b.ready <= io.dma_axi.b.ready @[quasar.scala 271:21] - _T_12.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 271:21] - _T_12.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 271:21] - _T_12.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 271:21] - _T_12.w.valid <= io.dma_axi.w.valid @[quasar.scala 271:21] - io.dma_axi.w.ready <= _T_12.w.ready @[quasar.scala 271:21] - _T_12.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 271:21] - _T_12.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 271:21] - _T_12.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 271:21] - _T_12.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 271:21] - _T_12.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 271:21] - _T_12.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 271:21] - _T_12.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 271:21] - _T_12.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 271:21] - _T_12.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 271:21] - _T_12.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 271:21] - _T_12.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 271:21] - io.dma_axi.aw.ready <= _T_12.aw.ready @[quasar.scala 271:21] - wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 272:36] - _T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36] - _T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 272:36] - _T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.r.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.r.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36] - _T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36] - _T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36] - _T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36] - _T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 272:36] - _T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 272:36] - _T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 272:36] - _T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36] - _T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36] - _T_13.b.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.b.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 272:36] - _T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 272:36] - _T_13.w.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.w.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36] - _T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36] - _T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36] - _T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36] - _T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 272:36] - _T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 272:36] - _T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 272:36] - _T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36] - _T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 272:36] - _T_13.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 272:21] - _T_13.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 272:21] - _T_13.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 272:21] - _T_13.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 272:21] - _T_13.r.valid <= io.sb_axi.r.valid @[quasar.scala 272:21] - io.sb_axi.r.ready <= _T_13.r.ready @[quasar.scala 272:21] - io.sb_axi.ar.bits.qos <= _T_13.ar.bits.qos @[quasar.scala 272:21] - io.sb_axi.ar.bits.prot <= _T_13.ar.bits.prot @[quasar.scala 272:21] - io.sb_axi.ar.bits.cache <= _T_13.ar.bits.cache @[quasar.scala 272:21] - io.sb_axi.ar.bits.lock <= _T_13.ar.bits.lock @[quasar.scala 272:21] - io.sb_axi.ar.bits.burst <= _T_13.ar.bits.burst @[quasar.scala 272:21] - io.sb_axi.ar.bits.size <= _T_13.ar.bits.size @[quasar.scala 272:21] - io.sb_axi.ar.bits.len <= _T_13.ar.bits.len @[quasar.scala 272:21] - io.sb_axi.ar.bits.region <= _T_13.ar.bits.region @[quasar.scala 272:21] - io.sb_axi.ar.bits.addr <= _T_13.ar.bits.addr @[quasar.scala 272:21] - io.sb_axi.ar.bits.id <= _T_13.ar.bits.id @[quasar.scala 272:21] - io.sb_axi.ar.valid <= _T_13.ar.valid @[quasar.scala 272:21] - _T_13.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 272:21] - _T_13.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 272:21] - _T_13.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 272:21] - _T_13.b.valid <= io.sb_axi.b.valid @[quasar.scala 272:21] - io.sb_axi.b.ready <= _T_13.b.ready @[quasar.scala 272:21] - io.sb_axi.w.bits.last <= _T_13.w.bits.last @[quasar.scala 272:21] - io.sb_axi.w.bits.strb <= _T_13.w.bits.strb @[quasar.scala 272:21] - io.sb_axi.w.bits.data <= _T_13.w.bits.data @[quasar.scala 272:21] - io.sb_axi.w.valid <= _T_13.w.valid @[quasar.scala 272:21] - _T_13.w.ready <= io.sb_axi.w.ready @[quasar.scala 272:21] - io.sb_axi.aw.bits.qos <= _T_13.aw.bits.qos @[quasar.scala 272:21] - io.sb_axi.aw.bits.prot <= _T_13.aw.bits.prot @[quasar.scala 272:21] - io.sb_axi.aw.bits.cache <= _T_13.aw.bits.cache @[quasar.scala 272:21] - io.sb_axi.aw.bits.lock <= _T_13.aw.bits.lock @[quasar.scala 272:21] - io.sb_axi.aw.bits.burst <= _T_13.aw.bits.burst @[quasar.scala 272:21] - io.sb_axi.aw.bits.size <= _T_13.aw.bits.size @[quasar.scala 272:21] - io.sb_axi.aw.bits.len <= _T_13.aw.bits.len @[quasar.scala 272:21] - io.sb_axi.aw.bits.region <= _T_13.aw.bits.region @[quasar.scala 272:21] - io.sb_axi.aw.bits.addr <= _T_13.aw.bits.addr @[quasar.scala 272:21] - io.sb_axi.aw.bits.id <= _T_13.aw.bits.id @[quasar.scala 272:21] - io.sb_axi.aw.valid <= _T_13.aw.valid @[quasar.scala 272:21] - _T_13.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 272:21] - wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 273:36] - _T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] - _T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] - _T_14.r.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_14.r.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.r.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] - _T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] - _T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] - _T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] - _T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] - _T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] - _T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] - _T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] - _T_14.ar.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.b.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] - _T_14.b.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.b.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 273:36] - _T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] - _T_14.w.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.w.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] - _T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] - _T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] - _T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] - _T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] - _T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] - _T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] - _T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] - _T_14.aw.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] - _T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 273:36] - _T_14.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 273:21] - _T_14.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 273:21] - _T_14.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 273:21] - _T_14.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 273:21] - _T_14.r.valid <= io.ifu_axi.r.valid @[quasar.scala 273:21] - io.ifu_axi.r.ready <= _T_14.r.ready @[quasar.scala 273:21] - io.ifu_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 273:21] - io.ifu_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 273:21] - io.ifu_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 273:21] - io.ifu_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 273:21] - io.ifu_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 273:21] - io.ifu_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 273:21] - io.ifu_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 273:21] - io.ifu_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 273:21] - io.ifu_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 273:21] - io.ifu_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 273:21] - io.ifu_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 273:21] - _T_14.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 273:21] - _T_14.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 273:21] - _T_14.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 273:21] - _T_14.b.valid <= io.ifu_axi.b.valid @[quasar.scala 273:21] - io.ifu_axi.b.ready <= _T_14.b.ready @[quasar.scala 273:21] - io.ifu_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 273:21] - io.ifu_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 273:21] - io.ifu_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 273:21] - io.ifu_axi.w.valid <= _T_14.w.valid @[quasar.scala 273:21] - _T_14.w.ready <= io.ifu_axi.w.ready @[quasar.scala 273:21] - io.ifu_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 273:21] - io.ifu_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 273:21] - io.ifu_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 273:21] - io.ifu_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 273:21] - io.ifu_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 273:21] - io.ifu_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 273:21] - io.ifu_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 273:21] - io.ifu_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 273:21] - io.ifu_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 273:21] - io.ifu_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 273:21] - io.ifu_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 273:21] - _T_14.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 273:21] - wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 274:36] - _T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36] - _T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 274:36] - _T_15.r.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_15.r.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.r.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36] - _T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36] - _T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36] - _T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36] - _T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 274:36] - _T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 274:36] - _T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 274:36] - _T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36] - _T_15.ar.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.b.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36] - _T_15.b.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.b.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 274:36] - _T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 274:36] - _T_15.w.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.w.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36] - _T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36] - _T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36] - _T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36] - _T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 274:36] - _T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 274:36] - _T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 274:36] - _T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36] - _T_15.aw.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] - _T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 274:36] - _T_15.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 274:21] - _T_15.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 274:21] - _T_15.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 274:21] - _T_15.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 274:21] - _T_15.r.valid <= io.lsu_axi.r.valid @[quasar.scala 274:21] - io.lsu_axi.r.ready <= _T_15.r.ready @[quasar.scala 274:21] - io.lsu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 274:21] - io.lsu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 274:21] - io.lsu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 274:21] - io.lsu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 274:21] - io.lsu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 274:21] - io.lsu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 274:21] - io.lsu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 274:21] - io.lsu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 274:21] - io.lsu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 274:21] - io.lsu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 274:21] - io.lsu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 274:21] - _T_15.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 274:21] - _T_15.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 274:21] - _T_15.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 274:21] - _T_15.b.valid <= io.lsu_axi.b.valid @[quasar.scala 274:21] - io.lsu_axi.b.ready <= _T_15.b.ready @[quasar.scala 274:21] - io.lsu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 274:21] - io.lsu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 274:21] - io.lsu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 274:21] - io.lsu_axi.w.valid <= _T_15.w.valid @[quasar.scala 274:21] - _T_15.w.ready <= io.lsu_axi.w.ready @[quasar.scala 274:21] - io.lsu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 274:21] - io.lsu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 274:21] - io.lsu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 274:21] - io.lsu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 274:21] - io.lsu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 274:21] - io.lsu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 274:21] - io.lsu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 274:21] - io.lsu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 274:21] - io.lsu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 274:21] - io.lsu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 274:21] - io.lsu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 274:21] - _T_15.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 274:21] + wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 271:36] + _T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36] + _T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 271:36] + _T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.r.valid <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.r.ready <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36] + _T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36] + _T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36] + _T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36] + _T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 271:36] + _T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 271:36] + _T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 271:36] + _T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36] + _T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36] + _T_13.b.valid <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.b.ready <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 271:36] + _T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 271:36] + _T_13.w.valid <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.w.ready <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36] + _T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36] + _T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36] + _T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36] + _T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 271:36] + _T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 271:36] + _T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 271:36] + _T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36] + _T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 271:36] + _T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 271:36] + io.dma_axi.r.bits.last <= _T_13.r.bits.last @[quasar.scala 271:21] + io.dma_axi.r.bits.resp <= _T_13.r.bits.resp @[quasar.scala 271:21] + io.dma_axi.r.bits.data <= _T_13.r.bits.data @[quasar.scala 271:21] + io.dma_axi.r.bits.id <= _T_13.r.bits.id @[quasar.scala 271:21] + io.dma_axi.r.valid <= _T_13.r.valid @[quasar.scala 271:21] + _T_13.r.ready <= io.dma_axi.r.ready @[quasar.scala 271:21] + _T_13.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 271:21] + _T_13.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 271:21] + _T_13.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 271:21] + _T_13.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 271:21] + _T_13.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 271:21] + _T_13.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 271:21] + _T_13.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 271:21] + _T_13.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 271:21] + _T_13.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 271:21] + _T_13.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 271:21] + _T_13.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 271:21] + io.dma_axi.ar.ready <= _T_13.ar.ready @[quasar.scala 271:21] + io.dma_axi.b.bits.id <= _T_13.b.bits.id @[quasar.scala 271:21] + io.dma_axi.b.bits.resp <= _T_13.b.bits.resp @[quasar.scala 271:21] + io.dma_axi.b.valid <= _T_13.b.valid @[quasar.scala 271:21] + _T_13.b.ready <= io.dma_axi.b.ready @[quasar.scala 271:21] + _T_13.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 271:21] + _T_13.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 271:21] + _T_13.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 271:21] + _T_13.w.valid <= io.dma_axi.w.valid @[quasar.scala 271:21] + io.dma_axi.w.ready <= _T_13.w.ready @[quasar.scala 271:21] + _T_13.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 271:21] + _T_13.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 271:21] + _T_13.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 271:21] + _T_13.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 271:21] + _T_13.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 271:21] + _T_13.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 271:21] + _T_13.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 271:21] + _T_13.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 271:21] + _T_13.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 271:21] + _T_13.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 271:21] + _T_13.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 271:21] + io.dma_axi.aw.ready <= _T_13.aw.ready @[quasar.scala 271:21] + wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 272:36] + _T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36] + _T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 272:36] + _T_14.r.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.r.valid <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.r.ready <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36] + _T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36] + _T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36] + _T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36] + _T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 272:36] + _T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 272:36] + _T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 272:36] + _T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36] + _T_14.ar.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.b.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36] + _T_14.b.valid <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.b.ready <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 272:36] + _T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 272:36] + _T_14.w.valid <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.w.ready <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36] + _T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36] + _T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36] + _T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36] + _T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 272:36] + _T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 272:36] + _T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 272:36] + _T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36] + _T_14.aw.bits.id <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 272:36] + _T_14.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 272:21] + _T_14.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 272:21] + _T_14.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 272:21] + _T_14.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 272:21] + _T_14.r.valid <= io.sb_axi.r.valid @[quasar.scala 272:21] + io.sb_axi.r.ready <= _T_14.r.ready @[quasar.scala 272:21] + io.sb_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 272:21] + io.sb_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 272:21] + io.sb_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 272:21] + io.sb_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 272:21] + io.sb_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 272:21] + io.sb_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 272:21] + io.sb_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 272:21] + io.sb_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 272:21] + io.sb_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 272:21] + io.sb_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 272:21] + io.sb_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 272:21] + _T_14.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 272:21] + _T_14.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 272:21] + _T_14.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 272:21] + _T_14.b.valid <= io.sb_axi.b.valid @[quasar.scala 272:21] + io.sb_axi.b.ready <= _T_14.b.ready @[quasar.scala 272:21] + io.sb_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 272:21] + io.sb_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 272:21] + io.sb_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 272:21] + io.sb_axi.w.valid <= _T_14.w.valid @[quasar.scala 272:21] + _T_14.w.ready <= io.sb_axi.w.ready @[quasar.scala 272:21] + io.sb_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 272:21] + io.sb_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 272:21] + io.sb_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 272:21] + io.sb_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 272:21] + io.sb_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 272:21] + io.sb_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 272:21] + io.sb_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 272:21] + io.sb_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 272:21] + io.sb_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 272:21] + io.sb_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 272:21] + io.sb_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 272:21] + _T_14.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 272:21] + wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 273:36] + _T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] + _T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] + _T_15.r.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] + _T_15.r.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.r.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] + _T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] + _T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] + _T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] + _T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] + _T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] + _T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] + _T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] + _T_15.ar.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] + _T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.b.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] + _T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] + _T_15.b.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.b.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 273:36] + _T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] + _T_15.w.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.w.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] + _T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] + _T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] + _T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] + _T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] + _T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] + _T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] + _T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] + _T_15.aw.bits.id <= UInt<3>("h00") @[quasar.scala 273:36] + _T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_15.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 273:21] + _T_15.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 273:21] + _T_15.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 273:21] + _T_15.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 273:21] + _T_15.r.valid <= io.ifu_axi.r.valid @[quasar.scala 273:21] + io.ifu_axi.r.ready <= _T_15.r.ready @[quasar.scala 273:21] + io.ifu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 273:21] + io.ifu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 273:21] + io.ifu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 273:21] + io.ifu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 273:21] + io.ifu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 273:21] + io.ifu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 273:21] + io.ifu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 273:21] + io.ifu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 273:21] + io.ifu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 273:21] + io.ifu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 273:21] + io.ifu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 273:21] + _T_15.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 273:21] + _T_15.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 273:21] + _T_15.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 273:21] + _T_15.b.valid <= io.ifu_axi.b.valid @[quasar.scala 273:21] + io.ifu_axi.b.ready <= _T_15.b.ready @[quasar.scala 273:21] + io.ifu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 273:21] + io.ifu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 273:21] + io.ifu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 273:21] + io.ifu_axi.w.valid <= _T_15.w.valid @[quasar.scala 273:21] + _T_15.w.ready <= io.ifu_axi.w.ready @[quasar.scala 273:21] + io.ifu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 273:21] + io.ifu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 273:21] + io.ifu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 273:21] + io.ifu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 273:21] + io.ifu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 273:21] + io.ifu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 273:21] + io.ifu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 273:21] + io.ifu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 273:21] + io.ifu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 273:21] + io.ifu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 273:21] + io.ifu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 273:21] + _T_15.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 273:21] + wire _T_16 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 274:36] + _T_16.r.bits.last <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.r.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36] + _T_16.r.bits.data <= UInt<64>("h00") @[quasar.scala 274:36] + _T_16.r.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] + _T_16.r.valid <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.r.ready <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36] + _T_16.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36] + _T_16.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36] + _T_16.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36] + _T_16.ar.bits.size <= UInt<3>("h00") @[quasar.scala 274:36] + _T_16.ar.bits.len <= UInt<8>("h00") @[quasar.scala 274:36] + _T_16.ar.bits.region <= UInt<4>("h00") @[quasar.scala 274:36] + _T_16.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36] + _T_16.ar.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] + _T_16.ar.valid <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.ar.ready <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.b.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] + _T_16.b.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36] + _T_16.b.valid <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.b.ready <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.w.bits.last <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.w.bits.strb <= UInt<8>("h00") @[quasar.scala 274:36] + _T_16.w.bits.data <= UInt<64>("h00") @[quasar.scala 274:36] + _T_16.w.valid <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.w.ready <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36] + _T_16.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36] + _T_16.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36] + _T_16.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36] + _T_16.aw.bits.size <= UInt<3>("h00") @[quasar.scala 274:36] + _T_16.aw.bits.len <= UInt<8>("h00") @[quasar.scala 274:36] + _T_16.aw.bits.region <= UInt<4>("h00") @[quasar.scala 274:36] + _T_16.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36] + _T_16.aw.bits.id <= UInt<3>("h00") @[quasar.scala 274:36] + _T_16.aw.valid <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.aw.ready <= UInt<1>("h00") @[quasar.scala 274:36] + _T_16.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 274:21] + _T_16.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 274:21] + _T_16.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 274:21] + _T_16.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 274:21] + _T_16.r.valid <= io.lsu_axi.r.valid @[quasar.scala 274:21] + io.lsu_axi.r.ready <= _T_16.r.ready @[quasar.scala 274:21] + io.lsu_axi.ar.bits.qos <= _T_16.ar.bits.qos @[quasar.scala 274:21] + io.lsu_axi.ar.bits.prot <= _T_16.ar.bits.prot @[quasar.scala 274:21] + io.lsu_axi.ar.bits.cache <= _T_16.ar.bits.cache @[quasar.scala 274:21] + io.lsu_axi.ar.bits.lock <= _T_16.ar.bits.lock @[quasar.scala 274:21] + io.lsu_axi.ar.bits.burst <= _T_16.ar.bits.burst @[quasar.scala 274:21] + io.lsu_axi.ar.bits.size <= _T_16.ar.bits.size @[quasar.scala 274:21] + io.lsu_axi.ar.bits.len <= _T_16.ar.bits.len @[quasar.scala 274:21] + io.lsu_axi.ar.bits.region <= _T_16.ar.bits.region @[quasar.scala 274:21] + io.lsu_axi.ar.bits.addr <= _T_16.ar.bits.addr @[quasar.scala 274:21] + io.lsu_axi.ar.bits.id <= _T_16.ar.bits.id @[quasar.scala 274:21] + io.lsu_axi.ar.valid <= _T_16.ar.valid @[quasar.scala 274:21] + _T_16.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 274:21] + _T_16.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 274:21] + _T_16.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 274:21] + _T_16.b.valid <= io.lsu_axi.b.valid @[quasar.scala 274:21] + io.lsu_axi.b.ready <= _T_16.b.ready @[quasar.scala 274:21] + io.lsu_axi.w.bits.last <= _T_16.w.bits.last @[quasar.scala 274:21] + io.lsu_axi.w.bits.strb <= _T_16.w.bits.strb @[quasar.scala 274:21] + io.lsu_axi.w.bits.data <= _T_16.w.bits.data @[quasar.scala 274:21] + io.lsu_axi.w.valid <= _T_16.w.valid @[quasar.scala 274:21] + _T_16.w.ready <= io.lsu_axi.w.ready @[quasar.scala 274:21] + io.lsu_axi.aw.bits.qos <= _T_16.aw.bits.qos @[quasar.scala 274:21] + io.lsu_axi.aw.bits.prot <= _T_16.aw.bits.prot @[quasar.scala 274:21] + io.lsu_axi.aw.bits.cache <= _T_16.aw.bits.cache @[quasar.scala 274:21] + io.lsu_axi.aw.bits.lock <= _T_16.aw.bits.lock @[quasar.scala 274:21] + io.lsu_axi.aw.bits.burst <= _T_16.aw.bits.burst @[quasar.scala 274:21] + io.lsu_axi.aw.bits.size <= _T_16.aw.bits.size @[quasar.scala 274:21] + io.lsu_axi.aw.bits.len <= _T_16.aw.bits.len @[quasar.scala 274:21] + io.lsu_axi.aw.bits.region <= _T_16.aw.bits.region @[quasar.scala 274:21] + io.lsu_axi.aw.bits.addr <= _T_16.aw.bits.addr @[quasar.scala 274:21] + io.lsu_axi.aw.bits.id <= _T_16.aw.bits.id @[quasar.scala 274:21] + io.lsu_axi.aw.valid <= _T_16.aw.valid @[quasar.scala 274:21] + _T_16.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 274:21] module quasar_wrapper : input clock : Clock diff --git a/design/quasar_wrapper.v b/design/quasar_wrapper.v index 038c8c13..8e3f75a1 100644 --- a/design/quasar_wrapper.v +++ b/design/quasar_wrapper.v @@ -50182,56 +50182,56 @@ module dec_timer_ctl( wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] reg [31:0] mitcnt0; // @[lib.scala 374:16] reg [31:0] mitb0_b; // @[lib.scala 374:16] - wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2694:22] - wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2655:36] + wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2688:22] + wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2649:36] reg [31:0] mitcnt1; // @[lib.scala 374:16] reg [31:0] mitb1_b; // @[lib.scala 374:16] - wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2703:18] - wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2656:36] - wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2666:72] - wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2666:49] - reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2719:67] - reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2718:60] - wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2719:90] + wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2697:18] + wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2650:36] + wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2660:72] + wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2660:49] + reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2713:67] + reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2712:60] + wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2713:90] wire [2:0] mitctl0 = {_T_57,_T_58}; // @[Cat.scala 29:58] - wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2668:56] - wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2668:76] - wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2668:53] - wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2668:112] - wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2668:138] - wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2668:109] - wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2668:173] - wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2668:171] - wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2669:35] - wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2671:59] - wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2678:72] - wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2678:49] - reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2733:52] - reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2732:55] - wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2733:75] + wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2662:56] + wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2662:76] + wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2662:53] + wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2662:112] + wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2662:138] + wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2662:109] + wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2662:173] + wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2662:171] + wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2663:35] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2665:59] + wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2672:72] + wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2672:49] + reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2727:52] + reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2726:55] + wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2727:75] wire [3:0] mitctl1 = {_T_66,_T_67}; // @[Cat.scala 29:58] - wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2680:76] - wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2680:53] - wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2680:138] - wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2680:109] - wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2680:171] - wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2683:60] - wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2683:72] + wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2674:76] + wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2674:53] + wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2674:138] + wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2674:109] + wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2674:171] + wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2677:60] + wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2677:72] wire [31:0] _T_34 = {31'h0,_T_33}; // @[Cat.scala 29:58] - wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2683:35] - wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2685:60] - wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2692:70] - wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2701:69] - wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2714:72] - wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2714:49] - wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2715:31] - wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2729:71] - wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2729:49] - wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2730:31] - wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2735:51] - wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2735:68] - wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2735:83] - wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2735:98] + wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2677:35] + wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2679:60] + wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2686:70] + wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2695:69] + wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2708:72] + wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2708:49] + wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2709:31] + wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2723:71] + wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2723:49] + wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2724:31] + wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2729:51] + wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2729:68] + wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2729:83] + wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2729:98] wire [31:0] _T_81 = {29'h0,_T_57,_T_58}; // @[Cat.scala 29:58] wire [31:0] _T_84 = {28'h0,_T_66,_T_67}; // @[Cat.scala 29:58] wire [31:0] _T_85 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72] @@ -50268,10 +50268,10 @@ module dec_timer_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2736:33] - assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2735:33] - assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2658:31] - assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2659:31] + assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2730:33] + assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2729:33] + assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2652:31] + assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2653:31] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -50919,36 +50919,36 @@ module csr_tlu( wire rvclkhdr_34_io_clk; // @[lib.scala 343:22] wire rvclkhdr_34_io_en; // @[lib.scala 343:22] wire rvclkhdr_34_io_scan_mode; // @[lib.scala 343:22] - wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1431:45] - wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1431:43] - wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1431:68] - wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1432:71] - wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1432:42] - wire _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1818:68] - wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1818:39] - wire _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1826:37] - reg mpmc_b; // @[dec_tlu_ctl.scala 1828:44] - wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1831:10] - wire _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1826:62] - wire mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1826:18] - wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1435:28] - wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1435:39] - wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1438:5] - wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1438:19] + wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1425:45] + wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1425:43] + wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1425:68] + wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1426:71] + wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1426:42] + wire _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1812:68] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1812:39] + wire _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1820:37] + reg mpmc_b; // @[dec_tlu_ctl.scala 1822:44] + wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1825:10] + wire _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1820:62] + wire mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1820:18] + wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1429:28] + wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1429:39] + wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1432:5] + wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1432:19] wire [1:0] _T_12 = {io_mstatus[0],1'h0}; // @[Cat.scala 29:58] - wire _T_13 = wr_mstatus_r & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1439:18] + wire _T_13 = wr_mstatus_r & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1433:18] wire [1:0] _T_16 = {io_dec_csr_wrdata_r[3],1'h0}; // @[Cat.scala 29:58] - wire _T_17 = ~io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1440:17] - wire _T_18 = io_mret_r & _T_17; // @[dec_tlu_ctl.scala 1440:15] + wire _T_17 = ~io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1434:17] + wire _T_18 = io_mret_r & _T_17; // @[dec_tlu_ctl.scala 1434:15] wire [1:0] _T_21 = {1'h1,io_mstatus[1]}; // @[Cat.scala 29:58] wire [1:0] _T_24 = {io_mstatus[1],1'h1}; // @[Cat.scala 29:58] - wire _T_26 = wr_mstatus_r & _T_17; // @[dec_tlu_ctl.scala 1442:18] + wire _T_26 = wr_mstatus_r & _T_17; // @[dec_tlu_ctl.scala 1436:18] wire [1:0] _T_30 = {io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] - wire _T_33 = _T_7 & _T_17; // @[dec_tlu_ctl.scala 1443:19] - wire _T_34 = ~io_mret_r; // @[dec_tlu_ctl.scala 1443:46] - wire _T_35 = _T_33 & _T_34; // @[dec_tlu_ctl.scala 1443:44] - wire _T_36 = ~set_mie_pmu_fw_halt; // @[dec_tlu_ctl.scala 1443:59] - wire _T_37 = _T_35 & _T_36; // @[dec_tlu_ctl.scala 1443:57] + wire _T_33 = _T_7 & _T_17; // @[dec_tlu_ctl.scala 1437:19] + wire _T_34 = ~io_mret_r; // @[dec_tlu_ctl.scala 1437:46] + wire _T_35 = _T_33 & _T_34; // @[dec_tlu_ctl.scala 1437:44] + wire _T_36 = ~set_mie_pmu_fw_halt; // @[dec_tlu_ctl.scala 1437:59] + wire _T_37 = _T_35 & _T_36; // @[dec_tlu_ctl.scala 1437:57] wire [1:0] _T_39 = _T_8 ? _T_12 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_40 = _T_13 ? _T_16 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_41 = _T_18 ? _T_21 : 2'h0; // @[Mux.scala 27:72] @@ -50959,155 +50959,155 @@ module csr_tlu( wire [1:0] _T_46 = _T_45 | _T_41; // @[Mux.scala 27:72] wire [1:0] _T_47 = _T_46 | _T_42; // @[Mux.scala 27:72] wire [1:0] _T_48 = _T_47 | _T_43; // @[Mux.scala 27:72] - wire _T_52 = ~io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 1446:50] - wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1446:81] - reg [1:0] _T_56; // @[dec_tlu_ctl.scala 1448:11] - wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1457:69] + wire _T_52 = ~io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 1440:50] + wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1440:81] + reg [1:0] _T_56; // @[dec_tlu_ctl.scala 1442:11] + wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1451:69] reg [30:0] _T_62; // @[lib.scala 374:16] reg [31:0] mdccmect; // @[lib.scala 374:16] - wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1878:41] + wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1872:41] wire [31:0] _T_566 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1878:61] - wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1878:61] - wire mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1878:94] + wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1872:61] + wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1872:61] + wire mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1872:94] reg [31:0] miccmect; // @[lib.scala 374:16] - wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1863:40] + wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1857:40] wire [31:0] _T_546 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1863:60] - wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1863:60] - wire miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1863:93] - wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1471:30] + wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1857:60] + wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1857:60] + wire miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1857:93] + wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1465:30] reg [31:0] micect; // @[lib.scala 374:16] - wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1848:39] + wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1842:39] wire [31:0] _T_524 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1848:57] - wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1848:57] - wire mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1848:88] - wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1471:46] + wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1842:57] + wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1842:57] + wire mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1842:88] + wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1465:46] wire [2:0] _T_65 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_67 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] - reg [5:0] _T_68; // @[dec_tlu_ctl.scala 1475:11] - wire _T_70 = io_dec_csr_wraddr_r == 12'h304; // @[dec_tlu_ctl.scala 1487:67] - wire wr_mie_r = io_dec_csr_wen_r_mod & _T_70; // @[dec_tlu_ctl.scala 1487:38] + reg [5:0] _T_68; // @[dec_tlu_ctl.scala 1469:11] + wire _T_70 = io_dec_csr_wraddr_r == 12'h304; // @[dec_tlu_ctl.scala 1481:67] + wire wr_mie_r = io_dec_csr_wen_r_mod & _T_70; // @[dec_tlu_ctl.scala 1481:38] wire [5:0] _T_78 = {io_dec_csr_wrdata_r[30:28],io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] - reg [5:0] mie; // @[dec_tlu_ctl.scala 1490:11] - wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[dec_tlu_ctl.scala 1497:54] - wire _T_83 = io_dec_csr_wraddr_r == 12'hb00; // @[dec_tlu_ctl.scala 1499:71] - wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_83; // @[dec_tlu_ctl.scala 1499:42] - wire _T_85 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 1501:71] - wire _T_86 = kill_ebreak_count_r | _T_85; // @[dec_tlu_ctl.scala 1501:46] - wire _T_87 = _T_86 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1501:94] + reg [5:0] mie; // @[dec_tlu_ctl.scala 1484:11] + wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[dec_tlu_ctl.scala 1491:54] + wire _T_83 = io_dec_csr_wraddr_r == 12'hb00; // @[dec_tlu_ctl.scala 1493:71] + wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_83; // @[dec_tlu_ctl.scala 1493:42] + wire _T_85 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 1495:71] + wire _T_86 = kill_ebreak_count_r | _T_85; // @[dec_tlu_ctl.scala 1495:46] + wire _T_87 = _T_86 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1495:94] reg [4:0] temp_ncount6_2; // @[Reg.scala 27:20] reg temp_ncount0; // @[Reg.scala 27:20] wire [6:0] mcountinhibit = {temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire _T_89 = _T_87 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1501:121] - wire mcyclel_cout_in = ~_T_89; // @[dec_tlu_ctl.scala 1501:24] + wire _T_89 = _T_87 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1495:121] + wire mcyclel_cout_in = ~_T_89; // @[dec_tlu_ctl.scala 1495:24] wire [31:0] _T_90 = {31'h0,mcyclel_cout_in}; // @[Cat.scala 29:58] reg [31:0] mcyclel; // @[lib.scala 374:16] - wire [32:0] mcyclel_inc = mcyclel + _T_90; // @[dec_tlu_ctl.scala 1505:25] - wire mcyclel_cout = mcyclel_inc[32]; // @[dec_tlu_ctl.scala 1507:32] - wire _T_101 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1515:68] - wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_101; // @[dec_tlu_ctl.scala 1515:39] - wire _T_98 = ~wr_mcycleh_r; // @[dec_tlu_ctl.scala 1509:71] - reg mcyclel_cout_f; // @[dec_tlu_ctl.scala 1509:54] + wire [32:0] mcyclel_inc = mcyclel + _T_90; // @[dec_tlu_ctl.scala 1499:25] + wire mcyclel_cout = mcyclel_inc[32]; // @[dec_tlu_ctl.scala 1501:32] + wire _T_101 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1509:68] + wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_101; // @[dec_tlu_ctl.scala 1509:39] + wire _T_98 = ~wr_mcycleh_r; // @[dec_tlu_ctl.scala 1503:71] + reg mcyclel_cout_f; // @[dec_tlu_ctl.scala 1503:54] wire [31:0] _T_103 = {31'h0,mcyclel_cout_f}; // @[Cat.scala 29:58] reg [31:0] mcycleh; // @[lib.scala 374:16] - wire [31:0] mcycleh_inc = mcycleh + _T_103; // @[dec_tlu_ctl.scala 1517:28] - wire _T_109 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1534:72] - wire _T_110 = _T_109 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1534:85] - wire _T_111 = _T_110 | io_illegal_r; // @[dec_tlu_ctl.scala 1534:113] - wire _T_113 = _T_111 | mcountinhibit[2]; // @[dec_tlu_ctl.scala 1534:128] - wire _T_115 = ~_T_113; // @[dec_tlu_ctl.scala 1534:58] - wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_115; // @[dec_tlu_ctl.scala 1534:56] - wire _T_117 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1536:73] - wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_117; // @[dec_tlu_ctl.scala 1536:44] + wire [31:0] mcycleh_inc = mcycleh + _T_103; // @[dec_tlu_ctl.scala 1511:28] + wire _T_109 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1528:72] + wire _T_110 = _T_109 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1528:85] + wire _T_111 = _T_110 | io_illegal_r; // @[dec_tlu_ctl.scala 1528:113] + wire _T_113 = _T_111 | mcountinhibit[2]; // @[dec_tlu_ctl.scala 1528:128] + wire _T_115 = ~_T_113; // @[dec_tlu_ctl.scala 1528:58] + wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_115; // @[dec_tlu_ctl.scala 1528:56] + wire _T_117 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1530:73] + wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_117; // @[dec_tlu_ctl.scala 1530:44] wire [31:0] _T_118 = {31'h0,i0_valid_no_ebreak_ecall_r}; // @[Cat.scala 29:58] reg [31:0] minstretl; // @[lib.scala 374:16] - wire [32:0] minstretl_inc = minstretl + _T_118; // @[dec_tlu_ctl.scala 1538:29] - wire minstretl_cout = minstretl_inc[32]; // @[dec_tlu_ctl.scala 1539:36] - reg minstret_enable_f; // @[dec_tlu_ctl.scala 1544:56] - wire _T_128 = io_dec_csr_wraddr_r == 12'hb82; // @[dec_tlu_ctl.scala 1553:71] - wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_128; // @[dec_tlu_ctl.scala 1553:42] - wire _T_125 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1545:75] - reg minstretl_cout_f; // @[dec_tlu_ctl.scala 1545:56] + wire [32:0] minstretl_inc = minstretl + _T_118; // @[dec_tlu_ctl.scala 1532:29] + wire minstretl_cout = minstretl_inc[32]; // @[dec_tlu_ctl.scala 1533:36] + reg minstret_enable_f; // @[dec_tlu_ctl.scala 1538:56] + wire _T_128 = io_dec_csr_wraddr_r == 12'hb82; // @[dec_tlu_ctl.scala 1547:71] + wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_128; // @[dec_tlu_ctl.scala 1547:42] + wire _T_125 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1539:75] + reg minstretl_cout_f; // @[dec_tlu_ctl.scala 1539:56] wire [31:0] _T_131 = {31'h0,minstretl_cout_f}; // @[Cat.scala 29:58] reg [31:0] minstreth; // @[lib.scala 374:16] - wire [31:0] minstreth_inc = minstreth + _T_131; // @[dec_tlu_ctl.scala 1556:29] - wire _T_139 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1567:72] + wire [31:0] minstreth_inc = minstreth + _T_131; // @[dec_tlu_ctl.scala 1550:29] + wire _T_139 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1561:72] reg [31:0] mscratch; // @[lib.scala 374:16] - wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1578:22] - wire _T_143 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1578:47] - wire _T_144 = _T_142 & _T_143; // @[dec_tlu_ctl.scala 1578:45] - wire sel_exu_npc_r = _T_144 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1578:72] - wire _T_146 = _T_142 & io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1579:47] - wire _T_147 = ~io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 1579:75] - wire sel_flush_npc_r = _T_146 & _T_147; // @[dec_tlu_ctl.scala 1579:73] - wire _T_148 = ~sel_exu_npc_r; // @[dec_tlu_ctl.scala 1580:23] - wire _T_149 = ~sel_flush_npc_r; // @[dec_tlu_ctl.scala 1580:40] - wire sel_hold_npc_r = _T_148 & _T_149; // @[dec_tlu_ctl.scala 1580:38] - wire _T_151 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 1584:13] - wire _T_152 = _T_151 & io_reset_delayed; // @[dec_tlu_ctl.scala 1584:35] + wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1572:22] + wire _T_143 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1572:47] + wire _T_144 = _T_142 & _T_143; // @[dec_tlu_ctl.scala 1572:45] + wire sel_exu_npc_r = _T_144 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1572:72] + wire _T_146 = _T_142 & io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1573:47] + wire _T_147 = ~io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 1573:75] + wire sel_flush_npc_r = _T_146 & _T_147; // @[dec_tlu_ctl.scala 1573:73] + wire _T_148 = ~sel_exu_npc_r; // @[dec_tlu_ctl.scala 1574:23] + wire _T_149 = ~sel_flush_npc_r; // @[dec_tlu_ctl.scala 1574:40] + wire sel_hold_npc_r = _T_148 & _T_149; // @[dec_tlu_ctl.scala 1574:38] + wire _T_151 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 1578:13] + wire _T_152 = _T_151 & io_reset_delayed; // @[dec_tlu_ctl.scala 1578:35] wire [30:0] _T_156 = sel_exu_npc_r ? io_exu_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_157 = _T_152 ? io_rst_vec : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_158 = sel_flush_npc_r ? io_tlu_flush_path_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_159 = sel_hold_npc_r ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_160 = _T_156 | _T_157; // @[Mux.scala 27:72] wire [30:0] _T_161 = _T_160 | _T_158; // @[Mux.scala 27:72] - wire _T_164 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1588:48] + wire _T_164 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1582:48] reg [30:0] _T_167; // @[lib.scala 374:16] - wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1591:44] - wire _T_170 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1595:22] + wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1585:44] + wire _T_170 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1589:22] wire [30:0] _T_171 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] reg [30:0] pc_r_d1; // @[lib.scala 374:16] wire [30:0] _T_172 = _T_170 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] pc_r = _T_171 | _T_172; // @[Mux.scala 27:72] - wire _T_176 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1599:68] - wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_176; // @[dec_tlu_ctl.scala 1599:39] - wire _T_177 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1602:27] - wire _T_178 = _T_177 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1602:48] - wire _T_182 = wr_mepc_r & _T_17; // @[dec_tlu_ctl.scala 1604:13] - wire _T_185 = ~wr_mepc_r; // @[dec_tlu_ctl.scala 1605:3] - wire _T_187 = _T_185 & _T_17; // @[dec_tlu_ctl.scala 1605:14] + wire _T_176 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1593:68] + wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_176; // @[dec_tlu_ctl.scala 1593:39] + wire _T_177 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1596:27] + wire _T_178 = _T_177 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1596:48] + wire _T_182 = wr_mepc_r & _T_17; // @[dec_tlu_ctl.scala 1598:13] + wire _T_185 = ~wr_mepc_r; // @[dec_tlu_ctl.scala 1599:3] + wire _T_187 = _T_185 & _T_17; // @[dec_tlu_ctl.scala 1599:14] wire [30:0] _T_189 = _T_178 ? pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_190 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_191 = _T_182 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_192 = _T_187 ? io_mepc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_193 = _T_189 | _T_190; // @[Mux.scala 27:72] wire [30:0] _T_194 = _T_193 | _T_191; // @[Mux.scala 27:72] - reg [30:0] _T_196; // @[dec_tlu_ctl.scala 1607:47] - wire _T_198 = io_dec_csr_wraddr_r == 12'h342; // @[dec_tlu_ctl.scala 1614:72] - wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_198; // @[dec_tlu_ctl.scala 1614:43] - wire _T_199 = io_exc_or_int_valid_r & io_take_nmi; // @[dec_tlu_ctl.scala 1615:53] - wire mcause_sel_nmi_store = _T_199 & io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 1615:67] - wire mcause_sel_nmi_load = _T_199 & io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 1616:66] - wire _T_202 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 1617:84] - wire mcause_sel_nmi_ext = _T_199 & _T_202; // @[dec_tlu_ctl.scala 1617:65] - wire _T_203 = &io_lsu_fir_error; // @[dec_tlu_ctl.scala 1623:53] - wire _T_206 = ~io_lsu_fir_error[0]; // @[dec_tlu_ctl.scala 1623:82] - wire _T_207 = io_lsu_fir_error[1] & _T_206; // @[dec_tlu_ctl.scala 1623:80] + reg [30:0] _T_196; // @[dec_tlu_ctl.scala 1601:47] + wire _T_198 = io_dec_csr_wraddr_r == 12'h342; // @[dec_tlu_ctl.scala 1608:72] + wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_198; // @[dec_tlu_ctl.scala 1608:43] + wire _T_199 = io_exc_or_int_valid_r & io_take_nmi; // @[dec_tlu_ctl.scala 1609:53] + wire mcause_sel_nmi_store = _T_199 & io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 1609:67] + wire mcause_sel_nmi_load = _T_199 & io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 1610:66] + wire _T_202 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 1611:84] + wire mcause_sel_nmi_ext = _T_199 & _T_202; // @[dec_tlu_ctl.scala 1611:65] + wire _T_203 = &io_lsu_fir_error; // @[dec_tlu_ctl.scala 1617:53] + wire _T_206 = ~io_lsu_fir_error[0]; // @[dec_tlu_ctl.scala 1617:82] + wire _T_207 = io_lsu_fir_error[1] & _T_206; // @[dec_tlu_ctl.scala 1617:80] wire [31:0] _T_212 = {30'h3c000400,_T_203,_T_207}; // @[Cat.scala 29:58] - wire _T_213 = ~io_take_nmi; // @[dec_tlu_ctl.scala 1629:56] - wire _T_214 = io_exc_or_int_valid_r & _T_213; // @[dec_tlu_ctl.scala 1629:54] + wire _T_213 = ~io_take_nmi; // @[dec_tlu_ctl.scala 1623:56] + wire _T_214 = io_exc_or_int_valid_r & _T_213; // @[dec_tlu_ctl.scala 1623:54] wire [31:0] _T_217 = {io_interrupt_valid_r,26'h0,io_exc_cause_r}; // @[Cat.scala 29:58] - wire _T_219 = wr_mcause_r & _T_17; // @[dec_tlu_ctl.scala 1630:44] - wire _T_221 = ~wr_mcause_r; // @[dec_tlu_ctl.scala 1631:32] - wire _T_223 = _T_221 & _T_17; // @[dec_tlu_ctl.scala 1631:45] + wire _T_219 = wr_mcause_r & _T_17; // @[dec_tlu_ctl.scala 1624:44] + wire _T_221 = ~wr_mcause_r; // @[dec_tlu_ctl.scala 1625:32] + wire _T_223 = _T_221 & _T_17; // @[dec_tlu_ctl.scala 1625:45] wire [31:0] _T_225 = mcause_sel_nmi_store ? 32'hf0000000 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_226 = mcause_sel_nmi_load ? 32'hf0000001 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_227 = mcause_sel_nmi_ext ? _T_212 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_228 = _T_214 ? _T_217 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_229 = _T_219 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] - reg [31:0] mcause; // @[dec_tlu_ctl.scala 1633:49] + reg [31:0] mcause; // @[dec_tlu_ctl.scala 1627:49] wire [31:0] _T_230 = _T_223 ? mcause : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_231 = _T_225 | _T_226; // @[Mux.scala 27:72] wire [31:0] _T_232 = _T_231 | _T_227; // @[Mux.scala 27:72] wire [31:0] _T_233 = _T_232 | _T_228; // @[Mux.scala 27:72] wire [31:0] _T_234 = _T_233 | _T_229; // @[Mux.scala 27:72] - wire _T_238 = io_dec_csr_wraddr_r == 12'h7ff; // @[dec_tlu_ctl.scala 1640:71] - wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_238; // @[dec_tlu_ctl.scala 1640:42] - wire _T_239 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[dec_tlu_ctl.scala 1642:56] + wire _T_238 = io_dec_csr_wraddr_r == 12'h7ff; // @[dec_tlu_ctl.scala 1634:71] + wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_238; // @[dec_tlu_ctl.scala 1634:42] + wire _T_239 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[dec_tlu_ctl.scala 1636:56] wire [3:0] _T_240 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] - wire [3:0] ifu_mscause = _T_239 ? 4'h9 : _T_240; // @[dec_tlu_ctl.scala 1642:24] + wire [3:0] ifu_mscause = _T_239 ? 4'h9 : _T_240; // @[dec_tlu_ctl.scala 1636:24] wire [3:0] _T_245 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72] wire [1:0] _T_247 = io_ebreak_r ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [3:0] _T_248 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] @@ -51116,189 +51116,189 @@ module csr_tlu( wire [3:0] _GEN_13 = {{2'd0}, _T_247}; // @[Mux.scala 27:72] wire [3:0] _T_250 = _T_249 | _GEN_13; // @[Mux.scala 27:72] wire [3:0] mscause_type = _T_250 | _T_248; // @[Mux.scala 27:72] - wire _T_254 = wr_mscause_r & _T_17; // @[dec_tlu_ctl.scala 1653:38] - wire _T_257 = ~wr_mscause_r; // @[dec_tlu_ctl.scala 1654:25] - wire _T_259 = _T_257 & _T_17; // @[dec_tlu_ctl.scala 1654:39] + wire _T_254 = wr_mscause_r & _T_17; // @[dec_tlu_ctl.scala 1647:38] + wire _T_257 = ~wr_mscause_r; // @[dec_tlu_ctl.scala 1648:25] + wire _T_259 = _T_257 & _T_17; // @[dec_tlu_ctl.scala 1648:39] wire [3:0] _T_261 = io_exc_or_int_valid_r ? mscause_type : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_262 = _T_254 ? io_dec_csr_wrdata_r[3:0] : 4'h0; // @[Mux.scala 27:72] - reg [3:0] mscause; // @[dec_tlu_ctl.scala 1656:47] + reg [3:0] mscause; // @[dec_tlu_ctl.scala 1650:47] wire [3:0] _T_263 = _T_259 ? mscause : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_264 = _T_261 | _T_262; // @[Mux.scala 27:72] - wire _T_268 = io_dec_csr_wraddr_r == 12'h343; // @[dec_tlu_ctl.scala 1663:69] - wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_268; // @[dec_tlu_ctl.scala 1663:40] - wire _T_269 = ~io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1664:83] - wire _T_270 = io_inst_acc_r & _T_269; // @[dec_tlu_ctl.scala 1664:81] - wire _T_271 = io_ebreak_r | _T_270; // @[dec_tlu_ctl.scala 1664:64] - wire _T_272 = _T_271 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1664:106] - wire _T_273 = io_exc_or_int_valid_r & _T_272; // @[dec_tlu_ctl.scala 1664:49] - wire mtval_capture_pc_r = _T_273 & _T_213; // @[dec_tlu_ctl.scala 1664:138] - wire _T_275 = io_inst_acc_r & io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1665:72] - wire _T_276 = io_exc_or_int_valid_r & _T_275; // @[dec_tlu_ctl.scala 1665:55] - wire mtval_capture_pc_plus2_r = _T_276 & _T_213; // @[dec_tlu_ctl.scala 1665:96] - wire _T_278 = io_exc_or_int_valid_r & io_illegal_r; // @[dec_tlu_ctl.scala 1666:51] - wire mtval_capture_inst_r = _T_278 & _T_213; // @[dec_tlu_ctl.scala 1666:66] - wire _T_280 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1667:50] - wire mtval_capture_lsu_r = _T_280 & _T_213; // @[dec_tlu_ctl.scala 1667:71] - wire _T_282 = ~mtval_capture_pc_r; // @[dec_tlu_ctl.scala 1668:46] - wire _T_283 = io_exc_or_int_valid_r & _T_282; // @[dec_tlu_ctl.scala 1668:44] - wire _T_284 = ~mtval_capture_inst_r; // @[dec_tlu_ctl.scala 1668:68] - wire _T_285 = _T_283 & _T_284; // @[dec_tlu_ctl.scala 1668:66] - wire _T_286 = ~mtval_capture_lsu_r; // @[dec_tlu_ctl.scala 1668:92] - wire _T_287 = _T_285 & _T_286; // @[dec_tlu_ctl.scala 1668:90] - wire _T_288 = ~io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1668:115] - wire mtval_clear_r = _T_287 & _T_288; // @[dec_tlu_ctl.scala 1668:113] + wire _T_268 = io_dec_csr_wraddr_r == 12'h343; // @[dec_tlu_ctl.scala 1657:69] + wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_268; // @[dec_tlu_ctl.scala 1657:40] + wire _T_269 = ~io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1658:83] + wire _T_270 = io_inst_acc_r & _T_269; // @[dec_tlu_ctl.scala 1658:81] + wire _T_271 = io_ebreak_r | _T_270; // @[dec_tlu_ctl.scala 1658:64] + wire _T_272 = _T_271 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1658:106] + wire _T_273 = io_exc_or_int_valid_r & _T_272; // @[dec_tlu_ctl.scala 1658:49] + wire mtval_capture_pc_r = _T_273 & _T_213; // @[dec_tlu_ctl.scala 1658:138] + wire _T_275 = io_inst_acc_r & io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1659:72] + wire _T_276 = io_exc_or_int_valid_r & _T_275; // @[dec_tlu_ctl.scala 1659:55] + wire mtval_capture_pc_plus2_r = _T_276 & _T_213; // @[dec_tlu_ctl.scala 1659:96] + wire _T_278 = io_exc_or_int_valid_r & io_illegal_r; // @[dec_tlu_ctl.scala 1660:51] + wire mtval_capture_inst_r = _T_278 & _T_213; // @[dec_tlu_ctl.scala 1660:66] + wire _T_280 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1661:50] + wire mtval_capture_lsu_r = _T_280 & _T_213; // @[dec_tlu_ctl.scala 1661:71] + wire _T_282 = ~mtval_capture_pc_r; // @[dec_tlu_ctl.scala 1662:46] + wire _T_283 = io_exc_or_int_valid_r & _T_282; // @[dec_tlu_ctl.scala 1662:44] + wire _T_284 = ~mtval_capture_inst_r; // @[dec_tlu_ctl.scala 1662:68] + wire _T_285 = _T_283 & _T_284; // @[dec_tlu_ctl.scala 1662:66] + wire _T_286 = ~mtval_capture_lsu_r; // @[dec_tlu_ctl.scala 1662:92] + wire _T_287 = _T_285 & _T_286; // @[dec_tlu_ctl.scala 1662:90] + wire _T_288 = ~io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1662:115] + wire mtval_clear_r = _T_287 & _T_288; // @[dec_tlu_ctl.scala 1662:113] wire [31:0] _T_290 = {pc_r,1'h0}; // @[Cat.scala 29:58] - wire [30:0] _T_293 = pc_r + 31'h1; // @[dec_tlu_ctl.scala 1673:83] + wire [30:0] _T_293 = pc_r + 31'h1; // @[dec_tlu_ctl.scala 1667:83] wire [31:0] _T_294 = {_T_293,1'h0}; // @[Cat.scala 29:58] - wire _T_297 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1676:18] - wire _T_298 = wr_mtval_r & _T_297; // @[dec_tlu_ctl.scala 1676:16] - wire _T_301 = ~wr_mtval_r; // @[dec_tlu_ctl.scala 1677:20] - wire _T_302 = _T_213 & _T_301; // @[dec_tlu_ctl.scala 1677:18] - wire _T_304 = _T_302 & _T_282; // @[dec_tlu_ctl.scala 1677:32] - wire _T_306 = _T_304 & _T_284; // @[dec_tlu_ctl.scala 1677:54] - wire _T_307 = ~mtval_clear_r; // @[dec_tlu_ctl.scala 1677:80] - wire _T_308 = _T_306 & _T_307; // @[dec_tlu_ctl.scala 1677:78] - wire _T_310 = _T_308 & _T_286; // @[dec_tlu_ctl.scala 1677:95] + wire _T_297 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1670:18] + wire _T_298 = wr_mtval_r & _T_297; // @[dec_tlu_ctl.scala 1670:16] + wire _T_301 = ~wr_mtval_r; // @[dec_tlu_ctl.scala 1671:20] + wire _T_302 = _T_213 & _T_301; // @[dec_tlu_ctl.scala 1671:18] + wire _T_304 = _T_302 & _T_282; // @[dec_tlu_ctl.scala 1671:32] + wire _T_306 = _T_304 & _T_284; // @[dec_tlu_ctl.scala 1671:54] + wire _T_307 = ~mtval_clear_r; // @[dec_tlu_ctl.scala 1671:80] + wire _T_308 = _T_306 & _T_307; // @[dec_tlu_ctl.scala 1671:78] + wire _T_310 = _T_308 & _T_286; // @[dec_tlu_ctl.scala 1671:95] wire [31:0] _T_312 = mtval_capture_pc_r ? _T_290 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_313 = mtval_capture_pc_plus2_r ? _T_294 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_314 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_315 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_316 = _T_298 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] - reg [31:0] mtval; // @[dec_tlu_ctl.scala 1679:46] + reg [31:0] mtval; // @[dec_tlu_ctl.scala 1673:46] wire [31:0] _T_317 = _T_310 ? mtval : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_318 = _T_312 | _T_313; // @[Mux.scala 27:72] wire [31:0] _T_319 = _T_318 | _T_314; // @[Mux.scala 27:72] wire [31:0] _T_320 = _T_319 | _T_315; // @[Mux.scala 27:72] wire [31:0] _T_321 = _T_320 | _T_316; // @[Mux.scala 27:72] - wire _T_325 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1694:68] + wire _T_325 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1688:68] reg [8:0] mcgc; // @[lib.scala 374:16] - wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1724:68] + wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1718:68] reg [14:0] mfdc_int; // @[lib.scala 374:16] - wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1737:19] - wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1738:19] + wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1731:19] + wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1732:19] wire [18:0] mfdc = {_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] - wire _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1757:77] - wire _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1757:48] - wire _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1757:87] - wire _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1757:113] - wire _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1764:68] - wire _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1767:71] - wire _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1767:69] - wire _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1768:73] - wire _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1768:71] - wire _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1769:73] - wire _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1769:71] - wire _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1770:73] - wire _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1770:71] - wire _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1771:73] - wire _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1771:71] - wire _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1772:73] - wire _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1772:71] - wire _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1773:73] - wire _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1773:71] - wire _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1774:73] - wire _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1774:71] - wire _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1775:73] - wire _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1775:71] - wire _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1776:73] - wire _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1776:71] - wire _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1777:73] - wire _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1777:71] - wire _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1778:73] - wire _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1778:70] - wire _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1779:73] - wire _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1779:70] - wire _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1780:73] - wire _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1780:70] - wire _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1781:73] - wire _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1781:70] - wire _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1782:70] + wire _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1751:77] + wire _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1751:48] + wire _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1751:87] + wire _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1751:113] + wire _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1758:68] + wire _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1761:71] + wire _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1761:69] + wire _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1762:73] + wire _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1762:71] + wire _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1763:73] + wire _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1763:71] + wire _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1764:73] + wire _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1764:71] + wire _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1765:73] + wire _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1765:71] + wire _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1766:73] + wire _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1766:71] + wire _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1767:73] + wire _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1767:71] + wire _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1768:73] + wire _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1768:71] + wire _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1769:73] + wire _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1769:71] + wire _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1770:73] + wire _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1770:71] + wire _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1771:73] + wire _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1771:71] + wire _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1772:73] + wire _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1772:70] + wire _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1773:73] + wire _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1773:70] + wire _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1774:73] + wire _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1774:70] + wire _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1775:73] + wire _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1775:70] + wire _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1776:70] wire [7:0] _T_451 = {io_dec_csr_wrdata_r[7],_T_429,io_dec_csr_wrdata_r[5],_T_434,io_dec_csr_wrdata_r[3],_T_439,io_dec_csr_wrdata_r[1],_T_444}; // @[Cat.scala 29:58] wire [15:0] _T_459 = {io_dec_csr_wrdata_r[15],_T_409,io_dec_csr_wrdata_r[13],_T_414,io_dec_csr_wrdata_r[11],_T_419,io_dec_csr_wrdata_r[9],_T_424,_T_451}; // @[Cat.scala 29:58] wire [7:0] _T_466 = {io_dec_csr_wrdata_r[23],_T_389,io_dec_csr_wrdata_r[21],_T_394,io_dec_csr_wrdata_r[19],_T_399,io_dec_csr_wrdata_r[17],_T_404}; // @[Cat.scala 29:58] wire [15:0] _T_474 = {io_dec_csr_wrdata_r[31],_T_369,io_dec_csr_wrdata_r[29],_T_374,io_dec_csr_wrdata_r[27],_T_379,io_dec_csr_wrdata_r[25],_T_384,_T_466}; // @[Cat.scala 29:58] reg [31:0] mrac; // @[lib.scala 374:16] - wire _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1795:69] - wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1795:40] - wire _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1805:59] - wire _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1805:57] - wire _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1807:49] - wire _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1807:86] - wire _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1807:84] - wire _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1807:111] - wire mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1807:109] + wire _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1789:69] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1789:40] + wire _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1799:59] + wire _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1799:57] + wire _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1801:49] + wire _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1801:86] + wire _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1801:84] + wire _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1801:111] + wire mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1801:109] reg [31:0] mdseac; // @[lib.scala 374:16] - wire _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1822:30] - wire _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1822:57] - wire _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1822:55] - wire _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1822:89] - wire _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1840:48] - wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1840:19] - wire _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1842:70] - wire wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1842:41] + wire _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1816:30] + wire _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1816:57] + wire _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1816:55] + wire _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1816:89] + wire _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1834:48] + wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1834:19] + wire _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1836:70] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1836:41] wire [26:0] _T_510 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] - wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1843:23] - wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1843:23] + wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1837:23] + wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1837:23] wire [31:0] _T_515 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] - wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1843:13] + wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1837:13] wire [31:0] _T_517 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] - wire _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1857:76] - wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1857:47] - wire _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1858:70] + wire _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1851:76] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1851:47] + wire _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1852:70] wire [26:0] _T_531 = {26'h0,_T_530}; // @[Cat.scala 29:58] - wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1858:33] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1852:33] wire [31:0] _T_538 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] - wire _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1861:48] - wire _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1872:76] - wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1872:47] + wire _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1855:48] + wire _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1866:76] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1866:47] wire [26:0] _T_552 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] - wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1873:33] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1867:33] wire [31:0] _T_559 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] - wire _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1888:69] - wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1888:40] - reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1892:43] - wire _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1901:69] - wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1901:40] - wire _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1904:43] - wire _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1904:41] - wire _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1904:78] - wire _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1904:98] + wire _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1882:69] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1882:40] + reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1886:43] + wire _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1895:69] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1895:40] + wire _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1898:43] + wire _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1898:41] + wire _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1898:78] + wire _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1898:98] wire [1:0] _T_583 = {_T_581,_T_582}; // @[Cat.scala 29:58] reg [1:0] mfdhs; // @[Reg.scala 27:20] - wire _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1906:71] + wire _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1900:71] reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] - wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1908:74] - wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1913:71] - wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1913:48] - wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1913:48] - wire _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1913:87] - wire _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1921:69] + wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1902:74] + wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1907:71] + wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1907:48] + wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1907:48] + wire _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1907:87] + wire _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1915:69] reg [21:0] meivt; // @[lib.scala 374:16] - wire _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1972:69] - wire _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1972:40] - wire wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1972:83] + wire _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1966:69] + wire _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1966:40] + wire wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1966:83] reg [7:0] meihap; // @[lib.scala 374:16] - wire _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1945:72] - wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1945:43] - reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1948:46] - wire _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1960:73] - wire _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1960:44] - wire wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1960:88] - reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1965:44] - wire _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 1981:69] - wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 1981:40] - reg [3:0] meipt; // @[dec_tlu_ctl.scala 1984:43] - wire _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2012:89] - wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2012:66] - wire _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2015:31] - wire _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2015:29] - wire _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2015:63] - wire _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2015:61] - wire _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2015:98] - wire _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2015:96] - wire _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2016:46] - wire _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2016:78] - wire _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2017:75] + wire _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1939:72] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1939:43] + reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1942:46] + wire _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1954:73] + wire _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1954:44] + wire wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1954:88] + reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1959:44] + wire _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 1975:69] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 1975:40] + reg [3:0] meipt; // @[dec_tlu_ctl.scala 1978:43] + wire _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2006:89] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2006:66] + wire _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2009:31] + wire _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2009:29] + wire _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2009:63] + wire _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2009:61] + wire _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2009:98] + wire _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2009:96] + wire _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2010:46] + wire _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2010:78] + wire _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2011:75] wire [2:0] _T_646 = _T_635 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_647 = _T_640 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_648 = _T_643 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] @@ -51306,103 +51306,103 @@ module csr_tlu( wire [2:0] _T_650 = _T_646 | _T_647; // @[Mux.scala 27:72] wire [2:0] _T_651 = _T_650 | _T_648; // @[Mux.scala 27:72] wire [2:0] dcsr_cause = _T_651 | _T_649; // @[Mux.scala 27:72] - wire _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2020:46] - wire _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2020:98] - wire wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2020:69] - wire _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2026:75] - wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2026:59] - wire _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2027:59] - wire _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2027:78] - wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2027:56] - wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2029:48] + wire _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2014:46] + wire _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2014:98] + wire wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2014:69] + wire _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2020:75] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2020:59] + wire _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2021:59] + wire _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2021:78] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2021:56] + wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2023:48] wire [15:0] _T_665 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] - wire _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2031:145] + wire _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2025:145] wire [15:0] _T_680 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_671,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] wire [15:0] _T_685 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] - wire _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2033:54] - wire _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2033:66] + wire _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2027:54] + wire _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2027:66] reg [15:0] _T_691; // @[lib.scala 374:16] - wire _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2041:97] - wire wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2041:68] - wire _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2042:67] - wire dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2042:65] - wire _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2046:21] - wire _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2046:39] - wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2046:37] - wire _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2046:56] - wire _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2048:49] + wire _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2035:97] + wire wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2035:68] + wire _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2036:67] + wire dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2036:65] + wire _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2040:21] + wire _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2040:39] + wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2040:37] + wire _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2040:56] + wire _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2042:49] wire [30:0] _T_708 = _T_701 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_709 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_710 = _T_706 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_711 = _T_708 | _T_709; // @[Mux.scala 27:72] - wire _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2050:36] + wire _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2044:36] reg [30:0] _T_716; // @[lib.scala 374:16] wire [2:0] _T_720 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] - wire _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2065:102] + wire _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2059:102] reg [16:0] dicawics; // @[lib.scala 374:16] - wire _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2083:100] - wire wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2083:71] + wire _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2077:100] + wire wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2077:71] reg [70:0] dicad0; // @[lib.scala 374:16] - wire _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2096:101] - wire wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2096:72] + wire _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2090:101] + wire wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2090:72] reg [31:0] dicad0h; // @[lib.scala 374:16] - wire _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2108:100] - wire _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2108:71] - wire [31:0] _T_745 = _T_742 ? io_dec_csr_wrdata_r : {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; // @[dec_tlu_ctl.scala 2110:21] - wire _T_746 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2113:78] + wire _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2102:100] + wire _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2102:71] + wire [31:0] _T_745 = _T_742 ? io_dec_csr_wrdata_r : {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; // @[dec_tlu_ctl.scala 2104:21] + wire _T_746 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2107:78] reg [31:0] _T_748; // @[Reg.scala 27:20] wire [31:0] dicad1 = {25'h0,_T_748[6:0]}; // @[Cat.scala 29:58] wire [38:0] _T_753 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] - wire _T_755 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2141:52] - wire _T_756 = _T_755 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2141:75] - wire _T_757 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2141:98] - wire _T_758 = _T_756 & _T_757; // @[dec_tlu_ctl.scala 2141:96] - wire _T_760 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2141:149] - wire _T_763 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2142:104] - reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2144:58] - reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2145:58] - wire _T_765 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2156:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_765; // @[dec_tlu_ctl.scala 2156:40] - reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2159:43] - wire tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2194:42] - wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2196:44] - wire _T_776 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2198:46] - wire tdata_action = _T_776 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2198:69] + wire _T_755 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2135:52] + wire _T_756 = _T_755 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2135:75] + wire _T_757 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2135:98] + wire _T_758 = _T_756 & _T_757; // @[dec_tlu_ctl.scala 2135:96] + wire _T_760 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2135:149] + wire _T_763 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2136:104] + reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2138:58] + reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2139:58] + wire _T_765 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2150:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_765; // @[dec_tlu_ctl.scala 2150:40] + reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2153:43] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2188:42] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2190:44] + wire _T_776 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2192:46] + wire tdata_action = _T_776 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2192:69] wire [9:0] tdata_wrdata_r = {_T_776,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_791 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2204:99] - wire _T_792 = io_dec_csr_wen_r_mod & _T_791; // @[dec_tlu_ctl.scala 2204:70] - wire _T_793 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2204:121] - wire _T_794 = _T_792 & _T_793; // @[dec_tlu_ctl.scala 2204:112] - wire _T_796 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_797 = _T_796 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_0 = _T_794 & _T_797; // @[dec_tlu_ctl.scala 2204:135] - wire _T_802 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2204:121] - wire _T_803 = _T_792 & _T_802; // @[dec_tlu_ctl.scala 2204:112] - wire _T_805 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_806 = _T_805 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_1 = _T_803 & _T_806; // @[dec_tlu_ctl.scala 2204:135] - wire _T_811 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2204:121] - wire _T_812 = _T_792 & _T_811; // @[dec_tlu_ctl.scala 2204:112] - wire _T_814 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_815 = _T_814 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_2 = _T_812 & _T_815; // @[dec_tlu_ctl.scala 2204:135] - wire _T_820 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2204:121] - wire _T_821 = _T_792 & _T_820; // @[dec_tlu_ctl.scala 2204:112] - wire _T_823 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2204:138] - wire _T_824 = _T_823 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2204:170] - wire wr_mtdata1_t_r_3 = _T_821 & _T_824; // @[dec_tlu_ctl.scala 2204:135] - wire _T_830 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2205:139] + wire _T_791 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2198:99] + wire _T_792 = io_dec_csr_wen_r_mod & _T_791; // @[dec_tlu_ctl.scala 2198:70] + wire _T_793 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2198:121] + wire _T_794 = _T_792 & _T_793; // @[dec_tlu_ctl.scala 2198:112] + wire _T_796 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2198:138] + wire _T_797 = _T_796 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2198:170] + wire wr_mtdata1_t_r_0 = _T_794 & _T_797; // @[dec_tlu_ctl.scala 2198:135] + wire _T_802 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2198:121] + wire _T_803 = _T_792 & _T_802; // @[dec_tlu_ctl.scala 2198:112] + wire _T_805 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2198:138] + wire _T_806 = _T_805 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2198:170] + wire wr_mtdata1_t_r_1 = _T_803 & _T_806; // @[dec_tlu_ctl.scala 2198:135] + wire _T_811 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2198:121] + wire _T_812 = _T_792 & _T_811; // @[dec_tlu_ctl.scala 2198:112] + wire _T_814 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2198:138] + wire _T_815 = _T_814 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2198:170] + wire wr_mtdata1_t_r_2 = _T_812 & _T_815; // @[dec_tlu_ctl.scala 2198:135] + wire _T_820 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2198:121] + wire _T_821 = _T_792 & _T_820; // @[dec_tlu_ctl.scala 2198:112] + wire _T_823 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2198:138] + wire _T_824 = _T_823 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2198:170] + wire wr_mtdata1_t_r_3 = _T_821 & _T_824; // @[dec_tlu_ctl.scala 2198:135] + wire _T_830 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2199:139] wire [9:0] _T_833 = {io_mtdata1_t_0[9],_T_830,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_839 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2205:139] + wire _T_839 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2199:139] wire [9:0] _T_842 = {io_mtdata1_t_1[9],_T_839,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_848 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2205:139] + wire _T_848 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2199:139] wire [9:0] _T_851 = {io_mtdata1_t_2[9],_T_848,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_857 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2205:139] + wire _T_857 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2199:139] wire [9:0] _T_860 = {io_mtdata1_t_3[9],_T_857,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_862; // @[dec_tlu_ctl.scala 2207:74] - reg [9:0] _T_863; // @[dec_tlu_ctl.scala 2207:74] - reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2207:74] - reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2207:74] + reg [9:0] _T_862; // @[dec_tlu_ctl.scala 2201:74] + reg [9:0] _T_863; // @[dec_tlu_ctl.scala 2201:74] + reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2201:74] + reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2201:74] wire [31:0] _T_880 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] wire [31:0] _T_895 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] wire [31:0] _T_910 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] @@ -51414,12 +51414,12 @@ module csr_tlu( wire [31:0] _T_930 = _T_926 | _T_927; // @[Mux.scala 27:72] wire [31:0] _T_931 = _T_930 | _T_928; // @[Mux.scala 27:72] wire [31:0] mtdata1_tsel_out = _T_931 | _T_929; // @[Mux.scala 27:72] - wire _T_958 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2224:98] - wire _T_959 = io_dec_csr_wen_r_mod & _T_958; // @[dec_tlu_ctl.scala 2224:69] - wire _T_961 = _T_959 & _T_793; // @[dec_tlu_ctl.scala 2224:111] - wire _T_970 = _T_959 & _T_802; // @[dec_tlu_ctl.scala 2224:111] - wire _T_979 = _T_959 & _T_811; // @[dec_tlu_ctl.scala 2224:111] - wire _T_988 = _T_959 & _T_820; // @[dec_tlu_ctl.scala 2224:111] + wire _T_958 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2218:98] + wire _T_959 = io_dec_csr_wen_r_mod & _T_958; // @[dec_tlu_ctl.scala 2218:69] + wire _T_961 = _T_959 & _T_793; // @[dec_tlu_ctl.scala 2218:111] + wire _T_970 = _T_959 & _T_802; // @[dec_tlu_ctl.scala 2218:111] + wire _T_979 = _T_959 & _T_811; // @[dec_tlu_ctl.scala 2218:111] + wire _T_988 = _T_959 & _T_820; // @[dec_tlu_ctl.scala 2218:111] reg [31:0] mtdata2_t_0; // @[lib.scala 374:16] reg [31:0] mtdata2_t_1; // @[lib.scala 374:16] reg [31:0] mtdata2_t_2; // @[lib.scala 374:16] @@ -51432,106 +51432,106 @@ module csr_tlu( wire [31:0] _T_1010 = _T_1009 | _T_1007; // @[Mux.scala 27:72] wire [31:0] mtdata2_tsel_out = _T_1010 | _T_1008; // @[Mux.scala 27:72] wire [3:0] _T_1013 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1013; // @[dec_tlu_ctl.scala 2249:59] - wire _T_1015 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2255:24] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1013; // @[dec_tlu_ctl.scala 2243:59] + wire _T_1015 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2249:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1016 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1018 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1020 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1022 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1024 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2259:96] - wire _T_1025 = io_tlu_i0_commit_cmt & _T_1024; // @[dec_tlu_ctl.scala 2259:94] - wire _T_1026 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1028 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2260:96] - wire _T_1029 = io_tlu_i0_commit_cmt & _T_1028; // @[dec_tlu_ctl.scala 2260:94] - wire _T_1031 = _T_1029 & _T_1024; // @[dec_tlu_ctl.scala 2260:115] - wire _T_1032 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1034 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2261:94] - wire _T_1036 = _T_1034 & _T_1024; // @[dec_tlu_ctl.scala 2261:115] - wire _T_1037 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1039 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1041 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1043 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1045 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2265:91] - wire _T_1046 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1048 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2266:105] - wire _T_1049 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1051 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2267:91] - wire _T_1052 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1054 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2268:91] - wire _T_1055 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1058 = _T_1051 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2269:100] - wire _T_1059 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1063 = _T_1054 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2270:101] - wire _T_1064 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1066 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2271:89] - wire _T_1067 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1069 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2272:89] - wire _T_1070 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1072 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2273:89] - wire _T_1073 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1075 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2274:89] - wire _T_1076 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1078 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2275:89] - wire _T_1079 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1081 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2276:89] - wire _T_1082 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1084 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2277:89] - wire _T_1085 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1087 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2278:89] - wire _T_1088 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1090 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2279:89] - wire _T_1091 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1093 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2280:89] - wire _T_1094 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2280:122] - wire _T_1095 = _T_1093 | _T_1094; // @[dec_tlu_ctl.scala 2280:101] - wire _T_1096 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1098 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2281:95] - wire _T_1099 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1101 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2282:97] - wire _T_1102 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1104 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2283:110] - wire _T_1105 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1109 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1111 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1113 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1115 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1117 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1119 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1121 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2291:98] - wire _T_1122 = _T_1121 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2291:120] - wire _T_1123 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1125 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2292:92] - wire _T_1126 = _T_1125 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2292:117] - wire _T_1127 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1129 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1131 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1133 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2295:97] - wire _T_1134 = _T_1133 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2295:129] - wire _T_1135 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1137 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1139 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1141 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1143 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1145 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1147 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1149 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1153 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2303:73] - wire _T_1154 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire [5:0] _T_1161 = io_mip & mie; // @[dec_tlu_ctl.scala 2304:113] - wire _T_1162 = |_T_1161; // @[dec_tlu_ctl.scala 2304:125] - wire _T_1163 = _T_1153 & _T_1162; // @[dec_tlu_ctl.scala 2304:98] - wire _T_1164 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1166 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2305:91] - wire _T_1167 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1169 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2306:94] - wire _T_1170 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1172 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2307:94] - wire _T_1173 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1175 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1177 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1179 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1181 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1016 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2250:34] + wire _T_1018 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2251:34] + wire _T_1020 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2252:34] + wire _T_1022 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2253:34] + wire _T_1024 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2253:96] + wire _T_1025 = io_tlu_i0_commit_cmt & _T_1024; // @[dec_tlu_ctl.scala 2253:94] + wire _T_1026 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2254:34] + wire _T_1028 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2254:96] + wire _T_1029 = io_tlu_i0_commit_cmt & _T_1028; // @[dec_tlu_ctl.scala 2254:94] + wire _T_1031 = _T_1029 & _T_1024; // @[dec_tlu_ctl.scala 2254:115] + wire _T_1032 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2255:34] + wire _T_1034 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2255:94] + wire _T_1036 = _T_1034 & _T_1024; // @[dec_tlu_ctl.scala 2255:115] + wire _T_1037 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1039 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1041 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1043 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1045 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2259:91] + wire _T_1046 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1048 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2260:105] + wire _T_1049 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1051 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2261:91] + wire _T_1052 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1054 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2262:91] + wire _T_1055 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1058 = _T_1051 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2263:100] + wire _T_1059 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1063 = _T_1054 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2264:101] + wire _T_1064 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1066 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2265:89] + wire _T_1067 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1069 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2266:89] + wire _T_1070 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1072 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2267:89] + wire _T_1073 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1075 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2268:89] + wire _T_1076 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1078 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2269:89] + wire _T_1079 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1081 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2270:89] + wire _T_1082 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1084 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2271:89] + wire _T_1085 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1087 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2272:89] + wire _T_1088 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1090 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2273:89] + wire _T_1091 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1093 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2274:89] + wire _T_1094 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2274:122] + wire _T_1095 = _T_1093 | _T_1094; // @[dec_tlu_ctl.scala 2274:101] + wire _T_1096 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1098 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2275:95] + wire _T_1099 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1101 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2276:97] + wire _T_1102 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1104 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2277:110] + wire _T_1105 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1109 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1111 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1113 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1115 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1117 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1119 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1121 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2285:98] + wire _T_1122 = _T_1121 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2285:120] + wire _T_1123 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1125 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2286:92] + wire _T_1126 = _T_1125 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2286:117] + wire _T_1127 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1129 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1131 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1133 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2289:97] + wire _T_1134 = _T_1133 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2289:129] + wire _T_1135 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1137 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1139 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1141 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1143 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1145 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1147 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1149 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1153 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2297:73] + wire _T_1154 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2298:34] + wire [5:0] _T_1161 = io_mip & mie; // @[dec_tlu_ctl.scala 2298:113] + wire _T_1162 = |_T_1161; // @[dec_tlu_ctl.scala 2298:125] + wire _T_1163 = _T_1153 & _T_1162; // @[dec_tlu_ctl.scala 2298:98] + wire _T_1164 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1166 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2299:91] + wire _T_1167 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1169 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2300:94] + wire _T_1170 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1172 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2301:94] + wire _T_1173 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1175 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1177 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1179 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1181 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2307:34] wire _T_1184 = _T_1018 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] wire _T_1185 = _T_1020 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] wire _T_1186 = _T_1022 & _T_1025; // @[Mux.scala 27:72] @@ -51643,65 +51643,65 @@ module csr_tlu( wire _T_1293 = _T_1292 | _T_1237; // @[Mux.scala 27:72] wire _T_1294 = _T_1293 | _T_1238; // @[Mux.scala 27:72] wire _T_1295 = _T_1294 | _T_1239; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1015 & _T_1295; // @[dec_tlu_ctl.scala 2255:44] - wire _T_1299 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2255:24] + wire mhpmc_inc_r_0 = _T_1015 & _T_1295; // @[dec_tlu_ctl.scala 2249:44] + wire _T_1299 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2249:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1300 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1302 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1304 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1306 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1310 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1316 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1321 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1323 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1325 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1327 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1330 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1333 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1336 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1339 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1343 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1348 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1351 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1354 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1357 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1360 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1363 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1366 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1369 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1372 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1375 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1380 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1383 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1386 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1389 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1393 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1395 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1397 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1399 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1401 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1403 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1407 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1411 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1413 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1415 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1419 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1421 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1423 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1425 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1427 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1429 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1431 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1433 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1438 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1448 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1451 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1454 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1457 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1459 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1461 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1463 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1465 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1300 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2250:34] + wire _T_1302 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2251:34] + wire _T_1304 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2252:34] + wire _T_1306 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2253:34] + wire _T_1310 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2254:34] + wire _T_1316 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2255:34] + wire _T_1321 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1323 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1325 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1327 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1330 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1333 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1336 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1339 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1343 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1348 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1351 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1354 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1357 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1360 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1363 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1366 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1369 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1372 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1375 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1380 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1383 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1386 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1389 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1393 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1395 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1397 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1399 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1401 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1403 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1407 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1411 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1413 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1415 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1419 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1421 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1423 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1425 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1427 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1429 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1431 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1433 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1438 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1448 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1451 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1454 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1457 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1459 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1461 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1463 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1465 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2307:34] wire _T_1468 = _T_1302 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] wire _T_1469 = _T_1304 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] wire _T_1470 = _T_1306 & _T_1025; // @[Mux.scala 27:72] @@ -51813,65 +51813,65 @@ module csr_tlu( wire _T_1577 = _T_1576 | _T_1521; // @[Mux.scala 27:72] wire _T_1578 = _T_1577 | _T_1522; // @[Mux.scala 27:72] wire _T_1579 = _T_1578 | _T_1523; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1299 & _T_1579; // @[dec_tlu_ctl.scala 2255:44] - wire _T_1583 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2255:24] + wire mhpmc_inc_r_1 = _T_1299 & _T_1579; // @[dec_tlu_ctl.scala 2249:44] + wire _T_1583 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2249:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1584 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1586 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1588 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1590 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1594 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1600 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1605 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1607 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1609 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1611 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1614 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1617 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1620 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1623 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1627 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1632 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1635 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1638 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1641 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1644 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1647 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1650 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1653 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1656 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1659 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1664 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1667 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1670 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1673 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1677 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1679 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1681 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1683 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1685 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1687 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1691 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1695 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1697 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1699 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1703 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1705 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1707 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1709 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1711 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1713 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1715 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1717 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1722 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1732 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1735 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1738 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1741 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1743 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1745 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1747 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1749 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1584 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2250:34] + wire _T_1586 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2251:34] + wire _T_1588 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2252:34] + wire _T_1590 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2253:34] + wire _T_1594 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2254:34] + wire _T_1600 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2255:34] + wire _T_1605 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1607 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1609 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1611 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1614 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1617 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1620 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1623 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1627 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1632 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1635 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1638 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1641 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1644 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1647 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1650 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1653 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1656 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1659 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1664 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1667 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1670 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1673 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1677 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1679 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1681 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1683 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1685 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1687 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1691 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1695 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1697 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1699 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1703 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1705 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1707 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1709 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1711 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1713 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1715 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1717 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1722 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1732 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1735 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1738 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1741 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1743 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1745 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1747 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1749 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2307:34] wire _T_1752 = _T_1586 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] wire _T_1753 = _T_1588 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] wire _T_1754 = _T_1590 & _T_1025; // @[Mux.scala 27:72] @@ -51983,65 +51983,65 @@ module csr_tlu( wire _T_1861 = _T_1860 | _T_1805; // @[Mux.scala 27:72] wire _T_1862 = _T_1861 | _T_1806; // @[Mux.scala 27:72] wire _T_1863 = _T_1862 | _T_1807; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1583 & _T_1863; // @[dec_tlu_ctl.scala 2255:44] - wire _T_1867 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2255:24] + wire mhpmc_inc_r_2 = _T_1583 & _T_1863; // @[dec_tlu_ctl.scala 2249:44] + wire _T_1867 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2249:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1868 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2256:34] - wire _T_1870 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2257:34] - wire _T_1872 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2258:34] - wire _T_1874 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2259:34] - wire _T_1878 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2260:34] - wire _T_1884 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2261:34] - wire _T_1889 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2262:34] - wire _T_1891 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2263:34] - wire _T_1893 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2264:34] - wire _T_1895 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2265:34] - wire _T_1898 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2266:34] - wire _T_1901 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2267:34] - wire _T_1904 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2268:34] - wire _T_1907 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2269:34] - wire _T_1911 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2270:34] - wire _T_1916 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2271:34] - wire _T_1919 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2272:34] - wire _T_1922 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1925 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1928 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1931 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1934 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1937 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1940 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1943 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1948 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1951 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1954 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1957 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1961 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1963 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1965 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1967 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1969 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1971 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1975 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1979 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1981 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1983 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1987 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1989 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1991 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1993 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1995 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1997 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1999 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2302:34] - wire _T_2001 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2303:34] - wire _T_2006 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2304:34] - wire _T_2016 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2305:34] - wire _T_2019 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2306:34] - wire _T_2022 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2307:34] - wire _T_2025 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2309:34] - wire _T_2027 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2310:34] - wire _T_2029 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2311:34] - wire _T_2031 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2312:34] - wire _T_2033 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1868 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2250:34] + wire _T_1870 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2251:34] + wire _T_1872 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2252:34] + wire _T_1874 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2253:34] + wire _T_1878 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2254:34] + wire _T_1884 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2255:34] + wire _T_1889 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2256:34] + wire _T_1891 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2257:34] + wire _T_1893 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2258:34] + wire _T_1895 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2259:34] + wire _T_1898 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2260:34] + wire _T_1901 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2261:34] + wire _T_1904 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2262:34] + wire _T_1907 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2263:34] + wire _T_1911 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2264:34] + wire _T_1916 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2265:34] + wire _T_1919 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2266:34] + wire _T_1922 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2267:34] + wire _T_1925 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2268:34] + wire _T_1928 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2269:34] + wire _T_1931 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2270:34] + wire _T_1934 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2271:34] + wire _T_1937 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2272:34] + wire _T_1940 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2273:34] + wire _T_1943 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1948 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1951 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1954 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1957 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1961 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1963 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1965 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1967 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1969 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1971 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1975 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1979 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1981 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1983 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1987 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1989 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1991 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1993 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1995 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1997 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1999 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2296:34] + wire _T_2001 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2297:34] + wire _T_2006 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2298:34] + wire _T_2016 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2299:34] + wire _T_2019 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2300:34] + wire _T_2022 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2301:34] + wire _T_2025 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2303:34] + wire _T_2027 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2304:34] + wire _T_2029 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2305:34] + wire _T_2031 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2306:34] + wire _T_2033 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2307:34] wire _T_2036 = _T_1870 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] wire _T_2037 = _T_1872 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] wire _T_2038 = _T_1874 & _T_1025; // @[Mux.scala 27:72] @@ -52153,103 +52153,103 @@ module csr_tlu( wire _T_2145 = _T_2144 | _T_2089; // @[Mux.scala 27:72] wire _T_2146 = _T_2145 | _T_2090; // @[Mux.scala 27:72] wire _T_2147 = _T_2146 | _T_2091; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1867 & _T_2147; // @[dec_tlu_ctl.scala 2255:44] - reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2316:53] - reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2317:53] - reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2318:53] - reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2319:53] - reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2320:56] - wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2323:67] - wire _T_2159 = ~_T_85; // @[dec_tlu_ctl.scala 2324:37] + wire mhpmc_inc_r_3 = _T_1867 & _T_2147; // @[dec_tlu_ctl.scala 2249:44] + reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2310:53] + reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2311:53] + reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2312:53] + reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2313:53] + reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2314:56] + wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2317:67] + wire _T_2159 = ~_T_85; // @[dec_tlu_ctl.scala 2318:37] wire [3:0] _T_2161 = _T_2159 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] wire [3:0] _T_2168 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2161 & _T_2168; // @[dec_tlu_ctl.scala 2324:86] - wire _T_2170 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2326:67] - wire _T_2171 = perfcnt_halted_d1 & _T_2170; // @[dec_tlu_ctl.scala 2326:65] - wire _T_2172 = ~_T_2171; // @[dec_tlu_ctl.scala 2326:45] - wire _T_2175 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2327:67] - wire _T_2176 = perfcnt_halted_d1 & _T_2175; // @[dec_tlu_ctl.scala 2327:65] - wire _T_2177 = ~_T_2176; // @[dec_tlu_ctl.scala 2327:45] - wire _T_2180 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2328:67] - wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2328:65] - wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2328:45] - wire _T_2185 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2329:67] - wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2329:65] - wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2329:45] - wire _T_2190 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2335:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2190; // @[dec_tlu_ctl.scala 2335:43] - wire _T_2191 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2336:23] - wire _T_2193 = _T_2191 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2336:39] - wire _T_2194 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2336:86] - wire mhpmc3_wr_en1 = _T_2193 & _T_2194; // @[dec_tlu_ctl.scala 2336:66] + wire [3:0] perfcnt_during_sleep = _T_2161 & _T_2168; // @[dec_tlu_ctl.scala 2318:86] + wire _T_2170 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2320:67] + wire _T_2171 = perfcnt_halted_d1 & _T_2170; // @[dec_tlu_ctl.scala 2320:65] + wire _T_2172 = ~_T_2171; // @[dec_tlu_ctl.scala 2320:45] + wire _T_2175 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2321:67] + wire _T_2176 = perfcnt_halted_d1 & _T_2175; // @[dec_tlu_ctl.scala 2321:65] + wire _T_2177 = ~_T_2176; // @[dec_tlu_ctl.scala 2321:45] + wire _T_2180 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2322:67] + wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2322:65] + wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2322:45] + wire _T_2185 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2323:67] + wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2323:65] + wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2323:45] + wire _T_2190 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2329:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2190; // @[dec_tlu_ctl.scala 2329:43] + wire _T_2191 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2330:23] + wire _T_2193 = _T_2191 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2330:39] + wire _T_2194 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2330:86] + wire mhpmc3_wr_en1 = _T_2193 & _T_2194; // @[dec_tlu_ctl.scala 2330:66] reg [31:0] mhpmc3h; // @[lib.scala 374:16] reg [31:0] mhpmc3; // @[lib.scala 374:16] wire [63:0] _T_2197 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] wire [63:0] _T_2198 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2197 + _T_2198; // @[dec_tlu_ctl.scala 2340:49] - wire _T_2206 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2345:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2206; // @[dec_tlu_ctl.scala 2345:44] - wire _T_2212 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2354:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2212; // @[dec_tlu_ctl.scala 2354:43] - wire _T_2215 = _T_2191 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2355:39] - wire _T_2216 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2355:86] - wire mhpmc4_wr_en1 = _T_2215 & _T_2216; // @[dec_tlu_ctl.scala 2355:66] + wire [63:0] mhpmc3_incr = _T_2197 + _T_2198; // @[dec_tlu_ctl.scala 2334:49] + wire _T_2206 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2339:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2206; // @[dec_tlu_ctl.scala 2339:44] + wire _T_2212 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2348:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2212; // @[dec_tlu_ctl.scala 2348:43] + wire _T_2215 = _T_2191 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2349:39] + wire _T_2216 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2349:86] + wire mhpmc4_wr_en1 = _T_2215 & _T_2216; // @[dec_tlu_ctl.scala 2349:66] reg [31:0] mhpmc4h; // @[lib.scala 374:16] reg [31:0] mhpmc4; // @[lib.scala 374:16] wire [63:0] _T_2219 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] wire [63:0] _T_2220 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2219 + _T_2220; // @[dec_tlu_ctl.scala 2360:49] - wire _T_2229 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2364:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2229; // @[dec_tlu_ctl.scala 2364:44] - wire _T_2235 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2373:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2235; // @[dec_tlu_ctl.scala 2373:43] - wire _T_2238 = _T_2191 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2374:39] - wire _T_2239 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2374:86] - wire mhpmc5_wr_en1 = _T_2238 & _T_2239; // @[dec_tlu_ctl.scala 2374:66] + wire [63:0] mhpmc4_incr = _T_2219 + _T_2220; // @[dec_tlu_ctl.scala 2354:49] + wire _T_2229 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2358:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2229; // @[dec_tlu_ctl.scala 2358:44] + wire _T_2235 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2367:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2235; // @[dec_tlu_ctl.scala 2367:43] + wire _T_2238 = _T_2191 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2368:39] + wire _T_2239 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2368:86] + wire mhpmc5_wr_en1 = _T_2238 & _T_2239; // @[dec_tlu_ctl.scala 2368:66] reg [31:0] mhpmc5h; // @[lib.scala 374:16] reg [31:0] mhpmc5; // @[lib.scala 374:16] wire [63:0] _T_2242 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] wire [63:0] _T_2243 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2242 + _T_2243; // @[dec_tlu_ctl.scala 2377:49] - wire _T_2251 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2382:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2251; // @[dec_tlu_ctl.scala 2382:44] - wire _T_2257 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2391:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2257; // @[dec_tlu_ctl.scala 2391:43] - wire _T_2260 = _T_2191 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2392:39] - wire _T_2261 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2392:86] - wire mhpmc6_wr_en1 = _T_2260 & _T_2261; // @[dec_tlu_ctl.scala 2392:66] + wire [63:0] mhpmc5_incr = _T_2242 + _T_2243; // @[dec_tlu_ctl.scala 2371:49] + wire _T_2251 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2376:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2251; // @[dec_tlu_ctl.scala 2376:44] + wire _T_2257 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2385:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2257; // @[dec_tlu_ctl.scala 2385:43] + wire _T_2260 = _T_2191 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2386:39] + wire _T_2261 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2386:86] + wire mhpmc6_wr_en1 = _T_2260 & _T_2261; // @[dec_tlu_ctl.scala 2386:66] reg [31:0] mhpmc6h; // @[lib.scala 374:16] reg [31:0] mhpmc6; // @[lib.scala 374:16] wire [63:0] _T_2264 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] wire [63:0] _T_2265 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2264 + _T_2265; // @[dec_tlu_ctl.scala 2395:49] - wire _T_2273 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2400:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2273; // @[dec_tlu_ctl.scala 2400:44] - wire _T_2279 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2411:56] - wire _T_2281 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2411:102] - wire _T_2282 = _T_2279 | _T_2281; // @[dec_tlu_ctl.scala 2411:71] - wire _T_2285 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2413:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2285; // @[dec_tlu_ctl.scala 2413:41] - wire _T_2289 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2420:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2289; // @[dec_tlu_ctl.scala 2420:41] - wire _T_2293 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2427:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2293; // @[dec_tlu_ctl.scala 2427:41] - wire _T_2297 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2434:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2297; // @[dec_tlu_ctl.scala 2434:41] - wire _T_2301 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2451:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2301; // @[dec_tlu_ctl.scala 2451:48] - wire _T_2313 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2466:51] - wire _T_2314 = _T_2313 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2466:78] - wire _T_2315 = _T_2314 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2466:104] - wire _T_2316 = _T_2315 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2466:130] - wire _T_2317 = _T_2316 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2467:32] - reg _T_2320; // @[dec_tlu_ctl.scala 2469:62] - wire _T_2321 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2470:91] - wire _T_2322 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2470:137] - wire _T_2323 = io_trigger_hit_r_d1 & _T_2322; // @[dec_tlu_ctl.scala 2470:135] - reg _T_2325; // @[dec_tlu_ctl.scala 2470:62] - reg [4:0] _T_2326; // @[dec_tlu_ctl.scala 2471:62] - reg _T_2327; // @[dec_tlu_ctl.scala 2472:62] + wire [63:0] mhpmc6_incr = _T_2264 + _T_2265; // @[dec_tlu_ctl.scala 2389:49] + wire _T_2273 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2394:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2273; // @[dec_tlu_ctl.scala 2394:44] + wire _T_2279 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2405:56] + wire _T_2281 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2405:102] + wire _T_2282 = _T_2279 | _T_2281; // @[dec_tlu_ctl.scala 2405:71] + wire _T_2285 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2407:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2285; // @[dec_tlu_ctl.scala 2407:41] + wire _T_2289 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2414:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2289; // @[dec_tlu_ctl.scala 2414:41] + wire _T_2293 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2421:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2293; // @[dec_tlu_ctl.scala 2421:41] + wire _T_2297 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2428:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2297; // @[dec_tlu_ctl.scala 2428:41] + wire _T_2301 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2445:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2301; // @[dec_tlu_ctl.scala 2445:48] + wire _T_2313 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2460:51] + wire _T_2314 = _T_2313 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2460:78] + wire _T_2315 = _T_2314 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2460:104] + wire _T_2316 = _T_2315 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2460:130] + wire _T_2317 = _T_2316 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2461:32] + reg _T_2320; // @[dec_tlu_ctl.scala 2463:62] + wire _T_2321 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2464:91] + wire _T_2322 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2464:137] + wire _T_2323 = io_trigger_hit_r_d1 & _T_2322; // @[dec_tlu_ctl.scala 2464:135] + reg _T_2325; // @[dec_tlu_ctl.scala 2464:62] + reg [4:0] _T_2326; // @[dec_tlu_ctl.scala 2465:62] + reg _T_2327; // @[dec_tlu_ctl.scala 2466:62] wire [31:0] _T_2333 = {io_core_id,4'h0}; // @[Cat.scala 29:58] wire [31:0] _T_2342 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] wire [31:0] _T_2347 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] @@ -52279,7 +52279,7 @@ module csr_tlu( wire [31:0] _T_2494 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2495 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2496 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2497 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2497 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2498 = io_csr_pkt_csr_mhartid ? _T_2333 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2499 = io_csr_pkt_csr_mstatus ? _T_2342 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2500 = io_csr_pkt_csr_mtvec ? _T_2347 : 32'h0; // @[Mux.scala 27:72] @@ -52596,84 +52596,84 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_753,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2136:56] - assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2139:41] - assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2147:41] - assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2148:41] - assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2212:40] - assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2213:43] - assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2214:40] - assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2215:40] - assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2216:40] - assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2217:40] - assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2230:51] - assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2212:40] - assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2213:43] - assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2214:40] - assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2215:40] - assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2216:40] - assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2217:40] - assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2230:51] - assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2212:40] - assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2213:43] - assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2214:40] - assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2215:40] - assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2216:40] - assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2217:40] - assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2230:51] - assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2212:40] - assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2213:43] - assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2214:40] - assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2215:40] - assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2216:40] - assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2217:40] - assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2230:51] - assign io_dec_tlu_int_valid_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2472:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2325; // @[dec_tlu_ctl.scala 2470:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2320; // @[dec_tlu_ctl.scala 2469:30] - assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2474:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2326; // @[dec_tlu_ctl.scala 2471:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2172; // @[dec_tlu_ctl.scala 2326:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2177; // @[dec_tlu_ctl.scala 2327:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2182; // @[dec_tlu_ctl.scala 2328:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2187; // @[dec_tlu_ctl.scala 2329:22] - assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1698:31] - assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1699:31] - assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1701:31] - assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1702:31] - assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1703:31] - assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1704:31] - assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1705:31] - assign io_dec_csr_rddata_d = _T_2603 | _T_2549; // @[dec_tlu_ctl.scala 2479:21] - assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1748:39] - assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1757:24] - assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 1986:19] - assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1950:22] - assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1936:20] - assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1787:21] - assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1746:39] - assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1745:39] - assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1744:39] - assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1743:39] - assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1742:39] - assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1431:23] - assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1822:17] - assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1447:13] - assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1446:20] - assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2033:10] - assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1459:11] - assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1474:9] - assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1488:12] - assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1582:11] - assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1588:14] - assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1607:10] - assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1805:22] - assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1913:16] - assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2050:9] - assign io_mtdata1_t_0 = _T_862; // @[dec_tlu_ctl.scala 2207:39] - assign io_mtdata1_t_1 = _T_863; // @[dec_tlu_ctl.scala 2207:39] - assign io_mtdata1_t_2 = _T_864; // @[dec_tlu_ctl.scala 2207:39] - assign io_mtdata1_t_3 = _T_865; // @[dec_tlu_ctl.scala 2207:39] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_753,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2130:56] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2133:41] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2141:41] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2142:41] + assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2206:40] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2207:43] + assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2208:40] + assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2209:40] + assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2210:40] + assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2211:40] + assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2224:51] + assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2206:40] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2207:43] + assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2208:40] + assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2209:40] + assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2210:40] + assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2211:40] + assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2224:51] + assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2206:40] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2207:43] + assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2208:40] + assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2209:40] + assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2210:40] + assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2211:40] + assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2224:51] + assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2206:40] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2207:43] + assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2208:40] + assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2209:40] + assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2210:40] + assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2211:40] + assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2224:51] + assign io_dec_tlu_int_valid_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2466:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2325; // @[dec_tlu_ctl.scala 2464:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2320; // @[dec_tlu_ctl.scala 2463:30] + assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2468:24] + assign io_dec_tlu_exc_cause_wb1 = _T_2326; // @[dec_tlu_ctl.scala 2465:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2172; // @[dec_tlu_ctl.scala 2320:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2177; // @[dec_tlu_ctl.scala 2321:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2182; // @[dec_tlu_ctl.scala 2322:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2187; // @[dec_tlu_ctl.scala 2323:22] + assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1692:31] + assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1693:31] + assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1695:31] + assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1696:31] + assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1697:31] + assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1698:31] + assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1699:31] + assign io_dec_csr_rddata_d = _T_2603 | _T_2549; // @[dec_tlu_ctl.scala 2473:21] + assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1742:39] + assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1751:24] + assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 1980:19] + assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1944:22] + assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1930:20] + assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1781:21] + assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1740:39] + assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1739:39] + assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1738:39] + assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1737:39] + assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1736:39] + assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1425:23] + assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1816:17] + assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1441:13] + assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1440:20] + assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2027:10] + assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1453:11] + assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1468:9] + assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1482:12] + assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1576:11] + assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1582:14] + assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1601:10] + assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1799:22] + assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1907:16] + assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2044:9] + assign io_mtdata1_t_0 = _T_862; // @[dec_tlu_ctl.scala 2201:39] + assign io_mtdata1_t_1 = _T_863; // @[dec_tlu_ctl.scala 2201:39] + assign io_mtdata1_t_2 = _T_864; // @[dec_tlu_ctl.scala 2201:39] + assign io_mtdata1_t_3 = _T_865; // @[dec_tlu_ctl.scala 2201:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -53858,371 +53858,371 @@ module dec_decode_csr_read( output io_csr_pkt_postsync, output io_csr_pkt_legal ); - wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2551:129] - wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:129] - wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:129] - wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:129] - wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2551:198] - wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:129] - wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:129] - wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2551:198] - wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:165] - wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2551:198] - wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:129] - wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:129] - wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2551:198] - wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2551:198] - wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2551:198] - wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2551:129] - wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2619:81] - wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2619:121] - wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2619:155] - wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2620:97] - wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2621:81] - wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2621:121] - wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2621:162] - wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2551:198] - wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2551:198] - wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2622:105] - wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2622:145] - wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2551:198] - wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2551:198] - wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2551:198] - wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2624:81] - wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2624:129] - wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2625:105] - wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2625:153] - wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2626:105] - wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2626:153] - wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2627:105] - wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2627:161] - wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2628:105] - wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2628:161] - wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2629:97] - wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2629:153] - wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2630:105] - wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2630:161] - wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2631:105] - wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2631:161] - wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2632:105] - wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2632:161] - wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2633:105] - wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2633:161] - wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2634:105] - wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2634:153] - wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2635:113] - wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2635:161] - wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2636:97] - wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2636:153] - wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] - wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2637:113] - wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2551:198] - assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2553:57] - assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2554:57] - assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2555:57] - assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2556:57] - assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2557:57] - assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2558:57] - assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2559:57] - assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2560:65] - assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2561:65] - assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2562:57] - assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2563:57] - assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2564:57] - assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2565:57] - assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2566:57] - assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2567:57] - assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2568:57] - assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:57] - assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:57] - assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2571:57] - assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2572:57] - assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2573:57] - assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:57] - assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2575:57] - assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2576:57] - assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2577:57] - assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2578:57] - assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2579:57] - assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2580:57] - assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2581:57] - assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2582:65] - assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2583:57] - assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2584:57] - assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2585:57] - assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2586:57] - assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2587:57] - assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2588:57] - assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2589:57] - assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2590:57] - assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2591:57] - assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2592:57] - assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2593:57] - assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2594:57] - assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2595:57] - assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2596:57] - assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2597:57] - assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2598:49] - assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2599:57] - assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2600:57] - assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2601:57] - assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2602:57] - assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2603:57] - assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2604:57] - assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2605:57] - assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2607:57] - assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2609:57] - assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2610:57] - assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2611:57] - assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2612:57] - assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2613:57] - assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2614:57] - assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2615:57] - assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2616:57] - assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2617:57] - assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2618:57] - assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2619:34] - assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2621:30] - assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2624:26] + wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2545:129] + wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2545:129] + wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2545:129] + wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:129] + wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2545:198] + wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2545:129] + wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:129] + wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2545:198] + wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2545:165] + wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2545:198] + wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2545:129] + wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:129] + wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2545:198] + wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2545:198] + wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2545:198] + wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2545:129] + wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2613:81] + wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2613:121] + wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2613:155] + wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2614:97] + wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2615:81] + wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2615:121] + wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2615:162] + wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2545:198] + wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2545:198] + wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2616:105] + wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2616:145] + wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2545:198] + wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2545:198] + wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2545:198] + wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2618:81] + wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2618:129] + wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2619:105] + wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2619:153] + wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2620:105] + wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2620:153] + wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2621:105] + wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2621:161] + wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2622:105] + wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2622:161] + wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2623:97] + wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2623:153] + wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2624:105] + wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2624:161] + wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2625:105] + wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2625:161] + wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2626:105] + wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2626:161] + wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2627:105] + wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2627:161] + wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2628:105] + wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2628:153] + wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2629:113] + wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2629:161] + wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2630:97] + wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2630:153] + wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2545:198] + wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2631:113] + wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2545:198] + assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2547:57] + assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2548:57] + assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2549:57] + assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2550:57] + assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2551:57] + assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2552:57] + assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2553:57] + assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2554:65] + assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2555:65] + assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2556:57] + assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2557:57] + assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2558:57] + assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2559:57] + assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2560:57] + assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2561:57] + assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2562:57] + assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2563:57] + assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2564:57] + assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2565:57] + assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2566:57] + assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2567:57] + assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:57] + assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2569:57] + assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:57] + assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2571:57] + assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2572:57] + assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2573:57] + assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2574:57] + assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2575:57] + assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2576:65] + assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2577:57] + assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2578:57] + assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2579:57] + assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2580:57] + assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2581:57] + assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2582:57] + assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2583:57] + assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2584:57] + assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2585:57] + assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2586:57] + assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2587:57] + assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2588:57] + assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2589:57] + assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2590:57] + assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2591:57] + assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2592:49] + assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2593:57] + assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2594:57] + assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2595:57] + assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2596:57] + assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2597:57] + assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2598:57] + assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2599:57] + assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2601:57] + assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2603:57] + assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2604:57] + assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2605:57] + assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2606:57] + assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2607:57] + assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2608:57] + assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2609:57] + assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2610:57] + assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2611:57] + assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2612:57] + assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2613:34] + assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2615:30] + assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2618:26] endmodule module dec_tlu_ctl( input clock, @@ -54499,26 +54499,26 @@ module dec_tlu_ctl( reg [31:0] _RAND_73; reg [31:0] _RAND_74; `endif // RANDOMIZE_REG_INIT - wire int_timers_clock; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_reset; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_free_clk; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_scan_mode; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 275:32] - wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 275:32] - wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 275:32] - wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 275:32] - wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 275:32] + wire int_timers_clock; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_reset; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_free_clk; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_scan_mode; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 269:32] + wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 269:32] + wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 269:32] + wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 269:32] + wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 269:32] wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] wire rvclkhdr_io_clk; // @[lib.scala 343:22] wire rvclkhdr_io_en; // @[lib.scala 343:22] @@ -54535,905 +54535,905 @@ module dec_tlu_ctl( wire rvclkhdr_3_io_clk; // @[lib.scala 343:22] wire rvclkhdr_3_io_en; // @[lib.scala 343:22] wire rvclkhdr_3_io_scan_mode; // @[lib.scala 343:22] - wire csr_clock; // @[dec_tlu_ctl.scala 813:15] - wire csr_reset; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_free_clk; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_active_clk; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_scan_mode; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 813:15] - wire [11:0] csr_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 813:15] - wire [11:0] csr_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 813:15] - wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 813:15] - wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 813:15] - wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 813:15] - wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 813:15] - wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 813:15] - wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 813:15] - wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 813:15] - wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 813:15] - wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 813:15] - wire [3:0] csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 813:15] - wire [29:0] csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 813:15] - wire [7:0] csr_io_pic_claimid; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 813:15] - wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_dec_illegal_inst; // @[dec_tlu_ctl.scala 813:15] - wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_mexintpend; // @[dec_tlu_ctl.scala 813:15] - wire [30:0] csr_io_exu_npc_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 813:15] - wire [30:0] csr_io_rst_vec; // @[dec_tlu_ctl.scala 813:15] - wire [27:0] csr_io_core_id; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 813:15] - wire [1:0] csr_io_mstatus; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_mret_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 813:15] - wire [15:0] csr_io_dcsr; // @[dec_tlu_ctl.scala 813:15] - wire [30:0] csr_io_mtvec; // @[dec_tlu_ctl.scala 813:15] - wire [5:0] csr_io_mip; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_timer_int_sync; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_soft_int_sync; // @[dec_tlu_ctl.scala 813:15] - wire [5:0] csr_io_mie_ns; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_wr_clk; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 813:15] - wire [1:0] csr_io_lsu_fir_error; // @[dec_tlu_ctl.scala 813:15] - wire [30:0] csr_io_npc_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire [30:0] csr_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire [30:0] csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_reset_delayed; // @[dec_tlu_ctl.scala 813:15] - wire [30:0] csr_io_mepc; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_e4e5_int_clk; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_inst_acc_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_inst_acc_second_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_take_nmi; // @[dec_tlu_ctl.scala 813:15] - wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[dec_tlu_ctl.scala 813:15] - wire [4:0] csr_io_exc_cause_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_i0_valid_wb; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_clk_override; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire [4:0] csr_io_exc_cause_wb; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ebreak_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ecall_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_illegal_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ic_perr_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_debug_halt_req_f; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_force_halt; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_take_ext_int_start; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_debug_halt_req; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_allow_dbg_halt_csr_write; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_enter_debug_halt_req; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_request_debug_mode_done; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_request_debug_mode_r; // @[dec_tlu_ctl.scala 813:15] - wire [30:0] csr_io_dpc; // @[dec_tlu_ctl.scala 813:15] - wire [3:0] csr_io_update_hit_bit_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_take_timer_int; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_take_ext_int; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 813:15] - wire csr_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 813:15] - wire [9:0] csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 813:15] - wire [9:0] csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 813:15] - wire [9:0] csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 813:15] - wire [9:0] csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 813:15] - wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1006:22] - wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1006:22] - reg dbg_halt_state_f; // @[dec_tlu_ctl.scala 365:114] - wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 274:39] - reg mpc_halt_state_f; // @[dec_tlu_ctl.scala 360:114] + wire csr_clock; // @[dec_tlu_ctl.scala 807:15] + wire csr_reset; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_free_clk; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_active_clk; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_scan_mode; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 807:15] + wire [11:0] csr_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 807:15] + wire [11:0] csr_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 807:15] + wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 807:15] + wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 807:15] + wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 807:15] + wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 807:15] + wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 807:15] + wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 807:15] + wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 807:15] + wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 807:15] + wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 807:15] + wire [3:0] csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 807:15] + wire [29:0] csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 807:15] + wire [7:0] csr_io_pic_claimid; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 807:15] + wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_dec_illegal_inst; // @[dec_tlu_ctl.scala 807:15] + wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_mexintpend; // @[dec_tlu_ctl.scala 807:15] + wire [30:0] csr_io_exu_npc_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 807:15] + wire [30:0] csr_io_rst_vec; // @[dec_tlu_ctl.scala 807:15] + wire [27:0] csr_io_core_id; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 807:15] + wire [1:0] csr_io_mstatus; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_mret_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 807:15] + wire [15:0] csr_io_dcsr; // @[dec_tlu_ctl.scala 807:15] + wire [30:0] csr_io_mtvec; // @[dec_tlu_ctl.scala 807:15] + wire [5:0] csr_io_mip; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_timer_int_sync; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_soft_int_sync; // @[dec_tlu_ctl.scala 807:15] + wire [5:0] csr_io_mie_ns; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_wr_clk; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 807:15] + wire [1:0] csr_io_lsu_fir_error; // @[dec_tlu_ctl.scala 807:15] + wire [30:0] csr_io_npc_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire [30:0] csr_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire [30:0] csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_reset_delayed; // @[dec_tlu_ctl.scala 807:15] + wire [30:0] csr_io_mepc; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_e4e5_int_clk; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_inst_acc_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_inst_acc_second_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_take_nmi; // @[dec_tlu_ctl.scala 807:15] + wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[dec_tlu_ctl.scala 807:15] + wire [4:0] csr_io_exc_cause_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_i0_valid_wb; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_clk_override; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire [4:0] csr_io_exc_cause_wb; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ebreak_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ecall_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_illegal_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ic_perr_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_debug_halt_req_f; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_force_halt; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_take_ext_int_start; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_debug_halt_req; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_allow_dbg_halt_csr_write; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_enter_debug_halt_req; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_request_debug_mode_done; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_request_debug_mode_r; // @[dec_tlu_ctl.scala 807:15] + wire [30:0] csr_io_dpc; // @[dec_tlu_ctl.scala 807:15] + wire [3:0] csr_io_update_hit_bit_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_take_timer_int; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_take_ext_int; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 807:15] + wire csr_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 807:15] + wire [9:0] csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 807:15] + wire [9:0] csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 807:15] + wire [9:0] csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 807:15] + wire [9:0] csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 807:15] + wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1000:22] + wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1000:22] + reg dbg_halt_state_f; // @[dec_tlu_ctl.scala 359:114] + wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 268:39] + reg mpc_halt_state_f; // @[dec_tlu_ctl.scala 354:114] wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] reg [6:0] _T_8; // @[lib.scala 37:81] reg [6:0] syncro_ff; // @[lib.scala 37:58] - wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 302:76] - wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 305:64] - wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 306:66] - wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 307:52] - wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 308:56] - wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 999:31] - reg lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 609:74] - wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 312:71] - reg e5_valid; // @[dec_tlu_ctl.scala 324:138] - wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[dec_tlu_ctl.scala 315:39] - reg debug_mode_status; // @[dec_tlu_ctl.scala 325:90] - reg i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 569:81] - reg nmi_int_delayed; // @[dec_tlu_ctl.scala 338:81] - wire _T_37 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 347:45] - wire _T_38 = nmi_int_sync & _T_37; // @[dec_tlu_ctl.scala 347:43] - reg mdseac_locked_f; // @[dec_tlu_ctl.scala 602:89] - wire _T_35 = ~mdseac_locked_f; // @[dec_tlu_ctl.scala 345:32] - wire _T_36 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 345:96] - wire nmi_lsu_detected = _T_35 & _T_36; // @[dec_tlu_ctl.scala 345:49] - wire _T_39 = _T_38 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 347:63] - reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 339:73] - reg take_nmi_r_d1; // @[dec_tlu_ctl.scala 810:107] - wire _T_40 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 347:106] - wire _T_41 = nmi_int_detected_f & _T_40; // @[dec_tlu_ctl.scala 347:104] - wire _T_42 = _T_39 | _T_41; // @[dec_tlu_ctl.scala 347:82] - reg take_ext_int_start_d3; // @[dec_tlu_ctl.scala 742:74] - wire _T_43 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 347:165] - wire _T_44 = take_ext_int_start_d3 & _T_43; // @[dec_tlu_ctl.scala 347:146] - wire nmi_int_detected = _T_42 | _T_44; // @[dec_tlu_ctl.scala 347:122] - wire _T_631 = ~io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 719:23] - wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 998:31] - wire _T_632 = _T_631 & mstatus_mie_ns; // @[dec_tlu_ctl.scala 719:48] - wire [5:0] mip = csr_io_mip; // @[dec_tlu_ctl.scala 1004:31] - wire _T_634 = _T_632 & mip[1]; // @[dec_tlu_ctl.scala 719:65] - wire [5:0] mie_ns = csr_io_mie_ns; // @[dec_tlu_ctl.scala 993:31] - wire timer_int_ready = _T_634 & mie_ns[1]; // @[dec_tlu_ctl.scala 719:83] - wire _T_391 = nmi_int_detected | timer_int_ready; // @[dec_tlu_ctl.scala 596:66] - wire _T_628 = _T_632 & mip[0]; // @[dec_tlu_ctl.scala 718:65] - wire soft_int_ready = _T_628 & mie_ns[0]; // @[dec_tlu_ctl.scala 718:83] - wire _T_392 = _T_391 | soft_int_ready; // @[dec_tlu_ctl.scala 596:84] - reg int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 576:74] - wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 596:101] - reg int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 577:74] - wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 596:125] - wire _T_608 = _T_632 & mip[2]; // @[dec_tlu_ctl.scala 715:65] - wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[dec_tlu_ctl.scala 715:83] - wire _T_395 = io_dec_pic_mhwakeup & mhwakeup_ready; // @[dec_tlu_ctl.scala 596:172] - wire _T_396 = _T_394 | _T_395; // @[dec_tlu_ctl.scala 596:149] - wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[dec_tlu_ctl.scala 596:191] - reg i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 568:81] - wire _T_398 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 596:216] - wire _T_399 = _T_397 & _T_398; // @[dec_tlu_ctl.scala 596:214] - wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[dec_tlu_ctl.scala 596:45] - wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 316:55] - wire _T_685 = ~_T_43; // @[dec_tlu_ctl.scala 747:49] - wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 747:47] - wire _T_698 = ~soft_int_ready; // @[dec_tlu_ctl.scala 764:40] - wire _T_699 = timer_int_ready & _T_698; // @[dec_tlu_ctl.scala 764:38] - wire _T_617 = ~io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 716:104] - wire ext_int_ready = mhwakeup_ready & _T_617; // @[dec_tlu_ctl.scala 716:102] - wire _T_700 = ~ext_int_ready; // @[dec_tlu_ctl.scala 764:58] - wire _T_701 = _T_699 & _T_700; // @[dec_tlu_ctl.scala 764:56] - wire _T_622 = _T_632 & mip[5]; // @[dec_tlu_ctl.scala 717:65] - wire ce_int_ready = _T_622 & mie_ns[5]; // @[dec_tlu_ctl.scala 717:83] - wire _T_702 = ~ce_int_ready; // @[dec_tlu_ctl.scala 764:75] - wire _T_703 = _T_701 & _T_702; // @[dec_tlu_ctl.scala 764:73] - wire _T_152 = ~debug_mode_status; // @[dec_tlu_ctl.scala 421:37] - reg dbg_halt_req_held; // @[dec_tlu_ctl.scala 464:98] - wire _T_106 = io_dbg_halt_req | dbg_halt_req_held; // @[dec_tlu_ctl.scala 398:48] - reg ext_int_freeze_d1; // @[dec_tlu_ctl.scala 743:90] - wire _T_107 = ~ext_int_freeze_d1; // @[dec_tlu_ctl.scala 398:71] - wire dbg_halt_req_final = _T_106 & _T_107; // @[dec_tlu_ctl.scala 398:69] - wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[dec_tlu_ctl.scala 357:70] - wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 401:50] - reg reset_detect; // @[dec_tlu_ctl.scala 334:106] - reg reset_detected; // @[dec_tlu_ctl.scala 335:98] - wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 336:89] - wire _T_110 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 401:95] - wire _T_111 = reset_delayed & _T_110; // @[dec_tlu_ctl.scala 401:93] - wire _T_112 = _T_109 | _T_111; // @[dec_tlu_ctl.scala 401:76] - wire _T_114 = _T_112 & _T_152; // @[dec_tlu_ctl.scala 401:119] - wire debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 401:147] - wire _T_153 = _T_152 & debug_halt_req; // @[dec_tlu_ctl.scala 421:63] - reg dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 456:90] - wire _T_154 = _T_153 | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 421:81] - reg trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 455:90] - wire _T_155 = _T_154 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 421:107] - reg ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 668:64] - wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 421:132] - reg debug_halt_req_f; // @[dec_tlu_ctl.scala 453:114] - wire force_halt = csr_io_force_halt; // @[dec_tlu_ctl.scala 996:31] - reg lsu_idle_any_f; // @[dec_tlu_ctl.scala 449:114] - wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[dec_tlu_ctl.scala 415:53] - wire _T_143 = _T_142 & io_tlu_mem_ifu_miss_state_idle; // @[dec_tlu_ctl.scala 415:70] - reg ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 450:98] - wire _T_144 = _T_143 & ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 415:103] - wire _T_145 = ~debug_halt_req; // @[dec_tlu_ctl.scala 415:129] - wire _T_146 = _T_144 & _T_145; // @[dec_tlu_ctl.scala 415:127] - reg debug_halt_req_d1; // @[dec_tlu_ctl.scala 457:114] - wire _T_147 = ~debug_halt_req_d1; // @[dec_tlu_ctl.scala 415:147] - wire _T_148 = _T_146 & _T_147; // @[dec_tlu_ctl.scala 415:145] - wire _T_149 = ~io_dec_div_active; // @[dec_tlu_ctl.scala 415:168] - wire _T_150 = _T_148 & _T_149; // @[dec_tlu_ctl.scala 415:166] - wire core_empty = force_halt | _T_150; // @[dec_tlu_ctl.scala 415:34] - wire _T_163 = debug_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 431:48] - reg dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 447:82] - reg dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 463:74] - wire _T_132 = ~dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 411:56] - wire _T_133 = dec_tlu_flush_noredir_r_d1 & _T_132; // @[dec_tlu_ctl.scala 411:54] - reg take_ext_int_start_d1; // @[dec_tlu_ctl.scala 740:74] - wire _T_134 = ~take_ext_int_start_d1; // @[dec_tlu_ctl.scala 411:84] - wire _T_135 = _T_133 & _T_134; // @[dec_tlu_ctl.scala 411:82] - reg halt_taken_f; // @[dec_tlu_ctl.scala 448:122] - reg dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 451:114] - wire _T_136 = ~dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 411:126] - wire _T_137 = halt_taken_f & _T_136; // @[dec_tlu_ctl.scala 411:124] - reg pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 575:74] - wire _T_138 = ~pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 411:146] - wire _T_139 = _T_137 & _T_138; // @[dec_tlu_ctl.scala 411:144] - reg interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 804:91] - wire _T_140 = ~interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 411:169] - wire _T_141 = _T_139 & _T_140; // @[dec_tlu_ctl.scala 411:167] - wire halt_taken = _T_135 | _T_141; // @[dec_tlu_ctl.scala 411:108] - wire _T_164 = _T_163 & halt_taken; // @[dec_tlu_ctl.scala 431:61] - reg debug_resume_req_f; // @[dec_tlu_ctl.scala 454:106] - wire _T_165 = ~debug_resume_req_f; // @[dec_tlu_ctl.scala 431:97] - wire _T_166 = dbg_tlu_halted_f & _T_165; // @[dec_tlu_ctl.scala 431:95] - wire dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 431:75] - wire _T_167 = ~dbg_tlu_halted; // @[dec_tlu_ctl.scala 432:73] - wire _T_168 = debug_halt_req_f & _T_167; // @[dec_tlu_ctl.scala 432:71] - wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[dec_tlu_ctl.scala 432:51] - wire [15:0] dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 1002:31] - wire _T_157 = ~dcsr[2]; // @[dec_tlu_ctl.scala 424:106] - wire _T_158 = debug_resume_req_f & _T_157; // @[dec_tlu_ctl.scala 424:104] - wire _T_159 = ~_T_158; // @[dec_tlu_ctl.scala 424:83] - wire _T_160 = debug_mode_status & _T_159; // @[dec_tlu_ctl.scala 424:81] - wire internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 424:53] - wire _T_177 = debug_resume_req_f & dcsr[2]; // @[dec_tlu_ctl.scala 437:60] - reg dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 462:66] - wire _T_178 = ~dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 437:111] - wire _T_179 = dcsr_single_step_running_f & _T_178; // @[dec_tlu_ctl.scala 437:109] - wire dcsr_single_step_running = _T_177 | _T_179; // @[dec_tlu_ctl.scala 437:79] - wire _T_665 = ~dcsr_single_step_running; // @[dec_tlu_ctl.scala 736:55] - wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 736:81] - wire _T_667 = internal_dbg_halt_mode & _T_666; // @[dec_tlu_ctl.scala 736:52] - wire _T_346 = ~io_dec_tlu_debug_mode; // @[dec_tlu_ctl.scala 565:62] - wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[dec_tlu_ctl.scala 565:60] - wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[dec_tlu_ctl.scala 565:85] - wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[dec_tlu_ctl.scala 581:50] - wire fw_halt_req = csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 1000:31] - wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[dec_tlu_ctl.scala 582:48] - reg pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 574:82] - wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 587:45] - wire _T_372 = _T_371 & halt_taken; // @[dec_tlu_ctl.scala 587:58] - wire _T_373 = ~enter_debug_halt_req; // @[dec_tlu_ctl.scala 587:73] - wire _T_374 = _T_372 & _T_373; // @[dec_tlu_ctl.scala 587:71] - wire _T_375 = ~i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 587:121] - wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[dec_tlu_ctl.scala 587:119] - wire _T_377 = _T_374 | _T_376; // @[dec_tlu_ctl.scala 587:96] - wire _T_378 = ~debug_halt_req_f; // @[dec_tlu_ctl.scala 587:143] - wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[dec_tlu_ctl.scala 587:141] - wire _T_361 = ~pmu_fw_tlu_halted; // @[dec_tlu_ctl.scala 583:72] - wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[dec_tlu_ctl.scala 583:70] - wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[dec_tlu_ctl.scala 583:49] - wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[dec_tlu_ctl.scala 583:93] - reg internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 573:70] - wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[dec_tlu_ctl.scala 584:83] - wire _T_369 = _T_367 & _T_378; // @[dec_tlu_ctl.scala 584:103] - wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[dec_tlu_ctl.scala 584:52] - wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 736:107] - wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 736:135] - wire _T_738 = ~internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 768:35] - wire _T_739 = nmi_int_detected & _T_738; // @[dec_tlu_ctl.scala 768:33] - wire _T_740 = ~internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 768:65] - wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[dec_tlu_ctl.scala 768:119] - wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 768:141] - wire _T_744 = _T_742 & _T_743; // @[dec_tlu_ctl.scala 768:139] - wire _T_746 = _T_744 & _T_178; // @[dec_tlu_ctl.scala 768:164] - wire _T_747 = _T_740 | _T_746; // @[dec_tlu_ctl.scala 768:89] - wire _T_748 = _T_739 & _T_747; // @[dec_tlu_ctl.scala 768:62] - wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 654:52] - wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 654:65] - wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 518:58] + wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 296:76] + wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 299:64] + wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 300:66] + wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 301:52] + wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 302:56] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 993:31] + reg lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 603:74] + wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 306:71] + reg e5_valid; // @[dec_tlu_ctl.scala 318:138] + wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[dec_tlu_ctl.scala 309:39] + reg debug_mode_status; // @[dec_tlu_ctl.scala 319:90] + reg i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 563:81] + reg nmi_int_delayed; // @[dec_tlu_ctl.scala 332:81] + wire _T_37 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 341:45] + wire _T_38 = nmi_int_sync & _T_37; // @[dec_tlu_ctl.scala 341:43] + reg mdseac_locked_f; // @[dec_tlu_ctl.scala 596:89] + wire _T_35 = ~mdseac_locked_f; // @[dec_tlu_ctl.scala 339:32] + wire _T_36 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 339:96] + wire nmi_lsu_detected = _T_35 & _T_36; // @[dec_tlu_ctl.scala 339:49] + wire _T_39 = _T_38 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 341:63] + reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 333:73] + reg take_nmi_r_d1; // @[dec_tlu_ctl.scala 804:107] + wire _T_40 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 341:106] + wire _T_41 = nmi_int_detected_f & _T_40; // @[dec_tlu_ctl.scala 341:104] + wire _T_42 = _T_39 | _T_41; // @[dec_tlu_ctl.scala 341:82] + reg take_ext_int_start_d3; // @[dec_tlu_ctl.scala 736:74] + wire _T_43 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 341:165] + wire _T_44 = take_ext_int_start_d3 & _T_43; // @[dec_tlu_ctl.scala 341:146] + wire nmi_int_detected = _T_42 | _T_44; // @[dec_tlu_ctl.scala 341:122] + wire _T_631 = ~io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 713:23] + wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 992:31] + wire _T_632 = _T_631 & mstatus_mie_ns; // @[dec_tlu_ctl.scala 713:48] + wire [5:0] mip = csr_io_mip; // @[dec_tlu_ctl.scala 998:31] + wire _T_634 = _T_632 & mip[1]; // @[dec_tlu_ctl.scala 713:65] + wire [5:0] mie_ns = csr_io_mie_ns; // @[dec_tlu_ctl.scala 987:31] + wire timer_int_ready = _T_634 & mie_ns[1]; // @[dec_tlu_ctl.scala 713:83] + wire _T_391 = nmi_int_detected | timer_int_ready; // @[dec_tlu_ctl.scala 590:66] + wire _T_628 = _T_632 & mip[0]; // @[dec_tlu_ctl.scala 712:65] + wire soft_int_ready = _T_628 & mie_ns[0]; // @[dec_tlu_ctl.scala 712:83] + wire _T_392 = _T_391 | soft_int_ready; // @[dec_tlu_ctl.scala 590:84] + reg int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 570:74] + wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 590:101] + reg int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 571:74] + wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 590:125] + wire _T_608 = _T_632 & mip[2]; // @[dec_tlu_ctl.scala 709:65] + wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[dec_tlu_ctl.scala 709:83] + wire _T_395 = io_dec_pic_mhwakeup & mhwakeup_ready; // @[dec_tlu_ctl.scala 590:172] + wire _T_396 = _T_394 | _T_395; // @[dec_tlu_ctl.scala 590:149] + wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[dec_tlu_ctl.scala 590:191] + reg i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 562:81] + wire _T_398 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 590:216] + wire _T_399 = _T_397 & _T_398; // @[dec_tlu_ctl.scala 590:214] + wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[dec_tlu_ctl.scala 590:45] + wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 310:55] + wire _T_685 = ~_T_43; // @[dec_tlu_ctl.scala 741:49] + wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 741:47] + wire _T_698 = ~soft_int_ready; // @[dec_tlu_ctl.scala 758:40] + wire _T_699 = timer_int_ready & _T_698; // @[dec_tlu_ctl.scala 758:38] + wire _T_617 = ~io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 710:104] + wire ext_int_ready = mhwakeup_ready & _T_617; // @[dec_tlu_ctl.scala 710:102] + wire _T_700 = ~ext_int_ready; // @[dec_tlu_ctl.scala 758:58] + wire _T_701 = _T_699 & _T_700; // @[dec_tlu_ctl.scala 758:56] + wire _T_622 = _T_632 & mip[5]; // @[dec_tlu_ctl.scala 711:65] + wire ce_int_ready = _T_622 & mie_ns[5]; // @[dec_tlu_ctl.scala 711:83] + wire _T_702 = ~ce_int_ready; // @[dec_tlu_ctl.scala 758:75] + wire _T_703 = _T_701 & _T_702; // @[dec_tlu_ctl.scala 758:73] + wire _T_152 = ~debug_mode_status; // @[dec_tlu_ctl.scala 415:37] + reg dbg_halt_req_held; // @[dec_tlu_ctl.scala 458:98] + wire _T_106 = io_dbg_halt_req | dbg_halt_req_held; // @[dec_tlu_ctl.scala 392:48] + reg ext_int_freeze_d1; // @[dec_tlu_ctl.scala 737:90] + wire _T_107 = ~ext_int_freeze_d1; // @[dec_tlu_ctl.scala 392:71] + wire dbg_halt_req_final = _T_106 & _T_107; // @[dec_tlu_ctl.scala 392:69] + wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[dec_tlu_ctl.scala 351:70] + wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 395:50] + reg reset_detect; // @[dec_tlu_ctl.scala 328:106] + reg reset_detected; // @[dec_tlu_ctl.scala 329:98] + wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 330:89] + wire _T_110 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 395:95] + wire _T_111 = reset_delayed & _T_110; // @[dec_tlu_ctl.scala 395:93] + wire _T_112 = _T_109 | _T_111; // @[dec_tlu_ctl.scala 395:76] + wire _T_114 = _T_112 & _T_152; // @[dec_tlu_ctl.scala 395:119] + wire debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 395:147] + wire _T_153 = _T_152 & debug_halt_req; // @[dec_tlu_ctl.scala 415:63] + reg dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 450:90] + wire _T_154 = _T_153 | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 415:81] + reg trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 449:90] + wire _T_155 = _T_154 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 415:107] + reg ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 662:64] + wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 415:132] + reg debug_halt_req_f; // @[dec_tlu_ctl.scala 447:114] + wire force_halt = csr_io_force_halt; // @[dec_tlu_ctl.scala 990:31] + reg lsu_idle_any_f; // @[dec_tlu_ctl.scala 443:114] + wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[dec_tlu_ctl.scala 409:53] + wire _T_143 = _T_142 & io_tlu_mem_ifu_miss_state_idle; // @[dec_tlu_ctl.scala 409:70] + reg ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 444:98] + wire _T_144 = _T_143 & ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 409:103] + wire _T_145 = ~debug_halt_req; // @[dec_tlu_ctl.scala 409:129] + wire _T_146 = _T_144 & _T_145; // @[dec_tlu_ctl.scala 409:127] + reg debug_halt_req_d1; // @[dec_tlu_ctl.scala 451:114] + wire _T_147 = ~debug_halt_req_d1; // @[dec_tlu_ctl.scala 409:147] + wire _T_148 = _T_146 & _T_147; // @[dec_tlu_ctl.scala 409:145] + wire _T_149 = ~io_dec_div_active; // @[dec_tlu_ctl.scala 409:168] + wire _T_150 = _T_148 & _T_149; // @[dec_tlu_ctl.scala 409:166] + wire core_empty = force_halt | _T_150; // @[dec_tlu_ctl.scala 409:34] + wire _T_163 = debug_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 425:48] + reg dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 441:82] + reg dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 457:74] + wire _T_132 = ~dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 405:56] + wire _T_133 = dec_tlu_flush_noredir_r_d1 & _T_132; // @[dec_tlu_ctl.scala 405:54] + reg take_ext_int_start_d1; // @[dec_tlu_ctl.scala 734:74] + wire _T_134 = ~take_ext_int_start_d1; // @[dec_tlu_ctl.scala 405:84] + wire _T_135 = _T_133 & _T_134; // @[dec_tlu_ctl.scala 405:82] + reg halt_taken_f; // @[dec_tlu_ctl.scala 442:122] + reg dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 445:114] + wire _T_136 = ~dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 405:126] + wire _T_137 = halt_taken_f & _T_136; // @[dec_tlu_ctl.scala 405:124] + reg pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 569:74] + wire _T_138 = ~pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 405:146] + wire _T_139 = _T_137 & _T_138; // @[dec_tlu_ctl.scala 405:144] + reg interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 798:91] + wire _T_140 = ~interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 405:169] + wire _T_141 = _T_139 & _T_140; // @[dec_tlu_ctl.scala 405:167] + wire halt_taken = _T_135 | _T_141; // @[dec_tlu_ctl.scala 405:108] + wire _T_164 = _T_163 & halt_taken; // @[dec_tlu_ctl.scala 425:61] + reg debug_resume_req_f; // @[dec_tlu_ctl.scala 448:106] + wire _T_165 = ~debug_resume_req_f; // @[dec_tlu_ctl.scala 425:97] + wire _T_166 = dbg_tlu_halted_f & _T_165; // @[dec_tlu_ctl.scala 425:95] + wire dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 425:75] + wire _T_167 = ~dbg_tlu_halted; // @[dec_tlu_ctl.scala 426:73] + wire _T_168 = debug_halt_req_f & _T_167; // @[dec_tlu_ctl.scala 426:71] + wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[dec_tlu_ctl.scala 426:51] + wire [15:0] dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 996:31] + wire _T_157 = ~dcsr[2]; // @[dec_tlu_ctl.scala 418:106] + wire _T_158 = debug_resume_req_f & _T_157; // @[dec_tlu_ctl.scala 418:104] + wire _T_159 = ~_T_158; // @[dec_tlu_ctl.scala 418:83] + wire _T_160 = debug_mode_status & _T_159; // @[dec_tlu_ctl.scala 418:81] + wire internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 418:53] + wire _T_177 = debug_resume_req_f & dcsr[2]; // @[dec_tlu_ctl.scala 431:60] + reg dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 456:66] + wire _T_178 = ~dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 431:111] + wire _T_179 = dcsr_single_step_running_f & _T_178; // @[dec_tlu_ctl.scala 431:109] + wire dcsr_single_step_running = _T_177 | _T_179; // @[dec_tlu_ctl.scala 431:79] + wire _T_665 = ~dcsr_single_step_running; // @[dec_tlu_ctl.scala 730:55] + wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 730:81] + wire _T_667 = internal_dbg_halt_mode & _T_666; // @[dec_tlu_ctl.scala 730:52] + wire _T_346 = ~io_dec_tlu_debug_mode; // @[dec_tlu_ctl.scala 559:62] + wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[dec_tlu_ctl.scala 559:60] + wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[dec_tlu_ctl.scala 559:85] + wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[dec_tlu_ctl.scala 575:50] + wire fw_halt_req = csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 994:31] + wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[dec_tlu_ctl.scala 576:48] + reg pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 568:82] + wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 581:45] + wire _T_372 = _T_371 & halt_taken; // @[dec_tlu_ctl.scala 581:58] + wire _T_373 = ~enter_debug_halt_req; // @[dec_tlu_ctl.scala 581:73] + wire _T_374 = _T_372 & _T_373; // @[dec_tlu_ctl.scala 581:71] + wire _T_375 = ~i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 581:121] + wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[dec_tlu_ctl.scala 581:119] + wire _T_377 = _T_374 | _T_376; // @[dec_tlu_ctl.scala 581:96] + wire _T_378 = ~debug_halt_req_f; // @[dec_tlu_ctl.scala 581:143] + wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[dec_tlu_ctl.scala 581:141] + wire _T_361 = ~pmu_fw_tlu_halted; // @[dec_tlu_ctl.scala 577:72] + wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[dec_tlu_ctl.scala 577:70] + wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[dec_tlu_ctl.scala 577:49] + wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[dec_tlu_ctl.scala 577:93] + reg internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 567:70] + wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[dec_tlu_ctl.scala 578:83] + wire _T_369 = _T_367 & _T_378; // @[dec_tlu_ctl.scala 578:103] + wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[dec_tlu_ctl.scala 578:52] + wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 730:107] + wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 730:135] + wire _T_738 = ~internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 762:35] + wire _T_739 = nmi_int_detected & _T_738; // @[dec_tlu_ctl.scala 762:33] + wire _T_740 = ~internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 762:65] + wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[dec_tlu_ctl.scala 762:119] + wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 762:141] + wire _T_744 = _T_742 & _T_743; // @[dec_tlu_ctl.scala 762:139] + wire _T_746 = _T_744 & _T_178; // @[dec_tlu_ctl.scala 762:164] + wire _T_747 = _T_740 | _T_746; // @[dec_tlu_ctl.scala 762:89] + wire _T_748 = _T_739 & _T_747; // @[dec_tlu_ctl.scala 762:62] + wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 648:52] + wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 648:65] + wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 512:58] wire [3:0] _T_299 = _T_297 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_300 = ~_T_299; // @[dec_tlu_ctl.scala 518:23] + wire [3:0] _T_300 = ~_T_299; // @[dec_tlu_ctl.scala 512:23] wire [3:0] _T_292 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 516:53] - wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1005:31] - wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1005:31] - wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1005:31] - wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1005:31] + wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 510:53] + wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 150:67 dec_tlu_ctl.scala 999:31] + wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 150:67 dec_tlu_ctl.scala 999:31] + wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 150:67 dec_tlu_ctl.scala 999:31] + wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 150:67 dec_tlu_ctl.scala 999:31] wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58] wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58] - wire [3:0] _T_279 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 508:57] - wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 662:49] + wire [3:0] _T_279 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 502:57] + wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 656:49] wire [3:0] _T_281 = inst_acc_r_raw ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_282 = _T_279 & _T_281; // @[dec_tlu_ctl.scala 508:72] - wire _T_283 = io_tlu_exu_exu_i0_br_error_r | io_tlu_exu_exu_i0_br_start_error_r; // @[dec_tlu_ctl.scala 508:137] + wire [3:0] _T_282 = _T_279 & _T_281; // @[dec_tlu_ctl.scala 502:72] + wire _T_283 = io_tlu_exu_exu_i0_br_error_r | io_tlu_exu_exu_i0_br_start_error_r; // @[dec_tlu_ctl.scala 502:137] wire [3:0] _T_285 = _T_283 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_286 = _T_282 | _T_285; // @[dec_tlu_ctl.scala 508:98] - wire [3:0] i0_iside_trigger_has_pri_r = ~_T_286; // @[dec_tlu_ctl.scala 508:38] - wire [3:0] _T_295 = _T_294 & i0_iside_trigger_has_pri_r; // @[dec_tlu_ctl.scala 516:90] + wire [3:0] _T_286 = _T_282 | _T_285; // @[dec_tlu_ctl.scala 502:98] + wire [3:0] i0_iside_trigger_has_pri_r = ~_T_286; // @[dec_tlu_ctl.scala 502:38] + wire [3:0] _T_295 = _T_294 & i0_iside_trigger_has_pri_r; // @[dec_tlu_ctl.scala 510:90] wire [3:0] trigger_store = {mtdata1_t_3[1],mtdata1_t_2[1],mtdata1_t_1[1],mtdata1_t_0[1]}; // @[Cat.scala 29:58] - wire [3:0] _T_287 = trigger_store & trigger_data; // @[dec_tlu_ctl.scala 511:51] + wire [3:0] _T_287 = trigger_store & trigger_data; // @[dec_tlu_ctl.scala 505:51] wire [3:0] _T_289 = io_lsu_error_pkt_r_valid ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_290 = _T_287 & _T_289; // @[dec_tlu_ctl.scala 511:66] - wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[dec_tlu_ctl.scala 511:35] - wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[dec_tlu_ctl.scala 516:119] - wire [1:0] mstatus = csr_io_mstatus; // @[dec_tlu_ctl.scala 1001:31] - wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[dec_tlu_ctl.scala 505:62] - wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 505:86] - wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[dec_tlu_ctl.scala 505:150] - wire _T_266 = _T_264 & mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 505:174] - wire _T_269 = mtdata1_t_1[6] | mstatus[0]; // @[dec_tlu_ctl.scala 505:239] - wire _T_271 = _T_269 & mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 505:263] - wire _T_274 = mtdata1_t_0[6] | mstatus[0]; // @[dec_tlu_ctl.scala 505:328] - wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 505:352] + wire [3:0] _T_290 = _T_287 & _T_289; // @[dec_tlu_ctl.scala 505:66] + wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[dec_tlu_ctl.scala 505:35] + wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[dec_tlu_ctl.scala 510:119] + wire [1:0] mstatus = csr_io_mstatus; // @[dec_tlu_ctl.scala 995:31] + wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[dec_tlu_ctl.scala 499:62] + wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 499:86] + wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[dec_tlu_ctl.scala 499:150] + wire _T_266 = _T_264 & mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 499:174] + wire _T_269 = mtdata1_t_1[6] | mstatus[0]; // @[dec_tlu_ctl.scala 499:239] + wire _T_271 = _T_269 & mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 499:263] + wire _T_274 = mtdata1_t_0[6] | mstatus[0]; // @[dec_tlu_ctl.scala 499:328] + wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 499:352] wire [3:0] trigger_enabled = {_T_261,_T_266,_T_271,_T_276}; // @[Cat.scala 29:58] - wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[dec_tlu_ctl.scala 516:146] - wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 518:84] - wire _T_303 = ~mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 521:60] - wire _T_305 = _T_303 | i0_trigger_r[2]; // @[dec_tlu_ctl.scala 521:89] - wire _T_306 = i0_trigger_r[3] & _T_305; // @[dec_tlu_ctl.scala 521:57] - wire _T_311 = _T_303 | i0_trigger_r[3]; // @[dec_tlu_ctl.scala 521:157] - wire _T_312 = i0_trigger_r[2] & _T_311; // @[dec_tlu_ctl.scala 521:125] - wire _T_315 = ~mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 521:196] - wire _T_317 = _T_315 | i0_trigger_r[0]; // @[dec_tlu_ctl.scala 521:225] - wire _T_318 = i0_trigger_r[1] & _T_317; // @[dec_tlu_ctl.scala 521:193] - wire _T_323 = _T_315 | i0_trigger_r[1]; // @[dec_tlu_ctl.scala 521:293] - wire _T_324 = i0_trigger_r[0] & _T_323; // @[dec_tlu_ctl.scala 521:261] + wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[dec_tlu_ctl.scala 510:146] + wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 512:84] + wire _T_303 = ~mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 515:60] + wire _T_305 = _T_303 | i0_trigger_r[2]; // @[dec_tlu_ctl.scala 515:89] + wire _T_306 = i0_trigger_r[3] & _T_305; // @[dec_tlu_ctl.scala 515:57] + wire _T_311 = _T_303 | i0_trigger_r[3]; // @[dec_tlu_ctl.scala 515:157] + wire _T_312 = i0_trigger_r[2] & _T_311; // @[dec_tlu_ctl.scala 515:125] + wire _T_315 = ~mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 515:196] + wire _T_317 = _T_315 | i0_trigger_r[0]; // @[dec_tlu_ctl.scala 515:225] + wire _T_318 = i0_trigger_r[1] & _T_317; // @[dec_tlu_ctl.scala 515:193] + wire _T_323 = _T_315 | i0_trigger_r[1]; // @[dec_tlu_ctl.scala 515:293] + wire _T_324 = i0_trigger_r[0] & _T_323; // @[dec_tlu_ctl.scala 515:261] wire [3:0] i0_trigger_chain_masked_r = {_T_306,_T_312,_T_318,_T_324}; // @[Cat.scala 29:58] - wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 524:57] - wire _T_465 = ~i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 654:91] - wire _T_466 = _T_464 & _T_465; // @[dec_tlu_ctl.scala 654:89] - wire _T_468 = ~dcsr[15]; // @[dec_tlu_ctl.scala 654:111] - wire _T_469 = _T_466 & _T_468; // @[dec_tlu_ctl.scala 654:109] - reg tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 328:90] - wire _T_429 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 629:44] - wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[dec_tlu_ctl.scala 629:42] - wire _T_432 = _T_430 & _T_283; // @[dec_tlu_ctl.scala 629:66] - reg ic_perr_r_d1; // @[dec_tlu_ctl.scala 322:122] - reg iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 323:114] - wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 629:154] - wire _T_435 = _T_433 & _T_107; // @[dec_tlu_ctl.scala 629:173] - wire _T_436 = _T_432 | _T_435; // @[dec_tlu_ctl.scala 629:137] - wire _T_438 = _T_436 & _T_465; // @[dec_tlu_ctl.scala 629:196] - wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[dec_tlu_ctl.scala 617:47] - wire _T_411 = ~io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 617:70] - wire _T_412 = _T_411 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec_tlu_ctl.scala 617:105] - wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[dec_tlu_ctl.scala 617:67] - wire _T_439 = ~lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 629:220] - wire rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 629:217] - wire _T_470 = ~rfpc_i0_r; // @[dec_tlu_ctl.scala 654:133] - wire ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 654:131] - wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[dec_tlu_ctl.scala 655:52] - wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 655:65] - wire _T_475 = _T_473 & _T_465; // @[dec_tlu_ctl.scala 655:89] - wire ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 655:109] - wire _T_523 = ebreak_r | ecall_r; // @[dec_tlu_ctl.scala 682:41] - wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[dec_tlu_ctl.scala 656:18] - wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 656:47] - wire _T_481 = _T_479 & _T_465; // @[dec_tlu_ctl.scala 656:71] - wire illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 656:91] - wire _T_524 = _T_523 | illegal_r; // @[dec_tlu_ctl.scala 682:51] - wire _T_511 = inst_acc_r_raw & _T_470; // @[dec_tlu_ctl.scala 663:33] - wire inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 663:46] - wire _T_525 = _T_524 | inst_acc_r; // @[dec_tlu_ctl.scala 682:63] - wire _T_527 = _T_525 & _T_470; // @[dec_tlu_ctl.scala 682:77] - wire _T_528 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 682:92] - wire i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 682:90] - wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[dec_tlu_ctl.scala 781:49] - wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 605:57] - wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[dec_tlu_ctl.scala 605:55] - wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 607:40] - wire _T_405 = _T_403 & _T_465; // @[dec_tlu_ctl.scala 607:62] - wire lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 607:82] - wire _T_790 = _T_789 | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 781:61] - wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 659:50] - wire _T_492 = _T_490 & _T_465; // @[dec_tlu_ctl.scala 659:74] - wire fence_i_r = _T_492 & _T_470; // @[dec_tlu_ctl.scala 659:95] - wire _T_791 = _T_790 | fence_i_r; // @[dec_tlu_ctl.scala 781:79] - wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 781:91] - wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[dec_tlu_ctl.scala 620:50] - wire _T_415 = ~lsu_exc_valid_r; // @[dec_tlu_ctl.scala 620:65] - wire _T_416 = _T_414 & _T_415; // @[dec_tlu_ctl.scala 620:63] - wire _T_417 = ~inst_acc_r; // @[dec_tlu_ctl.scala 620:82] - wire _T_418 = _T_416 & _T_417; // @[dec_tlu_ctl.scala 620:79] - wire _T_420 = _T_418 & _T_528; // @[dec_tlu_ctl.scala 620:94] - reg request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 460:82] - wire _T_421 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 620:121] - wire _T_422 = _T_420 & _T_421; // @[dec_tlu_ctl.scala 620:119] - wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 620:146] - reg iccm_repair_state_d1; // @[dec_tlu_ctl.scala 321:90] - wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 638:52] - wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 657:58] - wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 657:71] - wire _T_487 = _T_485 & _T_465; // @[dec_tlu_ctl.scala 657:95] - wire mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 657:115] - wire _T_446 = _T_523 | mret_r; // @[dec_tlu_ctl.scala 638:98] - wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 767:32] - wire _T_447 = _T_446 | take_reset; // @[dec_tlu_ctl.scala 638:107] - wire _T_448 = _T_447 | illegal_r; // @[dec_tlu_ctl.scala 638:120] - wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 638:176] - wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[dec_tlu_ctl.scala 638:153] - wire _T_451 = _T_448 | _T_450; // @[dec_tlu_ctl.scala 638:132] - wire _T_452 = ~_T_451; // @[dec_tlu_ctl.scala 638:77] - wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[dec_tlu_ctl.scala 638:75] - wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 781:108] - wire _T_794 = _T_793 | debug_resume_req_f; // @[dec_tlu_ctl.scala 781:135] - wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 779:43] - wire _T_211 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 480:28] - reg dec_pause_state_f; // @[dec_tlu_ctl.scala 459:98] - wire _T_212 = _T_211 & dec_pause_state_f; // @[dec_tlu_ctl.scala 480:48] - wire _T_213 = ext_int_ready | ce_int_ready; // @[dec_tlu_ctl.scala 480:86] - wire _T_214 = _T_213 | timer_int_ready; // @[dec_tlu_ctl.scala 480:101] - wire _T_215 = _T_214 | soft_int_ready; // @[dec_tlu_ctl.scala 480:119] - wire _T_216 = _T_215 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 480:136] - wire _T_217 = _T_216 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 480:160] - wire _T_218 = _T_217 | nmi_int_detected; // @[dec_tlu_ctl.scala 480:184] - wire _T_219 = _T_218 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 480:203] - wire _T_220 = ~_T_219; // @[dec_tlu_ctl.scala 480:70] - wire _T_221 = _T_212 & _T_220; // @[dec_tlu_ctl.scala 480:68] - wire _T_223 = _T_221 & _T_140; // @[dec_tlu_ctl.scala 480:224] - wire _T_225 = _T_223 & _T_378; // @[dec_tlu_ctl.scala 480:248] - wire _T_226 = ~pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 480:270] - wire _T_227 = _T_225 & _T_226; // @[dec_tlu_ctl.scala 480:268] - wire _T_228 = ~halt_taken_f; // @[dec_tlu_ctl.scala 480:291] - wire pause_expired_r = _T_227 & _T_228; // @[dec_tlu_ctl.scala 480:289] - wire sel_npc_resume = _T_786 | pause_expired_r; // @[dec_tlu_ctl.scala 779:66] - wire _T_795 = _T_794 | sel_npc_resume; // @[dec_tlu_ctl.scala 781:157] - reg dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 458:90] - wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 781:175] - wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 781:201] - wire _T_749 = ~synchronous_flush_r; // @[dec_tlu_ctl.scala 768:195] - wire _T_750 = _T_748 & _T_749; // @[dec_tlu_ctl.scala 768:193] - wire _T_751 = ~mret_r; // @[dec_tlu_ctl.scala 768:218] - wire _T_752 = _T_750 & _T_751; // @[dec_tlu_ctl.scala 768:216] - wire _T_753 = ~take_reset; // @[dec_tlu_ctl.scala 768:228] - wire _T_754 = _T_752 & _T_753; // @[dec_tlu_ctl.scala 768:226] - wire _T_519 = _T_466 & dcsr[15]; // @[dec_tlu_ctl.scala 666:121] - wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 666:142] - wire _T_755 = ~ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 768:242] - wire _T_756 = _T_754 & _T_755; // @[dec_tlu_ctl.scala 768:240] - wire _T_760 = _T_107 | _T_44; // @[dec_tlu_ctl.scala 768:288] - wire take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 768:266] - wire _T_670 = _T_669 | take_nmi; // @[dec_tlu_ctl.scala 736:155] - wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 736:166] - wire _T_672 = _T_671 | synchronous_flush_r; // @[dec_tlu_ctl.scala 736:191] - reg exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 806:91] - wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 736:214] - wire _T_674 = _T_673 | mret_r; // @[dec_tlu_ctl.scala 736:238] - wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 736:247] - wire _T_704 = ~block_interrupts; // @[dec_tlu_ctl.scala 764:91] - wire take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 764:89] - wire _T_762 = take_ext_int | take_timer_int; // @[dec_tlu_ctl.scala 771:38] - wire _T_693 = soft_int_ready & _T_700; // @[dec_tlu_ctl.scala 763:36] - wire _T_695 = _T_693 & _T_702; // @[dec_tlu_ctl.scala 763:53] - wire take_soft_int = _T_695 & _T_704; // @[dec_tlu_ctl.scala 763:69] - wire _T_763 = _T_762 | take_soft_int; // @[dec_tlu_ctl.scala 771:55] - wire _T_764 = _T_763 | take_nmi; // @[dec_tlu_ctl.scala 771:71] - wire _T_689 = ce_int_ready & _T_700; // @[dec_tlu_ctl.scala 762:33] - wire take_ce_int = _T_689 & _T_704; // @[dec_tlu_ctl.scala 762:50] - wire _T_765 = _T_764 | take_ce_int; // @[dec_tlu_ctl.scala 771:82] - wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[dec_tlu_ctl.scala 722:49] - wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[dec_tlu_ctl.scala 723:47] - wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 765:49] - wire _T_707 = _T_706 & int_timer0_int_possible; // @[dec_tlu_ctl.scala 765:74] - wire _T_709 = _T_707 & _T_631; // @[dec_tlu_ctl.scala 765:100] - wire _T_710 = ~timer_int_ready; // @[dec_tlu_ctl.scala 765:129] - wire _T_711 = _T_709 & _T_710; // @[dec_tlu_ctl.scala 765:127] - wire _T_713 = _T_711 & _T_698; // @[dec_tlu_ctl.scala 765:146] - wire _T_715 = _T_713 & _T_700; // @[dec_tlu_ctl.scala 765:164] - wire _T_717 = _T_715 & _T_702; // @[dec_tlu_ctl.scala 765:181] - wire take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 765:197] - wire _T_766 = _T_765 | take_int_timer0_int; // @[dec_tlu_ctl.scala 771:96] - wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[dec_tlu_ctl.scala 724:49] - wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[dec_tlu_ctl.scala 725:47] - wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 766:49] - wire _T_721 = _T_720 & int_timer1_int_possible; // @[dec_tlu_ctl.scala 766:74] - wire _T_723 = _T_721 & _T_631; // @[dec_tlu_ctl.scala 766:100] - wire _T_725 = ~_T_706; // @[dec_tlu_ctl.scala 766:129] - wire _T_726 = _T_723 & _T_725; // @[dec_tlu_ctl.scala 766:127] - wire _T_728 = _T_726 & _T_710; // @[dec_tlu_ctl.scala 766:177] - wire _T_730 = _T_728 & _T_698; // @[dec_tlu_ctl.scala 766:196] - wire _T_732 = _T_730 & _T_700; // @[dec_tlu_ctl.scala 766:214] - wire _T_734 = _T_732 & _T_702; // @[dec_tlu_ctl.scala 766:231] - wire take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 766:247] - wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 771:118] - wire _T_15 = _T_14 | interrupt_valid_r; // @[dec_tlu_ctl.scala 316:74] - wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 316:94] - wire _T_17 = _T_16 | reset_delayed; // @[dec_tlu_ctl.scala 316:117] - wire _T_18 = _T_17 | pause_expired_r; // @[dec_tlu_ctl.scala 316:133] - reg pause_expired_wb; // @[dec_tlu_ctl.scala 811:91] - wire _T_19 = _T_18 | pause_expired_wb; // @[dec_tlu_ctl.scala 316:151] - wire _T_496 = io_tlu_mem_ifu_ic_error_start & _T_107; // @[dec_tlu_ctl.scala 660:51] - wire _T_498 = _T_152 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 660:101] - wire _T_499 = _T_496 & _T_498; // @[dec_tlu_ctl.scala 660:72] - wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 660:131] - wire ic_perr_r = _T_499 & _T_500; // @[dec_tlu_ctl.scala 660:129] - wire _T_20 = _T_19 | ic_perr_r; // @[dec_tlu_ctl.scala 316:170] - wire _T_21 = _T_20 | ic_perr_r_d1; // @[dec_tlu_ctl.scala 316:182] - wire _T_503 = io_tlu_mem_ifu_iccm_rd_ecc_single_err & _T_107; // @[dec_tlu_ctl.scala 661:59] - wire _T_506 = _T_503 & _T_498; // @[dec_tlu_ctl.scala 661:80] - wire iccm_sbecc_r = _T_506 & _T_500; // @[dec_tlu_ctl.scala 661:137] - wire _T_22 = _T_21 | iccm_sbecc_r; // @[dec_tlu_ctl.scala 316:197] - wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 316:212] - wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 316:230] - reg lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 326:82] - reg lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 327:74] - reg _T_32; // @[dec_tlu_ctl.scala 329:74] - reg internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 330:74] - reg _T_33; // @[dec_tlu_ctl.scala 331:74] - reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 340:73] - reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 341:73] - wire _T_46 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 349:48] - wire _T_49 = ~_T_41; // @[dec_tlu_ctl.scala 349:96] - wire _T_50 = _T_46 & _T_49; // @[dec_tlu_ctl.scala 349:94] - wire _T_52 = nmi_lsu_load_type_f & _T_40; // @[dec_tlu_ctl.scala 349:159] - wire _T_54 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 350:49] - wire _T_58 = _T_54 & _T_49; // @[dec_tlu_ctl.scala 350:96] - wire _T_60 = nmi_lsu_store_type_f & _T_40; // @[dec_tlu_ctl.scala 350:162] - reg mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 358:74] - reg mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 359:74] - reg mpc_run_state_f; // @[dec_tlu_ctl.scala 361:106] - reg debug_brkpt_status_f; // @[dec_tlu_ctl.scala 362:90] - reg mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 363:90] - reg mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 364:90] - reg dbg_run_state_f; // @[dec_tlu_ctl.scala 366:106] - reg _T_65; // @[dec_tlu_ctl.scala 367:82] - wire _T_66 = ~mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 371:71] - wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_66; // @[dec_tlu_ctl.scala 371:69] - wire _T_67 = ~mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 372:70] - wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_67; // @[dec_tlu_ctl.scala 372:68] - wire _T_68 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[dec_tlu_ctl.scala 374:48] - wire _T_71 = _T_68 | _T_111; // @[dec_tlu_ctl.scala 374:80] - wire _T_72 = ~mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 374:125] - wire mpc_halt_state_ns = _T_71 & _T_72; // @[dec_tlu_ctl.scala 374:123] - wire _T_74 = ~mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 375:80] - wire _T_75 = mpc_debug_run_req_sync_pulse & _T_74; // @[dec_tlu_ctl.scala 375:78] - wire _T_76 = mpc_run_state_f | _T_75; // @[dec_tlu_ctl.scala 375:46] - wire _T_77 = ~dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 375:133] - wire _T_78 = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 375:131] - wire mpc_run_state_ns = _T_76 & _T_78; // @[dec_tlu_ctl.scala 375:103] - wire _T_80 = dbg_halt_req_final | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 377:70] - wire _T_81 = _T_80 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 377:96] - wire _T_82 = _T_81 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 377:121] - wire _T_83 = dbg_halt_state_f | _T_82; // @[dec_tlu_ctl.scala 377:48] - wire _T_84 = ~io_dbg_resume_req; // @[dec_tlu_ctl.scala 377:153] - wire dbg_halt_state_ns = _T_83 & _T_84; // @[dec_tlu_ctl.scala 377:151] - wire _T_86 = dbg_run_state_f | io_dbg_resume_req; // @[dec_tlu_ctl.scala 378:46] - wire dbg_run_state_ns = _T_86 & _T_78; // @[dec_tlu_ctl.scala 378:67] - wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 384:59] - wire _T_92 = debug_brkpt_valid | debug_brkpt_status_f; // @[dec_tlu_ctl.scala 385:53] - wire _T_94 = internal_dbg_halt_mode & _T_77; // @[dec_tlu_ctl.scala 385:103] - wire _T_96 = mpc_halt_state_f & debug_mode_status; // @[dec_tlu_ctl.scala 388:51] - wire _T_97 = _T_96 & mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 388:78] - wire _T_99 = ~dbg_halt_state_ns; // @[dec_tlu_ctl.scala 389:59] - wire _T_100 = mpc_debug_run_req_sync & _T_99; // @[dec_tlu_ctl.scala 389:57] - wire _T_101 = ~mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 389:80] - wire _T_102 = _T_100 & _T_101; // @[dec_tlu_ctl.scala 389:78] - wire _T_103 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 389:129] - wire _T_118 = mpc_run_state_ns & _T_99; // @[dec_tlu_ctl.scala 403:73] - wire _T_119 = ~mpc_halt_state_ns; // @[dec_tlu_ctl.scala 403:117] - wire _T_120 = dbg_run_state_ns & _T_119; // @[dec_tlu_ctl.scala 403:115] - wire _T_121 = _T_118 | _T_120; // @[dec_tlu_ctl.scala 403:95] - wire _T_122 = debug_halt_req_f | pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 408:43] - wire _T_124 = _T_122 & _T_749; // @[dec_tlu_ctl.scala 408:64] - wire _T_126 = _T_124 & _T_751; // @[dec_tlu_ctl.scala 408:87] - wire _T_128 = _T_126 & _T_228; // @[dec_tlu_ctl.scala 408:97] - wire _T_129 = ~dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 408:115] - wire _T_130 = _T_128 & _T_129; // @[dec_tlu_ctl.scala 408:113] - wire take_halt = _T_130 & _T_753; // @[dec_tlu_ctl.scala 408:143] - wire _T_170 = debug_resume_req_f & dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 433:49] - wire _T_172 = io_dec_tlu_i0_valid_r & _T_528; // @[dec_tlu_ctl.scala 435:59] - wire _T_174 = _T_172 & dcsr[2]; // @[dec_tlu_ctl.scala 435:84] - wire _T_329 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 530:61] - wire _T_332 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 530:121] - wire _T_335 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 530:181] - wire _T_338 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 530:241] + wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 518:57] + wire _T_465 = ~i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 648:91] + wire _T_466 = _T_464 & _T_465; // @[dec_tlu_ctl.scala 648:89] + wire _T_468 = ~dcsr[15]; // @[dec_tlu_ctl.scala 648:111] + wire _T_469 = _T_466 & _T_468; // @[dec_tlu_ctl.scala 648:109] + reg tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 322:90] + wire _T_429 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 623:44] + wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[dec_tlu_ctl.scala 623:42] + wire _T_432 = _T_430 & _T_283; // @[dec_tlu_ctl.scala 623:66] + reg ic_perr_r_d1; // @[dec_tlu_ctl.scala 316:122] + reg iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 317:114] + wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 623:154] + wire _T_435 = _T_433 & _T_107; // @[dec_tlu_ctl.scala 623:173] + wire _T_436 = _T_432 | _T_435; // @[dec_tlu_ctl.scala 623:137] + wire _T_438 = _T_436 & _T_465; // @[dec_tlu_ctl.scala 623:196] + wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[dec_tlu_ctl.scala 611:47] + wire _T_411 = ~io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 611:70] + wire _T_412 = _T_411 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec_tlu_ctl.scala 611:105] + wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[dec_tlu_ctl.scala 611:67] + wire _T_439 = ~lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 623:220] + wire rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 623:217] + wire _T_470 = ~rfpc_i0_r; // @[dec_tlu_ctl.scala 648:133] + wire ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 648:131] + wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[dec_tlu_ctl.scala 649:52] + wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 649:65] + wire _T_475 = _T_473 & _T_465; // @[dec_tlu_ctl.scala 649:89] + wire ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 649:109] + wire _T_523 = ebreak_r | ecall_r; // @[dec_tlu_ctl.scala 676:41] + wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[dec_tlu_ctl.scala 650:18] + wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 650:47] + wire _T_481 = _T_479 & _T_465; // @[dec_tlu_ctl.scala 650:71] + wire illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 650:91] + wire _T_524 = _T_523 | illegal_r; // @[dec_tlu_ctl.scala 676:51] + wire _T_511 = inst_acc_r_raw & _T_470; // @[dec_tlu_ctl.scala 657:33] + wire inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 657:46] + wire _T_525 = _T_524 | inst_acc_r; // @[dec_tlu_ctl.scala 676:63] + wire _T_527 = _T_525 & _T_470; // @[dec_tlu_ctl.scala 676:77] + wire _T_528 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 676:92] + wire i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 676:90] + wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[dec_tlu_ctl.scala 775:49] + wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 599:57] + wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[dec_tlu_ctl.scala 599:55] + wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 601:40] + wire _T_405 = _T_403 & _T_465; // @[dec_tlu_ctl.scala 601:62] + wire lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 601:82] + wire _T_790 = _T_789 | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 775:61] + wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 653:50] + wire _T_492 = _T_490 & _T_465; // @[dec_tlu_ctl.scala 653:74] + wire fence_i_r = _T_492 & _T_470; // @[dec_tlu_ctl.scala 653:95] + wire _T_791 = _T_790 | fence_i_r; // @[dec_tlu_ctl.scala 775:79] + wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 775:91] + wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[dec_tlu_ctl.scala 614:50] + wire _T_415 = ~lsu_exc_valid_r; // @[dec_tlu_ctl.scala 614:65] + wire _T_416 = _T_414 & _T_415; // @[dec_tlu_ctl.scala 614:63] + wire _T_417 = ~inst_acc_r; // @[dec_tlu_ctl.scala 614:82] + wire _T_418 = _T_416 & _T_417; // @[dec_tlu_ctl.scala 614:79] + wire _T_420 = _T_418 & _T_528; // @[dec_tlu_ctl.scala 614:94] + reg request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 454:82] + wire _T_421 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 614:121] + wire _T_422 = _T_420 & _T_421; // @[dec_tlu_ctl.scala 614:119] + wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 614:146] + reg iccm_repair_state_d1; // @[dec_tlu_ctl.scala 315:90] + wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 632:52] + wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 651:58] + wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 651:71] + wire _T_487 = _T_485 & _T_465; // @[dec_tlu_ctl.scala 651:95] + wire mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 651:115] + wire _T_446 = _T_523 | mret_r; // @[dec_tlu_ctl.scala 632:98] + wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 761:32] + wire _T_447 = _T_446 | take_reset; // @[dec_tlu_ctl.scala 632:107] + wire _T_448 = _T_447 | illegal_r; // @[dec_tlu_ctl.scala 632:120] + wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 632:176] + wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[dec_tlu_ctl.scala 632:153] + wire _T_451 = _T_448 | _T_450; // @[dec_tlu_ctl.scala 632:132] + wire _T_452 = ~_T_451; // @[dec_tlu_ctl.scala 632:77] + wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[dec_tlu_ctl.scala 632:75] + wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 775:108] + wire _T_794 = _T_793 | debug_resume_req_f; // @[dec_tlu_ctl.scala 775:135] + wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 773:43] + wire _T_211 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 474:28] + reg dec_pause_state_f; // @[dec_tlu_ctl.scala 453:98] + wire _T_212 = _T_211 & dec_pause_state_f; // @[dec_tlu_ctl.scala 474:48] + wire _T_213 = ext_int_ready | ce_int_ready; // @[dec_tlu_ctl.scala 474:86] + wire _T_214 = _T_213 | timer_int_ready; // @[dec_tlu_ctl.scala 474:101] + wire _T_215 = _T_214 | soft_int_ready; // @[dec_tlu_ctl.scala 474:119] + wire _T_216 = _T_215 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 474:136] + wire _T_217 = _T_216 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 474:160] + wire _T_218 = _T_217 | nmi_int_detected; // @[dec_tlu_ctl.scala 474:184] + wire _T_219 = _T_218 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 474:203] + wire _T_220 = ~_T_219; // @[dec_tlu_ctl.scala 474:70] + wire _T_221 = _T_212 & _T_220; // @[dec_tlu_ctl.scala 474:68] + wire _T_223 = _T_221 & _T_140; // @[dec_tlu_ctl.scala 474:224] + wire _T_225 = _T_223 & _T_378; // @[dec_tlu_ctl.scala 474:248] + wire _T_226 = ~pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 474:270] + wire _T_227 = _T_225 & _T_226; // @[dec_tlu_ctl.scala 474:268] + wire _T_228 = ~halt_taken_f; // @[dec_tlu_ctl.scala 474:291] + wire pause_expired_r = _T_227 & _T_228; // @[dec_tlu_ctl.scala 474:289] + wire sel_npc_resume = _T_786 | pause_expired_r; // @[dec_tlu_ctl.scala 773:66] + wire _T_795 = _T_794 | sel_npc_resume; // @[dec_tlu_ctl.scala 775:157] + reg dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 452:90] + wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 775:175] + wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 775:201] + wire _T_749 = ~synchronous_flush_r; // @[dec_tlu_ctl.scala 762:195] + wire _T_750 = _T_748 & _T_749; // @[dec_tlu_ctl.scala 762:193] + wire _T_751 = ~mret_r; // @[dec_tlu_ctl.scala 762:218] + wire _T_752 = _T_750 & _T_751; // @[dec_tlu_ctl.scala 762:216] + wire _T_753 = ~take_reset; // @[dec_tlu_ctl.scala 762:228] + wire _T_754 = _T_752 & _T_753; // @[dec_tlu_ctl.scala 762:226] + wire _T_519 = _T_466 & dcsr[15]; // @[dec_tlu_ctl.scala 660:121] + wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 660:142] + wire _T_755 = ~ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 762:242] + wire _T_756 = _T_754 & _T_755; // @[dec_tlu_ctl.scala 762:240] + wire _T_760 = _T_107 | _T_44; // @[dec_tlu_ctl.scala 762:288] + wire take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 762:266] + wire _T_670 = _T_669 | take_nmi; // @[dec_tlu_ctl.scala 730:155] + wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 730:166] + wire _T_672 = _T_671 | synchronous_flush_r; // @[dec_tlu_ctl.scala 730:191] + reg exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 800:91] + wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 730:214] + wire _T_674 = _T_673 | mret_r; // @[dec_tlu_ctl.scala 730:238] + wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 730:247] + wire _T_704 = ~block_interrupts; // @[dec_tlu_ctl.scala 758:91] + wire take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 758:89] + wire _T_762 = take_ext_int | take_timer_int; // @[dec_tlu_ctl.scala 765:38] + wire _T_693 = soft_int_ready & _T_700; // @[dec_tlu_ctl.scala 757:36] + wire _T_695 = _T_693 & _T_702; // @[dec_tlu_ctl.scala 757:53] + wire take_soft_int = _T_695 & _T_704; // @[dec_tlu_ctl.scala 757:69] + wire _T_763 = _T_762 | take_soft_int; // @[dec_tlu_ctl.scala 765:55] + wire _T_764 = _T_763 | take_nmi; // @[dec_tlu_ctl.scala 765:71] + wire _T_689 = ce_int_ready & _T_700; // @[dec_tlu_ctl.scala 756:33] + wire take_ce_int = _T_689 & _T_704; // @[dec_tlu_ctl.scala 756:50] + wire _T_765 = _T_764 | take_ce_int; // @[dec_tlu_ctl.scala 765:82] + wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[dec_tlu_ctl.scala 716:49] + wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[dec_tlu_ctl.scala 717:47] + wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 759:49] + wire _T_707 = _T_706 & int_timer0_int_possible; // @[dec_tlu_ctl.scala 759:74] + wire _T_709 = _T_707 & _T_631; // @[dec_tlu_ctl.scala 759:100] + wire _T_710 = ~timer_int_ready; // @[dec_tlu_ctl.scala 759:129] + wire _T_711 = _T_709 & _T_710; // @[dec_tlu_ctl.scala 759:127] + wire _T_713 = _T_711 & _T_698; // @[dec_tlu_ctl.scala 759:146] + wire _T_715 = _T_713 & _T_700; // @[dec_tlu_ctl.scala 759:164] + wire _T_717 = _T_715 & _T_702; // @[dec_tlu_ctl.scala 759:181] + wire take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 759:197] + wire _T_766 = _T_765 | take_int_timer0_int; // @[dec_tlu_ctl.scala 765:96] + wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[dec_tlu_ctl.scala 718:49] + wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[dec_tlu_ctl.scala 719:47] + wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 760:49] + wire _T_721 = _T_720 & int_timer1_int_possible; // @[dec_tlu_ctl.scala 760:74] + wire _T_723 = _T_721 & _T_631; // @[dec_tlu_ctl.scala 760:100] + wire _T_725 = ~_T_706; // @[dec_tlu_ctl.scala 760:129] + wire _T_726 = _T_723 & _T_725; // @[dec_tlu_ctl.scala 760:127] + wire _T_728 = _T_726 & _T_710; // @[dec_tlu_ctl.scala 760:177] + wire _T_730 = _T_728 & _T_698; // @[dec_tlu_ctl.scala 760:196] + wire _T_732 = _T_730 & _T_700; // @[dec_tlu_ctl.scala 760:214] + wire _T_734 = _T_732 & _T_702; // @[dec_tlu_ctl.scala 760:231] + wire take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 760:247] + wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 765:118] + wire _T_15 = _T_14 | interrupt_valid_r; // @[dec_tlu_ctl.scala 310:74] + wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 310:94] + wire _T_17 = _T_16 | reset_delayed; // @[dec_tlu_ctl.scala 310:117] + wire _T_18 = _T_17 | pause_expired_r; // @[dec_tlu_ctl.scala 310:133] + reg pause_expired_wb; // @[dec_tlu_ctl.scala 805:91] + wire _T_19 = _T_18 | pause_expired_wb; // @[dec_tlu_ctl.scala 310:151] + wire _T_496 = io_tlu_mem_ifu_ic_error_start & _T_107; // @[dec_tlu_ctl.scala 654:51] + wire _T_498 = _T_152 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 654:101] + wire _T_499 = _T_496 & _T_498; // @[dec_tlu_ctl.scala 654:72] + wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 654:131] + wire ic_perr_r = _T_499 & _T_500; // @[dec_tlu_ctl.scala 654:129] + wire _T_20 = _T_19 | ic_perr_r; // @[dec_tlu_ctl.scala 310:170] + wire _T_21 = _T_20 | ic_perr_r_d1; // @[dec_tlu_ctl.scala 310:182] + wire _T_503 = io_tlu_mem_ifu_iccm_rd_ecc_single_err & _T_107; // @[dec_tlu_ctl.scala 655:59] + wire _T_506 = _T_503 & _T_498; // @[dec_tlu_ctl.scala 655:80] + wire iccm_sbecc_r = _T_506 & _T_500; // @[dec_tlu_ctl.scala 655:137] + wire _T_22 = _T_21 | iccm_sbecc_r; // @[dec_tlu_ctl.scala 310:197] + wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 310:212] + wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 310:230] + reg lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 320:82] + reg lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 321:74] + reg _T_32; // @[dec_tlu_ctl.scala 323:74] + reg internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 324:74] + reg _T_33; // @[dec_tlu_ctl.scala 325:74] + reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 334:73] + reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 335:73] + wire _T_46 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 343:48] + wire _T_49 = ~_T_41; // @[dec_tlu_ctl.scala 343:96] + wire _T_50 = _T_46 & _T_49; // @[dec_tlu_ctl.scala 343:94] + wire _T_52 = nmi_lsu_load_type_f & _T_40; // @[dec_tlu_ctl.scala 343:159] + wire _T_54 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 344:49] + wire _T_58 = _T_54 & _T_49; // @[dec_tlu_ctl.scala 344:96] + wire _T_60 = nmi_lsu_store_type_f & _T_40; // @[dec_tlu_ctl.scala 344:162] + reg mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 352:74] + reg mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 353:74] + reg mpc_run_state_f; // @[dec_tlu_ctl.scala 355:106] + reg debug_brkpt_status_f; // @[dec_tlu_ctl.scala 356:90] + reg mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 357:90] + reg mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 358:90] + reg dbg_run_state_f; // @[dec_tlu_ctl.scala 360:106] + reg _T_65; // @[dec_tlu_ctl.scala 361:82] + wire _T_66 = ~mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 365:71] + wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_66; // @[dec_tlu_ctl.scala 365:69] + wire _T_67 = ~mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 366:70] + wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_67; // @[dec_tlu_ctl.scala 366:68] + wire _T_68 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[dec_tlu_ctl.scala 368:48] + wire _T_71 = _T_68 | _T_111; // @[dec_tlu_ctl.scala 368:80] + wire _T_72 = ~mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 368:125] + wire mpc_halt_state_ns = _T_71 & _T_72; // @[dec_tlu_ctl.scala 368:123] + wire _T_74 = ~mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 369:80] + wire _T_75 = mpc_debug_run_req_sync_pulse & _T_74; // @[dec_tlu_ctl.scala 369:78] + wire _T_76 = mpc_run_state_f | _T_75; // @[dec_tlu_ctl.scala 369:46] + wire _T_77 = ~dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 369:133] + wire _T_78 = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 369:131] + wire mpc_run_state_ns = _T_76 & _T_78; // @[dec_tlu_ctl.scala 369:103] + wire _T_80 = dbg_halt_req_final | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 371:70] + wire _T_81 = _T_80 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 371:96] + wire _T_82 = _T_81 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 371:121] + wire _T_83 = dbg_halt_state_f | _T_82; // @[dec_tlu_ctl.scala 371:48] + wire _T_84 = ~io_dbg_resume_req; // @[dec_tlu_ctl.scala 371:153] + wire dbg_halt_state_ns = _T_83 & _T_84; // @[dec_tlu_ctl.scala 371:151] + wire _T_86 = dbg_run_state_f | io_dbg_resume_req; // @[dec_tlu_ctl.scala 372:46] + wire dbg_run_state_ns = _T_86 & _T_78; // @[dec_tlu_ctl.scala 372:67] + wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 378:59] + wire _T_92 = debug_brkpt_valid | debug_brkpt_status_f; // @[dec_tlu_ctl.scala 379:53] + wire _T_94 = internal_dbg_halt_mode & _T_77; // @[dec_tlu_ctl.scala 379:103] + wire _T_96 = mpc_halt_state_f & debug_mode_status; // @[dec_tlu_ctl.scala 382:51] + wire _T_97 = _T_96 & mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 382:78] + wire _T_99 = ~dbg_halt_state_ns; // @[dec_tlu_ctl.scala 383:59] + wire _T_100 = mpc_debug_run_req_sync & _T_99; // @[dec_tlu_ctl.scala 383:57] + wire _T_101 = ~mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 383:80] + wire _T_102 = _T_100 & _T_101; // @[dec_tlu_ctl.scala 383:78] + wire _T_103 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 383:129] + wire _T_118 = mpc_run_state_ns & _T_99; // @[dec_tlu_ctl.scala 397:73] + wire _T_119 = ~mpc_halt_state_ns; // @[dec_tlu_ctl.scala 397:117] + wire _T_120 = dbg_run_state_ns & _T_119; // @[dec_tlu_ctl.scala 397:115] + wire _T_121 = _T_118 | _T_120; // @[dec_tlu_ctl.scala 397:95] + wire _T_122 = debug_halt_req_f | pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 402:43] + wire _T_124 = _T_122 & _T_749; // @[dec_tlu_ctl.scala 402:64] + wire _T_126 = _T_124 & _T_751; // @[dec_tlu_ctl.scala 402:87] + wire _T_128 = _T_126 & _T_228; // @[dec_tlu_ctl.scala 402:97] + wire _T_129 = ~dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 402:115] + wire _T_130 = _T_128 & _T_129; // @[dec_tlu_ctl.scala 402:113] + wire take_halt = _T_130 & _T_753; // @[dec_tlu_ctl.scala 402:143] + wire _T_170 = debug_resume_req_f & dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 427:49] + wire _T_172 = io_dec_tlu_i0_valid_r & _T_528; // @[dec_tlu_ctl.scala 429:59] + wire _T_174 = _T_172 & dcsr[2]; // @[dec_tlu_ctl.scala 429:84] + wire _T_329 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 524:61] + wire _T_332 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 524:121] + wire _T_335 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 524:181] + wire _T_338 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 524:241] wire [3:0] trigger_action = {_T_329,_T_332,_T_335,_T_338}; // @[Cat.scala 29:58] - wire [3:0] _T_343 = i0_trigger_chain_masked_r & trigger_action; // @[dec_tlu_ctl.scala 536:57] - wire i0_trigger_action_r = |_T_343; // @[dec_tlu_ctl.scala 536:75] - wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 538:45] - wire _T_180 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 442:57] - wire _T_182 = request_debug_mode_r_d1 & _T_402; // @[dec_tlu_ctl.scala 442:110] - reg request_debug_mode_done_f; // @[dec_tlu_ctl.scala 461:74] - wire _T_183 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[dec_tlu_ctl.scala 444:64] - reg _T_190; // @[dec_tlu_ctl.scala 452:98] - wire _T_201 = fence_i_r & internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 473:71] - wire _T_202 = take_halt | _T_201; // @[dec_tlu_ctl.scala 473:58] - wire _T_203 = _T_202 | io_dec_tlu_flush_pause_r; // @[dec_tlu_ctl.scala 473:97] - wire _T_204 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 473:144] - wire _T_205 = _T_203 | _T_204; // @[dec_tlu_ctl.scala 473:124] - wire take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 744:66] - wire _T_207 = ~interrupt_valid_r; // @[dec_tlu_ctl.scala 478:61] - wire _T_208 = dec_tlu_wr_pause_r_d1 & _T_207; // @[dec_tlu_ctl.scala 478:59] - wire _T_209 = ~take_ext_int_start; // @[dec_tlu_ctl.scala 478:82] - wire _T_231 = io_tlu_exu_dec_tlu_flush_lower_r & dcsr[2]; // @[dec_tlu_ctl.scala 482:82] - wire _T_232 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[dec_tlu_ctl.scala 482:125] - wire _T_233 = _T_231 & _T_232; // @[dec_tlu_ctl.scala 482:100] - wire _T_234 = ~io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec_tlu_ctl.scala 482:155] + wire [3:0] _T_343 = i0_trigger_chain_masked_r & trigger_action; // @[dec_tlu_ctl.scala 530:57] + wire i0_trigger_action_r = |_T_343; // @[dec_tlu_ctl.scala 530:75] + wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 532:45] + wire _T_180 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 436:57] + wire _T_182 = request_debug_mode_r_d1 & _T_402; // @[dec_tlu_ctl.scala 436:110] + reg request_debug_mode_done_f; // @[dec_tlu_ctl.scala 455:74] + wire _T_183 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[dec_tlu_ctl.scala 438:64] + reg _T_190; // @[dec_tlu_ctl.scala 446:98] + wire _T_201 = fence_i_r & internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 467:71] + wire _T_202 = take_halt | _T_201; // @[dec_tlu_ctl.scala 467:58] + wire _T_203 = _T_202 | io_dec_tlu_flush_pause_r; // @[dec_tlu_ctl.scala 467:97] + wire _T_204 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 467:144] + wire _T_205 = _T_203 | _T_204; // @[dec_tlu_ctl.scala 467:124] + wire take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 738:66] + wire _T_207 = ~interrupt_valid_r; // @[dec_tlu_ctl.scala 472:61] + wire _T_208 = dec_tlu_wr_pause_r_d1 & _T_207; // @[dec_tlu_ctl.scala 472:59] + wire _T_209 = ~take_ext_int_start; // @[dec_tlu_ctl.scala 472:82] + wire _T_231 = io_tlu_exu_dec_tlu_flush_lower_r & dcsr[2]; // @[dec_tlu_ctl.scala 476:82] + wire _T_232 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[dec_tlu_ctl.scala 476:125] + wire _T_233 = _T_231 & _T_232; // @[dec_tlu_ctl.scala 476:100] + wire _T_234 = ~io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec_tlu_ctl.scala 476:155] wire [3:0] _T_342 = i0_trigger_hit_raw_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire _T_345 = ~trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 540:55] - wire mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 540:53] - wire _T_350 = i_cpu_run_req_sync & _T_346; // @[dec_tlu_ctl.scala 566:58] - wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 566:83] - wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[dec_tlu_ctl.scala 566:105] - reg _T_353; // @[dec_tlu_ctl.scala 570:82] - reg _T_354; // @[dec_tlu_ctl.scala 571:82] - reg _T_355; // @[dec_tlu_ctl.scala 572:82] - wire _T_384 = io_o_cpu_halt_status & _T_375; // @[dec_tlu_ctl.scala 590:89] - wire _T_386 = _T_384 & _T_152; // @[dec_tlu_ctl.scala 590:109] - wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 591:41] - wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 591:88] - reg lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 603:72] - reg lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 610:73] - wire _T_408 = ~io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 611:40] - wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[dec_tlu_ctl.scala 611:38] - wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 612:38] - wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 613:38] - wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 623:38] - wire _T_425 = _T_424 | inst_acc_r; // @[dec_tlu_ctl.scala 623:53] - wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 623:79] - wire _T_427 = _T_425 | _T_426; // @[dec_tlu_ctl.scala 623:66] - wire _T_441 = ~io_tlu_exu_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 632:70] - wire _T_442 = iccm_repair_state_d1 & _T_441; // @[dec_tlu_ctl.scala 632:68] - wire _T_453 = io_tlu_exu_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 641:59] - wire _T_455 = io_tlu_exu_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 642:71] - wire _T_457 = io_tlu_exu_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 643:55] - wire _T_459 = _T_457 & _T_429; // @[dec_tlu_ctl.scala 643:79] - wire _T_460 = ~io_tlu_exu_exu_i0_br_mp_r; // @[dec_tlu_ctl.scala 643:106] - wire _T_461 = ~io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 643:135] - wire _T_462 = _T_460 | _T_461; // @[dec_tlu_ctl.scala 643:133] - wire _T_529 = ~take_nmi; // @[dec_tlu_ctl.scala 691:33] - wire _T_530 = take_ext_int & _T_529; // @[dec_tlu_ctl.scala 691:31] - wire _T_533 = take_timer_int & _T_529; // @[dec_tlu_ctl.scala 692:25] - wire _T_536 = take_soft_int & _T_529; // @[dec_tlu_ctl.scala 693:24] - wire _T_539 = take_int_timer0_int & _T_529; // @[dec_tlu_ctl.scala 694:30] - wire _T_542 = take_int_timer1_int & _T_529; // @[dec_tlu_ctl.scala 695:30] - wire _T_545 = take_ce_int & _T_529; // @[dec_tlu_ctl.scala 696:22] - wire _T_548 = illegal_r & _T_529; // @[dec_tlu_ctl.scala 697:20] - wire _T_551 = ecall_r & _T_529; // @[dec_tlu_ctl.scala 698:19] - wire _T_554 = inst_acc_r & _T_529; // @[dec_tlu_ctl.scala 699:22] - wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 700:20] - wire _T_558 = _T_556 & _T_529; // @[dec_tlu_ctl.scala 700:40] - wire _T_560 = ~lsu_exc_st_r; // @[dec_tlu_ctl.scala 701:25] - wire _T_561 = lsu_exc_ma_r & _T_560; // @[dec_tlu_ctl.scala 701:23] - wire _T_563 = _T_561 & _T_529; // @[dec_tlu_ctl.scala 701:39] - wire _T_566 = lsu_exc_acc_r & _T_560; // @[dec_tlu_ctl.scala 702:24] - wire _T_568 = _T_566 & _T_529; // @[dec_tlu_ctl.scala 702:40] - wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 703:23] - wire _T_572 = _T_570 & _T_529; // @[dec_tlu_ctl.scala 703:38] - wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 704:24] - wire _T_576 = _T_574 & _T_529; // @[dec_tlu_ctl.scala 704:39] + wire _T_345 = ~trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 534:55] + wire mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 534:53] + wire _T_350 = i_cpu_run_req_sync & _T_346; // @[dec_tlu_ctl.scala 560:58] + wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 560:83] + wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[dec_tlu_ctl.scala 560:105] + reg _T_353; // @[dec_tlu_ctl.scala 564:82] + reg _T_354; // @[dec_tlu_ctl.scala 565:82] + reg _T_355; // @[dec_tlu_ctl.scala 566:82] + wire _T_384 = io_o_cpu_halt_status & _T_375; // @[dec_tlu_ctl.scala 584:89] + wire _T_386 = _T_384 & _T_152; // @[dec_tlu_ctl.scala 584:109] + wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 585:41] + wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 585:88] + reg lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 597:72] + reg lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 604:73] + wire _T_408 = ~io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 605:40] + wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[dec_tlu_ctl.scala 605:38] + wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 606:38] + wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 607:38] + wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 617:38] + wire _T_425 = _T_424 | inst_acc_r; // @[dec_tlu_ctl.scala 617:53] + wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 617:79] + wire _T_427 = _T_425 | _T_426; // @[dec_tlu_ctl.scala 617:66] + wire _T_441 = ~io_tlu_exu_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 626:70] + wire _T_442 = iccm_repair_state_d1 & _T_441; // @[dec_tlu_ctl.scala 626:68] + wire _T_453 = io_tlu_exu_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 635:59] + wire _T_455 = io_tlu_exu_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 636:71] + wire _T_457 = io_tlu_exu_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 637:55] + wire _T_459 = _T_457 & _T_429; // @[dec_tlu_ctl.scala 637:79] + wire _T_460 = ~io_tlu_exu_exu_i0_br_mp_r; // @[dec_tlu_ctl.scala 637:106] + wire _T_461 = ~io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 637:135] + wire _T_462 = _T_460 | _T_461; // @[dec_tlu_ctl.scala 637:133] + wire _T_529 = ~take_nmi; // @[dec_tlu_ctl.scala 685:33] + wire _T_530 = take_ext_int & _T_529; // @[dec_tlu_ctl.scala 685:31] + wire _T_533 = take_timer_int & _T_529; // @[dec_tlu_ctl.scala 686:25] + wire _T_536 = take_soft_int & _T_529; // @[dec_tlu_ctl.scala 687:24] + wire _T_539 = take_int_timer0_int & _T_529; // @[dec_tlu_ctl.scala 688:30] + wire _T_542 = take_int_timer1_int & _T_529; // @[dec_tlu_ctl.scala 689:30] + wire _T_545 = take_ce_int & _T_529; // @[dec_tlu_ctl.scala 690:22] + wire _T_548 = illegal_r & _T_529; // @[dec_tlu_ctl.scala 691:20] + wire _T_551 = ecall_r & _T_529; // @[dec_tlu_ctl.scala 692:19] + wire _T_554 = inst_acc_r & _T_529; // @[dec_tlu_ctl.scala 693:22] + wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 694:20] + wire _T_558 = _T_556 & _T_529; // @[dec_tlu_ctl.scala 694:40] + wire _T_560 = ~lsu_exc_st_r; // @[dec_tlu_ctl.scala 695:25] + wire _T_561 = lsu_exc_ma_r & _T_560; // @[dec_tlu_ctl.scala 695:23] + wire _T_563 = _T_561 & _T_529; // @[dec_tlu_ctl.scala 695:39] + wire _T_566 = lsu_exc_acc_r & _T_560; // @[dec_tlu_ctl.scala 696:24] + wire _T_568 = _T_566 & _T_529; // @[dec_tlu_ctl.scala 696:40] + wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 697:23] + wire _T_572 = _T_570 & _T_529; // @[dec_tlu_ctl.scala 697:38] + wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 698:24] + wire _T_576 = _T_574 & _T_529; // @[dec_tlu_ctl.scala 698:39] wire [4:0] _T_578 = _T_530 ? 5'hb : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_579 = _T_533 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_580 = _T_536 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] @@ -55461,66 +55461,66 @@ module dec_tlu_ctl( wire [4:0] _T_602 = _T_601 | _T_589; // @[Mux.scala 27:72] wire [4:0] _T_603 = _T_602 | _T_590; // @[Mux.scala 27:72] wire [4:0] exc_cause_r = _T_603 | _T_591; // @[Mux.scala 27:72] - wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[dec_tlu_ctl.scala 729:52] - wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 729:74] - wire int_timer_stalled = _T_642 | mret_r; // @[dec_tlu_ctl.scala 729:98] - wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[dec_tlu_ctl.scala 731:72] - wire _T_644 = int_timer0_int_ready & _T_643; // @[dec_tlu_ctl.scala 731:49] - wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 731:121] - wire _T_647 = _T_645 & _T_207; // @[dec_tlu_ctl.scala 731:145] - wire _T_649 = _T_647 & _T_209; // @[dec_tlu_ctl.scala 731:166] - wire _T_651 = _T_649 & _T_152; // @[dec_tlu_ctl.scala 731:188] - wire _T_654 = int_timer1_int_ready & _T_643; // @[dec_tlu_ctl.scala 732:49] - wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 732:121] - wire _T_657 = _T_655 & _T_207; // @[dec_tlu_ctl.scala 732:145] - wire _T_659 = _T_657 & _T_209; // @[dec_tlu_ctl.scala 732:166] - wire _T_661 = _T_659 & _T_152; // @[dec_tlu_ctl.scala 732:188] - reg take_ext_int_start_d2; // @[dec_tlu_ctl.scala 741:74] - wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[dec_tlu_ctl.scala 746:46] - wire _T_682 = _T_681 | take_ext_int_start_d2; // @[dec_tlu_ctl.scala 746:70] - wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 748:49] - wire [30:0] mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 1003:31] + wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[dec_tlu_ctl.scala 723:52] + wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 723:74] + wire int_timer_stalled = _T_642 | mret_r; // @[dec_tlu_ctl.scala 723:98] + wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[dec_tlu_ctl.scala 725:72] + wire _T_644 = int_timer0_int_ready & _T_643; // @[dec_tlu_ctl.scala 725:49] + wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 725:121] + wire _T_647 = _T_645 & _T_207; // @[dec_tlu_ctl.scala 725:145] + wire _T_649 = _T_647 & _T_209; // @[dec_tlu_ctl.scala 725:166] + wire _T_651 = _T_649 & _T_152; // @[dec_tlu_ctl.scala 725:188] + wire _T_654 = int_timer1_int_ready & _T_643; // @[dec_tlu_ctl.scala 726:49] + wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 726:121] + wire _T_657 = _T_655 & _T_207; // @[dec_tlu_ctl.scala 726:145] + wire _T_659 = _T_657 & _T_209; // @[dec_tlu_ctl.scala 726:166] + wire _T_661 = _T_659 & _T_152; // @[dec_tlu_ctl.scala 726:188] + reg take_ext_int_start_d2; // @[dec_tlu_ctl.scala 735:74] + wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[dec_tlu_ctl.scala 740:46] + wire _T_682 = _T_681 | take_ext_int_start_d2; // @[dec_tlu_ctl.scala 740:70] + wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 742:49] + wire [30:0] mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 997:31] wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] wire [30:0] _T_771 = {25'h0,exc_cause_r,1'h0}; // @[Cat.scala 29:58] - wire [30:0] vectored_path = _T_769 + _T_771; // @[dec_tlu_ctl.scala 776:51] - wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[dec_tlu_ctl.scala 777:61] - wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[dec_tlu_ctl.scala 777:28] - wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[dec_tlu_ctl.scala 778:36] - wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 778:48] - wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[dec_tlu_ctl.scala 778:94] - wire _T_783 = _T_780 | _T_782; // @[dec_tlu_ctl.scala 778:74] - wire _T_785 = rfpc_i0_r & _T_743; // @[dec_tlu_ctl.scala 778:129] - wire sel_npc_r = _T_783 | _T_785; // @[dec_tlu_ctl.scala 778:116] - wire _T_798 = interrupt_valid_r | mret_r; // @[dec_tlu_ctl.scala 782:43] - wire _T_799 = _T_798 | synchronous_flush_r; // @[dec_tlu_ctl.scala 782:52] - wire _T_800 = _T_799 | take_halt; // @[dec_tlu_ctl.scala 782:74] - wire _T_801 = _T_800 | take_reset; // @[dec_tlu_ctl.scala 782:86] - wire _T_807 = _T_529 & sel_npc_r; // @[dec_tlu_ctl.scala 786:73] - wire _T_810 = _T_529 & rfpc_i0_r; // @[dec_tlu_ctl.scala 787:73] - wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 787:91] - wire _T_813 = ~sel_npc_r; // @[dec_tlu_ctl.scala 787:132] - wire _T_814 = _T_812 & _T_813; // @[dec_tlu_ctl.scala 787:121] - wire _T_816 = ~take_ext_int; // @[dec_tlu_ctl.scala 788:96] - wire _T_817 = interrupt_valid_r & _T_816; // @[dec_tlu_ctl.scala 788:82] - wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 789:80] - wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 789:98] - wire _T_823 = _T_821 & _T_207; // @[dec_tlu_ctl.scala 789:143] - wire _T_825 = _T_823 & _T_816; // @[dec_tlu_ctl.scala 789:164] - wire _T_830 = _T_529 & mret_r; // @[dec_tlu_ctl.scala 790:68] - wire _T_833 = _T_529 & debug_resume_req_f; // @[dec_tlu_ctl.scala 791:68] - wire _T_836 = _T_529 & sel_npc_resume; // @[dec_tlu_ctl.scala 792:68] + wire [30:0] vectored_path = _T_769 + _T_771; // @[dec_tlu_ctl.scala 770:51] + wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[dec_tlu_ctl.scala 771:61] + wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[dec_tlu_ctl.scala 771:28] + wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[dec_tlu_ctl.scala 772:36] + wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 772:48] + wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[dec_tlu_ctl.scala 772:94] + wire _T_783 = _T_780 | _T_782; // @[dec_tlu_ctl.scala 772:74] + wire _T_785 = rfpc_i0_r & _T_743; // @[dec_tlu_ctl.scala 772:129] + wire sel_npc_r = _T_783 | _T_785; // @[dec_tlu_ctl.scala 772:116] + wire _T_798 = interrupt_valid_r | mret_r; // @[dec_tlu_ctl.scala 776:43] + wire _T_799 = _T_798 | synchronous_flush_r; // @[dec_tlu_ctl.scala 776:52] + wire _T_800 = _T_799 | take_halt; // @[dec_tlu_ctl.scala 776:74] + wire _T_801 = _T_800 | take_reset; // @[dec_tlu_ctl.scala 776:86] + wire _T_807 = _T_529 & sel_npc_r; // @[dec_tlu_ctl.scala 780:73] + wire _T_810 = _T_529 & rfpc_i0_r; // @[dec_tlu_ctl.scala 781:73] + wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 781:91] + wire _T_813 = ~sel_npc_r; // @[dec_tlu_ctl.scala 781:132] + wire _T_814 = _T_812 & _T_813; // @[dec_tlu_ctl.scala 781:121] + wire _T_816 = ~take_ext_int; // @[dec_tlu_ctl.scala 782:96] + wire _T_817 = interrupt_valid_r & _T_816; // @[dec_tlu_ctl.scala 782:82] + wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 783:80] + wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 783:98] + wire _T_823 = _T_821 & _T_207; // @[dec_tlu_ctl.scala 783:143] + wire _T_825 = _T_823 & _T_816; // @[dec_tlu_ctl.scala 783:164] + wire _T_830 = _T_529 & mret_r; // @[dec_tlu_ctl.scala 784:68] + wire _T_833 = _T_529 & debug_resume_req_f; // @[dec_tlu_ctl.scala 785:68] + wire _T_836 = _T_529 & sel_npc_resume; // @[dec_tlu_ctl.scala 786:68] wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r = csr_io_npc_r; // @[dec_tlu_ctl.scala 991:31] + wire [30:0] npc_r = csr_io_npc_r; // @[dec_tlu_ctl.scala 985:31] wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72] - wire [30:0] mepc = csr_io_mepc; // @[dec_tlu_ctl.scala 994:31] + wire [30:0] mepc = csr_io_mepc; // @[dec_tlu_ctl.scala 988:31] wire [30:0] _T_843 = _T_830 ? mepc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] dpc = csr_io_dpc; // @[dec_tlu_ctl.scala 997:31] + wire [30:0] dpc = csr_io_dpc; // @[dec_tlu_ctl.scala 991:31] wire [30:0] _T_844 = _T_833 ? dpc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 992:31] + wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 986:31] wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72] wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72] @@ -55529,54 +55529,54 @@ module dec_tlu_ctl( wire [30:0] _T_850 = _T_849 | _T_843; // @[Mux.scala 27:72] wire [30:0] _T_851 = _T_850 | _T_844; // @[Mux.scala 27:72] wire [30:0] _T_852 = _T_851 | _T_845; // @[Mux.scala 27:72] - reg [30:0] tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 795:64] - wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[dec_tlu_ctl.scala 802:45] - wire _T_855 = _T_854 | interrupt_valid_r; // @[dec_tlu_ctl.scala 802:68] - reg i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 805:75] - reg [4:0] exc_cause_wb; // @[dec_tlu_ctl.scala 807:91] - wire _T_860 = ~illegal_r; // @[dec_tlu_ctl.scala 808:121] - reg i0_valid_wb; // @[dec_tlu_ctl.scala 808:99] - reg trigger_hit_r_d1; // @[dec_tlu_ctl.scala 809:83] - wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1010:42] - wire _T_865 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1010:67] - wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1015:55] - wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1015:73] - wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1015:92] - wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1015:115] - wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1015:136] - wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1015:158] - wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1015:179] - wire _T_881 = ~_T_880; // @[dec_tlu_ctl.scala 1015:36] - wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1015:201] - wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_883 = csr_pkt_legal & _T_882; // @[dec_tlu_ctl.scala 1015:33] - wire _T_884 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1015:223] - wire valid_csr = _T_883 & _T_884; // @[dec_tlu_ctl.scala 1015:221] - wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1017:46] - wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1017:107] - wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1017:129] - wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1017:150] - wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1017:172] - wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1008:16] - wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1017:193] - wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[dec_tlu_ctl.scala 1017:82] - wire _T_894 = ~_T_893; // @[dec_tlu_ctl.scala 1017:59] - dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 275:32] + reg [30:0] tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 789:64] + wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[dec_tlu_ctl.scala 796:45] + wire _T_855 = _T_854 | interrupt_valid_r; // @[dec_tlu_ctl.scala 796:68] + reg i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 799:75] + reg [4:0] exc_cause_wb; // @[dec_tlu_ctl.scala 801:91] + wire _T_860 = ~illegal_r; // @[dec_tlu_ctl.scala 802:121] + reg i0_valid_wb; // @[dec_tlu_ctl.scala 802:99] + reg trigger_hit_r_d1; // @[dec_tlu_ctl.scala 803:83] + wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1004:42] + wire _T_865 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1004:67] + wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1009:55] + wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1009:73] + wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1009:92] + wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1009:115] + wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1009:136] + wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1009:158] + wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1009:179] + wire _T_881 = ~_T_880; // @[dec_tlu_ctl.scala 1009:36] + wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1009:201] + wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_883 = csr_pkt_legal & _T_882; // @[dec_tlu_ctl.scala 1009:33] + wire _T_884 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1009:223] + wire valid_csr = _T_883 & _T_884; // @[dec_tlu_ctl.scala 1009:221] + wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1011:46] + wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1011:107] + wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1011:129] + wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1011:150] + wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1011:172] + wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 265:41 dec_tlu_ctl.scala 1002:16] + wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1011:193] + wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[dec_tlu_ctl.scala 1011:82] + wire _T_894 = ~_T_893; // @[dec_tlu_ctl.scala 1011:59] + dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 269:32] .clock(int_timers_clock), .reset(int_timers_reset), .io_free_clk(int_timers_io_free_clk), @@ -55622,7 +55622,7 @@ module dec_tlu_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - csr_tlu csr ( // @[dec_tlu_ctl.scala 813:15] + csr_tlu csr ( // @[dec_tlu_ctl.scala 807:15] .clock(csr_clock), .reset(csr_reset), .io_free_clk(csr_io_free_clk), @@ -55894,7 +55894,7 @@ module dec_tlu_ctl( .io_mtdata1_t_2(csr_io_mtdata1_t_2), .io_mtdata1_t_3(csr_io_mtdata1_t_3) ); - dec_decode_csr_read csr_read ( // @[dec_tlu_ctl.scala 1006:22] + dec_decode_csr_read csr_read ( // @[dec_tlu_ctl.scala 1000:22] .io_dec_csr_rdaddr_d(csr_read_io_dec_csr_rdaddr_d), .io_csr_pkt_csr_misa(csr_read_io_csr_pkt_csr_misa), .io_csr_pkt_csr_mvendorid(csr_read_io_csr_pkt_csr_mvendorid), @@ -55964,118 +55964,118 @@ module dec_tlu_ctl( .io_csr_pkt_postsync(csr_read_io_csr_pkt_postsync), .io_csr_pkt_legal(csr_read_io_csr_pkt_legal) ); - assign io_tlu_exu_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 872:44] - assign io_tlu_exu_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 798:49] - assign io_tlu_exu_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[dec_tlu_ctl.scala 799:49] - assign io_tlu_dma_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 902:48] - assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 486:29] - assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[dec_tlu_ctl.scala 487:29] - assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 468:41] - assign io_dec_tlu_debug_mode = debug_mode_status; // @[dec_tlu_ctl.scala 469:41] - assign io_dec_tlu_resume_ack = _T_190; // @[dec_tlu_ctl.scala 452:65] - assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[dec_tlu_ctl.scala 467:41] - assign io_dec_tlu_mpc_halted_only = _T_65; // @[dec_tlu_ctl.scala 367:49] - assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 475:33] - assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 878:40] - assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 878:40] - assign io_o_cpu_halt_status = _T_353; // @[dec_tlu_ctl.scala 570:49] - assign io_o_cpu_halt_ack = _T_354; // @[dec_tlu_ctl.scala 571:49] - assign io_o_cpu_run_ack = _T_355; // @[dec_tlu_ctl.scala 572:49] - assign io_o_debug_mode_status = debug_mode_status; // @[dec_tlu_ctl.scala 593:27] - assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 392:31] - assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 393:31] - assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 394:31] - assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 893:40] - assign io_dec_csr_legal_d = _T_887 & _T_894; // @[dec_tlu_ctl.scala 1017:20] - assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[dec_tlu_ctl.scala 329:41] - assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 333:37] - assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 895:40] - assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[dec_tlu_ctl.scala 478:34] - assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[dec_tlu_ctl.scala 1010:23] - assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1011:23] - assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 881:40] - assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 882:40] - assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 883:40] - assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 884:40] - assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 875:44] - assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 876:44] - assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 874:44] - assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 880:40] - assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 879:40] - assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 894:40] - assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 885:40] - assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 886:40] - assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 888:40] - assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 889:40] - assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 890:40] - assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 891:40] - assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 892:40] - assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 797:41] - assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[dec_tlu_ctl.scala 649:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 646:65] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[dec_tlu_ctl.scala 647:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[dec_tlu_ctl.scala 648:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 650:65] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 651:65] - assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_233 & _T_234; // @[dec_tlu_ctl.scala 482:45] - assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 898:47] - assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_205 | take_ext_int_start; // @[dec_tlu_ctl.scala 473:45] - assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 896:48] - assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_433; // @[dec_tlu_ctl.scala 483:41] - assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 624:37] - assign io_tlu_mem_dec_tlu_force_halt = _T_33; // @[dec_tlu_ctl.scala 331:41] - assign io_tlu_mem_dec_tlu_fence_i_wb = _T_492 & _T_470; // @[dec_tlu_ctl.scala 669:39] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 877:44] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 877:44] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 877:44] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 877:44] - assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 900:48] - assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 901:52] - assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 899:52] - assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 871:44] - assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 873:44] + assign io_tlu_exu_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 866:44] + assign io_tlu_exu_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 792:49] + assign io_tlu_exu_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[dec_tlu_ctl.scala 793:49] + assign io_tlu_dma_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 896:48] + assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 480:29] + assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[dec_tlu_ctl.scala 481:29] + assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 462:41] + assign io_dec_tlu_debug_mode = debug_mode_status; // @[dec_tlu_ctl.scala 463:41] + assign io_dec_tlu_resume_ack = _T_190; // @[dec_tlu_ctl.scala 446:65] + assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[dec_tlu_ctl.scala 461:41] + assign io_dec_tlu_mpc_halted_only = _T_65; // @[dec_tlu_ctl.scala 361:49] + assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 469:33] + assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 872:40] + assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 872:40] + assign io_o_cpu_halt_status = _T_353; // @[dec_tlu_ctl.scala 564:49] + assign io_o_cpu_halt_ack = _T_354; // @[dec_tlu_ctl.scala 565:49] + assign io_o_cpu_run_ack = _T_355; // @[dec_tlu_ctl.scala 566:49] + assign io_o_debug_mode_status = debug_mode_status; // @[dec_tlu_ctl.scala 587:27] + assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 386:31] + assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 387:31] + assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 388:31] + assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 887:40] + assign io_dec_csr_legal_d = _T_887 & _T_894; // @[dec_tlu_ctl.scala 1011:20] + assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[dec_tlu_ctl.scala 323:41] + assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 327:37] + assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 889:40] + assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[dec_tlu_ctl.scala 472:34] + assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[dec_tlu_ctl.scala 1004:23] + assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1005:23] + assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 875:40] + assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 876:40] + assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 877:40] + assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 878:40] + assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 869:44] + assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 870:44] + assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 868:44] + assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 874:40] + assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 873:40] + assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 888:40] + assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 879:40] + assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 880:40] + assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 882:40] + assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 883:40] + assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 884:40] + assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 885:40] + assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 886:40] + assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 791:41] + assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[dec_tlu_ctl.scala 643:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 640:65] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[dec_tlu_ctl.scala 641:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[dec_tlu_ctl.scala 642:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 644:65] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 645:65] + assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_233 & _T_234; // @[dec_tlu_ctl.scala 476:45] + assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 892:47] + assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_205 | take_ext_int_start; // @[dec_tlu_ctl.scala 467:45] + assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 890:48] + assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_433; // @[dec_tlu_ctl.scala 477:41] + assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 618:37] + assign io_tlu_mem_dec_tlu_force_halt = _T_33; // @[dec_tlu_ctl.scala 325:41] + assign io_tlu_mem_dec_tlu_fence_i_wb = _T_492 & _T_470; // @[dec_tlu_ctl.scala 663:39] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 871:44] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 871:44] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 871:44] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 871:44] + assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 894:48] + assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 895:52] + assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 893:52] + assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 865:44] + assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 867:44] assign int_timers_clock = clock; assign int_timers_reset = reset; - assign int_timers_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 276:73] - assign int_timers_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 277:73] - assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 278:49] - assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 280:49] - assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 281:49] - assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 282:73] - assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 283:73] - assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 284:73] - assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 285:73] - assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 286:73] - assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 287:73] - assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 288:57] - assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 289:49] - assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[dec_tlu_ctl.scala 290:48] + assign int_timers_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 270:73] + assign int_timers_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 271:73] + assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 272:49] + assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 274:49] + assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 275:49] + assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 276:73] + assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 277:73] + assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 278:73] + assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 279:73] + assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 280:73] + assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 281:73] + assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 282:57] + assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 283:49] + assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[dec_tlu_ctl.scala 284:48] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = dec_csr_wen_r_mod | io_dec_tlu_dec_clk_override; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] @@ -56090,197 +56090,197 @@ module dec_tlu_ctl( assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign csr_clock = clock; assign csr_reset = reset; - assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 814:44] - assign csr_io_active_clk = io_active_clk; // @[dec_tlu_ctl.scala 815:44] - assign csr_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 816:44] - assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 817:44] - assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 818:44] - assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 819:44] - assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 820:44] - assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 821:44] - assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 822:44] - assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 823:44] - assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 824:44] - assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 825:44] - assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 826:44] - assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 827:44] - assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 828:44] - assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 829:44] - assign csr_io_ifu_pmu_fetch_stall = io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 830:44] - assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 831:44] - assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 831:44] - assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 831:44] - assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 831:44] - assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 831:44] - assign csr_io_exu_pmu_i0_br_ataken = io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 832:44] - assign csr_io_exu_pmu_i0_br_misp = io_tlu_exu_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 833:44] - assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 834:44] - assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 835:44] - assign csr_io_exu_pmu_i0_pc4 = io_tlu_exu_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 836:44] - assign csr_io_ifu_pmu_ic_miss = io_tlu_mem_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 837:44] - assign csr_io_ifu_pmu_ic_hit = io_tlu_mem_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 838:44] - assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 839:44] - assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 840:44] - assign csr_io_dma_pmu_dccm_write = io_tlu_dma_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 841:44] - assign csr_io_dma_pmu_dccm_read = io_tlu_dma_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 842:44] - assign csr_io_dma_pmu_any_write = io_tlu_dma_dma_pmu_any_write; // @[dec_tlu_ctl.scala 843:44] - assign csr_io_dma_pmu_any_read = io_tlu_dma_dma_pmu_any_read; // @[dec_tlu_ctl.scala 844:44] - assign csr_io_lsu_pmu_bus_busy = io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 845:44] - assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 846:44] - assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 847:44] - assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 849:44] - assign csr_io_ifu_pmu_bus_busy = io_tlu_mem_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 850:44] - assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 851:44] - assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 852:44] - assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 853:44] - assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 854:44] - assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 855:44] - assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 856:44] - assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 857:44] - assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 858:44] - assign csr_io_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 859:44] - assign csr_io_lsu_imprecise_error_load_any = io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 860:44] - assign csr_io_lsu_imprecise_error_store_any = io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 861:44] - assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[dec_tlu_ctl.scala 862:44 dec_tlu_ctl.scala 903:44] - assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 863:44 dec_tlu_ctl.scala 904:44] - assign csr_io_mexintpend = io_dec_pic_mexintpend; // @[dec_tlu_ctl.scala 864:44 dec_tlu_ctl.scala 905:44] - assign csr_io_exu_npc_r = io_tlu_exu_exu_npc_r; // @[dec_tlu_ctl.scala 865:44 dec_tlu_ctl.scala 906:44] - assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 866:44 dec_tlu_ctl.scala 907:44] - assign csr_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 867:44 dec_tlu_ctl.scala 908:44] - assign csr_io_core_id = io_core_id; // @[dec_tlu_ctl.scala 868:44 dec_tlu_ctl.scala 909:44] - assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 869:44 dec_tlu_ctl.scala 910:44] - assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 870:44 dec_tlu_ctl.scala 911:44] - assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 914:39] - assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 915:39] - assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 916:39] - assign csr_io_mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 917:39] - assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 918:39] - assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 919:39] - assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 920:39] - assign csr_io_timer_int_sync = syncro_ff[5]; // @[dec_tlu_ctl.scala 921:39] - assign csr_io_soft_int_sync = syncro_ff[4]; // @[dec_tlu_ctl.scala 922:39] - assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[dec_tlu_ctl.scala 923:39] - assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 924:39] - assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 925:39] - assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 926:39] - assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 927:39] - assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 928:39] - assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 929:39] - assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 930:39] - assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 931:39] - assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 932:39] - assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 933:39] - assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 934:39] - assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[dec_tlu_ctl.scala 935:39] - assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 936:39] - assign csr_io_inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 937:39] - assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[dec_tlu_ctl.scala 938:39] - assign csr_io_take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 939:39] - assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[dec_tlu_ctl.scala 940:39] - assign csr_io_exc_cause_r = _T_603 | _T_591; // @[dec_tlu_ctl.scala 941:39] - assign csr_io_i0_valid_wb = i0_valid_wb; // @[dec_tlu_ctl.scala 942:39] - assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 943:39] - assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 944:39] - assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 945:39] - assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 946:39] - assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 947:39] - assign csr_io_exc_cause_wb = exc_cause_wb; // @[dec_tlu_ctl.scala 948:39] - assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[dec_tlu_ctl.scala 949:39] - assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[dec_tlu_ctl.scala 950:39] - assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 951:39] - assign csr_io_ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 952:39] - assign csr_io_ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 953:39] - assign csr_io_illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 954:39] - assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[dec_tlu_ctl.scala 955:39] - assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[dec_tlu_ctl.scala 956:39] - assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 957:39] - assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[dec_tlu_ctl.scala 958:39] - assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[dec_tlu_ctl.scala 959:39] - assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 960:39] - assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 961:39] - assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 962:39] - assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[dec_tlu_ctl.scala 963:39] - assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 964:39] - assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 965:39] - assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[dec_tlu_ctl.scala 966:65] - assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 967:49] - assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 968:49] - assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[dec_tlu_ctl.scala 969:49] - assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 970:49] - assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 971:39] - assign csr_io_debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 972:73] - assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 973:39] - assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 974:39] - assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 975:39] - assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 976:39] - assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[dec_tlu_ctl.scala 977:39] - assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[dec_tlu_ctl.scala 978:39] - assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 979:39] - assign csr_io_take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 980:39] - assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 981:39] - assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 982:39] - assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 983:39] - assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 984:39] - assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[dec_tlu_ctl.scala 985:39] - assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[dec_tlu_ctl.scala 986:39] - assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 987:39] - assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 988:39] - assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 989:39] - assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1007:37] + assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 808:44] + assign csr_io_active_clk = io_active_clk; // @[dec_tlu_ctl.scala 809:44] + assign csr_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 810:44] + assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 811:44] + assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 812:44] + assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 813:44] + assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 814:44] + assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 815:44] + assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 816:44] + assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 817:44] + assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 818:44] + assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 819:44] + assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 820:44] + assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 821:44] + assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 822:44] + assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 823:44] + assign csr_io_ifu_pmu_fetch_stall = io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 824:44] + assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 825:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 825:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 825:44] + assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 825:44] + assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 825:44] + assign csr_io_exu_pmu_i0_br_ataken = io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 826:44] + assign csr_io_exu_pmu_i0_br_misp = io_tlu_exu_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 827:44] + assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 828:44] + assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 829:44] + assign csr_io_exu_pmu_i0_pc4 = io_tlu_exu_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 830:44] + assign csr_io_ifu_pmu_ic_miss = io_tlu_mem_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 831:44] + assign csr_io_ifu_pmu_ic_hit = io_tlu_mem_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 832:44] + assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 833:44] + assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 834:44] + assign csr_io_dma_pmu_dccm_write = io_tlu_dma_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 835:44] + assign csr_io_dma_pmu_dccm_read = io_tlu_dma_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 836:44] + assign csr_io_dma_pmu_any_write = io_tlu_dma_dma_pmu_any_write; // @[dec_tlu_ctl.scala 837:44] + assign csr_io_dma_pmu_any_read = io_tlu_dma_dma_pmu_any_read; // @[dec_tlu_ctl.scala 838:44] + assign csr_io_lsu_pmu_bus_busy = io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 839:44] + assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 840:44] + assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 841:44] + assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 843:44] + assign csr_io_ifu_pmu_bus_busy = io_tlu_mem_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 844:44] + assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 845:44] + assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 846:44] + assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 847:44] + assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 848:44] + assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 849:44] + assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 850:44] + assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 851:44] + assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 852:44] + assign csr_io_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 853:44] + assign csr_io_lsu_imprecise_error_load_any = io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 854:44] + assign csr_io_lsu_imprecise_error_store_any = io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 855:44] + assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[dec_tlu_ctl.scala 856:44 dec_tlu_ctl.scala 897:44] + assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 857:44 dec_tlu_ctl.scala 898:44] + assign csr_io_mexintpend = io_dec_pic_mexintpend; // @[dec_tlu_ctl.scala 858:44 dec_tlu_ctl.scala 899:44] + assign csr_io_exu_npc_r = io_tlu_exu_exu_npc_r; // @[dec_tlu_ctl.scala 859:44 dec_tlu_ctl.scala 900:44] + assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 860:44 dec_tlu_ctl.scala 901:44] + assign csr_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 861:44 dec_tlu_ctl.scala 902:44] + assign csr_io_core_id = io_core_id; // @[dec_tlu_ctl.scala 862:44 dec_tlu_ctl.scala 903:44] + assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 863:44 dec_tlu_ctl.scala 904:44] + assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 864:44 dec_tlu_ctl.scala 905:44] + assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 908:39] + assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 909:39] + assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 910:39] + assign csr_io_mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 911:39] + assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 912:39] + assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 913:39] + assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 914:39] + assign csr_io_timer_int_sync = syncro_ff[5]; // @[dec_tlu_ctl.scala 915:39] + assign csr_io_soft_int_sync = syncro_ff[4]; // @[dec_tlu_ctl.scala 916:39] + assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[dec_tlu_ctl.scala 917:39] + assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 918:39] + assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 919:39] + assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 920:39] + assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 921:39] + assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 922:39] + assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 923:39] + assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 924:39] + assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 925:39] + assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 926:39] + assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 927:39] + assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 928:39] + assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[dec_tlu_ctl.scala 929:39] + assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 930:39] + assign csr_io_inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 931:39] + assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[dec_tlu_ctl.scala 932:39] + assign csr_io_take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 933:39] + assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[dec_tlu_ctl.scala 934:39] + assign csr_io_exc_cause_r = _T_603 | _T_591; // @[dec_tlu_ctl.scala 935:39] + assign csr_io_i0_valid_wb = i0_valid_wb; // @[dec_tlu_ctl.scala 936:39] + assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 937:39] + assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 938:39] + assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 939:39] + assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 940:39] + assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 941:39] + assign csr_io_exc_cause_wb = exc_cause_wb; // @[dec_tlu_ctl.scala 942:39] + assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[dec_tlu_ctl.scala 943:39] + assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[dec_tlu_ctl.scala 944:39] + assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 945:39] + assign csr_io_ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 946:39] + assign csr_io_ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 947:39] + assign csr_io_illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 948:39] + assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[dec_tlu_ctl.scala 949:39] + assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[dec_tlu_ctl.scala 950:39] + assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 951:39] + assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[dec_tlu_ctl.scala 952:39] + assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[dec_tlu_ctl.scala 953:39] + assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 954:39] + assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 955:39] + assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 956:39] + assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[dec_tlu_ctl.scala 957:39] + assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 958:39] + assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 959:39] + assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[dec_tlu_ctl.scala 960:65] + assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 961:49] + assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 962:49] + assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[dec_tlu_ctl.scala 963:49] + assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 964:49] + assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 965:39] + assign csr_io_debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 966:73] + assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 967:39] + assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 968:39] + assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 969:39] + assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 970:39] + assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[dec_tlu_ctl.scala 971:39] + assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[dec_tlu_ctl.scala 972:39] + assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 973:39] + assign csr_io_take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 974:39] + assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 975:39] + assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 976:39] + assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 977:39] + assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 978:39] + assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[dec_tlu_ctl.scala 979:39] + assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[dec_tlu_ctl.scala 980:39] + assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 981:39] + assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 982:39] + assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 983:39] + assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1001:37] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -85258,7 +85258,7 @@ module quasar( assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 211:29] assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 212:31] assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 213:33] - assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 214:34] + assign pic_ctrl_inst_io_extintsrc_req = {io_extintsrc_req,1'h0}; // @[quasar.scala 214:34] assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 215:28] assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 215:28] assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 215:28] diff --git a/design/src/main/scala/dec/dec_tlu_ctl.scala b/design/src/main/scala/dec/dec_tlu_ctl.scala index 445472f6..47225626 100644 --- a/design/src/main/scala/dec/dec_tlu_ctl.scala +++ b/design/src/main/scala/dec/dec_tlu_ctl.scala @@ -94,10 +94,6 @@ class dec_tlu_ctl_IO extends Bundle with lib { val dbg_resume_req = Input(UInt(1.W)) // DM requests a resume val dec_div_active = Input(UInt(1.W)) // oop div is active val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t))// trigger info for trigger blocks -// val pic_claimid = Input(UInt(8.W)) // pic claimid for csr -// val pic_pl = Input(UInt(4.W)) // pic priv level for csr -// val mhwakeup = Input(UInt(1.W)) // high priority external int, wakeup if halted -// val mexintpend= Input(UInt(1.W)) // external interrupt pending val timer_int= Input(UInt(1.W)) // timer interrupt pending val soft_int= Input(UInt(1.W)) // software interrupt pending val o_cpu_halt_status = Output(UInt(1.W)) // PMU interface, halted @@ -112,9 +108,7 @@ class dec_tlu_ctl_IO extends Bundle with lib { val mpc_debug_halt_ack = Output(UInt(1.W)) // Halt ack val mpc_debug_run_ack = Output(UInt(1.W)) // Run ack val debug_brkpt_status = Output(UInt(1.W)) // debug breakpoint -// val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC -// val dec_tlu_meipt = Output(UInt(4.W)) // to PIC - val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb + val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb val dec_csr_legal_d = Output(UInt(1.W)) // csr indicates legal operation val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state val dec_tlu_i0_kill_writeb_r = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state @@ -2480,7 +2474,7 @@ for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)} io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W), io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W), io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W), - io.csr_pkt.csr_mimpid.asBool -> 0x2.U(32.W), + io.csr_pkt.csr_mimpid.asBool -> 0x1.U(32.W), io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)), io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)), io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)), diff --git a/design/src/main/scala/quasar.scala b/design/src/main/scala/quasar.scala index 0d59507e..bcda27ac 100644 --- a/design/src/main/scala/quasar.scala +++ b/design/src/main/scala/quasar.scala @@ -211,7 +211,7 @@ class quasar extends Module with RequireAsyncReset with lib { pic_ctrl_inst.io.free_clk := free_clk pic_ctrl_inst.io.active_clk := active_clk pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override - pic_ctrl_inst.io.extintsrc_req := io.extintsrc_req + pic_ctrl_inst.io.extintsrc_req := Cat(io.extintsrc_req, 0.U) pic_ctrl_inst.io.lsu_pic <> lsu.io.lsu_pic pic_ctrl_inst.io.dec_pic <> dec.io.dec_pic // Trace Packet diff --git a/design/target/scala-2.12/classes/dec/CSR_IO.class b/design/target/scala-2.12/classes/dec/CSR_IO.class index ee18fa7a..122e561a 100644 Binary files a/design/target/scala-2.12/classes/dec/CSR_IO.class and b/design/target/scala-2.12/classes/dec/CSR_IO.class differ diff --git a/design/target/scala-2.12/classes/dec/CSRs.class b/design/target/scala-2.12/classes/dec/CSRs.class index 9c9823aa..97894b07 100644 Binary files a/design/target/scala-2.12/classes/dec/CSRs.class and b/design/target/scala-2.12/classes/dec/CSRs.class differ diff --git a/design/target/scala-2.12/classes/dec/csr_tlu.class b/design/target/scala-2.12/classes/dec/csr_tlu.class index ffbf665f..eee5f095 100644 Binary files a/design/target/scala-2.12/classes/dec/csr_tlu.class and b/design/target/scala-2.12/classes/dec/csr_tlu.class differ diff --git a/design/target/scala-2.12/classes/dec/dec_decode_csr_read.class b/design/target/scala-2.12/classes/dec/dec_decode_csr_read.class index f4591435..40e2b7eb 100644 Binary files a/design/target/scala-2.12/classes/dec/dec_decode_csr_read.class and b/design/target/scala-2.12/classes/dec/dec_decode_csr_read.class differ diff --git a/design/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class b/design/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class index babbd4f6..43e78e5d 100644 Binary files a/design/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class and b/design/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class differ diff --git a/design/target/scala-2.12/classes/dec/dec_timer_ctl.class b/design/target/scala-2.12/classes/dec/dec_timer_ctl.class index 15916c2f..6a28be63 100644 Binary files a/design/target/scala-2.12/classes/dec/dec_timer_ctl.class and b/design/target/scala-2.12/classes/dec/dec_timer_ctl.class differ diff --git a/design/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class b/design/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class index e0446870..e9865b16 100644 Binary files a/design/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class and b/design/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class differ diff --git a/design/target/scala-2.12/classes/dec/dec_tlu_ctl.class b/design/target/scala-2.12/classes/dec/dec_tlu_ctl.class index 6277ae75..dcf6f127 100644 Binary files a/design/target/scala-2.12/classes/dec/dec_tlu_ctl.class and b/design/target/scala-2.12/classes/dec/dec_tlu_ctl.class differ diff --git a/design/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class b/design/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class index a08af594..601d35ba 100644 Binary files a/design/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class and b/design/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class differ diff --git a/design/target/scala-2.12/classes/quasar.class b/design/target/scala-2.12/classes/quasar.class index 2867c5df..a182e4ac 100644 Binary files a/design/target/scala-2.12/classes/quasar.class and b/design/target/scala-2.12/classes/quasar.class differ diff --git a/design/target/scala-2.12/quasar_2.12-3.3.0.jar b/design/target/scala-2.12/quasar_2.12-3.3.0.jar new file mode 100644 index 00000000..b856590f Binary files /dev/null and b/design/target/scala-2.12/quasar_2.12-3.3.0.jar differ diff --git a/design/target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous b/design/target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous index 1f21ae46..4e80b32a 100644 --- a/design/target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous +++ b/design/target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]",{"hashes":[["/home/waleedbinehsan/Downloads/Quasar/design/build.sbt","64e90423e55489a1881257da55da81b4fc55ae8f"],["/home/waleedbinehsan/Downloads/Quasar/design/project/plugins.sbt","361bf1247779b42e03c86deb53015d6b2c401dac"]],"lastModifiedTimes":[]}] \ No newline at end of file +["sbt.Task[scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]",{"hashes":[["/home/waleedbinehsan/Desktop/Quasar/design/build.sbt","64e90423e55489a1881257da55da81b4fc55ae8f"],["/home/waleedbinehsan/Desktop/Quasar/design/project/plugins.sbt","361bf1247779b42e03c86deb53015d6b2c401dac"]],"lastModifiedTimes":[]}] \ No newline at end of file diff --git a/design/target/streams/_global/_global/checkBuildSources/_global/streams/out b/design/target/streams/_global/_global/checkBuildSources/_global/streams/out index 6c981659..24ce6f61 100644 --- a/design/target/streams/_global/_global/checkBuildSources/_global/streams/out +++ b/design/target/streams/_global/_global/checkBuildSources/_global/streams/out @@ -1 +1 @@ -[debug] Checking for meta build source updates +[debug] Checking for meta build source updates diff --git a/design/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/design/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp index f5e601b0..2d2a095a 100644 --- a/design/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp +++ b/design/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp @@ -1 +1 @@ -{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) 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\ No newline at end of file +{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) 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\ No newline at end of file diff --git a/design/target/streams/compile/_global/_global/compileOutputs/previous b/design/target/streams/compile/_global/_global/compileOutputs/previous index 31a2a3c4..d7defdd9 100644 --- a/design/target/streams/compile/_global/_global/compileOutputs/previous +++ b/design/target/streams/compile/_global/_global/compileOutputs/previous @@ -1 +1 @@ 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+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar","/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar"]] \ No newline at end of file diff --git a/design/target/streams/compile/compile/_global/streams/out b/design/target/streams/compile/compile/_global/streams/out index 754b55dd..8e47630b 100644 --- a/design/target/streams/compile/compile/_global/streams/out +++ b/design/target/streams/compile/compile/_global/streams/out @@ -1,8 +1,10 @@ -[warn] there were 101 feature warnings; re-run with -feature for details -[warn] one warning found -[warn] /home/abdulhameed.akram/Videos/Quasar/src/main/scala/quasar.scala:289:8: Generated class QUASAR differs only in case from quasar. +[warn] /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/lib.scala:25:5: match may not be exhaustive. +[warn] It would fail on the following inputs: (0, _), (1, _), (??, _), (_, 0), (_, 1), (_, ??), (_, _) +[warn]  (ICACHE_WAYPACK, ICACHE_ECC) match{ +[warn]  ^ +[warn] /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar.scala:288:8: Generated class QUASAR differs only in case from quasar. [warn]  Such classes will overwrite one another on case-insensitive filesystems. [warn] object QUASAR extends App { [warn]  ^ -[warn] there were 123 feature warnings; re-run with -feature for details -[warn] two warnings found +[warn] there were 3730 feature warnings; re-run with -feature for details +[warn] three warnings found diff --git a/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip b/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip index 3c27f64a..6e2ef655 100644 Binary files a/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip and b/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip differ diff --git a/design/target/streams/compile/compileIncremental/_global/streams/export b/design/target/streams/compile/compileIncremental/_global/streams/export index e9802a74..fa24aad1 100644 --- a/design/target/streams/compile/compileIncremental/_global/streams/export +++ b/design/target/streams/compile/compileIncremental/_global/streams/export @@ -1,2 +1 @@ -scalac -bootclasspath /home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath 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-Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/mem.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dma_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/pic_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_ifc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_aln_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_bp_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_compress_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_intf.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_trigger.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_ecc.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_stbuf.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_dccm_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_lsc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_buffer.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_addrcheck.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_clkdomain.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_mul_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_div_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_alu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dbg/dbg.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/param.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/axi4_to_ahb.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/lib.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/ahb_to_axi4.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dmi/dmi_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/include/bundle.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_trigger.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_decode_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_ib_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_dec_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_tlu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_gpr_ctl.scala diff --git a/design/target/streams/compile/compileIncremental/_global/streams/out b/design/target/streams/compile/compileIncremental/_global/streams/out index 7ef19cc0..95e90bf7 100644 --- a/design/target/streams/compile/compileIncremental/_global/streams/out +++ b/design/target/streams/compile/compileIncremental/_global/streams/out @@ -1 +1,100 @@ -[debug] No changes +[debug]  +[debug] Initial source changes:  +[debug]  removed:Set(/home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/lib.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/mem.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dbg/dbg.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_mul_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_dec_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/param.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dmi/dmi_wrapper.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/include/bundle.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/quasar_wrapper.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dma_ctrl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/quasar.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_div_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_stbuf.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_gpr_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_trigger.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_ib_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_trigger.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_addrcheck.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/pic_ctrl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_ecc.scala) +[debug]  added: Set(/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dma_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_ib_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_div_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_compress_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/mem.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_tlu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_stbuf.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/lib.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_buffer.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_intf.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_aln_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_gpr_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dmi/dmi_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_bp_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/ahb_to_axi4.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_ecc.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_clkdomain.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dbg/dbg.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_mul_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_addrcheck.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/axi4_to_ahb.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_trigger.scala) +[debug]  modified: Set() +[debug] Invalidated products: Set(/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/dma$delayedInit$body.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/dmi/dmi_wrapper.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/ifu/ifu_ifc_ctl$$anon$1.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/include/read_data.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lsu/lsu_top.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/include/lsu_tlu.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/dec/dec_tlu_ctl.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/include/dma_lsc_ctl.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/include/inst_pkt_t.class, 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/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lsu/lsu_stbuf$$anon$1.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lsu/lsu_trigger$$anon$1.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/dbg/sb_state_t$.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lsu/bus_buffer.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/include/dest_pkt_t.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/dmi/dmi_wrapper$$anon$1.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/include/trace_pkt_t.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/mem/blackbox_mem.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/dec/CSR_VAL.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lsu/lsu_ecc.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lib/lib$rvdffe$.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/dec/dec_gpr_ctl.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/ifu/mem_ctl_io.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lsu/lsu_bus_intf.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/pic_gen$delayedInit$body.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class, /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/lsu/lsu_top$.class) +[debug] External API changes: API Changes: Set() +[debug] Modified binary dependencies: Set(/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar, /home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar, /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar, /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar, /home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar, /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar, /home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar) +[debug] Initial directly invalidated classes: Set(include.class_pkt_t, lsu.lsu_clkdomain, include.dbg_ib, dec.dec, include.dec_alu, exu.exu, dec.dec_decode_ctl, include.lsu_dma, lib.axi4_to_ahb_IO, lib.lib.gated_latch, lsu.lsu_trigger, lsu.lsu_top, include.exu_bp, dec.dec_gpr_ctl, lsu.lsu_addrcheck, mem.quasar, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, include.dctl_dma, include.div_pkt_t, dec.dec_tlu_ctl_IO, include.gpr_exu, include.ahb_out_dma, include.aln_dec, include.lsu_exu, dbg.state_t, dmi.dmi_wrapper, dec.dec_ib_ctl_IO, exu.exu_main, include.lsu_tlu, mem.quasar.mem, exu.exu_div_ctl, include.dccm_ext_in_pkt_t, include.ccm_ext_in_pkt_t, QUASAR, include.inst_pkt_t, lsu.lsu, dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, lib.ahb_to_axi4, lib.lib.rvecc_encode, lib.axi4_to_ahb, quasar, include.tlu_dma, include.lsu_pic, include.dma_lsc_ctl, include.rets_pkt_t, lib.lib.rvecc_encode_64, include.mul_pkt_t, dbg.dbg_main, dec.csr_tlu, lsu.lsu_lsc_ctl, include.reg_pkt_t, dmi.dmi_wrapper_module, include.trap_pkt_t, pic_ctrl, include.dma_mem_ctl, include.write_data, include.ic_data_ext_in_pkt_t, dec.CSRs, exu.exu_alu_ctl, lib.lib.rvsyncss, include.tlu_exu, dec.dec_IO, include.ib_exu, include.iccm_mem, include.lsu_dec, QUASAR_Wrp, quasar_bundle, lsu.lsu_ecc, mem.blackbox_mem, include.predict_pkt_t, dec.dec_main, dma, include.dec_ifc, include.write_addr, include.ifu_dma, include.tlu_busbuff, ifu.mem_ctl_io, include.lsu_error_pkt_t, pic_gen, lsu.lsu_bus_buffer, include.ahb_out, quasar_wrapper, include.trigger_pkt_t, include.write_resp, dec.CSR_IO, include.alu_pkt_t, include.trace_pkt_t, include.br_tlu_pkt_t, ifu.ifu_main, lib.lib.rvclkhdr, dec.dec_gpr_ctl_IO, dec.dec_timer_ctl, include.dest_pkt_t, include.dec_exu, lib.lib.rvdffe, include.read_data, include.ahb_in, ifu.ifu_aln_ctl, dbg.dbg, include.dma_dccm_ctl, include.ic_mem, lsu.lsu_bus_intf, dec.dec_ib_ctl, include.br_pkt_t, dec.CSR_VAL, exu.exu_mul_ctl, include.ahb_channel, dec.dec_trigger, lsu.lsu_dccm_ctl, include.cache_debug_pkt_t, ifu.ifu_compress_ctl, include.dec_pic, include.exu_ifu, dbg.sb_state_t, include.ic_tag_ext_in_pkt_t, ifu.ifu_bp_ctl, mem.Mem_bundle, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, lsu.lsu_stbuf, mem.mem_lsu, dec.dec_decode_csr_read, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.lsu_pkt_t, include.dec_div, include.dec_dma, include.decode_exu, include.dec_pkt_t, dec.dec_timer_ctl_IO, include.dec_dbg, include.load_cam_pkt_t, include.dma_ifc, dbg.dbg_dma, include.ifu_dec, lib.lib, include.dec_tlu_csr_pkt, dma_ctrl, include.dec_bp, include.dbg_dctl, lsu.bus_buffer) +[debug]  +[debug] Sources indirectly invalidated by: +[debug]  product: Set(/home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/lib.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/mem.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dbg/dbg.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_mul_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_dec_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/param.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dmi/dmi_wrapper.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/include/bundle.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/quasar_wrapper.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dma_ctrl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/quasar.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_div_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_stbuf.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_gpr_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_trigger.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_ib_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_trigger.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_addrcheck.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/pic_ctrl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_ecc.scala) +[debug]  binary dep: Set(/home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/lib.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/mem.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dbg/dbg.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_mul_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_dec_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/param.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dmi/dmi_wrapper.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/include/bundle.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/quasar_wrapper.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dma_ctrl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/quasar.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_div_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_stbuf.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_gpr_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_trigger.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_ib_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_trigger.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_addrcheck.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/pic_ctrl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_ecc.scala) +[debug]  external source: Set() +[debug] All initially invalidated classes: Set(include.class_pkt_t, lsu.lsu_clkdomain, include.dbg_ib, dec.dec, include.dec_alu, exu.exu, dec.dec_decode_ctl, include.lsu_dma, lib.axi4_to_ahb_IO, lib.lib.gated_latch, lsu.lsu_trigger, lsu.lsu_top, include.exu_bp, dec.dec_gpr_ctl, lsu.lsu_addrcheck, mem.quasar, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, include.dctl_dma, include.div_pkt_t, dec.dec_tlu_ctl_IO, include.gpr_exu, include.ahb_out_dma, include.aln_dec, include.lsu_exu, dbg.state_t, dmi.dmi_wrapper, dec.dec_ib_ctl_IO, exu.exu_main, include.lsu_tlu, mem.quasar.mem, exu.exu_div_ctl, include.dccm_ext_in_pkt_t, include.ccm_ext_in_pkt_t, QUASAR, include.inst_pkt_t, lsu.lsu, dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, lib.ahb_to_axi4, lib.lib.rvecc_encode, lib.axi4_to_ahb, quasar, include.tlu_dma, include.lsu_pic, include.dma_lsc_ctl, include.rets_pkt_t, lib.lib.rvecc_encode_64, include.mul_pkt_t, dbg.dbg_main, dec.csr_tlu, lsu.lsu_lsc_ctl, include.reg_pkt_t, dmi.dmi_wrapper_module, include.trap_pkt_t, pic_ctrl, include.dma_mem_ctl, include.write_data, include.ic_data_ext_in_pkt_t, dec.CSRs, exu.exu_alu_ctl, lib.lib.rvsyncss, include.tlu_exu, dec.dec_IO, include.ib_exu, include.iccm_mem, include.lsu_dec, QUASAR_Wrp, quasar_bundle, lsu.lsu_ecc, mem.blackbox_mem, include.predict_pkt_t, dec.dec_main, dma, include.dec_ifc, include.write_addr, include.ifu_dma, include.tlu_busbuff, ifu.mem_ctl_io, include.lsu_error_pkt_t, pic_gen, lsu.lsu_bus_buffer, include.ahb_out, quasar_wrapper, include.trigger_pkt_t, include.write_resp, dec.CSR_IO, include.alu_pkt_t, include.trace_pkt_t, include.br_tlu_pkt_t, ifu.ifu_main, lib.lib.rvclkhdr, dec.dec_gpr_ctl_IO, dec.dec_timer_ctl, include.dest_pkt_t, include.dec_exu, lib.lib.rvdffe, include.read_data, include.ahb_in, ifu.ifu_aln_ctl, dbg.dbg, include.dma_dccm_ctl, include.ic_mem, lsu.lsu_bus_intf, dec.dec_ib_ctl, include.br_pkt_t, dec.CSR_VAL, exu.exu_mul_ctl, include.ahb_channel, dec.dec_trigger, lsu.lsu_dccm_ctl, include.cache_debug_pkt_t, ifu.ifu_compress_ctl, include.dec_pic, include.exu_ifu, dbg.sb_state_t, include.ic_tag_ext_in_pkt_t, ifu.ifu_bp_ctl, mem.Mem_bundle, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, lsu.lsu_stbuf, mem.mem_lsu, dec.dec_decode_csr_read, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.lsu_pkt_t, include.dec_div, include.dec_dma, include.decode_exu, include.dec_pkt_t, dec.dec_timer_ctl_IO, include.dec_dbg, include.load_cam_pkt_t, include.dma_ifc, dbg.dbg_dma, include.ifu_dec, lib.lib, include.dec_tlu_csr_pkt, dma_ctrl, include.dec_bp, include.dbg_dctl, lsu.bus_buffer) +[debug] All initially invalidated sources:Set(/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dma_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_ib_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/lib.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/mem.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_decode_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_clkdomain.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dbg/dbg.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_mul_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_div_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_dec_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/ahb_to_axi4.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_compress_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/mem.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_tlu_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_dec_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_alu_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dmi/dmi_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_stbuf.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/lib.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_buffer.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_intf.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_tlu_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_aln_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_gpr_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/quasar_wrapper.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lib/axi4_to_ahb.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dmi/dmi_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_bp_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_bus_intf.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/ahb_to_axi4.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dma_ctrl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/quasar.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/exu/exu_div_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_stbuf.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_gpr_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar_wrapper.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_ecc.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_clkdomain.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dbg/dbg.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_mul_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_ib_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_addrcheck.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/dec/dec_trigger.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_addrcheck.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/axi4_to_ahb.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_trigger.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala, /home/abdulhameed.akram/Videos/Quasar/src/main/scala/lsu/lsu_ecc.scala) +[debug] Initial set of included nodes: include.class_pkt_t, lsu.lsu_clkdomain, include.dbg_ib, dec.dec, include.dec_alu, exu.exu, dec.dec_decode_ctl, include.lsu_dma, lib.axi4_to_ahb_IO, lib.lib.gated_latch, lsu.lsu_trigger, lsu.lsu_top, include.exu_bp, dec.dec_gpr_ctl, lsu.lsu_addrcheck, mem.quasar, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, include.dctl_dma, include.div_pkt_t, dec.dec_tlu_ctl_IO, include.gpr_exu, include.ahb_out_dma, include.aln_dec, include.lsu_exu, dbg.state_t, dmi.dmi_wrapper, dec.dec_ib_ctl_IO, exu.exu_main, include.lsu_tlu, mem.quasar.mem, exu.exu_div_ctl, include.dccm_ext_in_pkt_t, include.ccm_ext_in_pkt_t, QUASAR, include.inst_pkt_t, lsu.lsu, dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, lib.ahb_to_axi4, lib.lib.rvecc_encode, lib.axi4_to_ahb, quasar, include.tlu_dma, include.lsu_pic, include.dma_lsc_ctl, include.rets_pkt_t, lib.lib.rvecc_encode_64, include.mul_pkt_t, dbg.dbg_main, dec.csr_tlu, lsu.lsu_lsc_ctl, include.reg_pkt_t, dmi.dmi_wrapper_module, include.trap_pkt_t, pic_ctrl, include.dma_mem_ctl, include.write_data, include.ic_data_ext_in_pkt_t, dec.CSRs, exu.exu_alu_ctl, lib.lib.rvsyncss, include.tlu_exu, dec.dec_IO, include.ib_exu, include.iccm_mem, include.lsu_dec, QUASAR_Wrp, quasar_bundle, lsu.lsu_ecc, mem.blackbox_mem, include.predict_pkt_t, dec.dec_main, dma, include.dec_ifc, include.write_addr, include.ifu_dma, include.tlu_busbuff, ifu.mem_ctl_io, include.lsu_error_pkt_t, pic_gen, lsu.lsu_bus_buffer, include.ahb_out, quasar_wrapper, include.trigger_pkt_t, include.write_resp, dec.CSR_IO, include.alu_pkt_t, include.trace_pkt_t, include.br_tlu_pkt_t, ifu.ifu_main, lib.lib.rvclkhdr, dec.dec_gpr_ctl_IO, dec.dec_timer_ctl, include.dest_pkt_t, include.dec_exu, lib.lib.rvdffe, include.read_data, include.ahb_in, ifu.ifu_aln_ctl, dbg.dbg, include.dma_dccm_ctl, include.ic_mem, lsu.lsu_bus_intf, dec.dec_ib_ctl, include.br_pkt_t, dec.CSR_VAL, exu.exu_mul_ctl, include.ahb_channel, dec.dec_trigger, lsu.lsu_dccm_ctl, include.cache_debug_pkt_t, ifu.ifu_compress_ctl, include.dec_pic, include.exu_ifu, dbg.sb_state_t, include.ic_tag_ext_in_pkt_t, ifu.ifu_bp_ctl, mem.Mem_bundle, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, lsu.lsu_stbuf, mem.mem_lsu, dec.dec_decode_csr_read, include.dec_mem_ctrl, ifu.ifu_mem_ctl, ifu.ifu_ifc_ctl, include.lsu_pkt_t, include.dec_div, include.dec_dma, include.decode_exu, include.dec_pkt_t, dec.dec_timer_ctl_IO, include.dec_dbg, include.load_cam_pkt_t, include.dma_ifc, dbg.dbg_dma, include.ifu_dec, lib.lib, include.dec_tlu_csr_pkt, dma_ctrl, include.dec_bp, include.dbg_dctl, lsu.bus_buffer +[debug] Including dec.dec_ib_ctl_IO by lib.param +[debug] Including lsu.lsu by lib.param +[debug] Including dec.dec_ib_ctl by lib.param +[debug] Including lib.lib by lib.param +[debug] Including ifu.ifu by lib.lib +[debug] Including include.aln_ib by lib.lib +[debug] Including dec.dec_tlu_ctl_IO by lib.lib +[debug] Including exu.exu_div_ctl by lib.lib +[debug] Including dec.dec_tlu_ctl by lib.lib +[debug] Including lib.ahb_to_axi4 by lib.lib +[debug] Including lib.axi4_to_ahb by lib.lib +[debug] Including quasar by lib.lib +[debug] Including dec.csr_tlu by lib.lib +[debug] Including lsu.lsu_lsc_ctl by lib.lib +[debug] Including pic_ctrl by lib.lib +[debug] Including include.write_data by lib.lib +[debug] Including exu.exu_alu_ctl by lib.lib +[debug] Including include.tlu_exu by lib.lib +[debug] Including dec.dec_IO by lib.lib +[debug] Including include.iccm_mem by lib.lib +[debug] Including quasar_bundle by lib.lib +[debug] Including lsu.lsu_ecc by lib.lib +[debug] Including mem.blackbox_mem by lib.lib +[debug] Including include.write_addr by lib.lib +[debug] Including ifu.mem_ctl_io by lib.lib +[debug] Including lsu.lsu_bus_buffer by lib.lib +[debug] Including quasar_wrapper by lib.lib +[debug] Including include.write_resp by lib.lib +[debug] Including dec.CSR_IO by lib.lib +[debug] Including dec.dec_timer_ctl by lib.lib +[debug] Including include.dec_exu by lib.lib +[debug] Including include.read_data by lib.lib +[debug] Including ifu.ifu_aln_ctl by lib.lib +[debug] Including dbg.dbg by lib.lib +[debug] Including include.ic_mem by lib.lib +[debug] Including lsu.lsu_bus_intf by lib.lib +[debug] Including exu.exu_mul_ctl by lib.lib +[debug] Including dec.dec_trigger by lib.lib +[debug] Including lsu.lsu_dccm_ctl by lib.lib +[debug] Including ifu.ifu_compress_ctl by lib.lib +[debug] Including ifu.ifu_bp_ctl by lib.lib +[debug] Including mem.Mem_bundle by lib.lib +[debug] Including include.dctl_busbuff by lib.lib +[debug] Including include.read_addr by lib.lib +[debug] Including include.axi_channels by lib.lib +[debug] Including dec.dec_dec_ctl by lib.lib +[debug] Including lsu.lsu_stbuf by lib.lib +[debug] Including mem.mem_lsu by lib.lib +[debug] Including include.dec_mem_ctrl by lib.lib +[debug] Including ifu.ifu_mem_ctl by lib.lib +[debug] Including ifu.ifu_ifc_ctl by lib.lib +[debug] Including include.decode_exu by lib.lib +[debug] Including dma_ctrl by lib.lib +[debug] Recompiling all sources: number of invalidated sources > 50.0% of all sources +[info] Compiling 39 Scala sources to /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes ... +[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 +[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 +[debug] [zinc] Running cached compiler 1090d025 for Scala compiler version 2.12.10 +[debug] [zinc] The Scala compiler is invoked with: +[debug]  -Xsource:2.11 +[debug]  -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar +[debug]  -bootclasspath +[debug]  /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar +[debug]  -classpath +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar +[debug] Scala compilation took 58.99550602 s +[debug] Done compiling. +[debug] Invalidating (transitively) by inheritance from dma_ctrl... +[debug] Initial set of included nodes: dma_ctrl +[debug] Invalidated by transitive inheritance dependency: Set(dma_ctrl) +[debug] None of the modified names appears in source file of quasar. This dependency is not being considered for invalidation. +[debug] Change NamesChange(dma_ctrl,ModifiedNames(changes = UsedName(dma_buffer_c1cgc,[Default]), UsedName(dma_free_cgc,[Default]), UsedName(dma_bus_cgc,[Default]))) invalidates 1 classes due to The dma_ctrl has the following regular definitions changed: +[debug]  UsedName(dma_buffer_c1cgc,[Default]), UsedName(dma_free_cgc,[Default]), UsedName(dma_bus_cgc,[Default]). +[debug]  > by transitive inheritance: Set(dma_ctrl) +[debug]  >  +[debug]  >  +[debug]   +[debug] New invalidations: +[debug]  Set() +[debug] Initial set of included nodes:  +[debug] Previously invalidated, but (transitively) depend on new invalidations: +[debug]  Set() +[debug] No classes were invalidated. diff --git a/design/target/streams/compile/copyResources/_global/streams/copy-resources b/design/target/streams/compile/copyResources/_global/streams/copy-resources index ade4d802..980e61e5 100644 --- a/design/target/streams/compile/copyResources/_global/streams/copy-resources +++ b/design/target/streams/compile/copyResources/_global/streams/copy-resources @@ -1 +1 @@ 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\ No newline at end of file diff --git a/design/target/streams/compile/copyResources/_global/streams/out b/design/target/streams/compile/copyResources/_global/streams/out index 613c3ffb..b3f57429 100644 --- a/design/target/streams/compile/copyResources/_global/streams/out +++ b/design/target/streams/compile/copyResources/_global/streams/out @@ -1,14 +1,14 @@ [debug] Copy resource mappings:  -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/ifu_iccm_mem.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/gated_latch.v,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/gated_latch.v) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/lsu_dccm_mem.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/dmi_wrapper.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/dmi_wrapper.sv) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/gated_latch.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/gated_latch.sv) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/rvjtag_tap.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/rvjtag_tap.sv) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/rvtaj_tap.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/rvtaj_tap.sv) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/mem.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/mem.sv) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/mem_mod.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/mem_mod.sv) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/beh_lib.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/beh_lib.sv) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/mem_lib.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/mem_lib.sv) -[debug]  (/home/abdulhameed.akram/Videos/Quasar/src/main/resources/vsrc/ifu_ic_mem.sv,/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.v,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/gated_latch.v) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/beh_lib.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/beh_lib.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvtaj_tap.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/rvtaj_tap.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/gated_latch.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/gated_latch.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/rvjtag_tap.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_lib.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_lib.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/mem_mod.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/mem_mod.sv) +[debug]  (/home/waleedbinehsan/Desktop/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv,/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv) diff --git a/design/target/streams/compile/dependencyClasspath/_global/streams/export b/design/target/streams/compile/dependencyClasspath/_global/streams/export index 58921df4..414eb951 100644 --- a/design/target/streams/compile/dependencyClasspath/_global/streams/export +++ b/design/target/streams/compile/dependencyClasspath/_global/streams/export @@ -1 +1 @@ -/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar +/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/design/target/streams/compile/exportedProductJars/_global/streams/export b/design/target/streams/compile/exportedProductJars/_global/streams/export index ab1754f8..00034520 100644 --- a/design/target/streams/compile/exportedProductJars/_global/streams/export +++ b/design/target/streams/compile/exportedProductJars/_global/streams/export @@ -1 +1 @@ -/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar +/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/quasar_2.12-3.3.0.jar diff --git a/design/target/streams/compile/exportedProducts/_global/streams/export b/design/target/streams/compile/exportedProducts/_global/streams/export index 2f56444e..0e856e20 100644 --- a/design/target/streams/compile/exportedProducts/_global/streams/export +++ b/design/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/classes +/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes diff --git a/design/target/streams/compile/packageBin/_global/streams/inputs b/design/target/streams/compile/packageBin/_global/streams/inputs index d8452f02..ba6b6d05 100644 --- a/design/target/streams/compile/packageBin/_global/streams/inputs +++ b/design/target/streams/compile/packageBin/_global/streams/inputs @@ -1 +1 @@ --1845828660 \ No newline at end of file +-1351690629 \ No newline at end of file diff --git a/design/target/streams/compile/packageBin/_global/streams/out b/design/target/streams/compile/packageBin/_global/streams/out index 3971eae1..3fc0b355 100644 --- a/design/target/streams/compile/packageBin/_global/streams/out +++ b/design/target/streams/compile/packageBin/_global/streams/out @@ -1 +1,487 @@ -[debug] Jar uptodate: /home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar +[debug] Packaging /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/quasar_2.12-3.3.0.jar ... +[debug] Input file mappings: +[debug]  pic_ctrl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/pic_ctrl$$anon$1.class +[debug]  QUASAR_Wrp$delayedInit$body.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class +[debug]  ifu +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu +[debug]  ifu/ifu_aln_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_aln_ctl$$anon$1.class +[debug]  ifu/ifu_aln_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_aln_ctl.class +[debug]  ifu/ifu_compress_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_compress_ctl$$anon$1.class +[debug]  ifu/ifu_ifc_ctl$$anon$1.class +[debug]  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/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/alu_pkt_t.class +[debug]  include/rets_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/rets_pkt_t.class +[debug]  include/read_addr$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/read_addr$.class +[debug]  dec +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec +[debug]  dec/dec_trigger$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_trigger$$anon$1.class +[debug]  dec/dec_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_IO.class +[debug]  dec/CSR_VAL.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/CSR_VAL.class +[debug]  dec/dec_ib_ctl_IO.class +[debug]  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/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_ib_ctl.class +[debug]  dec/dec_main$.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_main$.class +[debug]  dec/CSR_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/CSR_IO.class +[debug]  dec/dec_decode_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class +[debug]  dec/dec_decode_csr_read.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_decode_csr_read.class +[debug]  dec/dec.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec.class +[debug]  dec/dec_decode_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_decode_ctl.class +[debug]  dec/dec_trigger.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_trigger.class +[debug]  dec/csr_tlu.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/csr_tlu.class +[debug]  dec/dec_dec_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_dec_ctl.class +[debug]  dec/dec_gpr_ctl.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_gpr_ctl.class +[debug]  dec/CSRs.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/CSRs.class +[debug]  dec/dec_decode_csr_read_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class +[debug]  dec/dec_tlu_ctl_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class +[debug]  dec/dec_timer_ctl_IO.class +[debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class +[debug] Done packaging. diff --git a/design/target/streams/compile/packageBin/_global/streams/output b/design/target/streams/compile/packageBin/_global/streams/output index 3e238bb9..48f778a1 100644 --- a/design/target/streams/compile/packageBin/_global/streams/output +++ b/design/target/streams/compile/packageBin/_global/streams/output @@ -1 +1 @@ -333153426 \ No newline at end of file +-1545824173 \ No newline at end of file diff --git a/design/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export b/design/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export index 5a4177ae..10739d47 100644 --- a/design/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export +++ b/design/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export @@ -1 +1 @@ -/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar +/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/quasar_2.12-3.3.0.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/design/target/streams/runtime/exportedProductJars/_global/streams/export b/design/target/streams/runtime/exportedProductJars/_global/streams/export index ab1754f8..00034520 100644 --- a/design/target/streams/runtime/exportedProductJars/_global/streams/export +++ b/design/target/streams/runtime/exportedProductJars/_global/streams/export @@ -1 +1 @@ -/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar +/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/quasar_2.12-3.3.0.jar diff --git a/design/target/streams/runtime/fullClasspathAsJars/_global/streams/export b/design/target/streams/runtime/fullClasspathAsJars/_global/streams/export index 5a4177ae..10739d47 100644 --- a/design/target/streams/runtime/fullClasspathAsJars/_global/streams/export +++ b/design/target/streams/runtime/fullClasspathAsJars/_global/streams/export @@ -1 +1 @@ -/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/abdulhameed.akram/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/abdulhameed.akram/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar +/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/quasar_2.12-3.3.0.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/design/target/streams/runtime/internalDependencyAsJars/_global/streams/export b/design/target/streams/runtime/internalDependencyAsJars/_global/streams/export index ab1754f8..00034520 100644 --- a/design/target/streams/runtime/internalDependencyAsJars/_global/streams/export +++ b/design/target/streams/runtime/internalDependencyAsJars/_global/streams/export @@ -1 +1 @@ -/home/abdulhameed.akram/Videos/Quasar/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar +/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/quasar_2.12-3.3.0.jar diff --git a/project/build.properties b/project/build.properties new file mode 100644 index 00000000..a919a9b5 --- /dev/null +++ b/project/build.properties @@ -0,0 +1 @@ +sbt.version=1.3.8 diff --git a/project/target/config-classes/$27cce1eda699f039df66$.class b/project/target/config-classes/$27cce1eda699f039df66$.class new file mode 100644 index 00000000..75b0687d Binary files /dev/null and b/project/target/config-classes/$27cce1eda699f039df66$.class differ diff --git a/design/project/target/config-classes/$e4a8ad5aae0c730d8f97.cache b/project/target/config-classes/$27cce1eda699f039df66.cache similarity index 100% rename from design/project/target/config-classes/$e4a8ad5aae0c730d8f97.cache rename to project/target/config-classes/$27cce1eda699f039df66.cache diff --git a/project/target/config-classes/$27cce1eda699f039df66.class b/project/target/config-classes/$27cce1eda699f039df66.class new file mode 100644 index 00000000..dec8536c Binary files /dev/null and b/project/target/config-classes/$27cce1eda699f039df66.class differ diff --git a/project/target/config-classes/$3fbd82581ecade347275$.class b/project/target/config-classes/$3fbd82581ecade347275$.class new file mode 100644 index 00000000..2227f56e Binary files /dev/null and b/project/target/config-classes/$3fbd82581ecade347275$.class differ diff --git a/project/target/config-classes/$3fbd82581ecade347275.cache b/project/target/config-classes/$3fbd82581ecade347275.cache new file mode 100644 index 00000000..050f36c6 --- /dev/null +++ b/project/target/config-classes/$3fbd82581ecade347275.cache @@ -0,0 +1 @@ +sbt.internal.DslEntry \ No newline at end of file diff --git a/project/target/config-classes/$3fbd82581ecade347275.class b/project/target/config-classes/$3fbd82581ecade347275.class new file mode 100644 index 00000000..841da056 Binary files /dev/null and b/project/target/config-classes/$3fbd82581ecade347275.class differ diff --git a/project/target/config-classes/$59b601fcb0b59f25e5f5$.class b/project/target/config-classes/$59b601fcb0b59f25e5f5$.class new file mode 100644 index 00000000..3620489d Binary files /dev/null and b/project/target/config-classes/$59b601fcb0b59f25e5f5$.class differ diff --git a/project/target/config-classes/$59b601fcb0b59f25e5f5.cache b/project/target/config-classes/$59b601fcb0b59f25e5f5.cache new file mode 100644 index 00000000..050f36c6 --- /dev/null +++ b/project/target/config-classes/$59b601fcb0b59f25e5f5.cache @@ -0,0 +1 @@ +sbt.internal.DslEntry \ No newline at end of file diff --git a/project/target/config-classes/$59b601fcb0b59f25e5f5.class b/project/target/config-classes/$59b601fcb0b59f25e5f5.class new file mode 100644 index 00000000..5d8dfc12 Binary files /dev/null and b/project/target/config-classes/$59b601fcb0b59f25e5f5.class differ diff --git a/project/target/config-classes/$7e1407c47bdda52fa2ab$.class b/project/target/config-classes/$7e1407c47bdda52fa2ab$.class new file mode 100644 index 00000000..2a3bee08 Binary files /dev/null and b/project/target/config-classes/$7e1407c47bdda52fa2ab$.class differ diff --git a/project/target/config-classes/$7e1407c47bdda52fa2ab.cache b/project/target/config-classes/$7e1407c47bdda52fa2ab.cache new file mode 100644 index 00000000..050f36c6 --- /dev/null +++ b/project/target/config-classes/$7e1407c47bdda52fa2ab.cache @@ -0,0 +1 @@ +sbt.internal.DslEntry \ No newline at end of file diff --git a/project/target/config-classes/$7e1407c47bdda52fa2ab.class b/project/target/config-classes/$7e1407c47bdda52fa2ab.class new file mode 100644 index 00000000..a5b638ac Binary files /dev/null and b/project/target/config-classes/$7e1407c47bdda52fa2ab.class differ diff --git a/project/target/config-classes/$7e5e34023cc1dba24d2f$.class b/project/target/config-classes/$7e5e34023cc1dba24d2f$.class new file mode 100644 index 00000000..a496bd15 Binary files /dev/null and b/project/target/config-classes/$7e5e34023cc1dba24d2f$.class differ diff --git a/project/target/config-classes/$7e5e34023cc1dba24d2f.cache b/project/target/config-classes/$7e5e34023cc1dba24d2f.cache new file mode 100644 index 00000000..050f36c6 --- /dev/null +++ b/project/target/config-classes/$7e5e34023cc1dba24d2f.cache @@ -0,0 +1 @@ +sbt.internal.DslEntry \ No newline at end of file diff --git a/project/target/config-classes/$7e5e34023cc1dba24d2f.class b/project/target/config-classes/$7e5e34023cc1dba24d2f.class new file mode 100644 index 00000000..c3d97ee4 Binary files /dev/null and b/project/target/config-classes/$7e5e34023cc1dba24d2f.class differ diff --git a/project/target/config-classes/$9d6e172ad6c5fb547981$.class b/project/target/config-classes/$9d6e172ad6c5fb547981$.class new file mode 100644 index 00000000..8f5f3a3b Binary files /dev/null and b/project/target/config-classes/$9d6e172ad6c5fb547981$.class differ diff --git a/project/target/config-classes/$9d6e172ad6c5fb547981.cache b/project/target/config-classes/$9d6e172ad6c5fb547981.cache new file mode 100644 index 00000000..050f36c6 --- /dev/null +++ b/project/target/config-classes/$9d6e172ad6c5fb547981.cache @@ -0,0 +1 @@ +sbt.internal.DslEntry \ No newline at end of file diff --git a/project/target/config-classes/$9d6e172ad6c5fb547981.class b/project/target/config-classes/$9d6e172ad6c5fb547981.class new file mode 100644 index 00000000..416718d3 Binary files /dev/null and b/project/target/config-classes/$9d6e172ad6c5fb547981.class differ diff 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b/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out new file mode 100644 index 00000000..e69de29b diff --git a/project/target/streams/_global/update/_global/streams/out b/project/target/streams/_global/update/_global/streams/out new file mode 100644 index 00000000..973e5828 --- /dev/null +++ b/project/target/streams/_global/update/_global/streams/out @@ -0,0 +1,3 @@ +[debug] "not up to date. inChanged = true, force = false +[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")... +[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build") diff --git a/project/target/streams/compile/_global/_global/compileBinaryFileInputs/previous b/project/target/streams/compile/_global/_global/compileBinaryFileInputs/previous new file mode 100644 index 00000000..c924bf26 --- /dev/null +++ b/project/target/streams/compile/_global/_global/compileBinaryFileInputs/previous @@ -0,0 +1 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\ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/target/streams/compile/_global/_global/compileOutputs/previous new file mode 100644 index 00000000..e2319964 --- /dev/null +++ b/project/target/streams/compile/_global/_global/compileOutputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/Quasar/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/compileSourceFileInputs/previous b/project/target/streams/compile/_global/_global/compileSourceFileInputs/previous new file mode 100644 index 00000000..15829e87 --- /dev/null +++ b/project/target/streams/compile/_global/_global/compileSourceFileInputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[],"lastModifiedTimes":[]}}] \ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous b/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous new file mode 100644 index 00000000..5fb6daa8 --- /dev/null +++ b/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/project/target/streams/compile/_global/_global/discoveredMainClasses/data new file mode 100644 index 00000000..0637a088 --- /dev/null +++ b/project/target/streams/compile/_global/_global/discoveredMainClasses/data @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/managedSourcePaths/previous b/project/target/streams/compile/_global/_global/managedSourcePaths/previous new file mode 100644 index 00000000..a510b125 --- /dev/null +++ b/project/target/streams/compile/_global/_global/managedSourcePaths/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",[]] \ No newline at end of file diff --git a/project/target/streams/compile/compile/_global/streams/out b/project/target/streams/compile/compile/_global/streams/out new file mode 100644 index 00000000..e69de29b diff --git a/project/target/streams/compile/compileIncremental/_global/streams/export b/project/target/streams/compile/compileIncremental/_global/streams/export new file mode 100644 index 00000000..e69de29b diff --git a/project/target/streams/compile/compileIncremental/_global/streams/out b/project/target/streams/compile/compileIncremental/_global/streams/out new file mode 100644 index 00000000..6db8e09d --- /dev/null +++ b/project/target/streams/compile/compileIncremental/_global/streams/out @@ -0,0 +1 @@ +[debug] Full compilation, no sources in previous analysis. diff --git a/project/target/streams/compile/copyResources/_global/streams/copy-resources b/project/target/streams/compile/copyResources/_global/streams/copy-resources new file mode 100644 index 00000000..9d348e7b --- /dev/null +++ b/project/target/streams/compile/copyResources/_global/streams/copy-resources @@ -0,0 +1 @@ +[[{},{}],{}] \ No newline at end of file diff --git a/project/target/streams/compile/copyResources/_global/streams/out b/project/target/streams/compile/copyResources/_global/streams/out new file mode 100644 index 00000000..f25042f2 --- /dev/null +++ b/project/target/streams/compile/copyResources/_global/streams/out @@ -0,0 +1,2 @@ +[debug] Copy resource mappings:  +[debug]   diff --git a/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/target/streams/compile/dependencyClasspath/_global/streams/export new file mode 100644 index 00000000..04af299b --- /dev/null +++ b/project/target/streams/compile/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/target/streams/compile/exportedProducts/_global/streams/export b/project/target/streams/compile/exportedProducts/_global/streams/export new file mode 100644 index 00000000..21b0f701 --- /dev/null +++ b/project/target/streams/compile/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..a2d1c782 --- /dev/null +++ b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.3.4/zinc-compile-core_2.12-1.3.4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.3.8/testing_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.3.8/scripted-plugin_2.12-1.3.8.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.3.1/librarymanagement-ivy_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.3.8/zinc-lm-integration_2.12-1.3.8.jar diff --git a/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/target/streams/compile/internalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/compile/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/compile/managedClasspath/_global/streams/export b/project/target/streams/compile/managedClasspath/_global/streams/export new file mode 100644 index 00000000..a2d1c782 --- /dev/null +++ b/project/target/streams/compile/managedClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/ssl-config-core_2.12/0.4.0/ssl-config-core_2.12-0.4.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.3.3/io_2.12-1.3.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.3.8/main_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/trueaccord/lenses/lenses_2.12/0.4.12/lenses_2.12-0.4.12.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.3.8/command_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.5.6/caffeine-2.5.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.3.8/task-system_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.3.8/main-settings_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-core_2.12/0.5.0/gigahorse-core_2.12-0.5.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.7.0/protobuf-java-3.7.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-okhttp_2.12/0.5.0/gigahorse-okhttp_2.12-0.5.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-scalajson_2.12/0.8.3/sjson-new-scalajson_2.12-0.8.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.3.3/util-relation_2.12-1.3.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/spire-math/jawn-parser_2.12/0.10.4/jawn-parser_2.12-0.10.4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classpath_2.12/1.3.4/zinc-classpath_2.12-1.3.4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-core_2.12/1.3.4/zinc-core_2.12-1.3.4.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-compiler.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/4.5.0/jna-4.5.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/fastparse-utils_2.12/0.4.2/fastparse-utils_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lmax/disruptor/3.4.2/disruptor-3.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.3.8/tasks_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/reactivestreams/reactive-streams/1.0.2/reactive-streams-1.0.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.26/slf4j-api-1.7.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.3/file-tree-views-2.1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okhttp3/okhttp/3.14.2/okhttp-3.14.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.12/0.1.3/sourcecode_2.12-0.1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/jcraft/jsch/0.1.54/jsch-0.1.54.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-scripted_2.12/1.3.3/util-scripted_2.12-1.3.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.3.3/util-cache_2.12-1.3.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.11.2/log4j-slf4j-impl-2.11.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/4.5.0/jna-platform-4.5.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/jline/jline/2.14.6/jline-2.14.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.3.8/sbt-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.3.8/protocol_2.12-1.3.8.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/fastparse_2.12/0.4.2/fastparse_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parser-combinators_2.12/1.1.2/scala-parser-combinators_2.12-1.1.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.3.4/zinc_2.12-1.3.4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-caffeine_2.12/0.20.0/scalacache-caffeine_2.12-0.20.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-88d6a93d15f9b029958c1c289a8859e8dfe31a19/ivy-2.3.0-sbt-88d6a93d15f9b029958c1c289a8859e8dfe31a19.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.3.8/logic_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ipcsocket/ipcsocket/1.0.0/ipcsocket-1.0.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist_2.12/1.3.4/zinc-persist_2.12-1.3.4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-scalajson_2.12/1.0.0-M4/shaded-scalajson_2.12-1.0.0-M4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.3.8/collections_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.1.3/launcher-interface-1.1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/trueaccord/scalapb/scalapb-runtime_2.12/0.6.0/scalapb-runtime_2.12-0.6.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.3.4/compiler-interface-1.3.4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.3.3/util-control_2.12-1.3.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-agent/1.3.8/test-agent-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classfile_2.12/1.3.4/zinc-classfile_2.12-1.3.4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-apiinfo_2.12/1.3.4/zinc-apiinfo_2.12-1.3.4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.3.8/completion_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.3.4/zinc-compile_2.12-1.3.4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.0.0-RC5-3/lm-coursier-shaded_2.12-2.0.0-RC5-3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.3.8/core-macros_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.3.8/run_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-core_2.12/0.20.0/scalacache-core_2.12-0.20.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.3.3/util-position_2.12-1.3.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.8.3/sjson-new-core_2.12-0.8.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/config/1.3.3/config-1.3.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.3.1/librarymanagement-core_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbinary_2.12/0.5.0/sbinary_2.12-0.5.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okhttp3/okhttp-urlconnection/3.7.0/okhttp-urlconnection-3.7.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.11.2/log4j-api-2.11.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okio/okio/1.17.2/okio-1.17.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-interface/1.3.3/util-interface-1.3.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.11.2/log4j-core-2.11.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.3.3/util-logging_2.12-1.3.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-tracking_2.12/1.3.3/util-tracking_2.12-1.3.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-murmurhash_2.12/0.8.3/sjson-new-murmurhash_2.12-0.8.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.3.4/compiler-bridge_2.12-1.3.4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.3.8/actions_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-sbt-redux_2.12/1.3.8/scripted-sbt-redux_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.3.4/zinc-compile-core_2.12-1.3.4.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.3.8/testing_2.12-1.3.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.3.8/scripted-plugin_2.12-1.3.8.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.3.1/librarymanagement-ivy_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.3.8/zinc-lm-integration_2.12-1.3.8.jar diff --git a/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/target/streams/compile/unmanagedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/compile/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/target/streams/compile/unmanagedJars/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/compile/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/target/streams/runtime/dependencyClasspath/_global/streams/export new file mode 100644 index 00000000..098804aa --- /dev/null +++ b/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/target/streams/runtime/exportedProducts/_global/streams/export new file mode 100644 index 00000000..21b0f701 --- /dev/null +++ b/project/target/streams/runtime/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/target/streams/runtime/fullClasspath/_global/streams/export new file mode 100644 index 00000000..098804aa --- /dev/null +++ b/project/target/streams/runtime/fullClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..21b0f701 --- /dev/null +++ b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/target/streams/runtime/managedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/runtime/managedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/runtime/unmanagedClasspath/_global/streams/export b/project/target/streams/runtime/unmanagedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/runtime/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/runtime/unmanagedJars/_global/streams/export b/project/target/streams/runtime/unmanagedJars/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/runtime/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/.history b/target/.history new file mode 100644 index 00000000..d6828caf --- /dev/null +++ b/target/.history @@ -0,0 +1 @@ +;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure diff --git a/target/scala-2.12/quasar_2.12-3.3.0.jar b/target/scala-2.12/quasar_2.12-3.3.0.jar new file mode 100644 index 00000000..9476a7df Binary files /dev/null and b/target/scala-2.12/quasar_2.12-3.3.0.jar differ diff --git a/target/scala-2.12/update/update_cache_2.12/inputs b/target/scala-2.12/update/update_cache_2.12/inputs new file mode 100644 index 00000000..fd63c32b --- /dev/null +++ b/target/scala-2.12/update/update_cache_2.12/inputs @@ -0,0 +1 @@ +-711512175 \ No newline at end of file diff --git a/target/scala-2.12/update/update_cache_2.12/output b/target/scala-2.12/update/update_cache_2.12/output new file mode 100644 index 00000000..4ba78d23 --- /dev/null +++ b/target/scala-2.12/update/update_cache_2.12/output @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/target/streams/compile/_global/_global/compileOutputs/previous b/target/streams/compile/_global/_global/compileOutputs/previous new file mode 100644 index 00000000..687259c5 --- /dev/null +++ b/target/streams/compile/_global/_global/compileOutputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/Quasar/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/target/streams/compile/_global/_global/compileSourceFileInputs/previous b/target/streams/compile/_global/_global/compileSourceFileInputs/previous new file mode 100644 index 00000000..15829e87 --- /dev/null +++ b/target/streams/compile/_global/_global/compileSourceFileInputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, 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+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar","/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar","/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar"]] \ No newline at end of file diff --git a/target/streams/compile/_global/_global/discoveredMainClasses/data b/target/streams/compile/_global/_global/discoveredMainClasses/data new file mode 100644 index 00000000..0637a088 --- /dev/null +++ b/target/streams/compile/_global/_global/discoveredMainClasses/data @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/target/streams/compile/_global/_global/managedSourcePaths/previous b/target/streams/compile/_global/_global/managedSourcePaths/previous new file mode 100644 index 00000000..a510b125 --- /dev/null +++ b/target/streams/compile/_global/_global/managedSourcePaths/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",[]] \ No newline at end of file diff --git a/target/streams/compile/bgRun/_global/streams/out b/target/streams/compile/bgRun/_global/streams/out new file mode 100644 index 00000000..55a73dd0 --- /dev/null +++ b/target/streams/compile/bgRun/_global/streams/out @@ -0,0 +1,21 @@ +[error] java.lang.RuntimeException: No main class detected. +[error]  at scala.sys.package$.error(package.scala:30) +[error]  at sbt.Defaults$.$anonfun$bgRunTask$4(Defaults.scala:1474) +[error]  at scala.Option.getOrElse(Option.scala:189) +[error]  at sbt.Defaults$.$anonfun$bgRunTask$3(Defaults.scala:1474) +[error]  at scala.Function1.$anonfun$compose$1(Function1.scala:49) +[error]  at sbt.internal.util.$tilde$greater.$anonfun$$u2219$1(TypeFunctions.scala:62) +[error]  at sbt.std.Transform$$anon$4.work(Transform.scala:67) +[error]  at sbt.Execute.$anonfun$submit$2(Execute.scala:281) +[error]  at sbt.internal.util.ErrorHandling$.wideConvert(ErrorHandling.scala:19) +[error]  at sbt.Execute.work(Execute.scala:290) +[error]  at sbt.Execute.$anonfun$submit$1(Execute.scala:281) +[error]  at sbt.ConcurrentRestrictions$$anon$4.$anonfun$submitValid$1(ConcurrentRestrictions.scala:178) +[error]  at sbt.CompletionService$$anon$2.call(CompletionService.scala:37) +[error]  at java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264) +[error]  at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Executors.java:515) +[error]  at java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264) +[error]  at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128) +[error]  at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628) +[error]  at java.base/java.lang.Thread.run(Thread.java:834) +[error] (Compile / bgRun) No main class detected. diff --git a/target/streams/compile/compile/_global/streams/out b/target/streams/compile/compile/_global/streams/out new file mode 100644 index 00000000..e69de29b diff --git a/target/streams/compile/compileIncremental/_global/streams/export b/target/streams/compile/compileIncremental/_global/streams/export new file mode 100644 index 00000000..e69de29b diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out new file mode 100644 index 00000000..6db8e09d --- /dev/null +++ b/target/streams/compile/compileIncremental/_global/streams/out @@ -0,0 +1 @@ +[debug] Full compilation, no sources in previous analysis. diff --git a/target/streams/compile/copyResources/_global/streams/copy-resources b/target/streams/compile/copyResources/_global/streams/copy-resources new file mode 100644 index 00000000..9d348e7b --- /dev/null +++ b/target/streams/compile/copyResources/_global/streams/copy-resources @@ -0,0 +1 @@ +[[{},{}],{}] \ No newline at end of file diff --git a/target/streams/compile/copyResources/_global/streams/out b/target/streams/compile/copyResources/_global/streams/out new file mode 100644 index 00000000..f25042f2 --- /dev/null +++ b/target/streams/compile/copyResources/_global/streams/out @@ -0,0 +1,2 @@ +[debug] Copy resource mappings:  +[debug]   diff --git a/target/streams/compile/dependencyClasspath/_global/streams/export b/target/streams/compile/dependencyClasspath/_global/streams/export new file mode 100644 index 00000000..b39bd53f --- /dev/null +++ b/target/streams/compile/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar diff --git a/target/streams/compile/exportedProductJars/_global/streams/export b/target/streams/compile/exportedProductJars/_global/streams/export new file mode 100644 index 00000000..c08db94c --- /dev/null +++ b/target/streams/compile/exportedProductJars/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/quasar_2.12-3.3.0.jar diff --git a/target/streams/compile/exportedProducts/_global/streams/export b/target/streams/compile/exportedProducts/_global/streams/export new file mode 100644 index 00000000..804ab82b --- /dev/null +++ b/target/streams/compile/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes diff --git a/target/streams/compile/externalDependencyClasspath/_global/streams/export b/target/streams/compile/externalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..b39bd53f --- /dev/null +++ b/target/streams/compile/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/compile/internalDependencyClasspath/_global/streams/export b/target/streams/compile/internalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/compile/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/compile/mainClass/_global/streams/out b/target/streams/compile/mainClass/_global/streams/out new file mode 100644 index 00000000..e69de29b diff --git a/target/streams/compile/managedClasspath/_global/streams/export b/target/streams/compile/managedClasspath/_global/streams/export new file mode 100644 index 00000000..b39bd53f --- /dev/null +++ b/target/streams/compile/managedClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs new file mode 100644 index 00000000..1bc9c111 --- /dev/null +++ b/target/streams/compile/packageBin/_global/streams/inputs @@ -0,0 +1 @@ +1270117725 \ No newline at end of file diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out new file mode 100644 index 00000000..4517f52e --- /dev/null +++ b/target/streams/compile/packageBin/_global/streams/out @@ -0,0 +1,4 @@ +[debug] Packaging /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/quasar_2.12-3.3.0.jar ... +[debug] Input file mappings: +[debug]   +[debug] Done packaging. diff --git a/target/streams/compile/packageBin/_global/streams/output b/target/streams/compile/packageBin/_global/streams/output new file mode 100644 index 00000000..a98b4061 --- /dev/null +++ b/target/streams/compile/packageBin/_global/streams/output @@ -0,0 +1 @@ +894191719 \ No newline at end of file diff --git a/target/streams/compile/unmanagedClasspath/_global/streams/export b/target/streams/compile/unmanagedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/compile/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/compile/unmanagedJars/_global/streams/export b/target/streams/compile/unmanagedJars/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/compile/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export new file mode 100644 index 00000000..07e18363 --- /dev/null +++ b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/runtime/exportedProductJars/_global/streams/export b/target/streams/runtime/exportedProductJars/_global/streams/export new file mode 100644 index 00000000..c08db94c --- /dev/null +++ b/target/streams/runtime/exportedProductJars/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/quasar_2.12-3.3.0.jar diff --git a/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/target/streams/runtime/externalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..b39bd53f --- /dev/null +++ b/target/streams/runtime/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/runtime/fullClasspathAsJars/_global/streams/export b/target/streams/runtime/fullClasspathAsJars/_global/streams/export new file mode 100644 index 00000000..07e18363 --- /dev/null +++ b/target/streams/runtime/fullClasspathAsJars/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/runtime/internalDependencyAsJars/_global/streams/export b/target/streams/runtime/internalDependencyAsJars/_global/streams/export new file mode 100644 index 00000000..c08db94c --- /dev/null +++ b/target/streams/runtime/internalDependencyAsJars/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/quasar_2.12-3.3.0.jar diff --git a/target/streams/runtime/managedClasspath/_global/streams/export b/target/streams/runtime/managedClasspath/_global/streams/export new file mode 100644 index 00000000..b39bd53f --- /dev/null +++ b/target/streams/runtime/managedClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/runtime/unmanagedClasspath/_global/streams/export b/target/streams/runtime/unmanagedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/runtime/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/runtime/unmanagedJars/_global/streams/export b/target/streams/runtime/unmanagedJars/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/runtime/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/test/externalDependencyClasspath/_global/streams/export b/target/streams/test/externalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..b39bd53f --- /dev/null +++ b/target/streams/test/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/test/unmanagedClasspath/_global/streams/export b/target/streams/test/unmanagedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/test/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/test/unmanagedJars/_global/streams/export b/target/streams/test/unmanagedJars/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/test/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ +