Quasar 2.0 Final
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@ -18,9 +18,9 @@ class quasar_bundle extends Bundle with lib{
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val ifu_ahb = new ahb_channel
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val ifu_ahb = new ahb_channel
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val sb_ahb = new ahb_channel
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val sb_ahb = new ahb_channel
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val dma_ahb = new Bundle{
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val dma_ahb = new Bundle{
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val sig = Flipped(new ahb_channel())
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val sig = Flipped(new ahb_channel())
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val hsel = Input(Bool())
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val hsel = Input(Bool())
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val hreadyin = Input(Bool())}
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val hreadyin = Input(Bool())}
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val active_l2clk = Output(Clock())
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val active_l2clk = Output(Clock())
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val free_l2clk = Output(Clock())
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val free_l2clk = Output(Clock())
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@ -63,7 +63,6 @@ class quasar_bundle extends Bundle with lib{
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val dmi_reg_wr_en = Input(Bool())
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val dmi_reg_wr_en = Input(Bool())
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val dmi_reg_wdata = Input(UInt(32.W))
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val dmi_reg_wdata = Input(UInt(32.W))
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val dmi_reg_rdata = Output(UInt(32.W))
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val dmi_reg_rdata = Output(UInt(32.W))
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// val dmi_hard_reset = Input(Bool())
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val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
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val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
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val timer_int = Input(Bool())
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val timer_int = Input(Bool())
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val soft_int = Input(Bool())
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val soft_int = Input(Bool())
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@ -325,4 +324,4 @@ class quasar extends Module with RequireAsyncReset with lib {
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}
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}
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object QUASAR extends App {
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object QUASAR extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
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println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
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}
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}
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