Mask&MatchAdded

src/main/scala/ifu/el2_ifu_ifc_ctrl.scala

@@ -2,7 +2,16 @@ package ifu
 import lib._
 import chisel3._
 import chisel3.util._
-class el2_ifu_ifc_ctrl extends Module with el2_lib {
+class test extends Module with el2_lib {
+  val io = IO (new Bundle{
+    val in1 = Input(UInt(8.W))
+    val in2 = Input(UInt(8.W))
+    val in3 = Input(Bool())
+    val out = Output(UInt(1.W))}
+  )
+  io.out := rvmaskandmatch(io.in1, io.in2, io.in3)
+}
+/*class el2_ifu_ifc_ctrl extends Module with el2_lib {
 val io = IO(new Bundle{
   val free_clk = Input(Bool())
   val active_clk = Input(Bool())
@@ -137,7 +146,7 @@ val io = IO(new Bundle{
   val fb_write_f = RegNext(fb_write_ns, init = 0.U)
   val flush_fb = io.exu_flush_final
   val ifu_pmu_fetch_stall = wfm | (io.ifc_fetch_req_bf_raw & ( (fb_full_f &
-    ~(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
+    ~(io.ifu_fb_consume2 rvrangecheck| io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
 
   io.test1 := dma_iccm_stall_any_f
   io.test2 := dma_stall
@@ -171,7 +180,7 @@ class test extends Module with el2_lib {
   val (range, region) = rvrangecheck(ICCM_SADR, ICCM_SIZE, io.addr)
   io.in_region := region
   io.in_range := range
-}
+}*/
 object ifu_ifc extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctrl()))
+  println((new chisel3.stage.ChiselStage).emitVerilog(new test()))
 }

src/main/scala/lib/el2_lib.scala

@@ -207,6 +207,15 @@ trait el2_lib extends param{
     (in_region, in_range)
   }
 
+  def rvmaskandmatch(mask:UInt, data:UInt, masken:Bool):UInt={
+    val matchvec = Wire(Vec(data.getWidth,UInt(1.W)))
+    val masken_or_fullmask = masken & ~mask.andR
+    matchvec(0)  :=  masken_or_fullmask | (mask(0) === data(0)).asUInt
+    for(i <- 1 to data.getWidth-1)
+    matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt)
+    matchvec.asUInt
+  }
+
   // Move rvecc_encode to a proper trait
   def rvecc_encode(din:UInt) = {   //Done for verification and testing
     val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1)

test.anno.json

@@ -1,16 +1,11 @@
 [
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~test|test>io_in_region",
+    "sink":"~test|test>io_out",
     "sources":[
-      "~test|test>io_addr"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~test|test>io_in_range",
-    "sources":[
-      "~test|test>io_addr"
+      "~test|test>io_in3",
+      "~test|test>io_in1",
+      "~test|test>io_in2"
     ]
   },
   {

test.fir

@@ -3,12 +3,79 @@ circuit test :
   module test : 
     input clock : Clock
     input reset : UInt<1>
-    output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>}
+    output io : {flip in1 : UInt<8>, flip in2 : UInt<8>, flip in3 : UInt<1>, out : UInt<1>}
     
-    node _T = bits(io.addr, 31, 28) @[el2_lib.scala 203:25]
-    node range = eq(_T, UInt<4>("h0e")) @[el2_lib.scala 203:47]
-    node _T_1 = bits(io.addr, 31, 16) @[el2_lib.scala 206:14]
-    node region = eq(_T_1, UInt<16>("h0ee00")) @[el2_lib.scala 206:29]
-    io.in_region <= region @[el2_ifu_ifc_ctrl.scala 142:16]
-    io.in_range <= range @[el2_ifu_ifc_ctrl.scala 143:15]
+    wire _T : UInt<1>[8] @[el2_lib.scala 211:24]
+    node _T_1 = andr(io.in1) @[el2_lib.scala 212:45]
+    node _T_2 = not(_T_1) @[el2_lib.scala 212:39]
+    node _T_3 = and(io.in3, _T_2) @[el2_lib.scala 212:37]
+    node _T_4 = bits(io.in1, 0, 0) @[el2_lib.scala 213:48]
+    node _T_5 = bits(io.in2, 0, 0) @[el2_lib.scala 213:60]
+    node _T_6 = eq(_T_4, _T_5) @[el2_lib.scala 213:52]
+    node _T_7 = or(_T_3, _T_6) @[el2_lib.scala 213:41]
+    _T[0] <= _T_7 @[el2_lib.scala 213:18]
+    node _T_8 = bits(io.in1, 0, 0) @[el2_lib.scala 215:28]
+    node _T_9 = andr(_T_8) @[el2_lib.scala 215:36]
+    node _T_10 = and(_T_9, _T_3) @[el2_lib.scala 215:41]
+    node _T_11 = bits(io.in1, 1, 1) @[el2_lib.scala 215:74]
+    node _T_12 = bits(io.in2, 1, 1) @[el2_lib.scala 215:86]
+    node _T_13 = eq(_T_11, _T_12) @[el2_lib.scala 215:78]
+    node _T_14 = mux(_T_10, UInt<1>("h01"), _T_13) @[el2_lib.scala 215:23]
+    _T[1] <= _T_14 @[el2_lib.scala 215:17]
+    node _T_15 = bits(io.in1, 1, 0) @[el2_lib.scala 215:28]
+    node _T_16 = andr(_T_15) @[el2_lib.scala 215:36]
+    node _T_17 = and(_T_16, _T_3) @[el2_lib.scala 215:41]
+    node _T_18 = bits(io.in1, 2, 2) @[el2_lib.scala 215:74]
+    node _T_19 = bits(io.in2, 2, 2) @[el2_lib.scala 215:86]
+    node _T_20 = eq(_T_18, _T_19) @[el2_lib.scala 215:78]
+    node _T_21 = mux(_T_17, UInt<1>("h01"), _T_20) @[el2_lib.scala 215:23]
+    _T[2] <= _T_21 @[el2_lib.scala 215:17]
+    node _T_22 = bits(io.in1, 2, 0) @[el2_lib.scala 215:28]
+    node _T_23 = andr(_T_22) @[el2_lib.scala 215:36]
+    node _T_24 = and(_T_23, _T_3) @[el2_lib.scala 215:41]
+    node _T_25 = bits(io.in1, 3, 3) @[el2_lib.scala 215:74]
+    node _T_26 = bits(io.in2, 3, 3) @[el2_lib.scala 215:86]
+    node _T_27 = eq(_T_25, _T_26) @[el2_lib.scala 215:78]
+    node _T_28 = mux(_T_24, UInt<1>("h01"), _T_27) @[el2_lib.scala 215:23]
+    _T[3] <= _T_28 @[el2_lib.scala 215:17]
+    node _T_29 = bits(io.in1, 3, 0) @[el2_lib.scala 215:28]
+    node _T_30 = andr(_T_29) @[el2_lib.scala 215:36]
+    node _T_31 = and(_T_30, _T_3) @[el2_lib.scala 215:41]
+    node _T_32 = bits(io.in1, 4, 4) @[el2_lib.scala 215:74]
+    node _T_33 = bits(io.in2, 4, 4) @[el2_lib.scala 215:86]
+    node _T_34 = eq(_T_32, _T_33) @[el2_lib.scala 215:78]
+    node _T_35 = mux(_T_31, UInt<1>("h01"), _T_34) @[el2_lib.scala 215:23]
+    _T[4] <= _T_35 @[el2_lib.scala 215:17]
+    node _T_36 = bits(io.in1, 4, 0) @[el2_lib.scala 215:28]
+    node _T_37 = andr(_T_36) @[el2_lib.scala 215:36]
+    node _T_38 = and(_T_37, _T_3) @[el2_lib.scala 215:41]
+    node _T_39 = bits(io.in1, 5, 5) @[el2_lib.scala 215:74]
+    node _T_40 = bits(io.in2, 5, 5) @[el2_lib.scala 215:86]
+    node _T_41 = eq(_T_39, _T_40) @[el2_lib.scala 215:78]
+    node _T_42 = mux(_T_38, UInt<1>("h01"), _T_41) @[el2_lib.scala 215:23]
+    _T[5] <= _T_42 @[el2_lib.scala 215:17]
+    node _T_43 = bits(io.in1, 5, 0) @[el2_lib.scala 215:28]
+    node _T_44 = andr(_T_43) @[el2_lib.scala 215:36]
+    node _T_45 = and(_T_44, _T_3) @[el2_lib.scala 215:41]
+    node _T_46 = bits(io.in1, 6, 6) @[el2_lib.scala 215:74]
+    node _T_47 = bits(io.in2, 6, 6) @[el2_lib.scala 215:86]
+    node _T_48 = eq(_T_46, _T_47) @[el2_lib.scala 215:78]
+    node _T_49 = mux(_T_45, UInt<1>("h01"), _T_48) @[el2_lib.scala 215:23]
+    _T[6] <= _T_49 @[el2_lib.scala 215:17]
+    node _T_50 = bits(io.in1, 6, 0) @[el2_lib.scala 215:28]
+    node _T_51 = andr(_T_50) @[el2_lib.scala 215:36]
+    node _T_52 = and(_T_51, _T_3) @[el2_lib.scala 215:41]
+    node _T_53 = bits(io.in1, 7, 7) @[el2_lib.scala 215:74]
+    node _T_54 = bits(io.in2, 7, 7) @[el2_lib.scala 215:86]
+    node _T_55 = eq(_T_53, _T_54) @[el2_lib.scala 215:78]
+    node _T_56 = mux(_T_52, UInt<1>("h01"), _T_55) @[el2_lib.scala 215:23]
+    _T[7] <= _T_56 @[el2_lib.scala 215:17]
+    node _T_57 = cat(_T[1], _T[0]) @[el2_lib.scala 216:14]
+    node _T_58 = cat(_T[3], _T[2]) @[el2_lib.scala 216:14]
+    node _T_59 = cat(_T_58, _T_57) @[el2_lib.scala 216:14]
+    node _T_60 = cat(_T[5], _T[4]) @[el2_lib.scala 216:14]
+    node _T_61 = cat(_T[7], _T[6]) @[el2_lib.scala 216:14]
+    node _T_62 = cat(_T_61, _T_60) @[el2_lib.scala 216:14]
+    node _T_63 = cat(_T_62, _T_59) @[el2_lib.scala 216:14]
+    io.out <= _T_63 @[el2_ifu_ifc_ctrl.scala 12:10]
     

test.v

@@ -1,10 +1,44 @@
 module test(
   input        clock,
   input        reset,
-  input  [31:0] io_addr,
-  output        io_in_range,
-  output        io_in_region
+  input  [7:0] io_in1,
+  input  [7:0] io_in2,
+  input        io_in3,
+  output       io_out
 );
-  assign io_in_range = io_addr[31:28] == 4'he; // @[el2_ifu_ifc_ctrl.scala 143:15]
-  assign io_in_region = io_addr[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 142:16]
+  wire  _T_1 = &io_in1; // @[el2_lib.scala 212:45]
+  wire  _T_2 = ~_T_1; // @[el2_lib.scala 212:39]
+  wire  _T_3 = io_in3 & _T_2; // @[el2_lib.scala 212:37]
+  wire  _T_6 = io_in1[0] == io_in2[0]; // @[el2_lib.scala 213:52]
+  wire  _T_7 = _T_3 | _T_6; // @[el2_lib.scala 213:41]
+  wire  _T_9 = &io_in1[0]; // @[el2_lib.scala 215:36]
+  wire  _T_10 = _T_9 & _T_3; // @[el2_lib.scala 215:41]
+  wire  _T_13 = io_in1[1] == io_in2[1]; // @[el2_lib.scala 215:78]
+  wire  _T_14 = _T_10 | _T_13; // @[el2_lib.scala 215:23]
+  wire  _T_16 = &io_in1[1:0]; // @[el2_lib.scala 215:36]
+  wire  _T_17 = _T_16 & _T_3; // @[el2_lib.scala 215:41]
+  wire  _T_20 = io_in1[2] == io_in2[2]; // @[el2_lib.scala 215:78]
+  wire  _T_21 = _T_17 | _T_20; // @[el2_lib.scala 215:23]
+  wire  _T_23 = &io_in1[2:0]; // @[el2_lib.scala 215:36]
+  wire  _T_24 = _T_23 & _T_3; // @[el2_lib.scala 215:41]
+  wire  _T_27 = io_in1[3] == io_in2[3]; // @[el2_lib.scala 215:78]
+  wire  _T_28 = _T_24 | _T_27; // @[el2_lib.scala 215:23]
+  wire  _T_30 = &io_in1[3:0]; // @[el2_lib.scala 215:36]
+  wire  _T_31 = _T_30 & _T_3; // @[el2_lib.scala 215:41]
+  wire  _T_34 = io_in1[4] == io_in2[4]; // @[el2_lib.scala 215:78]
+  wire  _T_35 = _T_31 | _T_34; // @[el2_lib.scala 215:23]
+  wire  _T_37 = &io_in1[4:0]; // @[el2_lib.scala 215:36]
+  wire  _T_38 = _T_37 & _T_3; // @[el2_lib.scala 215:41]
+  wire  _T_41 = io_in1[5] == io_in2[5]; // @[el2_lib.scala 215:78]
+  wire  _T_42 = _T_38 | _T_41; // @[el2_lib.scala 215:23]
+  wire  _T_44 = &io_in1[5:0]; // @[el2_lib.scala 215:36]
+  wire  _T_45 = _T_44 & _T_3; // @[el2_lib.scala 215:41]
+  wire  _T_48 = io_in1[6] == io_in2[6]; // @[el2_lib.scala 215:78]
+  wire  _T_49 = _T_45 | _T_48; // @[el2_lib.scala 215:23]
+  wire  _T_51 = &io_in1[6:0]; // @[el2_lib.scala 215:36]
+  wire  _T_52 = _T_51 & _T_3; // @[el2_lib.scala 215:41]
+  wire  _T_55 = io_in1[7] == io_in2[7]; // @[el2_lib.scala 215:78]
+  wire  _T_56 = _T_52 | _T_55; // @[el2_lib.scala 215:23]
+  wire [7:0] _T_63 = {_T_56,_T_49,_T_42,_T_35,_T_28,_T_21,_T_14,_T_7}; // @[el2_lib.scala 216:14]
+  assign io_out = _T_63[0]; // @[el2_ifu_ifc_ctrl.scala 12:10]
 endmodule