diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index edc53b1b..8ddad915 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1 +1,3 @@ -/home/waleedbinehsan/Downloads/Quasar/gated_latch.v \ No newline at end of file +/home/waleedbinehsan/Downloads/Quasar/gated_latch.v +/home/waleedbinehsan/Downloads/Quasar/dmi_wrapper.sv +/home/waleedbinehsan/Downloads/Quasar/mem.sv \ No newline at end of file diff --git a/quasar.anno.json b/quasar.anno.json index 530fe620..45c5a322 100644 --- a/quasar.anno.json +++ b/quasar.anno.json @@ -1237,6 +1237,10 @@ "class":"firrtl.transforms.DontTouchAnnotation", "target":"~quasar|dec_trigger>io_dec_i0_trigger_match_d" }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~quasar|csr_tlu>_T_755" + }, { "class":"firrtl.options.TargetDirAnnotation", "directory":"." diff --git a/quasar.fir b/quasar.fir index b71b5159..bc4ad73e 100644 --- a/quasar.fir +++ b/quasar.fir @@ -71626,32 +71626,32 @@ circuit quasar : mitcnt1 <= UInt<1>("h00") wire mitcnt0 : UInt<32> mitcnt0 <= UInt<1>("h00") - node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2672:36] - node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2673:36] - io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2675:31] - io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2676:31] - node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2683:72] - node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2683:49] - node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2685:37] - node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2685:56] - node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2685:85] - node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2685:76] - node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2685:53] - node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2685:112] - node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2685:147] - node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2685:138] - node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2685:109] - node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2685:173] - node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2685:171] - node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2686:35] - node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2686:35] - node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2687:44] - node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2687:74] - node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2687:60] - node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2687:29] - node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2688:59] - node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2688:76] - node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2688:93] + node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2673:36] + node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2674:36] + io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2676:31] + io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2677:31] + node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2684:72] + node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2684:49] + node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2686:37] + node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2686:56] + node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2686:85] + node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2686:76] + node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2686:53] + node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2686:112] + node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2686:147] + node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2686:138] + node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2686:109] + node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2686:173] + node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2686:171] + node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2687:35] + node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2687:35] + node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2688:44] + node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2688:74] + node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2688:60] + node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2688:29] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2689:59] + node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2689:76] + node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2689:93] inst rvclkhdr of rvclkhdr_712 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -71660,34 +71660,34 @@ circuit quasar : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_18 <= mitcnt0_ns @[lib.scala 374:16] - mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2688:25] - node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2695:72] - node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2695:49] - node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2697:37] - node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2697:56] - node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2697:85] - node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2697:76] - node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2697:53] - node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2697:112] - node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2697:147] - node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2697:138] - node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2697:109] - node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2697:173] - node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2697:171] + mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2689:25] + node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2696:72] + node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2696:49] + node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2698:37] + node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2698:56] + node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2698:85] + node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2698:76] + node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2698:53] + node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2698:112] + node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2698:147] + node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2698:138] + node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2698:109] + node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2698:173] + node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2698:171] node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2700:68] - node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2700:60] - node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2700:72] + node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2701:68] + node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2701:60] + node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2701:72] node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58] - node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2700:35] - node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2700:35] - node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2701:45] - node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2701:75] - node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2701:61] - node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2701:30] - node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2702:60] - node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2702:77] - node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2702:94] + node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2701:35] + node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2701:35] + node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2702:45] + node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2702:75] + node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2702:61] + node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2702:30] + node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2703:60] + node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2703:77] + node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2703:94] inst rvclkhdr_1 of rvclkhdr_713 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -71696,11 +71696,11 @@ circuit quasar : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_42 <= mitcnt1_ns @[lib.scala 374:16] - mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2702:25] - node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2709:70] - node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2709:47] - node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2710:38] - node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2710:71] + mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2703:25] + node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2710:70] + node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2710:47] + node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2711:38] + node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2711:71] inst rvclkhdr_2 of rvclkhdr_714 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -71709,12 +71709,12 @@ circuit quasar : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mitb0_b <= _T_44 @[lib.scala 374:16] - node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2711:22] - mitb0 <= _T_46 @[dec_tlu_ctl.scala 2711:19] - node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2718:69] - node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2718:47] - node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2719:29] - node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2719:62] + node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2712:22] + mitb0 <= _T_46 @[dec_tlu_ctl.scala 2712:19] + node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2719:69] + node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2719:47] + node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2720:29] + node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2720:62] inst rvclkhdr_3 of rvclkhdr_715 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -71723,55 +71723,55 @@ circuit quasar : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mitb1_b <= _T_48 @[lib.scala 374:16] - node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2720:18] - mitb1 <= _T_50 @[dec_tlu_ctl.scala 2720:15] - node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2731:72] - node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2731:49] - node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2732:45] - node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2732:72] - node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2732:86] - node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2732:31] - node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2734:41] - node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2734:30] - reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2735:60] - mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2735:60] - node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2736:78] - reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2736:67] - _T_57 <= _T_56 @[dec_tlu_ctl.scala 2736:67] - node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2736:90] + node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2721:18] + mitb1 <= _T_50 @[dec_tlu_ctl.scala 2721:15] + node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2732:72] + node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2732:49] + node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2733:45] + node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2733:72] + node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2733:86] + node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2733:31] + node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2735:41] + node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2735:30] + reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2736:60] + mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2736:60] + node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2737:78] + reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2737:67] + _T_57 <= _T_56 @[dec_tlu_ctl.scala 2737:67] + node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2737:90] node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58] - mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2736:31] - node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2746:71] - node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2746:49] - node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2747:45] - node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2747:71] - node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2747:85] - node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2747:31] - node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2748:40] - node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2748:29] - reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2749:55] - mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2749:55] - node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2750:63] - reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2750:52] - _T_66 <= _T_65 @[dec_tlu_ctl.scala 2750:52] - node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2750:75] + mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2737:31] + node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2747:71] + node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2747:49] + node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2748:45] + node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2748:71] + node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2748:85] + node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2748:31] + node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2749:40] + node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2749:29] + reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2750:55] + mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2750:55] + node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2751:63] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2751:52] + _T_66 <= _T_65 @[dec_tlu_ctl.scala 2751:52] + node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2751:75] node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58] - mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2750:16] - node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2752:51] - node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2752:68] - node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2752:83] - node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2752:98] - node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2752:115] - io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2752:33] - node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2754:25] - node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2754:44] - node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2755:32] - node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2756:30] - node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2757:30] - node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2758:32] + mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2751:16] + node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2753:51] + node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2753:68] + node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2753:83] + node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2753:98] + node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2753:115] + io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2753:33] + node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2755:25] + node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2755:44] + node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2756:32] + node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2757:30] + node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2758:30] + node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2759:32] node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58] - node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2759:32] + node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2760:32] node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58] node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72] @@ -71787,7 +71787,7 @@ circuit quasar : node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72] wire _T_96 : UInt<32> @[Mux.scala 27:72] _T_96 <= _T_95 @[Mux.scala 27:72] - io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2753:33] + io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2754:33] extmodule gated_latch_716 : output Q : Clock @@ -73963,621 +73963,621 @@ circuit quasar : node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2126:100] node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2126:71] node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2128:34] - node _T_754 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2128:61] - node _T_755 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2128:91] - node _T_756 = mux(_T_753, _T_754, _T_755) @[dec_tlu_ctl.scala 2128:21] - node _T_757 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2130:78] - node _T_758 = bits(_T_757, 0, 0) @[dec_tlu_ctl.scala 2130:111] - reg _T_759 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_758 : @[Reg.scala 28:19] - _T_759 <= _T_756 @[Reg.scala 28:23] + node _T_754 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2128:86] + node _T_755 = mux(_T_753, io.dec_csr_wrdata_r, _T_754) @[dec_tlu_ctl.scala 2128:21] + node _T_756 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2131:78] + node _T_757 = bits(_T_756, 0, 0) @[dec_tlu_ctl.scala 2131:111] + reg _T_758 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_757 : @[Reg.scala 28:19] + _T_758 <= _T_755 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_748 <= _T_759 @[dec_tlu_ctl.scala 2130:13] - node _T_760 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] - dicad1 <= _T_760 @[dec_tlu_ctl.scala 2131:9] - node _T_761 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2153:69] - node _T_762 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2153:83] - node _T_763 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2153:97] - node _T_764 = cat(_T_761, _T_762) @[Cat.scala 29:58] - node _T_765 = cat(_T_764, _T_763) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_765 @[dec_tlu_ctl.scala 2153:56] - io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2156:41] - node _T_766 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2158:52] - node _T_767 = and(_T_766, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2158:75] - node _T_768 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2158:98] - node _T_769 = and(_T_767, _T_768) @[dec_tlu_ctl.scala 2158:96] - node _T_770 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2158:142] - node _T_771 = eq(_T_770, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2158:149] - node icache_rd_valid = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2158:120] - node _T_772 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2159:52] - node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2159:97] - node _T_774 = eq(_T_773, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:104] - node icache_wr_valid = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2159:75] - reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2161:58] - icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2161:58] - reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2162:58] - icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2162:58] - io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2164:41] - io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2165:41] - node _T_775 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2173:62] - node _T_776 = eq(_T_775, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2173:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_776) @[dec_tlu_ctl.scala 2173:40] - node _T_777 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2174:32] - node _T_778 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2174:59] - node mtsel_ns = mux(_T_777, _T_778, mtsel) @[dec_tlu_ctl.scala 2174:20] - reg _T_779 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2176:43] - _T_779 <= mtsel_ns @[dec_tlu_ctl.scala 2176:43] - mtsel <= _T_779 @[dec_tlu_ctl.scala 2176:8] - node _T_780 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2211:38] - node _T_781 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2211:64] - node _T_782 = not(_T_781) @[dec_tlu_ctl.scala 2211:44] - node tdata_load = and(_T_780, _T_782) @[dec_tlu_ctl.scala 2211:42] - node _T_783 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2213:40] - node _T_784 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:66] - node _T_785 = not(_T_784) @[dec_tlu_ctl.scala 2213:46] - node tdata_opcode = and(_T_783, _T_785) @[dec_tlu_ctl.scala 2213:44] - node _T_786 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2215:41] - node _T_787 = and(_T_786, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2215:46] - node _T_788 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2215:90] - node tdata_action = and(_T_787, _T_788) @[dec_tlu_ctl.scala 2215:69] - node _T_789 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:47] - node _T_790 = and(_T_789, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:52] - node _T_791 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2217:94] - node _T_792 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2217:136] - node _T_793 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2218:43] - node _T_794 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2218:83] - node _T_795 = cat(_T_794, tdata_load) @[Cat.scala 29:58] - node _T_796 = cat(_T_793, tdata_opcode) @[Cat.scala 29:58] - node _T_797 = cat(_T_796, _T_795) @[Cat.scala 29:58] - node _T_798 = cat(tdata_action, _T_792) @[Cat.scala 29:58] - node _T_799 = cat(_T_790, _T_791) @[Cat.scala 29:58] - node _T_800 = cat(_T_799, _T_798) @[Cat.scala 29:58] - node tdata_wrdata_r = cat(_T_800, _T_797) @[Cat.scala 29:58] - node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] - node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] - node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2221:70] - node _T_804 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2221:121] - node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2221:112] - node _T_806 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2221:154] - node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2221:138] - node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] - node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2221:135] - node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] - node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] - node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2221:70] - node _T_813 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2221:121] - node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2221:112] - node _T_815 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2221:154] - node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2221:138] - node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] - node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2221:135] - node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] - node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] - node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2221:70] - node _T_822 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2221:121] - node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2221:112] - node _T_824 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2221:154] - node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2221:138] - node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] - node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2221:135] - node _T_828 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] - node _T_829 = eq(_T_828, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] - node _T_830 = and(io.dec_csr_wen_r_mod, _T_829) @[dec_tlu_ctl.scala 2221:70] - node _T_831 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2221:121] - node _T_832 = and(_T_830, _T_831) @[dec_tlu_ctl.scala 2221:112] - node _T_833 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2221:154] - node _T_834 = not(_T_833) @[dec_tlu_ctl.scala 2221:138] - node _T_835 = or(_T_834, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] - node _T_836 = and(_T_832, _T_835) @[dec_tlu_ctl.scala 2221:135] - wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2221:42] - wr_mtdata1_t_r[0] <= _T_809 @[dec_tlu_ctl.scala 2221:42] - wr_mtdata1_t_r[1] <= _T_818 @[dec_tlu_ctl.scala 2221:42] - wr_mtdata1_t_r[2] <= _T_827 @[dec_tlu_ctl.scala 2221:42] - wr_mtdata1_t_r[3] <= _T_836 @[dec_tlu_ctl.scala 2221:42] - node _T_837 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2222:68] - node _T_838 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:111] - node _T_839 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2222:135] - node _T_840 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2222:156] - node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2222:139] - node _T_842 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2222:176] - node _T_843 = cat(_T_838, _T_841) @[Cat.scala 29:58] - node _T_844 = cat(_T_843, _T_842) @[Cat.scala 29:58] - node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2222:49] - node _T_846 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2222:68] - node _T_847 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:111] - node _T_848 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2222:135] - node _T_849 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2222:156] - node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2222:139] - node _T_851 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2222:176] - node _T_852 = cat(_T_847, _T_850) @[Cat.scala 29:58] - node _T_853 = cat(_T_852, _T_851) @[Cat.scala 29:58] - node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2222:49] - node _T_855 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2222:68] - node _T_856 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:111] - node _T_857 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2222:135] - node _T_858 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2222:156] - node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2222:139] - node _T_860 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2222:176] - node _T_861 = cat(_T_856, _T_859) @[Cat.scala 29:58] - node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58] - node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2222:49] - node _T_864 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2222:68] - node _T_865 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:111] - node _T_866 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2222:135] - node _T_867 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2222:156] - node _T_868 = or(_T_866, _T_867) @[dec_tlu_ctl.scala 2222:139] - node _T_869 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2222:176] - node _T_870 = cat(_T_865, _T_868) @[Cat.scala 29:58] - node _T_871 = cat(_T_870, _T_869) @[Cat.scala 29:58] - node _T_872 = mux(_T_864, tdata_wrdata_r, _T_871) @[dec_tlu_ctl.scala 2222:49] - wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2222:40] - mtdata1_t_ns[0] <= _T_845 @[dec_tlu_ctl.scala 2222:40] - mtdata1_t_ns[1] <= _T_854 @[dec_tlu_ctl.scala 2222:40] - mtdata1_t_ns[2] <= _T_863 @[dec_tlu_ctl.scala 2222:40] - mtdata1_t_ns[3] <= _T_872 @[dec_tlu_ctl.scala 2222:40] - reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] - _T_873 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2224:74] - io.mtdata1_t[0] <= _T_873 @[dec_tlu_ctl.scala 2224:39] - reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] - _T_874 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2224:74] - io.mtdata1_t[1] <= _T_874 @[dec_tlu_ctl.scala 2224:39] - reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] - _T_875 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2224:74] - io.mtdata1_t[2] <= _T_875 @[dec_tlu_ctl.scala 2224:39] - reg _T_876 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] - _T_876 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2224:74] - io.mtdata1_t[3] <= _T_876 @[dec_tlu_ctl.scala 2224:39] - node _T_877 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2227:58] - node _T_878 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2227:104] - node _T_879 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2227:142] - node _T_880 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2227:174] - node _T_881 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2227:206] - node _T_882 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2227:238] - node _T_883 = cat(UInt<3>("h00"), _T_882) @[Cat.scala 29:58] - node _T_884 = cat(_T_880, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_885 = cat(_T_884, _T_881) @[Cat.scala 29:58] - node _T_886 = cat(_T_885, _T_883) @[Cat.scala 29:58] - node _T_887 = cat(_T_879, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_888 = cat(UInt<4>("h02"), _T_878) @[Cat.scala 29:58] - node _T_889 = cat(_T_888, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_890 = cat(_T_889, _T_887) @[Cat.scala 29:58] - node _T_891 = cat(_T_890, _T_886) @[Cat.scala 29:58] - node _T_892 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2227:58] - node _T_893 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2227:104] - node _T_894 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2227:142] - node _T_895 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2227:174] - node _T_896 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2227:206] - node _T_897 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2227:238] - node _T_898 = cat(UInt<3>("h00"), _T_897) @[Cat.scala 29:58] - node _T_899 = cat(_T_895, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_900 = cat(_T_899, _T_896) @[Cat.scala 29:58] - node _T_901 = cat(_T_900, _T_898) @[Cat.scala 29:58] - node _T_902 = cat(_T_894, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_903 = cat(UInt<4>("h02"), _T_893) @[Cat.scala 29:58] - node _T_904 = cat(_T_903, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_905 = cat(_T_904, _T_902) @[Cat.scala 29:58] - node _T_906 = cat(_T_905, _T_901) @[Cat.scala 29:58] - node _T_907 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2227:58] - node _T_908 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2227:104] - node _T_909 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2227:142] - node _T_910 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2227:174] - node _T_911 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2227:206] - node _T_912 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2227:238] - node _T_913 = cat(UInt<3>("h00"), _T_912) @[Cat.scala 29:58] - node _T_914 = cat(_T_910, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_915 = cat(_T_914, _T_911) @[Cat.scala 29:58] - node _T_916 = cat(_T_915, _T_913) @[Cat.scala 29:58] - node _T_917 = cat(_T_909, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_918 = cat(UInt<4>("h02"), _T_908) @[Cat.scala 29:58] - node _T_919 = cat(_T_918, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_920 = cat(_T_919, _T_917) @[Cat.scala 29:58] - node _T_921 = cat(_T_920, _T_916) @[Cat.scala 29:58] - node _T_922 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2227:58] - node _T_923 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2227:104] - node _T_924 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2227:142] - node _T_925 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2227:174] - node _T_926 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2227:206] - node _T_927 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2227:238] - node _T_928 = cat(UInt<3>("h00"), _T_927) @[Cat.scala 29:58] - node _T_929 = cat(_T_925, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_930 = cat(_T_929, _T_926) @[Cat.scala 29:58] - node _T_931 = cat(_T_930, _T_928) @[Cat.scala 29:58] - node _T_932 = cat(_T_924, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_933 = cat(UInt<4>("h02"), _T_923) @[Cat.scala 29:58] - node _T_934 = cat(_T_933, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_935 = cat(_T_934, _T_932) @[Cat.scala 29:58] - node _T_936 = cat(_T_935, _T_931) @[Cat.scala 29:58] - node _T_937 = mux(_T_877, _T_891, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_938 = mux(_T_892, _T_906, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_939 = mux(_T_907, _T_921, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_940 = mux(_T_922, _T_936, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_941 = or(_T_937, _T_938) @[Mux.scala 27:72] + _T_748 <= _T_758 @[dec_tlu_ctl.scala 2131:13] + node _T_759 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] + dicad1 <= _T_759 @[dec_tlu_ctl.scala 2132:9] + node _T_760 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2154:69] + node _T_761 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2154:83] + node _T_762 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2154:97] + node _T_763 = cat(_T_760, _T_761) @[Cat.scala 29:58] + node _T_764 = cat(_T_763, _T_762) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_764 @[dec_tlu_ctl.scala 2154:56] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2157:41] + node _T_765 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2159:52] + node _T_766 = and(_T_765, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2159:75] + node _T_767 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2159:98] + node _T_768 = and(_T_766, _T_767) @[dec_tlu_ctl.scala 2159:96] + node _T_769 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2159:142] + node _T_770 = eq(_T_769, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:149] + node icache_rd_valid = and(_T_768, _T_770) @[dec_tlu_ctl.scala 2159:120] + node _T_771 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2160:52] + node _T_772 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2160:97] + node _T_773 = eq(_T_772, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:104] + node icache_wr_valid = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2160:75] + reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2162:58] + icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2162:58] + reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2163:58] + icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2163:58] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2165:41] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2166:41] + node _T_774 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2174:62] + node _T_775 = eq(_T_774, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2174:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_775) @[dec_tlu_ctl.scala 2174:40] + node _T_776 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2175:32] + node _T_777 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2175:59] + node mtsel_ns = mux(_T_776, _T_777, mtsel) @[dec_tlu_ctl.scala 2175:20] + reg _T_778 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2177:43] + _T_778 <= mtsel_ns @[dec_tlu_ctl.scala 2177:43] + mtsel <= _T_778 @[dec_tlu_ctl.scala 2177:8] + node _T_779 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2212:38] + node _T_780 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2212:64] + node _T_781 = not(_T_780) @[dec_tlu_ctl.scala 2212:44] + node tdata_load = and(_T_779, _T_781) @[dec_tlu_ctl.scala 2212:42] + node _T_782 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2214:40] + node _T_783 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2214:66] + node _T_784 = not(_T_783) @[dec_tlu_ctl.scala 2214:46] + node tdata_opcode = and(_T_782, _T_784) @[dec_tlu_ctl.scala 2214:44] + node _T_785 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2216:41] + node _T_786 = and(_T_785, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2216:46] + node _T_787 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2216:90] + node tdata_action = and(_T_786, _T_787) @[dec_tlu_ctl.scala 2216:69] + node _T_788 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2218:47] + node _T_789 = and(_T_788, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:52] + node _T_790 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2218:94] + node _T_791 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2218:136] + node _T_792 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2219:43] + node _T_793 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2219:83] + node _T_794 = cat(_T_793, tdata_load) @[Cat.scala 29:58] + node _T_795 = cat(_T_792, tdata_opcode) @[Cat.scala 29:58] + node _T_796 = cat(_T_795, _T_794) @[Cat.scala 29:58] + node _T_797 = cat(tdata_action, _T_791) @[Cat.scala 29:58] + node _T_798 = cat(_T_789, _T_790) @[Cat.scala 29:58] + node _T_799 = cat(_T_798, _T_797) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_799, _T_796) @[Cat.scala 29:58] + node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2222:70] + node _T_803 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2222:121] + node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2222:112] + node _T_805 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2222:138] + node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2222:135] + node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2222:70] + node _T_812 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2222:121] + node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2222:112] + node _T_814 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2222:138] + node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2222:135] + node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2222:70] + node _T_821 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2222:121] + node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2222:112] + node _T_823 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2222:138] + node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2222:135] + node _T_827 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_828 = eq(_T_827, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_829 = and(io.dec_csr_wen_r_mod, _T_828) @[dec_tlu_ctl.scala 2222:70] + node _T_830 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2222:121] + node _T_831 = and(_T_829, _T_830) @[dec_tlu_ctl.scala 2222:112] + node _T_832 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_833 = not(_T_832) @[dec_tlu_ctl.scala 2222:138] + node _T_834 = or(_T_833, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_835 = and(_T_831, _T_834) @[dec_tlu_ctl.scala 2222:135] + wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[0] <= _T_808 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[1] <= _T_817 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[2] <= _T_826 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[3] <= _T_835 @[dec_tlu_ctl.scala 2222:42] + node _T_836 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_837 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_838 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2223:135] + node _T_839 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2223:139] + node _T_841 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58] + node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58] + node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2223:49] + node _T_845 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_846 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_847 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2223:135] + node _T_848 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2223:139] + node _T_850 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58] + node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58] + node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2223:49] + node _T_854 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_855 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_856 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2223:135] + node _T_857 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2223:139] + node _T_859 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58] + node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58] + node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2223:49] + node _T_863 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_864 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_865 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2223:135] + node _T_866 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_867 = or(_T_865, _T_866) @[dec_tlu_ctl.scala 2223:139] + node _T_868 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_869 = cat(_T_864, _T_867) @[Cat.scala 29:58] + node _T_870 = cat(_T_869, _T_868) @[Cat.scala 29:58] + node _T_871 = mux(_T_863, tdata_wrdata_r, _T_870) @[dec_tlu_ctl.scala 2223:49] + wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[0] <= _T_844 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[1] <= _T_853 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[2] <= _T_862 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[3] <= _T_871 @[dec_tlu_ctl.scala 2223:40] + reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_872 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[0] <= _T_872 @[dec_tlu_ctl.scala 2225:39] + reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_873 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[1] <= _T_873 @[dec_tlu_ctl.scala 2225:39] + reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_874 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[2] <= _T_874 @[dec_tlu_ctl.scala 2225:39] + reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_875 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[3] <= _T_875 @[dec_tlu_ctl.scala 2225:39] + node _T_876 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2228:58] + node _T_877 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_878 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_879 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_880 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_881 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_882 = cat(UInt<3>("h00"), _T_881) @[Cat.scala 29:58] + node _T_883 = cat(_T_879, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_884 = cat(_T_883, _T_880) @[Cat.scala 29:58] + node _T_885 = cat(_T_884, _T_882) @[Cat.scala 29:58] + node _T_886 = cat(_T_878, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_887 = cat(UInt<4>("h02"), _T_877) @[Cat.scala 29:58] + node _T_888 = cat(_T_887, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_886) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_885) @[Cat.scala 29:58] + node _T_891 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2228:58] + node _T_892 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_893 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_894 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_895 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_896 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_897 = cat(UInt<3>("h00"), _T_896) @[Cat.scala 29:58] + node _T_898 = cat(_T_894, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_899 = cat(_T_898, _T_895) @[Cat.scala 29:58] + node _T_900 = cat(_T_899, _T_897) @[Cat.scala 29:58] + node _T_901 = cat(_T_893, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_902 = cat(UInt<4>("h02"), _T_892) @[Cat.scala 29:58] + node _T_903 = cat(_T_902, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_901) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_900) @[Cat.scala 29:58] + node _T_906 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2228:58] + node _T_907 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_908 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_909 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_910 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_911 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_912 = cat(UInt<3>("h00"), _T_911) @[Cat.scala 29:58] + node _T_913 = cat(_T_909, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_914 = cat(_T_913, _T_910) @[Cat.scala 29:58] + node _T_915 = cat(_T_914, _T_912) @[Cat.scala 29:58] + node _T_916 = cat(_T_908, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_917 = cat(UInt<4>("h02"), _T_907) @[Cat.scala 29:58] + node _T_918 = cat(_T_917, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, _T_916) @[Cat.scala 29:58] + node _T_920 = cat(_T_919, _T_915) @[Cat.scala 29:58] + node _T_921 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2228:58] + node _T_922 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_923 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_924 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_925 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_926 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_927 = cat(UInt<3>("h00"), _T_926) @[Cat.scala 29:58] + node _T_928 = cat(_T_924, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_929 = cat(_T_928, _T_925) @[Cat.scala 29:58] + node _T_930 = cat(_T_929, _T_927) @[Cat.scala 29:58] + node _T_931 = cat(_T_923, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_932 = cat(UInt<4>("h02"), _T_922) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] + node _T_935 = cat(_T_934, _T_930) @[Cat.scala 29:58] + node _T_936 = mux(_T_876, _T_890, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_937 = mux(_T_891, _T_905, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_906, _T_920, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = mux(_T_921, _T_935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_940 = or(_T_936, _T_937) @[Mux.scala 27:72] + node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72] - node _T_943 = or(_T_942, _T_940) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata1_tsel_out <= _T_943 @[Mux.scala 27:72] - node _T_944 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2229:58] - io.trigger_pkt_any[0].select <= _T_944 @[dec_tlu_ctl.scala 2229:40] - node _T_945 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2230:61] - io.trigger_pkt_any[0].match_pkt <= _T_945 @[dec_tlu_ctl.scala 2230:43] - node _T_946 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[0].store <= _T_946 @[dec_tlu_ctl.scala 2231:40] - node _T_947 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[0].load <= _T_947 @[dec_tlu_ctl.scala 2232:40] - node _T_948 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[0].execute <= _T_948 @[dec_tlu_ctl.scala 2233:40] - node _T_949 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[0].m <= _T_949 @[dec_tlu_ctl.scala 2234:40] - node _T_950 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2229:58] - io.trigger_pkt_any[1].select <= _T_950 @[dec_tlu_ctl.scala 2229:40] - node _T_951 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2230:61] - io.trigger_pkt_any[1].match_pkt <= _T_951 @[dec_tlu_ctl.scala 2230:43] - node _T_952 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[1].store <= _T_952 @[dec_tlu_ctl.scala 2231:40] - node _T_953 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[1].load <= _T_953 @[dec_tlu_ctl.scala 2232:40] - node _T_954 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[1].execute <= _T_954 @[dec_tlu_ctl.scala 2233:40] - node _T_955 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[1].m <= _T_955 @[dec_tlu_ctl.scala 2234:40] - node _T_956 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2229:58] - io.trigger_pkt_any[2].select <= _T_956 @[dec_tlu_ctl.scala 2229:40] - node _T_957 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2230:61] - io.trigger_pkt_any[2].match_pkt <= _T_957 @[dec_tlu_ctl.scala 2230:43] - node _T_958 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[2].store <= _T_958 @[dec_tlu_ctl.scala 2231:40] - node _T_959 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[2].load <= _T_959 @[dec_tlu_ctl.scala 2232:40] - node _T_960 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[2].execute <= _T_960 @[dec_tlu_ctl.scala 2233:40] - node _T_961 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[2].m <= _T_961 @[dec_tlu_ctl.scala 2234:40] - node _T_962 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2229:58] - io.trigger_pkt_any[3].select <= _T_962 @[dec_tlu_ctl.scala 2229:40] - node _T_963 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2230:61] - io.trigger_pkt_any[3].match_pkt <= _T_963 @[dec_tlu_ctl.scala 2230:43] - node _T_964 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[3].store <= _T_964 @[dec_tlu_ctl.scala 2231:40] - node _T_965 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[3].load <= _T_965 @[dec_tlu_ctl.scala 2232:40] - node _T_966 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[3].execute <= _T_966 @[dec_tlu_ctl.scala 2233:40] - node _T_967 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[3].m <= _T_967 @[dec_tlu_ctl.scala 2234:40] - node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] - node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] - node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2241:69] - node _T_971 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2241:120] - node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2241:111] - node _T_973 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2241:153] - node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2241:137] - node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] - node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2241:134] - node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] - node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] - node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2241:69] - node _T_980 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2241:120] - node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2241:111] - node _T_982 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2241:153] - node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2241:137] - node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] - node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2241:134] - node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] - node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] - node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2241:69] - node _T_989 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2241:120] - node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2241:111] - node _T_991 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2241:153] - node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2241:137] - node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] - node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2241:134] - node _T_995 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] - node _T_996 = eq(_T_995, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] - node _T_997 = and(io.dec_csr_wen_r_mod, _T_996) @[dec_tlu_ctl.scala 2241:69] - node _T_998 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2241:120] - node _T_999 = and(_T_997, _T_998) @[dec_tlu_ctl.scala 2241:111] - node _T_1000 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2241:153] - node _T_1001 = not(_T_1000) @[dec_tlu_ctl.scala 2241:137] - node _T_1002 = or(_T_1001, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] - node _T_1003 = and(_T_999, _T_1002) @[dec_tlu_ctl.scala 2241:134] - wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2241:42] - wr_mtdata2_t_r[0] <= _T_976 @[dec_tlu_ctl.scala 2241:42] - wr_mtdata2_t_r[1] <= _T_985 @[dec_tlu_ctl.scala 2241:42] - wr_mtdata2_t_r[2] <= _T_994 @[dec_tlu_ctl.scala 2241:42] - wr_mtdata2_t_r[3] <= _T_1003 @[dec_tlu_ctl.scala 2241:42] - node _T_1004 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2242:84] + mtdata1_tsel_out <= _T_942 @[Mux.scala 27:72] + node _T_943 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[0].select <= _T_943 @[dec_tlu_ctl.scala 2230:40] + node _T_944 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[0].match_pkt <= _T_944 @[dec_tlu_ctl.scala 2231:43] + node _T_945 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[0].store <= _T_945 @[dec_tlu_ctl.scala 2232:40] + node _T_946 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[0].load <= _T_946 @[dec_tlu_ctl.scala 2233:40] + node _T_947 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[0].execute <= _T_947 @[dec_tlu_ctl.scala 2234:40] + node _T_948 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[0].m <= _T_948 @[dec_tlu_ctl.scala 2235:40] + node _T_949 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[1].select <= _T_949 @[dec_tlu_ctl.scala 2230:40] + node _T_950 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[1].match_pkt <= _T_950 @[dec_tlu_ctl.scala 2231:43] + node _T_951 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[1].store <= _T_951 @[dec_tlu_ctl.scala 2232:40] + node _T_952 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[1].load <= _T_952 @[dec_tlu_ctl.scala 2233:40] + node _T_953 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[1].execute <= _T_953 @[dec_tlu_ctl.scala 2234:40] + node _T_954 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[1].m <= _T_954 @[dec_tlu_ctl.scala 2235:40] + node _T_955 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[2].select <= _T_955 @[dec_tlu_ctl.scala 2230:40] + node _T_956 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[2].match_pkt <= _T_956 @[dec_tlu_ctl.scala 2231:43] + node _T_957 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[2].store <= _T_957 @[dec_tlu_ctl.scala 2232:40] + node _T_958 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[2].load <= _T_958 @[dec_tlu_ctl.scala 2233:40] + node _T_959 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[2].execute <= _T_959 @[dec_tlu_ctl.scala 2234:40] + node _T_960 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[2].m <= _T_960 @[dec_tlu_ctl.scala 2235:40] + node _T_961 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[3].select <= _T_961 @[dec_tlu_ctl.scala 2230:40] + node _T_962 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[3].match_pkt <= _T_962 @[dec_tlu_ctl.scala 2231:43] + node _T_963 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[3].store <= _T_963 @[dec_tlu_ctl.scala 2232:40] + node _T_964 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[3].load <= _T_964 @[dec_tlu_ctl.scala 2233:40] + node _T_965 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[3].execute <= _T_965 @[dec_tlu_ctl.scala 2234:40] + node _T_966 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[3].m <= _T_966 @[dec_tlu_ctl.scala 2235:40] + node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2242:69] + node _T_970 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2242:120] + node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2242:111] + node _T_972 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2242:137] + node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2242:134] + node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2242:69] + node _T_979 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2242:120] + node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2242:111] + node _T_981 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2242:137] + node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2242:134] + node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2242:69] + node _T_988 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2242:120] + node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2242:111] + node _T_990 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2242:137] + node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2242:134] + node _T_994 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_995 = eq(_T_994, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_996 = and(io.dec_csr_wen_r_mod, _T_995) @[dec_tlu_ctl.scala 2242:69] + node _T_997 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2242:120] + node _T_998 = and(_T_996, _T_997) @[dec_tlu_ctl.scala 2242:111] + node _T_999 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_1000 = not(_T_999) @[dec_tlu_ctl.scala 2242:137] + node _T_1001 = or(_T_1000, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_1002 = and(_T_998, _T_1001) @[dec_tlu_ctl.scala 2242:134] + wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[0] <= _T_975 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[1] <= _T_984 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[2] <= _T_993 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[3] <= _T_1002 @[dec_tlu_ctl.scala 2242:42] + node _T_1003 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_22.io.en <= _T_1004 @[lib.scala 371:17] + rvclkhdr_22.io.en <= _T_1003 @[lib.scala 371:17] rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1005 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1005 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[0] <= _T_1005 @[dec_tlu_ctl.scala 2242:36] - node _T_1006 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2242:84] + reg _T_1004 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1004 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[0] <= _T_1004 @[dec_tlu_ctl.scala 2243:36] + node _T_1005 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_23.io.en <= _T_1006 @[lib.scala 371:17] + rvclkhdr_23.io.en <= _T_1005 @[lib.scala 371:17] rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1007 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1007 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[1] <= _T_1007 @[dec_tlu_ctl.scala 2242:36] - node _T_1008 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2242:84] + reg _T_1006 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1006 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[1] <= _T_1006 @[dec_tlu_ctl.scala 2243:36] + node _T_1007 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_24.io.en <= _T_1008 @[lib.scala 371:17] + rvclkhdr_24.io.en <= _T_1007 @[lib.scala 371:17] rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1009 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1009 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[2] <= _T_1009 @[dec_tlu_ctl.scala 2242:36] - node _T_1010 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2242:84] + reg _T_1008 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1008 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[2] <= _T_1008 @[dec_tlu_ctl.scala 2243:36] + node _T_1009 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_25.io.en <= _T_1010 @[lib.scala 371:17] + rvclkhdr_25.io.en <= _T_1009 @[lib.scala 371:17] rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1011 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1011 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[3] <= _T_1011 @[dec_tlu_ctl.scala 2242:36] - node _T_1012 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2246:57] - node _T_1013 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2246:57] - node _T_1014 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2246:57] - node _T_1015 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2246:57] - node _T_1016 = mux(_T_1012, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1017 = mux(_T_1013, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1018 = mux(_T_1014, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1019 = mux(_T_1015, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1020 = or(_T_1016, _T_1017) @[Mux.scala 27:72] + reg _T_1010 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1010 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[3] <= _T_1010 @[dec_tlu_ctl.scala 2243:36] + node _T_1011 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2247:57] + node _T_1012 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2247:57] + node _T_1013 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2247:57] + node _T_1014 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2247:57] + node _T_1015 = mux(_T_1011, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1016 = mux(_T_1012, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1017 = mux(_T_1013, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1018 = mux(_T_1014, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1019 = or(_T_1015, _T_1016) @[Mux.scala 27:72] + node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72] - node _T_1022 = or(_T_1021, _T_1019) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata2_tsel_out <= _T_1022 @[Mux.scala 27:72] - io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2247:51] - io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2247:51] - io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2247:51] - io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2247:51] - mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2257:15] - mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2258:15] - mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2259:15] - mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2260:15] - node _T_1023 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] - node _T_1024 = mux(_T_1023, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1024) @[dec_tlu_ctl.scala 2266:59] - wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2267:24] - wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2268:27] - node _T_1025 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2272:38] - node _T_1026 = not(_T_1025) @[dec_tlu_ctl.scala 2272:24] - node _T_1027 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] - node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2273:62] - node _T_1029 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] - node _T_1030 = bits(_T_1029, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1031 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] - node _T_1032 = bits(_T_1031, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1033 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] - node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] - node _T_1036 = and(io.tlu_i0_commit_cmt, _T_1035) @[dec_tlu_ctl.scala 2276:94] - node _T_1037 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] - node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1039 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] - node _T_1040 = and(io.tlu_i0_commit_cmt, _T_1039) @[dec_tlu_ctl.scala 2277:94] - node _T_1041 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] - node _T_1042 = and(_T_1040, _T_1041) @[dec_tlu_ctl.scala 2277:115] - node _T_1043 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] - node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1045 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] - node _T_1046 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1047 = and(_T_1045, _T_1046) @[dec_tlu_ctl.scala 2278:115] - node _T_1048 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] - node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1050 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] - node _T_1051 = bits(_T_1050, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1052 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] - node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1054 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] - node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] - node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] - node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1059 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] - node _T_1060 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] - node _T_1061 = bits(_T_1060, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1062 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] - node _T_1063 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] - node _T_1064 = bits(_T_1063, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1065 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] - node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] - node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1069 = and(_T_1068, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] - node _T_1070 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] - node _T_1074 = and(_T_1072, _T_1073) @[dec_tlu_ctl.scala 2287:101] - node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] - node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2288:59] - node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] - node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] - node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] - node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] - node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] - node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] - node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] - node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] - node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] - node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] - node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] - node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] - node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] - node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] - node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] - node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] - node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] - node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] - node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] - node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] - node _T_1106 = or(_T_1104, _T_1105) @[dec_tlu_ctl.scala 2297:101] - node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] - node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] - node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] - node _T_1111 = bits(_T_1110, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] - node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] - node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] - node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] - node _T_1117 = bits(_T_1116, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] - node _T_1119 = bits(_T_1118, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] - node _T_1121 = bits(_T_1120, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] - node _T_1123 = bits(_T_1122, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] - node _T_1125 = bits(_T_1124, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] - node _T_1127 = bits(_T_1126, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] - node _T_1129 = bits(_T_1128, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] - node _T_1131 = bits(_T_1130, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] - node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] - node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] - node _T_1135 = bits(_T_1134, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] - node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] - node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] - node _T_1139 = bits(_T_1138, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] - node _T_1141 = bits(_T_1140, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] - node _T_1143 = bits(_T_1142, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] - node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] - node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] - node _T_1147 = bits(_T_1146, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] - node _T_1149 = bits(_T_1148, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] - node _T_1151 = bits(_T_1150, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] - node _T_1153 = bits(_T_1152, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] - node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] - node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] - node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] - node _T_1161 = bits(_T_1160, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] - node _T_1163 = bits(_T_1162, 0, 0) @[dec_tlu_ctl.scala 2320:84] - node _T_1164 = not(_T_1163) @[dec_tlu_ctl.scala 2320:73] - node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] - node _T_1166 = bits(_T_1165, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1169 = not(_T_1168) @[dec_tlu_ctl.scala 2321:73] - node _T_1170 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] - node _T_1171 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] - node _T_1172 = and(_T_1170, _T_1171) @[dec_tlu_ctl.scala 2321:113] - node _T_1173 = orr(_T_1172) @[dec_tlu_ctl.scala 2321:125] - node _T_1174 = and(_T_1169, _T_1173) @[dec_tlu_ctl.scala 2321:98] - node _T_1175 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] - node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1177 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] - node _T_1178 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] - node _T_1179 = bits(_T_1178, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1180 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] - node _T_1181 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] - node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1183 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1184 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] - node _T_1185 = bits(_T_1184, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1186 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] - node _T_1187 = bits(_T_1186, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1188 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] - node _T_1189 = bits(_T_1188, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1190 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] - node _T_1191 = bits(_T_1190, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1192 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] - node _T_1193 = bits(_T_1192, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1194 = mux(_T_1028, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1196 = mux(_T_1032, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1197 = mux(_T_1034, _T_1036, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1198 = mux(_T_1038, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1199 = mux(_T_1044, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1200 = mux(_T_1049, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1201 = mux(_T_1051, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1202 = mux(_T_1053, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1203 = mux(_T_1055, _T_1056, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1204 = mux(_T_1058, _T_1059, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1205 = mux(_T_1061, _T_1062, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1206 = mux(_T_1064, _T_1065, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1207 = mux(_T_1067, _T_1069, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1208 = mux(_T_1071, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1209 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1210 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1211 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1212 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1213 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1214 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1215 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1216 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1217 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1218 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1219 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1220 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1221 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1222 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1223 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1224 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1225 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1226 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1227 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1228 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1229 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1230 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1231 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1232 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1233 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1234 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1235 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1236 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1237 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1238 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1239 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1240 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1241 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1242 = mux(_T_1166, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1243 = mux(_T_1176, _T_1177, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1244 = mux(_T_1179, _T_1180, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1245 = mux(_T_1182, _T_1183, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1246 = mux(_T_1185, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1247 = mux(_T_1187, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1248 = mux(_T_1189, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1249 = mux(_T_1191, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1250 = mux(_T_1193, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1251 = or(_T_1194, _T_1195) @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1021 @[Mux.scala 27:72] + io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2248:51] + io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2248:51] + io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2248:51] + io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2248:51] + mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2258:15] + mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2259:15] + mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2260:15] + mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2261:15] + node _T_1022 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1023 = mux(_T_1022, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1023) @[dec_tlu_ctl.scala 2267:59] + wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2268:24] + wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2269:27] + node _T_1024 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2273:38] + node _T_1025 = not(_T_1024) @[dec_tlu_ctl.scala 2273:24] + node _T_1026 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1028 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1030 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1031 = bits(_T_1030, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1032 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1034 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1035 = and(io.tlu_i0_commit_cmt, _T_1034) @[dec_tlu_ctl.scala 2277:94] + node _T_1036 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1037 = bits(_T_1036, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1038 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1039 = and(io.tlu_i0_commit_cmt, _T_1038) @[dec_tlu_ctl.scala 2278:94] + node _T_1040 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1041 = and(_T_1039, _T_1040) @[dec_tlu_ctl.scala 2278:115] + node _T_1042 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1044 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1045 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1046 = and(_T_1044, _T_1045) @[dec_tlu_ctl.scala 2279:115] + node _T_1047 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1049 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1051 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1053 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1058 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1062 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1063 = bits(_T_1062, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1064 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1068 = and(_T_1067, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1069 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1072 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2288:101] + node _T_1074 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1077 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1080 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1083 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1086 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1089 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1092 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1095 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1096 = bits(_T_1095, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1097 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1098 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1100 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1101 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1103 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1105 = or(_T_1103, _T_1104) @[dec_tlu_ctl.scala 2298:101] + node _T_1106 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1108 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1111 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1112 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1114 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1115 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1117 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1119 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1121 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1123 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1125 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1127 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1129 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1131 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1132 = or(_T_1131, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1133 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1135 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1136 = or(_T_1135, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1137 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1139 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1141 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1143 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1144 = and(_T_1143, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1149 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1151 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1153 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1155 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1157 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1159 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1160 = bits(_T_1159, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1161 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1162 = bits(_T_1161, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1163 = not(_T_1162) @[dec_tlu_ctl.scala 2321:73] + node _T_1164 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1166 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1168 = not(_T_1167) @[dec_tlu_ctl.scala 2322:73] + node _T_1169 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1170 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1171 = and(_T_1169, _T_1170) @[dec_tlu_ctl.scala 2322:113] + node _T_1172 = orr(_T_1171) @[dec_tlu_ctl.scala 2322:125] + node _T_1173 = and(_T_1168, _T_1172) @[dec_tlu_ctl.scala 2322:98] + node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1186 = bits(_T_1185, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1188 = bits(_T_1187, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1190 = bits(_T_1189, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1192 = bits(_T_1191, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1193 = mux(_T_1027, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1194 = mux(_T_1029, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1031, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1033, _T_1035, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1037, _T_1041, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1043, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1048, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1050, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1052, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1066, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1070, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1093, _T_1094, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1096, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1102, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1107, _T_1108, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1110, _T_1111, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1113, _T_1114, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1116, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1118, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1120, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1122, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1124, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1126, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1128, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1130, _T_1132, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1138, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1140, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1142, _T_1144, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1146, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1148, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1150, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1152, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1154, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1156, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1158, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1160, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1243 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1244 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1245 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1246 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1247 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1248 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1249 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1250 = or(_T_1193, _T_1194) @[Mux.scala 27:72] + node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72] node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72] node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72] node _T_1254 = or(_T_1253, _T_1198) @[Mux.scala 27:72] @@ -74632,238 +74632,238 @@ circuit quasar : node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72] node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72] node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72] - node _T_1306 = or(_T_1305, _T_1250) @[Mux.scala 27:72] - wire _T_1307 : UInt<1> @[Mux.scala 27:72] - _T_1307 <= _T_1306 @[Mux.scala 27:72] - node _T_1308 = and(_T_1026, _T_1307) @[dec_tlu_ctl.scala 2272:44] - mhpmc_inc_r[0] <= _T_1308 @[dec_tlu_ctl.scala 2272:19] - node _T_1309 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2272:38] - node _T_1310 = not(_T_1309) @[dec_tlu_ctl.scala 2272:24] - node _T_1311 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] - node _T_1312 = bits(_T_1311, 0, 0) @[dec_tlu_ctl.scala 2273:62] - node _T_1313 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] - node _T_1314 = bits(_T_1313, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1315 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] - node _T_1316 = bits(_T_1315, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1317 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] - node _T_1318 = bits(_T_1317, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] - node _T_1320 = and(io.tlu_i0_commit_cmt, _T_1319) @[dec_tlu_ctl.scala 2276:94] - node _T_1321 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] - node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1323 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] - node _T_1324 = and(io.tlu_i0_commit_cmt, _T_1323) @[dec_tlu_ctl.scala 2277:94] - node _T_1325 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] - node _T_1326 = and(_T_1324, _T_1325) @[dec_tlu_ctl.scala 2277:115] - node _T_1327 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] - node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1329 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] - node _T_1330 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1331 = and(_T_1329, _T_1330) @[dec_tlu_ctl.scala 2278:115] - node _T_1332 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] - node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1334 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] - node _T_1335 = bits(_T_1334, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1336 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] - node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1338 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] - node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] - node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] - node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1343 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] - node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] - node _T_1345 = bits(_T_1344, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] - node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] - node _T_1348 = bits(_T_1347, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] - node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] - node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1353 = and(_T_1352, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] - node _T_1354 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1357 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] - node _T_1358 = and(_T_1356, _T_1357) @[dec_tlu_ctl.scala 2287:101] - node _T_1359 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] - node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2288:59] - node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] - node _T_1362 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] - node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] - node _T_1365 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] - node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] - node _T_1368 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] - node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] - node _T_1371 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] - node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] - node _T_1374 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] - node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] - node _T_1377 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] - node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] - node _T_1380 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] - node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1382 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] - node _T_1383 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] - node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1385 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] - node _T_1386 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] - node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] - node _T_1389 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] - node _T_1390 = or(_T_1388, _T_1389) @[dec_tlu_ctl.scala 2297:101] - node _T_1391 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] - node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1393 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] - node _T_1394 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] - node _T_1395 = bits(_T_1394, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1396 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] - node _T_1397 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] - node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1399 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] - node _T_1400 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] - node _T_1401 = bits(_T_1400, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1402 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] - node _T_1403 = bits(_T_1402, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1404 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] - node _T_1405 = bits(_T_1404, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1406 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] - node _T_1407 = bits(_T_1406, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1408 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] - node _T_1409 = bits(_T_1408, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1410 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] - node _T_1411 = bits(_T_1410, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1412 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] - node _T_1413 = bits(_T_1412, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1414 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] - node _T_1415 = bits(_T_1414, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1416 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] - node _T_1417 = or(_T_1416, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] - node _T_1418 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] - node _T_1419 = bits(_T_1418, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1420 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] - node _T_1421 = or(_T_1420, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] - node _T_1422 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] - node _T_1423 = bits(_T_1422, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1424 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] - node _T_1425 = bits(_T_1424, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1426 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] - node _T_1427 = bits(_T_1426, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1428 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] - node _T_1429 = and(_T_1428, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] - node _T_1430 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] - node _T_1431 = bits(_T_1430, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1432 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] - node _T_1433 = bits(_T_1432, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1434 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] - node _T_1435 = bits(_T_1434, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1436 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] - node _T_1437 = bits(_T_1436, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1438 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] - node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1440 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] - node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1442 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] - node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1444 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] - node _T_1445 = bits(_T_1444, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1446 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] - node _T_1447 = bits(_T_1446, 0, 0) @[dec_tlu_ctl.scala 2320:84] - node _T_1448 = not(_T_1447) @[dec_tlu_ctl.scala 2320:73] - node _T_1449 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] - node _T_1450 = bits(_T_1449, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1451 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1453 = not(_T_1452) @[dec_tlu_ctl.scala 2321:73] - node _T_1454 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] - node _T_1455 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] - node _T_1456 = and(_T_1454, _T_1455) @[dec_tlu_ctl.scala 2321:113] - node _T_1457 = orr(_T_1456) @[dec_tlu_ctl.scala 2321:125] - node _T_1458 = and(_T_1453, _T_1457) @[dec_tlu_ctl.scala 2321:98] - node _T_1459 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] - node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1461 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] - node _T_1462 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] - node _T_1463 = bits(_T_1462, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1464 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] - node _T_1465 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] - node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1467 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] - node _T_1469 = bits(_T_1468, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] - node _T_1471 = bits(_T_1470, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] - node _T_1473 = bits(_T_1472, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] - node _T_1475 = bits(_T_1474, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1476 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] - node _T_1477 = bits(_T_1476, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1478 = mux(_T_1312, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1479 = mux(_T_1314, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1480 = mux(_T_1316, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1481 = mux(_T_1318, _T_1320, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1482 = mux(_T_1322, _T_1326, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1483 = mux(_T_1328, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1484 = mux(_T_1333, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1485 = mux(_T_1335, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1486 = mux(_T_1337, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1487 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1488 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1489 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1490 = mux(_T_1348, _T_1349, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1491 = mux(_T_1351, _T_1353, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1492 = mux(_T_1355, _T_1358, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1493 = mux(_T_1360, _T_1361, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1494 = mux(_T_1363, _T_1364, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1495 = mux(_T_1366, _T_1367, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1496 = mux(_T_1369, _T_1370, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1497 = mux(_T_1372, _T_1373, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1498 = mux(_T_1375, _T_1376, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1499 = mux(_T_1378, _T_1379, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1500 = mux(_T_1381, _T_1382, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1501 = mux(_T_1384, _T_1385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1502 = mux(_T_1387, _T_1390, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1503 = mux(_T_1392, _T_1393, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1504 = mux(_T_1395, _T_1396, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1505 = mux(_T_1398, _T_1399, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1506 = mux(_T_1401, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1507 = mux(_T_1403, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1508 = mux(_T_1405, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1509 = mux(_T_1407, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1510 = mux(_T_1409, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1511 = mux(_T_1411, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1512 = mux(_T_1413, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1513 = mux(_T_1415, _T_1417, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1514 = mux(_T_1419, _T_1421, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1515 = mux(_T_1423, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1516 = mux(_T_1425, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1517 = mux(_T_1427, _T_1429, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1518 = mux(_T_1431, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1519 = mux(_T_1433, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1520 = mux(_T_1435, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1521 = mux(_T_1437, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1522 = mux(_T_1439, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1523 = mux(_T_1441, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1524 = mux(_T_1443, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1525 = mux(_T_1445, _T_1448, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1526 = mux(_T_1450, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1527 = mux(_T_1460, _T_1461, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1528 = mux(_T_1463, _T_1464, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1529 = mux(_T_1466, _T_1467, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1530 = mux(_T_1469, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1531 = mux(_T_1471, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1532 = mux(_T_1473, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1533 = mux(_T_1475, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1534 = mux(_T_1477, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1535 = or(_T_1478, _T_1479) @[Mux.scala 27:72] + wire _T_1306 : UInt<1> @[Mux.scala 27:72] + _T_1306 <= _T_1305 @[Mux.scala 27:72] + node _T_1307 = and(_T_1025, _T_1306) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[0] <= _T_1307 @[dec_tlu_ctl.scala 2273:19] + node _T_1308 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2273:38] + node _T_1309 = not(_T_1308) @[dec_tlu_ctl.scala 2273:24] + node _T_1310 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1312 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1314 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1315 = bits(_T_1314, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1316 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1318 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1319 = and(io.tlu_i0_commit_cmt, _T_1318) @[dec_tlu_ctl.scala 2277:94] + node _T_1320 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1321 = bits(_T_1320, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1322 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1323 = and(io.tlu_i0_commit_cmt, _T_1322) @[dec_tlu_ctl.scala 2278:94] + node _T_1324 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1325 = and(_T_1323, _T_1324) @[dec_tlu_ctl.scala 2278:115] + node _T_1326 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1328 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1329 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1330 = and(_T_1328, _T_1329) @[dec_tlu_ctl.scala 2279:115] + node _T_1331 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1333 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1335 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1337 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1342 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1346 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1347 = bits(_T_1346, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1348 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1352 = and(_T_1351, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1353 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1357 = and(_T_1355, _T_1356) @[dec_tlu_ctl.scala 2288:101] + node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1380 = bits(_T_1379, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1389 = or(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2298:101] + node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1444 = bits(_T_1443, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1446 = bits(_T_1445, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1447 = not(_T_1446) @[dec_tlu_ctl.scala 2321:73] + node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1452 = not(_T_1451) @[dec_tlu_ctl.scala 2322:73] + node _T_1453 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1454 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1455 = and(_T_1453, _T_1454) @[dec_tlu_ctl.scala 2322:113] + node _T_1456 = orr(_T_1455) @[dec_tlu_ctl.scala 2322:125] + node _T_1457 = and(_T_1452, _T_1456) @[dec_tlu_ctl.scala 2322:98] + node _T_1458 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1460 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1461 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1463 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1464 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1469 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1470 = bits(_T_1469, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1471 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1472 = bits(_T_1471, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1473 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1474 = bits(_T_1473, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1475 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1476 = bits(_T_1475, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1477 = mux(_T_1311, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1315, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1321, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1327, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1332, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1334, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1336, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1341, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1344, _T_1345, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1347, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1350, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1354, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1449, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1459, _T_1460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1462, _T_1463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1465, _T_1466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1468, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1470, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = mux(_T_1472, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1532 = mux(_T_1474, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1533 = mux(_T_1476, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1534 = or(_T_1477, _T_1478) @[Mux.scala 27:72] + node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72] node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72] node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72] node _T_1538 = or(_T_1537, _T_1482) @[Mux.scala 27:72] @@ -74918,238 +74918,238 @@ circuit quasar : node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72] node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72] node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72] - node _T_1590 = or(_T_1589, _T_1534) @[Mux.scala 27:72] - wire _T_1591 : UInt<1> @[Mux.scala 27:72] - _T_1591 <= _T_1590 @[Mux.scala 27:72] - node _T_1592 = and(_T_1310, _T_1591) @[dec_tlu_ctl.scala 2272:44] - mhpmc_inc_r[1] <= _T_1592 @[dec_tlu_ctl.scala 2272:19] - node _T_1593 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2272:38] - node _T_1594 = not(_T_1593) @[dec_tlu_ctl.scala 2272:24] - node _T_1595 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] - node _T_1596 = bits(_T_1595, 0, 0) @[dec_tlu_ctl.scala 2273:62] - node _T_1597 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] - node _T_1598 = bits(_T_1597, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1599 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] - node _T_1600 = bits(_T_1599, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1601 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] - node _T_1602 = bits(_T_1601, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] - node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[dec_tlu_ctl.scala 2276:94] - node _T_1605 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] - node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1607 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] - node _T_1608 = and(io.tlu_i0_commit_cmt, _T_1607) @[dec_tlu_ctl.scala 2277:94] - node _T_1609 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] - node _T_1610 = and(_T_1608, _T_1609) @[dec_tlu_ctl.scala 2277:115] - node _T_1611 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] - node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1613 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] - node _T_1614 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1615 = and(_T_1613, _T_1614) @[dec_tlu_ctl.scala 2278:115] - node _T_1616 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] - node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1618 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] - node _T_1619 = bits(_T_1618, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1620 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] - node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1622 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] - node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] - node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] - node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1627 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] - node _T_1628 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] - node _T_1629 = bits(_T_1628, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1630 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] - node _T_1631 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] - node _T_1632 = bits(_T_1631, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1633 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] - node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] - node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1637 = and(_T_1636, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] - node _T_1638 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1641 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] - node _T_1642 = and(_T_1640, _T_1641) @[dec_tlu_ctl.scala 2287:101] - node _T_1643 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] - node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2288:59] - node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] - node _T_1646 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] - node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] - node _T_1649 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] - node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] - node _T_1652 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] - node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] - node _T_1655 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] - node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] - node _T_1658 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] - node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] - node _T_1661 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] - node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] - node _T_1664 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] - node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1666 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] - node _T_1667 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] - node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1669 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] - node _T_1670 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] - node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] - node _T_1673 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] - node _T_1674 = or(_T_1672, _T_1673) @[dec_tlu_ctl.scala 2297:101] - node _T_1675 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] - node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1677 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] - node _T_1678 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] - node _T_1679 = bits(_T_1678, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1680 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] - node _T_1681 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] - node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1683 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] - node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] - node _T_1685 = bits(_T_1684, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] - node _T_1687 = bits(_T_1686, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1688 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] - node _T_1689 = bits(_T_1688, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1690 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] - node _T_1691 = bits(_T_1690, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1692 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] - node _T_1693 = bits(_T_1692, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1694 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] - node _T_1695 = bits(_T_1694, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1696 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] - node _T_1697 = bits(_T_1696, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1698 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] - node _T_1699 = bits(_T_1698, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1700 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] - node _T_1701 = or(_T_1700, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] - node _T_1702 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] - node _T_1703 = bits(_T_1702, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1704 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] - node _T_1705 = or(_T_1704, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] - node _T_1706 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] - node _T_1707 = bits(_T_1706, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1708 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] - node _T_1709 = bits(_T_1708, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1710 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] - node _T_1711 = bits(_T_1710, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1712 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] - node _T_1713 = and(_T_1712, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] - node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] - node _T_1715 = bits(_T_1714, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] - node _T_1717 = bits(_T_1716, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] - node _T_1719 = bits(_T_1718, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] - node _T_1721 = bits(_T_1720, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] - node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1724 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] - node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1726 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] - node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1728 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] - node _T_1729 = bits(_T_1728, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1730 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] - node _T_1731 = bits(_T_1730, 0, 0) @[dec_tlu_ctl.scala 2320:84] - node _T_1732 = not(_T_1731) @[dec_tlu_ctl.scala 2320:73] - node _T_1733 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] - node _T_1734 = bits(_T_1733, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1735 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1737 = not(_T_1736) @[dec_tlu_ctl.scala 2321:73] - node _T_1738 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] - node _T_1739 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] - node _T_1740 = and(_T_1738, _T_1739) @[dec_tlu_ctl.scala 2321:113] - node _T_1741 = orr(_T_1740) @[dec_tlu_ctl.scala 2321:125] - node _T_1742 = and(_T_1737, _T_1741) @[dec_tlu_ctl.scala 2321:98] - node _T_1743 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] - node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1745 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] - node _T_1746 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] - node _T_1747 = bits(_T_1746, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] - node _T_1749 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] - node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1751 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1752 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] - node _T_1753 = bits(_T_1752, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1754 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] - node _T_1755 = bits(_T_1754, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1756 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] - node _T_1757 = bits(_T_1756, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1758 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] - node _T_1759 = bits(_T_1758, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1760 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] - node _T_1761 = bits(_T_1760, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1762 = mux(_T_1596, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1763 = mux(_T_1598, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1764 = mux(_T_1600, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1765 = mux(_T_1602, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1766 = mux(_T_1606, _T_1610, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1767 = mux(_T_1612, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1768 = mux(_T_1617, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1769 = mux(_T_1619, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1770 = mux(_T_1621, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1771 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1772 = mux(_T_1626, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1773 = mux(_T_1629, _T_1630, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1774 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1775 = mux(_T_1635, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1776 = mux(_T_1639, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1777 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1778 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1779 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1780 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1781 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1782 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1783 = mux(_T_1662, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1784 = mux(_T_1665, _T_1666, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1785 = mux(_T_1668, _T_1669, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1786 = mux(_T_1671, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1787 = mux(_T_1676, _T_1677, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1788 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1789 = mux(_T_1682, _T_1683, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1790 = mux(_T_1685, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1791 = mux(_T_1687, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1792 = mux(_T_1689, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1793 = mux(_T_1691, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1794 = mux(_T_1693, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1795 = mux(_T_1695, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1796 = mux(_T_1697, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1797 = mux(_T_1699, _T_1701, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1798 = mux(_T_1703, _T_1705, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1799 = mux(_T_1707, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1800 = mux(_T_1709, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1801 = mux(_T_1711, _T_1713, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1802 = mux(_T_1715, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1803 = mux(_T_1717, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1804 = mux(_T_1719, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1805 = mux(_T_1721, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1806 = mux(_T_1723, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1807 = mux(_T_1725, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1808 = mux(_T_1727, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1809 = mux(_T_1729, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1810 = mux(_T_1734, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1811 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1812 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1813 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1814 = mux(_T_1753, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1815 = mux(_T_1755, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1816 = mux(_T_1757, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1817 = mux(_T_1759, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1818 = mux(_T_1761, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1819 = or(_T_1762, _T_1763) @[Mux.scala 27:72] + wire _T_1590 : UInt<1> @[Mux.scala 27:72] + _T_1590 <= _T_1589 @[Mux.scala 27:72] + node _T_1591 = and(_T_1309, _T_1590) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[1] <= _T_1591 @[dec_tlu_ctl.scala 2273:19] + node _T_1592 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2273:38] + node _T_1593 = not(_T_1592) @[dec_tlu_ctl.scala 2273:24] + node _T_1594 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1596 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1598 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1599 = bits(_T_1598, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1600 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1602 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1603 = and(io.tlu_i0_commit_cmt, _T_1602) @[dec_tlu_ctl.scala 2277:94] + node _T_1604 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1605 = bits(_T_1604, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1606 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1607 = and(io.tlu_i0_commit_cmt, _T_1606) @[dec_tlu_ctl.scala 2278:94] + node _T_1608 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1609 = and(_T_1607, _T_1608) @[dec_tlu_ctl.scala 2278:115] + node _T_1610 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1612 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1613 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1614 = and(_T_1612, _T_1613) @[dec_tlu_ctl.scala 2279:115] + node _T_1615 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1617 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1619 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1621 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1626 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1631 = bits(_T_1630, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1636 = and(_T_1635, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1637 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1640 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1641 = and(_T_1639, _T_1640) @[dec_tlu_ctl.scala 2288:101] + node _T_1642 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1645 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1648 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1651 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1654 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1657 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1660 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1663 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1664 = bits(_T_1663, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1665 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1666 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1668 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1669 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1673 = or(_T_1671, _T_1672) @[dec_tlu_ctl.scala 2298:101] + node _T_1674 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1676 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1679 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1680 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1682 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1683 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1685 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1687 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1689 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1691 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1693 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1695 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1697 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1699 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1700 = or(_T_1699, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1701 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1703 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1704 = or(_T_1703, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1705 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1707 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1709 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1711 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1712 = and(_T_1711, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1717 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1719 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1721 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1723 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1725 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1727 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1728 = bits(_T_1727, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1729 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1730 = bits(_T_1729, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1731 = not(_T_1730) @[dec_tlu_ctl.scala 2321:73] + node _T_1732 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1734 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1736 = not(_T_1735) @[dec_tlu_ctl.scala 2322:73] + node _T_1737 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1738 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1739 = and(_T_1737, _T_1738) @[dec_tlu_ctl.scala 2322:113] + node _T_1740 = orr(_T_1739) @[dec_tlu_ctl.scala 2322:125] + node _T_1741 = and(_T_1736, _T_1740) @[dec_tlu_ctl.scala 2322:98] + node _T_1742 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1744 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1745 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1747 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1748 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1750 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1754 = bits(_T_1753, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1756 = bits(_T_1755, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1758 = bits(_T_1757, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1759 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1760 = bits(_T_1759, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1761 = mux(_T_1595, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = mux(_T_1597, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1599, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1601, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1605, _T_1609, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1611, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1616, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1618, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1620, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1631, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1634, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1638, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1664, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1670, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1678, _T_1679, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1681, _T_1682, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1684, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1686, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1688, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1690, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1692, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1694, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1696, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1698, _T_1700, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1706, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1708, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1710, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1714, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1716, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1718, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1720, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1722, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1724, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1726, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1728, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1733, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1811 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1812 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1813 = mux(_T_1752, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1814 = mux(_T_1754, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1815 = mux(_T_1756, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1816 = mux(_T_1758, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1817 = mux(_T_1760, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1818 = or(_T_1761, _T_1762) @[Mux.scala 27:72] + node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72] node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72] node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72] node _T_1822 = or(_T_1821, _T_1766) @[Mux.scala 27:72] @@ -75204,238 +75204,238 @@ circuit quasar : node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72] node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72] node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72] - node _T_1874 = or(_T_1873, _T_1818) @[Mux.scala 27:72] - wire _T_1875 : UInt<1> @[Mux.scala 27:72] - _T_1875 <= _T_1874 @[Mux.scala 27:72] - node _T_1876 = and(_T_1594, _T_1875) @[dec_tlu_ctl.scala 2272:44] - mhpmc_inc_r[2] <= _T_1876 @[dec_tlu_ctl.scala 2272:19] - node _T_1877 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2272:38] - node _T_1878 = not(_T_1877) @[dec_tlu_ctl.scala 2272:24] - node _T_1879 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] - node _T_1880 = bits(_T_1879, 0, 0) @[dec_tlu_ctl.scala 2273:62] - node _T_1881 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] - node _T_1882 = bits(_T_1881, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1883 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] - node _T_1884 = bits(_T_1883, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1885 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] - node _T_1886 = bits(_T_1885, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] - node _T_1888 = and(io.tlu_i0_commit_cmt, _T_1887) @[dec_tlu_ctl.scala 2276:94] - node _T_1889 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] - node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1891 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] - node _T_1892 = and(io.tlu_i0_commit_cmt, _T_1891) @[dec_tlu_ctl.scala 2277:94] - node _T_1893 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] - node _T_1894 = and(_T_1892, _T_1893) @[dec_tlu_ctl.scala 2277:115] - node _T_1895 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] - node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1897 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] - node _T_1898 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1899 = and(_T_1897, _T_1898) @[dec_tlu_ctl.scala 2278:115] - node _T_1900 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] - node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1902 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] - node _T_1903 = bits(_T_1902, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1904 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] - node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1906 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] - node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] - node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] - node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1911 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] - node _T_1912 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] - node _T_1913 = bits(_T_1912, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1914 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] - node _T_1915 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] - node _T_1916 = bits(_T_1915, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1917 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] - node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] - node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1921 = and(_T_1920, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] - node _T_1922 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1925 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] - node _T_1926 = and(_T_1924, _T_1925) @[dec_tlu_ctl.scala 2287:101] - node _T_1927 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] - node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2288:59] - node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] - node _T_1930 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] - node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] - node _T_1933 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] - node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] - node _T_1936 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] - node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] - node _T_1939 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] - node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] - node _T_1942 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] - node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] - node _T_1945 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] - node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] - node _T_1948 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] - node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] - node _T_1951 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] - node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] - node _T_1954 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] - node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] - node _T_1957 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] - node _T_1958 = or(_T_1956, _T_1957) @[dec_tlu_ctl.scala 2297:101] - node _T_1959 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] - node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1961 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] - node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] - node _T_1963 = bits(_T_1962, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1964 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] - node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] - node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1967 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] - node _T_1968 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] - node _T_1969 = bits(_T_1968, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1970 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] - node _T_1971 = bits(_T_1970, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1972 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] - node _T_1973 = bits(_T_1972, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1974 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] - node _T_1975 = bits(_T_1974, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1976 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] - node _T_1977 = bits(_T_1976, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1978 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] - node _T_1979 = bits(_T_1978, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1980 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] - node _T_1981 = bits(_T_1980, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1982 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] - node _T_1983 = bits(_T_1982, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1984 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] - node _T_1985 = or(_T_1984, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] - node _T_1986 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] - node _T_1987 = bits(_T_1986, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1988 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] - node _T_1989 = or(_T_1988, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] - node _T_1990 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] - node _T_1991 = bits(_T_1990, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1992 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] - node _T_1993 = bits(_T_1992, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1994 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] - node _T_1995 = bits(_T_1994, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1996 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] - node _T_1997 = and(_T_1996, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] - node _T_1998 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] - node _T_1999 = bits(_T_1998, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_2000 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] - node _T_2001 = bits(_T_2000, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_2002 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] - node _T_2003 = bits(_T_2002, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_2004 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] - node _T_2005 = bits(_T_2004, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_2006 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] - node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_2008 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] - node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_2010 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] - node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_2012 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] - node _T_2013 = bits(_T_2012, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_2014 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] - node _T_2015 = bits(_T_2014, 0, 0) @[dec_tlu_ctl.scala 2320:84] - node _T_2016 = not(_T_2015) @[dec_tlu_ctl.scala 2320:73] - node _T_2017 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] - node _T_2018 = bits(_T_2017, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_2019 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_2021 = not(_T_2020) @[dec_tlu_ctl.scala 2321:73] - node _T_2022 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] - node _T_2023 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] - node _T_2024 = and(_T_2022, _T_2023) @[dec_tlu_ctl.scala 2321:113] - node _T_2025 = orr(_T_2024) @[dec_tlu_ctl.scala 2321:125] - node _T_2026 = and(_T_2021, _T_2025) @[dec_tlu_ctl.scala 2321:98] - node _T_2027 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] - node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_2029 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] - node _T_2030 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] - node _T_2031 = bits(_T_2030, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_2032 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] - node _T_2033 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] - node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_2035 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] - node _T_2037 = bits(_T_2036, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] - node _T_2039 = bits(_T_2038, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] - node _T_2041 = bits(_T_2040, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_2042 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] - node _T_2043 = bits(_T_2042, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_2044 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] - node _T_2045 = bits(_T_2044, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_2046 = mux(_T_1880, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_1882, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_1884, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_1886, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_1890, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_1896, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_1901, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_1903, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_1905, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_1907, _T_1908, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_1910, _T_1911, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_1913, _T_1914, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = mux(_T_1916, _T_1917, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2059 = mux(_T_1919, _T_1921, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2060 = mux(_T_1923, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2061 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2062 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2063 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2064 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2065 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2066 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2067 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2068 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2069 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2070 = mux(_T_1955, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2071 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2072 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2073 = mux(_T_1966, _T_1967, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2074 = mux(_T_1969, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2075 = mux(_T_1971, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2076 = mux(_T_1973, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2077 = mux(_T_1975, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2078 = mux(_T_1977, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2079 = mux(_T_1979, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2080 = mux(_T_1981, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2081 = mux(_T_1983, _T_1985, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2082 = mux(_T_1987, _T_1989, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2083 = mux(_T_1991, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2084 = mux(_T_1993, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2085 = mux(_T_1995, _T_1997, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2086 = mux(_T_1999, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2087 = mux(_T_2001, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2088 = mux(_T_2003, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2089 = mux(_T_2005, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2090 = mux(_T_2007, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2091 = mux(_T_2009, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2092 = mux(_T_2011, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2093 = mux(_T_2013, _T_2016, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2094 = mux(_T_2018, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2095 = mux(_T_2028, _T_2029, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2096 = mux(_T_2031, _T_2032, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2097 = mux(_T_2034, _T_2035, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2098 = mux(_T_2037, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2099 = mux(_T_2039, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2100 = mux(_T_2041, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2101 = mux(_T_2043, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2102 = mux(_T_2045, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2103 = or(_T_2046, _T_2047) @[Mux.scala 27:72] + wire _T_1874 : UInt<1> @[Mux.scala 27:72] + _T_1874 <= _T_1873 @[Mux.scala 27:72] + node _T_1875 = and(_T_1593, _T_1874) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[2] <= _T_1875 @[dec_tlu_ctl.scala 2273:19] + node _T_1876 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2273:38] + node _T_1877 = not(_T_1876) @[dec_tlu_ctl.scala 2273:24] + node _T_1878 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1880 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1882 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1883 = bits(_T_1882, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1884 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1886 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[dec_tlu_ctl.scala 2277:94] + node _T_1888 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1889 = bits(_T_1888, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1890 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1891 = and(io.tlu_i0_commit_cmt, _T_1890) @[dec_tlu_ctl.scala 2278:94] + node _T_1892 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1893 = and(_T_1891, _T_1892) @[dec_tlu_ctl.scala 2278:115] + node _T_1894 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1896 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1897 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1898 = and(_T_1896, _T_1897) @[dec_tlu_ctl.scala 2279:115] + node _T_1899 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1901 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1903 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1905 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1910 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1914 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1915 = bits(_T_1914, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1916 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1920 = and(_T_1919, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1921 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1924 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1925 = and(_T_1923, _T_1924) @[dec_tlu_ctl.scala 2288:101] + node _T_1926 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1929 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1932 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1935 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1938 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1941 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1944 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1947 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1948 = bits(_T_1947, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1949 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1950 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1952 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1953 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1955 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1957 = or(_T_1955, _T_1956) @[dec_tlu_ctl.scala 2298:101] + node _T_1958 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1960 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1963 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1964 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1966 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1971 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1973 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1975 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1977 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1979 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1981 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1983 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1984 = or(_T_1983, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1985 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1987 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1988 = or(_T_1987, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1993 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1995 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1996 = and(_T_1995, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_2007 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_2009 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_2011 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_2012 = bits(_T_2011, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_2013 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_2014 = bits(_T_2013, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_2015 = not(_T_2014) @[dec_tlu_ctl.scala 2321:73] + node _T_2016 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_2018 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_2020 = not(_T_2019) @[dec_tlu_ctl.scala 2322:73] + node _T_2021 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_2022 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_2023 = and(_T_2021, _T_2022) @[dec_tlu_ctl.scala 2322:113] + node _T_2024 = orr(_T_2023) @[dec_tlu_ctl.scala 2322:125] + node _T_2025 = and(_T_2020, _T_2024) @[dec_tlu_ctl.scala 2322:98] + node _T_2026 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_2028 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_2029 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_2032 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_2034 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_2037 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_2038 = bits(_T_2037, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_2039 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_2040 = bits(_T_2039, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_2041 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_2042 = bits(_T_2041, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_2043 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_2044 = bits(_T_2043, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_2045 = mux(_T_1879, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_1881, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1883, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1885, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1889, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1895, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1900, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1902, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1904, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1909, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1912, _T_1913, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1915, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1918, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1922, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1954, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1959, _T_1960, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1962, _T_1963, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1965, _T_1966, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1968, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1970, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1972, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1974, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1976, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1978, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1980, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1982, _T_1984, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_1990, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_1992, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_1994, _T_1996, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_1998, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_2000, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2002, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2004, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2006, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2008, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2010, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2012, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2017, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2095 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2096 = mux(_T_2033, _T_2034, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2097 = mux(_T_2036, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2098 = mux(_T_2038, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2099 = mux(_T_2040, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2100 = mux(_T_2042, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2101 = mux(_T_2044, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2102 = or(_T_2045, _T_2046) @[Mux.scala 27:72] + node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72] node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72] node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72] node _T_2106 = or(_T_2105, _T_2050) @[Mux.scala 27:72] @@ -75490,576 +75490,576 @@ circuit quasar : node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72] node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72] node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72] - node _T_2158 = or(_T_2157, _T_2102) @[Mux.scala 27:72] - wire _T_2159 : UInt<1> @[Mux.scala 27:72] - _T_2159 <= _T_2158 @[Mux.scala 27:72] - node _T_2160 = and(_T_1878, _T_2159) @[dec_tlu_ctl.scala 2272:44] - mhpmc_inc_r[3] <= _T_2160 @[dec_tlu_ctl.scala 2272:19] - reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2333:53] - _T_2161 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2333:53] - mhpmc_inc_r_d1[0] <= _T_2161 @[dec_tlu_ctl.scala 2333:20] - reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] - _T_2162 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2334:53] - mhpmc_inc_r_d1[1] <= _T_2162 @[dec_tlu_ctl.scala 2334:20] - reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] - _T_2163 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2335:53] - mhpmc_inc_r_d1[2] <= _T_2163 @[dec_tlu_ctl.scala 2335:20] - reg _T_2164 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] - _T_2164 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2336:53] - mhpmc_inc_r_d1[3] <= _T_2164 @[dec_tlu_ctl.scala 2336:20] - reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:56] - perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2337:56] - node _T_2165 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2340:53] - node _T_2166 = and(io.dec_tlu_dbg_halted, _T_2165) @[dec_tlu_ctl.scala 2340:44] - node _T_2167 = or(_T_2166, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2340:67] - perfcnt_halted <= _T_2167 @[dec_tlu_ctl.scala 2340:17] - node _T_2168 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:70] - node _T_2169 = and(io.dec_tlu_dbg_halted, _T_2168) @[dec_tlu_ctl.scala 2341:61] - node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2341:37] - node _T_2171 = bits(_T_2170, 0, 0) @[Bitwise.scala 72:15] - node _T_2172 = mux(_T_2171, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2173 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2341:104] - node _T_2174 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2341:120] - node _T_2175 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2341:136] - node _T_2176 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2341:152] - node _T_2177 = cat(_T_2175, _T_2176) @[Cat.scala 29:58] - node _T_2178 = cat(_T_2173, _T_2174) @[Cat.scala 29:58] - node _T_2179 = cat(_T_2178, _T_2177) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2172, _T_2179) @[dec_tlu_ctl.scala 2341:86] - node _T_2180 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2343:88] - node _T_2181 = not(_T_2180) @[dec_tlu_ctl.scala 2343:67] - node _T_2182 = and(perfcnt_halted_d1, _T_2181) @[dec_tlu_ctl.scala 2343:65] - node _T_2183 = not(_T_2182) @[dec_tlu_ctl.scala 2343:45] - node _T_2184 = and(mhpmc_inc_r_d1[0], _T_2183) @[dec_tlu_ctl.scala 2343:43] - io.dec_tlu_perfcnt0 <= _T_2184 @[dec_tlu_ctl.scala 2343:22] - node _T_2185 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2344:88] - node _T_2186 = not(_T_2185) @[dec_tlu_ctl.scala 2344:67] - node _T_2187 = and(perfcnt_halted_d1, _T_2186) @[dec_tlu_ctl.scala 2344:65] - node _T_2188 = not(_T_2187) @[dec_tlu_ctl.scala 2344:45] - node _T_2189 = and(mhpmc_inc_r_d1[1], _T_2188) @[dec_tlu_ctl.scala 2344:43] - io.dec_tlu_perfcnt1 <= _T_2189 @[dec_tlu_ctl.scala 2344:22] - node _T_2190 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2345:88] - node _T_2191 = not(_T_2190) @[dec_tlu_ctl.scala 2345:67] - node _T_2192 = and(perfcnt_halted_d1, _T_2191) @[dec_tlu_ctl.scala 2345:65] - node _T_2193 = not(_T_2192) @[dec_tlu_ctl.scala 2345:45] - node _T_2194 = and(mhpmc_inc_r_d1[2], _T_2193) @[dec_tlu_ctl.scala 2345:43] - io.dec_tlu_perfcnt2 <= _T_2194 @[dec_tlu_ctl.scala 2345:22] - node _T_2195 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2346:88] - node _T_2196 = not(_T_2195) @[dec_tlu_ctl.scala 2346:67] - node _T_2197 = and(perfcnt_halted_d1, _T_2196) @[dec_tlu_ctl.scala 2346:65] - node _T_2198 = not(_T_2197) @[dec_tlu_ctl.scala 2346:45] - node _T_2199 = and(mhpmc_inc_r_d1[3], _T_2198) @[dec_tlu_ctl.scala 2346:43] - io.dec_tlu_perfcnt3 <= _T_2199 @[dec_tlu_ctl.scala 2346:22] - node _T_2200 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2352:65] - node _T_2201 = eq(_T_2200, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2352:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2201) @[dec_tlu_ctl.scala 2352:43] - node _T_2202 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2353:23] - node _T_2203 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2353:61] - node _T_2204 = or(_T_2202, _T_2203) @[dec_tlu_ctl.scala 2353:39] - node _T_2205 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2353:86] - node mhpmc3_wr_en1 = and(_T_2204, _T_2205) @[dec_tlu_ctl.scala 2353:66] - node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2354:36] - node _T_2206 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2357:28] - node _T_2207 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2357:41] - node _T_2208 = cat(_T_2206, _T_2207) @[Cat.scala 29:58] - node _T_2209 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2210 = add(_T_2208, _T_2209) @[dec_tlu_ctl.scala 2357:49] - node _T_2211 = tail(_T_2210, 1) @[dec_tlu_ctl.scala 2357:49] - mhpmc3_incr <= _T_2211 @[dec_tlu_ctl.scala 2357:14] - node _T_2212 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2358:36] - node _T_2213 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2358:76] - node mhpmc3_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[dec_tlu_ctl.scala 2358:21] - node _T_2214 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2360:42] + wire _T_2158 : UInt<1> @[Mux.scala 27:72] + _T_2158 <= _T_2157 @[Mux.scala 27:72] + node _T_2159 = and(_T_1877, _T_2158) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[3] <= _T_2159 @[dec_tlu_ctl.scala 2273:19] + reg _T_2160 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] + _T_2160 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2334:53] + mhpmc_inc_r_d1[0] <= _T_2160 @[dec_tlu_ctl.scala 2334:20] + reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] + _T_2161 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2335:53] + mhpmc_inc_r_d1[1] <= _T_2161 @[dec_tlu_ctl.scala 2335:20] + reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] + _T_2162 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2336:53] + mhpmc_inc_r_d1[2] <= _T_2162 @[dec_tlu_ctl.scala 2336:20] + reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] + _T_2163 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2337:53] + mhpmc_inc_r_d1[3] <= _T_2163 @[dec_tlu_ctl.scala 2337:20] + reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:56] + perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2338:56] + node _T_2164 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:53] + node _T_2165 = and(io.dec_tlu_dbg_halted, _T_2164) @[dec_tlu_ctl.scala 2341:44] + node _T_2166 = or(_T_2165, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2341:67] + perfcnt_halted <= _T_2166 @[dec_tlu_ctl.scala 2341:17] + node _T_2167 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:70] + node _T_2168 = and(io.dec_tlu_dbg_halted, _T_2167) @[dec_tlu_ctl.scala 2342:61] + node _T_2169 = not(_T_2168) @[dec_tlu_ctl.scala 2342:37] + node _T_2170 = bits(_T_2169, 0, 0) @[Bitwise.scala 72:15] + node _T_2171 = mux(_T_2170, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2172 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2342:104] + node _T_2173 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2342:120] + node _T_2174 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2342:136] + node _T_2175 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2342:152] + node _T_2176 = cat(_T_2174, _T_2175) @[Cat.scala 29:58] + node _T_2177 = cat(_T_2172, _T_2173) @[Cat.scala 29:58] + node _T_2178 = cat(_T_2177, _T_2176) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2171, _T_2178) @[dec_tlu_ctl.scala 2342:86] + node _T_2179 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2344:88] + node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2344:67] + node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2344:65] + node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2344:45] + node _T_2183 = and(mhpmc_inc_r_d1[0], _T_2182) @[dec_tlu_ctl.scala 2344:43] + io.dec_tlu_perfcnt0 <= _T_2183 @[dec_tlu_ctl.scala 2344:22] + node _T_2184 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2345:88] + node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2345:67] + node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2345:65] + node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2345:45] + node _T_2188 = and(mhpmc_inc_r_d1[1], _T_2187) @[dec_tlu_ctl.scala 2345:43] + io.dec_tlu_perfcnt1 <= _T_2188 @[dec_tlu_ctl.scala 2345:22] + node _T_2189 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2346:88] + node _T_2190 = not(_T_2189) @[dec_tlu_ctl.scala 2346:67] + node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[dec_tlu_ctl.scala 2346:65] + node _T_2192 = not(_T_2191) @[dec_tlu_ctl.scala 2346:45] + node _T_2193 = and(mhpmc_inc_r_d1[2], _T_2192) @[dec_tlu_ctl.scala 2346:43] + io.dec_tlu_perfcnt2 <= _T_2193 @[dec_tlu_ctl.scala 2346:22] + node _T_2194 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2347:88] + node _T_2195 = not(_T_2194) @[dec_tlu_ctl.scala 2347:67] + node _T_2196 = and(perfcnt_halted_d1, _T_2195) @[dec_tlu_ctl.scala 2347:65] + node _T_2197 = not(_T_2196) @[dec_tlu_ctl.scala 2347:45] + node _T_2198 = and(mhpmc_inc_r_d1[3], _T_2197) @[dec_tlu_ctl.scala 2347:43] + io.dec_tlu_perfcnt3 <= _T_2198 @[dec_tlu_ctl.scala 2347:22] + node _T_2199 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2353:65] + node _T_2200 = eq(_T_2199, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2353:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2200) @[dec_tlu_ctl.scala 2353:43] + node _T_2201 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2354:23] + node _T_2202 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2354:61] + node _T_2203 = or(_T_2201, _T_2202) @[dec_tlu_ctl.scala 2354:39] + node _T_2204 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2354:86] + node mhpmc3_wr_en1 = and(_T_2203, _T_2204) @[dec_tlu_ctl.scala 2354:66] + node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2355:36] + node _T_2205 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2358:28] + node _T_2206 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2358:41] + node _T_2207 = cat(_T_2205, _T_2206) @[Cat.scala 29:58] + node _T_2208 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2209 = add(_T_2207, _T_2208) @[dec_tlu_ctl.scala 2358:49] + node _T_2210 = tail(_T_2209, 1) @[dec_tlu_ctl.scala 2358:49] + mhpmc3_incr <= _T_2210 @[dec_tlu_ctl.scala 2358:14] + node _T_2211 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2359:36] + node _T_2212 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2359:76] + node mhpmc3_ns = mux(_T_2211, io.dec_csr_wrdata_r, _T_2212) @[dec_tlu_ctl.scala 2359:21] + node _T_2213 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2361:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_26.io.en <= _T_2214 @[lib.scala 371:17] + rvclkhdr_26.io.en <= _T_2213 @[lib.scala 371:17] rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2215 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2215 <= mhpmc3_ns @[lib.scala 374:16] - mhpmc3 <= _T_2215 @[dec_tlu_ctl.scala 2360:9] - node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2362:66] - node _T_2217 = eq(_T_2216, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2362:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[dec_tlu_ctl.scala 2362:44] - node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2363:38] - node _T_2218 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2364:38] - node _T_2219 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2364:78] - node mhpmc3h_ns = mux(_T_2218, io.dec_csr_wrdata_r, _T_2219) @[dec_tlu_ctl.scala 2364:22] - node _T_2220 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2366:46] + reg _T_2214 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2214 <= mhpmc3_ns @[lib.scala 374:16] + mhpmc3 <= _T_2214 @[dec_tlu_ctl.scala 2361:9] + node _T_2215 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2363:66] + node _T_2216 = eq(_T_2215, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2363:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2216) @[dec_tlu_ctl.scala 2363:44] + node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2364:38] + node _T_2217 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2365:38] + node _T_2218 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2365:78] + node mhpmc3h_ns = mux(_T_2217, io.dec_csr_wrdata_r, _T_2218) @[dec_tlu_ctl.scala 2365:22] + node _T_2219 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_27.io.en <= _T_2220 @[lib.scala 371:17] + rvclkhdr_27.io.en <= _T_2219 @[lib.scala 371:17] rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2221 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2221 <= mhpmc3h_ns @[lib.scala 374:16] - mhpmc3h <= _T_2221 @[dec_tlu_ctl.scala 2366:10] - node _T_2222 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2371:65] - node _T_2223 = eq(_T_2222, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2371:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2223) @[dec_tlu_ctl.scala 2371:43] - node _T_2224 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2372:23] - node _T_2225 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2372:61] - node _T_2226 = or(_T_2224, _T_2225) @[dec_tlu_ctl.scala 2372:39] - node _T_2227 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2372:86] - node mhpmc4_wr_en1 = and(_T_2226, _T_2227) @[dec_tlu_ctl.scala 2372:66] - node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2373:36] - node _T_2228 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2377:28] - node _T_2229 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2377:41] - node _T_2230 = cat(_T_2228, _T_2229) @[Cat.scala 29:58] - node _T_2231 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2232 = add(_T_2230, _T_2231) @[dec_tlu_ctl.scala 2377:49] - node _T_2233 = tail(_T_2232, 1) @[dec_tlu_ctl.scala 2377:49] - mhpmc4_incr <= _T_2233 @[dec_tlu_ctl.scala 2377:14] - node _T_2234 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2378:36] - node _T_2235 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2378:63] - node _T_2236 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2378:82] - node mhpmc4_ns = mux(_T_2234, _T_2235, _T_2236) @[dec_tlu_ctl.scala 2378:21] - node _T_2237 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2379:43] + reg _T_2220 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2220 <= mhpmc3h_ns @[lib.scala 374:16] + mhpmc3h <= _T_2220 @[dec_tlu_ctl.scala 2367:10] + node _T_2221 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2372:65] + node _T_2222 = eq(_T_2221, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2372:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2222) @[dec_tlu_ctl.scala 2372:43] + node _T_2223 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2373:23] + node _T_2224 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2373:61] + node _T_2225 = or(_T_2223, _T_2224) @[dec_tlu_ctl.scala 2373:39] + node _T_2226 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2373:86] + node mhpmc4_wr_en1 = and(_T_2225, _T_2226) @[dec_tlu_ctl.scala 2373:66] + node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2374:36] + node _T_2227 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2378:28] + node _T_2228 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2378:41] + node _T_2229 = cat(_T_2227, _T_2228) @[Cat.scala 29:58] + node _T_2230 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2231 = add(_T_2229, _T_2230) @[dec_tlu_ctl.scala 2378:49] + node _T_2232 = tail(_T_2231, 1) @[dec_tlu_ctl.scala 2378:49] + mhpmc4_incr <= _T_2232 @[dec_tlu_ctl.scala 2378:14] + node _T_2233 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2379:36] + node _T_2234 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2379:63] + node _T_2235 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2379:82] + node mhpmc4_ns = mux(_T_2233, _T_2234, _T_2235) @[dec_tlu_ctl.scala 2379:21] + node _T_2236 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_28.io.en <= _T_2237 @[lib.scala 371:17] + rvclkhdr_28.io.en <= _T_2236 @[lib.scala 371:17] rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2238 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2238 <= mhpmc4_ns @[lib.scala 374:16] - mhpmc4 <= _T_2238 @[dec_tlu_ctl.scala 2379:9] - node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2381:66] - node _T_2240 = eq(_T_2239, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2381:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[dec_tlu_ctl.scala 2381:44] - node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2382:38] - node _T_2241 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2383:38] - node _T_2242 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2383:78] - node mhpmc4h_ns = mux(_T_2241, io.dec_csr_wrdata_r, _T_2242) @[dec_tlu_ctl.scala 2383:22] - node _T_2243 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2384:46] + reg _T_2237 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2237 <= mhpmc4_ns @[lib.scala 374:16] + mhpmc4 <= _T_2237 @[dec_tlu_ctl.scala 2380:9] + node _T_2238 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] + node _T_2239 = eq(_T_2238, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2382:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2239) @[dec_tlu_ctl.scala 2382:44] + node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2383:38] + node _T_2240 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] + node _T_2241 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] + node mhpmc4h_ns = mux(_T_2240, io.dec_csr_wrdata_r, _T_2241) @[dec_tlu_ctl.scala 2384:22] + node _T_2242 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2385:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_29.io.en <= _T_2243 @[lib.scala 371:17] + rvclkhdr_29.io.en <= _T_2242 @[lib.scala 371:17] rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2244 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2244 <= mhpmc4h_ns @[lib.scala 374:16] - mhpmc4h <= _T_2244 @[dec_tlu_ctl.scala 2384:10] - node _T_2245 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2390:65] - node _T_2246 = eq(_T_2245, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2390:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2246) @[dec_tlu_ctl.scala 2390:43] - node _T_2247 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2391:23] - node _T_2248 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2391:61] - node _T_2249 = or(_T_2247, _T_2248) @[dec_tlu_ctl.scala 2391:39] - node _T_2250 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2391:86] - node mhpmc5_wr_en1 = and(_T_2249, _T_2250) @[dec_tlu_ctl.scala 2391:66] - node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2392:36] - node _T_2251 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2394:28] - node _T_2252 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2394:41] - node _T_2253 = cat(_T_2251, _T_2252) @[Cat.scala 29:58] - node _T_2254 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2255 = add(_T_2253, _T_2254) @[dec_tlu_ctl.scala 2394:49] - node _T_2256 = tail(_T_2255, 1) @[dec_tlu_ctl.scala 2394:49] - mhpmc5_incr <= _T_2256 @[dec_tlu_ctl.scala 2394:14] - node _T_2257 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2395:36] - node _T_2258 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2395:76] - node mhpmc5_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[dec_tlu_ctl.scala 2395:21] - node _T_2259 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2397:43] + reg _T_2243 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2243 <= mhpmc4h_ns @[lib.scala 374:16] + mhpmc4h <= _T_2243 @[dec_tlu_ctl.scala 2385:10] + node _T_2244 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] + node _T_2245 = eq(_T_2244, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2391:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2245) @[dec_tlu_ctl.scala 2391:43] + node _T_2246 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] + node _T_2247 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2392:61] + node _T_2248 = or(_T_2246, _T_2247) @[dec_tlu_ctl.scala 2392:39] + node _T_2249 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2392:86] + node mhpmc5_wr_en1 = and(_T_2248, _T_2249) @[dec_tlu_ctl.scala 2392:66] + node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2393:36] + node _T_2250 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2395:28] + node _T_2251 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2395:41] + node _T_2252 = cat(_T_2250, _T_2251) @[Cat.scala 29:58] + node _T_2253 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2254 = add(_T_2252, _T_2253) @[dec_tlu_ctl.scala 2395:49] + node _T_2255 = tail(_T_2254, 1) @[dec_tlu_ctl.scala 2395:49] + mhpmc5_incr <= _T_2255 @[dec_tlu_ctl.scala 2395:14] + node _T_2256 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] + node _T_2257 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] + node mhpmc5_ns = mux(_T_2256, io.dec_csr_wrdata_r, _T_2257) @[dec_tlu_ctl.scala 2396:21] + node _T_2258 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_30.io.en <= _T_2259 @[lib.scala 371:17] + rvclkhdr_30.io.en <= _T_2258 @[lib.scala 371:17] rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2260 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2260 <= mhpmc5_ns @[lib.scala 374:16] - mhpmc5 <= _T_2260 @[dec_tlu_ctl.scala 2397:9] - node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2399:66] - node _T_2262 = eq(_T_2261, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2399:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[dec_tlu_ctl.scala 2399:44] - node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2400:38] - node _T_2263 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2401:38] - node _T_2264 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2401:78] - node mhpmc5h_ns = mux(_T_2263, io.dec_csr_wrdata_r, _T_2264) @[dec_tlu_ctl.scala 2401:22] - node _T_2265 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2403:46] + reg _T_2259 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2259 <= mhpmc5_ns @[lib.scala 374:16] + mhpmc5 <= _T_2259 @[dec_tlu_ctl.scala 2398:9] + node _T_2260 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] + node _T_2261 = eq(_T_2260, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2400:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2261) @[dec_tlu_ctl.scala 2400:44] + node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2401:38] + node _T_2262 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] + node _T_2263 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] + node mhpmc5h_ns = mux(_T_2262, io.dec_csr_wrdata_r, _T_2263) @[dec_tlu_ctl.scala 2402:22] + node _T_2264 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset rvclkhdr_31.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_31.io.en <= _T_2265 @[lib.scala 371:17] + rvclkhdr_31.io.en <= _T_2264 @[lib.scala 371:17] rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2266 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2266 <= mhpmc5h_ns @[lib.scala 374:16] - mhpmc5h <= _T_2266 @[dec_tlu_ctl.scala 2403:10] - node _T_2267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2408:65] - node _T_2268 = eq(_T_2267, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2408:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2268) @[dec_tlu_ctl.scala 2408:43] - node _T_2269 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2409:23] - node _T_2270 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2409:61] - node _T_2271 = or(_T_2269, _T_2270) @[dec_tlu_ctl.scala 2409:39] - node _T_2272 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2409:86] - node mhpmc6_wr_en1 = and(_T_2271, _T_2272) @[dec_tlu_ctl.scala 2409:66] - node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2410:36] - node _T_2273 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2412:28] - node _T_2274 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2412:41] - node _T_2275 = cat(_T_2273, _T_2274) @[Cat.scala 29:58] - node _T_2276 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2277 = add(_T_2275, _T_2276) @[dec_tlu_ctl.scala 2412:49] - node _T_2278 = tail(_T_2277, 1) @[dec_tlu_ctl.scala 2412:49] - mhpmc6_incr <= _T_2278 @[dec_tlu_ctl.scala 2412:14] - node _T_2279 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2413:36] - node _T_2280 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2413:76] - node mhpmc6_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[dec_tlu_ctl.scala 2413:21] - node _T_2281 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2415:43] + reg _T_2265 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2265 <= mhpmc5h_ns @[lib.scala 374:16] + mhpmc5h <= _T_2265 @[dec_tlu_ctl.scala 2404:10] + node _T_2266 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2409:65] + node _T_2267 = eq(_T_2266, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2409:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2267) @[dec_tlu_ctl.scala 2409:43] + node _T_2268 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2410:23] + node _T_2269 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2410:61] + node _T_2270 = or(_T_2268, _T_2269) @[dec_tlu_ctl.scala 2410:39] + node _T_2271 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2410:86] + node mhpmc6_wr_en1 = and(_T_2270, _T_2271) @[dec_tlu_ctl.scala 2410:66] + node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2411:36] + node _T_2272 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2413:28] + node _T_2273 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2413:41] + node _T_2274 = cat(_T_2272, _T_2273) @[Cat.scala 29:58] + node _T_2275 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2276 = add(_T_2274, _T_2275) @[dec_tlu_ctl.scala 2413:49] + node _T_2277 = tail(_T_2276, 1) @[dec_tlu_ctl.scala 2413:49] + mhpmc6_incr <= _T_2277 @[dec_tlu_ctl.scala 2413:14] + node _T_2278 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2414:36] + node _T_2279 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2414:76] + node mhpmc6_ns = mux(_T_2278, io.dec_csr_wrdata_r, _T_2279) @[dec_tlu_ctl.scala 2414:21] + node _T_2280 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2416:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset rvclkhdr_32.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_32.io.en <= _T_2281 @[lib.scala 371:17] + rvclkhdr_32.io.en <= _T_2280 @[lib.scala 371:17] rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2282 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2282 <= mhpmc6_ns @[lib.scala 374:16] - mhpmc6 <= _T_2282 @[dec_tlu_ctl.scala 2415:9] - node _T_2283 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2417:66] - node _T_2284 = eq(_T_2283, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2417:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2284) @[dec_tlu_ctl.scala 2417:44] - node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2418:38] - node _T_2285 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2419:38] - node _T_2286 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2419:78] - node mhpmc6h_ns = mux(_T_2285, io.dec_csr_wrdata_r, _T_2286) @[dec_tlu_ctl.scala 2419:22] - node _T_2287 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2421:46] + reg _T_2281 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2281 <= mhpmc6_ns @[lib.scala 374:16] + mhpmc6 <= _T_2281 @[dec_tlu_ctl.scala 2416:9] + node _T_2282 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2418:66] + node _T_2283 = eq(_T_2282, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2418:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2283) @[dec_tlu_ctl.scala 2418:44] + node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2419:38] + node _T_2284 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2420:38] + node _T_2285 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2420:78] + node mhpmc6h_ns = mux(_T_2284, io.dec_csr_wrdata_r, _T_2285) @[dec_tlu_ctl.scala 2420:22] + node _T_2286 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2422:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset rvclkhdr_33.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_33.io.en <= _T_2287 @[lib.scala 371:17] + rvclkhdr_33.io.en <= _T_2286 @[lib.scala 371:17] rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2288 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2288 <= mhpmc6h_ns @[lib.scala 374:16] - mhpmc6h <= _T_2288 @[dec_tlu_ctl.scala 2421:10] - node _T_2289 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2428:50] - node _T_2290 = gt(_T_2289, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2428:56] - node _T_2291 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2428:93] - node _T_2292 = orr(_T_2291) @[dec_tlu_ctl.scala 2428:102] - node _T_2293 = or(_T_2290, _T_2292) @[dec_tlu_ctl.scala 2428:71] - node _T_2294 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2428:141] - node event_saturate_r = mux(_T_2293, UInt<10>("h0204"), _T_2294) @[dec_tlu_ctl.scala 2428:28] - node _T_2295 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2430:63] - node _T_2296 = eq(_T_2295, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2430:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2296) @[dec_tlu_ctl.scala 2430:41] - node _T_2297 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2432:80] - reg _T_2298 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2297 : @[Reg.scala 28:19] - _T_2298 <= event_saturate_r @[Reg.scala 28:23] + reg _T_2287 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2287 <= mhpmc6h_ns @[lib.scala 374:16] + mhpmc6h <= _T_2287 @[dec_tlu_ctl.scala 2422:10] + node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:50] + node _T_2289 = gt(_T_2288, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2429:56] + node _T_2290 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2429:93] + node _T_2291 = orr(_T_2290) @[dec_tlu_ctl.scala 2429:102] + node _T_2292 = or(_T_2289, _T_2291) @[dec_tlu_ctl.scala 2429:71] + node _T_2293 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:141] + node event_saturate_r = mux(_T_2292, UInt<10>("h0204"), _T_2293) @[dec_tlu_ctl.scala 2429:28] + node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2431:63] + node _T_2295 = eq(_T_2294, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2431:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2431:41] + node _T_2296 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2433:80] + reg _T_2297 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2296 : @[Reg.scala 28:19] + _T_2297 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2298 @[dec_tlu_ctl.scala 2432:9] - node _T_2299 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2437:63] - node _T_2300 = eq(_T_2299, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2437:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2300) @[dec_tlu_ctl.scala 2437:41] - node _T_2301 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2438:80] - reg _T_2302 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2301 : @[Reg.scala 28:19] - _T_2302 <= event_saturate_r @[Reg.scala 28:23] + mhpme3 <= _T_2297 @[dec_tlu_ctl.scala 2433:9] + node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2438:63] + node _T_2299 = eq(_T_2298, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2438:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2438:41] + node _T_2300 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2439:80] + reg _T_2301 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2300 : @[Reg.scala 28:19] + _T_2301 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2302 @[dec_tlu_ctl.scala 2438:9] - node _T_2303 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2444:63] - node _T_2304 = eq(_T_2303, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2444:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2304) @[dec_tlu_ctl.scala 2444:41] - node _T_2305 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2445:80] - reg _T_2306 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2305 : @[Reg.scala 28:19] - _T_2306 <= event_saturate_r @[Reg.scala 28:23] + mhpme4 <= _T_2301 @[dec_tlu_ctl.scala 2439:9] + node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2445:63] + node _T_2303 = eq(_T_2302, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2445:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2445:41] + node _T_2304 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2446:80] + reg _T_2305 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2304 : @[Reg.scala 28:19] + _T_2305 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2306 @[dec_tlu_ctl.scala 2445:9] - node _T_2307 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2451:63] - node _T_2308 = eq(_T_2307, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2451:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2308) @[dec_tlu_ctl.scala 2451:41] - node _T_2309 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2452:80] - reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2309 : @[Reg.scala 28:19] - _T_2310 <= event_saturate_r @[Reg.scala 28:23] + mhpme5 <= _T_2305 @[dec_tlu_ctl.scala 2446:9] + node _T_2306 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2452:63] + node _T_2307 = eq(_T_2306, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2452:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2307) @[dec_tlu_ctl.scala 2452:41] + node _T_2308 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2453:80] + reg _T_2309 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2308 : @[Reg.scala 28:19] + _T_2309 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2310 @[dec_tlu_ctl.scala 2452:9] - node _T_2311 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2468:70] - node _T_2312 = eq(_T_2311, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2468:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2312) @[dec_tlu_ctl.scala 2468:48] - node _T_2313 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2470:54] + mhpme6 <= _T_2309 @[dec_tlu_ctl.scala 2453:9] + node _T_2310 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2469:70] + node _T_2311 = eq(_T_2310, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2469:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2311) @[dec_tlu_ctl.scala 2469:48] + node _T_2312 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2471:54] wire temp_ncount0 : UInt<1> - temp_ncount0 <= _T_2313 - node _T_2314 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2471:54] + temp_ncount0 <= _T_2312 + node _T_2313 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2472:54] wire temp_ncount1 : UInt<1> - temp_ncount1 <= _T_2314 - node _T_2315 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2472:55] + temp_ncount1 <= _T_2313 + node _T_2314 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2473:55] wire temp_ncount6_2 : UInt<5> - temp_ncount6_2 <= _T_2315 - node _T_2316 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2473:74] - node _T_2317 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2473:103] - reg _T_2318 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2317 : @[Reg.scala 28:19] - _T_2318 <= _T_2316 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2314 + node _T_2315 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2474:74] + node _T_2316 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2474:103] + reg _T_2317 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2316 : @[Reg.scala 28:19] + _T_2317 <= _T_2315 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2318 @[dec_tlu_ctl.scala 2473:17] - node _T_2319 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2475:72] - node _T_2320 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:99] - reg _T_2321 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2320 : @[Reg.scala 28:19] - _T_2321 <= _T_2319 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2317 @[dec_tlu_ctl.scala 2474:17] + node _T_2318 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2476:72] + node _T_2319 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2476:99] + reg _T_2320 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2319 : @[Reg.scala 28:19] + _T_2320 <= _T_2318 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2321 @[dec_tlu_ctl.scala 2475:15] - node _T_2322 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2323 = cat(_T_2322, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2323 @[dec_tlu_ctl.scala 2476:16] - node _T_2324 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2483:51] - node _T_2325 = or(_T_2324, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2483:78] - node _T_2326 = or(_T_2325, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2483:104] - node _T_2327 = or(_T_2326, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2483:130] - node _T_2328 = or(_T_2327, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2484:32] - node _T_2329 = or(_T_2328, io.clk_override) @[dec_tlu_ctl.scala 2484:59] - node _T_2330 = bits(_T_2329, 0, 0) @[dec_tlu_ctl.scala 2484:78] + temp_ncount0 <= _T_2320 @[dec_tlu_ctl.scala 2476:15] + node _T_2321 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2322 = cat(_T_2321, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2322 @[dec_tlu_ctl.scala 2477:16] + node _T_2323 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2484:51] + node _T_2324 = or(_T_2323, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2484:78] + node _T_2325 = or(_T_2324, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2484:104] + node _T_2326 = or(_T_2325, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2484:130] + node _T_2327 = or(_T_2326, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2485:32] + node _T_2328 = or(_T_2327, io.clk_override) @[dec_tlu_ctl.scala 2485:59] + node _T_2329 = bits(_T_2328, 0, 0) @[dec_tlu_ctl.scala 2485:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_34.io.en <= _T_2330 @[lib.scala 345:16] + rvclkhdr_34.io.en <= _T_2329 @[lib.scala 345:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2486:62] - _T_2331 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2486:62] - io.dec_tlu_i0_valid_wb1 <= _T_2331 @[dec_tlu_ctl.scala 2486:30] - node _T_2332 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2487:91] - node _T_2333 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2487:137] - node _T_2334 = and(io.trigger_hit_r_d1, _T_2333) @[dec_tlu_ctl.scala 2487:135] - node _T_2335 = or(_T_2332, _T_2334) @[dec_tlu_ctl.scala 2487:112] - reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] - _T_2336 <= _T_2335 @[dec_tlu_ctl.scala 2487:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2487:30] - reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] - _T_2337 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2488:62] - io.dec_tlu_exc_cause_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2488:30] - reg _T_2338 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] - _T_2338 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2489:62] - io.dec_tlu_int_valid_wb1 <= _T_2338 @[dec_tlu_ctl.scala 2489:30] - io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2491:24] - node _T_2339 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2497:61] - node _T_2340 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2498:42] - node _T_2341 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2499:40] - node _T_2342 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2500:39] - node _T_2343 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2501:40] - node _T_2344 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2345 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2502:40] - node _T_2346 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2502:103] - node _T_2347 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2502:128] - node _T_2348 = cat(UInt<3>("h00"), _T_2347) @[Cat.scala 29:58] - node _T_2349 = cat(_T_2348, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2350 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] - node _T_2351 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58] - node _T_2353 = cat(_T_2352, _T_2349) @[Cat.scala 29:58] - node _T_2354 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2503:38] - node _T_2355 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2503:70] - node _T_2356 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2503:96] - node _T_2357 = cat(_T_2355, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2358 = cat(_T_2357, _T_2356) @[Cat.scala 29:58] - node _T_2359 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2504:36] - node _T_2360 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2504:78] - node _T_2361 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2504:102] - node _T_2362 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2504:123] - node _T_2363 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2504:144] - node _T_2364 = cat(_T_2363, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2365 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2366 = cat(_T_2365, _T_2364) @[Cat.scala 29:58] - node _T_2367 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2368 = cat(UInt<1>("h00"), _T_2360) @[Cat.scala 29:58] - node _T_2369 = cat(_T_2368, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2370 = cat(_T_2369, _T_2367) @[Cat.scala 29:58] - node _T_2371 = cat(_T_2370, _T_2366) @[Cat.scala 29:58] - node _T_2372 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2505:36] - node _T_2373 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2505:75] - node _T_2374 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2505:96] - node _T_2375 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2505:114] - node _T_2376 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2505:132] - node _T_2377 = cat(_T_2376, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2378 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2379 = cat(_T_2378, _T_2377) @[Cat.scala 29:58] - node _T_2380 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2381 = cat(UInt<1>("h00"), _T_2373) @[Cat.scala 29:58] - node _T_2382 = cat(_T_2381, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2383 = cat(_T_2382, _T_2380) @[Cat.scala 29:58] - node _T_2384 = cat(_T_2383, _T_2379) @[Cat.scala 29:58] - node _T_2385 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2506:40] - node _T_2386 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2506:65] - node _T_2387 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2507:40] - node _T_2388 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2507:69] - node _T_2389 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2508:42] - node _T_2390 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2508:72] - node _T_2391 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2509:42] - node _T_2392 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2509:72] - node _T_2393 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2510:41] - node _T_2394 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2510:66] - node _T_2395 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2511:37] - node _T_2396 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2397 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2512:39] - node _T_2398 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2512:64] - node _T_2399 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2513:40] - node _T_2400 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2513:80] - node _T_2401 = cat(UInt<28>("h00"), _T_2400) @[Cat.scala 29:58] - node _T_2402 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2514:38] - node _T_2403 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2514:63] - node _T_2404 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2515:37] - node _T_2405 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2515:62] - node _T_2406 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2516:39] - node _T_2407 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2516:64] - node _T_2408 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2517:38] - node _T_2409 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2410 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2518:39] - node _T_2411 = cat(meivt, meihap) @[Cat.scala 29:58] - node _T_2412 = cat(_T_2411, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2413 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2519:41] - node _T_2414 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2519:81] - node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58] - node _T_2416 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] - node _T_2417 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] - node _T_2418 = cat(UInt<28>("h00"), _T_2417) @[Cat.scala 29:58] - node _T_2419 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2521:38] - node _T_2420 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2521:78] - node _T_2421 = cat(UInt<28>("h00"), _T_2420) @[Cat.scala 29:58] - node _T_2422 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2522:37] - node _T_2423 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2522:77] - node _T_2424 = cat(UInt<23>("h00"), _T_2423) @[Cat.scala 29:58] - node _T_2425 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2523:37] - node _T_2426 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2523:77] - node _T_2427 = cat(UInt<13>("h00"), _T_2426) @[Cat.scala 29:58] - node _T_2428 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2524:37] - node _T_2429 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2524:85] - node _T_2430 = cat(UInt<16>("h04000"), _T_2429) @[Cat.scala 29:58] - node _T_2431 = cat(_T_2430, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2432 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2525:36] - node _T_2433 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2434 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2526:39] - node _T_2435 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2526:64] - node _T_2436 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2527:40] - node _T_2437 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2527:65] - node _T_2438 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2528:39] - node _T_2439 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2528:64] - node _T_2440 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2529:41] - node _T_2441 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2529:80] - node _T_2442 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2529:104] - node _T_2443 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2529:131] - node _T_2444 = cat(UInt<3>("h00"), _T_2443) @[Cat.scala 29:58] - node _T_2445 = cat(_T_2444, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2446 = cat(UInt<2>("h00"), _T_2442) @[Cat.scala 29:58] - node _T_2447 = cat(UInt<7>("h00"), _T_2441) @[Cat.scala 29:58] - node _T_2448 = cat(_T_2447, _T_2446) @[Cat.scala 29:58] - node _T_2449 = cat(_T_2448, _T_2445) @[Cat.scala 29:58] - node _T_2450 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2530:38] - node _T_2451 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2530:78] - node _T_2452 = cat(UInt<30>("h00"), _T_2451) @[Cat.scala 29:58] - node _T_2453 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2531:40] - node _T_2454 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2531:74] - node _T_2455 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2532:40] - node _T_2456 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] - node _T_2457 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2533:39] - node _T_2458 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2533:64] - node _T_2459 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2534:41] - node _T_2460 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2534:66] - node _T_2461 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] - node _T_2462 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] - node _T_2463 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2536:39] - node _T_2464 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2536:64] - node _T_2465 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2537:39] - node _T_2466 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2537:64] - node _T_2467 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2538:39] - node _T_2468 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2538:64] - node _T_2469 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2539:39] - node _T_2470 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2539:64] - node _T_2471 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2540:40] - node _T_2472 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2540:65] - node _T_2473 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2541:40] - node _T_2474 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2541:65] - node _T_2475 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2542:40] - node _T_2476 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2542:65] - node _T_2477 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2543:40] - node _T_2478 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2543:65] - node _T_2479 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2544:38] - node _T_2480 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2544:78] - node _T_2481 = cat(UInt<26>("h00"), _T_2480) @[Cat.scala 29:58] - node _T_2482 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2545:38] - node _T_2483 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2545:78] - node _T_2484 = cat(UInt<30>("h00"), _T_2483) @[Cat.scala 29:58] - node _T_2485 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2546:39] - node _T_2486 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2546:79] - node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] - node _T_2488 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2547:39] - node _T_2489 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2547:79] - node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58] - node _T_2491 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2548:39] - node _T_2492 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2548:78] - node _T_2493 = cat(UInt<22>("h00"), _T_2492) @[Cat.scala 29:58] - node _T_2494 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2549:39] - node _T_2495 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2549:78] - node _T_2496 = cat(UInt<22>("h00"), _T_2495) @[Cat.scala 29:58] - node _T_2497 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2550:46] - node _T_2498 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2550:86] - node _T_2499 = cat(UInt<25>("h00"), _T_2498) @[Cat.scala 29:58] - node _T_2500 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2551:37] - node _T_2501 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] - node _T_2502 = cat(_T_2501, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2503 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2552:37] - node _T_2504 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2552:76] - node _T_2505 = mux(_T_2339, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2506 = mux(_T_2340, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2507 = mux(_T_2341, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2508 = mux(_T_2342, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2509 = mux(_T_2343, _T_2344, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2510 = mux(_T_2345, _T_2353, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2511 = mux(_T_2354, _T_2358, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2512 = mux(_T_2359, _T_2371, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2513 = mux(_T_2372, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2514 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2515 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2516 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2517 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2518 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2519 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2520 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2521 = mux(_T_2399, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2522 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2523 = mux(_T_2404, _T_2405, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2524 = mux(_T_2406, _T_2407, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2525 = mux(_T_2408, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2526 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2527 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2528 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2529 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2530 = mux(_T_2422, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2531 = mux(_T_2425, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2532 = mux(_T_2428, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2533 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2534 = mux(_T_2434, _T_2435, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2535 = mux(_T_2436, _T_2437, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2536 = mux(_T_2438, _T_2439, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2537 = mux(_T_2440, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2538 = mux(_T_2450, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2539 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2540 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2541 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2542 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2543 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2544 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2545 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2546 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2547 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2548 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2549 = mux(_T_2473, _T_2474, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2550 = mux(_T_2475, _T_2476, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2551 = mux(_T_2477, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2552 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2553 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2554 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2555 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2556 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2557 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2558 = mux(_T_2497, _T_2499, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2559 = mux(_T_2500, _T_2502, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2560 = mux(_T_2503, _T_2504, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2561 = or(_T_2505, _T_2506) @[Mux.scala 27:72] + reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] + _T_2330 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2487:62] + io.dec_tlu_i0_valid_wb1 <= _T_2330 @[dec_tlu_ctl.scala 2487:30] + node _T_2331 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2488:91] + node _T_2332 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2488:137] + node _T_2333 = and(io.trigger_hit_r_d1, _T_2332) @[dec_tlu_ctl.scala 2488:135] + node _T_2334 = or(_T_2331, _T_2333) @[dec_tlu_ctl.scala 2488:112] + reg _T_2335 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] + _T_2335 <= _T_2334 @[dec_tlu_ctl.scala 2488:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2335 @[dec_tlu_ctl.scala 2488:30] + reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] + _T_2336 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2489:62] + io.dec_tlu_exc_cause_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2489:30] + reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] + _T_2337 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2490:62] + io.dec_tlu_int_valid_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2490:30] + io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2492:24] + node _T_2338 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2498:61] + node _T_2339 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2499:42] + node _T_2340 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2500:40] + node _T_2341 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2501:39] + node _T_2342 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2502:40] + node _T_2343 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2344 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:40] + node _T_2345 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2503:103] + node _T_2346 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:128] + node _T_2347 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] + node _T_2348 = cat(_T_2347, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2349 = cat(UInt<3>("h00"), _T_2345) @[Cat.scala 29:58] + node _T_2350 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2351 = cat(_T_2350, _T_2349) @[Cat.scala 29:58] + node _T_2352 = cat(_T_2351, _T_2348) @[Cat.scala 29:58] + node _T_2353 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:38] + node _T_2354 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2504:70] + node _T_2355 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:96] + node _T_2356 = cat(_T_2354, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2357 = cat(_T_2356, _T_2355) @[Cat.scala 29:58] + node _T_2358 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2505:36] + node _T_2359 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2505:78] + node _T_2360 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2505:102] + node _T_2361 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2505:123] + node _T_2362 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2505:144] + node _T_2363 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2364 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2365 = cat(_T_2364, _T_2363) @[Cat.scala 29:58] + node _T_2366 = cat(_T_2360, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2367 = cat(UInt<1>("h00"), _T_2359) @[Cat.scala 29:58] + node _T_2368 = cat(_T_2367, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2369 = cat(_T_2368, _T_2366) @[Cat.scala 29:58] + node _T_2370 = cat(_T_2369, _T_2365) @[Cat.scala 29:58] + node _T_2371 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2506:36] + node _T_2372 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2506:75] + node _T_2373 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2506:96] + node _T_2374 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2506:114] + node _T_2375 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2506:132] + node _T_2376 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2377 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2378 = cat(_T_2377, _T_2376) @[Cat.scala 29:58] + node _T_2379 = cat(_T_2373, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2380 = cat(UInt<1>("h00"), _T_2372) @[Cat.scala 29:58] + node _T_2381 = cat(_T_2380, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2382 = cat(_T_2381, _T_2379) @[Cat.scala 29:58] + node _T_2383 = cat(_T_2382, _T_2378) @[Cat.scala 29:58] + node _T_2384 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2507:40] + node _T_2385 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2507:65] + node _T_2386 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2508:40] + node _T_2387 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2508:69] + node _T_2388 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2509:42] + node _T_2389 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2509:72] + node _T_2390 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2510:42] + node _T_2391 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2510:72] + node _T_2392 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2511:41] + node _T_2393 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2511:66] + node _T_2394 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2512:37] + node _T_2395 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2396 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2513:39] + node _T_2397 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2513:64] + node _T_2398 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2514:40] + node _T_2399 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2514:80] + node _T_2400 = cat(UInt<28>("h00"), _T_2399) @[Cat.scala 29:58] + node _T_2401 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2515:38] + node _T_2402 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2515:63] + node _T_2403 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2516:37] + node _T_2404 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2516:62] + node _T_2405 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2517:39] + node _T_2406 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2517:64] + node _T_2407 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2518:38] + node _T_2408 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2409 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2519:39] + node _T_2410 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2411 = cat(_T_2410, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2412 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] + node _T_2413 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] + node _T_2414 = cat(UInt<28>("h00"), _T_2413) @[Cat.scala 29:58] + node _T_2415 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] + node _T_2416 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] + node _T_2417 = cat(UInt<28>("h00"), _T_2416) @[Cat.scala 29:58] + node _T_2418 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2522:38] + node _T_2419 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2522:78] + node _T_2420 = cat(UInt<28>("h00"), _T_2419) @[Cat.scala 29:58] + node _T_2421 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2523:37] + node _T_2422 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2523:77] + node _T_2423 = cat(UInt<23>("h00"), _T_2422) @[Cat.scala 29:58] + node _T_2424 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2524:37] + node _T_2425 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2524:77] + node _T_2426 = cat(UInt<13>("h00"), _T_2425) @[Cat.scala 29:58] + node _T_2427 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2525:37] + node _T_2428 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2525:85] + node _T_2429 = cat(UInt<16>("h04000"), _T_2428) @[Cat.scala 29:58] + node _T_2430 = cat(_T_2429, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2431 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2526:36] + node _T_2432 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2433 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2527:39] + node _T_2434 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2527:64] + node _T_2435 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2528:40] + node _T_2436 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2528:65] + node _T_2437 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2529:39] + node _T_2438 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2529:64] + node _T_2439 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2530:41] + node _T_2440 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2530:80] + node _T_2441 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2530:104] + node _T_2442 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2530:131] + node _T_2443 = cat(UInt<3>("h00"), _T_2442) @[Cat.scala 29:58] + node _T_2444 = cat(_T_2443, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2445 = cat(UInt<2>("h00"), _T_2441) @[Cat.scala 29:58] + node _T_2446 = cat(UInt<7>("h00"), _T_2440) @[Cat.scala 29:58] + node _T_2447 = cat(_T_2446, _T_2445) @[Cat.scala 29:58] + node _T_2448 = cat(_T_2447, _T_2444) @[Cat.scala 29:58] + node _T_2449 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2531:38] + node _T_2450 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2531:78] + node _T_2451 = cat(UInt<30>("h00"), _T_2450) @[Cat.scala 29:58] + node _T_2452 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2532:40] + node _T_2453 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] + node _T_2454 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2533:40] + node _T_2455 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] + node _T_2456 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2534:39] + node _T_2457 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2534:64] + node _T_2458 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] + node _T_2459 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] + node _T_2460 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] + node _T_2461 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] + node _T_2462 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2537:39] + node _T_2463 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2537:64] + node _T_2464 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2538:39] + node _T_2465 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2538:64] + node _T_2466 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2539:39] + node _T_2467 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2539:64] + node _T_2468 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2540:39] + node _T_2469 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2540:64] + node _T_2470 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2541:40] + node _T_2471 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2541:65] + node _T_2472 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2542:40] + node _T_2473 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2542:65] + node _T_2474 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2543:40] + node _T_2475 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2543:65] + node _T_2476 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2544:40] + node _T_2477 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2544:65] + node _T_2478 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2545:38] + node _T_2479 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2545:78] + node _T_2480 = cat(UInt<26>("h00"), _T_2479) @[Cat.scala 29:58] + node _T_2481 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2546:38] + node _T_2482 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2546:78] + node _T_2483 = cat(UInt<30>("h00"), _T_2482) @[Cat.scala 29:58] + node _T_2484 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2547:39] + node _T_2485 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2547:79] + node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58] + node _T_2487 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2548:39] + node _T_2488 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2548:79] + node _T_2489 = cat(UInt<22>("h00"), _T_2488) @[Cat.scala 29:58] + node _T_2490 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2549:39] + node _T_2491 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2549:78] + node _T_2492 = cat(UInt<22>("h00"), _T_2491) @[Cat.scala 29:58] + node _T_2493 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2550:39] + node _T_2494 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2550:78] + node _T_2495 = cat(UInt<22>("h00"), _T_2494) @[Cat.scala 29:58] + node _T_2496 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2551:46] + node _T_2497 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2551:86] + node _T_2498 = cat(UInt<25>("h00"), _T_2497) @[Cat.scala 29:58] + node _T_2499 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2552:37] + node _T_2500 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2501 = cat(_T_2500, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2502 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2553:37] + node _T_2503 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2553:76] + node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2341, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2358, _T_2370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2371, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2390, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2398, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2401, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2403, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2405, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2407, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2418, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2421, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2424, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2427, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2431, _T_2432, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2433, _T_2434, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2435, _T_2436, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2437, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2439, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2449, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2470, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2472, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2474, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2476, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2553 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2554 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2555 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2556 = mux(_T_2493, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2557 = mux(_T_2496, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2558 = mux(_T_2499, _T_2501, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2559 = mux(_T_2502, _T_2503, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2560 = or(_T_2504, _T_2505) @[Mux.scala 27:72] + node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72] @@ -76113,1691 +76113,1690 @@ circuit quasar : node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72] node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72] node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72] - node _T_2615 = or(_T_2614, _T_2560) @[Mux.scala 27:72] - wire _T_2616 : UInt @[Mux.scala 27:72] - _T_2616 <= _T_2615 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2616 @[dec_tlu_ctl.scala 2496:21] + wire _T_2615 : UInt @[Mux.scala 27:72] + _T_2615 <= _T_2614 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2615 @[dec_tlu_ctl.scala 2497:21] module dec_decode_csr_read : input clock : Clock input reset : AsyncReset output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} - node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2568:198] - node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2568:198] - node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2568:198] - node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2570:57] - node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2568:198] - node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2568:198] - node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2571:57] - node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2568:198] - node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2568:198] - node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2572:57] - node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2568:198] - node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2568:198] - node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2573:57] - node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2568:198] - node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2574:57] - node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2568:198] - node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2568:198] - node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2568:198] - node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2575:57] - node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2568:198] - node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2568:198] - node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2568:198] - node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2576:57] - node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2568:198] - node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2577:65] - node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2568:198] - node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2568:198] - node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2568:198] - node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2578:65] - node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2568:198] - node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2568:198] - node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2568:198] - node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2568:198] - node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2579:57] - node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2568:198] - node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2568:198] - node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2568:198] - node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2568:198] - node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2568:198] - node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2580:57] - node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2568:198] - node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2568:198] - node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2568:198] - node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2568:198] - node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2568:198] - node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2581:57] - node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2568:198] - node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2568:198] - node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2568:198] - node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2568:198] - node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2568:198] - node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2582:57] - node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2568:198] - node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2568:198] - node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2568:198] - node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2583:57] - node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2568:198] - node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2568:198] - node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2584:57] - node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2568:198] - node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2568:198] - node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2585:57] - node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2568:198] - node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2586:57] - node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2568:198] - node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2568:198] - node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2587:57] - node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2568:198] - node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2568:198] - node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2568:198] - node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2568:198] - node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2588:57] - node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2568:198] - node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2568:198] - node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2568:198] - node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2589:57] - node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2568:198] - node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2568:198] - node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2590:57] - node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2568:198] - node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2591:57] - node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2568:198] - node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2568:198] - node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2568:198] - node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2568:198] - node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2592:57] - node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2568:198] - node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2568:198] - node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2593:57] - node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2568:198] - node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2594:57] - node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2568:198] - node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2568:198] - node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2595:57] - node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2568:198] - node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2568:198] - node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2568:198] - node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2596:57] - node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2568:198] - node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2568:198] - node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2597:57] - node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2568:198] - node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2568:198] - node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2568:198] - node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2598:57] - node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2568:198] - node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2568:198] - node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2568:198] - node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2599:65] - node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2568:198] - node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2568:198] - node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2568:198] - node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2600:57] - node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2568:198] - node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2568:198] - node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2601:57] - node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2568:198] - node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2568:198] - node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2602:57] - node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2568:198] - node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2568:198] - node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2568:198] - node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2568:198] - node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2603:57] - node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2568:198] - node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2568:198] - node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2568:198] - node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2568:198] - node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2568:198] - node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2604:57] - node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2568:198] - node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2568:198] - node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2568:198] - node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2568:198] - node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2605:57] - node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2568:198] - node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2568:198] - node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2568:198] - node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2568:198] - node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2568:198] - node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2606:57] - node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2568:198] - node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2568:198] - node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2568:198] - node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2568:198] - node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2607:57] - node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2568:198] - node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2568:198] - node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2568:198] - node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2568:198] - node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2568:198] - node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2608:57] - node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2568:198] - node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2568:198] - node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2568:198] - node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2568:198] - node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2609:57] - node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2568:198] - node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2568:198] - node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2568:198] - node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2568:198] - node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2568:198] - node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2610:57] - node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2568:198] - node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2568:198] - node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2568:198] - node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2568:198] - node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2611:57] - node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2568:198] - node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2568:198] - node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2568:198] - node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2568:198] - node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2612:57] - node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2568:198] - node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2568:198] - node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2568:198] - node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2568:198] - node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2613:57] - node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2568:198] - node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2568:198] - node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2568:198] - node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2568:198] - node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2614:57] - node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2568:198] - node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2568:198] - node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2568:198] - node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2568:198] - node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2615:49] - node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2568:198] - node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2568:198] - node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2568:198] - node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2616:57] - node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2568:198] - node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2568:198] - node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2568:198] - node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2617:57] - node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2568:198] - node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2568:198] - node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2568:198] - node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2618:57] - node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2568:198] - node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2568:198] - node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2568:198] - node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2619:57] - node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2568:198] - node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2568:198] - node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2568:198] - node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2620:57] - node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2568:198] - node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2568:198] - node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2621:57] - node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2568:198] - node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2568:198] - node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2568:198] - node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2622:57] - node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2568:198] - node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2568:198] - node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2568:198] - node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2568:198] - node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2623:57] - node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2568:198] - node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2568:198] - node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2624:57] - node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2568:198] - node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2568:198] - node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2625:57] - node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2568:198] - node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2568:198] - node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2568:198] - node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2626:57] - node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2568:198] - node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2568:198] - node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2627:57] - node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2568:198] - node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2568:198] - node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2628:57] - node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2568:198] - node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2568:198] - node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2568:198] - node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2629:57] - node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2568:198] - node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2568:198] - node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2630:57] - node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2568:198] - node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2568:198] - node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2568:198] - node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2568:198] - node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2631:57] - node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2568:198] - node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2568:198] - node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2632:57] - node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2568:198] - node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2568:198] - node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2568:198] - node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2633:57] - node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2568:198] - node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2568:198] - node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2568:198] - node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2634:57] - node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2568:198] - node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2568:198] - node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2568:198] - node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2635:57] - node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2568:198] - node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2568:198] - node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2568:198] - node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2568:198] - node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2568:198] - node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2568:198] - node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2568:198] - node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2568:198] - node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2568:198] - node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2636:81] - node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2568:198] - node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2568:198] - node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2568:198] - node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2568:198] - node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2568:198] - node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2636:121] - node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2568:198] - node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2568:198] - node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2568:198] - node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2568:198] - node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2636:155] - node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2568:198] - node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2568:198] - node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2568:198] - node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2568:198] - node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2637:97] - node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2568:198] - node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2568:198] - node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2568:198] - node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2568:198] - node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2568:198] - node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2637:137] - io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2636:34] - node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2568:198] - node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2568:198] - node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2568:198] - node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2568:198] - node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2568:198] - node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2568:198] - node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2568:198] - node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2568:198] - node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2638:81] - node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2568:198] - node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2568:198] - node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2568:198] - node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2638:121] - node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2568:198] - node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2568:198] - node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2568:198] - node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2638:162] - node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2568:198] - node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2568:198] - node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2568:198] - node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2568:198] - node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2568:198] - node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2568:198] - node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2639:105] - node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2568:198] - node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2568:198] - node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2568:198] - node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2568:198] - node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2568:198] - node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2639:145] - node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2568:198] - node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2568:198] - node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2568:198] - node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2568:198] - node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2639:178] - io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2638:30] - node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2568:198] - node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2568:198] - node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2568:198] - node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2568:198] - node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2568:198] - node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2568:198] - node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2568:198] - node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2568:198] - node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2568:198] - node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2568:198] - node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2568:198] - node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2568:198] - node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2568:198] - node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2568:198] - node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2568:198] - node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2568:198] - node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2568:198] - node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2568:198] - node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2568:198] - node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2641:81] - node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2568:198] - node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2568:198] - node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2568:198] - node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2568:198] - node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2568:198] - node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2568:198] - node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2568:198] - node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2568:198] - node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2641:129] - node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2568:198] - node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2568:198] - node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2568:198] - node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2568:198] - node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2568:198] - node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2568:198] - node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2568:198] - node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2568:198] - node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2568:198] - node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2642:105] - node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2568:198] - node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2568:198] - node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2568:198] - node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2568:198] - node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2568:198] - node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2568:198] - node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2642:153] - node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2568:198] - node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2568:198] - node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2568:198] - node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2568:198] - node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2568:198] - node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2568:198] - node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2568:198] - node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2568:198] - node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2568:198] - node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2568:198] - node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2568:198] - node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2643:105] - node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2568:198] - node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2568:198] - node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2568:198] - node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2568:198] - node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2568:198] - node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2568:198] - node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2568:198] - node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2568:198] - node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2568:198] - node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2643:153] - node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2568:198] - node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2568:198] - node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2568:198] - node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2568:198] - node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2568:198] - node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2568:198] - node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2568:198] - node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2568:198] - node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2568:198] - node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2644:105] - node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2568:198] - node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2568:198] - node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2568:198] - node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2568:198] - node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2568:198] - node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2568:198] - node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2568:198] - node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2568:198] - node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2568:198] - node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2644:161] - node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2568:198] - node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2568:198] - node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2568:198] - node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2568:198] - node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2568:198] - node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2568:198] - node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2568:198] - node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2645:105] - node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2568:198] - node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2568:198] - node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2568:198] - node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2568:198] - node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2568:198] - node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2568:198] - node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2568:198] - node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2568:198] - node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2568:198] - node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2568:198] - node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2645:161] - node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2568:198] - node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2568:198] - node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2568:198] - node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2568:198] - node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2568:198] - node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2568:198] - node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2568:198] - node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2568:198] - node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2568:198] - node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2646:97] - node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2568:198] - node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2568:198] - node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2568:198] - node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2568:198] - node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2568:198] - node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2568:198] - node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2568:198] - node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2568:198] - node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2568:198] - node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2646:153] - node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2568:198] - node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2568:198] - node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2568:198] - node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2568:198] - node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2568:198] - node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2568:198] - node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2568:198] - node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2568:198] - node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2568:198] - node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2647:105] - node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2568:198] - node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2568:198] - node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2568:198] - node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2568:198] - node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2568:198] - node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2568:198] - node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2568:198] - node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2568:198] - node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2647:161] - node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2568:198] - node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2568:198] - node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2568:198] - node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2568:198] - node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2568:198] - node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2568:198] - node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2568:198] - node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2568:198] - node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2648:105] - node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2568:198] - node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2568:198] - node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2568:198] - node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2568:198] - node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2568:198] - node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2568:198] - node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2568:198] - node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2568:198] - node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2568:198] - node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2648:161] - node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2568:198] - node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2568:198] - node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2568:198] - node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2568:198] - node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2568:198] - node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2568:198] - node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2649:105] - node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2568:198] - node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2568:198] - node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2568:198] - node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2568:198] - node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2568:198] - node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2568:198] - node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2568:198] - node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2568:198] - node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2568:198] - node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2649:161] - node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2568:198] - node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2568:198] - node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2568:198] - node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2568:198] - node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2568:198] - node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2568:198] - node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2568:198] - node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2568:198] - node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2650:105] - node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2568:198] - node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2568:198] - node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2568:198] - node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2568:198] - node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2568:198] - node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2568:198] - node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2568:198] - node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2568:198] - node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2568:198] - node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2650:161] - node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2568:198] - node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2568:198] - node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2568:198] - node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2568:198] - node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2568:198] - node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2568:198] - node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2568:198] - node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2568:198] - node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2568:198] - node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2568:198] - node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2651:105] - node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2568:198] - node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2568:198] - node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2568:198] - node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2568:198] - node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2568:198] - node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2568:198] - node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2651:153] - node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2568:198] - node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2568:198] - node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2568:198] - node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2568:198] - node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2568:198] - node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2568:198] - node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2568:198] - node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2568:198] - node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2568:198] - node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2652:113] - node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2568:198] - node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2568:198] - node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2568:198] - node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2568:198] - node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2568:198] - node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2568:198] - node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2568:198] - node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2568:198] - node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2568:198] - node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2652:161] - node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2568:198] - node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2568:198] - node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2568:198] - node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2568:198] - node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2568:198] - node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2568:198] - node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2568:198] - node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2653:97] - node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2568:198] - node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2568:198] - node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2568:198] - node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2568:198] - node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2568:198] - node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2568:198] - node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2653:153] - node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2568:198] - node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2568:198] - node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2568:198] - node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2568:198] - node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2568:198] - node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2568:198] - node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2568:198] - node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2654:113] - node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2568:198] - node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2568:198] - node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2568:198] - node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2568:198] - node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2568:198] - node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2568:198] - node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2654:169] - io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2641:26] + node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2569:198] + node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2569:198] + node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2569:198] + node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2571:57] + node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2569:198] + node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2569:198] + node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2572:57] + node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2569:198] + node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2569:198] + node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2573:57] + node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2569:198] + node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2569:198] + node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2574:57] + node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2569:198] + node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2575:57] + node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2569:198] + node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2569:198] + node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2569:198] + node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2576:57] + node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2569:198] + node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2569:198] + node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2569:198] + node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2577:57] + node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2569:198] + node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2578:65] + node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2569:198] + node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2569:198] + node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2569:198] + node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2579:65] + node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2569:198] + node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2569:198] + node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2569:198] + node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2569:198] + node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2580:57] + node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2569:198] + node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2569:198] + node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2569:198] + node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2569:198] + node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2569:198] + node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2581:57] + node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2569:198] + node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2569:198] + node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2569:198] + node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2569:198] + node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2569:198] + node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2582:57] + node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2569:198] + node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2569:198] + node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2569:198] + node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2569:198] + node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2569:198] + node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2583:57] + node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2569:198] + node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2569:198] + node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2569:198] + node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2584:57] + node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2569:198] + node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2569:198] + node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2585:57] + node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2569:198] + node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2569:198] + node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2586:57] + node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2569:198] + node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2587:57] + node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2569:198] + node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2569:198] + node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2588:57] + node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2569:198] + node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2569:198] + node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2569:198] + node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2569:198] + node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2589:57] + node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2569:198] + node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2569:198] + node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2569:198] + node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2590:57] + node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2569:198] + node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2569:198] + node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2591:57] + node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2569:198] + node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2592:57] + node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2569:198] + node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2569:198] + node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2569:198] + node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2569:198] + node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2593:57] + node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2569:198] + node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2569:198] + node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2594:57] + node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2569:198] + node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2595:57] + node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2569:198] + node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2569:198] + node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2596:57] + node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2569:198] + node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2569:198] + node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2569:198] + node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2597:57] + node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2569:198] + node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2569:198] + node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2598:57] + node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2569:198] + node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2569:198] + node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2569:198] + node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2599:57] + node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2569:198] + node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2569:198] + node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2569:198] + node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2600:65] + node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2569:198] + node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2569:198] + node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2569:198] + node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2601:57] + node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2569:198] + node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2569:198] + node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2602:57] + node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2569:198] + node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2569:198] + node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2603:57] + node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2569:198] + node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2569:198] + node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2569:198] + node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2569:198] + node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2604:57] + node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2569:198] + node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2569:198] + node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2569:198] + node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2569:198] + node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2569:198] + node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2605:57] + node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2569:198] + node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2569:198] + node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2569:198] + node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2569:198] + node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2606:57] + node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2569:198] + node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2569:198] + node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2569:198] + node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2569:198] + node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2569:198] + node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2607:57] + node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2569:198] + node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2569:198] + node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2569:198] + node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2569:198] + node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2608:57] + node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2569:198] + node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2569:198] + node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2569:198] + node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2569:198] + node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2569:198] + node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2609:57] + node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2569:198] + node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2569:198] + node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2569:198] + node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2569:198] + node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2610:57] + node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2569:198] + node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2569:198] + node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2569:198] + node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2569:198] + node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2569:198] + node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2611:57] + node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2569:198] + node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2569:198] + node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2569:198] + node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2569:198] + node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2612:57] + node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2569:198] + node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2569:198] + node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2569:198] + node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2569:198] + node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2613:57] + node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2569:198] + node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2569:198] + node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2569:198] + node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2569:198] + node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2614:57] + node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2569:198] + node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2569:198] + node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2569:198] + node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2569:198] + node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2615:57] + node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2569:198] + node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2569:198] + node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2569:198] + node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2569:198] + node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2616:49] + node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2569:198] + node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2569:198] + node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2569:198] + node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2617:57] + node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2569:198] + node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2569:198] + node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2569:198] + node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2618:57] + node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2569:198] + node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2569:198] + node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2569:198] + node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2619:57] + node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2569:198] + node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2569:198] + node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2569:198] + node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2620:57] + node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2569:198] + node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2569:198] + node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2569:198] + node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2621:57] + node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2569:198] + node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2569:198] + node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2622:57] + node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2569:198] + node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2569:198] + node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2569:198] + node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2623:57] + node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2569:198] + node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2569:198] + node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2569:198] + node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2569:198] + node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2624:57] + node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2569:198] + node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2569:198] + node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2625:57] + node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2569:198] + node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2569:198] + node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2626:57] + node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2569:198] + node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2569:198] + node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2569:198] + node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2627:57] + node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2569:198] + node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2569:198] + node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2628:57] + node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2569:198] + node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2569:198] + node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2629:57] + node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2569:198] + node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2569:198] + node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2569:198] + node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2630:57] + node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2569:198] + node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2569:198] + node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2631:57] + node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2569:198] + node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2569:198] + node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2569:198] + node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2569:198] + node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2632:57] + node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2569:198] + node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2569:198] + node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2633:57] + node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2569:198] + node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2569:198] + node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2569:198] + node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2634:57] + node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2569:198] + node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2569:198] + node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2569:198] + node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2635:57] + node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2569:198] + node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2569:198] + node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2569:198] + node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2636:57] + node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2569:198] + node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2569:198] + node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2569:198] + node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2569:198] + node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2569:198] + node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2569:198] + node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2569:198] + node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2569:198] + node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2569:198] + node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2637:81] + node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2569:198] + node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2569:198] + node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2569:198] + node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2569:198] + node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2569:198] + node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2637:121] + node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2569:198] + node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2569:198] + node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2569:198] + node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2569:198] + node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2637:155] + node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2569:198] + node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2569:198] + node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2569:198] + node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2569:198] + node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2638:97] + node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2569:198] + node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2569:198] + node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2569:198] + node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2569:198] + node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2569:198] + node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2638:137] + io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2637:34] + node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2569:198] + node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2569:198] + node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2569:198] + node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2569:198] + node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2569:198] + node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2569:198] + node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2569:198] + node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2569:198] + node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2639:81] + node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2569:198] + node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2569:198] + node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2569:198] + node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2639:121] + node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2569:198] + node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2569:198] + node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2569:198] + node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2639:162] + node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2569:198] + node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2569:198] + node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2569:198] + node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2569:198] + node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2569:198] + node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2569:198] + node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2640:105] + node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2569:198] + node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2569:198] + node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2569:198] + node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2569:198] + node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2569:198] + node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2640:145] + node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2569:198] + node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2569:198] + node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2569:198] + node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2569:198] + node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2640:178] + io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2639:30] + node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2569:198] + node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2569:198] + node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2569:198] + node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2569:198] + node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2569:198] + node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2569:198] + node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2569:198] + node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2569:198] + node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2569:198] + node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2569:198] + node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2569:198] + node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2569:198] + node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2569:198] + node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2569:198] + node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2569:198] + node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2569:198] + node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2569:198] + node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2569:198] + node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2569:198] + node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2642:81] + node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2569:198] + node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2569:198] + node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2569:198] + node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2569:198] + node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2569:198] + node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2569:198] + node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2569:198] + node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2569:198] + node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2642:129] + node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2569:198] + node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2569:198] + node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2569:198] + node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2569:198] + node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2569:198] + node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2569:198] + node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2569:198] + node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2569:198] + node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2569:198] + node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2643:105] + node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2569:198] + node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2569:198] + node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2569:198] + node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2569:198] + node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2569:198] + node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2569:198] + node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2643:153] + node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2569:198] + node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2569:198] + node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2569:198] + node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2569:198] + node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2569:198] + node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2569:198] + node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2569:198] + node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2569:198] + node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2569:198] + node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2569:198] + node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2569:198] + node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2644:105] + node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2569:198] + node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2569:198] + node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2569:198] + node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2569:198] + node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2569:198] + node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2569:198] + node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2569:198] + node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2569:198] + node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2569:198] + node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2644:153] + node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2569:198] + node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2569:198] + node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2569:198] + node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2569:198] + node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2569:198] + node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2569:198] + node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2569:198] + node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2569:198] + node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2569:198] + node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2645:105] + node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2569:198] + node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2569:198] + node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2569:198] + node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2569:198] + node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2569:198] + node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2569:198] + node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2569:198] + node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2569:198] + node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2569:198] + node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2645:161] + node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2569:198] + node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2569:198] + node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2569:198] + node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2569:198] + node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2569:198] + node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2569:198] + node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2569:198] + node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2646:105] + node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2569:198] + node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2569:198] + node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2569:198] + node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2569:198] + node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2569:198] + node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2569:198] + node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2569:198] + node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2569:198] + node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2569:198] + node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2569:198] + node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2646:161] + node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2569:198] + node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2569:198] + node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2569:198] + node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2569:198] + node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2569:198] + node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2569:198] + node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2569:198] + node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2569:198] + node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2569:198] + node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2647:97] + node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2569:198] + node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2569:198] + node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2569:198] + node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2569:198] + node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2569:198] + node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2569:198] + node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2569:198] + node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2569:198] + node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2569:198] + node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2647:153] + node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2569:198] + node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2569:198] + node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2569:198] + node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2569:198] + node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2569:198] + node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2569:198] + node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2569:198] + node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2569:198] + node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2569:198] + node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2648:105] + node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2569:198] + node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2569:198] + node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2569:198] + node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2569:198] + node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2569:198] + node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2569:198] + node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2569:198] + node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2569:198] + node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2648:161] + node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2569:198] + node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2569:198] + node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2569:198] + node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2569:198] + node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2569:198] + node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2569:198] + node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2569:198] + node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2569:198] + node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2649:105] + node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2569:198] + node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2569:198] + node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2569:198] + node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2569:198] + node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2569:198] + node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2569:198] + node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2569:198] + node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2569:198] + node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2569:198] + node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2649:161] + node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2569:198] + node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2569:198] + node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2569:198] + node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2569:198] + node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2569:198] + node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2569:198] + node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2650:105] + node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2569:198] + node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2569:198] + node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2569:198] + node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2569:198] + node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2569:198] + node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2569:198] + node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2569:198] + node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2569:198] + node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2569:198] + node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2650:161] + node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2569:198] + node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2569:198] + node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2569:198] + node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2569:198] + node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2569:198] + node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2569:198] + node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2569:198] + node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2569:198] + node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2651:105] + node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2569:198] + node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2569:198] + node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2569:198] + node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2569:198] + node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2569:198] + node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2569:198] + node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2569:198] + node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2569:198] + node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2569:198] + node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2651:161] + node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2569:198] + node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2569:198] + node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2569:198] + node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2569:198] + node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2569:198] + node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2569:198] + node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2569:198] + node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2569:198] + node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2569:198] + node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2569:198] + node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2652:105] + node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2569:198] + node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2569:198] + node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2569:198] + node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2569:198] + node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2569:198] + node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2569:198] + node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2652:153] + node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2569:198] + node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2569:198] + node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2569:198] + node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2569:198] + node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2569:198] + node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2569:198] + node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2569:198] + node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2569:198] + node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2569:198] + node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2653:113] + node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2569:198] + node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2569:198] + node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2569:198] + node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2569:198] + node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2569:198] + node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2569:198] + node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2569:198] + node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2569:198] + node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2569:198] + node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2653:161] + node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2569:198] + node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2569:198] + node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2569:198] + node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2569:198] + node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2569:198] + node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2569:198] + node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2569:198] + node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2654:97] + node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2569:198] + node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2569:198] + node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2569:198] + node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2569:198] + node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2569:198] + node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2569:198] + node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2654:153] + node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2569:198] + node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2569:198] + node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2569:198] + node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2569:198] + node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2569:198] + node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2569:198] + node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2569:198] + node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2655:113] + node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2569:198] + node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2569:198] + node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2569:198] + node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2569:198] + node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2569:198] + node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2569:198] + node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2655:169] + io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2642:26] module dec_tlu_ctl : input clock : Clock @@ -109158,6 +109157,8 @@ circuit quasar : ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 102:25] ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 102:25] ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 103:42] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 104:43] ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 105:33] ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 106:51] ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 106:51] diff --git a/quasar.v b/quasar.v index 1cb87743..0f4ed38b 100644 --- a/quasar.v +++ b/quasar.v @@ -50189,56 +50189,56 @@ module dec_timer_ctl( wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] reg [31:0] mitcnt0; // @[lib.scala 374:16] reg [31:0] mitb0_b; // @[lib.scala 374:16] - wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2711:22] - wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2672:36] + wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2712:22] + wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2673:36] reg [31:0] mitcnt1; // @[lib.scala 374:16] reg [31:0] mitb1_b; // @[lib.scala 374:16] - wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2720:18] - wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2673:36] - wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2683:72] - wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2683:49] - reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2736:67] - reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2735:60] - wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2736:90] + wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2721:18] + wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2674:36] + wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2684:72] + wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2684:49] + reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2737:67] + reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2736:60] + wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2737:90] wire [2:0] mitctl0 = {_T_57,_T_58}; // @[Cat.scala 29:58] - wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2685:56] - wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2685:76] - wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2685:53] - wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2685:112] - wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2685:138] - wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2685:109] - wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2685:173] - wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2685:171] - wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2686:35] - wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2688:59] - wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2695:72] - wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2695:49] - reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2750:52] - reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2749:55] - wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2750:75] + wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2686:56] + wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2686:76] + wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2686:53] + wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2686:112] + wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2686:138] + wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2686:109] + wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2686:173] + wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2686:171] + wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2687:35] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2689:59] + wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2696:72] + wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2696:49] + reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2751:52] + reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2750:55] + wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2751:75] wire [3:0] mitctl1 = {_T_66,_T_67}; // @[Cat.scala 29:58] - wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2697:76] - wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2697:53] - wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2697:138] - wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2697:109] - wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2697:171] - wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2700:60] - wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2700:72] + wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2698:76] + wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2698:53] + wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2698:138] + wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2698:109] + wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2698:171] + wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2701:60] + wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2701:72] wire [31:0] _T_34 = {31'h0,_T_33}; // @[Cat.scala 29:58] - wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2700:35] - wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2702:60] - wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2709:70] - wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2718:69] - wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2731:72] - wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2731:49] - wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2732:31] - wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2746:71] - wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2746:49] - wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2747:31] - wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2752:51] - wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2752:68] - wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2752:83] - wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2752:98] + wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2701:35] + wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2703:60] + wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2710:70] + wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2719:69] + wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2732:72] + wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2732:49] + wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2733:31] + wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2747:71] + wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2747:49] + wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2748:31] + wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2753:51] + wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2753:68] + wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2753:83] + wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2753:98] wire [31:0] _T_81 = {29'h0,_T_57,_T_58}; // @[Cat.scala 29:58] wire [31:0] _T_84 = {28'h0,_T_66,_T_67}; // @[Cat.scala 29:58] wire [31:0] _T_85 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72] @@ -50275,10 +50275,10 @@ module dec_timer_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2753:33] - assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2752:33] - assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2675:31] - assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2676:31] + assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2754:33] + assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2753:33] + assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2676:31] + assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2677:31] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -51359,245 +51359,247 @@ module csr_tlu( reg [31:0] dicad0h; // @[lib.scala 374:16] wire _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2126:100] wire _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2126:71] - wire _T_757 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2130:78] - reg [6:0] _T_759; // @[Reg.scala 27:20] - wire [31:0] dicad1 = {25'h0,_T_759}; // @[Cat.scala 29:58] - wire [38:0] _T_764 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] - wire _T_766 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2158:52] - wire _T_767 = _T_766 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2158:75] - wire _T_768 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2158:98] - wire _T_769 = _T_767 & _T_768; // @[dec_tlu_ctl.scala 2158:96] - wire _T_771 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2158:149] - wire _T_774 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2159:104] - reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2161:58] - reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2162:58] - wire _T_776 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2173:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_776; // @[dec_tlu_ctl.scala 2173:40] - reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2176:43] - wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2211:42] - wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2213:44] - wire _T_787 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2215:46] - wire tdata_action = _T_787 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2215:69] - wire [9:0] tdata_wrdata_r = {_T_787,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_802 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2221:99] - wire _T_803 = io_dec_csr_wen_r_mod & _T_802; // @[dec_tlu_ctl.scala 2221:70] - wire _T_804 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2221:121] - wire _T_805 = _T_803 & _T_804; // @[dec_tlu_ctl.scala 2221:112] - wire _T_807 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2221:138] - wire _T_808 = _T_807 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] - wire wr_mtdata1_t_r_0 = _T_805 & _T_808; // @[dec_tlu_ctl.scala 2221:135] - wire _T_813 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2221:121] - wire _T_814 = _T_803 & _T_813; // @[dec_tlu_ctl.scala 2221:112] - wire _T_816 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2221:138] - wire _T_817 = _T_816 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] - wire wr_mtdata1_t_r_1 = _T_814 & _T_817; // @[dec_tlu_ctl.scala 2221:135] - wire _T_822 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2221:121] - wire _T_823 = _T_803 & _T_822; // @[dec_tlu_ctl.scala 2221:112] - wire _T_825 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2221:138] - wire _T_826 = _T_825 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] - wire wr_mtdata1_t_r_2 = _T_823 & _T_826; // @[dec_tlu_ctl.scala 2221:135] - wire _T_831 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2221:121] - wire _T_832 = _T_803 & _T_831; // @[dec_tlu_ctl.scala 2221:112] - wire _T_834 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2221:138] - wire _T_835 = _T_834 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] - wire wr_mtdata1_t_r_3 = _T_832 & _T_835; // @[dec_tlu_ctl.scala 2221:135] - wire _T_841 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2222:139] - wire [9:0] _T_844 = {io_mtdata1_t_0[9],_T_841,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_850 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2222:139] - wire [9:0] _T_853 = {io_mtdata1_t_1[9],_T_850,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_859 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2222:139] - wire [9:0] _T_862 = {io_mtdata1_t_2[9],_T_859,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_868 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2222:139] - wire [9:0] _T_871 = {io_mtdata1_t_3[9],_T_868,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2224:74] - reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2224:74] - reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2224:74] - reg [9:0] _T_876; // @[dec_tlu_ctl.scala 2224:74] - wire [31:0] _T_891 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_906 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_921 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_936 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_937 = _T_804 ? _T_891 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_938 = _T_813 ? _T_906 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_939 = _T_822 ? _T_921 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_940 = _T_831 ? _T_936 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_941 = _T_937 | _T_938; // @[Mux.scala 27:72] - wire [31:0] _T_942 = _T_941 | _T_939; // @[Mux.scala 27:72] - wire [31:0] mtdata1_tsel_out = _T_942 | _T_940; // @[Mux.scala 27:72] - wire _T_969 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2241:98] - wire _T_970 = io_dec_csr_wen_r_mod & _T_969; // @[dec_tlu_ctl.scala 2241:69] - wire _T_972 = _T_970 & _T_804; // @[dec_tlu_ctl.scala 2241:111] - wire _T_981 = _T_970 & _T_813; // @[dec_tlu_ctl.scala 2241:111] - wire _T_990 = _T_970 & _T_822; // @[dec_tlu_ctl.scala 2241:111] - wire _T_999 = _T_970 & _T_831; // @[dec_tlu_ctl.scala 2241:111] + wire [31:0] _T_755 = _T_752 ? io_dec_csr_wrdata_r : {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; // @[dec_tlu_ctl.scala 2128:21] + wire _T_756 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2131:78] + reg [31:0] _T_758; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_758[6:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_763 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_765 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2159:52] + wire _T_766 = _T_765 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2159:75] + wire _T_767 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2159:98] + wire _T_768 = _T_766 & _T_767; // @[dec_tlu_ctl.scala 2159:96] + wire _T_770 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2159:149] + wire _T_773 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2160:104] + reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2162:58] + reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2163:58] + wire _T_775 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2174:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_775; // @[dec_tlu_ctl.scala 2174:40] + reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2177:43] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2212:42] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2214:44] + wire _T_786 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2216:46] + wire tdata_action = _T_786 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2216:69] + wire [9:0] tdata_wrdata_r = {_T_786,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_801 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2222:99] + wire _T_802 = io_dec_csr_wen_r_mod & _T_801; // @[dec_tlu_ctl.scala 2222:70] + wire _T_803 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2222:121] + wire _T_804 = _T_802 & _T_803; // @[dec_tlu_ctl.scala 2222:112] + wire _T_806 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_0 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2222:135] + wire _T_812 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2222:121] + wire _T_813 = _T_802 & _T_812; // @[dec_tlu_ctl.scala 2222:112] + wire _T_815 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_1 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2222:135] + wire _T_821 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2222:121] + wire _T_822 = _T_802 & _T_821; // @[dec_tlu_ctl.scala 2222:112] + wire _T_824 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_2 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2222:135] + wire _T_830 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2222:121] + wire _T_831 = _T_802 & _T_830; // @[dec_tlu_ctl.scala 2222:112] + wire _T_833 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_834 = _T_833 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_3 = _T_831 & _T_834; // @[dec_tlu_ctl.scala 2222:135] + wire _T_840 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_843 = {io_mtdata1_t_0[9],_T_840,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_849 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_852 = {io_mtdata1_t_1[9],_T_849,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_858 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_861 = {io_mtdata1_t_2[9],_T_858,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_867 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_870 = {io_mtdata1_t_3[9],_T_867,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_872; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2225:74] + wire [31:0] _T_890 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_905 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_920 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_935 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_936 = _T_803 ? _T_890 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_937 = _T_812 ? _T_905 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_938 = _T_821 ? _T_920 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_939 = _T_830 ? _T_935 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_940 = _T_936 | _T_937; // @[Mux.scala 27:72] + wire [31:0] _T_941 = _T_940 | _T_938; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_941 | _T_939; // @[Mux.scala 27:72] + wire _T_968 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2242:98] + wire _T_969 = io_dec_csr_wen_r_mod & _T_968; // @[dec_tlu_ctl.scala 2242:69] + wire _T_971 = _T_969 & _T_803; // @[dec_tlu_ctl.scala 2242:111] + wire _T_980 = _T_969 & _T_812; // @[dec_tlu_ctl.scala 2242:111] + wire _T_989 = _T_969 & _T_821; // @[dec_tlu_ctl.scala 2242:111] + wire _T_998 = _T_969 & _T_830; // @[dec_tlu_ctl.scala 2242:111] reg [31:0] mtdata2_t_0; // @[lib.scala 374:16] reg [31:0] mtdata2_t_1; // @[lib.scala 374:16] reg [31:0] mtdata2_t_2; // @[lib.scala 374:16] reg [31:0] mtdata2_t_3; // @[lib.scala 374:16] - wire [31:0] _T_1016 = _T_804 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1017 = _T_813 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1018 = _T_822 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1019 = _T_831 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1020 = _T_1016 | _T_1017; // @[Mux.scala 27:72] - wire [31:0] _T_1021 = _T_1020 | _T_1018; // @[Mux.scala 27:72] - wire [31:0] mtdata2_tsel_out = _T_1021 | _T_1019; // @[Mux.scala 27:72] - wire [3:0] _T_1024 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1024; // @[dec_tlu_ctl.scala 2266:59] - wire _T_1026 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2272:24] + wire [31:0] _T_1015 = _T_803 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1016 = _T_812 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1017 = _T_821 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1018 = _T_830 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1019 = _T_1015 | _T_1016; // @[Mux.scala 27:72] + wire [31:0] _T_1020 = _T_1019 | _T_1017; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1020 | _T_1018; // @[Mux.scala 27:72] + wire [3:0] _T_1023 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1023; // @[dec_tlu_ctl.scala 2267:59] + wire _T_1025 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1027 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1029 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1031 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1033 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1035 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2276:96] - wire _T_1036 = io_tlu_i0_commit_cmt & _T_1035; // @[dec_tlu_ctl.scala 2276:94] - wire _T_1037 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1039 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2277:96] - wire _T_1040 = io_tlu_i0_commit_cmt & _T_1039; // @[dec_tlu_ctl.scala 2277:94] - wire _T_1042 = _T_1040 & _T_1035; // @[dec_tlu_ctl.scala 2277:115] - wire _T_1043 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1045 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:94] - wire _T_1047 = _T_1045 & _T_1035; // @[dec_tlu_ctl.scala 2278:115] - wire _T_1048 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1050 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1052 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1054 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1056 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2282:91] - wire _T_1057 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1059 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2283:105] - wire _T_1060 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1062 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2284:91] - wire _T_1063 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1065 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2285:91] - wire _T_1066 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1069 = _T_1062 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2286:100] - wire _T_1070 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1074 = _T_1065 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:101] - wire _T_1075 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1077 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2288:89] - wire _T_1078 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1080 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2289:89] - wire _T_1081 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1083 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2290:89] - wire _T_1084 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1086 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2291:89] - wire _T_1087 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1089 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2292:89] - wire _T_1090 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1092 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2293:89] - wire _T_1093 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1095 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2294:89] - wire _T_1096 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1098 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2295:89] - wire _T_1099 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1101 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2296:89] - wire _T_1102 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1104 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2297:89] - wire _T_1105 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2297:122] - wire _T_1106 = _T_1104 | _T_1105; // @[dec_tlu_ctl.scala 2297:101] - wire _T_1107 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1109 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2298:95] - wire _T_1110 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1112 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:97] - wire _T_1113 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1115 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:110] - wire _T_1116 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1120 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1122 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1124 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1126 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1128 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1130 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1132 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2308:98] - wire _T_1133 = _T_1132 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2308:120] - wire _T_1134 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1136 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2309:92] - wire _T_1137 = _T_1136 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2309:117] - wire _T_1138 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1140 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1142 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1144 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2312:97] - wire _T_1145 = _T_1144 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2312:129] - wire _T_1146 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1148 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1150 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1152 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1154 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1156 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1158 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1160 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1164 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2320:73] - wire _T_1165 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] - wire [5:0] _T_1172 = io_mip & mie; // @[dec_tlu_ctl.scala 2321:113] - wire _T_1173 = |_T_1172; // @[dec_tlu_ctl.scala 2321:125] - wire _T_1174 = _T_1164 & _T_1173; // @[dec_tlu_ctl.scala 2321:98] - wire _T_1175 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1177 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2322:91] - wire _T_1178 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1180 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2323:94] - wire _T_1181 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1183 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2324:94] - wire _T_1184 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1186 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1188 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1190 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1192 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1195 = _T_1029 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1196 = _T_1031 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1197 = _T_1033 & _T_1036; // @[Mux.scala 27:72] - wire _T_1198 = _T_1037 & _T_1042; // @[Mux.scala 27:72] - wire _T_1199 = _T_1043 & _T_1047; // @[Mux.scala 27:72] - wire _T_1200 = _T_1048 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1201 = _T_1050 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1202 = _T_1052 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1203 = _T_1054 & _T_1056; // @[Mux.scala 27:72] - wire _T_1204 = _T_1057 & _T_1059; // @[Mux.scala 27:72] - wire _T_1205 = _T_1060 & _T_1062; // @[Mux.scala 27:72] - wire _T_1206 = _T_1063 & _T_1065; // @[Mux.scala 27:72] - wire _T_1207 = _T_1066 & _T_1069; // @[Mux.scala 27:72] - wire _T_1208 = _T_1070 & _T_1074; // @[Mux.scala 27:72] - wire _T_1209 = _T_1075 & _T_1077; // @[Mux.scala 27:72] - wire _T_1210 = _T_1078 & _T_1080; // @[Mux.scala 27:72] - wire _T_1211 = _T_1081 & _T_1083; // @[Mux.scala 27:72] - wire _T_1212 = _T_1084 & _T_1086; // @[Mux.scala 27:72] - wire _T_1213 = _T_1087 & _T_1089; // @[Mux.scala 27:72] - wire _T_1214 = _T_1090 & _T_1092; // @[Mux.scala 27:72] - wire _T_1215 = _T_1093 & _T_1095; // @[Mux.scala 27:72] - wire _T_1216 = _T_1096 & _T_1098; // @[Mux.scala 27:72] - wire _T_1217 = _T_1099 & _T_1101; // @[Mux.scala 27:72] - wire _T_1218 = _T_1102 & _T_1106; // @[Mux.scala 27:72] - wire _T_1219 = _T_1107 & _T_1109; // @[Mux.scala 27:72] - wire _T_1220 = _T_1110 & _T_1112; // @[Mux.scala 27:72] - wire _T_1221 = _T_1113 & _T_1115; // @[Mux.scala 27:72] - wire _T_1222 = _T_1116 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1224 = _T_1120 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1225 = _T_1122 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1226 = _T_1124 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1227 = _T_1126 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1228 = _T_1128 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1229 = _T_1130 & _T_1133; // @[Mux.scala 27:72] - wire _T_1230 = _T_1134 & _T_1137; // @[Mux.scala 27:72] - wire _T_1231 = _T_1138 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1232 = _T_1140 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1233 = _T_1142 & _T_1145; // @[Mux.scala 27:72] - wire _T_1234 = _T_1146 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1235 = _T_1148 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1236 = _T_1150 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1237 = _T_1152 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1238 = _T_1154 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1239 = _T_1156 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1240 = _T_1158 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1241 = _T_1160 & _T_1164; // @[Mux.scala 27:72] - wire _T_1242 = _T_1165 & _T_1174; // @[Mux.scala 27:72] - wire _T_1243 = _T_1175 & _T_1177; // @[Mux.scala 27:72] - wire _T_1244 = _T_1178 & _T_1180; // @[Mux.scala 27:72] - wire _T_1245 = _T_1181 & _T_1183; // @[Mux.scala 27:72] - wire _T_1246 = _T_1184 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1247 = _T_1186 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1248 = _T_1188 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1249 = _T_1190 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1250 = _T_1192 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1251 = _T_1027 | _T_1195; // @[Mux.scala 27:72] + wire _T_1026 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1028 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1030 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1032 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1034 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2277:96] + wire _T_1035 = io_tlu_i0_commit_cmt & _T_1034; // @[dec_tlu_ctl.scala 2277:94] + wire _T_1036 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1038 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:96] + wire _T_1039 = io_tlu_i0_commit_cmt & _T_1038; // @[dec_tlu_ctl.scala 2278:94] + wire _T_1041 = _T_1039 & _T_1034; // @[dec_tlu_ctl.scala 2278:115] + wire _T_1042 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1044 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:94] + wire _T_1046 = _T_1044 & _T_1034; // @[dec_tlu_ctl.scala 2279:115] + wire _T_1047 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1049 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1051 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1053 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1055 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2283:91] + wire _T_1056 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1058 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2284:105] + wire _T_1059 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1061 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2285:91] + wire _T_1062 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1064 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2286:91] + wire _T_1065 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1068 = _T_1061 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:100] + wire _T_1069 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1073 = _T_1064 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:101] + wire _T_1074 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1076 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2289:89] + wire _T_1077 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1079 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2290:89] + wire _T_1080 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1082 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2291:89] + wire _T_1083 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1085 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2292:89] + wire _T_1086 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1088 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2293:89] + wire _T_1089 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1091 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2294:89] + wire _T_1092 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1094 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2295:89] + wire _T_1095 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1097 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2296:89] + wire _T_1098 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1100 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2297:89] + wire _T_1101 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1103 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2298:89] + wire _T_1104 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2298:122] + wire _T_1105 = _T_1103 | _T_1104; // @[dec_tlu_ctl.scala 2298:101] + wire _T_1106 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1108 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:95] + wire _T_1109 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1111 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:97] + wire _T_1112 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1114 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:110] + wire _T_1115 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1119 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1121 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1123 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1125 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1127 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1129 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1131 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2309:98] + wire _T_1132 = _T_1131 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2309:120] + wire _T_1133 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1135 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2310:92] + wire _T_1136 = _T_1135 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2310:117] + wire _T_1137 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1139 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1141 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1143 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2313:97] + wire _T_1144 = _T_1143 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2313:129] + wire _T_1145 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1147 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1149 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1151 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1153 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1155 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1157 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1159 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1163 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2321:73] + wire _T_1164 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire [5:0] _T_1171 = io_mip & mie; // @[dec_tlu_ctl.scala 2322:113] + wire _T_1172 = |_T_1171; // @[dec_tlu_ctl.scala 2322:125] + wire _T_1173 = _T_1163 & _T_1172; // @[dec_tlu_ctl.scala 2322:98] + wire _T_1174 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2323:91] + wire _T_1177 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2324:94] + wire _T_1180 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2325:94] + wire _T_1183 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1185 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1187 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1189 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1191 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1194 = _T_1028 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1195 = _T_1030 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1196 = _T_1032 & _T_1035; // @[Mux.scala 27:72] + wire _T_1197 = _T_1036 & _T_1041; // @[Mux.scala 27:72] + wire _T_1198 = _T_1042 & _T_1046; // @[Mux.scala 27:72] + wire _T_1199 = _T_1047 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1200 = _T_1049 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1201 = _T_1051 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1202 = _T_1053 & _T_1055; // @[Mux.scala 27:72] + wire _T_1203 = _T_1056 & _T_1058; // @[Mux.scala 27:72] + wire _T_1204 = _T_1059 & _T_1061; // @[Mux.scala 27:72] + wire _T_1205 = _T_1062 & _T_1064; // @[Mux.scala 27:72] + wire _T_1206 = _T_1065 & _T_1068; // @[Mux.scala 27:72] + wire _T_1207 = _T_1069 & _T_1073; // @[Mux.scala 27:72] + wire _T_1208 = _T_1074 & _T_1076; // @[Mux.scala 27:72] + wire _T_1209 = _T_1077 & _T_1079; // @[Mux.scala 27:72] + wire _T_1210 = _T_1080 & _T_1082; // @[Mux.scala 27:72] + wire _T_1211 = _T_1083 & _T_1085; // @[Mux.scala 27:72] + wire _T_1212 = _T_1086 & _T_1088; // @[Mux.scala 27:72] + wire _T_1213 = _T_1089 & _T_1091; // @[Mux.scala 27:72] + wire _T_1214 = _T_1092 & _T_1094; // @[Mux.scala 27:72] + wire _T_1215 = _T_1095 & _T_1097; // @[Mux.scala 27:72] + wire _T_1216 = _T_1098 & _T_1100; // @[Mux.scala 27:72] + wire _T_1217 = _T_1101 & _T_1105; // @[Mux.scala 27:72] + wire _T_1218 = _T_1106 & _T_1108; // @[Mux.scala 27:72] + wire _T_1219 = _T_1109 & _T_1111; // @[Mux.scala 27:72] + wire _T_1220 = _T_1112 & _T_1114; // @[Mux.scala 27:72] + wire _T_1221 = _T_1115 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1223 = _T_1119 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1224 = _T_1121 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1225 = _T_1123 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1226 = _T_1125 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1227 = _T_1127 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1228 = _T_1129 & _T_1132; // @[Mux.scala 27:72] + wire _T_1229 = _T_1133 & _T_1136; // @[Mux.scala 27:72] + wire _T_1230 = _T_1137 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1231 = _T_1139 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1232 = _T_1141 & _T_1144; // @[Mux.scala 27:72] + wire _T_1233 = _T_1145 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1234 = _T_1147 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1235 = _T_1149 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1236 = _T_1151 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1237 = _T_1153 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1238 = _T_1155 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1239 = _T_1157 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1240 = _T_1159 & _T_1163; // @[Mux.scala 27:72] + wire _T_1241 = _T_1164 & _T_1173; // @[Mux.scala 27:72] + wire _T_1242 = _T_1174 & _T_1176; // @[Mux.scala 27:72] + wire _T_1243 = _T_1177 & _T_1179; // @[Mux.scala 27:72] + wire _T_1244 = _T_1180 & _T_1182; // @[Mux.scala 27:72] + wire _T_1245 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1246 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1247 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1248 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1249 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1250 = _T_1026 | _T_1194; // @[Mux.scala 27:72] + wire _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72] wire _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72] wire _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72] wire _T_1254 = _T_1253 | _T_1198; // @[Mux.scala 27:72] @@ -51624,8 +51626,8 @@ module csr_tlu( wire _T_1275 = _T_1274 | _T_1219; // @[Mux.scala 27:72] wire _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72] wire _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72] - wire _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72] - wire _T_1279 = _T_1278 | _T_1202; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1201; // @[Mux.scala 27:72] + wire _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72] wire _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72] wire _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72] wire _T_1282 = _T_1281 | _T_1226; // @[Mux.scala 27:72] @@ -51652,122 +51654,122 @@ module csr_tlu( wire _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72] wire _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72] wire _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72] - wire _T_1306 = _T_1305 | _T_1250; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1026 & _T_1306; // @[dec_tlu_ctl.scala 2272:44] - wire _T_1310 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2272:24] + wire mhpmc_inc_r_0 = _T_1025 & _T_1305; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1309 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1311 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1313 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1315 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1317 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1321 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1327 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1332 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1334 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1336 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1338 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1341 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1344 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1347 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1350 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1354 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1359 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1362 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1365 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1368 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1371 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1374 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1377 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1380 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1383 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1386 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1391 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1394 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1397 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1400 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1404 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1406 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1408 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1410 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1412 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1414 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1418 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1422 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1424 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1426 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1430 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1432 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1434 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1436 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1438 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1440 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1442 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1444 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1449 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1459 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1462 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1465 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1468 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1470 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1472 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1474 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1476 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1479 = _T_1313 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1480 = _T_1315 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1481 = _T_1317 & _T_1036; // @[Mux.scala 27:72] - wire _T_1482 = _T_1321 & _T_1042; // @[Mux.scala 27:72] - wire _T_1483 = _T_1327 & _T_1047; // @[Mux.scala 27:72] - wire _T_1484 = _T_1332 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1485 = _T_1334 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1486 = _T_1336 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1487 = _T_1338 & _T_1056; // @[Mux.scala 27:72] - wire _T_1488 = _T_1341 & _T_1059; // @[Mux.scala 27:72] - wire _T_1489 = _T_1344 & _T_1062; // @[Mux.scala 27:72] - wire _T_1490 = _T_1347 & _T_1065; // @[Mux.scala 27:72] - wire _T_1491 = _T_1350 & _T_1069; // @[Mux.scala 27:72] - wire _T_1492 = _T_1354 & _T_1074; // @[Mux.scala 27:72] - wire _T_1493 = _T_1359 & _T_1077; // @[Mux.scala 27:72] - wire _T_1494 = _T_1362 & _T_1080; // @[Mux.scala 27:72] - wire _T_1495 = _T_1365 & _T_1083; // @[Mux.scala 27:72] - wire _T_1496 = _T_1368 & _T_1086; // @[Mux.scala 27:72] - wire _T_1497 = _T_1371 & _T_1089; // @[Mux.scala 27:72] - wire _T_1498 = _T_1374 & _T_1092; // @[Mux.scala 27:72] - wire _T_1499 = _T_1377 & _T_1095; // @[Mux.scala 27:72] - wire _T_1500 = _T_1380 & _T_1098; // @[Mux.scala 27:72] - wire _T_1501 = _T_1383 & _T_1101; // @[Mux.scala 27:72] - wire _T_1502 = _T_1386 & _T_1106; // @[Mux.scala 27:72] - wire _T_1503 = _T_1391 & _T_1109; // @[Mux.scala 27:72] - wire _T_1504 = _T_1394 & _T_1112; // @[Mux.scala 27:72] - wire _T_1505 = _T_1397 & _T_1115; // @[Mux.scala 27:72] - wire _T_1506 = _T_1400 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1508 = _T_1404 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1509 = _T_1406 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1510 = _T_1408 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1511 = _T_1410 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1512 = _T_1412 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1513 = _T_1414 & _T_1133; // @[Mux.scala 27:72] - wire _T_1514 = _T_1418 & _T_1137; // @[Mux.scala 27:72] - wire _T_1515 = _T_1422 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1516 = _T_1424 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1517 = _T_1426 & _T_1145; // @[Mux.scala 27:72] - wire _T_1518 = _T_1430 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1519 = _T_1432 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1520 = _T_1434 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1521 = _T_1436 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1522 = _T_1438 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1523 = _T_1440 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1524 = _T_1442 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1525 = _T_1444 & _T_1164; // @[Mux.scala 27:72] - wire _T_1526 = _T_1449 & _T_1174; // @[Mux.scala 27:72] - wire _T_1527 = _T_1459 & _T_1177; // @[Mux.scala 27:72] - wire _T_1528 = _T_1462 & _T_1180; // @[Mux.scala 27:72] - wire _T_1529 = _T_1465 & _T_1183; // @[Mux.scala 27:72] - wire _T_1530 = _T_1468 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1531 = _T_1470 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1532 = _T_1472 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1533 = _T_1474 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1534 = _T_1476 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1535 = _T_1311 | _T_1479; // @[Mux.scala 27:72] + wire _T_1310 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1312 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1314 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1316 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1320 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1326 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1331 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1333 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1335 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1337 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1340 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1343 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1346 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1349 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1353 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1358 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1361 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1364 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1367 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1370 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1373 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1376 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1379 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1382 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1385 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1390 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1393 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1396 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1399 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1403 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1405 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1407 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1409 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1411 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1413 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1417 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1421 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1423 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1425 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1429 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1431 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1433 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1435 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1437 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1439 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1441 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1443 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1448 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1458 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1461 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1464 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1467 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1469 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1471 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1473 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1475 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1478 = _T_1312 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1479 = _T_1314 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1480 = _T_1316 & _T_1035; // @[Mux.scala 27:72] + wire _T_1481 = _T_1320 & _T_1041; // @[Mux.scala 27:72] + wire _T_1482 = _T_1326 & _T_1046; // @[Mux.scala 27:72] + wire _T_1483 = _T_1331 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1484 = _T_1333 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1485 = _T_1335 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1486 = _T_1337 & _T_1055; // @[Mux.scala 27:72] + wire _T_1487 = _T_1340 & _T_1058; // @[Mux.scala 27:72] + wire _T_1488 = _T_1343 & _T_1061; // @[Mux.scala 27:72] + wire _T_1489 = _T_1346 & _T_1064; // @[Mux.scala 27:72] + wire _T_1490 = _T_1349 & _T_1068; // @[Mux.scala 27:72] + wire _T_1491 = _T_1353 & _T_1073; // @[Mux.scala 27:72] + wire _T_1492 = _T_1358 & _T_1076; // @[Mux.scala 27:72] + wire _T_1493 = _T_1361 & _T_1079; // @[Mux.scala 27:72] + wire _T_1494 = _T_1364 & _T_1082; // @[Mux.scala 27:72] + wire _T_1495 = _T_1367 & _T_1085; // @[Mux.scala 27:72] + wire _T_1496 = _T_1370 & _T_1088; // @[Mux.scala 27:72] + wire _T_1497 = _T_1373 & _T_1091; // @[Mux.scala 27:72] + wire _T_1498 = _T_1376 & _T_1094; // @[Mux.scala 27:72] + wire _T_1499 = _T_1379 & _T_1097; // @[Mux.scala 27:72] + wire _T_1500 = _T_1382 & _T_1100; // @[Mux.scala 27:72] + wire _T_1501 = _T_1385 & _T_1105; // @[Mux.scala 27:72] + wire _T_1502 = _T_1390 & _T_1108; // @[Mux.scala 27:72] + wire _T_1503 = _T_1393 & _T_1111; // @[Mux.scala 27:72] + wire _T_1504 = _T_1396 & _T_1114; // @[Mux.scala 27:72] + wire _T_1505 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1507 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1508 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1509 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1510 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1511 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1512 = _T_1413 & _T_1132; // @[Mux.scala 27:72] + wire _T_1513 = _T_1417 & _T_1136; // @[Mux.scala 27:72] + wire _T_1514 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1515 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1516 = _T_1425 & _T_1144; // @[Mux.scala 27:72] + wire _T_1517 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1518 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1519 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1520 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1521 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1522 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1523 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1524 = _T_1443 & _T_1163; // @[Mux.scala 27:72] + wire _T_1525 = _T_1448 & _T_1173; // @[Mux.scala 27:72] + wire _T_1526 = _T_1458 & _T_1176; // @[Mux.scala 27:72] + wire _T_1527 = _T_1461 & _T_1179; // @[Mux.scala 27:72] + wire _T_1528 = _T_1464 & _T_1182; // @[Mux.scala 27:72] + wire _T_1529 = _T_1467 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1530 = _T_1469 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1531 = _T_1471 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1532 = _T_1473 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1533 = _T_1475 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1534 = _T_1310 | _T_1478; // @[Mux.scala 27:72] + wire _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72] wire _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72] wire _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72] wire _T_1538 = _T_1537 | _T_1482; // @[Mux.scala 27:72] @@ -51794,8 +51796,8 @@ module csr_tlu( wire _T_1559 = _T_1558 | _T_1503; // @[Mux.scala 27:72] wire _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72] wire _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72] - wire _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72] - wire _T_1563 = _T_1562 | _T_1486; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1485; // @[Mux.scala 27:72] + wire _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72] wire _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72] wire _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72] wire _T_1566 = _T_1565 | _T_1510; // @[Mux.scala 27:72] @@ -51822,122 +51824,122 @@ module csr_tlu( wire _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72] wire _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72] wire _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72] - wire _T_1590 = _T_1589 | _T_1534; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1310 & _T_1590; // @[dec_tlu_ctl.scala 2272:44] - wire _T_1594 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2272:24] + wire mhpmc_inc_r_1 = _T_1309 & _T_1589; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1593 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1595 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1597 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1599 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1601 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1605 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1611 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1616 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1618 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1620 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1622 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1625 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1628 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1631 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1634 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1638 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1643 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1646 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1649 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1652 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1655 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1658 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1661 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1664 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1667 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1670 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1675 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1678 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1681 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1684 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1688 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1690 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1692 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1694 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1696 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1698 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1702 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1706 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1708 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1710 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1714 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1716 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1718 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1720 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1722 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1724 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1726 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1728 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1733 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1743 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1746 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1749 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1752 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1754 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1756 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1758 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1760 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1763 = _T_1597 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1764 = _T_1599 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1765 = _T_1601 & _T_1036; // @[Mux.scala 27:72] - wire _T_1766 = _T_1605 & _T_1042; // @[Mux.scala 27:72] - wire _T_1767 = _T_1611 & _T_1047; // @[Mux.scala 27:72] - wire _T_1768 = _T_1616 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1769 = _T_1618 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1770 = _T_1620 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1771 = _T_1622 & _T_1056; // @[Mux.scala 27:72] - wire _T_1772 = _T_1625 & _T_1059; // @[Mux.scala 27:72] - wire _T_1773 = _T_1628 & _T_1062; // @[Mux.scala 27:72] - wire _T_1774 = _T_1631 & _T_1065; // @[Mux.scala 27:72] - wire _T_1775 = _T_1634 & _T_1069; // @[Mux.scala 27:72] - wire _T_1776 = _T_1638 & _T_1074; // @[Mux.scala 27:72] - wire _T_1777 = _T_1643 & _T_1077; // @[Mux.scala 27:72] - wire _T_1778 = _T_1646 & _T_1080; // @[Mux.scala 27:72] - wire _T_1779 = _T_1649 & _T_1083; // @[Mux.scala 27:72] - wire _T_1780 = _T_1652 & _T_1086; // @[Mux.scala 27:72] - wire _T_1781 = _T_1655 & _T_1089; // @[Mux.scala 27:72] - wire _T_1782 = _T_1658 & _T_1092; // @[Mux.scala 27:72] - wire _T_1783 = _T_1661 & _T_1095; // @[Mux.scala 27:72] - wire _T_1784 = _T_1664 & _T_1098; // @[Mux.scala 27:72] - wire _T_1785 = _T_1667 & _T_1101; // @[Mux.scala 27:72] - wire _T_1786 = _T_1670 & _T_1106; // @[Mux.scala 27:72] - wire _T_1787 = _T_1675 & _T_1109; // @[Mux.scala 27:72] - wire _T_1788 = _T_1678 & _T_1112; // @[Mux.scala 27:72] - wire _T_1789 = _T_1681 & _T_1115; // @[Mux.scala 27:72] - wire _T_1790 = _T_1684 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1792 = _T_1688 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1793 = _T_1690 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1794 = _T_1692 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1795 = _T_1694 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1796 = _T_1696 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1797 = _T_1698 & _T_1133; // @[Mux.scala 27:72] - wire _T_1798 = _T_1702 & _T_1137; // @[Mux.scala 27:72] - wire _T_1799 = _T_1706 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1800 = _T_1708 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1801 = _T_1710 & _T_1145; // @[Mux.scala 27:72] - wire _T_1802 = _T_1714 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1803 = _T_1716 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1804 = _T_1718 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1805 = _T_1720 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1806 = _T_1722 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1807 = _T_1724 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1808 = _T_1726 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1809 = _T_1728 & _T_1164; // @[Mux.scala 27:72] - wire _T_1810 = _T_1733 & _T_1174; // @[Mux.scala 27:72] - wire _T_1811 = _T_1743 & _T_1177; // @[Mux.scala 27:72] - wire _T_1812 = _T_1746 & _T_1180; // @[Mux.scala 27:72] - wire _T_1813 = _T_1749 & _T_1183; // @[Mux.scala 27:72] - wire _T_1814 = _T_1752 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1815 = _T_1754 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1816 = _T_1756 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1817 = _T_1758 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1818 = _T_1760 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1819 = _T_1595 | _T_1763; // @[Mux.scala 27:72] + wire _T_1594 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1596 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1598 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1600 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1604 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1610 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1615 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1617 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1619 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1621 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1624 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1627 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1630 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1633 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1637 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1642 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1645 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1648 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1651 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1654 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1657 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1660 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1663 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1666 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1669 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1674 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1677 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1680 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1683 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1687 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1689 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1691 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1693 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1695 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1697 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1701 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1705 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1707 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1709 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1713 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1715 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1717 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1719 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1721 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1723 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1725 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1727 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1732 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1742 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1745 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1748 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1751 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1753 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1755 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1757 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1759 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1762 = _T_1596 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1763 = _T_1598 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1764 = _T_1600 & _T_1035; // @[Mux.scala 27:72] + wire _T_1765 = _T_1604 & _T_1041; // @[Mux.scala 27:72] + wire _T_1766 = _T_1610 & _T_1046; // @[Mux.scala 27:72] + wire _T_1767 = _T_1615 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1768 = _T_1617 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1769 = _T_1619 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1770 = _T_1621 & _T_1055; // @[Mux.scala 27:72] + wire _T_1771 = _T_1624 & _T_1058; // @[Mux.scala 27:72] + wire _T_1772 = _T_1627 & _T_1061; // @[Mux.scala 27:72] + wire _T_1773 = _T_1630 & _T_1064; // @[Mux.scala 27:72] + wire _T_1774 = _T_1633 & _T_1068; // @[Mux.scala 27:72] + wire _T_1775 = _T_1637 & _T_1073; // @[Mux.scala 27:72] + wire _T_1776 = _T_1642 & _T_1076; // @[Mux.scala 27:72] + wire _T_1777 = _T_1645 & _T_1079; // @[Mux.scala 27:72] + wire _T_1778 = _T_1648 & _T_1082; // @[Mux.scala 27:72] + wire _T_1779 = _T_1651 & _T_1085; // @[Mux.scala 27:72] + wire _T_1780 = _T_1654 & _T_1088; // @[Mux.scala 27:72] + wire _T_1781 = _T_1657 & _T_1091; // @[Mux.scala 27:72] + wire _T_1782 = _T_1660 & _T_1094; // @[Mux.scala 27:72] + wire _T_1783 = _T_1663 & _T_1097; // @[Mux.scala 27:72] + wire _T_1784 = _T_1666 & _T_1100; // @[Mux.scala 27:72] + wire _T_1785 = _T_1669 & _T_1105; // @[Mux.scala 27:72] + wire _T_1786 = _T_1674 & _T_1108; // @[Mux.scala 27:72] + wire _T_1787 = _T_1677 & _T_1111; // @[Mux.scala 27:72] + wire _T_1788 = _T_1680 & _T_1114; // @[Mux.scala 27:72] + wire _T_1789 = _T_1683 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1791 = _T_1687 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1792 = _T_1689 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1793 = _T_1691 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1794 = _T_1693 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1795 = _T_1695 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1796 = _T_1697 & _T_1132; // @[Mux.scala 27:72] + wire _T_1797 = _T_1701 & _T_1136; // @[Mux.scala 27:72] + wire _T_1798 = _T_1705 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1799 = _T_1707 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1800 = _T_1709 & _T_1144; // @[Mux.scala 27:72] + wire _T_1801 = _T_1713 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1802 = _T_1715 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1803 = _T_1717 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1804 = _T_1719 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1805 = _T_1721 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1806 = _T_1723 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1807 = _T_1725 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1808 = _T_1727 & _T_1163; // @[Mux.scala 27:72] + wire _T_1809 = _T_1732 & _T_1173; // @[Mux.scala 27:72] + wire _T_1810 = _T_1742 & _T_1176; // @[Mux.scala 27:72] + wire _T_1811 = _T_1745 & _T_1179; // @[Mux.scala 27:72] + wire _T_1812 = _T_1748 & _T_1182; // @[Mux.scala 27:72] + wire _T_1813 = _T_1751 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1814 = _T_1753 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1815 = _T_1755 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1816 = _T_1757 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1817 = _T_1759 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1818 = _T_1594 | _T_1762; // @[Mux.scala 27:72] + wire _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72] wire _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72] wire _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72] wire _T_1822 = _T_1821 | _T_1766; // @[Mux.scala 27:72] @@ -51964,8 +51966,8 @@ module csr_tlu( wire _T_1843 = _T_1842 | _T_1787; // @[Mux.scala 27:72] wire _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72] wire _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72] - wire _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72] - wire _T_1847 = _T_1846 | _T_1770; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1769; // @[Mux.scala 27:72] + wire _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72] wire _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72] wire _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72] wire _T_1850 = _T_1849 | _T_1794; // @[Mux.scala 27:72] @@ -51992,122 +51994,122 @@ module csr_tlu( wire _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72] wire _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72] wire _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72] - wire _T_1874 = _T_1873 | _T_1818; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1594 & _T_1874; // @[dec_tlu_ctl.scala 2272:44] - wire _T_1878 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2272:24] + wire mhpmc_inc_r_2 = _T_1593 & _T_1873; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1877 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1879 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1881 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1883 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1885 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1889 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1895 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1900 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1902 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1904 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1906 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1909 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1912 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1915 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1918 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1922 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1927 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1930 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1933 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1936 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1939 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1942 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1945 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1948 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1951 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1954 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1959 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1962 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1965 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1968 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1972 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1974 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1976 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1978 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1980 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1982 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1986 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1990 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1992 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1994 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1998 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] - wire _T_2000 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] - wire _T_2002 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] - wire _T_2004 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] - wire _T_2006 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] - wire _T_2008 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] - wire _T_2010 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] - wire _T_2012 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] - wire _T_2017 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] - wire _T_2027 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] - wire _T_2030 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] - wire _T_2033 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] - wire _T_2036 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] - wire _T_2038 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] - wire _T_2040 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] - wire _T_2042 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] - wire _T_2044 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] - wire _T_2047 = _T_1881 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_2048 = _T_1883 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_2049 = _T_1885 & _T_1036; // @[Mux.scala 27:72] - wire _T_2050 = _T_1889 & _T_1042; // @[Mux.scala 27:72] - wire _T_2051 = _T_1895 & _T_1047; // @[Mux.scala 27:72] - wire _T_2052 = _T_1900 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_2053 = _T_1902 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_2054 = _T_1904 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_2055 = _T_1906 & _T_1056; // @[Mux.scala 27:72] - wire _T_2056 = _T_1909 & _T_1059; // @[Mux.scala 27:72] - wire _T_2057 = _T_1912 & _T_1062; // @[Mux.scala 27:72] - wire _T_2058 = _T_1915 & _T_1065; // @[Mux.scala 27:72] - wire _T_2059 = _T_1918 & _T_1069; // @[Mux.scala 27:72] - wire _T_2060 = _T_1922 & _T_1074; // @[Mux.scala 27:72] - wire _T_2061 = _T_1927 & _T_1077; // @[Mux.scala 27:72] - wire _T_2062 = _T_1930 & _T_1080; // @[Mux.scala 27:72] - wire _T_2063 = _T_1933 & _T_1083; // @[Mux.scala 27:72] - wire _T_2064 = _T_1936 & _T_1086; // @[Mux.scala 27:72] - wire _T_2065 = _T_1939 & _T_1089; // @[Mux.scala 27:72] - wire _T_2066 = _T_1942 & _T_1092; // @[Mux.scala 27:72] - wire _T_2067 = _T_1945 & _T_1095; // @[Mux.scala 27:72] - wire _T_2068 = _T_1948 & _T_1098; // @[Mux.scala 27:72] - wire _T_2069 = _T_1951 & _T_1101; // @[Mux.scala 27:72] - wire _T_2070 = _T_1954 & _T_1106; // @[Mux.scala 27:72] - wire _T_2071 = _T_1959 & _T_1109; // @[Mux.scala 27:72] - wire _T_2072 = _T_1962 & _T_1112; // @[Mux.scala 27:72] - wire _T_2073 = _T_1965 & _T_1115; // @[Mux.scala 27:72] - wire _T_2074 = _T_1968 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_2076 = _T_1972 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_2077 = _T_1974 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_2078 = _T_1976 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_2079 = _T_1978 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_2080 = _T_1980 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_2081 = _T_1982 & _T_1133; // @[Mux.scala 27:72] - wire _T_2082 = _T_1986 & _T_1137; // @[Mux.scala 27:72] - wire _T_2083 = _T_1990 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_2084 = _T_1992 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_2085 = _T_1994 & _T_1145; // @[Mux.scala 27:72] - wire _T_2086 = _T_1998 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2087 = _T_2000 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2088 = _T_2002 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_2089 = _T_2004 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2090 = _T_2006 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2091 = _T_2008 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2092 = _T_2010 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2093 = _T_2012 & _T_1164; // @[Mux.scala 27:72] - wire _T_2094 = _T_2017 & _T_1174; // @[Mux.scala 27:72] - wire _T_2095 = _T_2027 & _T_1177; // @[Mux.scala 27:72] - wire _T_2096 = _T_2030 & _T_1180; // @[Mux.scala 27:72] - wire _T_2097 = _T_2033 & _T_1183; // @[Mux.scala 27:72] - wire _T_2098 = _T_2036 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_2099 = _T_2038 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_2100 = _T_2040 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_2101 = _T_2042 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_2102 = _T_2044 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_2103 = _T_1879 | _T_2047; // @[Mux.scala 27:72] + wire _T_1878 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1880 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1882 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1884 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1888 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1894 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1899 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1901 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1903 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1905 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1908 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1911 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1914 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1917 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1921 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1926 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1929 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1932 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1935 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1938 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1941 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1944 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1947 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1950 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1953 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1958 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1961 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1964 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1967 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1971 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1973 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1975 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1977 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1979 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1981 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1985 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1989 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1991 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1993 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1997 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1999 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_2001 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_2003 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_2005 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_2007 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_2009 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_2011 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_2016 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_2026 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_2029 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_2032 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_2035 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_2037 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_2039 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_2041 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_2043 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_2046 = _T_1880 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2047 = _T_1882 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2048 = _T_1884 & _T_1035; // @[Mux.scala 27:72] + wire _T_2049 = _T_1888 & _T_1041; // @[Mux.scala 27:72] + wire _T_2050 = _T_1894 & _T_1046; // @[Mux.scala 27:72] + wire _T_2051 = _T_1899 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2052 = _T_1901 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2053 = _T_1903 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2054 = _T_1905 & _T_1055; // @[Mux.scala 27:72] + wire _T_2055 = _T_1908 & _T_1058; // @[Mux.scala 27:72] + wire _T_2056 = _T_1911 & _T_1061; // @[Mux.scala 27:72] + wire _T_2057 = _T_1914 & _T_1064; // @[Mux.scala 27:72] + wire _T_2058 = _T_1917 & _T_1068; // @[Mux.scala 27:72] + wire _T_2059 = _T_1921 & _T_1073; // @[Mux.scala 27:72] + wire _T_2060 = _T_1926 & _T_1076; // @[Mux.scala 27:72] + wire _T_2061 = _T_1929 & _T_1079; // @[Mux.scala 27:72] + wire _T_2062 = _T_1932 & _T_1082; // @[Mux.scala 27:72] + wire _T_2063 = _T_1935 & _T_1085; // @[Mux.scala 27:72] + wire _T_2064 = _T_1938 & _T_1088; // @[Mux.scala 27:72] + wire _T_2065 = _T_1941 & _T_1091; // @[Mux.scala 27:72] + wire _T_2066 = _T_1944 & _T_1094; // @[Mux.scala 27:72] + wire _T_2067 = _T_1947 & _T_1097; // @[Mux.scala 27:72] + wire _T_2068 = _T_1950 & _T_1100; // @[Mux.scala 27:72] + wire _T_2069 = _T_1953 & _T_1105; // @[Mux.scala 27:72] + wire _T_2070 = _T_1958 & _T_1108; // @[Mux.scala 27:72] + wire _T_2071 = _T_1961 & _T_1111; // @[Mux.scala 27:72] + wire _T_2072 = _T_1964 & _T_1114; // @[Mux.scala 27:72] + wire _T_2073 = _T_1967 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2075 = _T_1971 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2076 = _T_1973 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2077 = _T_1975 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2078 = _T_1977 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2079 = _T_1979 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2080 = _T_1981 & _T_1132; // @[Mux.scala 27:72] + wire _T_2081 = _T_1985 & _T_1136; // @[Mux.scala 27:72] + wire _T_2082 = _T_1989 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2083 = _T_1991 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2084 = _T_1993 & _T_1144; // @[Mux.scala 27:72] + wire _T_2085 = _T_1997 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2086 = _T_1999 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2087 = _T_2001 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2088 = _T_2003 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2089 = _T_2005 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2090 = _T_2007 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2091 = _T_2009 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2092 = _T_2011 & _T_1163; // @[Mux.scala 27:72] + wire _T_2093 = _T_2016 & _T_1173; // @[Mux.scala 27:72] + wire _T_2094 = _T_2026 & _T_1176; // @[Mux.scala 27:72] + wire _T_2095 = _T_2029 & _T_1179; // @[Mux.scala 27:72] + wire _T_2096 = _T_2032 & _T_1182; // @[Mux.scala 27:72] + wire _T_2097 = _T_2035 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2098 = _T_2037 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2099 = _T_2039 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2100 = _T_2041 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2101 = _T_2043 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2102 = _T_1878 | _T_2046; // @[Mux.scala 27:72] + wire _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72] wire _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72] wire _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72] wire _T_2106 = _T_2105 | _T_2050; // @[Mux.scala 27:72] @@ -52134,8 +52136,8 @@ module csr_tlu( wire _T_2127 = _T_2126 | _T_2071; // @[Mux.scala 27:72] wire _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72] wire _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72] - wire _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72] - wire _T_2131 = _T_2130 | _T_2054; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2053; // @[Mux.scala 27:72] + wire _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72] wire _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72] wire _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72] wire _T_2134 = _T_2133 | _T_2078; // @[Mux.scala 27:72] @@ -52162,187 +52164,187 @@ module csr_tlu( wire _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72] wire _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72] wire _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72] - wire _T_2158 = _T_2157 | _T_2102; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1878 & _T_2158; // @[dec_tlu_ctl.scala 2272:44] - reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2333:53] - reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2334:53] - reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2335:53] - reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2336:53] - reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2337:56] - wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2340:67] - wire _T_2170 = ~_T_85; // @[dec_tlu_ctl.scala 2341:37] - wire [3:0] _T_2172 = _T_2170 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_2179 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2172 & _T_2179; // @[dec_tlu_ctl.scala 2341:86] - wire _T_2181 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2343:67] - wire _T_2182 = perfcnt_halted_d1 & _T_2181; // @[dec_tlu_ctl.scala 2343:65] - wire _T_2183 = ~_T_2182; // @[dec_tlu_ctl.scala 2343:45] - wire _T_2186 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2344:67] - wire _T_2187 = perfcnt_halted_d1 & _T_2186; // @[dec_tlu_ctl.scala 2344:65] - wire _T_2188 = ~_T_2187; // @[dec_tlu_ctl.scala 2344:45] - wire _T_2191 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2345:67] - wire _T_2192 = perfcnt_halted_d1 & _T_2191; // @[dec_tlu_ctl.scala 2345:65] - wire _T_2193 = ~_T_2192; // @[dec_tlu_ctl.scala 2345:45] - wire _T_2196 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2346:67] - wire _T_2197 = perfcnt_halted_d1 & _T_2196; // @[dec_tlu_ctl.scala 2346:65] - wire _T_2198 = ~_T_2197; // @[dec_tlu_ctl.scala 2346:45] - wire _T_2201 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2352:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2201; // @[dec_tlu_ctl.scala 2352:43] - wire _T_2202 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2353:23] - wire _T_2204 = _T_2202 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2353:39] - wire _T_2205 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2353:86] - wire mhpmc3_wr_en1 = _T_2204 & _T_2205; // @[dec_tlu_ctl.scala 2353:66] + wire mhpmc_inc_r_3 = _T_1877 & _T_2157; // @[dec_tlu_ctl.scala 2273:44] + reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2334:53] + reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2335:53] + reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2336:53] + reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2337:53] + reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2338:56] + wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2341:67] + wire _T_2169 = ~_T_85; // @[dec_tlu_ctl.scala 2342:37] + wire [3:0] _T_2171 = _T_2169 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2178 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2171 & _T_2178; // @[dec_tlu_ctl.scala 2342:86] + wire _T_2180 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2344:67] + wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2344:65] + wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2344:45] + wire _T_2185 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2345:67] + wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2345:65] + wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2345:45] + wire _T_2190 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2346:67] + wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[dec_tlu_ctl.scala 2346:65] + wire _T_2192 = ~_T_2191; // @[dec_tlu_ctl.scala 2346:45] + wire _T_2195 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2347:67] + wire _T_2196 = perfcnt_halted_d1 & _T_2195; // @[dec_tlu_ctl.scala 2347:65] + wire _T_2197 = ~_T_2196; // @[dec_tlu_ctl.scala 2347:45] + wire _T_2200 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2353:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2200; // @[dec_tlu_ctl.scala 2353:43] + wire _T_2201 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2354:23] + wire _T_2203 = _T_2201 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2354:39] + wire _T_2204 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2354:86] + wire mhpmc3_wr_en1 = _T_2203 & _T_2204; // @[dec_tlu_ctl.scala 2354:66] reg [31:0] mhpmc3h; // @[lib.scala 374:16] reg [31:0] mhpmc3; // @[lib.scala 374:16] - wire [63:0] _T_2208 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] - wire [63:0] _T_2209 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2208 + _T_2209; // @[dec_tlu_ctl.scala 2357:49] - wire _T_2217 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2362:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2217; // @[dec_tlu_ctl.scala 2362:44] - wire _T_2223 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2371:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2223; // @[dec_tlu_ctl.scala 2371:43] - wire _T_2226 = _T_2202 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2372:39] - wire _T_2227 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2372:86] - wire mhpmc4_wr_en1 = _T_2226 & _T_2227; // @[dec_tlu_ctl.scala 2372:66] + wire [63:0] _T_2207 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2208 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2207 + _T_2208; // @[dec_tlu_ctl.scala 2358:49] + wire _T_2216 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2363:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2216; // @[dec_tlu_ctl.scala 2363:44] + wire _T_2222 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2372:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2222; // @[dec_tlu_ctl.scala 2372:43] + wire _T_2225 = _T_2201 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2373:39] + wire _T_2226 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2373:86] + wire mhpmc4_wr_en1 = _T_2225 & _T_2226; // @[dec_tlu_ctl.scala 2373:66] reg [31:0] mhpmc4h; // @[lib.scala 374:16] reg [31:0] mhpmc4; // @[lib.scala 374:16] - wire [63:0] _T_2230 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] - wire [63:0] _T_2231 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2230 + _T_2231; // @[dec_tlu_ctl.scala 2377:49] - wire _T_2240 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2381:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2240; // @[dec_tlu_ctl.scala 2381:44] - wire _T_2246 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2390:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2246; // @[dec_tlu_ctl.scala 2390:43] - wire _T_2249 = _T_2202 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2391:39] - wire _T_2250 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2391:86] - wire mhpmc5_wr_en1 = _T_2249 & _T_2250; // @[dec_tlu_ctl.scala 2391:66] + wire [63:0] _T_2229 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2230 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2229 + _T_2230; // @[dec_tlu_ctl.scala 2378:49] + wire _T_2239 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2382:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2239; // @[dec_tlu_ctl.scala 2382:44] + wire _T_2245 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2391:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2245; // @[dec_tlu_ctl.scala 2391:43] + wire _T_2248 = _T_2201 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2392:39] + wire _T_2249 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2392:86] + wire mhpmc5_wr_en1 = _T_2248 & _T_2249; // @[dec_tlu_ctl.scala 2392:66] reg [31:0] mhpmc5h; // @[lib.scala 374:16] reg [31:0] mhpmc5; // @[lib.scala 374:16] - wire [63:0] _T_2253 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] - wire [63:0] _T_2254 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2253 + _T_2254; // @[dec_tlu_ctl.scala 2394:49] - wire _T_2262 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2399:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2262; // @[dec_tlu_ctl.scala 2399:44] - wire _T_2268 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2408:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2268; // @[dec_tlu_ctl.scala 2408:43] - wire _T_2271 = _T_2202 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2409:39] - wire _T_2272 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2409:86] - wire mhpmc6_wr_en1 = _T_2271 & _T_2272; // @[dec_tlu_ctl.scala 2409:66] + wire [63:0] _T_2252 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2253 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2252 + _T_2253; // @[dec_tlu_ctl.scala 2395:49] + wire _T_2261 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2400:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2261; // @[dec_tlu_ctl.scala 2400:44] + wire _T_2267 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2409:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2267; // @[dec_tlu_ctl.scala 2409:43] + wire _T_2270 = _T_2201 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2410:39] + wire _T_2271 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2410:86] + wire mhpmc6_wr_en1 = _T_2270 & _T_2271; // @[dec_tlu_ctl.scala 2410:66] reg [31:0] mhpmc6h; // @[lib.scala 374:16] reg [31:0] mhpmc6; // @[lib.scala 374:16] - wire [63:0] _T_2275 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] - wire [63:0] _T_2276 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2275 + _T_2276; // @[dec_tlu_ctl.scala 2412:49] - wire _T_2284 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2417:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2284; // @[dec_tlu_ctl.scala 2417:44] - wire _T_2290 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2428:56] - wire _T_2292 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2428:102] - wire _T_2293 = _T_2290 | _T_2292; // @[dec_tlu_ctl.scala 2428:71] - wire _T_2296 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2430:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2296; // @[dec_tlu_ctl.scala 2430:41] - wire _T_2300 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2437:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2300; // @[dec_tlu_ctl.scala 2437:41] - wire _T_2304 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2444:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2304; // @[dec_tlu_ctl.scala 2444:41] - wire _T_2308 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2451:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2308; // @[dec_tlu_ctl.scala 2451:41] - wire _T_2312 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2468:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2312; // @[dec_tlu_ctl.scala 2468:48] - wire _T_2324 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2483:51] - wire _T_2325 = _T_2324 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2483:78] - wire _T_2326 = _T_2325 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2483:104] - wire _T_2327 = _T_2326 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2483:130] - wire _T_2328 = _T_2327 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2484:32] - reg _T_2331; // @[dec_tlu_ctl.scala 2486:62] - wire _T_2332 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2487:91] - wire _T_2333 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2487:137] - wire _T_2334 = io_trigger_hit_r_d1 & _T_2333; // @[dec_tlu_ctl.scala 2487:135] - reg _T_2336; // @[dec_tlu_ctl.scala 2487:62] - reg [4:0] _T_2337; // @[dec_tlu_ctl.scala 2488:62] - reg _T_2338; // @[dec_tlu_ctl.scala 2489:62] - wire [31:0] _T_2344 = {io_core_id,4'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2353 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2358 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2371 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2384 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2396 = {io_mepc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2401 = {28'h0,mscause}; // @[Cat.scala 29:58] - wire [31:0] _T_2409 = {meivt,10'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2412 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2415 = {28'h0,meicurpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2418 = {28'h0,meicidpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2421 = {28'h0,meipt}; // @[Cat.scala 29:58] - wire [31:0] _T_2424 = {23'h0,mcgc}; // @[Cat.scala 29:58] - wire [31:0] _T_2427 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2431 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] - wire [31:0] _T_2433 = {io_dpc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2449 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2452 = {30'h0,mtsel}; // @[Cat.scala 29:58] - wire [31:0] _T_2481 = {26'h0,mfdht}; // @[Cat.scala 29:58] - wire [31:0] _T_2484 = {30'h0,mfdhs}; // @[Cat.scala 29:58] - wire [31:0] _T_2487 = {22'h0,mhpme3}; // @[Cat.scala 29:58] - wire [31:0] _T_2490 = {22'h0,mhpme4}; // @[Cat.scala 29:58] - wire [31:0] _T_2493 = {22'h0,mhpme5}; // @[Cat.scala 29:58] - wire [31:0] _T_2496 = {22'h0,mhpme6}; // @[Cat.scala 29:58] - wire [31:0] _T_2499 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire [31:0] _T_2502 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2505 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2506 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2507 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2508 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2509 = io_csr_pkt_csr_mhartid ? _T_2344 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2510 = io_csr_pkt_csr_mstatus ? _T_2353 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2511 = io_csr_pkt_csr_mtvec ? _T_2358 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2512 = io_csr_pkt_csr_mip ? _T_2371 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2513 = io_csr_pkt_csr_mie ? _T_2384 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2514 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2515 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2516 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2517 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2518 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2519 = io_csr_pkt_csr_mepc ? _T_2396 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2520 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2521 = io_csr_pkt_csr_mscause ? _T_2401 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2522 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2523 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2524 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2525 = io_csr_pkt_csr_meivt ? _T_2409 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2526 = io_csr_pkt_csr_meihap ? _T_2412 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2527 = io_csr_pkt_csr_meicurpl ? _T_2415 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2528 = io_csr_pkt_csr_meicidpl ? _T_2418 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2529 = io_csr_pkt_csr_meipt ? _T_2421 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2530 = io_csr_pkt_csr_mcgc ? _T_2424 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2531 = io_csr_pkt_csr_mfdc ? _T_2427 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2532 = io_csr_pkt_csr_dcsr ? _T_2431 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2533 = io_csr_pkt_csr_dpc ? _T_2433 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2535 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2536 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2537 = io_csr_pkt_csr_dicawics ? _T_2449 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2538 = io_csr_pkt_csr_mtsel ? _T_2452 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2540 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2541 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2542 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2543 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2551 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2552 = io_csr_pkt_csr_mfdht ? _T_2481 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2553 = io_csr_pkt_csr_mfdhs ? _T_2484 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme3 ? _T_2487 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme4 ? _T_2490 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme5 ? _T_2493 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2557 = io_csr_pkt_csr_mhpme6 ? _T_2496 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2558 = io_csr_pkt_csr_mcountinhibit ? _T_2499 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2559 = io_csr_pkt_csr_mpmc ? _T_2502 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2560 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2561 = _T_2505 | _T_2506; // @[Mux.scala 27:72] + wire [63:0] _T_2274 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2275 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2274 + _T_2275; // @[dec_tlu_ctl.scala 2413:49] + wire _T_2283 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2418:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2283; // @[dec_tlu_ctl.scala 2418:44] + wire _T_2289 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2429:56] + wire _T_2291 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2429:102] + wire _T_2292 = _T_2289 | _T_2291; // @[dec_tlu_ctl.scala 2429:71] + wire _T_2295 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2431:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2431:41] + wire _T_2299 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2438:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2438:41] + wire _T_2303 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2445:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2445:41] + wire _T_2307 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2452:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2307; // @[dec_tlu_ctl.scala 2452:41] + wire _T_2311 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2469:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2311; // @[dec_tlu_ctl.scala 2469:48] + wire _T_2323 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2484:51] + wire _T_2324 = _T_2323 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2484:78] + wire _T_2325 = _T_2324 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2484:104] + wire _T_2326 = _T_2325 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2484:130] + wire _T_2327 = _T_2326 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2485:32] + reg _T_2330; // @[dec_tlu_ctl.scala 2487:62] + wire _T_2331 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2488:91] + wire _T_2332 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2488:137] + wire _T_2333 = io_trigger_hit_r_d1 & _T_2332; // @[dec_tlu_ctl.scala 2488:135] + reg _T_2335; // @[dec_tlu_ctl.scala 2488:62] + reg [4:0] _T_2336; // @[dec_tlu_ctl.scala 2489:62] + reg _T_2337; // @[dec_tlu_ctl.scala 2490:62] + wire [31:0] _T_2343 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2352 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2357 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2370 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2383 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2395 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2400 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2408 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2411 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2414 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2417 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2420 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2423 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2426 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2430 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2432 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2448 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2451 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2480 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2483 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2486 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2489 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2492 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2495 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2498 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2501 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2504 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2505 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mhartid ? _T_2343 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mstatus ? _T_2352 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_mtvec ? _T_2357 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_mip ? _T_2370 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mie ? _T_2383 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_mepc ? _T_2395 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_mscause ? _T_2400 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_meivt ? _T_2408 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_meihap ? _T_2411 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_meicurpl ? _T_2414 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_meicidpl ? _T_2417 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_meipt ? _T_2420 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_mcgc ? _T_2423 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_mfdc ? _T_2426 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_dcsr ? _T_2430 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_dpc ? _T_2432 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_dicawics ? _T_2448 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_mtsel ? _T_2451 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_csr_pkt_csr_mfdht ? _T_2480 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = io_csr_pkt_csr_mfdhs ? _T_2483 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = io_csr_pkt_csr_mhpme3 ? _T_2486 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme4 ? _T_2489 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme5 ? _T_2492 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme6 ? _T_2495 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = io_csr_pkt_csr_mcountinhibit ? _T_2498 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = io_csr_pkt_csr_mpmc ? _T_2501 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = _T_2504 | _T_2505; // @[Mux.scala 27:72] + wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] wire [31:0] _T_2564 = _T_2563 | _T_2509; // @[Mux.scala 27:72] @@ -52395,7 +52397,6 @@ module csr_tlu( wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72] wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72] wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72] - wire [31:0] _T_2614 = _T_2613 | _T_2559; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -52606,54 +52607,54 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_764,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2153:56] - assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2156:41] - assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2164:41] - assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2165:41] - assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2229:40] - assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2230:43] - assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2247:51] - assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2229:40] - assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2230:43] - assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2247:51] - assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2229:40] - assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2230:43] - assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2247:51] - assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2229:40] - assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2230:43] - assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2247:51] - assign io_dec_tlu_int_valid_wb1 = _T_2338; // @[dec_tlu_ctl.scala 2489:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2487:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2331; // @[dec_tlu_ctl.scala 2486:30] - assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2491:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2488:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2183; // @[dec_tlu_ctl.scala 2343:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2188; // @[dec_tlu_ctl.scala 2344:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2193; // @[dec_tlu_ctl.scala 2345:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2198; // @[dec_tlu_ctl.scala 2346:22] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_763,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2154:56] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2157:41] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2165:41] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2166:41] + assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2230:40] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2231:43] + assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2248:51] + assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2230:40] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2231:43] + assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2248:51] + assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2230:40] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2231:43] + assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2248:51] + assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2230:40] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2231:43] + assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2248:51] + assign io_dec_tlu_int_valid_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2490:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2335; // @[dec_tlu_ctl.scala 2488:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2330; // @[dec_tlu_ctl.scala 2487:30] + assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2492:24] + assign io_dec_tlu_exc_cause_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2489:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2182; // @[dec_tlu_ctl.scala 2344:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2187; // @[dec_tlu_ctl.scala 2345:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2192; // @[dec_tlu_ctl.scala 2346:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2197; // @[dec_tlu_ctl.scala 2347:22] assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1716:31] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1717:31] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1719:31] assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1721:31] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1722:31] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1723:31] - assign io_dec_csr_rddata_d = _T_2614 | _T_2560; // @[dec_tlu_ctl.scala 2496:21] + assign io_dec_csr_rddata_d = _T_2613 | _T_2559; // @[dec_tlu_ctl.scala 2497:21] assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1766:39] assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1775:24] assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2004:19] @@ -52680,10 +52681,10 @@ module csr_tlu( assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1823:22] assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1931:16] assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2068:9] - assign io_mtdata1_t_0 = _T_873; // @[dec_tlu_ctl.scala 2224:39] - assign io_mtdata1_t_1 = _T_874; // @[dec_tlu_ctl.scala 2224:39] - assign io_mtdata1_t_2 = _T_875; // @[dec_tlu_ctl.scala 2224:39] - assign io_mtdata1_t_3 = _T_876; // @[dec_tlu_ctl.scala 2224:39] + assign io_mtdata1_t_0 = _T_872; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_1 = _T_873; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_2 = _T_874; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_3 = _T_875; // @[dec_tlu_ctl.scala 2225:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -52751,16 +52752,16 @@ module csr_tlu( assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_22_io_en = _T_972 & _T_808; // @[lib.scala 371:17] + assign rvclkhdr_22_io_en = _T_971 & _T_807; // @[lib.scala 371:17] assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_23_io_en = _T_981 & _T_817; // @[lib.scala 371:17] + assign rvclkhdr_23_io_en = _T_980 & _T_816; // @[lib.scala 371:17] assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_24_io_en = _T_990 & _T_826; // @[lib.scala 371:17] + assign rvclkhdr_24_io_en = _T_989 & _T_825; // @[lib.scala 371:17] assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_25_io_en = _T_999 & _T_835; // @[lib.scala 371:17] + assign rvclkhdr_25_io_en = _T_998 & _T_834; // @[lib.scala 371:17] assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17] @@ -52787,7 +52788,7 @@ module csr_tlu( assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17] assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_34_io_en = _T_2328 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_34_io_en = _T_2327 | io_clk_override; // @[lib.scala 345:16] assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -52907,7 +52908,7 @@ initial begin _RAND_40 = {1{`RANDOM}}; dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - _T_759 = _RAND_41[6:0]; + _T_758 = _RAND_41[31:0]; _RAND_42 = {1{`RANDOM}}; icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; @@ -52915,13 +52916,13 @@ initial begin _RAND_44 = {1{`RANDOM}}; mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_873 = _RAND_45[9:0]; + _T_872 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_874 = _RAND_46[9:0]; + _T_873 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_875 = _RAND_47[9:0]; + _T_874 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - _T_876 = _RAND_48[9:0]; + _T_875 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; @@ -52965,13 +52966,13 @@ initial begin _RAND_69 = {1{`RANDOM}}; mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2331 = _RAND_70[0:0]; + _T_2330 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2336 = _RAND_71[0:0]; + _T_2335 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2337 = _RAND_72[4:0]; + _T_2336 = _RAND_72[4:0]; _RAND_73 = {1{`RANDOM}}; - _T_2338 = _RAND_73[0:0]; + _T_2337 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -53097,7 +53098,7 @@ initial begin dicad0h = 32'h0; end if (reset) begin - _T_759 = 7'h0; + _T_758 = 32'h0; end if (reset) begin icache_rd_valid_f = 1'h0; @@ -53108,6 +53109,9 @@ initial begin if (reset) begin mtsel = 2'h0; end + if (reset) begin + _T_872 = 10'h0; + end if (reset) begin _T_873 = 10'h0; end @@ -53117,9 +53121,6 @@ initial begin if (reset) begin _T_875 = 10'h0; end - if (reset) begin - _T_876 = 10'h0; - end if (reset) begin mtdata2_t_0 = 32'h0; end @@ -53184,16 +53185,16 @@ initial begin mhpmc6 = 32'h0; end if (reset) begin - _T_2331 = 1'h0; + _T_2330 = 1'h0; end if (reset) begin - _T_2336 = 1'h0; + _T_2335 = 1'h0; end if (reset) begin - _T_2337 = 5'h0; + _T_2336 = 5'h0; end if (reset) begin - _T_2338 = 1'h0; + _T_2337 = 1'h0; end `endif // RANDOMIZE end // initial @@ -53524,12 +53525,12 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_759 <= 7'h0; - end else if (_T_757) begin + _T_758 <= 32'h0; + end else if (_T_756) begin if (_T_752) begin - _T_759 <= io_dec_csr_wrdata_r[6:0]; + _T_758 <= io_dec_csr_wrdata_r; end else begin - _T_759 <= io_ifu_ic_debug_rd_data[70:64]; + _T_758 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; end end end @@ -53537,14 +53538,14 @@ end // initial if (reset) begin icache_rd_valid_f <= 1'h0; end else begin - icache_rd_valid_f <= _T_769 & _T_771; + icache_rd_valid_f <= _T_768 & _T_770; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin icache_wr_valid_f <= 1'h0; end else begin - icache_wr_valid_f <= _T_663 & _T_774; + icache_wr_valid_f <= _T_663 & _T_773; end end always @(posedge io_csr_wr_clk or posedge reset) begin @@ -53556,38 +53557,38 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_873 <= 10'h0; + _T_872 <= 10'h0; end else if (wr_mtdata1_t_r_0) begin + _T_872 <= tdata_wrdata_r; + end else begin + _T_872 <= _T_843; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_873 <= 10'h0; + end else if (wr_mtdata1_t_r_1) begin _T_873 <= tdata_wrdata_r; end else begin - _T_873 <= _T_844; + _T_873 <= _T_852; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin _T_874 <= 10'h0; - end else if (wr_mtdata1_t_r_1) begin + end else if (wr_mtdata1_t_r_2) begin _T_874 <= tdata_wrdata_r; end else begin - _T_874 <= _T_853; + _T_874 <= _T_861; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin _T_875 <= 10'h0; - end else if (wr_mtdata1_t_r_2) begin + end else if (wr_mtdata1_t_r_3) begin _T_875 <= tdata_wrdata_r; end else begin - _T_875 <= _T_862; - end - end - always @(posedge io_active_clk or posedge reset) begin - if (reset) begin - _T_876 <= 10'h0; - end else if (wr_mtdata1_t_r_3) begin - _T_876 <= tdata_wrdata_r; - end else begin - _T_876 <= _T_871; + _T_875 <= _T_870; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin @@ -53622,7 +53623,7 @@ end // initial if (reset) begin mhpme3 <= 10'h0; end else if (wr_mhpme3_r) begin - if (_T_2293) begin + if (_T_2292) begin mhpme3 <= 10'h204; end else begin mhpme3 <= io_dec_csr_wrdata_r[9:0]; @@ -53633,7 +53634,7 @@ end // initial if (reset) begin mhpme4 <= 10'h0; end else if (wr_mhpme4_r) begin - if (_T_2293) begin + if (_T_2292) begin mhpme4 <= 10'h204; end else begin mhpme4 <= io_dec_csr_wrdata_r[9:0]; @@ -53644,7 +53645,7 @@ end // initial if (reset) begin mhpme5 <= 10'h0; end else if (wr_mhpme5_r) begin - if (_T_2293) begin + if (_T_2292) begin mhpme5 <= 10'h204; end else begin mhpme5 <= io_dec_csr_wrdata_r[9:0]; @@ -53655,7 +53656,7 @@ end // initial if (reset) begin mhpme6 <= 10'h0; end else if (wr_mhpme6_r) begin - if (_T_2293) begin + if (_T_2292) begin mhpme6 <= 10'h204; end else begin mhpme6 <= io_dec_csr_wrdata_r[9:0]; @@ -53666,28 +53667,28 @@ end // initial if (reset) begin mhpmc_inc_r_d1_0 <= 1'h0; end else begin - mhpmc_inc_r_d1_0 <= _T_1026 & _T_1306; + mhpmc_inc_r_d1_0 <= _T_1025 & _T_1305; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_1 <= 1'h0; end else begin - mhpmc_inc_r_d1_1 <= _T_1310 & _T_1590; + mhpmc_inc_r_d1_1 <= _T_1309 & _T_1589; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_2 <= 1'h0; end else begin - mhpmc_inc_r_d1_2 <= _T_1594 & _T_1874; + mhpmc_inc_r_d1_2 <= _T_1593 & _T_1873; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_3 <= 1'h0; end else begin - mhpmc_inc_r_d1_3 <= _T_1878 & _T_2158; + mhpmc_inc_r_d1_3 <= _T_1877 & _T_2157; end end always @(posedge io_free_clk or posedge reset) begin @@ -53771,30 +53772,30 @@ end // initial end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2331 <= 1'h0; + _T_2330 <= 1'h0; end else begin - _T_2331 <= io_i0_valid_wb; + _T_2330 <= io_i0_valid_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2336 <= 1'h0; + _T_2335 <= 1'h0; end else begin - _T_2336 <= _T_2332 | _T_2334; + _T_2335 <= _T_2331 | _T_2333; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2337 <= 5'h0; + _T_2336 <= 5'h0; end else begin - _T_2337 <= io_exc_cause_wb; + _T_2336 <= io_exc_cause_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2338 <= 1'h0; + _T_2337 <= 1'h0; end else begin - _T_2338 <= io_interrupt_valid_r_d1; + _T_2337 <= io_interrupt_valid_r_d1; end end endmodule @@ -53868,371 +53869,371 @@ module dec_decode_csr_read( output io_csr_pkt_postsync, output io_csr_pkt_legal ); - wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2568:198] - wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:165] - wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2568:198] - wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2636:81] - wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2636:121] - wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2636:155] - wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2637:97] - wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2638:81] - wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2638:121] - wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2638:162] - wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2568:198] - wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2639:105] - wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2639:145] - wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2568:198] - wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2568:198] - wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2641:81] - wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2641:129] - wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2642:105] - wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2642:153] - wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2643:105] - wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2643:153] - wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2644:105] - wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2644:161] - wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2645:105] - wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2645:161] - wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2646:97] - wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2646:153] - wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2647:105] - wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2647:161] - wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2648:105] - wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2648:161] - wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2649:105] - wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2649:161] - wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2650:105] - wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2650:161] - wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2651:105] - wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2651:153] - wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2652:113] - wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2652:161] - wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2653:97] - wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2653:153] - wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2654:113] - wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:57] - assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2571:57] - assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2572:57] - assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2573:57] - assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:57] - assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2575:57] - assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2576:57] - assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2577:65] - assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2578:65] - assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2579:57] - assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2580:57] - assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2581:57] - assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2582:57] - assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2583:57] - assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2584:57] - assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2585:57] - assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2586:57] - assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2587:57] - assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2588:57] - assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2589:57] - assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2590:57] - assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2591:57] - assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2592:57] - assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2593:57] - assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2594:57] - assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2595:57] - assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2596:57] - assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2597:57] - assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2598:57] - assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2599:65] - assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2600:57] - assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2601:57] - assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2602:57] - assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2603:57] - assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2604:57] - assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2605:57] - assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2606:57] - assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2607:57] - assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2608:57] - assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2609:57] - assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2610:57] - assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2611:57] - assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2612:57] - assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2613:57] - assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2614:57] - assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2615:49] - assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2616:57] - assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2617:57] - assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2618:57] - assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2619:57] - assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2620:57] - assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2621:57] - assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2622:57] - assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2624:57] - assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2626:57] - assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2627:57] - assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2628:57] - assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2629:57] - assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2630:57] - assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2631:57] - assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2632:57] - assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2633:57] - assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2634:57] - assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2635:57] - assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2636:34] - assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2638:30] - assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2641:26] + wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2569:198] + wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:165] + wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2569:198] + wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2637:81] + wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2637:121] + wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2637:155] + wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2638:97] + wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2639:81] + wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2639:121] + wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2639:162] + wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2569:198] + wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2640:105] + wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2640:145] + wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2569:198] + wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2569:198] + wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2642:81] + wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2642:129] + wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2643:105] + wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2643:153] + wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2644:105] + wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2644:153] + wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2645:105] + wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2645:161] + wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2646:105] + wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2646:161] + wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2647:97] + wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2647:153] + wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2648:105] + wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2648:161] + wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2649:105] + wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2649:161] + wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2650:105] + wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2650:161] + wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2651:105] + wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2651:161] + wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2652:105] + wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2652:153] + wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2653:113] + wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2653:161] + wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2654:97] + wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2654:153] + wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2655:113] + wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2571:57] + assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2572:57] + assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2573:57] + assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2574:57] + assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2575:57] + assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2576:57] + assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2577:57] + assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2578:65] + assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2579:65] + assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2580:57] + assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2581:57] + assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2582:57] + assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2583:57] + assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2584:57] + assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2585:57] + assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2586:57] + assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2587:57] + assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2588:57] + assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2589:57] + assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2590:57] + assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2591:57] + assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2592:57] + assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2593:57] + assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2594:57] + assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2595:57] + assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2596:57] + assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2597:57] + assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2598:57] + assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2599:57] + assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2600:65] + assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2601:57] + assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2602:57] + assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2603:57] + assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2604:57] + assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2605:57] + assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2606:57] + assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2607:57] + assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2608:57] + assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2609:57] + assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2610:57] + assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2611:57] + assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2612:57] + assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2613:57] + assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2614:57] + assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2615:57] + assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2616:49] + assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2617:57] + assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2618:57] + assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2619:57] + assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2620:57] + assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2621:57] + assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2622:57] + assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2623:57] + assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2625:57] + assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2627:57] + assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2628:57] + assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2629:57] + assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2630:57] + assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2631:57] + assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2632:57] + assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2633:57] + assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2634:57] + assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2635:57] + assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2636:57] + assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2637:34] + assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2639:30] + assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2642:26] endmodule module dec_tlu_ctl( input clock, diff --git a/quasar_wrapper.anno.json b/quasar_wrapper.anno.json index 50a67c3d..bd0b063d 100644 --- a/quasar_wrapper.anno.json +++ b/quasar_wrapper.anno.json @@ -980,6 +980,10 @@ "class":"firrtl.transforms.DontTouchAnnotation", "target":"~quasar_wrapper|dec_trigger>io_dec_i0_trigger_match_d" }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~quasar_wrapper|csr_tlu>_T_755" + }, { "class":"firrtl.transforms.BlackBoxResourceAnno", "target":"quasar_wrapper.dmi_wrapper", diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 2902eb56..86f0fd80 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -71689,32 +71689,32 @@ circuit quasar_wrapper : mitcnt1 <= UInt<1>("h00") wire mitcnt0 : UInt<32> mitcnt0 <= UInt<1>("h00") - node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2672:36] - node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2673:36] - io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2675:31] - io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2676:31] - node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2683:72] - node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2683:49] - node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2685:37] - node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2685:56] - node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2685:85] - node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2685:76] - node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2685:53] - node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2685:112] - node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2685:147] - node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2685:138] - node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2685:109] - node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2685:173] - node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2685:171] - node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2686:35] - node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2686:35] - node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2687:44] - node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2687:74] - node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2687:60] - node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2687:29] - node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2688:59] - node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2688:76] - node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2688:93] + node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2673:36] + node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2674:36] + io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2676:31] + io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2677:31] + node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2684:72] + node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2684:49] + node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2686:37] + node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2686:56] + node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2686:85] + node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2686:76] + node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2686:53] + node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2686:112] + node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2686:147] + node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2686:138] + node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2686:109] + node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2686:173] + node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2686:171] + node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2687:35] + node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2687:35] + node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2688:44] + node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2688:74] + node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2688:60] + node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2688:29] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2689:59] + node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2689:76] + node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2689:93] inst rvclkhdr of rvclkhdr_712 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -71723,34 +71723,34 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_18 <= mitcnt0_ns @[lib.scala 374:16] - mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2688:25] - node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2695:72] - node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2695:49] - node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2697:37] - node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2697:56] - node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2697:85] - node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2697:76] - node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2697:53] - node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2697:112] - node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2697:147] - node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2697:138] - node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2697:109] - node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2697:173] - node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2697:171] + mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2689:25] + node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2696:72] + node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2696:49] + node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2698:37] + node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2698:56] + node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2698:85] + node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2698:76] + node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2698:53] + node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2698:112] + node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2698:147] + node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2698:138] + node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2698:109] + node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2698:173] + node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2698:171] node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2700:68] - node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2700:60] - node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2700:72] + node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2701:68] + node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2701:60] + node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2701:72] node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58] - node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2700:35] - node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2700:35] - node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2701:45] - node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2701:75] - node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2701:61] - node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2701:30] - node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2702:60] - node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2702:77] - node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2702:94] + node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2701:35] + node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2701:35] + node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2702:45] + node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2702:75] + node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2702:61] + node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2702:30] + node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2703:60] + node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2703:77] + node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2703:94] inst rvclkhdr_1 of rvclkhdr_713 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -71759,11 +71759,11 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_42 <= mitcnt1_ns @[lib.scala 374:16] - mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2702:25] - node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2709:70] - node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2709:47] - node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2710:38] - node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2710:71] + mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2703:25] + node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2710:70] + node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2710:47] + node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2711:38] + node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2711:71] inst rvclkhdr_2 of rvclkhdr_714 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -71772,12 +71772,12 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mitb0_b <= _T_44 @[lib.scala 374:16] - node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2711:22] - mitb0 <= _T_46 @[dec_tlu_ctl.scala 2711:19] - node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2718:69] - node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2718:47] - node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2719:29] - node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2719:62] + node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2712:22] + mitb0 <= _T_46 @[dec_tlu_ctl.scala 2712:19] + node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2719:69] + node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2719:47] + node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2720:29] + node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2720:62] inst rvclkhdr_3 of rvclkhdr_715 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -71786,55 +71786,55 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mitb1_b <= _T_48 @[lib.scala 374:16] - node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2720:18] - mitb1 <= _T_50 @[dec_tlu_ctl.scala 2720:15] - node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2731:72] - node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2731:49] - node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2732:45] - node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2732:72] - node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2732:86] - node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2732:31] - node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2734:41] - node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2734:30] - reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2735:60] - mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2735:60] - node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2736:78] - reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2736:67] - _T_57 <= _T_56 @[dec_tlu_ctl.scala 2736:67] - node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2736:90] + node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2721:18] + mitb1 <= _T_50 @[dec_tlu_ctl.scala 2721:15] + node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2732:72] + node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2732:49] + node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2733:45] + node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2733:72] + node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2733:86] + node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2733:31] + node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2735:41] + node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2735:30] + reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2736:60] + mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2736:60] + node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2737:78] + reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2737:67] + _T_57 <= _T_56 @[dec_tlu_ctl.scala 2737:67] + node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2737:90] node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58] - mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2736:31] - node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2746:71] - node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2746:49] - node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2747:45] - node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2747:71] - node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2747:85] - node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2747:31] - node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2748:40] - node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2748:29] - reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2749:55] - mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2749:55] - node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2750:63] - reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2750:52] - _T_66 <= _T_65 @[dec_tlu_ctl.scala 2750:52] - node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2750:75] + mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2737:31] + node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2747:71] + node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2747:49] + node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2748:45] + node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2748:71] + node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2748:85] + node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2748:31] + node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2749:40] + node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2749:29] + reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2750:55] + mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2750:55] + node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2751:63] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2751:52] + _T_66 <= _T_65 @[dec_tlu_ctl.scala 2751:52] + node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2751:75] node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58] - mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2750:16] - node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2752:51] - node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2752:68] - node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2752:83] - node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2752:98] - node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2752:115] - io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2752:33] - node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2754:25] - node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2754:44] - node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2755:32] - node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2756:30] - node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2757:30] - node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2758:32] + mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2751:16] + node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2753:51] + node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2753:68] + node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2753:83] + node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2753:98] + node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2753:115] + io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2753:33] + node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2755:25] + node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2755:44] + node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2756:32] + node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2757:30] + node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2758:30] + node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2759:32] node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58] - node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2759:32] + node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2760:32] node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58] node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72] @@ -71850,7 +71850,7 @@ circuit quasar_wrapper : node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72] wire _T_96 : UInt<32> @[Mux.scala 27:72] _T_96 <= _T_95 @[Mux.scala 27:72] - io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2753:33] + io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2754:33] extmodule gated_latch_716 : output Q : Clock @@ -74026,621 +74026,621 @@ circuit quasar_wrapper : node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2126:100] node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2126:71] node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2128:34] - node _T_754 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2128:61] - node _T_755 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2128:91] - node _T_756 = mux(_T_753, _T_754, _T_755) @[dec_tlu_ctl.scala 2128:21] - node _T_757 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2130:78] - node _T_758 = bits(_T_757, 0, 0) @[dec_tlu_ctl.scala 2130:111] - reg _T_759 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_758 : @[Reg.scala 28:19] - _T_759 <= _T_756 @[Reg.scala 28:23] + node _T_754 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2128:86] + node _T_755 = mux(_T_753, io.dec_csr_wrdata_r, _T_754) @[dec_tlu_ctl.scala 2128:21] + node _T_756 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2131:78] + node _T_757 = bits(_T_756, 0, 0) @[dec_tlu_ctl.scala 2131:111] + reg _T_758 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_757 : @[Reg.scala 28:19] + _T_758 <= _T_755 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_748 <= _T_759 @[dec_tlu_ctl.scala 2130:13] - node _T_760 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] - dicad1 <= _T_760 @[dec_tlu_ctl.scala 2131:9] - node _T_761 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2153:69] - node _T_762 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2153:83] - node _T_763 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2153:97] - node _T_764 = cat(_T_761, _T_762) @[Cat.scala 29:58] - node _T_765 = cat(_T_764, _T_763) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_765 @[dec_tlu_ctl.scala 2153:56] - io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2156:41] - node _T_766 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2158:52] - node _T_767 = and(_T_766, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2158:75] - node _T_768 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2158:98] - node _T_769 = and(_T_767, _T_768) @[dec_tlu_ctl.scala 2158:96] - node _T_770 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2158:142] - node _T_771 = eq(_T_770, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2158:149] - node icache_rd_valid = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2158:120] - node _T_772 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2159:52] - node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2159:97] - node _T_774 = eq(_T_773, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:104] - node icache_wr_valid = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2159:75] - reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2161:58] - icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2161:58] - reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2162:58] - icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2162:58] - io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2164:41] - io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2165:41] - node _T_775 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2173:62] - node _T_776 = eq(_T_775, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2173:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_776) @[dec_tlu_ctl.scala 2173:40] - node _T_777 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2174:32] - node _T_778 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2174:59] - node mtsel_ns = mux(_T_777, _T_778, mtsel) @[dec_tlu_ctl.scala 2174:20] - reg _T_779 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2176:43] - _T_779 <= mtsel_ns @[dec_tlu_ctl.scala 2176:43] - mtsel <= _T_779 @[dec_tlu_ctl.scala 2176:8] - node _T_780 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2211:38] - node _T_781 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2211:64] - node _T_782 = not(_T_781) @[dec_tlu_ctl.scala 2211:44] - node tdata_load = and(_T_780, _T_782) @[dec_tlu_ctl.scala 2211:42] - node _T_783 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2213:40] - node _T_784 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:66] - node _T_785 = not(_T_784) @[dec_tlu_ctl.scala 2213:46] - node tdata_opcode = and(_T_783, _T_785) @[dec_tlu_ctl.scala 2213:44] - node _T_786 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2215:41] - node _T_787 = and(_T_786, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2215:46] - node _T_788 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2215:90] - node tdata_action = and(_T_787, _T_788) @[dec_tlu_ctl.scala 2215:69] - node _T_789 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:47] - node _T_790 = and(_T_789, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:52] - node _T_791 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2217:94] - node _T_792 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2217:136] - node _T_793 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2218:43] - node _T_794 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2218:83] - node _T_795 = cat(_T_794, tdata_load) @[Cat.scala 29:58] - node _T_796 = cat(_T_793, tdata_opcode) @[Cat.scala 29:58] - node _T_797 = cat(_T_796, _T_795) @[Cat.scala 29:58] - node _T_798 = cat(tdata_action, _T_792) @[Cat.scala 29:58] - node _T_799 = cat(_T_790, _T_791) @[Cat.scala 29:58] - node _T_800 = cat(_T_799, _T_798) @[Cat.scala 29:58] - node tdata_wrdata_r = cat(_T_800, _T_797) @[Cat.scala 29:58] - node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] - node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] - node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2221:70] - node _T_804 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2221:121] - node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2221:112] - node _T_806 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2221:154] - node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2221:138] - node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] - node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2221:135] - node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] - node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] - node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2221:70] - node _T_813 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2221:121] - node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2221:112] - node _T_815 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2221:154] - node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2221:138] - node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] - node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2221:135] - node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] - node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] - node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2221:70] - node _T_822 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2221:121] - node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2221:112] - node _T_824 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2221:154] - node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2221:138] - node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] - node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2221:135] - node _T_828 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2221:92] - node _T_829 = eq(_T_828, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2221:99] - node _T_830 = and(io.dec_csr_wen_r_mod, _T_829) @[dec_tlu_ctl.scala 2221:70] - node _T_831 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2221:121] - node _T_832 = and(_T_830, _T_831) @[dec_tlu_ctl.scala 2221:112] - node _T_833 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2221:154] - node _T_834 = not(_T_833) @[dec_tlu_ctl.scala 2221:138] - node _T_835 = or(_T_834, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:170] - node _T_836 = and(_T_832, _T_835) @[dec_tlu_ctl.scala 2221:135] - wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2221:42] - wr_mtdata1_t_r[0] <= _T_809 @[dec_tlu_ctl.scala 2221:42] - wr_mtdata1_t_r[1] <= _T_818 @[dec_tlu_ctl.scala 2221:42] - wr_mtdata1_t_r[2] <= _T_827 @[dec_tlu_ctl.scala 2221:42] - wr_mtdata1_t_r[3] <= _T_836 @[dec_tlu_ctl.scala 2221:42] - node _T_837 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2222:68] - node _T_838 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:111] - node _T_839 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2222:135] - node _T_840 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2222:156] - node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2222:139] - node _T_842 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2222:176] - node _T_843 = cat(_T_838, _T_841) @[Cat.scala 29:58] - node _T_844 = cat(_T_843, _T_842) @[Cat.scala 29:58] - node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2222:49] - node _T_846 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2222:68] - node _T_847 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:111] - node _T_848 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2222:135] - node _T_849 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2222:156] - node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2222:139] - node _T_851 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2222:176] - node _T_852 = cat(_T_847, _T_850) @[Cat.scala 29:58] - node _T_853 = cat(_T_852, _T_851) @[Cat.scala 29:58] - node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2222:49] - node _T_855 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2222:68] - node _T_856 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:111] - node _T_857 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2222:135] - node _T_858 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2222:156] - node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2222:139] - node _T_860 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2222:176] - node _T_861 = cat(_T_856, _T_859) @[Cat.scala 29:58] - node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58] - node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2222:49] - node _T_864 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2222:68] - node _T_865 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:111] - node _T_866 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2222:135] - node _T_867 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2222:156] - node _T_868 = or(_T_866, _T_867) @[dec_tlu_ctl.scala 2222:139] - node _T_869 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2222:176] - node _T_870 = cat(_T_865, _T_868) @[Cat.scala 29:58] - node _T_871 = cat(_T_870, _T_869) @[Cat.scala 29:58] - node _T_872 = mux(_T_864, tdata_wrdata_r, _T_871) @[dec_tlu_ctl.scala 2222:49] - wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2222:40] - mtdata1_t_ns[0] <= _T_845 @[dec_tlu_ctl.scala 2222:40] - mtdata1_t_ns[1] <= _T_854 @[dec_tlu_ctl.scala 2222:40] - mtdata1_t_ns[2] <= _T_863 @[dec_tlu_ctl.scala 2222:40] - mtdata1_t_ns[3] <= _T_872 @[dec_tlu_ctl.scala 2222:40] - reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] - _T_873 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2224:74] - io.mtdata1_t[0] <= _T_873 @[dec_tlu_ctl.scala 2224:39] - reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] - _T_874 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2224:74] - io.mtdata1_t[1] <= _T_874 @[dec_tlu_ctl.scala 2224:39] - reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] - _T_875 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2224:74] - io.mtdata1_t[2] <= _T_875 @[dec_tlu_ctl.scala 2224:39] - reg _T_876 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2224:74] - _T_876 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2224:74] - io.mtdata1_t[3] <= _T_876 @[dec_tlu_ctl.scala 2224:39] - node _T_877 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2227:58] - node _T_878 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2227:104] - node _T_879 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2227:142] - node _T_880 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2227:174] - node _T_881 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2227:206] - node _T_882 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2227:238] - node _T_883 = cat(UInt<3>("h00"), _T_882) @[Cat.scala 29:58] - node _T_884 = cat(_T_880, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_885 = cat(_T_884, _T_881) @[Cat.scala 29:58] - node _T_886 = cat(_T_885, _T_883) @[Cat.scala 29:58] - node _T_887 = cat(_T_879, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_888 = cat(UInt<4>("h02"), _T_878) @[Cat.scala 29:58] - node _T_889 = cat(_T_888, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_890 = cat(_T_889, _T_887) @[Cat.scala 29:58] - node _T_891 = cat(_T_890, _T_886) @[Cat.scala 29:58] - node _T_892 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2227:58] - node _T_893 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2227:104] - node _T_894 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2227:142] - node _T_895 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2227:174] - node _T_896 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2227:206] - node _T_897 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2227:238] - node _T_898 = cat(UInt<3>("h00"), _T_897) @[Cat.scala 29:58] - node _T_899 = cat(_T_895, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_900 = cat(_T_899, _T_896) @[Cat.scala 29:58] - node _T_901 = cat(_T_900, _T_898) @[Cat.scala 29:58] - node _T_902 = cat(_T_894, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_903 = cat(UInt<4>("h02"), _T_893) @[Cat.scala 29:58] - node _T_904 = cat(_T_903, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_905 = cat(_T_904, _T_902) @[Cat.scala 29:58] - node _T_906 = cat(_T_905, _T_901) @[Cat.scala 29:58] - node _T_907 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2227:58] - node _T_908 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2227:104] - node _T_909 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2227:142] - node _T_910 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2227:174] - node _T_911 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2227:206] - node _T_912 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2227:238] - node _T_913 = cat(UInt<3>("h00"), _T_912) @[Cat.scala 29:58] - node _T_914 = cat(_T_910, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_915 = cat(_T_914, _T_911) @[Cat.scala 29:58] - node _T_916 = cat(_T_915, _T_913) @[Cat.scala 29:58] - node _T_917 = cat(_T_909, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_918 = cat(UInt<4>("h02"), _T_908) @[Cat.scala 29:58] - node _T_919 = cat(_T_918, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_920 = cat(_T_919, _T_917) @[Cat.scala 29:58] - node _T_921 = cat(_T_920, _T_916) @[Cat.scala 29:58] - node _T_922 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2227:58] - node _T_923 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2227:104] - node _T_924 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2227:142] - node _T_925 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2227:174] - node _T_926 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2227:206] - node _T_927 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2227:238] - node _T_928 = cat(UInt<3>("h00"), _T_927) @[Cat.scala 29:58] - node _T_929 = cat(_T_925, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_930 = cat(_T_929, _T_926) @[Cat.scala 29:58] - node _T_931 = cat(_T_930, _T_928) @[Cat.scala 29:58] - node _T_932 = cat(_T_924, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_933 = cat(UInt<4>("h02"), _T_923) @[Cat.scala 29:58] - node _T_934 = cat(_T_933, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_935 = cat(_T_934, _T_932) @[Cat.scala 29:58] - node _T_936 = cat(_T_935, _T_931) @[Cat.scala 29:58] - node _T_937 = mux(_T_877, _T_891, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_938 = mux(_T_892, _T_906, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_939 = mux(_T_907, _T_921, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_940 = mux(_T_922, _T_936, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_941 = or(_T_937, _T_938) @[Mux.scala 27:72] + _T_748 <= _T_758 @[dec_tlu_ctl.scala 2131:13] + node _T_759 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] + dicad1 <= _T_759 @[dec_tlu_ctl.scala 2132:9] + node _T_760 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2154:69] + node _T_761 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2154:83] + node _T_762 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2154:97] + node _T_763 = cat(_T_760, _T_761) @[Cat.scala 29:58] + node _T_764 = cat(_T_763, _T_762) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_764 @[dec_tlu_ctl.scala 2154:56] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2157:41] + node _T_765 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2159:52] + node _T_766 = and(_T_765, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2159:75] + node _T_767 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2159:98] + node _T_768 = and(_T_766, _T_767) @[dec_tlu_ctl.scala 2159:96] + node _T_769 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2159:142] + node _T_770 = eq(_T_769, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:149] + node icache_rd_valid = and(_T_768, _T_770) @[dec_tlu_ctl.scala 2159:120] + node _T_771 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2160:52] + node _T_772 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2160:97] + node _T_773 = eq(_T_772, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:104] + node icache_wr_valid = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2160:75] + reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2162:58] + icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2162:58] + reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2163:58] + icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2163:58] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2165:41] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2166:41] + node _T_774 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2174:62] + node _T_775 = eq(_T_774, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2174:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_775) @[dec_tlu_ctl.scala 2174:40] + node _T_776 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2175:32] + node _T_777 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2175:59] + node mtsel_ns = mux(_T_776, _T_777, mtsel) @[dec_tlu_ctl.scala 2175:20] + reg _T_778 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2177:43] + _T_778 <= mtsel_ns @[dec_tlu_ctl.scala 2177:43] + mtsel <= _T_778 @[dec_tlu_ctl.scala 2177:8] + node _T_779 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2212:38] + node _T_780 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2212:64] + node _T_781 = not(_T_780) @[dec_tlu_ctl.scala 2212:44] + node tdata_load = and(_T_779, _T_781) @[dec_tlu_ctl.scala 2212:42] + node _T_782 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2214:40] + node _T_783 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2214:66] + node _T_784 = not(_T_783) @[dec_tlu_ctl.scala 2214:46] + node tdata_opcode = and(_T_782, _T_784) @[dec_tlu_ctl.scala 2214:44] + node _T_785 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2216:41] + node _T_786 = and(_T_785, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2216:46] + node _T_787 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2216:90] + node tdata_action = and(_T_786, _T_787) @[dec_tlu_ctl.scala 2216:69] + node _T_788 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2218:47] + node _T_789 = and(_T_788, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:52] + node _T_790 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2218:94] + node _T_791 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2218:136] + node _T_792 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2219:43] + node _T_793 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2219:83] + node _T_794 = cat(_T_793, tdata_load) @[Cat.scala 29:58] + node _T_795 = cat(_T_792, tdata_opcode) @[Cat.scala 29:58] + node _T_796 = cat(_T_795, _T_794) @[Cat.scala 29:58] + node _T_797 = cat(tdata_action, _T_791) @[Cat.scala 29:58] + node _T_798 = cat(_T_789, _T_790) @[Cat.scala 29:58] + node _T_799 = cat(_T_798, _T_797) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_799, _T_796) @[Cat.scala 29:58] + node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2222:70] + node _T_803 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2222:121] + node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2222:112] + node _T_805 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2222:138] + node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2222:135] + node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2222:70] + node _T_812 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2222:121] + node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2222:112] + node _T_814 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2222:138] + node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2222:135] + node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2222:70] + node _T_821 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2222:121] + node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2222:112] + node _T_823 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2222:138] + node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2222:135] + node _T_827 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_828 = eq(_T_827, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_829 = and(io.dec_csr_wen_r_mod, _T_828) @[dec_tlu_ctl.scala 2222:70] + node _T_830 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2222:121] + node _T_831 = and(_T_829, _T_830) @[dec_tlu_ctl.scala 2222:112] + node _T_832 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_833 = not(_T_832) @[dec_tlu_ctl.scala 2222:138] + node _T_834 = or(_T_833, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_835 = and(_T_831, _T_834) @[dec_tlu_ctl.scala 2222:135] + wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[0] <= _T_808 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[1] <= _T_817 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[2] <= _T_826 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[3] <= _T_835 @[dec_tlu_ctl.scala 2222:42] + node _T_836 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_837 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_838 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2223:135] + node _T_839 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2223:139] + node _T_841 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58] + node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58] + node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2223:49] + node _T_845 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_846 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_847 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2223:135] + node _T_848 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2223:139] + node _T_850 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58] + node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58] + node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2223:49] + node _T_854 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_855 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_856 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2223:135] + node _T_857 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2223:139] + node _T_859 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58] + node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58] + node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2223:49] + node _T_863 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_864 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_865 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2223:135] + node _T_866 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_867 = or(_T_865, _T_866) @[dec_tlu_ctl.scala 2223:139] + node _T_868 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_869 = cat(_T_864, _T_867) @[Cat.scala 29:58] + node _T_870 = cat(_T_869, _T_868) @[Cat.scala 29:58] + node _T_871 = mux(_T_863, tdata_wrdata_r, _T_870) @[dec_tlu_ctl.scala 2223:49] + wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[0] <= _T_844 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[1] <= _T_853 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[2] <= _T_862 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[3] <= _T_871 @[dec_tlu_ctl.scala 2223:40] + reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_872 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[0] <= _T_872 @[dec_tlu_ctl.scala 2225:39] + reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_873 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[1] <= _T_873 @[dec_tlu_ctl.scala 2225:39] + reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_874 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[2] <= _T_874 @[dec_tlu_ctl.scala 2225:39] + reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_875 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[3] <= _T_875 @[dec_tlu_ctl.scala 2225:39] + node _T_876 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2228:58] + node _T_877 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_878 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_879 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_880 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_881 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_882 = cat(UInt<3>("h00"), _T_881) @[Cat.scala 29:58] + node _T_883 = cat(_T_879, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_884 = cat(_T_883, _T_880) @[Cat.scala 29:58] + node _T_885 = cat(_T_884, _T_882) @[Cat.scala 29:58] + node _T_886 = cat(_T_878, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_887 = cat(UInt<4>("h02"), _T_877) @[Cat.scala 29:58] + node _T_888 = cat(_T_887, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_886) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_885) @[Cat.scala 29:58] + node _T_891 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2228:58] + node _T_892 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_893 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_894 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_895 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_896 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_897 = cat(UInt<3>("h00"), _T_896) @[Cat.scala 29:58] + node _T_898 = cat(_T_894, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_899 = cat(_T_898, _T_895) @[Cat.scala 29:58] + node _T_900 = cat(_T_899, _T_897) @[Cat.scala 29:58] + node _T_901 = cat(_T_893, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_902 = cat(UInt<4>("h02"), _T_892) @[Cat.scala 29:58] + node _T_903 = cat(_T_902, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_901) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_900) @[Cat.scala 29:58] + node _T_906 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2228:58] + node _T_907 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_908 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_909 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_910 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_911 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_912 = cat(UInt<3>("h00"), _T_911) @[Cat.scala 29:58] + node _T_913 = cat(_T_909, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_914 = cat(_T_913, _T_910) @[Cat.scala 29:58] + node _T_915 = cat(_T_914, _T_912) @[Cat.scala 29:58] + node _T_916 = cat(_T_908, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_917 = cat(UInt<4>("h02"), _T_907) @[Cat.scala 29:58] + node _T_918 = cat(_T_917, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, _T_916) @[Cat.scala 29:58] + node _T_920 = cat(_T_919, _T_915) @[Cat.scala 29:58] + node _T_921 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2228:58] + node _T_922 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_923 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_924 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_925 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_926 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_927 = cat(UInt<3>("h00"), _T_926) @[Cat.scala 29:58] + node _T_928 = cat(_T_924, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_929 = cat(_T_928, _T_925) @[Cat.scala 29:58] + node _T_930 = cat(_T_929, _T_927) @[Cat.scala 29:58] + node _T_931 = cat(_T_923, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_932 = cat(UInt<4>("h02"), _T_922) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] + node _T_935 = cat(_T_934, _T_930) @[Cat.scala 29:58] + node _T_936 = mux(_T_876, _T_890, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_937 = mux(_T_891, _T_905, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_906, _T_920, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = mux(_T_921, _T_935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_940 = or(_T_936, _T_937) @[Mux.scala 27:72] + node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72] - node _T_943 = or(_T_942, _T_940) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata1_tsel_out <= _T_943 @[Mux.scala 27:72] - node _T_944 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2229:58] - io.trigger_pkt_any[0].select <= _T_944 @[dec_tlu_ctl.scala 2229:40] - node _T_945 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2230:61] - io.trigger_pkt_any[0].match_pkt <= _T_945 @[dec_tlu_ctl.scala 2230:43] - node _T_946 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[0].store <= _T_946 @[dec_tlu_ctl.scala 2231:40] - node _T_947 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[0].load <= _T_947 @[dec_tlu_ctl.scala 2232:40] - node _T_948 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[0].execute <= _T_948 @[dec_tlu_ctl.scala 2233:40] - node _T_949 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[0].m <= _T_949 @[dec_tlu_ctl.scala 2234:40] - node _T_950 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2229:58] - io.trigger_pkt_any[1].select <= _T_950 @[dec_tlu_ctl.scala 2229:40] - node _T_951 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2230:61] - io.trigger_pkt_any[1].match_pkt <= _T_951 @[dec_tlu_ctl.scala 2230:43] - node _T_952 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[1].store <= _T_952 @[dec_tlu_ctl.scala 2231:40] - node _T_953 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[1].load <= _T_953 @[dec_tlu_ctl.scala 2232:40] - node _T_954 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[1].execute <= _T_954 @[dec_tlu_ctl.scala 2233:40] - node _T_955 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[1].m <= _T_955 @[dec_tlu_ctl.scala 2234:40] - node _T_956 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2229:58] - io.trigger_pkt_any[2].select <= _T_956 @[dec_tlu_ctl.scala 2229:40] - node _T_957 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2230:61] - io.trigger_pkt_any[2].match_pkt <= _T_957 @[dec_tlu_ctl.scala 2230:43] - node _T_958 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[2].store <= _T_958 @[dec_tlu_ctl.scala 2231:40] - node _T_959 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[2].load <= _T_959 @[dec_tlu_ctl.scala 2232:40] - node _T_960 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[2].execute <= _T_960 @[dec_tlu_ctl.scala 2233:40] - node _T_961 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[2].m <= _T_961 @[dec_tlu_ctl.scala 2234:40] - node _T_962 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2229:58] - io.trigger_pkt_any[3].select <= _T_962 @[dec_tlu_ctl.scala 2229:40] - node _T_963 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2230:61] - io.trigger_pkt_any[3].match_pkt <= _T_963 @[dec_tlu_ctl.scala 2230:43] - node _T_964 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2231:58] - io.trigger_pkt_any[3].store <= _T_964 @[dec_tlu_ctl.scala 2231:40] - node _T_965 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[3].load <= _T_965 @[dec_tlu_ctl.scala 2232:40] - node _T_966 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[3].execute <= _T_966 @[dec_tlu_ctl.scala 2233:40] - node _T_967 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[3].m <= _T_967 @[dec_tlu_ctl.scala 2234:40] - node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] - node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] - node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2241:69] - node _T_971 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2241:120] - node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2241:111] - node _T_973 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2241:153] - node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2241:137] - node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] - node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2241:134] - node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] - node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] - node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2241:69] - node _T_980 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2241:120] - node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2241:111] - node _T_982 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2241:153] - node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2241:137] - node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] - node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2241:134] - node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] - node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] - node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2241:69] - node _T_989 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2241:120] - node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2241:111] - node _T_991 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2241:153] - node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2241:137] - node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] - node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2241:134] - node _T_995 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2241:91] - node _T_996 = eq(_T_995, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2241:98] - node _T_997 = and(io.dec_csr_wen_r_mod, _T_996) @[dec_tlu_ctl.scala 2241:69] - node _T_998 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2241:120] - node _T_999 = and(_T_997, _T_998) @[dec_tlu_ctl.scala 2241:111] - node _T_1000 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2241:153] - node _T_1001 = not(_T_1000) @[dec_tlu_ctl.scala 2241:137] - node _T_1002 = or(_T_1001, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2241:169] - node _T_1003 = and(_T_999, _T_1002) @[dec_tlu_ctl.scala 2241:134] - wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2241:42] - wr_mtdata2_t_r[0] <= _T_976 @[dec_tlu_ctl.scala 2241:42] - wr_mtdata2_t_r[1] <= _T_985 @[dec_tlu_ctl.scala 2241:42] - wr_mtdata2_t_r[2] <= _T_994 @[dec_tlu_ctl.scala 2241:42] - wr_mtdata2_t_r[3] <= _T_1003 @[dec_tlu_ctl.scala 2241:42] - node _T_1004 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2242:84] + mtdata1_tsel_out <= _T_942 @[Mux.scala 27:72] + node _T_943 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[0].select <= _T_943 @[dec_tlu_ctl.scala 2230:40] + node _T_944 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[0].match_pkt <= _T_944 @[dec_tlu_ctl.scala 2231:43] + node _T_945 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[0].store <= _T_945 @[dec_tlu_ctl.scala 2232:40] + node _T_946 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[0].load <= _T_946 @[dec_tlu_ctl.scala 2233:40] + node _T_947 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[0].execute <= _T_947 @[dec_tlu_ctl.scala 2234:40] + node _T_948 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[0].m <= _T_948 @[dec_tlu_ctl.scala 2235:40] + node _T_949 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[1].select <= _T_949 @[dec_tlu_ctl.scala 2230:40] + node _T_950 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[1].match_pkt <= _T_950 @[dec_tlu_ctl.scala 2231:43] + node _T_951 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[1].store <= _T_951 @[dec_tlu_ctl.scala 2232:40] + node _T_952 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[1].load <= _T_952 @[dec_tlu_ctl.scala 2233:40] + node _T_953 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[1].execute <= _T_953 @[dec_tlu_ctl.scala 2234:40] + node _T_954 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[1].m <= _T_954 @[dec_tlu_ctl.scala 2235:40] + node _T_955 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[2].select <= _T_955 @[dec_tlu_ctl.scala 2230:40] + node _T_956 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[2].match_pkt <= _T_956 @[dec_tlu_ctl.scala 2231:43] + node _T_957 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[2].store <= _T_957 @[dec_tlu_ctl.scala 2232:40] + node _T_958 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[2].load <= _T_958 @[dec_tlu_ctl.scala 2233:40] + node _T_959 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[2].execute <= _T_959 @[dec_tlu_ctl.scala 2234:40] + node _T_960 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[2].m <= _T_960 @[dec_tlu_ctl.scala 2235:40] + node _T_961 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[3].select <= _T_961 @[dec_tlu_ctl.scala 2230:40] + node _T_962 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[3].match_pkt <= _T_962 @[dec_tlu_ctl.scala 2231:43] + node _T_963 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[3].store <= _T_963 @[dec_tlu_ctl.scala 2232:40] + node _T_964 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[3].load <= _T_964 @[dec_tlu_ctl.scala 2233:40] + node _T_965 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[3].execute <= _T_965 @[dec_tlu_ctl.scala 2234:40] + node _T_966 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[3].m <= _T_966 @[dec_tlu_ctl.scala 2235:40] + node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2242:69] + node _T_970 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2242:120] + node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2242:111] + node _T_972 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2242:137] + node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2242:134] + node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2242:69] + node _T_979 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2242:120] + node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2242:111] + node _T_981 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2242:137] + node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2242:134] + node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2242:69] + node _T_988 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2242:120] + node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2242:111] + node _T_990 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2242:137] + node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2242:134] + node _T_994 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_995 = eq(_T_994, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_996 = and(io.dec_csr_wen_r_mod, _T_995) @[dec_tlu_ctl.scala 2242:69] + node _T_997 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2242:120] + node _T_998 = and(_T_996, _T_997) @[dec_tlu_ctl.scala 2242:111] + node _T_999 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_1000 = not(_T_999) @[dec_tlu_ctl.scala 2242:137] + node _T_1001 = or(_T_1000, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_1002 = and(_T_998, _T_1001) @[dec_tlu_ctl.scala 2242:134] + wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[0] <= _T_975 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[1] <= _T_984 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[2] <= _T_993 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[3] <= _T_1002 @[dec_tlu_ctl.scala 2242:42] + node _T_1003 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_22.io.en <= _T_1004 @[lib.scala 371:17] + rvclkhdr_22.io.en <= _T_1003 @[lib.scala 371:17] rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1005 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1005 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[0] <= _T_1005 @[dec_tlu_ctl.scala 2242:36] - node _T_1006 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2242:84] + reg _T_1004 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1004 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[0] <= _T_1004 @[dec_tlu_ctl.scala 2243:36] + node _T_1005 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_23.io.en <= _T_1006 @[lib.scala 371:17] + rvclkhdr_23.io.en <= _T_1005 @[lib.scala 371:17] rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1007 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1007 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[1] <= _T_1007 @[dec_tlu_ctl.scala 2242:36] - node _T_1008 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2242:84] + reg _T_1006 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1006 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[1] <= _T_1006 @[dec_tlu_ctl.scala 2243:36] + node _T_1007 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_24.io.en <= _T_1008 @[lib.scala 371:17] + rvclkhdr_24.io.en <= _T_1007 @[lib.scala 371:17] rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1009 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1009 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[2] <= _T_1009 @[dec_tlu_ctl.scala 2242:36] - node _T_1010 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2242:84] + reg _T_1008 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1008 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[2] <= _T_1008 @[dec_tlu_ctl.scala 2243:36] + node _T_1009 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_25.io.en <= _T_1010 @[lib.scala 371:17] + rvclkhdr_25.io.en <= _T_1009 @[lib.scala 371:17] rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1011 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1011 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[3] <= _T_1011 @[dec_tlu_ctl.scala 2242:36] - node _T_1012 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2246:57] - node _T_1013 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2246:57] - node _T_1014 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2246:57] - node _T_1015 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2246:57] - node _T_1016 = mux(_T_1012, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1017 = mux(_T_1013, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1018 = mux(_T_1014, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1019 = mux(_T_1015, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1020 = or(_T_1016, _T_1017) @[Mux.scala 27:72] + reg _T_1010 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1010 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[3] <= _T_1010 @[dec_tlu_ctl.scala 2243:36] + node _T_1011 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2247:57] + node _T_1012 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2247:57] + node _T_1013 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2247:57] + node _T_1014 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2247:57] + node _T_1015 = mux(_T_1011, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1016 = mux(_T_1012, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1017 = mux(_T_1013, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1018 = mux(_T_1014, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1019 = or(_T_1015, _T_1016) @[Mux.scala 27:72] + node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72] - node _T_1022 = or(_T_1021, _T_1019) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata2_tsel_out <= _T_1022 @[Mux.scala 27:72] - io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2247:51] - io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2247:51] - io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2247:51] - io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2247:51] - mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2257:15] - mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2258:15] - mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2259:15] - mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2260:15] - node _T_1023 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] - node _T_1024 = mux(_T_1023, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1024) @[dec_tlu_ctl.scala 2266:59] - wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2267:24] - wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2268:27] - node _T_1025 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2272:38] - node _T_1026 = not(_T_1025) @[dec_tlu_ctl.scala 2272:24] - node _T_1027 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] - node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2273:62] - node _T_1029 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] - node _T_1030 = bits(_T_1029, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1031 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] - node _T_1032 = bits(_T_1031, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1033 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] - node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] - node _T_1036 = and(io.tlu_i0_commit_cmt, _T_1035) @[dec_tlu_ctl.scala 2276:94] - node _T_1037 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] - node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1039 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] - node _T_1040 = and(io.tlu_i0_commit_cmt, _T_1039) @[dec_tlu_ctl.scala 2277:94] - node _T_1041 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] - node _T_1042 = and(_T_1040, _T_1041) @[dec_tlu_ctl.scala 2277:115] - node _T_1043 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] - node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1045 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] - node _T_1046 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1047 = and(_T_1045, _T_1046) @[dec_tlu_ctl.scala 2278:115] - node _T_1048 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] - node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1050 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] - node _T_1051 = bits(_T_1050, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1052 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] - node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1054 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] - node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] - node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] - node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1059 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] - node _T_1060 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] - node _T_1061 = bits(_T_1060, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1062 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] - node _T_1063 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] - node _T_1064 = bits(_T_1063, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1065 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] - node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] - node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1069 = and(_T_1068, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] - node _T_1070 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] - node _T_1074 = and(_T_1072, _T_1073) @[dec_tlu_ctl.scala 2287:101] - node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] - node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2288:59] - node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] - node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] - node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] - node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] - node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] - node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] - node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] - node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] - node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] - node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] - node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] - node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] - node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] - node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] - node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] - node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] - node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] - node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] - node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] - node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] - node _T_1106 = or(_T_1104, _T_1105) @[dec_tlu_ctl.scala 2297:101] - node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] - node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] - node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] - node _T_1111 = bits(_T_1110, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] - node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] - node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] - node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] - node _T_1117 = bits(_T_1116, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] - node _T_1119 = bits(_T_1118, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] - node _T_1121 = bits(_T_1120, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] - node _T_1123 = bits(_T_1122, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] - node _T_1125 = bits(_T_1124, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] - node _T_1127 = bits(_T_1126, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] - node _T_1129 = bits(_T_1128, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] - node _T_1131 = bits(_T_1130, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] - node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] - node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] - node _T_1135 = bits(_T_1134, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] - node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] - node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] - node _T_1139 = bits(_T_1138, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] - node _T_1141 = bits(_T_1140, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] - node _T_1143 = bits(_T_1142, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] - node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] - node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] - node _T_1147 = bits(_T_1146, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] - node _T_1149 = bits(_T_1148, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] - node _T_1151 = bits(_T_1150, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] - node _T_1153 = bits(_T_1152, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] - node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] - node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] - node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] - node _T_1161 = bits(_T_1160, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] - node _T_1163 = bits(_T_1162, 0, 0) @[dec_tlu_ctl.scala 2320:84] - node _T_1164 = not(_T_1163) @[dec_tlu_ctl.scala 2320:73] - node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] - node _T_1166 = bits(_T_1165, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1169 = not(_T_1168) @[dec_tlu_ctl.scala 2321:73] - node _T_1170 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] - node _T_1171 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] - node _T_1172 = and(_T_1170, _T_1171) @[dec_tlu_ctl.scala 2321:113] - node _T_1173 = orr(_T_1172) @[dec_tlu_ctl.scala 2321:125] - node _T_1174 = and(_T_1169, _T_1173) @[dec_tlu_ctl.scala 2321:98] - node _T_1175 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] - node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1177 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] - node _T_1178 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] - node _T_1179 = bits(_T_1178, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1180 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] - node _T_1181 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] - node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1183 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1184 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] - node _T_1185 = bits(_T_1184, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1186 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] - node _T_1187 = bits(_T_1186, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1188 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] - node _T_1189 = bits(_T_1188, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1190 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] - node _T_1191 = bits(_T_1190, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1192 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] - node _T_1193 = bits(_T_1192, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1194 = mux(_T_1028, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1196 = mux(_T_1032, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1197 = mux(_T_1034, _T_1036, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1198 = mux(_T_1038, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1199 = mux(_T_1044, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1200 = mux(_T_1049, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1201 = mux(_T_1051, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1202 = mux(_T_1053, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1203 = mux(_T_1055, _T_1056, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1204 = mux(_T_1058, _T_1059, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1205 = mux(_T_1061, _T_1062, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1206 = mux(_T_1064, _T_1065, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1207 = mux(_T_1067, _T_1069, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1208 = mux(_T_1071, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1209 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1210 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1211 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1212 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1213 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1214 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1215 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1216 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1217 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1218 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1219 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1220 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1221 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1222 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1223 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1224 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1225 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1226 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1227 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1228 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1229 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1230 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1231 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1232 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1233 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1234 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1235 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1236 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1237 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1238 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1239 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1240 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1241 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1242 = mux(_T_1166, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1243 = mux(_T_1176, _T_1177, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1244 = mux(_T_1179, _T_1180, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1245 = mux(_T_1182, _T_1183, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1246 = mux(_T_1185, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1247 = mux(_T_1187, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1248 = mux(_T_1189, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1249 = mux(_T_1191, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1250 = mux(_T_1193, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1251 = or(_T_1194, _T_1195) @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1021 @[Mux.scala 27:72] + io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2248:51] + io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2248:51] + io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2248:51] + io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2248:51] + mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2258:15] + mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2259:15] + mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2260:15] + mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2261:15] + node _T_1022 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1023 = mux(_T_1022, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1023) @[dec_tlu_ctl.scala 2267:59] + wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2268:24] + wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2269:27] + node _T_1024 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2273:38] + node _T_1025 = not(_T_1024) @[dec_tlu_ctl.scala 2273:24] + node _T_1026 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1028 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1030 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1031 = bits(_T_1030, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1032 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1034 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1035 = and(io.tlu_i0_commit_cmt, _T_1034) @[dec_tlu_ctl.scala 2277:94] + node _T_1036 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1037 = bits(_T_1036, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1038 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1039 = and(io.tlu_i0_commit_cmt, _T_1038) @[dec_tlu_ctl.scala 2278:94] + node _T_1040 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1041 = and(_T_1039, _T_1040) @[dec_tlu_ctl.scala 2278:115] + node _T_1042 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1044 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1045 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1046 = and(_T_1044, _T_1045) @[dec_tlu_ctl.scala 2279:115] + node _T_1047 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1049 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1051 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1053 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1058 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1062 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1063 = bits(_T_1062, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1064 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1068 = and(_T_1067, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1069 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1072 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2288:101] + node _T_1074 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1077 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1080 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1083 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1086 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1089 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1092 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1095 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1096 = bits(_T_1095, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1097 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1098 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1100 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1101 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1103 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1105 = or(_T_1103, _T_1104) @[dec_tlu_ctl.scala 2298:101] + node _T_1106 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1108 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1111 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1112 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1114 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1115 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1117 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1119 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1121 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1123 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1125 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1127 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1129 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1131 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1132 = or(_T_1131, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1133 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1135 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1136 = or(_T_1135, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1137 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1139 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1141 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1143 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1144 = and(_T_1143, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1149 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1151 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1153 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1155 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1157 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1159 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1160 = bits(_T_1159, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1161 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1162 = bits(_T_1161, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1163 = not(_T_1162) @[dec_tlu_ctl.scala 2321:73] + node _T_1164 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1166 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1168 = not(_T_1167) @[dec_tlu_ctl.scala 2322:73] + node _T_1169 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1170 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1171 = and(_T_1169, _T_1170) @[dec_tlu_ctl.scala 2322:113] + node _T_1172 = orr(_T_1171) @[dec_tlu_ctl.scala 2322:125] + node _T_1173 = and(_T_1168, _T_1172) @[dec_tlu_ctl.scala 2322:98] + node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1186 = bits(_T_1185, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1188 = bits(_T_1187, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1190 = bits(_T_1189, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1192 = bits(_T_1191, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1193 = mux(_T_1027, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1194 = mux(_T_1029, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1031, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1033, _T_1035, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1037, _T_1041, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1043, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1048, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1050, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1052, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1066, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1070, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1093, _T_1094, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1096, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1102, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1107, _T_1108, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1110, _T_1111, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1113, _T_1114, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1116, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1118, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1120, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1122, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1124, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1126, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1128, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1130, _T_1132, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1138, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1140, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1142, _T_1144, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1146, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1148, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1150, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1152, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1154, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1156, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1158, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1160, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1243 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1244 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1245 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1246 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1247 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1248 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1249 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1250 = or(_T_1193, _T_1194) @[Mux.scala 27:72] + node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72] node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72] node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72] node _T_1254 = or(_T_1253, _T_1198) @[Mux.scala 27:72] @@ -74695,238 +74695,238 @@ circuit quasar_wrapper : node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72] node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72] node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72] - node _T_1306 = or(_T_1305, _T_1250) @[Mux.scala 27:72] - wire _T_1307 : UInt<1> @[Mux.scala 27:72] - _T_1307 <= _T_1306 @[Mux.scala 27:72] - node _T_1308 = and(_T_1026, _T_1307) @[dec_tlu_ctl.scala 2272:44] - mhpmc_inc_r[0] <= _T_1308 @[dec_tlu_ctl.scala 2272:19] - node _T_1309 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2272:38] - node _T_1310 = not(_T_1309) @[dec_tlu_ctl.scala 2272:24] - node _T_1311 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] - node _T_1312 = bits(_T_1311, 0, 0) @[dec_tlu_ctl.scala 2273:62] - node _T_1313 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] - node _T_1314 = bits(_T_1313, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1315 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] - node _T_1316 = bits(_T_1315, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1317 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] - node _T_1318 = bits(_T_1317, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] - node _T_1320 = and(io.tlu_i0_commit_cmt, _T_1319) @[dec_tlu_ctl.scala 2276:94] - node _T_1321 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] - node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1323 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] - node _T_1324 = and(io.tlu_i0_commit_cmt, _T_1323) @[dec_tlu_ctl.scala 2277:94] - node _T_1325 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] - node _T_1326 = and(_T_1324, _T_1325) @[dec_tlu_ctl.scala 2277:115] - node _T_1327 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] - node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1329 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] - node _T_1330 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1331 = and(_T_1329, _T_1330) @[dec_tlu_ctl.scala 2278:115] - node _T_1332 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] - node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1334 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] - node _T_1335 = bits(_T_1334, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1336 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] - node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1338 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] - node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] - node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] - node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1343 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] - node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] - node _T_1345 = bits(_T_1344, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] - node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] - node _T_1348 = bits(_T_1347, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] - node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] - node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1353 = and(_T_1352, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] - node _T_1354 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1357 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] - node _T_1358 = and(_T_1356, _T_1357) @[dec_tlu_ctl.scala 2287:101] - node _T_1359 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] - node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2288:59] - node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] - node _T_1362 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] - node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] - node _T_1365 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] - node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] - node _T_1368 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] - node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] - node _T_1371 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] - node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] - node _T_1374 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] - node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] - node _T_1377 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] - node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] - node _T_1380 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] - node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1382 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] - node _T_1383 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] - node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1385 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] - node _T_1386 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] - node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] - node _T_1389 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] - node _T_1390 = or(_T_1388, _T_1389) @[dec_tlu_ctl.scala 2297:101] - node _T_1391 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] - node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1393 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] - node _T_1394 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] - node _T_1395 = bits(_T_1394, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1396 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] - node _T_1397 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] - node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1399 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] - node _T_1400 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] - node _T_1401 = bits(_T_1400, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1402 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] - node _T_1403 = bits(_T_1402, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1404 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] - node _T_1405 = bits(_T_1404, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1406 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] - node _T_1407 = bits(_T_1406, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1408 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] - node _T_1409 = bits(_T_1408, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1410 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] - node _T_1411 = bits(_T_1410, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1412 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] - node _T_1413 = bits(_T_1412, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1414 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] - node _T_1415 = bits(_T_1414, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1416 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] - node _T_1417 = or(_T_1416, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] - node _T_1418 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] - node _T_1419 = bits(_T_1418, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1420 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] - node _T_1421 = or(_T_1420, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] - node _T_1422 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] - node _T_1423 = bits(_T_1422, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1424 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] - node _T_1425 = bits(_T_1424, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1426 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] - node _T_1427 = bits(_T_1426, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1428 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] - node _T_1429 = and(_T_1428, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] - node _T_1430 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] - node _T_1431 = bits(_T_1430, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1432 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] - node _T_1433 = bits(_T_1432, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1434 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] - node _T_1435 = bits(_T_1434, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1436 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] - node _T_1437 = bits(_T_1436, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1438 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] - node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1440 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] - node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1442 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] - node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1444 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] - node _T_1445 = bits(_T_1444, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1446 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] - node _T_1447 = bits(_T_1446, 0, 0) @[dec_tlu_ctl.scala 2320:84] - node _T_1448 = not(_T_1447) @[dec_tlu_ctl.scala 2320:73] - node _T_1449 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] - node _T_1450 = bits(_T_1449, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1451 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1453 = not(_T_1452) @[dec_tlu_ctl.scala 2321:73] - node _T_1454 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] - node _T_1455 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] - node _T_1456 = and(_T_1454, _T_1455) @[dec_tlu_ctl.scala 2321:113] - node _T_1457 = orr(_T_1456) @[dec_tlu_ctl.scala 2321:125] - node _T_1458 = and(_T_1453, _T_1457) @[dec_tlu_ctl.scala 2321:98] - node _T_1459 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] - node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1461 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] - node _T_1462 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] - node _T_1463 = bits(_T_1462, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1464 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] - node _T_1465 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] - node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1467 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] - node _T_1469 = bits(_T_1468, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] - node _T_1471 = bits(_T_1470, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] - node _T_1473 = bits(_T_1472, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] - node _T_1475 = bits(_T_1474, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1476 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] - node _T_1477 = bits(_T_1476, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1478 = mux(_T_1312, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1479 = mux(_T_1314, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1480 = mux(_T_1316, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1481 = mux(_T_1318, _T_1320, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1482 = mux(_T_1322, _T_1326, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1483 = mux(_T_1328, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1484 = mux(_T_1333, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1485 = mux(_T_1335, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1486 = mux(_T_1337, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1487 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1488 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1489 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1490 = mux(_T_1348, _T_1349, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1491 = mux(_T_1351, _T_1353, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1492 = mux(_T_1355, _T_1358, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1493 = mux(_T_1360, _T_1361, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1494 = mux(_T_1363, _T_1364, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1495 = mux(_T_1366, _T_1367, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1496 = mux(_T_1369, _T_1370, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1497 = mux(_T_1372, _T_1373, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1498 = mux(_T_1375, _T_1376, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1499 = mux(_T_1378, _T_1379, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1500 = mux(_T_1381, _T_1382, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1501 = mux(_T_1384, _T_1385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1502 = mux(_T_1387, _T_1390, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1503 = mux(_T_1392, _T_1393, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1504 = mux(_T_1395, _T_1396, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1505 = mux(_T_1398, _T_1399, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1506 = mux(_T_1401, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1507 = mux(_T_1403, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1508 = mux(_T_1405, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1509 = mux(_T_1407, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1510 = mux(_T_1409, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1511 = mux(_T_1411, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1512 = mux(_T_1413, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1513 = mux(_T_1415, _T_1417, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1514 = mux(_T_1419, _T_1421, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1515 = mux(_T_1423, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1516 = mux(_T_1425, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1517 = mux(_T_1427, _T_1429, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1518 = mux(_T_1431, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1519 = mux(_T_1433, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1520 = mux(_T_1435, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1521 = mux(_T_1437, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1522 = mux(_T_1439, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1523 = mux(_T_1441, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1524 = mux(_T_1443, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1525 = mux(_T_1445, _T_1448, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1526 = mux(_T_1450, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1527 = mux(_T_1460, _T_1461, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1528 = mux(_T_1463, _T_1464, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1529 = mux(_T_1466, _T_1467, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1530 = mux(_T_1469, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1531 = mux(_T_1471, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1532 = mux(_T_1473, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1533 = mux(_T_1475, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1534 = mux(_T_1477, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1535 = or(_T_1478, _T_1479) @[Mux.scala 27:72] + wire _T_1306 : UInt<1> @[Mux.scala 27:72] + _T_1306 <= _T_1305 @[Mux.scala 27:72] + node _T_1307 = and(_T_1025, _T_1306) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[0] <= _T_1307 @[dec_tlu_ctl.scala 2273:19] + node _T_1308 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2273:38] + node _T_1309 = not(_T_1308) @[dec_tlu_ctl.scala 2273:24] + node _T_1310 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1312 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1314 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1315 = bits(_T_1314, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1316 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1318 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1319 = and(io.tlu_i0_commit_cmt, _T_1318) @[dec_tlu_ctl.scala 2277:94] + node _T_1320 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1321 = bits(_T_1320, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1322 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1323 = and(io.tlu_i0_commit_cmt, _T_1322) @[dec_tlu_ctl.scala 2278:94] + node _T_1324 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1325 = and(_T_1323, _T_1324) @[dec_tlu_ctl.scala 2278:115] + node _T_1326 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1328 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1329 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1330 = and(_T_1328, _T_1329) @[dec_tlu_ctl.scala 2279:115] + node _T_1331 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1333 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1335 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1337 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1342 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1346 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1347 = bits(_T_1346, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1348 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1352 = and(_T_1351, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1353 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1357 = and(_T_1355, _T_1356) @[dec_tlu_ctl.scala 2288:101] + node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1380 = bits(_T_1379, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1389 = or(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2298:101] + node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1444 = bits(_T_1443, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1446 = bits(_T_1445, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1447 = not(_T_1446) @[dec_tlu_ctl.scala 2321:73] + node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1452 = not(_T_1451) @[dec_tlu_ctl.scala 2322:73] + node _T_1453 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1454 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1455 = and(_T_1453, _T_1454) @[dec_tlu_ctl.scala 2322:113] + node _T_1456 = orr(_T_1455) @[dec_tlu_ctl.scala 2322:125] + node _T_1457 = and(_T_1452, _T_1456) @[dec_tlu_ctl.scala 2322:98] + node _T_1458 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1460 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1461 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1463 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1464 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1469 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1470 = bits(_T_1469, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1471 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1472 = bits(_T_1471, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1473 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1474 = bits(_T_1473, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1475 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1476 = bits(_T_1475, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1477 = mux(_T_1311, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1315, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1321, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1327, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1332, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1334, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1336, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1341, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1344, _T_1345, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1347, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1350, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1354, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1449, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1459, _T_1460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1462, _T_1463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1465, _T_1466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1468, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1470, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = mux(_T_1472, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1532 = mux(_T_1474, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1533 = mux(_T_1476, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1534 = or(_T_1477, _T_1478) @[Mux.scala 27:72] + node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72] node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72] node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72] node _T_1538 = or(_T_1537, _T_1482) @[Mux.scala 27:72] @@ -74981,238 +74981,238 @@ circuit quasar_wrapper : node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72] node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72] node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72] - node _T_1590 = or(_T_1589, _T_1534) @[Mux.scala 27:72] - wire _T_1591 : UInt<1> @[Mux.scala 27:72] - _T_1591 <= _T_1590 @[Mux.scala 27:72] - node _T_1592 = and(_T_1310, _T_1591) @[dec_tlu_ctl.scala 2272:44] - mhpmc_inc_r[1] <= _T_1592 @[dec_tlu_ctl.scala 2272:19] - node _T_1593 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2272:38] - node _T_1594 = not(_T_1593) @[dec_tlu_ctl.scala 2272:24] - node _T_1595 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] - node _T_1596 = bits(_T_1595, 0, 0) @[dec_tlu_ctl.scala 2273:62] - node _T_1597 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] - node _T_1598 = bits(_T_1597, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1599 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] - node _T_1600 = bits(_T_1599, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1601 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] - node _T_1602 = bits(_T_1601, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] - node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[dec_tlu_ctl.scala 2276:94] - node _T_1605 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] - node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1607 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] - node _T_1608 = and(io.tlu_i0_commit_cmt, _T_1607) @[dec_tlu_ctl.scala 2277:94] - node _T_1609 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] - node _T_1610 = and(_T_1608, _T_1609) @[dec_tlu_ctl.scala 2277:115] - node _T_1611 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] - node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1613 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] - node _T_1614 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1615 = and(_T_1613, _T_1614) @[dec_tlu_ctl.scala 2278:115] - node _T_1616 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] - node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1618 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] - node _T_1619 = bits(_T_1618, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1620 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] - node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1622 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] - node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] - node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] - node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1627 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] - node _T_1628 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] - node _T_1629 = bits(_T_1628, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1630 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] - node _T_1631 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] - node _T_1632 = bits(_T_1631, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1633 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] - node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] - node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1637 = and(_T_1636, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] - node _T_1638 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1641 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] - node _T_1642 = and(_T_1640, _T_1641) @[dec_tlu_ctl.scala 2287:101] - node _T_1643 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] - node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2288:59] - node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] - node _T_1646 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] - node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] - node _T_1649 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] - node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] - node _T_1652 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] - node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] - node _T_1655 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] - node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] - node _T_1658 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] - node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] - node _T_1661 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] - node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] - node _T_1664 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] - node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1666 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] - node _T_1667 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] - node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1669 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] - node _T_1670 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] - node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] - node _T_1673 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] - node _T_1674 = or(_T_1672, _T_1673) @[dec_tlu_ctl.scala 2297:101] - node _T_1675 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] - node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1677 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] - node _T_1678 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] - node _T_1679 = bits(_T_1678, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1680 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] - node _T_1681 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] - node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1683 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] - node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] - node _T_1685 = bits(_T_1684, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] - node _T_1687 = bits(_T_1686, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1688 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] - node _T_1689 = bits(_T_1688, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1690 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] - node _T_1691 = bits(_T_1690, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1692 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] - node _T_1693 = bits(_T_1692, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1694 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] - node _T_1695 = bits(_T_1694, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1696 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] - node _T_1697 = bits(_T_1696, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1698 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] - node _T_1699 = bits(_T_1698, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1700 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] - node _T_1701 = or(_T_1700, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] - node _T_1702 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] - node _T_1703 = bits(_T_1702, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1704 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] - node _T_1705 = or(_T_1704, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] - node _T_1706 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] - node _T_1707 = bits(_T_1706, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1708 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] - node _T_1709 = bits(_T_1708, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1710 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] - node _T_1711 = bits(_T_1710, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1712 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] - node _T_1713 = and(_T_1712, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] - node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] - node _T_1715 = bits(_T_1714, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] - node _T_1717 = bits(_T_1716, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] - node _T_1719 = bits(_T_1718, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] - node _T_1721 = bits(_T_1720, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] - node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1724 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] - node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1726 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] - node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1728 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] - node _T_1729 = bits(_T_1728, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1730 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] - node _T_1731 = bits(_T_1730, 0, 0) @[dec_tlu_ctl.scala 2320:84] - node _T_1732 = not(_T_1731) @[dec_tlu_ctl.scala 2320:73] - node _T_1733 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] - node _T_1734 = bits(_T_1733, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1735 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1737 = not(_T_1736) @[dec_tlu_ctl.scala 2321:73] - node _T_1738 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] - node _T_1739 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] - node _T_1740 = and(_T_1738, _T_1739) @[dec_tlu_ctl.scala 2321:113] - node _T_1741 = orr(_T_1740) @[dec_tlu_ctl.scala 2321:125] - node _T_1742 = and(_T_1737, _T_1741) @[dec_tlu_ctl.scala 2321:98] - node _T_1743 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] - node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1745 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] - node _T_1746 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] - node _T_1747 = bits(_T_1746, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] - node _T_1749 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] - node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1751 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1752 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] - node _T_1753 = bits(_T_1752, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1754 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] - node _T_1755 = bits(_T_1754, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1756 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] - node _T_1757 = bits(_T_1756, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1758 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] - node _T_1759 = bits(_T_1758, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1760 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] - node _T_1761 = bits(_T_1760, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1762 = mux(_T_1596, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1763 = mux(_T_1598, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1764 = mux(_T_1600, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1765 = mux(_T_1602, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1766 = mux(_T_1606, _T_1610, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1767 = mux(_T_1612, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1768 = mux(_T_1617, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1769 = mux(_T_1619, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1770 = mux(_T_1621, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1771 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1772 = mux(_T_1626, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1773 = mux(_T_1629, _T_1630, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1774 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1775 = mux(_T_1635, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1776 = mux(_T_1639, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1777 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1778 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1779 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1780 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1781 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1782 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1783 = mux(_T_1662, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1784 = mux(_T_1665, _T_1666, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1785 = mux(_T_1668, _T_1669, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1786 = mux(_T_1671, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1787 = mux(_T_1676, _T_1677, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1788 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1789 = mux(_T_1682, _T_1683, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1790 = mux(_T_1685, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1791 = mux(_T_1687, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1792 = mux(_T_1689, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1793 = mux(_T_1691, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1794 = mux(_T_1693, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1795 = mux(_T_1695, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1796 = mux(_T_1697, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1797 = mux(_T_1699, _T_1701, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1798 = mux(_T_1703, _T_1705, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1799 = mux(_T_1707, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1800 = mux(_T_1709, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1801 = mux(_T_1711, _T_1713, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1802 = mux(_T_1715, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1803 = mux(_T_1717, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1804 = mux(_T_1719, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1805 = mux(_T_1721, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1806 = mux(_T_1723, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1807 = mux(_T_1725, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1808 = mux(_T_1727, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1809 = mux(_T_1729, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1810 = mux(_T_1734, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1811 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1812 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1813 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1814 = mux(_T_1753, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1815 = mux(_T_1755, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1816 = mux(_T_1757, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1817 = mux(_T_1759, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1818 = mux(_T_1761, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1819 = or(_T_1762, _T_1763) @[Mux.scala 27:72] + wire _T_1590 : UInt<1> @[Mux.scala 27:72] + _T_1590 <= _T_1589 @[Mux.scala 27:72] + node _T_1591 = and(_T_1309, _T_1590) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[1] <= _T_1591 @[dec_tlu_ctl.scala 2273:19] + node _T_1592 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2273:38] + node _T_1593 = not(_T_1592) @[dec_tlu_ctl.scala 2273:24] + node _T_1594 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1596 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1598 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1599 = bits(_T_1598, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1600 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1602 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1603 = and(io.tlu_i0_commit_cmt, _T_1602) @[dec_tlu_ctl.scala 2277:94] + node _T_1604 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1605 = bits(_T_1604, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1606 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1607 = and(io.tlu_i0_commit_cmt, _T_1606) @[dec_tlu_ctl.scala 2278:94] + node _T_1608 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1609 = and(_T_1607, _T_1608) @[dec_tlu_ctl.scala 2278:115] + node _T_1610 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1612 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1613 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1614 = and(_T_1612, _T_1613) @[dec_tlu_ctl.scala 2279:115] + node _T_1615 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1617 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1619 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1621 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1626 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1631 = bits(_T_1630, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1636 = and(_T_1635, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1637 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1640 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1641 = and(_T_1639, _T_1640) @[dec_tlu_ctl.scala 2288:101] + node _T_1642 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1645 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1648 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1651 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1654 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1657 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1660 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1663 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1664 = bits(_T_1663, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1665 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1666 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1668 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1669 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1673 = or(_T_1671, _T_1672) @[dec_tlu_ctl.scala 2298:101] + node _T_1674 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1676 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1679 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1680 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1682 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1683 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1685 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1687 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1689 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1691 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1693 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1695 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1697 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1699 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1700 = or(_T_1699, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1701 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1703 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1704 = or(_T_1703, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1705 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1707 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1709 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1711 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1712 = and(_T_1711, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1717 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1719 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1721 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1723 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1725 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1727 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1728 = bits(_T_1727, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1729 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1730 = bits(_T_1729, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1731 = not(_T_1730) @[dec_tlu_ctl.scala 2321:73] + node _T_1732 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1734 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1736 = not(_T_1735) @[dec_tlu_ctl.scala 2322:73] + node _T_1737 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1738 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1739 = and(_T_1737, _T_1738) @[dec_tlu_ctl.scala 2322:113] + node _T_1740 = orr(_T_1739) @[dec_tlu_ctl.scala 2322:125] + node _T_1741 = and(_T_1736, _T_1740) @[dec_tlu_ctl.scala 2322:98] + node _T_1742 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1744 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1745 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1747 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1748 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1750 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1754 = bits(_T_1753, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1756 = bits(_T_1755, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1758 = bits(_T_1757, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1759 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1760 = bits(_T_1759, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1761 = mux(_T_1595, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = mux(_T_1597, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1599, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1601, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1605, _T_1609, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1611, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1616, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1618, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1620, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1631, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1634, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1638, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1664, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1670, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1678, _T_1679, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1681, _T_1682, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1684, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1686, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1688, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1690, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1692, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1694, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1696, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1698, _T_1700, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1706, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1708, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1710, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1714, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1716, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1718, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1720, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1722, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1724, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1726, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1728, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1733, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1811 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1812 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1813 = mux(_T_1752, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1814 = mux(_T_1754, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1815 = mux(_T_1756, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1816 = mux(_T_1758, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1817 = mux(_T_1760, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1818 = or(_T_1761, _T_1762) @[Mux.scala 27:72] + node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72] node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72] node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72] node _T_1822 = or(_T_1821, _T_1766) @[Mux.scala 27:72] @@ -75267,238 +75267,238 @@ circuit quasar_wrapper : node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72] node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72] node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72] - node _T_1874 = or(_T_1873, _T_1818) @[Mux.scala 27:72] - wire _T_1875 : UInt<1> @[Mux.scala 27:72] - _T_1875 <= _T_1874 @[Mux.scala 27:72] - node _T_1876 = and(_T_1594, _T_1875) @[dec_tlu_ctl.scala 2272:44] - mhpmc_inc_r[2] <= _T_1876 @[dec_tlu_ctl.scala 2272:19] - node _T_1877 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2272:38] - node _T_1878 = not(_T_1877) @[dec_tlu_ctl.scala 2272:24] - node _T_1879 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2273:34] - node _T_1880 = bits(_T_1879, 0, 0) @[dec_tlu_ctl.scala 2273:62] - node _T_1881 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2274:34] - node _T_1882 = bits(_T_1881, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1883 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2275:34] - node _T_1884 = bits(_T_1883, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1885 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2276:34] - node _T_1886 = bits(_T_1885, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2276:96] - node _T_1888 = and(io.tlu_i0_commit_cmt, _T_1887) @[dec_tlu_ctl.scala 2276:94] - node _T_1889 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2277:34] - node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1891 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2277:96] - node _T_1892 = and(io.tlu_i0_commit_cmt, _T_1891) @[dec_tlu_ctl.scala 2277:94] - node _T_1893 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:117] - node _T_1894 = and(_T_1892, _T_1893) @[dec_tlu_ctl.scala 2277:115] - node _T_1895 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2278:34] - node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1897 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:94] - node _T_1898 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1899 = and(_T_1897, _T_1898) @[dec_tlu_ctl.scala 2278:115] - node _T_1900 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2279:34] - node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1902 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2280:34] - node _T_1903 = bits(_T_1902, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1904 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2281:34] - node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1906 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2282:34] - node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2282:91] - node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2283:34] - node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1911 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2283:105] - node _T_1912 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2284:34] - node _T_1913 = bits(_T_1912, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1914 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2284:91] - node _T_1915 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2285:34] - node _T_1916 = bits(_T_1915, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1917 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2285:91] - node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2286:34] - node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] - node _T_1921 = and(_T_1920, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2286:100] - node _T_1922 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] - node _T_1925 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2287:142] - node _T_1926 = and(_T_1924, _T_1925) @[dec_tlu_ctl.scala 2287:101] - node _T_1927 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2288:34] - node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2288:59] - node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2288:89] - node _T_1930 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2289:34] - node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2289:89] - node _T_1933 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2290:34] - node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2290:89] - node _T_1936 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2291:34] - node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2291:89] - node _T_1939 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2292:34] - node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2292:89] - node _T_1942 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2293:34] - node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2293:89] - node _T_1945 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2294:34] - node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2294:89] - node _T_1948 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2295:34] - node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2295:89] - node _T_1951 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2296:34] - node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2296:89] - node _T_1954 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2297:34] - node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2297:89] - node _T_1957 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2297:122] - node _T_1958 = or(_T_1956, _T_1957) @[dec_tlu_ctl.scala 2297:101] - node _T_1959 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2298:34] - node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2298:62] - node _T_1961 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2298:95] - node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2299:34] - node _T_1963 = bits(_T_1962, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1964 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:97] - node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2300:34] - node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1967 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:110] - node _T_1968 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2301:34] - node _T_1969 = bits(_T_1968, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1970 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2302:34] - node _T_1971 = bits(_T_1970, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1972 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2303:34] - node _T_1973 = bits(_T_1972, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1974 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2304:34] - node _T_1975 = bits(_T_1974, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1976 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2305:34] - node _T_1977 = bits(_T_1976, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1978 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2306:34] - node _T_1979 = bits(_T_1978, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1980 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2307:34] - node _T_1981 = bits(_T_1980, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1982 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2308:34] - node _T_1983 = bits(_T_1982, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1984 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2308:98] - node _T_1985 = or(_T_1984, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2308:120] - node _T_1986 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2309:34] - node _T_1987 = bits(_T_1986, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1988 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2309:92] - node _T_1989 = or(_T_1988, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2309:117] - node _T_1990 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2310:34] - node _T_1991 = bits(_T_1990, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1992 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2311:34] - node _T_1993 = bits(_T_1992, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1994 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2312:34] - node _T_1995 = bits(_T_1994, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1996 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2312:97] - node _T_1997 = and(_T_1996, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2312:129] - node _T_1998 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2313:34] - node _T_1999 = bits(_T_1998, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_2000 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2314:34] - node _T_2001 = bits(_T_2000, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_2002 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2315:34] - node _T_2003 = bits(_T_2002, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_2004 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2316:34] - node _T_2005 = bits(_T_2004, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_2006 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2317:34] - node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_2008 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2318:34] - node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_2010 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2319:34] - node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_2012 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2320:34] - node _T_2013 = bits(_T_2012, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_2014 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2320:84] - node _T_2015 = bits(_T_2014, 0, 0) @[dec_tlu_ctl.scala 2320:84] - node _T_2016 = not(_T_2015) @[dec_tlu_ctl.scala 2320:73] - node _T_2017 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2321:34] - node _T_2018 = bits(_T_2017, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_2019 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_2021 = not(_T_2020) @[dec_tlu_ctl.scala 2321:73] - node _T_2022 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2321:107] - node _T_2023 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2321:118] - node _T_2024 = and(_T_2022, _T_2023) @[dec_tlu_ctl.scala 2321:113] - node _T_2025 = orr(_T_2024) @[dec_tlu_ctl.scala 2321:125] - node _T_2026 = and(_T_2021, _T_2025) @[dec_tlu_ctl.scala 2321:98] - node _T_2027 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2322:34] - node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_2029 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2322:91] - node _T_2030 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2323:34] - node _T_2031 = bits(_T_2030, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_2032 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2323:94] - node _T_2033 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2324:34] - node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_2035 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2326:34] - node _T_2037 = bits(_T_2036, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2327:34] - node _T_2039 = bits(_T_2038, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2328:34] - node _T_2041 = bits(_T_2040, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_2042 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2329:34] - node _T_2043 = bits(_T_2042, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_2044 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2330:34] - node _T_2045 = bits(_T_2044, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_2046 = mux(_T_1880, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_1882, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_1884, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_1886, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_1890, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_1896, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_1901, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_1903, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_1905, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_1907, _T_1908, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_1910, _T_1911, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_1913, _T_1914, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = mux(_T_1916, _T_1917, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2059 = mux(_T_1919, _T_1921, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2060 = mux(_T_1923, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2061 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2062 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2063 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2064 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2065 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2066 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2067 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2068 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2069 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2070 = mux(_T_1955, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2071 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2072 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2073 = mux(_T_1966, _T_1967, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2074 = mux(_T_1969, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2075 = mux(_T_1971, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2076 = mux(_T_1973, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2077 = mux(_T_1975, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2078 = mux(_T_1977, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2079 = mux(_T_1979, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2080 = mux(_T_1981, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2081 = mux(_T_1983, _T_1985, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2082 = mux(_T_1987, _T_1989, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2083 = mux(_T_1991, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2084 = mux(_T_1993, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2085 = mux(_T_1995, _T_1997, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2086 = mux(_T_1999, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2087 = mux(_T_2001, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2088 = mux(_T_2003, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2089 = mux(_T_2005, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2090 = mux(_T_2007, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2091 = mux(_T_2009, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2092 = mux(_T_2011, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2093 = mux(_T_2013, _T_2016, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2094 = mux(_T_2018, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2095 = mux(_T_2028, _T_2029, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2096 = mux(_T_2031, _T_2032, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2097 = mux(_T_2034, _T_2035, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2098 = mux(_T_2037, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2099 = mux(_T_2039, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2100 = mux(_T_2041, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2101 = mux(_T_2043, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2102 = mux(_T_2045, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2103 = or(_T_2046, _T_2047) @[Mux.scala 27:72] + wire _T_1874 : UInt<1> @[Mux.scala 27:72] + _T_1874 <= _T_1873 @[Mux.scala 27:72] + node _T_1875 = and(_T_1593, _T_1874) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[2] <= _T_1875 @[dec_tlu_ctl.scala 2273:19] + node _T_1876 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2273:38] + node _T_1877 = not(_T_1876) @[dec_tlu_ctl.scala 2273:24] + node _T_1878 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1880 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1882 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1883 = bits(_T_1882, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1884 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1886 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[dec_tlu_ctl.scala 2277:94] + node _T_1888 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1889 = bits(_T_1888, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1890 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1891 = and(io.tlu_i0_commit_cmt, _T_1890) @[dec_tlu_ctl.scala 2278:94] + node _T_1892 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1893 = and(_T_1891, _T_1892) @[dec_tlu_ctl.scala 2278:115] + node _T_1894 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1896 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1897 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1898 = and(_T_1896, _T_1897) @[dec_tlu_ctl.scala 2279:115] + node _T_1899 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1901 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1903 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1905 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1910 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1914 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1915 = bits(_T_1914, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1916 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1920 = and(_T_1919, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1921 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1924 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1925 = and(_T_1923, _T_1924) @[dec_tlu_ctl.scala 2288:101] + node _T_1926 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1929 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1932 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1935 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1938 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1941 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1944 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1947 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1948 = bits(_T_1947, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1949 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1950 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1952 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1953 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1955 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1957 = or(_T_1955, _T_1956) @[dec_tlu_ctl.scala 2298:101] + node _T_1958 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1960 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1963 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1964 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1966 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1971 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1973 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1975 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1977 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1979 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1981 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1983 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1984 = or(_T_1983, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1985 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1987 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1988 = or(_T_1987, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1993 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1995 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1996 = and(_T_1995, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_2007 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_2009 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_2011 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_2012 = bits(_T_2011, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_2013 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_2014 = bits(_T_2013, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_2015 = not(_T_2014) @[dec_tlu_ctl.scala 2321:73] + node _T_2016 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_2018 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_2020 = not(_T_2019) @[dec_tlu_ctl.scala 2322:73] + node _T_2021 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_2022 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_2023 = and(_T_2021, _T_2022) @[dec_tlu_ctl.scala 2322:113] + node _T_2024 = orr(_T_2023) @[dec_tlu_ctl.scala 2322:125] + node _T_2025 = and(_T_2020, _T_2024) @[dec_tlu_ctl.scala 2322:98] + node _T_2026 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_2028 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_2029 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_2032 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_2034 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_2037 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_2038 = bits(_T_2037, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_2039 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_2040 = bits(_T_2039, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_2041 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_2042 = bits(_T_2041, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_2043 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_2044 = bits(_T_2043, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_2045 = mux(_T_1879, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_1881, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1883, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1885, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1889, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1895, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1900, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1902, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1904, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1909, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1912, _T_1913, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1915, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1918, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1922, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1954, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1959, _T_1960, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1962, _T_1963, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1965, _T_1966, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1968, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1970, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1972, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1974, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1976, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1978, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1980, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1982, _T_1984, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_1990, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_1992, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_1994, _T_1996, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_1998, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_2000, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2002, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2004, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2006, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2008, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2010, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2012, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2017, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2095 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2096 = mux(_T_2033, _T_2034, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2097 = mux(_T_2036, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2098 = mux(_T_2038, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2099 = mux(_T_2040, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2100 = mux(_T_2042, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2101 = mux(_T_2044, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2102 = or(_T_2045, _T_2046) @[Mux.scala 27:72] + node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72] node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72] node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72] node _T_2106 = or(_T_2105, _T_2050) @[Mux.scala 27:72] @@ -75553,576 +75553,576 @@ circuit quasar_wrapper : node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72] node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72] node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72] - node _T_2158 = or(_T_2157, _T_2102) @[Mux.scala 27:72] - wire _T_2159 : UInt<1> @[Mux.scala 27:72] - _T_2159 <= _T_2158 @[Mux.scala 27:72] - node _T_2160 = and(_T_1878, _T_2159) @[dec_tlu_ctl.scala 2272:44] - mhpmc_inc_r[3] <= _T_2160 @[dec_tlu_ctl.scala 2272:19] - reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2333:53] - _T_2161 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2333:53] - mhpmc_inc_r_d1[0] <= _T_2161 @[dec_tlu_ctl.scala 2333:20] - reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] - _T_2162 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2334:53] - mhpmc_inc_r_d1[1] <= _T_2162 @[dec_tlu_ctl.scala 2334:20] - reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] - _T_2163 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2335:53] - mhpmc_inc_r_d1[2] <= _T_2163 @[dec_tlu_ctl.scala 2335:20] - reg _T_2164 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] - _T_2164 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2336:53] - mhpmc_inc_r_d1[3] <= _T_2164 @[dec_tlu_ctl.scala 2336:20] - reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:56] - perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2337:56] - node _T_2165 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2340:53] - node _T_2166 = and(io.dec_tlu_dbg_halted, _T_2165) @[dec_tlu_ctl.scala 2340:44] - node _T_2167 = or(_T_2166, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2340:67] - perfcnt_halted <= _T_2167 @[dec_tlu_ctl.scala 2340:17] - node _T_2168 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:70] - node _T_2169 = and(io.dec_tlu_dbg_halted, _T_2168) @[dec_tlu_ctl.scala 2341:61] - node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2341:37] - node _T_2171 = bits(_T_2170, 0, 0) @[Bitwise.scala 72:15] - node _T_2172 = mux(_T_2171, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2173 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2341:104] - node _T_2174 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2341:120] - node _T_2175 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2341:136] - node _T_2176 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2341:152] - node _T_2177 = cat(_T_2175, _T_2176) @[Cat.scala 29:58] - node _T_2178 = cat(_T_2173, _T_2174) @[Cat.scala 29:58] - node _T_2179 = cat(_T_2178, _T_2177) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2172, _T_2179) @[dec_tlu_ctl.scala 2341:86] - node _T_2180 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2343:88] - node _T_2181 = not(_T_2180) @[dec_tlu_ctl.scala 2343:67] - node _T_2182 = and(perfcnt_halted_d1, _T_2181) @[dec_tlu_ctl.scala 2343:65] - node _T_2183 = not(_T_2182) @[dec_tlu_ctl.scala 2343:45] - node _T_2184 = and(mhpmc_inc_r_d1[0], _T_2183) @[dec_tlu_ctl.scala 2343:43] - io.dec_tlu_perfcnt0 <= _T_2184 @[dec_tlu_ctl.scala 2343:22] - node _T_2185 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2344:88] - node _T_2186 = not(_T_2185) @[dec_tlu_ctl.scala 2344:67] - node _T_2187 = and(perfcnt_halted_d1, _T_2186) @[dec_tlu_ctl.scala 2344:65] - node _T_2188 = not(_T_2187) @[dec_tlu_ctl.scala 2344:45] - node _T_2189 = and(mhpmc_inc_r_d1[1], _T_2188) @[dec_tlu_ctl.scala 2344:43] - io.dec_tlu_perfcnt1 <= _T_2189 @[dec_tlu_ctl.scala 2344:22] - node _T_2190 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2345:88] - node _T_2191 = not(_T_2190) @[dec_tlu_ctl.scala 2345:67] - node _T_2192 = and(perfcnt_halted_d1, _T_2191) @[dec_tlu_ctl.scala 2345:65] - node _T_2193 = not(_T_2192) @[dec_tlu_ctl.scala 2345:45] - node _T_2194 = and(mhpmc_inc_r_d1[2], _T_2193) @[dec_tlu_ctl.scala 2345:43] - io.dec_tlu_perfcnt2 <= _T_2194 @[dec_tlu_ctl.scala 2345:22] - node _T_2195 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2346:88] - node _T_2196 = not(_T_2195) @[dec_tlu_ctl.scala 2346:67] - node _T_2197 = and(perfcnt_halted_d1, _T_2196) @[dec_tlu_ctl.scala 2346:65] - node _T_2198 = not(_T_2197) @[dec_tlu_ctl.scala 2346:45] - node _T_2199 = and(mhpmc_inc_r_d1[3], _T_2198) @[dec_tlu_ctl.scala 2346:43] - io.dec_tlu_perfcnt3 <= _T_2199 @[dec_tlu_ctl.scala 2346:22] - node _T_2200 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2352:65] - node _T_2201 = eq(_T_2200, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2352:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2201) @[dec_tlu_ctl.scala 2352:43] - node _T_2202 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2353:23] - node _T_2203 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2353:61] - node _T_2204 = or(_T_2202, _T_2203) @[dec_tlu_ctl.scala 2353:39] - node _T_2205 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2353:86] - node mhpmc3_wr_en1 = and(_T_2204, _T_2205) @[dec_tlu_ctl.scala 2353:66] - node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2354:36] - node _T_2206 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2357:28] - node _T_2207 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2357:41] - node _T_2208 = cat(_T_2206, _T_2207) @[Cat.scala 29:58] - node _T_2209 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2210 = add(_T_2208, _T_2209) @[dec_tlu_ctl.scala 2357:49] - node _T_2211 = tail(_T_2210, 1) @[dec_tlu_ctl.scala 2357:49] - mhpmc3_incr <= _T_2211 @[dec_tlu_ctl.scala 2357:14] - node _T_2212 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2358:36] - node _T_2213 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2358:76] - node mhpmc3_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[dec_tlu_ctl.scala 2358:21] - node _T_2214 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2360:42] + wire _T_2158 : UInt<1> @[Mux.scala 27:72] + _T_2158 <= _T_2157 @[Mux.scala 27:72] + node _T_2159 = and(_T_1877, _T_2158) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[3] <= _T_2159 @[dec_tlu_ctl.scala 2273:19] + reg _T_2160 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] + _T_2160 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2334:53] + mhpmc_inc_r_d1[0] <= _T_2160 @[dec_tlu_ctl.scala 2334:20] + reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] + _T_2161 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2335:53] + mhpmc_inc_r_d1[1] <= _T_2161 @[dec_tlu_ctl.scala 2335:20] + reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] + _T_2162 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2336:53] + mhpmc_inc_r_d1[2] <= _T_2162 @[dec_tlu_ctl.scala 2336:20] + reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] + _T_2163 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2337:53] + mhpmc_inc_r_d1[3] <= _T_2163 @[dec_tlu_ctl.scala 2337:20] + reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:56] + perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2338:56] + node _T_2164 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:53] + node _T_2165 = and(io.dec_tlu_dbg_halted, _T_2164) @[dec_tlu_ctl.scala 2341:44] + node _T_2166 = or(_T_2165, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2341:67] + perfcnt_halted <= _T_2166 @[dec_tlu_ctl.scala 2341:17] + node _T_2167 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:70] + node _T_2168 = and(io.dec_tlu_dbg_halted, _T_2167) @[dec_tlu_ctl.scala 2342:61] + node _T_2169 = not(_T_2168) @[dec_tlu_ctl.scala 2342:37] + node _T_2170 = bits(_T_2169, 0, 0) @[Bitwise.scala 72:15] + node _T_2171 = mux(_T_2170, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2172 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2342:104] + node _T_2173 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2342:120] + node _T_2174 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2342:136] + node _T_2175 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2342:152] + node _T_2176 = cat(_T_2174, _T_2175) @[Cat.scala 29:58] + node _T_2177 = cat(_T_2172, _T_2173) @[Cat.scala 29:58] + node _T_2178 = cat(_T_2177, _T_2176) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2171, _T_2178) @[dec_tlu_ctl.scala 2342:86] + node _T_2179 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2344:88] + node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2344:67] + node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2344:65] + node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2344:45] + node _T_2183 = and(mhpmc_inc_r_d1[0], _T_2182) @[dec_tlu_ctl.scala 2344:43] + io.dec_tlu_perfcnt0 <= _T_2183 @[dec_tlu_ctl.scala 2344:22] + node _T_2184 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2345:88] + node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2345:67] + node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2345:65] + node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2345:45] + node _T_2188 = and(mhpmc_inc_r_d1[1], _T_2187) @[dec_tlu_ctl.scala 2345:43] + io.dec_tlu_perfcnt1 <= _T_2188 @[dec_tlu_ctl.scala 2345:22] + node _T_2189 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2346:88] + node _T_2190 = not(_T_2189) @[dec_tlu_ctl.scala 2346:67] + node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[dec_tlu_ctl.scala 2346:65] + node _T_2192 = not(_T_2191) @[dec_tlu_ctl.scala 2346:45] + node _T_2193 = and(mhpmc_inc_r_d1[2], _T_2192) @[dec_tlu_ctl.scala 2346:43] + io.dec_tlu_perfcnt2 <= _T_2193 @[dec_tlu_ctl.scala 2346:22] + node _T_2194 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2347:88] + node _T_2195 = not(_T_2194) @[dec_tlu_ctl.scala 2347:67] + node _T_2196 = and(perfcnt_halted_d1, _T_2195) @[dec_tlu_ctl.scala 2347:65] + node _T_2197 = not(_T_2196) @[dec_tlu_ctl.scala 2347:45] + node _T_2198 = and(mhpmc_inc_r_d1[3], _T_2197) @[dec_tlu_ctl.scala 2347:43] + io.dec_tlu_perfcnt3 <= _T_2198 @[dec_tlu_ctl.scala 2347:22] + node _T_2199 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2353:65] + node _T_2200 = eq(_T_2199, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2353:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2200) @[dec_tlu_ctl.scala 2353:43] + node _T_2201 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2354:23] + node _T_2202 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2354:61] + node _T_2203 = or(_T_2201, _T_2202) @[dec_tlu_ctl.scala 2354:39] + node _T_2204 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2354:86] + node mhpmc3_wr_en1 = and(_T_2203, _T_2204) @[dec_tlu_ctl.scala 2354:66] + node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2355:36] + node _T_2205 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2358:28] + node _T_2206 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2358:41] + node _T_2207 = cat(_T_2205, _T_2206) @[Cat.scala 29:58] + node _T_2208 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2209 = add(_T_2207, _T_2208) @[dec_tlu_ctl.scala 2358:49] + node _T_2210 = tail(_T_2209, 1) @[dec_tlu_ctl.scala 2358:49] + mhpmc3_incr <= _T_2210 @[dec_tlu_ctl.scala 2358:14] + node _T_2211 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2359:36] + node _T_2212 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2359:76] + node mhpmc3_ns = mux(_T_2211, io.dec_csr_wrdata_r, _T_2212) @[dec_tlu_ctl.scala 2359:21] + node _T_2213 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2361:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_26.io.en <= _T_2214 @[lib.scala 371:17] + rvclkhdr_26.io.en <= _T_2213 @[lib.scala 371:17] rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2215 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2215 <= mhpmc3_ns @[lib.scala 374:16] - mhpmc3 <= _T_2215 @[dec_tlu_ctl.scala 2360:9] - node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2362:66] - node _T_2217 = eq(_T_2216, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2362:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[dec_tlu_ctl.scala 2362:44] - node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2363:38] - node _T_2218 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2364:38] - node _T_2219 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2364:78] - node mhpmc3h_ns = mux(_T_2218, io.dec_csr_wrdata_r, _T_2219) @[dec_tlu_ctl.scala 2364:22] - node _T_2220 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2366:46] + reg _T_2214 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2214 <= mhpmc3_ns @[lib.scala 374:16] + mhpmc3 <= _T_2214 @[dec_tlu_ctl.scala 2361:9] + node _T_2215 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2363:66] + node _T_2216 = eq(_T_2215, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2363:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2216) @[dec_tlu_ctl.scala 2363:44] + node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2364:38] + node _T_2217 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2365:38] + node _T_2218 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2365:78] + node mhpmc3h_ns = mux(_T_2217, io.dec_csr_wrdata_r, _T_2218) @[dec_tlu_ctl.scala 2365:22] + node _T_2219 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_27.io.en <= _T_2220 @[lib.scala 371:17] + rvclkhdr_27.io.en <= _T_2219 @[lib.scala 371:17] rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2221 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2221 <= mhpmc3h_ns @[lib.scala 374:16] - mhpmc3h <= _T_2221 @[dec_tlu_ctl.scala 2366:10] - node _T_2222 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2371:65] - node _T_2223 = eq(_T_2222, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2371:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2223) @[dec_tlu_ctl.scala 2371:43] - node _T_2224 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2372:23] - node _T_2225 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2372:61] - node _T_2226 = or(_T_2224, _T_2225) @[dec_tlu_ctl.scala 2372:39] - node _T_2227 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2372:86] - node mhpmc4_wr_en1 = and(_T_2226, _T_2227) @[dec_tlu_ctl.scala 2372:66] - node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2373:36] - node _T_2228 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2377:28] - node _T_2229 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2377:41] - node _T_2230 = cat(_T_2228, _T_2229) @[Cat.scala 29:58] - node _T_2231 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2232 = add(_T_2230, _T_2231) @[dec_tlu_ctl.scala 2377:49] - node _T_2233 = tail(_T_2232, 1) @[dec_tlu_ctl.scala 2377:49] - mhpmc4_incr <= _T_2233 @[dec_tlu_ctl.scala 2377:14] - node _T_2234 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2378:36] - node _T_2235 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2378:63] - node _T_2236 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2378:82] - node mhpmc4_ns = mux(_T_2234, _T_2235, _T_2236) @[dec_tlu_ctl.scala 2378:21] - node _T_2237 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2379:43] + reg _T_2220 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2220 <= mhpmc3h_ns @[lib.scala 374:16] + mhpmc3h <= _T_2220 @[dec_tlu_ctl.scala 2367:10] + node _T_2221 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2372:65] + node _T_2222 = eq(_T_2221, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2372:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2222) @[dec_tlu_ctl.scala 2372:43] + node _T_2223 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2373:23] + node _T_2224 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2373:61] + node _T_2225 = or(_T_2223, _T_2224) @[dec_tlu_ctl.scala 2373:39] + node _T_2226 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2373:86] + node mhpmc4_wr_en1 = and(_T_2225, _T_2226) @[dec_tlu_ctl.scala 2373:66] + node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2374:36] + node _T_2227 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2378:28] + node _T_2228 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2378:41] + node _T_2229 = cat(_T_2227, _T_2228) @[Cat.scala 29:58] + node _T_2230 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2231 = add(_T_2229, _T_2230) @[dec_tlu_ctl.scala 2378:49] + node _T_2232 = tail(_T_2231, 1) @[dec_tlu_ctl.scala 2378:49] + mhpmc4_incr <= _T_2232 @[dec_tlu_ctl.scala 2378:14] + node _T_2233 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2379:36] + node _T_2234 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2379:63] + node _T_2235 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2379:82] + node mhpmc4_ns = mux(_T_2233, _T_2234, _T_2235) @[dec_tlu_ctl.scala 2379:21] + node _T_2236 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_28.io.en <= _T_2237 @[lib.scala 371:17] + rvclkhdr_28.io.en <= _T_2236 @[lib.scala 371:17] rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2238 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2238 <= mhpmc4_ns @[lib.scala 374:16] - mhpmc4 <= _T_2238 @[dec_tlu_ctl.scala 2379:9] - node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2381:66] - node _T_2240 = eq(_T_2239, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2381:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[dec_tlu_ctl.scala 2381:44] - node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2382:38] - node _T_2241 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2383:38] - node _T_2242 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2383:78] - node mhpmc4h_ns = mux(_T_2241, io.dec_csr_wrdata_r, _T_2242) @[dec_tlu_ctl.scala 2383:22] - node _T_2243 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2384:46] + reg _T_2237 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2237 <= mhpmc4_ns @[lib.scala 374:16] + mhpmc4 <= _T_2237 @[dec_tlu_ctl.scala 2380:9] + node _T_2238 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] + node _T_2239 = eq(_T_2238, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2382:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2239) @[dec_tlu_ctl.scala 2382:44] + node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2383:38] + node _T_2240 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] + node _T_2241 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] + node mhpmc4h_ns = mux(_T_2240, io.dec_csr_wrdata_r, _T_2241) @[dec_tlu_ctl.scala 2384:22] + node _T_2242 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2385:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_29.io.en <= _T_2243 @[lib.scala 371:17] + rvclkhdr_29.io.en <= _T_2242 @[lib.scala 371:17] rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2244 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2244 <= mhpmc4h_ns @[lib.scala 374:16] - mhpmc4h <= _T_2244 @[dec_tlu_ctl.scala 2384:10] - node _T_2245 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2390:65] - node _T_2246 = eq(_T_2245, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2390:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2246) @[dec_tlu_ctl.scala 2390:43] - node _T_2247 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2391:23] - node _T_2248 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2391:61] - node _T_2249 = or(_T_2247, _T_2248) @[dec_tlu_ctl.scala 2391:39] - node _T_2250 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2391:86] - node mhpmc5_wr_en1 = and(_T_2249, _T_2250) @[dec_tlu_ctl.scala 2391:66] - node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2392:36] - node _T_2251 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2394:28] - node _T_2252 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2394:41] - node _T_2253 = cat(_T_2251, _T_2252) @[Cat.scala 29:58] - node _T_2254 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2255 = add(_T_2253, _T_2254) @[dec_tlu_ctl.scala 2394:49] - node _T_2256 = tail(_T_2255, 1) @[dec_tlu_ctl.scala 2394:49] - mhpmc5_incr <= _T_2256 @[dec_tlu_ctl.scala 2394:14] - node _T_2257 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2395:36] - node _T_2258 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2395:76] - node mhpmc5_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[dec_tlu_ctl.scala 2395:21] - node _T_2259 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2397:43] + reg _T_2243 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2243 <= mhpmc4h_ns @[lib.scala 374:16] + mhpmc4h <= _T_2243 @[dec_tlu_ctl.scala 2385:10] + node _T_2244 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] + node _T_2245 = eq(_T_2244, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2391:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2245) @[dec_tlu_ctl.scala 2391:43] + node _T_2246 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] + node _T_2247 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2392:61] + node _T_2248 = or(_T_2246, _T_2247) @[dec_tlu_ctl.scala 2392:39] + node _T_2249 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2392:86] + node mhpmc5_wr_en1 = and(_T_2248, _T_2249) @[dec_tlu_ctl.scala 2392:66] + node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2393:36] + node _T_2250 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2395:28] + node _T_2251 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2395:41] + node _T_2252 = cat(_T_2250, _T_2251) @[Cat.scala 29:58] + node _T_2253 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2254 = add(_T_2252, _T_2253) @[dec_tlu_ctl.scala 2395:49] + node _T_2255 = tail(_T_2254, 1) @[dec_tlu_ctl.scala 2395:49] + mhpmc5_incr <= _T_2255 @[dec_tlu_ctl.scala 2395:14] + node _T_2256 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] + node _T_2257 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] + node mhpmc5_ns = mux(_T_2256, io.dec_csr_wrdata_r, _T_2257) @[dec_tlu_ctl.scala 2396:21] + node _T_2258 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_30.io.en <= _T_2259 @[lib.scala 371:17] + rvclkhdr_30.io.en <= _T_2258 @[lib.scala 371:17] rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2260 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2260 <= mhpmc5_ns @[lib.scala 374:16] - mhpmc5 <= _T_2260 @[dec_tlu_ctl.scala 2397:9] - node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2399:66] - node _T_2262 = eq(_T_2261, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2399:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[dec_tlu_ctl.scala 2399:44] - node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2400:38] - node _T_2263 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2401:38] - node _T_2264 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2401:78] - node mhpmc5h_ns = mux(_T_2263, io.dec_csr_wrdata_r, _T_2264) @[dec_tlu_ctl.scala 2401:22] - node _T_2265 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2403:46] + reg _T_2259 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2259 <= mhpmc5_ns @[lib.scala 374:16] + mhpmc5 <= _T_2259 @[dec_tlu_ctl.scala 2398:9] + node _T_2260 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] + node _T_2261 = eq(_T_2260, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2400:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2261) @[dec_tlu_ctl.scala 2400:44] + node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2401:38] + node _T_2262 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] + node _T_2263 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] + node mhpmc5h_ns = mux(_T_2262, io.dec_csr_wrdata_r, _T_2263) @[dec_tlu_ctl.scala 2402:22] + node _T_2264 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset rvclkhdr_31.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_31.io.en <= _T_2265 @[lib.scala 371:17] + rvclkhdr_31.io.en <= _T_2264 @[lib.scala 371:17] rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2266 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2266 <= mhpmc5h_ns @[lib.scala 374:16] - mhpmc5h <= _T_2266 @[dec_tlu_ctl.scala 2403:10] - node _T_2267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2408:65] - node _T_2268 = eq(_T_2267, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2408:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2268) @[dec_tlu_ctl.scala 2408:43] - node _T_2269 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2409:23] - node _T_2270 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2409:61] - node _T_2271 = or(_T_2269, _T_2270) @[dec_tlu_ctl.scala 2409:39] - node _T_2272 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2409:86] - node mhpmc6_wr_en1 = and(_T_2271, _T_2272) @[dec_tlu_ctl.scala 2409:66] - node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2410:36] - node _T_2273 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2412:28] - node _T_2274 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2412:41] - node _T_2275 = cat(_T_2273, _T_2274) @[Cat.scala 29:58] - node _T_2276 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2277 = add(_T_2275, _T_2276) @[dec_tlu_ctl.scala 2412:49] - node _T_2278 = tail(_T_2277, 1) @[dec_tlu_ctl.scala 2412:49] - mhpmc6_incr <= _T_2278 @[dec_tlu_ctl.scala 2412:14] - node _T_2279 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2413:36] - node _T_2280 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2413:76] - node mhpmc6_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[dec_tlu_ctl.scala 2413:21] - node _T_2281 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2415:43] + reg _T_2265 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2265 <= mhpmc5h_ns @[lib.scala 374:16] + mhpmc5h <= _T_2265 @[dec_tlu_ctl.scala 2404:10] + node _T_2266 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2409:65] + node _T_2267 = eq(_T_2266, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2409:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2267) @[dec_tlu_ctl.scala 2409:43] + node _T_2268 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2410:23] + node _T_2269 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2410:61] + node _T_2270 = or(_T_2268, _T_2269) @[dec_tlu_ctl.scala 2410:39] + node _T_2271 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2410:86] + node mhpmc6_wr_en1 = and(_T_2270, _T_2271) @[dec_tlu_ctl.scala 2410:66] + node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2411:36] + node _T_2272 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2413:28] + node _T_2273 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2413:41] + node _T_2274 = cat(_T_2272, _T_2273) @[Cat.scala 29:58] + node _T_2275 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2276 = add(_T_2274, _T_2275) @[dec_tlu_ctl.scala 2413:49] + node _T_2277 = tail(_T_2276, 1) @[dec_tlu_ctl.scala 2413:49] + mhpmc6_incr <= _T_2277 @[dec_tlu_ctl.scala 2413:14] + node _T_2278 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2414:36] + node _T_2279 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2414:76] + node mhpmc6_ns = mux(_T_2278, io.dec_csr_wrdata_r, _T_2279) @[dec_tlu_ctl.scala 2414:21] + node _T_2280 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2416:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset rvclkhdr_32.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_32.io.en <= _T_2281 @[lib.scala 371:17] + rvclkhdr_32.io.en <= _T_2280 @[lib.scala 371:17] rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2282 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2282 <= mhpmc6_ns @[lib.scala 374:16] - mhpmc6 <= _T_2282 @[dec_tlu_ctl.scala 2415:9] - node _T_2283 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2417:66] - node _T_2284 = eq(_T_2283, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2417:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2284) @[dec_tlu_ctl.scala 2417:44] - node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2418:38] - node _T_2285 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2419:38] - node _T_2286 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2419:78] - node mhpmc6h_ns = mux(_T_2285, io.dec_csr_wrdata_r, _T_2286) @[dec_tlu_ctl.scala 2419:22] - node _T_2287 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2421:46] + reg _T_2281 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2281 <= mhpmc6_ns @[lib.scala 374:16] + mhpmc6 <= _T_2281 @[dec_tlu_ctl.scala 2416:9] + node _T_2282 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2418:66] + node _T_2283 = eq(_T_2282, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2418:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2283) @[dec_tlu_ctl.scala 2418:44] + node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2419:38] + node _T_2284 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2420:38] + node _T_2285 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2420:78] + node mhpmc6h_ns = mux(_T_2284, io.dec_csr_wrdata_r, _T_2285) @[dec_tlu_ctl.scala 2420:22] + node _T_2286 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2422:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset rvclkhdr_33.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_33.io.en <= _T_2287 @[lib.scala 371:17] + rvclkhdr_33.io.en <= _T_2286 @[lib.scala 371:17] rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2288 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2288 <= mhpmc6h_ns @[lib.scala 374:16] - mhpmc6h <= _T_2288 @[dec_tlu_ctl.scala 2421:10] - node _T_2289 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2428:50] - node _T_2290 = gt(_T_2289, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2428:56] - node _T_2291 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2428:93] - node _T_2292 = orr(_T_2291) @[dec_tlu_ctl.scala 2428:102] - node _T_2293 = or(_T_2290, _T_2292) @[dec_tlu_ctl.scala 2428:71] - node _T_2294 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2428:141] - node event_saturate_r = mux(_T_2293, UInt<10>("h0204"), _T_2294) @[dec_tlu_ctl.scala 2428:28] - node _T_2295 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2430:63] - node _T_2296 = eq(_T_2295, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2430:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2296) @[dec_tlu_ctl.scala 2430:41] - node _T_2297 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2432:80] - reg _T_2298 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2297 : @[Reg.scala 28:19] - _T_2298 <= event_saturate_r @[Reg.scala 28:23] + reg _T_2287 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2287 <= mhpmc6h_ns @[lib.scala 374:16] + mhpmc6h <= _T_2287 @[dec_tlu_ctl.scala 2422:10] + node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:50] + node _T_2289 = gt(_T_2288, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2429:56] + node _T_2290 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2429:93] + node _T_2291 = orr(_T_2290) @[dec_tlu_ctl.scala 2429:102] + node _T_2292 = or(_T_2289, _T_2291) @[dec_tlu_ctl.scala 2429:71] + node _T_2293 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:141] + node event_saturate_r = mux(_T_2292, UInt<10>("h0204"), _T_2293) @[dec_tlu_ctl.scala 2429:28] + node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2431:63] + node _T_2295 = eq(_T_2294, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2431:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2431:41] + node _T_2296 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2433:80] + reg _T_2297 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2296 : @[Reg.scala 28:19] + _T_2297 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2298 @[dec_tlu_ctl.scala 2432:9] - node _T_2299 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2437:63] - node _T_2300 = eq(_T_2299, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2437:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2300) @[dec_tlu_ctl.scala 2437:41] - node _T_2301 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2438:80] - reg _T_2302 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2301 : @[Reg.scala 28:19] - _T_2302 <= event_saturate_r @[Reg.scala 28:23] + mhpme3 <= _T_2297 @[dec_tlu_ctl.scala 2433:9] + node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2438:63] + node _T_2299 = eq(_T_2298, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2438:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2438:41] + node _T_2300 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2439:80] + reg _T_2301 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2300 : @[Reg.scala 28:19] + _T_2301 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2302 @[dec_tlu_ctl.scala 2438:9] - node _T_2303 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2444:63] - node _T_2304 = eq(_T_2303, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2444:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2304) @[dec_tlu_ctl.scala 2444:41] - node _T_2305 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2445:80] - reg _T_2306 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2305 : @[Reg.scala 28:19] - _T_2306 <= event_saturate_r @[Reg.scala 28:23] + mhpme4 <= _T_2301 @[dec_tlu_ctl.scala 2439:9] + node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2445:63] + node _T_2303 = eq(_T_2302, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2445:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2445:41] + node _T_2304 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2446:80] + reg _T_2305 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2304 : @[Reg.scala 28:19] + _T_2305 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2306 @[dec_tlu_ctl.scala 2445:9] - node _T_2307 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2451:63] - node _T_2308 = eq(_T_2307, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2451:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2308) @[dec_tlu_ctl.scala 2451:41] - node _T_2309 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2452:80] - reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2309 : @[Reg.scala 28:19] - _T_2310 <= event_saturate_r @[Reg.scala 28:23] + mhpme5 <= _T_2305 @[dec_tlu_ctl.scala 2446:9] + node _T_2306 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2452:63] + node _T_2307 = eq(_T_2306, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2452:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2307) @[dec_tlu_ctl.scala 2452:41] + node _T_2308 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2453:80] + reg _T_2309 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2308 : @[Reg.scala 28:19] + _T_2309 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2310 @[dec_tlu_ctl.scala 2452:9] - node _T_2311 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2468:70] - node _T_2312 = eq(_T_2311, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2468:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2312) @[dec_tlu_ctl.scala 2468:48] - node _T_2313 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2470:54] + mhpme6 <= _T_2309 @[dec_tlu_ctl.scala 2453:9] + node _T_2310 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2469:70] + node _T_2311 = eq(_T_2310, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2469:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2311) @[dec_tlu_ctl.scala 2469:48] + node _T_2312 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2471:54] wire temp_ncount0 : UInt<1> - temp_ncount0 <= _T_2313 - node _T_2314 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2471:54] + temp_ncount0 <= _T_2312 + node _T_2313 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2472:54] wire temp_ncount1 : UInt<1> - temp_ncount1 <= _T_2314 - node _T_2315 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2472:55] + temp_ncount1 <= _T_2313 + node _T_2314 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2473:55] wire temp_ncount6_2 : UInt<5> - temp_ncount6_2 <= _T_2315 - node _T_2316 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2473:74] - node _T_2317 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2473:103] - reg _T_2318 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2317 : @[Reg.scala 28:19] - _T_2318 <= _T_2316 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2314 + node _T_2315 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2474:74] + node _T_2316 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2474:103] + reg _T_2317 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2316 : @[Reg.scala 28:19] + _T_2317 <= _T_2315 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2318 @[dec_tlu_ctl.scala 2473:17] - node _T_2319 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2475:72] - node _T_2320 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:99] - reg _T_2321 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2320 : @[Reg.scala 28:19] - _T_2321 <= _T_2319 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2317 @[dec_tlu_ctl.scala 2474:17] + node _T_2318 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2476:72] + node _T_2319 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2476:99] + reg _T_2320 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2319 : @[Reg.scala 28:19] + _T_2320 <= _T_2318 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2321 @[dec_tlu_ctl.scala 2475:15] - node _T_2322 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2323 = cat(_T_2322, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2323 @[dec_tlu_ctl.scala 2476:16] - node _T_2324 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2483:51] - node _T_2325 = or(_T_2324, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2483:78] - node _T_2326 = or(_T_2325, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2483:104] - node _T_2327 = or(_T_2326, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2483:130] - node _T_2328 = or(_T_2327, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2484:32] - node _T_2329 = or(_T_2328, io.clk_override) @[dec_tlu_ctl.scala 2484:59] - node _T_2330 = bits(_T_2329, 0, 0) @[dec_tlu_ctl.scala 2484:78] + temp_ncount0 <= _T_2320 @[dec_tlu_ctl.scala 2476:15] + node _T_2321 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2322 = cat(_T_2321, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2322 @[dec_tlu_ctl.scala 2477:16] + node _T_2323 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2484:51] + node _T_2324 = or(_T_2323, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2484:78] + node _T_2325 = or(_T_2324, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2484:104] + node _T_2326 = or(_T_2325, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2484:130] + node _T_2327 = or(_T_2326, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2485:32] + node _T_2328 = or(_T_2327, io.clk_override) @[dec_tlu_ctl.scala 2485:59] + node _T_2329 = bits(_T_2328, 0, 0) @[dec_tlu_ctl.scala 2485:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_34.io.en <= _T_2330 @[lib.scala 345:16] + rvclkhdr_34.io.en <= _T_2329 @[lib.scala 345:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2486:62] - _T_2331 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2486:62] - io.dec_tlu_i0_valid_wb1 <= _T_2331 @[dec_tlu_ctl.scala 2486:30] - node _T_2332 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2487:91] - node _T_2333 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2487:137] - node _T_2334 = and(io.trigger_hit_r_d1, _T_2333) @[dec_tlu_ctl.scala 2487:135] - node _T_2335 = or(_T_2332, _T_2334) @[dec_tlu_ctl.scala 2487:112] - reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] - _T_2336 <= _T_2335 @[dec_tlu_ctl.scala 2487:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2487:30] - reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] - _T_2337 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2488:62] - io.dec_tlu_exc_cause_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2488:30] - reg _T_2338 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] - _T_2338 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2489:62] - io.dec_tlu_int_valid_wb1 <= _T_2338 @[dec_tlu_ctl.scala 2489:30] - io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2491:24] - node _T_2339 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2497:61] - node _T_2340 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2498:42] - node _T_2341 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2499:40] - node _T_2342 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2500:39] - node _T_2343 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2501:40] - node _T_2344 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2345 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2502:40] - node _T_2346 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2502:103] - node _T_2347 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2502:128] - node _T_2348 = cat(UInt<3>("h00"), _T_2347) @[Cat.scala 29:58] - node _T_2349 = cat(_T_2348, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2350 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] - node _T_2351 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58] - node _T_2353 = cat(_T_2352, _T_2349) @[Cat.scala 29:58] - node _T_2354 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2503:38] - node _T_2355 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2503:70] - node _T_2356 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2503:96] - node _T_2357 = cat(_T_2355, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2358 = cat(_T_2357, _T_2356) @[Cat.scala 29:58] - node _T_2359 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2504:36] - node _T_2360 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2504:78] - node _T_2361 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2504:102] - node _T_2362 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2504:123] - node _T_2363 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2504:144] - node _T_2364 = cat(_T_2363, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2365 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2366 = cat(_T_2365, _T_2364) @[Cat.scala 29:58] - node _T_2367 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2368 = cat(UInt<1>("h00"), _T_2360) @[Cat.scala 29:58] - node _T_2369 = cat(_T_2368, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2370 = cat(_T_2369, _T_2367) @[Cat.scala 29:58] - node _T_2371 = cat(_T_2370, _T_2366) @[Cat.scala 29:58] - node _T_2372 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2505:36] - node _T_2373 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2505:75] - node _T_2374 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2505:96] - node _T_2375 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2505:114] - node _T_2376 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2505:132] - node _T_2377 = cat(_T_2376, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2378 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2379 = cat(_T_2378, _T_2377) @[Cat.scala 29:58] - node _T_2380 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2381 = cat(UInt<1>("h00"), _T_2373) @[Cat.scala 29:58] - node _T_2382 = cat(_T_2381, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2383 = cat(_T_2382, _T_2380) @[Cat.scala 29:58] - node _T_2384 = cat(_T_2383, _T_2379) @[Cat.scala 29:58] - node _T_2385 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2506:40] - node _T_2386 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2506:65] - node _T_2387 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2507:40] - node _T_2388 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2507:69] - node _T_2389 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2508:42] - node _T_2390 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2508:72] - node _T_2391 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2509:42] - node _T_2392 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2509:72] - node _T_2393 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2510:41] - node _T_2394 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2510:66] - node _T_2395 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2511:37] - node _T_2396 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2397 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2512:39] - node _T_2398 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2512:64] - node _T_2399 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2513:40] - node _T_2400 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2513:80] - node _T_2401 = cat(UInt<28>("h00"), _T_2400) @[Cat.scala 29:58] - node _T_2402 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2514:38] - node _T_2403 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2514:63] - node _T_2404 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2515:37] - node _T_2405 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2515:62] - node _T_2406 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2516:39] - node _T_2407 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2516:64] - node _T_2408 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2517:38] - node _T_2409 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2410 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2518:39] - node _T_2411 = cat(meivt, meihap) @[Cat.scala 29:58] - node _T_2412 = cat(_T_2411, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2413 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2519:41] - node _T_2414 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2519:81] - node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58] - node _T_2416 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] - node _T_2417 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] - node _T_2418 = cat(UInt<28>("h00"), _T_2417) @[Cat.scala 29:58] - node _T_2419 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2521:38] - node _T_2420 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2521:78] - node _T_2421 = cat(UInt<28>("h00"), _T_2420) @[Cat.scala 29:58] - node _T_2422 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2522:37] - node _T_2423 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2522:77] - node _T_2424 = cat(UInt<23>("h00"), _T_2423) @[Cat.scala 29:58] - node _T_2425 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2523:37] - node _T_2426 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2523:77] - node _T_2427 = cat(UInt<13>("h00"), _T_2426) @[Cat.scala 29:58] - node _T_2428 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2524:37] - node _T_2429 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2524:85] - node _T_2430 = cat(UInt<16>("h04000"), _T_2429) @[Cat.scala 29:58] - node _T_2431 = cat(_T_2430, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2432 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2525:36] - node _T_2433 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2434 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2526:39] - node _T_2435 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2526:64] - node _T_2436 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2527:40] - node _T_2437 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2527:65] - node _T_2438 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2528:39] - node _T_2439 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2528:64] - node _T_2440 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2529:41] - node _T_2441 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2529:80] - node _T_2442 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2529:104] - node _T_2443 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2529:131] - node _T_2444 = cat(UInt<3>("h00"), _T_2443) @[Cat.scala 29:58] - node _T_2445 = cat(_T_2444, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2446 = cat(UInt<2>("h00"), _T_2442) @[Cat.scala 29:58] - node _T_2447 = cat(UInt<7>("h00"), _T_2441) @[Cat.scala 29:58] - node _T_2448 = cat(_T_2447, _T_2446) @[Cat.scala 29:58] - node _T_2449 = cat(_T_2448, _T_2445) @[Cat.scala 29:58] - node _T_2450 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2530:38] - node _T_2451 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2530:78] - node _T_2452 = cat(UInt<30>("h00"), _T_2451) @[Cat.scala 29:58] - node _T_2453 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2531:40] - node _T_2454 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2531:74] - node _T_2455 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2532:40] - node _T_2456 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] - node _T_2457 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2533:39] - node _T_2458 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2533:64] - node _T_2459 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2534:41] - node _T_2460 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2534:66] - node _T_2461 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] - node _T_2462 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] - node _T_2463 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2536:39] - node _T_2464 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2536:64] - node _T_2465 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2537:39] - node _T_2466 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2537:64] - node _T_2467 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2538:39] - node _T_2468 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2538:64] - node _T_2469 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2539:39] - node _T_2470 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2539:64] - node _T_2471 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2540:40] - node _T_2472 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2540:65] - node _T_2473 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2541:40] - node _T_2474 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2541:65] - node _T_2475 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2542:40] - node _T_2476 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2542:65] - node _T_2477 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2543:40] - node _T_2478 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2543:65] - node _T_2479 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2544:38] - node _T_2480 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2544:78] - node _T_2481 = cat(UInt<26>("h00"), _T_2480) @[Cat.scala 29:58] - node _T_2482 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2545:38] - node _T_2483 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2545:78] - node _T_2484 = cat(UInt<30>("h00"), _T_2483) @[Cat.scala 29:58] - node _T_2485 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2546:39] - node _T_2486 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2546:79] - node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] - node _T_2488 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2547:39] - node _T_2489 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2547:79] - node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58] - node _T_2491 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2548:39] - node _T_2492 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2548:78] - node _T_2493 = cat(UInt<22>("h00"), _T_2492) @[Cat.scala 29:58] - node _T_2494 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2549:39] - node _T_2495 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2549:78] - node _T_2496 = cat(UInt<22>("h00"), _T_2495) @[Cat.scala 29:58] - node _T_2497 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2550:46] - node _T_2498 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2550:86] - node _T_2499 = cat(UInt<25>("h00"), _T_2498) @[Cat.scala 29:58] - node _T_2500 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2551:37] - node _T_2501 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] - node _T_2502 = cat(_T_2501, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2503 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2552:37] - node _T_2504 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2552:76] - node _T_2505 = mux(_T_2339, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2506 = mux(_T_2340, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2507 = mux(_T_2341, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2508 = mux(_T_2342, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2509 = mux(_T_2343, _T_2344, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2510 = mux(_T_2345, _T_2353, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2511 = mux(_T_2354, _T_2358, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2512 = mux(_T_2359, _T_2371, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2513 = mux(_T_2372, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2514 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2515 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2516 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2517 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2518 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2519 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2520 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2521 = mux(_T_2399, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2522 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2523 = mux(_T_2404, _T_2405, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2524 = mux(_T_2406, _T_2407, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2525 = mux(_T_2408, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2526 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2527 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2528 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2529 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2530 = mux(_T_2422, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2531 = mux(_T_2425, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2532 = mux(_T_2428, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2533 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2534 = mux(_T_2434, _T_2435, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2535 = mux(_T_2436, _T_2437, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2536 = mux(_T_2438, _T_2439, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2537 = mux(_T_2440, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2538 = mux(_T_2450, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2539 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2540 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2541 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2542 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2543 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2544 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2545 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2546 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2547 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2548 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2549 = mux(_T_2473, _T_2474, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2550 = mux(_T_2475, _T_2476, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2551 = mux(_T_2477, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2552 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2553 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2554 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2555 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2556 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2557 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2558 = mux(_T_2497, _T_2499, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2559 = mux(_T_2500, _T_2502, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2560 = mux(_T_2503, _T_2504, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2561 = or(_T_2505, _T_2506) @[Mux.scala 27:72] + reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] + _T_2330 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2487:62] + io.dec_tlu_i0_valid_wb1 <= _T_2330 @[dec_tlu_ctl.scala 2487:30] + node _T_2331 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2488:91] + node _T_2332 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2488:137] + node _T_2333 = and(io.trigger_hit_r_d1, _T_2332) @[dec_tlu_ctl.scala 2488:135] + node _T_2334 = or(_T_2331, _T_2333) @[dec_tlu_ctl.scala 2488:112] + reg _T_2335 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] + _T_2335 <= _T_2334 @[dec_tlu_ctl.scala 2488:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2335 @[dec_tlu_ctl.scala 2488:30] + reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] + _T_2336 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2489:62] + io.dec_tlu_exc_cause_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2489:30] + reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] + _T_2337 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2490:62] + io.dec_tlu_int_valid_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2490:30] + io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2492:24] + node _T_2338 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2498:61] + node _T_2339 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2499:42] + node _T_2340 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2500:40] + node _T_2341 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2501:39] + node _T_2342 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2502:40] + node _T_2343 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2344 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:40] + node _T_2345 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2503:103] + node _T_2346 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:128] + node _T_2347 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] + node _T_2348 = cat(_T_2347, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2349 = cat(UInt<3>("h00"), _T_2345) @[Cat.scala 29:58] + node _T_2350 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2351 = cat(_T_2350, _T_2349) @[Cat.scala 29:58] + node _T_2352 = cat(_T_2351, _T_2348) @[Cat.scala 29:58] + node _T_2353 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:38] + node _T_2354 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2504:70] + node _T_2355 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:96] + node _T_2356 = cat(_T_2354, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2357 = cat(_T_2356, _T_2355) @[Cat.scala 29:58] + node _T_2358 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2505:36] + node _T_2359 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2505:78] + node _T_2360 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2505:102] + node _T_2361 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2505:123] + node _T_2362 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2505:144] + node _T_2363 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2364 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2365 = cat(_T_2364, _T_2363) @[Cat.scala 29:58] + node _T_2366 = cat(_T_2360, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2367 = cat(UInt<1>("h00"), _T_2359) @[Cat.scala 29:58] + node _T_2368 = cat(_T_2367, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2369 = cat(_T_2368, _T_2366) @[Cat.scala 29:58] + node _T_2370 = cat(_T_2369, _T_2365) @[Cat.scala 29:58] + node _T_2371 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2506:36] + node _T_2372 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2506:75] + node _T_2373 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2506:96] + node _T_2374 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2506:114] + node _T_2375 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2506:132] + node _T_2376 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2377 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2378 = cat(_T_2377, _T_2376) @[Cat.scala 29:58] + node _T_2379 = cat(_T_2373, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2380 = cat(UInt<1>("h00"), _T_2372) @[Cat.scala 29:58] + node _T_2381 = cat(_T_2380, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2382 = cat(_T_2381, _T_2379) @[Cat.scala 29:58] + node _T_2383 = cat(_T_2382, _T_2378) @[Cat.scala 29:58] + node _T_2384 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2507:40] + node _T_2385 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2507:65] + node _T_2386 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2508:40] + node _T_2387 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2508:69] + node _T_2388 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2509:42] + node _T_2389 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2509:72] + node _T_2390 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2510:42] + node _T_2391 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2510:72] + node _T_2392 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2511:41] + node _T_2393 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2511:66] + node _T_2394 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2512:37] + node _T_2395 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2396 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2513:39] + node _T_2397 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2513:64] + node _T_2398 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2514:40] + node _T_2399 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2514:80] + node _T_2400 = cat(UInt<28>("h00"), _T_2399) @[Cat.scala 29:58] + node _T_2401 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2515:38] + node _T_2402 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2515:63] + node _T_2403 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2516:37] + node _T_2404 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2516:62] + node _T_2405 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2517:39] + node _T_2406 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2517:64] + node _T_2407 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2518:38] + node _T_2408 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2409 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2519:39] + node _T_2410 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2411 = cat(_T_2410, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2412 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] + node _T_2413 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] + node _T_2414 = cat(UInt<28>("h00"), _T_2413) @[Cat.scala 29:58] + node _T_2415 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] + node _T_2416 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] + node _T_2417 = cat(UInt<28>("h00"), _T_2416) @[Cat.scala 29:58] + node _T_2418 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2522:38] + node _T_2419 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2522:78] + node _T_2420 = cat(UInt<28>("h00"), _T_2419) @[Cat.scala 29:58] + node _T_2421 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2523:37] + node _T_2422 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2523:77] + node _T_2423 = cat(UInt<23>("h00"), _T_2422) @[Cat.scala 29:58] + node _T_2424 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2524:37] + node _T_2425 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2524:77] + node _T_2426 = cat(UInt<13>("h00"), _T_2425) @[Cat.scala 29:58] + node _T_2427 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2525:37] + node _T_2428 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2525:85] + node _T_2429 = cat(UInt<16>("h04000"), _T_2428) @[Cat.scala 29:58] + node _T_2430 = cat(_T_2429, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2431 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2526:36] + node _T_2432 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2433 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2527:39] + node _T_2434 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2527:64] + node _T_2435 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2528:40] + node _T_2436 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2528:65] + node _T_2437 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2529:39] + node _T_2438 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2529:64] + node _T_2439 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2530:41] + node _T_2440 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2530:80] + node _T_2441 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2530:104] + node _T_2442 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2530:131] + node _T_2443 = cat(UInt<3>("h00"), _T_2442) @[Cat.scala 29:58] + node _T_2444 = cat(_T_2443, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2445 = cat(UInt<2>("h00"), _T_2441) @[Cat.scala 29:58] + node _T_2446 = cat(UInt<7>("h00"), _T_2440) @[Cat.scala 29:58] + node _T_2447 = cat(_T_2446, _T_2445) @[Cat.scala 29:58] + node _T_2448 = cat(_T_2447, _T_2444) @[Cat.scala 29:58] + node _T_2449 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2531:38] + node _T_2450 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2531:78] + node _T_2451 = cat(UInt<30>("h00"), _T_2450) @[Cat.scala 29:58] + node _T_2452 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2532:40] + node _T_2453 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] + node _T_2454 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2533:40] + node _T_2455 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] + node _T_2456 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2534:39] + node _T_2457 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2534:64] + node _T_2458 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] + node _T_2459 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] + node _T_2460 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] + node _T_2461 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] + node _T_2462 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2537:39] + node _T_2463 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2537:64] + node _T_2464 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2538:39] + node _T_2465 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2538:64] + node _T_2466 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2539:39] + node _T_2467 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2539:64] + node _T_2468 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2540:39] + node _T_2469 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2540:64] + node _T_2470 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2541:40] + node _T_2471 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2541:65] + node _T_2472 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2542:40] + node _T_2473 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2542:65] + node _T_2474 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2543:40] + node _T_2475 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2543:65] + node _T_2476 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2544:40] + node _T_2477 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2544:65] + node _T_2478 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2545:38] + node _T_2479 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2545:78] + node _T_2480 = cat(UInt<26>("h00"), _T_2479) @[Cat.scala 29:58] + node _T_2481 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2546:38] + node _T_2482 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2546:78] + node _T_2483 = cat(UInt<30>("h00"), _T_2482) @[Cat.scala 29:58] + node _T_2484 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2547:39] + node _T_2485 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2547:79] + node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58] + node _T_2487 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2548:39] + node _T_2488 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2548:79] + node _T_2489 = cat(UInt<22>("h00"), _T_2488) @[Cat.scala 29:58] + node _T_2490 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2549:39] + node _T_2491 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2549:78] + node _T_2492 = cat(UInt<22>("h00"), _T_2491) @[Cat.scala 29:58] + node _T_2493 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2550:39] + node _T_2494 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2550:78] + node _T_2495 = cat(UInt<22>("h00"), _T_2494) @[Cat.scala 29:58] + node _T_2496 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2551:46] + node _T_2497 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2551:86] + node _T_2498 = cat(UInt<25>("h00"), _T_2497) @[Cat.scala 29:58] + node _T_2499 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2552:37] + node _T_2500 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2501 = cat(_T_2500, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2502 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2553:37] + node _T_2503 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2553:76] + node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2341, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2358, _T_2370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2371, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2390, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2398, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2401, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2403, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2405, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2407, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2418, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2421, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2424, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2427, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2431, _T_2432, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2433, _T_2434, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2435, _T_2436, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2437, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2439, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2449, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2470, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2472, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2474, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2476, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2553 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2554 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2555 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2556 = mux(_T_2493, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2557 = mux(_T_2496, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2558 = mux(_T_2499, _T_2501, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2559 = mux(_T_2502, _T_2503, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2560 = or(_T_2504, _T_2505) @[Mux.scala 27:72] + node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72] @@ -76176,1691 +76176,1690 @@ circuit quasar_wrapper : node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72] node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72] node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72] - node _T_2615 = or(_T_2614, _T_2560) @[Mux.scala 27:72] - wire _T_2616 : UInt @[Mux.scala 27:72] - _T_2616 <= _T_2615 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2616 @[dec_tlu_ctl.scala 2496:21] + wire _T_2615 : UInt @[Mux.scala 27:72] + _T_2615 <= _T_2614 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2615 @[dec_tlu_ctl.scala 2497:21] module dec_decode_csr_read : input clock : Clock input reset : AsyncReset output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} - node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2568:198] - node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2568:198] - node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2568:198] - node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2570:57] - node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2568:198] - node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2568:198] - node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2571:57] - node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2568:198] - node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2568:198] - node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2572:57] - node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2568:198] - node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2568:198] - node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2573:57] - node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2568:198] - node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2574:57] - node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2568:198] - node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2568:198] - node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2568:198] - node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2575:57] - node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2568:198] - node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2568:198] - node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2568:198] - node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2576:57] - node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2568:198] - node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2577:65] - node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2568:198] - node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2568:198] - node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2568:198] - node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2578:65] - node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2568:198] - node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2568:198] - node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2568:198] - node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2568:198] - node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2579:57] - node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2568:198] - node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2568:198] - node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2568:198] - node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2568:198] - node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2568:198] - node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2580:57] - node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2568:198] - node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2568:198] - node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2568:198] - node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2568:198] - node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2568:198] - node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2581:57] - node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2568:198] - node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2568:198] - node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2568:198] - node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2568:198] - node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2568:198] - node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2582:57] - node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2568:198] - node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2568:198] - node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2568:198] - node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2583:57] - node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2568:198] - node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2568:198] - node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2584:57] - node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2568:198] - node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2568:198] - node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2585:57] - node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2568:198] - node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2586:57] - node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2568:198] - node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2568:198] - node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2587:57] - node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2568:198] - node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2568:198] - node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2568:198] - node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2568:198] - node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2588:57] - node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2568:198] - node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2568:198] - node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2568:198] - node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2589:57] - node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2568:198] - node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2568:198] - node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2590:57] - node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2568:198] - node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2591:57] - node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2568:198] - node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2568:198] - node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2568:198] - node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2568:198] - node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2592:57] - node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2568:198] - node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2568:198] - node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2593:57] - node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2568:198] - node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2594:57] - node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2568:198] - node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2568:198] - node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2595:57] - node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2568:198] - node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2568:198] - node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2568:198] - node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2596:57] - node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2568:198] - node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2568:198] - node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2597:57] - node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2568:198] - node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2568:198] - node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2568:198] - node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2598:57] - node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2568:198] - node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2568:198] - node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2568:198] - node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2599:65] - node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2568:198] - node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2568:198] - node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2568:198] - node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2600:57] - node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2568:198] - node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2568:198] - node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2601:57] - node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2568:198] - node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2568:198] - node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2602:57] - node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2568:198] - node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2568:198] - node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2568:198] - node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2568:198] - node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2603:57] - node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2568:198] - node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2568:198] - node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2568:198] - node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2568:198] - node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2568:198] - node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2604:57] - node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2568:198] - node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2568:198] - node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2568:198] - node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2568:198] - node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2605:57] - node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2568:198] - node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2568:198] - node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2568:198] - node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2568:198] - node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2568:198] - node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2606:57] - node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2568:198] - node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2568:198] - node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2568:198] - node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2568:198] - node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2607:57] - node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2568:198] - node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2568:198] - node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2568:198] - node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2568:198] - node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2568:198] - node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2608:57] - node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2568:198] - node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2568:198] - node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2568:198] - node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2568:198] - node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2609:57] - node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2568:198] - node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2568:198] - node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2568:198] - node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2568:198] - node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2568:198] - node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2610:57] - node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2568:198] - node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2568:198] - node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2568:198] - node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2568:198] - node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2611:57] - node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2568:198] - node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2568:198] - node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2568:198] - node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2568:198] - node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2612:57] - node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2568:198] - node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2568:198] - node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2568:198] - node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2568:198] - node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2613:57] - node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2568:198] - node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2568:198] - node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2568:198] - node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2568:198] - node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2614:57] - node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2568:198] - node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2568:198] - node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2568:198] - node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2568:198] - node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2615:49] - node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2568:198] - node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2568:198] - node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2568:198] - node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2616:57] - node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2568:198] - node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2568:198] - node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2568:198] - node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2617:57] - node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2568:198] - node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2568:198] - node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2568:198] - node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2618:57] - node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2568:198] - node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2568:198] - node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2568:198] - node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2619:57] - node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2568:198] - node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2568:198] - node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2568:198] - node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2620:57] - node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2568:198] - node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2568:198] - node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2621:57] - node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2568:198] - node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2568:198] - node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2568:198] - node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2622:57] - node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2568:198] - node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2568:198] - node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2568:198] - node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2568:198] - node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2623:57] - node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2568:198] - node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2568:198] - node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2624:57] - node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2568:198] - node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2568:198] - node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2625:57] - node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2568:198] - node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2568:198] - node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2568:198] - node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2626:57] - node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2568:198] - node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2568:198] - node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2627:57] - node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2568:198] - node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2568:198] - node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2628:57] - node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2568:198] - node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2568:198] - node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2568:198] - node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2629:57] - node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2568:198] - node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2568:198] - node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2630:57] - node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2568:198] - node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2568:198] - node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2568:198] - node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2568:198] - node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2631:57] - node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2568:198] - node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2568:198] - node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2632:57] - node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2568:198] - node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2568:198] - node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2568:198] - node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2633:57] - node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2568:198] - node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2568:198] - node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2568:198] - node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2634:57] - node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2568:198] - node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2568:198] - node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2568:198] - node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2568:198] - io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2635:57] - node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2568:198] - node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2568:198] - node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2568:198] - node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2568:198] - node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2568:198] - node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2568:198] - node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2568:198] - node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2568:198] - node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2568:198] - node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2636:81] - node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2568:198] - node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2568:198] - node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2568:198] - node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2568:198] - node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2568:198] - node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2636:121] - node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2568:198] - node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2568:198] - node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2568:198] - node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2568:198] - node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2636:155] - node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2568:198] - node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2568:198] - node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2568:198] - node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2568:198] - node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2637:97] - node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2568:198] - node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2568:198] - node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2568:198] - node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2568:198] - node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2568:198] - node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2637:137] - io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2636:34] - node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2568:198] - node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2568:198] - node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2568:198] - node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2568:198] - node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2568:198] - node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2568:198] - node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2568:198] - node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2568:198] - node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2638:81] - node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2568:198] - node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2568:198] - node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2568:198] - node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2638:121] - node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2568:198] - node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2568:198] - node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2568:198] - node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2638:162] - node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2568:198] - node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2568:198] - node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2568:198] - node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2568:198] - node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2568:198] - node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2568:198] - node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2639:105] - node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2568:198] - node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2568:198] - node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2568:198] - node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2568:198] - node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2568:198] - node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2639:145] - node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2568:198] - node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2568:198] - node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2568:198] - node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2568:198] - node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2639:178] - io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2638:30] - node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2568:198] - node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2568:198] - node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2568:198] - node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2568:198] - node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2568:198] - node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2568:198] - node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2568:198] - node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2568:198] - node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2568:198] - node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2568:198] - node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2568:198] - node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2568:198] - node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2568:198] - node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2568:198] - node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2568:198] - node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2568:198] - node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2568:198] - node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2568:198] - node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2568:198] - node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2641:81] - node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2568:198] - node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2568:198] - node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2568:198] - node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2568:198] - node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2568:198] - node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2568:198] - node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2568:198] - node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2568:198] - node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2641:129] - node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2568:198] - node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2568:198] - node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2568:198] - node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2568:198] - node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2568:198] - node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2568:198] - node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2568:198] - node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2568:198] - node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2568:198] - node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2642:105] - node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2568:198] - node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2568:198] - node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2568:198] - node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2568:198] - node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2568:198] - node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2568:198] - node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2642:153] - node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2568:198] - node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2568:198] - node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2568:198] - node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2568:198] - node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2568:198] - node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2568:198] - node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2568:198] - node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2568:198] - node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2568:198] - node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2568:198] - node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2568:198] - node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2643:105] - node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2568:198] - node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2568:198] - node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2568:198] - node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2568:198] - node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2568:198] - node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2568:198] - node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2568:198] - node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2568:198] - node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2568:198] - node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2643:153] - node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2568:198] - node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2568:198] - node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2568:198] - node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2568:198] - node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2568:198] - node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2568:198] - node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2568:198] - node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2568:198] - node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2568:198] - node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2644:105] - node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2568:198] - node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2568:198] - node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2568:198] - node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2568:198] - node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2568:198] - node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2568:198] - node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2568:198] - node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2568:198] - node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2568:198] - node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2644:161] - node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2568:198] - node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2568:198] - node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2568:198] - node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2568:198] - node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2568:198] - node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2568:198] - node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2568:198] - node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2645:105] - node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2568:198] - node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2568:198] - node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2568:198] - node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2568:198] - node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2568:198] - node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2568:198] - node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2568:198] - node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2568:198] - node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2568:198] - node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2568:198] - node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2645:161] - node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2568:198] - node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2568:198] - node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2568:198] - node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2568:198] - node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2568:198] - node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2568:198] - node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2568:198] - node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2568:198] - node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2568:198] - node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2646:97] - node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2568:198] - node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2568:198] - node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2568:198] - node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2568:198] - node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2568:198] - node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2568:198] - node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2568:198] - node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2568:198] - node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2568:198] - node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2646:153] - node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2568:198] - node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2568:198] - node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2568:198] - node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2568:198] - node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2568:198] - node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2568:198] - node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2568:198] - node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2568:198] - node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2568:198] - node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2647:105] - node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:106] - node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2568:198] - node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2568:198] - node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2568:198] - node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2568:198] - node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2568:198] - node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2568:198] - node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2568:198] - node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2568:198] - node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2647:161] - node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2568:198] - node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2568:198] - node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2568:198] - node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2568:198] - node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2568:198] - node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2568:198] - node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2568:198] - node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2568:198] - node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2648:105] - node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2568:198] - node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2568:198] - node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2568:198] - node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2568:198] - node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2568:198] - node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2568:198] - node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2568:198] - node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2568:198] - node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2568:198] - node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2648:161] - node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:106] - node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2568:198] - node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2568:198] - node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2568:198] - node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2568:198] - node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2568:198] - node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2568:198] - node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2649:105] - node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2568:198] - node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2568:198] - node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2568:198] - node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2568:198] - node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2568:198] - node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2568:198] - node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2568:198] - node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2568:198] - node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2568:198] - node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2649:161] - node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2568:198] - node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2568:198] - node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2568:198] - node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2568:198] - node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2568:198] - node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2568:198] - node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2568:198] - node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2568:198] - node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2650:105] - node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2568:198] - node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2568:198] - node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2568:198] - node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2568:198] - node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2568:198] - node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2568:198] - node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2568:198] - node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2568:198] - node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2568:198] - node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2650:161] - node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:106] - node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:106] - node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2568:198] - node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2568:198] - node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2568:198] - node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2568:198] - node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2568:198] - node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2568:198] - node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2568:198] - node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2568:198] - node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2568:198] - node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2568:198] - node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2651:105] - node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:106] - node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2568:198] - node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2568:198] - node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2568:198] - node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2568:198] - node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2568:198] - node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2568:198] - node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2651:153] - node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:106] - node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2568:149] - node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2568:198] - node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2568:198] - node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2568:198] - node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2568:198] - node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2568:198] - node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2568:198] - node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2568:198] - node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2568:198] - node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2568:198] - node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2652:113] - node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:149] - node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:149] - node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2568:149] - node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2568:185] - node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:165] - node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2568:198] - node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2568:198] - node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2568:198] - node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2568:198] - node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2568:198] - node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2568:198] - node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2568:198] - node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2568:198] - node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2568:198] - node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2652:161] - node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2568:198] - node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2568:198] - node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2568:198] - node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2568:198] - node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2568:198] - node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2568:198] - node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2568:198] - node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2653:97] - node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2568:106] - node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2568:198] - node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2568:198] - node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2568:198] - node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2568:198] - node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2568:198] - node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2568:198] - node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2653:153] - node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:149] - node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2568:149] - node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:106] - node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2568:198] - node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2568:198] - node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2568:198] - node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2568:198] - node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2568:198] - node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2568:198] - node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2568:198] - node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2654:113] - node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2568:106] - node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2568:149] - node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2568:106] - node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2568:106] - node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2568:149] - node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2568:149] - node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2568:129] - node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2568:106] - node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2568:198] - node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2568:198] - node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2568:198] - node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2568:198] - node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2568:198] - node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2568:198] - node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2654:169] - io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2641:26] + node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2569:198] + node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2569:198] + node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2569:198] + node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2571:57] + node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2569:198] + node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2569:198] + node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2572:57] + node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2569:198] + node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2569:198] + node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2573:57] + node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2569:198] + node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2569:198] + node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2574:57] + node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2569:198] + node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2575:57] + node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2569:198] + node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2569:198] + node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2569:198] + node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2576:57] + node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2569:198] + node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2569:198] + node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2569:198] + node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2577:57] + node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2569:198] + node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2578:65] + node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2569:198] + node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2569:198] + node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2569:198] + node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2579:65] + node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2569:198] + node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2569:198] + node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2569:198] + node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2569:198] + node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2580:57] + node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2569:198] + node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2569:198] + node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2569:198] + node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2569:198] + node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2569:198] + node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2581:57] + node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2569:198] + node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2569:198] + node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2569:198] + node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2569:198] + node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2569:198] + node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2582:57] + node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2569:198] + node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2569:198] + node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2569:198] + node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2569:198] + node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2569:198] + node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2583:57] + node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2569:198] + node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2569:198] + node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2569:198] + node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2584:57] + node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2569:198] + node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2569:198] + node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2585:57] + node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2569:198] + node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2569:198] + node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2586:57] + node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2569:198] + node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2587:57] + node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2569:198] + node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2569:198] + node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2588:57] + node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2569:198] + node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2569:198] + node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2569:198] + node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2569:198] + node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2589:57] + node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2569:198] + node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2569:198] + node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2569:198] + node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2590:57] + node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2569:198] + node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2569:198] + node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2591:57] + node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2569:198] + node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2592:57] + node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2569:198] + node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2569:198] + node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2569:198] + node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2569:198] + node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2593:57] + node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2569:198] + node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2569:198] + node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2594:57] + node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2569:198] + node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2595:57] + node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2569:198] + node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2569:198] + node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2596:57] + node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2569:198] + node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2569:198] + node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2569:198] + node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2597:57] + node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2569:198] + node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2569:198] + node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2598:57] + node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2569:198] + node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2569:198] + node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2569:198] + node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2599:57] + node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2569:198] + node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2569:198] + node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2569:198] + node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2600:65] + node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2569:198] + node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2569:198] + node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2569:198] + node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2601:57] + node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2569:198] + node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2569:198] + node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2602:57] + node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2569:198] + node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2569:198] + node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2603:57] + node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2569:198] + node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2569:198] + node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2569:198] + node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2569:198] + node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2604:57] + node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2569:198] + node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2569:198] + node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2569:198] + node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2569:198] + node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2569:198] + node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2605:57] + node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2569:198] + node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2569:198] + node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2569:198] + node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2569:198] + node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2606:57] + node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2569:198] + node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2569:198] + node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2569:198] + node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2569:198] + node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2569:198] + node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2607:57] + node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2569:198] + node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2569:198] + node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2569:198] + node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2569:198] + node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2608:57] + node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2569:198] + node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2569:198] + node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2569:198] + node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2569:198] + node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2569:198] + node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2609:57] + node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2569:198] + node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2569:198] + node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2569:198] + node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2569:198] + node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2610:57] + node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2569:198] + node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2569:198] + node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2569:198] + node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2569:198] + node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2569:198] + node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2611:57] + node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2569:198] + node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2569:198] + node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2569:198] + node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2569:198] + node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2612:57] + node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2569:198] + node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2569:198] + node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2569:198] + node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2569:198] + node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2613:57] + node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2569:198] + node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2569:198] + node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2569:198] + node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2569:198] + node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2614:57] + node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2569:198] + node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2569:198] + node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2569:198] + node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2569:198] + node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2615:57] + node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2569:198] + node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2569:198] + node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2569:198] + node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2569:198] + node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2616:49] + node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2569:198] + node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2569:198] + node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2569:198] + node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2617:57] + node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2569:198] + node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2569:198] + node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2569:198] + node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2618:57] + node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2569:198] + node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2569:198] + node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2569:198] + node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2619:57] + node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2569:198] + node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2569:198] + node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2569:198] + node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2620:57] + node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2569:198] + node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2569:198] + node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2569:198] + node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2621:57] + node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2569:198] + node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2569:198] + node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2622:57] + node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2569:198] + node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2569:198] + node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2569:198] + node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2623:57] + node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2569:198] + node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2569:198] + node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2569:198] + node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2569:198] + node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2624:57] + node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2569:198] + node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2569:198] + node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2625:57] + node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2569:198] + node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2569:198] + node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2626:57] + node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2569:198] + node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2569:198] + node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2569:198] + node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2627:57] + node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2569:198] + node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2569:198] + node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2628:57] + node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2569:198] + node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2569:198] + node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2629:57] + node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2569:198] + node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2569:198] + node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2569:198] + node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2630:57] + node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2569:198] + node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2569:198] + node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2631:57] + node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2569:198] + node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2569:198] + node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2569:198] + node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2569:198] + node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2632:57] + node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2569:198] + node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2569:198] + node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2633:57] + node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2569:198] + node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2569:198] + node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2569:198] + node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2634:57] + node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2569:198] + node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2569:198] + node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2569:198] + node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2635:57] + node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2569:198] + node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2569:198] + node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2569:198] + node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2569:198] + io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2636:57] + node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2569:198] + node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2569:198] + node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2569:198] + node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2569:198] + node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2569:198] + node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2569:198] + node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2569:198] + node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2569:198] + node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2569:198] + node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2637:81] + node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2569:198] + node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2569:198] + node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2569:198] + node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2569:198] + node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2569:198] + node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2637:121] + node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2569:198] + node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2569:198] + node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2569:198] + node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2569:198] + node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2637:155] + node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2569:198] + node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2569:198] + node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2569:198] + node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2569:198] + node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2638:97] + node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2569:198] + node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2569:198] + node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2569:198] + node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2569:198] + node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2569:198] + node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2638:137] + io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2637:34] + node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2569:198] + node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2569:198] + node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2569:198] + node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2569:198] + node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2569:198] + node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2569:198] + node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2569:198] + node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2569:198] + node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2639:81] + node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2569:198] + node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2569:198] + node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2569:198] + node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2639:121] + node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2569:198] + node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2569:198] + node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2569:198] + node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2639:162] + node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2569:198] + node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2569:198] + node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2569:198] + node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2569:198] + node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2569:198] + node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2569:198] + node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2640:105] + node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2569:198] + node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2569:198] + node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2569:198] + node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2569:198] + node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2569:198] + node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2640:145] + node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2569:198] + node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2569:198] + node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2569:198] + node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2569:198] + node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2640:178] + io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2639:30] + node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2569:198] + node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2569:198] + node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2569:198] + node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2569:198] + node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2569:198] + node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2569:198] + node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2569:198] + node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2569:198] + node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2569:198] + node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2569:198] + node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2569:198] + node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2569:198] + node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2569:198] + node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2569:198] + node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2569:198] + node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2569:198] + node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2569:198] + node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2569:198] + node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2569:198] + node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2642:81] + node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2569:198] + node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2569:198] + node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2569:198] + node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2569:198] + node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2569:198] + node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2569:198] + node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2569:198] + node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2569:198] + node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2642:129] + node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2569:198] + node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2569:198] + node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2569:198] + node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2569:198] + node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2569:198] + node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2569:198] + node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2569:198] + node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2569:198] + node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2569:198] + node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2643:105] + node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2569:198] + node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2569:198] + node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2569:198] + node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2569:198] + node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2569:198] + node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2569:198] + node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2643:153] + node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2569:198] + node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2569:198] + node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2569:198] + node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2569:198] + node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2569:198] + node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2569:198] + node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2569:198] + node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2569:198] + node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2569:198] + node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2569:198] + node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2569:198] + node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2644:105] + node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2569:198] + node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2569:198] + node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2569:198] + node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2569:198] + node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2569:198] + node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2569:198] + node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2569:198] + node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2569:198] + node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2569:198] + node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2644:153] + node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2569:198] + node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2569:198] + node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2569:198] + node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2569:198] + node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2569:198] + node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2569:198] + node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2569:198] + node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2569:198] + node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2569:198] + node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2645:105] + node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2569:198] + node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2569:198] + node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2569:198] + node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2569:198] + node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2569:198] + node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2569:198] + node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2569:198] + node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2569:198] + node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2569:198] + node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2645:161] + node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2569:198] + node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2569:198] + node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2569:198] + node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2569:198] + node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2569:198] + node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2569:198] + node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2569:198] + node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2646:105] + node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2569:198] + node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2569:198] + node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2569:198] + node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2569:198] + node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2569:198] + node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2569:198] + node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2569:198] + node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2569:198] + node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2569:198] + node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2569:198] + node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2646:161] + node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2569:198] + node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2569:198] + node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2569:198] + node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2569:198] + node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2569:198] + node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2569:198] + node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2569:198] + node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2569:198] + node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2569:198] + node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2647:97] + node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2569:198] + node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2569:198] + node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2569:198] + node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2569:198] + node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2569:198] + node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2569:198] + node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2569:198] + node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2569:198] + node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2569:198] + node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2647:153] + node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2569:198] + node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2569:198] + node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2569:198] + node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2569:198] + node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2569:198] + node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2569:198] + node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2569:198] + node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2569:198] + node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2569:198] + node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2648:105] + node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:106] + node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2569:198] + node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2569:198] + node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2569:198] + node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2569:198] + node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2569:198] + node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2569:198] + node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2569:198] + node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2569:198] + node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2648:161] + node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2569:198] + node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2569:198] + node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2569:198] + node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2569:198] + node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2569:198] + node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2569:198] + node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2569:198] + node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2569:198] + node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2649:105] + node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2569:198] + node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2569:198] + node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2569:198] + node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2569:198] + node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2569:198] + node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2569:198] + node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2569:198] + node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2569:198] + node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2569:198] + node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2649:161] + node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:106] + node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2569:198] + node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2569:198] + node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2569:198] + node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2569:198] + node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2569:198] + node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2569:198] + node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2650:105] + node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2569:198] + node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2569:198] + node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2569:198] + node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2569:198] + node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2569:198] + node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2569:198] + node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2569:198] + node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2569:198] + node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2569:198] + node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2650:161] + node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2569:198] + node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2569:198] + node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2569:198] + node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2569:198] + node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2569:198] + node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2569:198] + node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2569:198] + node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2569:198] + node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2651:105] + node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2569:198] + node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2569:198] + node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2569:198] + node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2569:198] + node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2569:198] + node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2569:198] + node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2569:198] + node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2569:198] + node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2569:198] + node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2651:161] + node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:106] + node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:106] + node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2569:198] + node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2569:198] + node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2569:198] + node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2569:198] + node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2569:198] + node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2569:198] + node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2569:198] + node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2569:198] + node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2569:198] + node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2569:198] + node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2652:105] + node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:106] + node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2569:198] + node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2569:198] + node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2569:198] + node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2569:198] + node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2569:198] + node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2569:198] + node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2652:153] + node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:106] + node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2569:149] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2569:198] + node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2569:198] + node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2569:198] + node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2569:198] + node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2569:198] + node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2569:198] + node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2569:198] + node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2569:198] + node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2569:198] + node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2653:113] + node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:149] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:149] + node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2569:149] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2569:185] + node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:165] + node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2569:198] + node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2569:198] + node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2569:198] + node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2569:198] + node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2569:198] + node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2569:198] + node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2569:198] + node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2569:198] + node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2569:198] + node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2653:161] + node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2569:198] + node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2569:198] + node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2569:198] + node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2569:198] + node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2569:198] + node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2569:198] + node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2569:198] + node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2654:97] + node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2569:106] + node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2569:198] + node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2569:198] + node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2569:198] + node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2569:198] + node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2569:198] + node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2569:198] + node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2654:153] + node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:149] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2569:149] + node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:106] + node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2569:198] + node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2569:198] + node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2569:198] + node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2569:198] + node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2569:198] + node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2569:198] + node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2569:198] + node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2655:113] + node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2569:106] + node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2569:149] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2569:106] + node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2569:106] + node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2569:149] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2569:149] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2569:129] + node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2569:106] + node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2569:198] + node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2569:198] + node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2569:198] + node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2569:198] + node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2569:198] + node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2569:198] + node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2655:169] + io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2642:26] module dec_tlu_ctl : input clock : Clock @@ -109221,6 +109220,8 @@ circuit quasar_wrapper : ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 102:25] ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 102:25] ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 102:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 103:42] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 104:43] ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 105:33] ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 106:51] ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 106:51] @@ -109464,347 +109465,346 @@ circuit quasar_wrapper : lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 171:18] lsu.io.scan_mode <= io.scan_mode @[quasar.scala 172:20] lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 173:19] - dbg.reset <= io.core_rst_l @[quasar.scala 176:13] - node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 177:32] - dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 177:26] - node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 178:60] - dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 178:28] - node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 179:60] - dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 179:28] - dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 180:29] - dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 181:29] - dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 182:34] - dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 183:29] - dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 184:21] - dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 185:23] - dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 186:24] - dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 187:24] - dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 188:25] - node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 189:42] - dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 189:20] - dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 190:23] - dbg.io.scan_mode <= io.scan_mode @[quasar.scala 191:20] - dma_ctrl.reset <= io.core_rst_l @[quasar.scala 195:18] - dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 196:24] - dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 197:30] - dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 198:28] - dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 199:25] - dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 200:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 200:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 200:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 200:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 200:23] - dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 201:26] - dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 201:26] - dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 202:28] - dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 203:31] - dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 204:29] - dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 205:30] - dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 206:26] - dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 207:34] - pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 210:30] - pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 211:23] - pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 212:29] - pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 213:31] - pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 214:33] - pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 215:34] - lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 216:28] - pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 216:28] - pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 216:28] - pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 216:28] - pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 216:28] - pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 216:28] - pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 216:28] - dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 217:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 217:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 217:28] - dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 217:28] - dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 217:28] - dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 217:28] - io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 219:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 219:19] - io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 219:19] - io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 219:19] - io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 219:19] - io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 219:19] - io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 219:19] - io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 222:24] - io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 223:23] - io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 224:31] - io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 225:21] - io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 226:24] - io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 227:20] - io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 228:26] - io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 229:25] - io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 230:24] - io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 231:25] - io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 232:23] - io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 233:23] - io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 234:23] - io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 235:23] - io.dmi_reg_rdata <= dbg.io.dmi_reg_rdata @[quasar.scala 236:20] - lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 239:11] - lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 239:11] - io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 239:11] - io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 239:11] - io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 239:11] - io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 239:11] - io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 239:11] - io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 239:11] - io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 239:11] - io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 239:11] - wire _T_12 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 278:42] - _T_12.out.hwdata <= UInt<64>("h00") @[quasar.scala 278:42] - _T_12.out.hwrite <= UInt<1>("h00") @[quasar.scala 278:42] - _T_12.out.htrans <= UInt<2>("h00") @[quasar.scala 278:42] - _T_12.out.hsize <= UInt<3>("h00") @[quasar.scala 278:42] - _T_12.out.hprot <= UInt<4>("h00") @[quasar.scala 278:42] - _T_12.out.hmastlock <= UInt<1>("h00") @[quasar.scala 278:42] - _T_12.out.hburst <= UInt<3>("h00") @[quasar.scala 278:42] - _T_12.out.haddr <= UInt<32>("h00") @[quasar.scala 278:42] - _T_12.in.hresp <= UInt<1>("h00") @[quasar.scala 278:42] - _T_12.in.hready <= UInt<1>("h00") @[quasar.scala 278:42] - _T_12.in.hrdata <= UInt<64>("h00") @[quasar.scala 278:42] - io.lsu_ahb.out.hwdata <= _T_12.out.hwdata @[quasar.scala 278:27] - io.lsu_ahb.out.hwrite <= _T_12.out.hwrite @[quasar.scala 278:27] - io.lsu_ahb.out.htrans <= _T_12.out.htrans @[quasar.scala 278:27] - io.lsu_ahb.out.hsize <= _T_12.out.hsize @[quasar.scala 278:27] - io.lsu_ahb.out.hprot <= _T_12.out.hprot @[quasar.scala 278:27] - io.lsu_ahb.out.hmastlock <= _T_12.out.hmastlock @[quasar.scala 278:27] - io.lsu_ahb.out.hburst <= _T_12.out.hburst @[quasar.scala 278:27] - io.lsu_ahb.out.haddr <= _T_12.out.haddr @[quasar.scala 278:27] - _T_12.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 278:27] - _T_12.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 278:27] - _T_12.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 278:27] - wire _T_13 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 279:42] - _T_13.out.hwdata <= UInt<64>("h00") @[quasar.scala 279:42] - _T_13.out.hwrite <= UInt<1>("h00") @[quasar.scala 279:42] - _T_13.out.htrans <= UInt<2>("h00") @[quasar.scala 279:42] - _T_13.out.hsize <= UInt<3>("h00") @[quasar.scala 279:42] - _T_13.out.hprot <= UInt<4>("h00") @[quasar.scala 279:42] - _T_13.out.hmastlock <= UInt<1>("h00") @[quasar.scala 279:42] - _T_13.out.hburst <= UInt<3>("h00") @[quasar.scala 279:42] - _T_13.out.haddr <= UInt<32>("h00") @[quasar.scala 279:42] - _T_13.in.hresp <= UInt<1>("h00") @[quasar.scala 279:42] - _T_13.in.hready <= UInt<1>("h00") @[quasar.scala 279:42] - _T_13.in.hrdata <= UInt<64>("h00") @[quasar.scala 279:42] - io.ifu_ahb.out.hwdata <= _T_13.out.hwdata @[quasar.scala 279:27] - io.ifu_ahb.out.hwrite <= _T_13.out.hwrite @[quasar.scala 279:27] - io.ifu_ahb.out.htrans <= _T_13.out.htrans @[quasar.scala 279:27] - io.ifu_ahb.out.hsize <= _T_13.out.hsize @[quasar.scala 279:27] - io.ifu_ahb.out.hprot <= _T_13.out.hprot @[quasar.scala 279:27] - io.ifu_ahb.out.hmastlock <= _T_13.out.hmastlock @[quasar.scala 279:27] - io.ifu_ahb.out.hburst <= _T_13.out.hburst @[quasar.scala 279:27] - io.ifu_ahb.out.haddr <= _T_13.out.haddr @[quasar.scala 279:27] - _T_13.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 279:27] - _T_13.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 279:27] - _T_13.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 279:27] - wire _T_14 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 280:42] - _T_14.out.hwdata <= UInt<64>("h00") @[quasar.scala 280:42] - _T_14.out.hwrite <= UInt<1>("h00") @[quasar.scala 280:42] - _T_14.out.htrans <= UInt<2>("h00") @[quasar.scala 280:42] - _T_14.out.hsize <= UInt<3>("h00") @[quasar.scala 280:42] - _T_14.out.hprot <= UInt<4>("h00") @[quasar.scala 280:42] - _T_14.out.hmastlock <= UInt<1>("h00") @[quasar.scala 280:42] - _T_14.out.hburst <= UInt<3>("h00") @[quasar.scala 280:42] - _T_14.out.haddr <= UInt<32>("h00") @[quasar.scala 280:42] - _T_14.in.hresp <= UInt<1>("h00") @[quasar.scala 280:42] - _T_14.in.hready <= UInt<1>("h00") @[quasar.scala 280:42] - _T_14.in.hrdata <= UInt<64>("h00") @[quasar.scala 280:42] - io.sb_ahb.out.hwdata <= _T_14.out.hwdata @[quasar.scala 280:27] - io.sb_ahb.out.hwrite <= _T_14.out.hwrite @[quasar.scala 280:27] - io.sb_ahb.out.htrans <= _T_14.out.htrans @[quasar.scala 280:27] - io.sb_ahb.out.hsize <= _T_14.out.hsize @[quasar.scala 280:27] - io.sb_ahb.out.hprot <= _T_14.out.hprot @[quasar.scala 280:27] - io.sb_ahb.out.hmastlock <= _T_14.out.hmastlock @[quasar.scala 280:27] - io.sb_ahb.out.hburst <= _T_14.out.hburst @[quasar.scala 280:27] - io.sb_ahb.out.haddr <= _T_14.out.haddr @[quasar.scala 280:27] - _T_14.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 280:27] - _T_14.in.hready <= io.sb_ahb.in.hready @[quasar.scala 280:27] - _T_14.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 280:27] - wire _T_15 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar.scala 281:42] - _T_15.hreadyin <= UInt<1>("h00") @[quasar.scala 281:42] - _T_15.hsel <= UInt<1>("h00") @[quasar.scala 281:42] - _T_15.sig.out.hwdata <= UInt<64>("h00") @[quasar.scala 281:42] - _T_15.sig.out.hwrite <= UInt<1>("h00") @[quasar.scala 281:42] - _T_15.sig.out.htrans <= UInt<2>("h00") @[quasar.scala 281:42] - _T_15.sig.out.hsize <= UInt<3>("h00") @[quasar.scala 281:42] - _T_15.sig.out.hprot <= UInt<4>("h00") @[quasar.scala 281:42] - _T_15.sig.out.hmastlock <= UInt<1>("h00") @[quasar.scala 281:42] - _T_15.sig.out.hburst <= UInt<3>("h00") @[quasar.scala 281:42] - _T_15.sig.out.haddr <= UInt<32>("h00") @[quasar.scala 281:42] - _T_15.sig.in.hresp <= UInt<1>("h00") @[quasar.scala 281:42] - _T_15.sig.in.hready <= UInt<1>("h00") @[quasar.scala 281:42] - _T_15.sig.in.hrdata <= UInt<64>("h00") @[quasar.scala 281:42] - _T_15.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 281:27] - _T_15.hsel <= io.dma_ahb.hsel @[quasar.scala 281:27] - _T_15.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 281:27] - _T_15.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 281:27] - _T_15.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 281:27] - _T_15.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 281:27] - _T_15.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 281:27] - _T_15.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 281:27] - _T_15.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 281:27] - _T_15.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 281:27] - io.dma_ahb.sig.in.hresp <= _T_15.sig.in.hresp @[quasar.scala 281:27] - io.dma_ahb.sig.in.hready <= _T_15.sig.in.hready @[quasar.scala 281:27] - io.dma_ahb.sig.in.hrdata <= _T_15.sig.in.hrdata @[quasar.scala 281:27] - io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 282:27] - io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 282:27] - io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 282:27] - io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 282:27] - io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 282:27] - io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 282:27] - io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 282:27] - io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 282:27] - io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 282:27] - io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 282:27] - dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 282:27] - io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 282:27] - dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 283:27] - dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 283:27] - dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 283:27] - dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 283:27] - dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 283:27] - io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 283:27] - io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 283:27] - io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 283:27] - io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 283:27] - io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 283:27] - io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 283:27] - io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 283:27] - io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 283:27] - io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 283:27] - io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 283:27] - io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 283:27] - io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 283:27] - dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 283:27] - dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 283:27] - dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 283:27] - dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 283:27] - io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 283:27] - io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 283:27] - io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 283:27] - io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 283:27] - io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 283:27] - dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 283:27] - io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 283:27] - io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 283:27] - io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 283:27] - io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 283:27] - io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 283:27] - io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 283:27] - io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 283:27] - io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 283:27] - io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 283:27] - io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 283:27] - io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 283:27] - dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 283:27] - ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 284:27] - ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 284:27] - ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 284:27] - ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 284:27] - ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 284:27] - io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 284:27] - io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 284:27] - io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 284:27] - io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 284:27] - io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 284:27] - io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 284:27] - io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 284:27] - io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 284:27] - io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 284:27] - io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 284:27] - io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 284:27] - io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 284:27] - ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 284:27] - ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 284:27] - ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 284:27] - ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 284:27] - io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 284:27] - io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 284:27] - io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 284:27] - io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 284:27] - io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 284:27] - ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 284:27] - io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 284:27] - io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 284:27] - io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 284:27] - io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 284:27] - io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 284:27] - io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 284:27] - io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 284:27] - io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 284:27] - io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 284:27] - io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 284:27] - io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 284:27] - ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 284:27] - lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 285:27] - lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 285:27] - lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 285:27] - lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 285:27] - lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 285:27] - io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 285:27] - io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 285:27] - io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 285:27] - io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 285:27] - io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 285:27] - io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 285:27] - io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 285:27] - io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 285:27] - io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 285:27] - io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 285:27] - io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 285:27] - io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 285:27] - lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 285:27] - lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 285:27] - lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 285:27] - lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 285:27] - io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 285:27] - io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 285:27] - io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 285:27] - io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 285:27] - io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 285:27] - lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 285:27] - io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 285:27] - io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 285:27] - io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 285:27] - io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 285:27] - io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 285:27] - io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 285:27] - io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 285:27] - io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 285:27] - io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 285:27] - io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 285:27] - io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 285:27] - lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 285:27] + node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 176:32] + dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 176:26] + node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 177:60] + dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 177:28] + node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 178:60] + dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 178:28] + dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 179:29] + dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 180:29] + dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 181:34] + dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 182:29] + dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 183:21] + dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 184:23] + dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 185:24] + dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 186:24] + dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 187:25] + node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 188:42] + dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 188:20] + dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 189:23] + dbg.io.scan_mode <= io.scan_mode @[quasar.scala 190:20] + dma_ctrl.reset <= io.core_rst_l @[quasar.scala 194:18] + dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 195:24] + dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 196:30] + dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 197:28] + dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 198:25] + dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 199:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 199:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 199:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 199:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 199:23] + dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 200:26] + dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 200:26] + dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 201:28] + dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 202:31] + dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 203:29] + dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 204:30] + dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 205:26] + dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 206:34] + pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 209:30] + pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 210:23] + pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 211:29] + pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 212:31] + pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 213:33] + pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 214:34] + lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 215:28] + pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 215:28] + pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 215:28] + pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 215:28] + pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 215:28] + pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 215:28] + pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 215:28] + dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 216:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 216:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 216:28] + dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 216:28] + dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 216:28] + dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 216:28] + io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 218:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 218:19] + io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 218:19] + io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 218:19] + io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 218:19] + io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 218:19] + io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 218:19] + io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 221:24] + io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 222:23] + io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 223:31] + io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 224:21] + io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 225:24] + io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 226:20] + io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 227:26] + io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 228:25] + io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 229:24] + io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 230:25] + io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 231:23] + io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 232:23] + io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 233:23] + io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 234:23] + io.dmi_reg_rdata <= dbg.io.dmi_reg_rdata @[quasar.scala 235:20] + lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 238:11] + lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 238:11] + io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 238:11] + io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 238:11] + io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 238:11] + io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 238:11] + io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 238:11] + io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 238:11] + io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 238:11] + io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 238:11] + wire _T_12 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 277:42] + _T_12.out.hwdata <= UInt<64>("h00") @[quasar.scala 277:42] + _T_12.out.hwrite <= UInt<1>("h00") @[quasar.scala 277:42] + _T_12.out.htrans <= UInt<2>("h00") @[quasar.scala 277:42] + _T_12.out.hsize <= UInt<3>("h00") @[quasar.scala 277:42] + _T_12.out.hprot <= UInt<4>("h00") @[quasar.scala 277:42] + _T_12.out.hmastlock <= UInt<1>("h00") @[quasar.scala 277:42] + _T_12.out.hburst <= UInt<3>("h00") @[quasar.scala 277:42] + _T_12.out.haddr <= UInt<32>("h00") @[quasar.scala 277:42] + _T_12.in.hresp <= UInt<1>("h00") @[quasar.scala 277:42] + _T_12.in.hready <= UInt<1>("h00") @[quasar.scala 277:42] + _T_12.in.hrdata <= UInt<64>("h00") @[quasar.scala 277:42] + io.lsu_ahb.out.hwdata <= _T_12.out.hwdata @[quasar.scala 277:27] + io.lsu_ahb.out.hwrite <= _T_12.out.hwrite @[quasar.scala 277:27] + io.lsu_ahb.out.htrans <= _T_12.out.htrans @[quasar.scala 277:27] + io.lsu_ahb.out.hsize <= _T_12.out.hsize @[quasar.scala 277:27] + io.lsu_ahb.out.hprot <= _T_12.out.hprot @[quasar.scala 277:27] + io.lsu_ahb.out.hmastlock <= _T_12.out.hmastlock @[quasar.scala 277:27] + io.lsu_ahb.out.hburst <= _T_12.out.hburst @[quasar.scala 277:27] + io.lsu_ahb.out.haddr <= _T_12.out.haddr @[quasar.scala 277:27] + _T_12.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 277:27] + _T_12.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 277:27] + _T_12.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 277:27] + wire _T_13 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 278:42] + _T_13.out.hwdata <= UInt<64>("h00") @[quasar.scala 278:42] + _T_13.out.hwrite <= UInt<1>("h00") @[quasar.scala 278:42] + _T_13.out.htrans <= UInt<2>("h00") @[quasar.scala 278:42] + _T_13.out.hsize <= UInt<3>("h00") @[quasar.scala 278:42] + _T_13.out.hprot <= UInt<4>("h00") @[quasar.scala 278:42] + _T_13.out.hmastlock <= UInt<1>("h00") @[quasar.scala 278:42] + _T_13.out.hburst <= UInt<3>("h00") @[quasar.scala 278:42] + _T_13.out.haddr <= UInt<32>("h00") @[quasar.scala 278:42] + _T_13.in.hresp <= UInt<1>("h00") @[quasar.scala 278:42] + _T_13.in.hready <= UInt<1>("h00") @[quasar.scala 278:42] + _T_13.in.hrdata <= UInt<64>("h00") @[quasar.scala 278:42] + io.ifu_ahb.out.hwdata <= _T_13.out.hwdata @[quasar.scala 278:27] + io.ifu_ahb.out.hwrite <= _T_13.out.hwrite @[quasar.scala 278:27] + io.ifu_ahb.out.htrans <= _T_13.out.htrans @[quasar.scala 278:27] + io.ifu_ahb.out.hsize <= _T_13.out.hsize @[quasar.scala 278:27] + io.ifu_ahb.out.hprot <= _T_13.out.hprot @[quasar.scala 278:27] + io.ifu_ahb.out.hmastlock <= _T_13.out.hmastlock @[quasar.scala 278:27] + io.ifu_ahb.out.hburst <= _T_13.out.hburst @[quasar.scala 278:27] + io.ifu_ahb.out.haddr <= _T_13.out.haddr @[quasar.scala 278:27] + _T_13.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 278:27] + _T_13.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 278:27] + _T_13.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 278:27] + wire _T_14 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 279:42] + _T_14.out.hwdata <= UInt<64>("h00") @[quasar.scala 279:42] + _T_14.out.hwrite <= UInt<1>("h00") @[quasar.scala 279:42] + _T_14.out.htrans <= UInt<2>("h00") @[quasar.scala 279:42] + _T_14.out.hsize <= UInt<3>("h00") @[quasar.scala 279:42] + _T_14.out.hprot <= UInt<4>("h00") @[quasar.scala 279:42] + _T_14.out.hmastlock <= UInt<1>("h00") @[quasar.scala 279:42] + _T_14.out.hburst <= UInt<3>("h00") @[quasar.scala 279:42] + _T_14.out.haddr <= UInt<32>("h00") @[quasar.scala 279:42] + _T_14.in.hresp <= UInt<1>("h00") @[quasar.scala 279:42] + _T_14.in.hready <= UInt<1>("h00") @[quasar.scala 279:42] + _T_14.in.hrdata <= UInt<64>("h00") @[quasar.scala 279:42] + io.sb_ahb.out.hwdata <= _T_14.out.hwdata @[quasar.scala 279:27] + io.sb_ahb.out.hwrite <= _T_14.out.hwrite @[quasar.scala 279:27] + io.sb_ahb.out.htrans <= _T_14.out.htrans @[quasar.scala 279:27] + io.sb_ahb.out.hsize <= _T_14.out.hsize @[quasar.scala 279:27] + io.sb_ahb.out.hprot <= _T_14.out.hprot @[quasar.scala 279:27] + io.sb_ahb.out.hmastlock <= _T_14.out.hmastlock @[quasar.scala 279:27] + io.sb_ahb.out.hburst <= _T_14.out.hburst @[quasar.scala 279:27] + io.sb_ahb.out.haddr <= _T_14.out.haddr @[quasar.scala 279:27] + _T_14.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 279:27] + _T_14.in.hready <= io.sb_ahb.in.hready @[quasar.scala 279:27] + _T_14.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 279:27] + wire _T_15 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar.scala 280:42] + _T_15.hreadyin <= UInt<1>("h00") @[quasar.scala 280:42] + _T_15.hsel <= UInt<1>("h00") @[quasar.scala 280:42] + _T_15.sig.out.hwdata <= UInt<64>("h00") @[quasar.scala 280:42] + _T_15.sig.out.hwrite <= UInt<1>("h00") @[quasar.scala 280:42] + _T_15.sig.out.htrans <= UInt<2>("h00") @[quasar.scala 280:42] + _T_15.sig.out.hsize <= UInt<3>("h00") @[quasar.scala 280:42] + _T_15.sig.out.hprot <= UInt<4>("h00") @[quasar.scala 280:42] + _T_15.sig.out.hmastlock <= UInt<1>("h00") @[quasar.scala 280:42] + _T_15.sig.out.hburst <= UInt<3>("h00") @[quasar.scala 280:42] + _T_15.sig.out.haddr <= UInt<32>("h00") @[quasar.scala 280:42] + _T_15.sig.in.hresp <= UInt<1>("h00") @[quasar.scala 280:42] + _T_15.sig.in.hready <= UInt<1>("h00") @[quasar.scala 280:42] + _T_15.sig.in.hrdata <= UInt<64>("h00") @[quasar.scala 280:42] + _T_15.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 280:27] + _T_15.hsel <= io.dma_ahb.hsel @[quasar.scala 280:27] + _T_15.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 280:27] + _T_15.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 280:27] + _T_15.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 280:27] + _T_15.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 280:27] + _T_15.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 280:27] + _T_15.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 280:27] + _T_15.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 280:27] + _T_15.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 280:27] + io.dma_ahb.sig.in.hresp <= _T_15.sig.in.hresp @[quasar.scala 280:27] + io.dma_ahb.sig.in.hready <= _T_15.sig.in.hready @[quasar.scala 280:27] + io.dma_ahb.sig.in.hrdata <= _T_15.sig.in.hrdata @[quasar.scala 280:27] + io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 281:27] + io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 281:27] + io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 281:27] + io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 281:27] + io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 281:27] + io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 281:27] + io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 281:27] + io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 281:27] + io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 281:27] + io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 281:27] + dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 281:27] + io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 281:27] + dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 282:27] + dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 282:27] + dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 282:27] + dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 282:27] + dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 282:27] + io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 282:27] + io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 282:27] + io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 282:27] + io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 282:27] + io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 282:27] + io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 282:27] + io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 282:27] + io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 282:27] + io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 282:27] + io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 282:27] + io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 282:27] + io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 282:27] + dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 282:27] + dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 282:27] + dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 282:27] + dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 282:27] + io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 282:27] + io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 282:27] + io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 282:27] + io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 282:27] + io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 282:27] + dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 282:27] + io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 282:27] + io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 282:27] + io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 282:27] + io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 282:27] + io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 282:27] + io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 282:27] + io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 282:27] + io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 282:27] + io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 282:27] + io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 282:27] + io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 282:27] + dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 282:27] + ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 283:27] + ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 283:27] + ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 283:27] + ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 283:27] + ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 283:27] + io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 283:27] + io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 283:27] + io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 283:27] + io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 283:27] + io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 283:27] + io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 283:27] + io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 283:27] + io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 283:27] + io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 283:27] + io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 283:27] + io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 283:27] + io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 283:27] + ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 283:27] + ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 283:27] + ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 283:27] + ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 283:27] + io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 283:27] + io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 283:27] + io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 283:27] + io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 283:27] + io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 283:27] + ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 283:27] + io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 283:27] + io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 283:27] + io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 283:27] + io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 283:27] + io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 283:27] + io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 283:27] + io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 283:27] + io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 283:27] + io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 283:27] + io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 283:27] + io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 283:27] + ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 283:27] + lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 284:27] + lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 284:27] + lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 284:27] + lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 284:27] + lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 284:27] + io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 284:27] + io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 284:27] + io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 284:27] + io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 284:27] + io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 284:27] + io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 284:27] + io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 284:27] + io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 284:27] + io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 284:27] + io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 284:27] + io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 284:27] + io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 284:27] + lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 284:27] + lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 284:27] + lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 284:27] + lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 284:27] + io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 284:27] + io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 284:27] + io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 284:27] + io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 284:27] + io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 284:27] + lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 284:27] + io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 284:27] + io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 284:27] + io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 284:27] + io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 284:27] + io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 284:27] + io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 284:27] + io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 284:27] + io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 284:27] + io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 284:27] + io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 284:27] + io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 284:27] + lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 284:27] module quasar_wrapper : input clock : Clock diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 85b14314..e66ba6b6 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -50189,56 +50189,56 @@ module dec_timer_ctl( wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] reg [31:0] mitcnt0; // @[lib.scala 374:16] reg [31:0] mitb0_b; // @[lib.scala 374:16] - wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2711:22] - wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2672:36] + wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2712:22] + wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2673:36] reg [31:0] mitcnt1; // @[lib.scala 374:16] reg [31:0] mitb1_b; // @[lib.scala 374:16] - wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2720:18] - wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2673:36] - wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2683:72] - wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2683:49] - reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2736:67] - reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2735:60] - wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2736:90] + wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2721:18] + wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2674:36] + wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2684:72] + wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2684:49] + reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2737:67] + reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2736:60] + wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2737:90] wire [2:0] mitctl0 = {_T_57,_T_58}; // @[Cat.scala 29:58] - wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2685:56] - wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2685:76] - wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2685:53] - wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2685:112] - wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2685:138] - wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2685:109] - wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2685:173] - wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2685:171] - wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2686:35] - wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2688:59] - wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2695:72] - wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2695:49] - reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2750:52] - reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2749:55] - wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2750:75] + wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2686:56] + wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2686:76] + wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2686:53] + wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2686:112] + wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2686:138] + wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2686:109] + wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2686:173] + wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2686:171] + wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2687:35] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2689:59] + wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2696:72] + wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2696:49] + reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2751:52] + reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2750:55] + wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2751:75] wire [3:0] mitctl1 = {_T_66,_T_67}; // @[Cat.scala 29:58] - wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2697:76] - wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2697:53] - wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2697:138] - wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2697:109] - wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2697:171] - wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2700:60] - wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2700:72] + wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2698:76] + wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2698:53] + wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2698:138] + wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2698:109] + wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2698:171] + wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2701:60] + wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2701:72] wire [31:0] _T_34 = {31'h0,_T_33}; // @[Cat.scala 29:58] - wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2700:35] - wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2702:60] - wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2709:70] - wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2718:69] - wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2731:72] - wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2731:49] - wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2732:31] - wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2746:71] - wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2746:49] - wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2747:31] - wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2752:51] - wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2752:68] - wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2752:83] - wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2752:98] + wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2701:35] + wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2703:60] + wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2710:70] + wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2719:69] + wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2732:72] + wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2732:49] + wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2733:31] + wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2747:71] + wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2747:49] + wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2748:31] + wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2753:51] + wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2753:68] + wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2753:83] + wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2753:98] wire [31:0] _T_81 = {29'h0,_T_57,_T_58}; // @[Cat.scala 29:58] wire [31:0] _T_84 = {28'h0,_T_66,_T_67}; // @[Cat.scala 29:58] wire [31:0] _T_85 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72] @@ -50275,10 +50275,10 @@ module dec_timer_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2753:33] - assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2752:33] - assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2675:31] - assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2676:31] + assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2754:33] + assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2753:33] + assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2676:31] + assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2677:31] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -51359,245 +51359,247 @@ module csr_tlu( reg [31:0] dicad0h; // @[lib.scala 374:16] wire _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2126:100] wire _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2126:71] - wire _T_757 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2130:78] - reg [6:0] _T_759; // @[Reg.scala 27:20] - wire [31:0] dicad1 = {25'h0,_T_759}; // @[Cat.scala 29:58] - wire [38:0] _T_764 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] - wire _T_766 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2158:52] - wire _T_767 = _T_766 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2158:75] - wire _T_768 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2158:98] - wire _T_769 = _T_767 & _T_768; // @[dec_tlu_ctl.scala 2158:96] - wire _T_771 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2158:149] - wire _T_774 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2159:104] - reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2161:58] - reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2162:58] - wire _T_776 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2173:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_776; // @[dec_tlu_ctl.scala 2173:40] - reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2176:43] - wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2211:42] - wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2213:44] - wire _T_787 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2215:46] - wire tdata_action = _T_787 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2215:69] - wire [9:0] tdata_wrdata_r = {_T_787,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_802 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2221:99] - wire _T_803 = io_dec_csr_wen_r_mod & _T_802; // @[dec_tlu_ctl.scala 2221:70] - wire _T_804 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2221:121] - wire _T_805 = _T_803 & _T_804; // @[dec_tlu_ctl.scala 2221:112] - wire _T_807 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2221:138] - wire _T_808 = _T_807 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] - wire wr_mtdata1_t_r_0 = _T_805 & _T_808; // @[dec_tlu_ctl.scala 2221:135] - wire _T_813 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2221:121] - wire _T_814 = _T_803 & _T_813; // @[dec_tlu_ctl.scala 2221:112] - wire _T_816 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2221:138] - wire _T_817 = _T_816 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] - wire wr_mtdata1_t_r_1 = _T_814 & _T_817; // @[dec_tlu_ctl.scala 2221:135] - wire _T_822 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2221:121] - wire _T_823 = _T_803 & _T_822; // @[dec_tlu_ctl.scala 2221:112] - wire _T_825 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2221:138] - wire _T_826 = _T_825 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] - wire wr_mtdata1_t_r_2 = _T_823 & _T_826; // @[dec_tlu_ctl.scala 2221:135] - wire _T_831 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2221:121] - wire _T_832 = _T_803 & _T_831; // @[dec_tlu_ctl.scala 2221:112] - wire _T_834 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2221:138] - wire _T_835 = _T_834 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:170] - wire wr_mtdata1_t_r_3 = _T_832 & _T_835; // @[dec_tlu_ctl.scala 2221:135] - wire _T_841 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2222:139] - wire [9:0] _T_844 = {io_mtdata1_t_0[9],_T_841,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_850 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2222:139] - wire [9:0] _T_853 = {io_mtdata1_t_1[9],_T_850,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_859 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2222:139] - wire [9:0] _T_862 = {io_mtdata1_t_2[9],_T_859,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_868 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2222:139] - wire [9:0] _T_871 = {io_mtdata1_t_3[9],_T_868,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2224:74] - reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2224:74] - reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2224:74] - reg [9:0] _T_876; // @[dec_tlu_ctl.scala 2224:74] - wire [31:0] _T_891 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_906 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_921 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_936 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_937 = _T_804 ? _T_891 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_938 = _T_813 ? _T_906 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_939 = _T_822 ? _T_921 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_940 = _T_831 ? _T_936 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_941 = _T_937 | _T_938; // @[Mux.scala 27:72] - wire [31:0] _T_942 = _T_941 | _T_939; // @[Mux.scala 27:72] - wire [31:0] mtdata1_tsel_out = _T_942 | _T_940; // @[Mux.scala 27:72] - wire _T_969 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2241:98] - wire _T_970 = io_dec_csr_wen_r_mod & _T_969; // @[dec_tlu_ctl.scala 2241:69] - wire _T_972 = _T_970 & _T_804; // @[dec_tlu_ctl.scala 2241:111] - wire _T_981 = _T_970 & _T_813; // @[dec_tlu_ctl.scala 2241:111] - wire _T_990 = _T_970 & _T_822; // @[dec_tlu_ctl.scala 2241:111] - wire _T_999 = _T_970 & _T_831; // @[dec_tlu_ctl.scala 2241:111] + wire [31:0] _T_755 = _T_752 ? io_dec_csr_wrdata_r : {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; // @[dec_tlu_ctl.scala 2128:21] + wire _T_756 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2131:78] + reg [31:0] _T_758; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_758[6:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_763 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_765 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2159:52] + wire _T_766 = _T_765 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2159:75] + wire _T_767 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2159:98] + wire _T_768 = _T_766 & _T_767; // @[dec_tlu_ctl.scala 2159:96] + wire _T_770 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2159:149] + wire _T_773 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2160:104] + reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2162:58] + reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2163:58] + wire _T_775 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2174:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_775; // @[dec_tlu_ctl.scala 2174:40] + reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2177:43] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2212:42] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2214:44] + wire _T_786 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2216:46] + wire tdata_action = _T_786 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2216:69] + wire [9:0] tdata_wrdata_r = {_T_786,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_801 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2222:99] + wire _T_802 = io_dec_csr_wen_r_mod & _T_801; // @[dec_tlu_ctl.scala 2222:70] + wire _T_803 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2222:121] + wire _T_804 = _T_802 & _T_803; // @[dec_tlu_ctl.scala 2222:112] + wire _T_806 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_0 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2222:135] + wire _T_812 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2222:121] + wire _T_813 = _T_802 & _T_812; // @[dec_tlu_ctl.scala 2222:112] + wire _T_815 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_1 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2222:135] + wire _T_821 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2222:121] + wire _T_822 = _T_802 & _T_821; // @[dec_tlu_ctl.scala 2222:112] + wire _T_824 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_2 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2222:135] + wire _T_830 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2222:121] + wire _T_831 = _T_802 & _T_830; // @[dec_tlu_ctl.scala 2222:112] + wire _T_833 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_834 = _T_833 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_3 = _T_831 & _T_834; // @[dec_tlu_ctl.scala 2222:135] + wire _T_840 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_843 = {io_mtdata1_t_0[9],_T_840,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_849 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_852 = {io_mtdata1_t_1[9],_T_849,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_858 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_861 = {io_mtdata1_t_2[9],_T_858,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_867 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_870 = {io_mtdata1_t_3[9],_T_867,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_872; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2225:74] + wire [31:0] _T_890 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_905 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_920 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_935 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_936 = _T_803 ? _T_890 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_937 = _T_812 ? _T_905 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_938 = _T_821 ? _T_920 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_939 = _T_830 ? _T_935 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_940 = _T_936 | _T_937; // @[Mux.scala 27:72] + wire [31:0] _T_941 = _T_940 | _T_938; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_941 | _T_939; // @[Mux.scala 27:72] + wire _T_968 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2242:98] + wire _T_969 = io_dec_csr_wen_r_mod & _T_968; // @[dec_tlu_ctl.scala 2242:69] + wire _T_971 = _T_969 & _T_803; // @[dec_tlu_ctl.scala 2242:111] + wire _T_980 = _T_969 & _T_812; // @[dec_tlu_ctl.scala 2242:111] + wire _T_989 = _T_969 & _T_821; // @[dec_tlu_ctl.scala 2242:111] + wire _T_998 = _T_969 & _T_830; // @[dec_tlu_ctl.scala 2242:111] reg [31:0] mtdata2_t_0; // @[lib.scala 374:16] reg [31:0] mtdata2_t_1; // @[lib.scala 374:16] reg [31:0] mtdata2_t_2; // @[lib.scala 374:16] reg [31:0] mtdata2_t_3; // @[lib.scala 374:16] - wire [31:0] _T_1016 = _T_804 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1017 = _T_813 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1018 = _T_822 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1019 = _T_831 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1020 = _T_1016 | _T_1017; // @[Mux.scala 27:72] - wire [31:0] _T_1021 = _T_1020 | _T_1018; // @[Mux.scala 27:72] - wire [31:0] mtdata2_tsel_out = _T_1021 | _T_1019; // @[Mux.scala 27:72] - wire [3:0] _T_1024 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1024; // @[dec_tlu_ctl.scala 2266:59] - wire _T_1026 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2272:24] + wire [31:0] _T_1015 = _T_803 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1016 = _T_812 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1017 = _T_821 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1018 = _T_830 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1019 = _T_1015 | _T_1016; // @[Mux.scala 27:72] + wire [31:0] _T_1020 = _T_1019 | _T_1017; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1020 | _T_1018; // @[Mux.scala 27:72] + wire [3:0] _T_1023 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1023; // @[dec_tlu_ctl.scala 2267:59] + wire _T_1025 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1027 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1029 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1031 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1033 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1035 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2276:96] - wire _T_1036 = io_tlu_i0_commit_cmt & _T_1035; // @[dec_tlu_ctl.scala 2276:94] - wire _T_1037 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1039 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2277:96] - wire _T_1040 = io_tlu_i0_commit_cmt & _T_1039; // @[dec_tlu_ctl.scala 2277:94] - wire _T_1042 = _T_1040 & _T_1035; // @[dec_tlu_ctl.scala 2277:115] - wire _T_1043 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1045 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:94] - wire _T_1047 = _T_1045 & _T_1035; // @[dec_tlu_ctl.scala 2278:115] - wire _T_1048 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1050 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1052 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1054 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1056 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2282:91] - wire _T_1057 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1059 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2283:105] - wire _T_1060 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1062 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2284:91] - wire _T_1063 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1065 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2285:91] - wire _T_1066 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1069 = _T_1062 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2286:100] - wire _T_1070 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1074 = _T_1065 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:101] - wire _T_1075 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1077 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2288:89] - wire _T_1078 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1080 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2289:89] - wire _T_1081 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1083 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2290:89] - wire _T_1084 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1086 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2291:89] - wire _T_1087 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1089 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2292:89] - wire _T_1090 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1092 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2293:89] - wire _T_1093 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1095 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2294:89] - wire _T_1096 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1098 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2295:89] - wire _T_1099 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1101 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2296:89] - wire _T_1102 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1104 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2297:89] - wire _T_1105 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2297:122] - wire _T_1106 = _T_1104 | _T_1105; // @[dec_tlu_ctl.scala 2297:101] - wire _T_1107 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1109 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2298:95] - wire _T_1110 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1112 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:97] - wire _T_1113 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1115 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:110] - wire _T_1116 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1120 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1122 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1124 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1126 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1128 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1130 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1132 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2308:98] - wire _T_1133 = _T_1132 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2308:120] - wire _T_1134 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1136 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2309:92] - wire _T_1137 = _T_1136 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2309:117] - wire _T_1138 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1140 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1142 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1144 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2312:97] - wire _T_1145 = _T_1144 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2312:129] - wire _T_1146 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1148 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1150 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1152 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1154 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1156 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1158 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1160 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1164 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2320:73] - wire _T_1165 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] - wire [5:0] _T_1172 = io_mip & mie; // @[dec_tlu_ctl.scala 2321:113] - wire _T_1173 = |_T_1172; // @[dec_tlu_ctl.scala 2321:125] - wire _T_1174 = _T_1164 & _T_1173; // @[dec_tlu_ctl.scala 2321:98] - wire _T_1175 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1177 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2322:91] - wire _T_1178 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1180 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2323:94] - wire _T_1181 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1183 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2324:94] - wire _T_1184 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1186 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1188 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1190 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1192 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1195 = _T_1029 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1196 = _T_1031 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1197 = _T_1033 & _T_1036; // @[Mux.scala 27:72] - wire _T_1198 = _T_1037 & _T_1042; // @[Mux.scala 27:72] - wire _T_1199 = _T_1043 & _T_1047; // @[Mux.scala 27:72] - wire _T_1200 = _T_1048 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1201 = _T_1050 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1202 = _T_1052 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1203 = _T_1054 & _T_1056; // @[Mux.scala 27:72] - wire _T_1204 = _T_1057 & _T_1059; // @[Mux.scala 27:72] - wire _T_1205 = _T_1060 & _T_1062; // @[Mux.scala 27:72] - wire _T_1206 = _T_1063 & _T_1065; // @[Mux.scala 27:72] - wire _T_1207 = _T_1066 & _T_1069; // @[Mux.scala 27:72] - wire _T_1208 = _T_1070 & _T_1074; // @[Mux.scala 27:72] - wire _T_1209 = _T_1075 & _T_1077; // @[Mux.scala 27:72] - wire _T_1210 = _T_1078 & _T_1080; // @[Mux.scala 27:72] - wire _T_1211 = _T_1081 & _T_1083; // @[Mux.scala 27:72] - wire _T_1212 = _T_1084 & _T_1086; // @[Mux.scala 27:72] - wire _T_1213 = _T_1087 & _T_1089; // @[Mux.scala 27:72] - wire _T_1214 = _T_1090 & _T_1092; // @[Mux.scala 27:72] - wire _T_1215 = _T_1093 & _T_1095; // @[Mux.scala 27:72] - wire _T_1216 = _T_1096 & _T_1098; // @[Mux.scala 27:72] - wire _T_1217 = _T_1099 & _T_1101; // @[Mux.scala 27:72] - wire _T_1218 = _T_1102 & _T_1106; // @[Mux.scala 27:72] - wire _T_1219 = _T_1107 & _T_1109; // @[Mux.scala 27:72] - wire _T_1220 = _T_1110 & _T_1112; // @[Mux.scala 27:72] - wire _T_1221 = _T_1113 & _T_1115; // @[Mux.scala 27:72] - wire _T_1222 = _T_1116 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1224 = _T_1120 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1225 = _T_1122 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1226 = _T_1124 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1227 = _T_1126 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1228 = _T_1128 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1229 = _T_1130 & _T_1133; // @[Mux.scala 27:72] - wire _T_1230 = _T_1134 & _T_1137; // @[Mux.scala 27:72] - wire _T_1231 = _T_1138 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1232 = _T_1140 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1233 = _T_1142 & _T_1145; // @[Mux.scala 27:72] - wire _T_1234 = _T_1146 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1235 = _T_1148 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1236 = _T_1150 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1237 = _T_1152 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1238 = _T_1154 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1239 = _T_1156 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1240 = _T_1158 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1241 = _T_1160 & _T_1164; // @[Mux.scala 27:72] - wire _T_1242 = _T_1165 & _T_1174; // @[Mux.scala 27:72] - wire _T_1243 = _T_1175 & _T_1177; // @[Mux.scala 27:72] - wire _T_1244 = _T_1178 & _T_1180; // @[Mux.scala 27:72] - wire _T_1245 = _T_1181 & _T_1183; // @[Mux.scala 27:72] - wire _T_1246 = _T_1184 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1247 = _T_1186 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1248 = _T_1188 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1249 = _T_1190 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1250 = _T_1192 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1251 = _T_1027 | _T_1195; // @[Mux.scala 27:72] + wire _T_1026 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1028 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1030 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1032 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1034 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2277:96] + wire _T_1035 = io_tlu_i0_commit_cmt & _T_1034; // @[dec_tlu_ctl.scala 2277:94] + wire _T_1036 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1038 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:96] + wire _T_1039 = io_tlu_i0_commit_cmt & _T_1038; // @[dec_tlu_ctl.scala 2278:94] + wire _T_1041 = _T_1039 & _T_1034; // @[dec_tlu_ctl.scala 2278:115] + wire _T_1042 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1044 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:94] + wire _T_1046 = _T_1044 & _T_1034; // @[dec_tlu_ctl.scala 2279:115] + wire _T_1047 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1049 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1051 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1053 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1055 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2283:91] + wire _T_1056 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1058 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2284:105] + wire _T_1059 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1061 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2285:91] + wire _T_1062 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1064 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2286:91] + wire _T_1065 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1068 = _T_1061 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:100] + wire _T_1069 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1073 = _T_1064 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:101] + wire _T_1074 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1076 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2289:89] + wire _T_1077 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1079 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2290:89] + wire _T_1080 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1082 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2291:89] + wire _T_1083 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1085 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2292:89] + wire _T_1086 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1088 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2293:89] + wire _T_1089 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1091 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2294:89] + wire _T_1092 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1094 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2295:89] + wire _T_1095 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1097 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2296:89] + wire _T_1098 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1100 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2297:89] + wire _T_1101 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1103 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2298:89] + wire _T_1104 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2298:122] + wire _T_1105 = _T_1103 | _T_1104; // @[dec_tlu_ctl.scala 2298:101] + wire _T_1106 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1108 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:95] + wire _T_1109 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1111 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:97] + wire _T_1112 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1114 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:110] + wire _T_1115 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1119 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1121 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1123 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1125 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1127 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1129 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1131 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2309:98] + wire _T_1132 = _T_1131 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2309:120] + wire _T_1133 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1135 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2310:92] + wire _T_1136 = _T_1135 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2310:117] + wire _T_1137 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1139 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1141 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1143 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2313:97] + wire _T_1144 = _T_1143 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2313:129] + wire _T_1145 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1147 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1149 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1151 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1153 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1155 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1157 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1159 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1163 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2321:73] + wire _T_1164 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire [5:0] _T_1171 = io_mip & mie; // @[dec_tlu_ctl.scala 2322:113] + wire _T_1172 = |_T_1171; // @[dec_tlu_ctl.scala 2322:125] + wire _T_1173 = _T_1163 & _T_1172; // @[dec_tlu_ctl.scala 2322:98] + wire _T_1174 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2323:91] + wire _T_1177 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2324:94] + wire _T_1180 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2325:94] + wire _T_1183 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1185 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1187 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1189 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1191 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1194 = _T_1028 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1195 = _T_1030 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1196 = _T_1032 & _T_1035; // @[Mux.scala 27:72] + wire _T_1197 = _T_1036 & _T_1041; // @[Mux.scala 27:72] + wire _T_1198 = _T_1042 & _T_1046; // @[Mux.scala 27:72] + wire _T_1199 = _T_1047 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1200 = _T_1049 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1201 = _T_1051 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1202 = _T_1053 & _T_1055; // @[Mux.scala 27:72] + wire _T_1203 = _T_1056 & _T_1058; // @[Mux.scala 27:72] + wire _T_1204 = _T_1059 & _T_1061; // @[Mux.scala 27:72] + wire _T_1205 = _T_1062 & _T_1064; // @[Mux.scala 27:72] + wire _T_1206 = _T_1065 & _T_1068; // @[Mux.scala 27:72] + wire _T_1207 = _T_1069 & _T_1073; // @[Mux.scala 27:72] + wire _T_1208 = _T_1074 & _T_1076; // @[Mux.scala 27:72] + wire _T_1209 = _T_1077 & _T_1079; // @[Mux.scala 27:72] + wire _T_1210 = _T_1080 & _T_1082; // @[Mux.scala 27:72] + wire _T_1211 = _T_1083 & _T_1085; // @[Mux.scala 27:72] + wire _T_1212 = _T_1086 & _T_1088; // @[Mux.scala 27:72] + wire _T_1213 = _T_1089 & _T_1091; // @[Mux.scala 27:72] + wire _T_1214 = _T_1092 & _T_1094; // @[Mux.scala 27:72] + wire _T_1215 = _T_1095 & _T_1097; // @[Mux.scala 27:72] + wire _T_1216 = _T_1098 & _T_1100; // @[Mux.scala 27:72] + wire _T_1217 = _T_1101 & _T_1105; // @[Mux.scala 27:72] + wire _T_1218 = _T_1106 & _T_1108; // @[Mux.scala 27:72] + wire _T_1219 = _T_1109 & _T_1111; // @[Mux.scala 27:72] + wire _T_1220 = _T_1112 & _T_1114; // @[Mux.scala 27:72] + wire _T_1221 = _T_1115 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1223 = _T_1119 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1224 = _T_1121 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1225 = _T_1123 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1226 = _T_1125 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1227 = _T_1127 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1228 = _T_1129 & _T_1132; // @[Mux.scala 27:72] + wire _T_1229 = _T_1133 & _T_1136; // @[Mux.scala 27:72] + wire _T_1230 = _T_1137 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1231 = _T_1139 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1232 = _T_1141 & _T_1144; // @[Mux.scala 27:72] + wire _T_1233 = _T_1145 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1234 = _T_1147 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1235 = _T_1149 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1236 = _T_1151 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1237 = _T_1153 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1238 = _T_1155 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1239 = _T_1157 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1240 = _T_1159 & _T_1163; // @[Mux.scala 27:72] + wire _T_1241 = _T_1164 & _T_1173; // @[Mux.scala 27:72] + wire _T_1242 = _T_1174 & _T_1176; // @[Mux.scala 27:72] + wire _T_1243 = _T_1177 & _T_1179; // @[Mux.scala 27:72] + wire _T_1244 = _T_1180 & _T_1182; // @[Mux.scala 27:72] + wire _T_1245 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1246 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1247 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1248 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1249 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1250 = _T_1026 | _T_1194; // @[Mux.scala 27:72] + wire _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72] wire _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72] wire _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72] wire _T_1254 = _T_1253 | _T_1198; // @[Mux.scala 27:72] @@ -51624,8 +51626,8 @@ module csr_tlu( wire _T_1275 = _T_1274 | _T_1219; // @[Mux.scala 27:72] wire _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72] wire _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72] - wire _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72] - wire _T_1279 = _T_1278 | _T_1202; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1201; // @[Mux.scala 27:72] + wire _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72] wire _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72] wire _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72] wire _T_1282 = _T_1281 | _T_1226; // @[Mux.scala 27:72] @@ -51652,122 +51654,122 @@ module csr_tlu( wire _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72] wire _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72] wire _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72] - wire _T_1306 = _T_1305 | _T_1250; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1026 & _T_1306; // @[dec_tlu_ctl.scala 2272:44] - wire _T_1310 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2272:24] + wire mhpmc_inc_r_0 = _T_1025 & _T_1305; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1309 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1311 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1313 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1315 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1317 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1321 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1327 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1332 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1334 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1336 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1338 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1341 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1344 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1347 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1350 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1354 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1359 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1362 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1365 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1368 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1371 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1374 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1377 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1380 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1383 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1386 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1391 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1394 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1397 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1400 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1404 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1406 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1408 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1410 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1412 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1414 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1418 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1422 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1424 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1426 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1430 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1432 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1434 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1436 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1438 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1440 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1442 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1444 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1449 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1459 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1462 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1465 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1468 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1470 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1472 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1474 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1476 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1479 = _T_1313 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1480 = _T_1315 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1481 = _T_1317 & _T_1036; // @[Mux.scala 27:72] - wire _T_1482 = _T_1321 & _T_1042; // @[Mux.scala 27:72] - wire _T_1483 = _T_1327 & _T_1047; // @[Mux.scala 27:72] - wire _T_1484 = _T_1332 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1485 = _T_1334 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1486 = _T_1336 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1487 = _T_1338 & _T_1056; // @[Mux.scala 27:72] - wire _T_1488 = _T_1341 & _T_1059; // @[Mux.scala 27:72] - wire _T_1489 = _T_1344 & _T_1062; // @[Mux.scala 27:72] - wire _T_1490 = _T_1347 & _T_1065; // @[Mux.scala 27:72] - wire _T_1491 = _T_1350 & _T_1069; // @[Mux.scala 27:72] - wire _T_1492 = _T_1354 & _T_1074; // @[Mux.scala 27:72] - wire _T_1493 = _T_1359 & _T_1077; // @[Mux.scala 27:72] - wire _T_1494 = _T_1362 & _T_1080; // @[Mux.scala 27:72] - wire _T_1495 = _T_1365 & _T_1083; // @[Mux.scala 27:72] - wire _T_1496 = _T_1368 & _T_1086; // @[Mux.scala 27:72] - wire _T_1497 = _T_1371 & _T_1089; // @[Mux.scala 27:72] - wire _T_1498 = _T_1374 & _T_1092; // @[Mux.scala 27:72] - wire _T_1499 = _T_1377 & _T_1095; // @[Mux.scala 27:72] - wire _T_1500 = _T_1380 & _T_1098; // @[Mux.scala 27:72] - wire _T_1501 = _T_1383 & _T_1101; // @[Mux.scala 27:72] - wire _T_1502 = _T_1386 & _T_1106; // @[Mux.scala 27:72] - wire _T_1503 = _T_1391 & _T_1109; // @[Mux.scala 27:72] - wire _T_1504 = _T_1394 & _T_1112; // @[Mux.scala 27:72] - wire _T_1505 = _T_1397 & _T_1115; // @[Mux.scala 27:72] - wire _T_1506 = _T_1400 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1508 = _T_1404 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1509 = _T_1406 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1510 = _T_1408 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1511 = _T_1410 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1512 = _T_1412 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1513 = _T_1414 & _T_1133; // @[Mux.scala 27:72] - wire _T_1514 = _T_1418 & _T_1137; // @[Mux.scala 27:72] - wire _T_1515 = _T_1422 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1516 = _T_1424 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1517 = _T_1426 & _T_1145; // @[Mux.scala 27:72] - wire _T_1518 = _T_1430 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1519 = _T_1432 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1520 = _T_1434 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1521 = _T_1436 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1522 = _T_1438 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1523 = _T_1440 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1524 = _T_1442 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1525 = _T_1444 & _T_1164; // @[Mux.scala 27:72] - wire _T_1526 = _T_1449 & _T_1174; // @[Mux.scala 27:72] - wire _T_1527 = _T_1459 & _T_1177; // @[Mux.scala 27:72] - wire _T_1528 = _T_1462 & _T_1180; // @[Mux.scala 27:72] - wire _T_1529 = _T_1465 & _T_1183; // @[Mux.scala 27:72] - wire _T_1530 = _T_1468 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1531 = _T_1470 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1532 = _T_1472 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1533 = _T_1474 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1534 = _T_1476 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1535 = _T_1311 | _T_1479; // @[Mux.scala 27:72] + wire _T_1310 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1312 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1314 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1316 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1320 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1326 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1331 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1333 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1335 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1337 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1340 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1343 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1346 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1349 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1353 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1358 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1361 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1364 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1367 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1370 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1373 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1376 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1379 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1382 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1385 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1390 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1393 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1396 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1399 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1403 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1405 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1407 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1409 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1411 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1413 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1417 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1421 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1423 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1425 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1429 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1431 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1433 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1435 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1437 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1439 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1441 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1443 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1448 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1458 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1461 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1464 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1467 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1469 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1471 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1473 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1475 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1478 = _T_1312 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1479 = _T_1314 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1480 = _T_1316 & _T_1035; // @[Mux.scala 27:72] + wire _T_1481 = _T_1320 & _T_1041; // @[Mux.scala 27:72] + wire _T_1482 = _T_1326 & _T_1046; // @[Mux.scala 27:72] + wire _T_1483 = _T_1331 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1484 = _T_1333 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1485 = _T_1335 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1486 = _T_1337 & _T_1055; // @[Mux.scala 27:72] + wire _T_1487 = _T_1340 & _T_1058; // @[Mux.scala 27:72] + wire _T_1488 = _T_1343 & _T_1061; // @[Mux.scala 27:72] + wire _T_1489 = _T_1346 & _T_1064; // @[Mux.scala 27:72] + wire _T_1490 = _T_1349 & _T_1068; // @[Mux.scala 27:72] + wire _T_1491 = _T_1353 & _T_1073; // @[Mux.scala 27:72] + wire _T_1492 = _T_1358 & _T_1076; // @[Mux.scala 27:72] + wire _T_1493 = _T_1361 & _T_1079; // @[Mux.scala 27:72] + wire _T_1494 = _T_1364 & _T_1082; // @[Mux.scala 27:72] + wire _T_1495 = _T_1367 & _T_1085; // @[Mux.scala 27:72] + wire _T_1496 = _T_1370 & _T_1088; // @[Mux.scala 27:72] + wire _T_1497 = _T_1373 & _T_1091; // @[Mux.scala 27:72] + wire _T_1498 = _T_1376 & _T_1094; // @[Mux.scala 27:72] + wire _T_1499 = _T_1379 & _T_1097; // @[Mux.scala 27:72] + wire _T_1500 = _T_1382 & _T_1100; // @[Mux.scala 27:72] + wire _T_1501 = _T_1385 & _T_1105; // @[Mux.scala 27:72] + wire _T_1502 = _T_1390 & _T_1108; // @[Mux.scala 27:72] + wire _T_1503 = _T_1393 & _T_1111; // @[Mux.scala 27:72] + wire _T_1504 = _T_1396 & _T_1114; // @[Mux.scala 27:72] + wire _T_1505 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1507 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1508 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1509 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1510 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1511 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1512 = _T_1413 & _T_1132; // @[Mux.scala 27:72] + wire _T_1513 = _T_1417 & _T_1136; // @[Mux.scala 27:72] + wire _T_1514 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1515 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1516 = _T_1425 & _T_1144; // @[Mux.scala 27:72] + wire _T_1517 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1518 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1519 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1520 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1521 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1522 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1523 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1524 = _T_1443 & _T_1163; // @[Mux.scala 27:72] + wire _T_1525 = _T_1448 & _T_1173; // @[Mux.scala 27:72] + wire _T_1526 = _T_1458 & _T_1176; // @[Mux.scala 27:72] + wire _T_1527 = _T_1461 & _T_1179; // @[Mux.scala 27:72] + wire _T_1528 = _T_1464 & _T_1182; // @[Mux.scala 27:72] + wire _T_1529 = _T_1467 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1530 = _T_1469 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1531 = _T_1471 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1532 = _T_1473 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1533 = _T_1475 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1534 = _T_1310 | _T_1478; // @[Mux.scala 27:72] + wire _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72] wire _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72] wire _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72] wire _T_1538 = _T_1537 | _T_1482; // @[Mux.scala 27:72] @@ -51794,8 +51796,8 @@ module csr_tlu( wire _T_1559 = _T_1558 | _T_1503; // @[Mux.scala 27:72] wire _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72] wire _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72] - wire _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72] - wire _T_1563 = _T_1562 | _T_1486; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1485; // @[Mux.scala 27:72] + wire _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72] wire _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72] wire _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72] wire _T_1566 = _T_1565 | _T_1510; // @[Mux.scala 27:72] @@ -51822,122 +51824,122 @@ module csr_tlu( wire _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72] wire _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72] wire _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72] - wire _T_1590 = _T_1589 | _T_1534; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1310 & _T_1590; // @[dec_tlu_ctl.scala 2272:44] - wire _T_1594 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2272:24] + wire mhpmc_inc_r_1 = _T_1309 & _T_1589; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1593 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1595 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1597 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1599 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1601 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1605 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1611 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1616 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1618 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1620 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1622 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1625 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1628 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1631 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1634 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1638 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1643 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1646 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1649 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1652 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1655 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1658 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1661 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1664 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1667 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1670 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1675 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1678 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1681 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1684 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1688 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1690 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1692 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1694 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1696 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1698 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1702 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1706 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1708 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1710 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1714 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1716 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1718 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1720 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1722 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1724 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1726 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1728 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1733 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1743 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1746 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1749 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1752 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1754 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1756 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1758 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1760 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1763 = _T_1597 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1764 = _T_1599 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1765 = _T_1601 & _T_1036; // @[Mux.scala 27:72] - wire _T_1766 = _T_1605 & _T_1042; // @[Mux.scala 27:72] - wire _T_1767 = _T_1611 & _T_1047; // @[Mux.scala 27:72] - wire _T_1768 = _T_1616 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1769 = _T_1618 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1770 = _T_1620 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1771 = _T_1622 & _T_1056; // @[Mux.scala 27:72] - wire _T_1772 = _T_1625 & _T_1059; // @[Mux.scala 27:72] - wire _T_1773 = _T_1628 & _T_1062; // @[Mux.scala 27:72] - wire _T_1774 = _T_1631 & _T_1065; // @[Mux.scala 27:72] - wire _T_1775 = _T_1634 & _T_1069; // @[Mux.scala 27:72] - wire _T_1776 = _T_1638 & _T_1074; // @[Mux.scala 27:72] - wire _T_1777 = _T_1643 & _T_1077; // @[Mux.scala 27:72] - wire _T_1778 = _T_1646 & _T_1080; // @[Mux.scala 27:72] - wire _T_1779 = _T_1649 & _T_1083; // @[Mux.scala 27:72] - wire _T_1780 = _T_1652 & _T_1086; // @[Mux.scala 27:72] - wire _T_1781 = _T_1655 & _T_1089; // @[Mux.scala 27:72] - wire _T_1782 = _T_1658 & _T_1092; // @[Mux.scala 27:72] - wire _T_1783 = _T_1661 & _T_1095; // @[Mux.scala 27:72] - wire _T_1784 = _T_1664 & _T_1098; // @[Mux.scala 27:72] - wire _T_1785 = _T_1667 & _T_1101; // @[Mux.scala 27:72] - wire _T_1786 = _T_1670 & _T_1106; // @[Mux.scala 27:72] - wire _T_1787 = _T_1675 & _T_1109; // @[Mux.scala 27:72] - wire _T_1788 = _T_1678 & _T_1112; // @[Mux.scala 27:72] - wire _T_1789 = _T_1681 & _T_1115; // @[Mux.scala 27:72] - wire _T_1790 = _T_1684 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1792 = _T_1688 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1793 = _T_1690 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1794 = _T_1692 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1795 = _T_1694 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1796 = _T_1696 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1797 = _T_1698 & _T_1133; // @[Mux.scala 27:72] - wire _T_1798 = _T_1702 & _T_1137; // @[Mux.scala 27:72] - wire _T_1799 = _T_1706 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1800 = _T_1708 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1801 = _T_1710 & _T_1145; // @[Mux.scala 27:72] - wire _T_1802 = _T_1714 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1803 = _T_1716 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1804 = _T_1718 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1805 = _T_1720 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1806 = _T_1722 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1807 = _T_1724 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1808 = _T_1726 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1809 = _T_1728 & _T_1164; // @[Mux.scala 27:72] - wire _T_1810 = _T_1733 & _T_1174; // @[Mux.scala 27:72] - wire _T_1811 = _T_1743 & _T_1177; // @[Mux.scala 27:72] - wire _T_1812 = _T_1746 & _T_1180; // @[Mux.scala 27:72] - wire _T_1813 = _T_1749 & _T_1183; // @[Mux.scala 27:72] - wire _T_1814 = _T_1752 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1815 = _T_1754 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1816 = _T_1756 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1817 = _T_1758 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1818 = _T_1760 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1819 = _T_1595 | _T_1763; // @[Mux.scala 27:72] + wire _T_1594 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1596 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1598 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1600 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1604 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1610 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1615 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1617 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1619 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1621 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1624 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1627 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1630 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1633 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1637 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1642 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1645 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1648 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1651 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1654 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1657 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1660 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1663 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1666 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1669 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1674 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1677 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1680 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1683 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1687 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1689 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1691 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1693 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1695 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1697 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1701 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1705 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1707 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1709 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1713 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1715 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1717 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1719 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1721 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1723 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1725 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1727 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1732 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1742 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1745 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1748 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1751 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1753 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1755 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1757 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1759 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1762 = _T_1596 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1763 = _T_1598 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1764 = _T_1600 & _T_1035; // @[Mux.scala 27:72] + wire _T_1765 = _T_1604 & _T_1041; // @[Mux.scala 27:72] + wire _T_1766 = _T_1610 & _T_1046; // @[Mux.scala 27:72] + wire _T_1767 = _T_1615 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1768 = _T_1617 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1769 = _T_1619 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1770 = _T_1621 & _T_1055; // @[Mux.scala 27:72] + wire _T_1771 = _T_1624 & _T_1058; // @[Mux.scala 27:72] + wire _T_1772 = _T_1627 & _T_1061; // @[Mux.scala 27:72] + wire _T_1773 = _T_1630 & _T_1064; // @[Mux.scala 27:72] + wire _T_1774 = _T_1633 & _T_1068; // @[Mux.scala 27:72] + wire _T_1775 = _T_1637 & _T_1073; // @[Mux.scala 27:72] + wire _T_1776 = _T_1642 & _T_1076; // @[Mux.scala 27:72] + wire _T_1777 = _T_1645 & _T_1079; // @[Mux.scala 27:72] + wire _T_1778 = _T_1648 & _T_1082; // @[Mux.scala 27:72] + wire _T_1779 = _T_1651 & _T_1085; // @[Mux.scala 27:72] + wire _T_1780 = _T_1654 & _T_1088; // @[Mux.scala 27:72] + wire _T_1781 = _T_1657 & _T_1091; // @[Mux.scala 27:72] + wire _T_1782 = _T_1660 & _T_1094; // @[Mux.scala 27:72] + wire _T_1783 = _T_1663 & _T_1097; // @[Mux.scala 27:72] + wire _T_1784 = _T_1666 & _T_1100; // @[Mux.scala 27:72] + wire _T_1785 = _T_1669 & _T_1105; // @[Mux.scala 27:72] + wire _T_1786 = _T_1674 & _T_1108; // @[Mux.scala 27:72] + wire _T_1787 = _T_1677 & _T_1111; // @[Mux.scala 27:72] + wire _T_1788 = _T_1680 & _T_1114; // @[Mux.scala 27:72] + wire _T_1789 = _T_1683 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1791 = _T_1687 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1792 = _T_1689 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1793 = _T_1691 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1794 = _T_1693 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1795 = _T_1695 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1796 = _T_1697 & _T_1132; // @[Mux.scala 27:72] + wire _T_1797 = _T_1701 & _T_1136; // @[Mux.scala 27:72] + wire _T_1798 = _T_1705 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1799 = _T_1707 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1800 = _T_1709 & _T_1144; // @[Mux.scala 27:72] + wire _T_1801 = _T_1713 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1802 = _T_1715 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1803 = _T_1717 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1804 = _T_1719 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1805 = _T_1721 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1806 = _T_1723 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1807 = _T_1725 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1808 = _T_1727 & _T_1163; // @[Mux.scala 27:72] + wire _T_1809 = _T_1732 & _T_1173; // @[Mux.scala 27:72] + wire _T_1810 = _T_1742 & _T_1176; // @[Mux.scala 27:72] + wire _T_1811 = _T_1745 & _T_1179; // @[Mux.scala 27:72] + wire _T_1812 = _T_1748 & _T_1182; // @[Mux.scala 27:72] + wire _T_1813 = _T_1751 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1814 = _T_1753 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1815 = _T_1755 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1816 = _T_1757 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1817 = _T_1759 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1818 = _T_1594 | _T_1762; // @[Mux.scala 27:72] + wire _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72] wire _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72] wire _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72] wire _T_1822 = _T_1821 | _T_1766; // @[Mux.scala 27:72] @@ -51964,8 +51966,8 @@ module csr_tlu( wire _T_1843 = _T_1842 | _T_1787; // @[Mux.scala 27:72] wire _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72] wire _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72] - wire _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72] - wire _T_1847 = _T_1846 | _T_1770; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1769; // @[Mux.scala 27:72] + wire _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72] wire _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72] wire _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72] wire _T_1850 = _T_1849 | _T_1794; // @[Mux.scala 27:72] @@ -51992,122 +51994,122 @@ module csr_tlu( wire _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72] wire _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72] wire _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72] - wire _T_1874 = _T_1873 | _T_1818; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1594 & _T_1874; // @[dec_tlu_ctl.scala 2272:44] - wire _T_1878 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2272:24] + wire mhpmc_inc_r_2 = _T_1593 & _T_1873; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1877 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1879 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2273:34] - wire _T_1881 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1883 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1885 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1889 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1895 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1900 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1902 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1904 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1906 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1909 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1912 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1915 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1918 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1922 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1927 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1930 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1933 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1936 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1939 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1942 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1945 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1948 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1951 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1954 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1959 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1962 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1965 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1968 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1972 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1974 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1976 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1978 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1980 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1982 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1986 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1990 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1992 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1994 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1998 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2313:34] - wire _T_2000 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2314:34] - wire _T_2002 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2315:34] - wire _T_2004 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2316:34] - wire _T_2006 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2317:34] - wire _T_2008 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2318:34] - wire _T_2010 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2319:34] - wire _T_2012 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2320:34] - wire _T_2017 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2321:34] - wire _T_2027 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2322:34] - wire _T_2030 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2323:34] - wire _T_2033 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2324:34] - wire _T_2036 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2326:34] - wire _T_2038 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2327:34] - wire _T_2040 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2328:34] - wire _T_2042 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2329:34] - wire _T_2044 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2330:34] - wire _T_2047 = _T_1881 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_2048 = _T_1883 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_2049 = _T_1885 & _T_1036; // @[Mux.scala 27:72] - wire _T_2050 = _T_1889 & _T_1042; // @[Mux.scala 27:72] - wire _T_2051 = _T_1895 & _T_1047; // @[Mux.scala 27:72] - wire _T_2052 = _T_1900 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_2053 = _T_1902 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_2054 = _T_1904 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_2055 = _T_1906 & _T_1056; // @[Mux.scala 27:72] - wire _T_2056 = _T_1909 & _T_1059; // @[Mux.scala 27:72] - wire _T_2057 = _T_1912 & _T_1062; // @[Mux.scala 27:72] - wire _T_2058 = _T_1915 & _T_1065; // @[Mux.scala 27:72] - wire _T_2059 = _T_1918 & _T_1069; // @[Mux.scala 27:72] - wire _T_2060 = _T_1922 & _T_1074; // @[Mux.scala 27:72] - wire _T_2061 = _T_1927 & _T_1077; // @[Mux.scala 27:72] - wire _T_2062 = _T_1930 & _T_1080; // @[Mux.scala 27:72] - wire _T_2063 = _T_1933 & _T_1083; // @[Mux.scala 27:72] - wire _T_2064 = _T_1936 & _T_1086; // @[Mux.scala 27:72] - wire _T_2065 = _T_1939 & _T_1089; // @[Mux.scala 27:72] - wire _T_2066 = _T_1942 & _T_1092; // @[Mux.scala 27:72] - wire _T_2067 = _T_1945 & _T_1095; // @[Mux.scala 27:72] - wire _T_2068 = _T_1948 & _T_1098; // @[Mux.scala 27:72] - wire _T_2069 = _T_1951 & _T_1101; // @[Mux.scala 27:72] - wire _T_2070 = _T_1954 & _T_1106; // @[Mux.scala 27:72] - wire _T_2071 = _T_1959 & _T_1109; // @[Mux.scala 27:72] - wire _T_2072 = _T_1962 & _T_1112; // @[Mux.scala 27:72] - wire _T_2073 = _T_1965 & _T_1115; // @[Mux.scala 27:72] - wire _T_2074 = _T_1968 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_2076 = _T_1972 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_2077 = _T_1974 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_2078 = _T_1976 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_2079 = _T_1978 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_2080 = _T_1980 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_2081 = _T_1982 & _T_1133; // @[Mux.scala 27:72] - wire _T_2082 = _T_1986 & _T_1137; // @[Mux.scala 27:72] - wire _T_2083 = _T_1990 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_2084 = _T_1992 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_2085 = _T_1994 & _T_1145; // @[Mux.scala 27:72] - wire _T_2086 = _T_1998 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2087 = _T_2000 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2088 = _T_2002 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_2089 = _T_2004 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2090 = _T_2006 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2091 = _T_2008 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2092 = _T_2010 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2093 = _T_2012 & _T_1164; // @[Mux.scala 27:72] - wire _T_2094 = _T_2017 & _T_1174; // @[Mux.scala 27:72] - wire _T_2095 = _T_2027 & _T_1177; // @[Mux.scala 27:72] - wire _T_2096 = _T_2030 & _T_1180; // @[Mux.scala 27:72] - wire _T_2097 = _T_2033 & _T_1183; // @[Mux.scala 27:72] - wire _T_2098 = _T_2036 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_2099 = _T_2038 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_2100 = _T_2040 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_2101 = _T_2042 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_2102 = _T_2044 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_2103 = _T_1879 | _T_2047; // @[Mux.scala 27:72] + wire _T_1878 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1880 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1882 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1884 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1888 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1894 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1899 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1901 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1903 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1905 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1908 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1911 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1914 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1917 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1921 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1926 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1929 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1932 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1935 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1938 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1941 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1944 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1947 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1950 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1953 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1958 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1961 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1964 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1967 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1971 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1973 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1975 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1977 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1979 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1981 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1985 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1989 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1991 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1993 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1997 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1999 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_2001 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_2003 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_2005 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_2007 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_2009 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_2011 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_2016 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_2026 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_2029 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_2032 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_2035 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_2037 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_2039 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_2041 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_2043 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_2046 = _T_1880 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2047 = _T_1882 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2048 = _T_1884 & _T_1035; // @[Mux.scala 27:72] + wire _T_2049 = _T_1888 & _T_1041; // @[Mux.scala 27:72] + wire _T_2050 = _T_1894 & _T_1046; // @[Mux.scala 27:72] + wire _T_2051 = _T_1899 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2052 = _T_1901 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2053 = _T_1903 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2054 = _T_1905 & _T_1055; // @[Mux.scala 27:72] + wire _T_2055 = _T_1908 & _T_1058; // @[Mux.scala 27:72] + wire _T_2056 = _T_1911 & _T_1061; // @[Mux.scala 27:72] + wire _T_2057 = _T_1914 & _T_1064; // @[Mux.scala 27:72] + wire _T_2058 = _T_1917 & _T_1068; // @[Mux.scala 27:72] + wire _T_2059 = _T_1921 & _T_1073; // @[Mux.scala 27:72] + wire _T_2060 = _T_1926 & _T_1076; // @[Mux.scala 27:72] + wire _T_2061 = _T_1929 & _T_1079; // @[Mux.scala 27:72] + wire _T_2062 = _T_1932 & _T_1082; // @[Mux.scala 27:72] + wire _T_2063 = _T_1935 & _T_1085; // @[Mux.scala 27:72] + wire _T_2064 = _T_1938 & _T_1088; // @[Mux.scala 27:72] + wire _T_2065 = _T_1941 & _T_1091; // @[Mux.scala 27:72] + wire _T_2066 = _T_1944 & _T_1094; // @[Mux.scala 27:72] + wire _T_2067 = _T_1947 & _T_1097; // @[Mux.scala 27:72] + wire _T_2068 = _T_1950 & _T_1100; // @[Mux.scala 27:72] + wire _T_2069 = _T_1953 & _T_1105; // @[Mux.scala 27:72] + wire _T_2070 = _T_1958 & _T_1108; // @[Mux.scala 27:72] + wire _T_2071 = _T_1961 & _T_1111; // @[Mux.scala 27:72] + wire _T_2072 = _T_1964 & _T_1114; // @[Mux.scala 27:72] + wire _T_2073 = _T_1967 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2075 = _T_1971 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2076 = _T_1973 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2077 = _T_1975 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2078 = _T_1977 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2079 = _T_1979 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2080 = _T_1981 & _T_1132; // @[Mux.scala 27:72] + wire _T_2081 = _T_1985 & _T_1136; // @[Mux.scala 27:72] + wire _T_2082 = _T_1989 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2083 = _T_1991 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2084 = _T_1993 & _T_1144; // @[Mux.scala 27:72] + wire _T_2085 = _T_1997 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2086 = _T_1999 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2087 = _T_2001 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2088 = _T_2003 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2089 = _T_2005 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2090 = _T_2007 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2091 = _T_2009 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2092 = _T_2011 & _T_1163; // @[Mux.scala 27:72] + wire _T_2093 = _T_2016 & _T_1173; // @[Mux.scala 27:72] + wire _T_2094 = _T_2026 & _T_1176; // @[Mux.scala 27:72] + wire _T_2095 = _T_2029 & _T_1179; // @[Mux.scala 27:72] + wire _T_2096 = _T_2032 & _T_1182; // @[Mux.scala 27:72] + wire _T_2097 = _T_2035 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2098 = _T_2037 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2099 = _T_2039 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2100 = _T_2041 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2101 = _T_2043 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2102 = _T_1878 | _T_2046; // @[Mux.scala 27:72] + wire _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72] wire _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72] wire _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72] wire _T_2106 = _T_2105 | _T_2050; // @[Mux.scala 27:72] @@ -52134,8 +52136,8 @@ module csr_tlu( wire _T_2127 = _T_2126 | _T_2071; // @[Mux.scala 27:72] wire _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72] wire _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72] - wire _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72] - wire _T_2131 = _T_2130 | _T_2054; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2053; // @[Mux.scala 27:72] + wire _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72] wire _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72] wire _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72] wire _T_2134 = _T_2133 | _T_2078; // @[Mux.scala 27:72] @@ -52162,187 +52164,187 @@ module csr_tlu( wire _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72] wire _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72] wire _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72] - wire _T_2158 = _T_2157 | _T_2102; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1878 & _T_2158; // @[dec_tlu_ctl.scala 2272:44] - reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2333:53] - reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2334:53] - reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2335:53] - reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2336:53] - reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2337:56] - wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2340:67] - wire _T_2170 = ~_T_85; // @[dec_tlu_ctl.scala 2341:37] - wire [3:0] _T_2172 = _T_2170 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_2179 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2172 & _T_2179; // @[dec_tlu_ctl.scala 2341:86] - wire _T_2181 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2343:67] - wire _T_2182 = perfcnt_halted_d1 & _T_2181; // @[dec_tlu_ctl.scala 2343:65] - wire _T_2183 = ~_T_2182; // @[dec_tlu_ctl.scala 2343:45] - wire _T_2186 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2344:67] - wire _T_2187 = perfcnt_halted_d1 & _T_2186; // @[dec_tlu_ctl.scala 2344:65] - wire _T_2188 = ~_T_2187; // @[dec_tlu_ctl.scala 2344:45] - wire _T_2191 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2345:67] - wire _T_2192 = perfcnt_halted_d1 & _T_2191; // @[dec_tlu_ctl.scala 2345:65] - wire _T_2193 = ~_T_2192; // @[dec_tlu_ctl.scala 2345:45] - wire _T_2196 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2346:67] - wire _T_2197 = perfcnt_halted_d1 & _T_2196; // @[dec_tlu_ctl.scala 2346:65] - wire _T_2198 = ~_T_2197; // @[dec_tlu_ctl.scala 2346:45] - wire _T_2201 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2352:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2201; // @[dec_tlu_ctl.scala 2352:43] - wire _T_2202 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2353:23] - wire _T_2204 = _T_2202 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2353:39] - wire _T_2205 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2353:86] - wire mhpmc3_wr_en1 = _T_2204 & _T_2205; // @[dec_tlu_ctl.scala 2353:66] + wire mhpmc_inc_r_3 = _T_1877 & _T_2157; // @[dec_tlu_ctl.scala 2273:44] + reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2334:53] + reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2335:53] + reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2336:53] + reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2337:53] + reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2338:56] + wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2341:67] + wire _T_2169 = ~_T_85; // @[dec_tlu_ctl.scala 2342:37] + wire [3:0] _T_2171 = _T_2169 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2178 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2171 & _T_2178; // @[dec_tlu_ctl.scala 2342:86] + wire _T_2180 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2344:67] + wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2344:65] + wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2344:45] + wire _T_2185 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2345:67] + wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2345:65] + wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2345:45] + wire _T_2190 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2346:67] + wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[dec_tlu_ctl.scala 2346:65] + wire _T_2192 = ~_T_2191; // @[dec_tlu_ctl.scala 2346:45] + wire _T_2195 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2347:67] + wire _T_2196 = perfcnt_halted_d1 & _T_2195; // @[dec_tlu_ctl.scala 2347:65] + wire _T_2197 = ~_T_2196; // @[dec_tlu_ctl.scala 2347:45] + wire _T_2200 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2353:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2200; // @[dec_tlu_ctl.scala 2353:43] + wire _T_2201 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2354:23] + wire _T_2203 = _T_2201 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2354:39] + wire _T_2204 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2354:86] + wire mhpmc3_wr_en1 = _T_2203 & _T_2204; // @[dec_tlu_ctl.scala 2354:66] reg [31:0] mhpmc3h; // @[lib.scala 374:16] reg [31:0] mhpmc3; // @[lib.scala 374:16] - wire [63:0] _T_2208 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] - wire [63:0] _T_2209 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2208 + _T_2209; // @[dec_tlu_ctl.scala 2357:49] - wire _T_2217 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2362:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2217; // @[dec_tlu_ctl.scala 2362:44] - wire _T_2223 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2371:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2223; // @[dec_tlu_ctl.scala 2371:43] - wire _T_2226 = _T_2202 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2372:39] - wire _T_2227 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2372:86] - wire mhpmc4_wr_en1 = _T_2226 & _T_2227; // @[dec_tlu_ctl.scala 2372:66] + wire [63:0] _T_2207 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2208 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2207 + _T_2208; // @[dec_tlu_ctl.scala 2358:49] + wire _T_2216 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2363:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2216; // @[dec_tlu_ctl.scala 2363:44] + wire _T_2222 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2372:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2222; // @[dec_tlu_ctl.scala 2372:43] + wire _T_2225 = _T_2201 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2373:39] + wire _T_2226 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2373:86] + wire mhpmc4_wr_en1 = _T_2225 & _T_2226; // @[dec_tlu_ctl.scala 2373:66] reg [31:0] mhpmc4h; // @[lib.scala 374:16] reg [31:0] mhpmc4; // @[lib.scala 374:16] - wire [63:0] _T_2230 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] - wire [63:0] _T_2231 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2230 + _T_2231; // @[dec_tlu_ctl.scala 2377:49] - wire _T_2240 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2381:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2240; // @[dec_tlu_ctl.scala 2381:44] - wire _T_2246 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2390:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2246; // @[dec_tlu_ctl.scala 2390:43] - wire _T_2249 = _T_2202 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2391:39] - wire _T_2250 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2391:86] - wire mhpmc5_wr_en1 = _T_2249 & _T_2250; // @[dec_tlu_ctl.scala 2391:66] + wire [63:0] _T_2229 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2230 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2229 + _T_2230; // @[dec_tlu_ctl.scala 2378:49] + wire _T_2239 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2382:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2239; // @[dec_tlu_ctl.scala 2382:44] + wire _T_2245 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2391:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2245; // @[dec_tlu_ctl.scala 2391:43] + wire _T_2248 = _T_2201 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2392:39] + wire _T_2249 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2392:86] + wire mhpmc5_wr_en1 = _T_2248 & _T_2249; // @[dec_tlu_ctl.scala 2392:66] reg [31:0] mhpmc5h; // @[lib.scala 374:16] reg [31:0] mhpmc5; // @[lib.scala 374:16] - wire [63:0] _T_2253 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] - wire [63:0] _T_2254 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2253 + _T_2254; // @[dec_tlu_ctl.scala 2394:49] - wire _T_2262 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2399:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2262; // @[dec_tlu_ctl.scala 2399:44] - wire _T_2268 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2408:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2268; // @[dec_tlu_ctl.scala 2408:43] - wire _T_2271 = _T_2202 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2409:39] - wire _T_2272 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2409:86] - wire mhpmc6_wr_en1 = _T_2271 & _T_2272; // @[dec_tlu_ctl.scala 2409:66] + wire [63:0] _T_2252 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2253 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2252 + _T_2253; // @[dec_tlu_ctl.scala 2395:49] + wire _T_2261 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2400:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2261; // @[dec_tlu_ctl.scala 2400:44] + wire _T_2267 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2409:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2267; // @[dec_tlu_ctl.scala 2409:43] + wire _T_2270 = _T_2201 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2410:39] + wire _T_2271 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2410:86] + wire mhpmc6_wr_en1 = _T_2270 & _T_2271; // @[dec_tlu_ctl.scala 2410:66] reg [31:0] mhpmc6h; // @[lib.scala 374:16] reg [31:0] mhpmc6; // @[lib.scala 374:16] - wire [63:0] _T_2275 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] - wire [63:0] _T_2276 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2275 + _T_2276; // @[dec_tlu_ctl.scala 2412:49] - wire _T_2284 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2417:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2284; // @[dec_tlu_ctl.scala 2417:44] - wire _T_2290 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2428:56] - wire _T_2292 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2428:102] - wire _T_2293 = _T_2290 | _T_2292; // @[dec_tlu_ctl.scala 2428:71] - wire _T_2296 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2430:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2296; // @[dec_tlu_ctl.scala 2430:41] - wire _T_2300 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2437:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2300; // @[dec_tlu_ctl.scala 2437:41] - wire _T_2304 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2444:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2304; // @[dec_tlu_ctl.scala 2444:41] - wire _T_2308 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2451:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2308; // @[dec_tlu_ctl.scala 2451:41] - wire _T_2312 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2468:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2312; // @[dec_tlu_ctl.scala 2468:48] - wire _T_2324 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2483:51] - wire _T_2325 = _T_2324 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2483:78] - wire _T_2326 = _T_2325 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2483:104] - wire _T_2327 = _T_2326 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2483:130] - wire _T_2328 = _T_2327 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2484:32] - reg _T_2331; // @[dec_tlu_ctl.scala 2486:62] - wire _T_2332 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2487:91] - wire _T_2333 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2487:137] - wire _T_2334 = io_trigger_hit_r_d1 & _T_2333; // @[dec_tlu_ctl.scala 2487:135] - reg _T_2336; // @[dec_tlu_ctl.scala 2487:62] - reg [4:0] _T_2337; // @[dec_tlu_ctl.scala 2488:62] - reg _T_2338; // @[dec_tlu_ctl.scala 2489:62] - wire [31:0] _T_2344 = {io_core_id,4'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2353 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2358 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2371 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2384 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2396 = {io_mepc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2401 = {28'h0,mscause}; // @[Cat.scala 29:58] - wire [31:0] _T_2409 = {meivt,10'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2412 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2415 = {28'h0,meicurpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2418 = {28'h0,meicidpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2421 = {28'h0,meipt}; // @[Cat.scala 29:58] - wire [31:0] _T_2424 = {23'h0,mcgc}; // @[Cat.scala 29:58] - wire [31:0] _T_2427 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2431 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] - wire [31:0] _T_2433 = {io_dpc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2449 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2452 = {30'h0,mtsel}; // @[Cat.scala 29:58] - wire [31:0] _T_2481 = {26'h0,mfdht}; // @[Cat.scala 29:58] - wire [31:0] _T_2484 = {30'h0,mfdhs}; // @[Cat.scala 29:58] - wire [31:0] _T_2487 = {22'h0,mhpme3}; // @[Cat.scala 29:58] - wire [31:0] _T_2490 = {22'h0,mhpme4}; // @[Cat.scala 29:58] - wire [31:0] _T_2493 = {22'h0,mhpme5}; // @[Cat.scala 29:58] - wire [31:0] _T_2496 = {22'h0,mhpme6}; // @[Cat.scala 29:58] - wire [31:0] _T_2499 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire [31:0] _T_2502 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2505 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2506 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2507 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2508 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2509 = io_csr_pkt_csr_mhartid ? _T_2344 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2510 = io_csr_pkt_csr_mstatus ? _T_2353 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2511 = io_csr_pkt_csr_mtvec ? _T_2358 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2512 = io_csr_pkt_csr_mip ? _T_2371 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2513 = io_csr_pkt_csr_mie ? _T_2384 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2514 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2515 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2516 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2517 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2518 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2519 = io_csr_pkt_csr_mepc ? _T_2396 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2520 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2521 = io_csr_pkt_csr_mscause ? _T_2401 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2522 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2523 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2524 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2525 = io_csr_pkt_csr_meivt ? _T_2409 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2526 = io_csr_pkt_csr_meihap ? _T_2412 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2527 = io_csr_pkt_csr_meicurpl ? _T_2415 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2528 = io_csr_pkt_csr_meicidpl ? _T_2418 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2529 = io_csr_pkt_csr_meipt ? _T_2421 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2530 = io_csr_pkt_csr_mcgc ? _T_2424 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2531 = io_csr_pkt_csr_mfdc ? _T_2427 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2532 = io_csr_pkt_csr_dcsr ? _T_2431 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2533 = io_csr_pkt_csr_dpc ? _T_2433 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2535 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2536 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2537 = io_csr_pkt_csr_dicawics ? _T_2449 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2538 = io_csr_pkt_csr_mtsel ? _T_2452 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2540 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2541 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2542 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2543 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2551 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2552 = io_csr_pkt_csr_mfdht ? _T_2481 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2553 = io_csr_pkt_csr_mfdhs ? _T_2484 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme3 ? _T_2487 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme4 ? _T_2490 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme5 ? _T_2493 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2557 = io_csr_pkt_csr_mhpme6 ? _T_2496 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2558 = io_csr_pkt_csr_mcountinhibit ? _T_2499 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2559 = io_csr_pkt_csr_mpmc ? _T_2502 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2560 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2561 = _T_2505 | _T_2506; // @[Mux.scala 27:72] + wire [63:0] _T_2274 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2275 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2274 + _T_2275; // @[dec_tlu_ctl.scala 2413:49] + wire _T_2283 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2418:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2283; // @[dec_tlu_ctl.scala 2418:44] + wire _T_2289 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2429:56] + wire _T_2291 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2429:102] + wire _T_2292 = _T_2289 | _T_2291; // @[dec_tlu_ctl.scala 2429:71] + wire _T_2295 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2431:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2431:41] + wire _T_2299 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2438:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2438:41] + wire _T_2303 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2445:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2445:41] + wire _T_2307 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2452:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2307; // @[dec_tlu_ctl.scala 2452:41] + wire _T_2311 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2469:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2311; // @[dec_tlu_ctl.scala 2469:48] + wire _T_2323 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2484:51] + wire _T_2324 = _T_2323 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2484:78] + wire _T_2325 = _T_2324 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2484:104] + wire _T_2326 = _T_2325 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2484:130] + wire _T_2327 = _T_2326 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2485:32] + reg _T_2330; // @[dec_tlu_ctl.scala 2487:62] + wire _T_2331 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2488:91] + wire _T_2332 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2488:137] + wire _T_2333 = io_trigger_hit_r_d1 & _T_2332; // @[dec_tlu_ctl.scala 2488:135] + reg _T_2335; // @[dec_tlu_ctl.scala 2488:62] + reg [4:0] _T_2336; // @[dec_tlu_ctl.scala 2489:62] + reg _T_2337; // @[dec_tlu_ctl.scala 2490:62] + wire [31:0] _T_2343 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2352 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2357 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2370 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2383 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2395 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2400 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2408 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2411 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2414 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2417 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2420 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2423 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2426 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2430 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2432 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2448 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2451 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2480 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2483 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2486 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2489 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2492 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2495 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2498 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2501 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2504 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2505 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mhartid ? _T_2343 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mstatus ? _T_2352 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_mtvec ? _T_2357 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_mip ? _T_2370 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mie ? _T_2383 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_mepc ? _T_2395 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_mscause ? _T_2400 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_meivt ? _T_2408 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_meihap ? _T_2411 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_meicurpl ? _T_2414 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_meicidpl ? _T_2417 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_meipt ? _T_2420 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_mcgc ? _T_2423 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_mfdc ? _T_2426 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_dcsr ? _T_2430 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_dpc ? _T_2432 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_dicawics ? _T_2448 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_mtsel ? _T_2451 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_csr_pkt_csr_mfdht ? _T_2480 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = io_csr_pkt_csr_mfdhs ? _T_2483 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = io_csr_pkt_csr_mhpme3 ? _T_2486 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme4 ? _T_2489 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme5 ? _T_2492 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme6 ? _T_2495 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = io_csr_pkt_csr_mcountinhibit ? _T_2498 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = io_csr_pkt_csr_mpmc ? _T_2501 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = _T_2504 | _T_2505; // @[Mux.scala 27:72] + wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] wire [31:0] _T_2564 = _T_2563 | _T_2509; // @[Mux.scala 27:72] @@ -52395,7 +52397,6 @@ module csr_tlu( wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72] wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72] wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72] - wire [31:0] _T_2614 = _T_2613 | _T_2559; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -52606,54 +52607,54 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_764,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2153:56] - assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2156:41] - assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2164:41] - assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2165:41] - assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2229:40] - assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2230:43] - assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2247:51] - assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2229:40] - assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2230:43] - assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2247:51] - assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2229:40] - assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2230:43] - assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2247:51] - assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2229:40] - assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2230:43] - assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2231:40] - assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2232:40] - assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2233:40] - assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2234:40] - assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2247:51] - assign io_dec_tlu_int_valid_wb1 = _T_2338; // @[dec_tlu_ctl.scala 2489:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2487:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2331; // @[dec_tlu_ctl.scala 2486:30] - assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2491:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2488:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2183; // @[dec_tlu_ctl.scala 2343:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2188; // @[dec_tlu_ctl.scala 2344:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2193; // @[dec_tlu_ctl.scala 2345:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2198; // @[dec_tlu_ctl.scala 2346:22] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_763,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2154:56] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2157:41] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2165:41] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2166:41] + assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2230:40] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2231:43] + assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2248:51] + assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2230:40] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2231:43] + assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2248:51] + assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2230:40] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2231:43] + assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2248:51] + assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2230:40] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2231:43] + assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2232:40] + assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2248:51] + assign io_dec_tlu_int_valid_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2490:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2335; // @[dec_tlu_ctl.scala 2488:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2330; // @[dec_tlu_ctl.scala 2487:30] + assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2492:24] + assign io_dec_tlu_exc_cause_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2489:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2182; // @[dec_tlu_ctl.scala 2344:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2187; // @[dec_tlu_ctl.scala 2345:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2192; // @[dec_tlu_ctl.scala 2346:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2197; // @[dec_tlu_ctl.scala 2347:22] assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1716:31] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1717:31] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1719:31] assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1721:31] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1722:31] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1723:31] - assign io_dec_csr_rddata_d = _T_2614 | _T_2560; // @[dec_tlu_ctl.scala 2496:21] + assign io_dec_csr_rddata_d = _T_2613 | _T_2559; // @[dec_tlu_ctl.scala 2497:21] assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1766:39] assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1775:24] assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2004:19] @@ -52680,10 +52681,10 @@ module csr_tlu( assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1823:22] assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1931:16] assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2068:9] - assign io_mtdata1_t_0 = _T_873; // @[dec_tlu_ctl.scala 2224:39] - assign io_mtdata1_t_1 = _T_874; // @[dec_tlu_ctl.scala 2224:39] - assign io_mtdata1_t_2 = _T_875; // @[dec_tlu_ctl.scala 2224:39] - assign io_mtdata1_t_3 = _T_876; // @[dec_tlu_ctl.scala 2224:39] + assign io_mtdata1_t_0 = _T_872; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_1 = _T_873; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_2 = _T_874; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_3 = _T_875; // @[dec_tlu_ctl.scala 2225:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -52751,16 +52752,16 @@ module csr_tlu( assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_22_io_en = _T_972 & _T_808; // @[lib.scala 371:17] + assign rvclkhdr_22_io_en = _T_971 & _T_807; // @[lib.scala 371:17] assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_23_io_en = _T_981 & _T_817; // @[lib.scala 371:17] + assign rvclkhdr_23_io_en = _T_980 & _T_816; // @[lib.scala 371:17] assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_24_io_en = _T_990 & _T_826; // @[lib.scala 371:17] + assign rvclkhdr_24_io_en = _T_989 & _T_825; // @[lib.scala 371:17] assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_25_io_en = _T_999 & _T_835; // @[lib.scala 371:17] + assign rvclkhdr_25_io_en = _T_998 & _T_834; // @[lib.scala 371:17] assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17] @@ -52787,7 +52788,7 @@ module csr_tlu( assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17] assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_34_io_en = _T_2328 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_34_io_en = _T_2327 | io_clk_override; // @[lib.scala 345:16] assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -52907,7 +52908,7 @@ initial begin _RAND_40 = {1{`RANDOM}}; dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - _T_759 = _RAND_41[6:0]; + _T_758 = _RAND_41[31:0]; _RAND_42 = {1{`RANDOM}}; icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; @@ -52915,13 +52916,13 @@ initial begin _RAND_44 = {1{`RANDOM}}; mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_873 = _RAND_45[9:0]; + _T_872 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_874 = _RAND_46[9:0]; + _T_873 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_875 = _RAND_47[9:0]; + _T_874 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - _T_876 = _RAND_48[9:0]; + _T_875 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; @@ -52965,13 +52966,13 @@ initial begin _RAND_69 = {1{`RANDOM}}; mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2331 = _RAND_70[0:0]; + _T_2330 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2336 = _RAND_71[0:0]; + _T_2335 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2337 = _RAND_72[4:0]; + _T_2336 = _RAND_72[4:0]; _RAND_73 = {1{`RANDOM}}; - _T_2338 = _RAND_73[0:0]; + _T_2337 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -53097,7 +53098,7 @@ initial begin dicad0h = 32'h0; end if (reset) begin - _T_759 = 7'h0; + _T_758 = 32'h0; end if (reset) begin icache_rd_valid_f = 1'h0; @@ -53108,6 +53109,9 @@ initial begin if (reset) begin mtsel = 2'h0; end + if (reset) begin + _T_872 = 10'h0; + end if (reset) begin _T_873 = 10'h0; end @@ -53117,9 +53121,6 @@ initial begin if (reset) begin _T_875 = 10'h0; end - if (reset) begin - _T_876 = 10'h0; - end if (reset) begin mtdata2_t_0 = 32'h0; end @@ -53184,16 +53185,16 @@ initial begin mhpmc6 = 32'h0; end if (reset) begin - _T_2331 = 1'h0; + _T_2330 = 1'h0; end if (reset) begin - _T_2336 = 1'h0; + _T_2335 = 1'h0; end if (reset) begin - _T_2337 = 5'h0; + _T_2336 = 5'h0; end if (reset) begin - _T_2338 = 1'h0; + _T_2337 = 1'h0; end `endif // RANDOMIZE end // initial @@ -53524,12 +53525,12 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_759 <= 7'h0; - end else if (_T_757) begin + _T_758 <= 32'h0; + end else if (_T_756) begin if (_T_752) begin - _T_759 <= io_dec_csr_wrdata_r[6:0]; + _T_758 <= io_dec_csr_wrdata_r; end else begin - _T_759 <= io_ifu_ic_debug_rd_data[70:64]; + _T_758 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; end end end @@ -53537,14 +53538,14 @@ end // initial if (reset) begin icache_rd_valid_f <= 1'h0; end else begin - icache_rd_valid_f <= _T_769 & _T_771; + icache_rd_valid_f <= _T_768 & _T_770; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin icache_wr_valid_f <= 1'h0; end else begin - icache_wr_valid_f <= _T_663 & _T_774; + icache_wr_valid_f <= _T_663 & _T_773; end end always @(posedge io_csr_wr_clk or posedge reset) begin @@ -53556,38 +53557,38 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_873 <= 10'h0; + _T_872 <= 10'h0; end else if (wr_mtdata1_t_r_0) begin + _T_872 <= tdata_wrdata_r; + end else begin + _T_872 <= _T_843; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_873 <= 10'h0; + end else if (wr_mtdata1_t_r_1) begin _T_873 <= tdata_wrdata_r; end else begin - _T_873 <= _T_844; + _T_873 <= _T_852; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin _T_874 <= 10'h0; - end else if (wr_mtdata1_t_r_1) begin + end else if (wr_mtdata1_t_r_2) begin _T_874 <= tdata_wrdata_r; end else begin - _T_874 <= _T_853; + _T_874 <= _T_861; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin _T_875 <= 10'h0; - end else if (wr_mtdata1_t_r_2) begin + end else if (wr_mtdata1_t_r_3) begin _T_875 <= tdata_wrdata_r; end else begin - _T_875 <= _T_862; - end - end - always @(posedge io_active_clk or posedge reset) begin - if (reset) begin - _T_876 <= 10'h0; - end else if (wr_mtdata1_t_r_3) begin - _T_876 <= tdata_wrdata_r; - end else begin - _T_876 <= _T_871; + _T_875 <= _T_870; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin @@ -53622,7 +53623,7 @@ end // initial if (reset) begin mhpme3 <= 10'h0; end else if (wr_mhpme3_r) begin - if (_T_2293) begin + if (_T_2292) begin mhpme3 <= 10'h204; end else begin mhpme3 <= io_dec_csr_wrdata_r[9:0]; @@ -53633,7 +53634,7 @@ end // initial if (reset) begin mhpme4 <= 10'h0; end else if (wr_mhpme4_r) begin - if (_T_2293) begin + if (_T_2292) begin mhpme4 <= 10'h204; end else begin mhpme4 <= io_dec_csr_wrdata_r[9:0]; @@ -53644,7 +53645,7 @@ end // initial if (reset) begin mhpme5 <= 10'h0; end else if (wr_mhpme5_r) begin - if (_T_2293) begin + if (_T_2292) begin mhpme5 <= 10'h204; end else begin mhpme5 <= io_dec_csr_wrdata_r[9:0]; @@ -53655,7 +53656,7 @@ end // initial if (reset) begin mhpme6 <= 10'h0; end else if (wr_mhpme6_r) begin - if (_T_2293) begin + if (_T_2292) begin mhpme6 <= 10'h204; end else begin mhpme6 <= io_dec_csr_wrdata_r[9:0]; @@ -53666,28 +53667,28 @@ end // initial if (reset) begin mhpmc_inc_r_d1_0 <= 1'h0; end else begin - mhpmc_inc_r_d1_0 <= _T_1026 & _T_1306; + mhpmc_inc_r_d1_0 <= _T_1025 & _T_1305; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_1 <= 1'h0; end else begin - mhpmc_inc_r_d1_1 <= _T_1310 & _T_1590; + mhpmc_inc_r_d1_1 <= _T_1309 & _T_1589; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_2 <= 1'h0; end else begin - mhpmc_inc_r_d1_2 <= _T_1594 & _T_1874; + mhpmc_inc_r_d1_2 <= _T_1593 & _T_1873; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_3 <= 1'h0; end else begin - mhpmc_inc_r_d1_3 <= _T_1878 & _T_2158; + mhpmc_inc_r_d1_3 <= _T_1877 & _T_2157; end end always @(posedge io_free_clk or posedge reset) begin @@ -53771,30 +53772,30 @@ end // initial end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2331 <= 1'h0; + _T_2330 <= 1'h0; end else begin - _T_2331 <= io_i0_valid_wb; + _T_2330 <= io_i0_valid_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2336 <= 1'h0; + _T_2335 <= 1'h0; end else begin - _T_2336 <= _T_2332 | _T_2334; + _T_2335 <= _T_2331 | _T_2333; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2337 <= 5'h0; + _T_2336 <= 5'h0; end else begin - _T_2337 <= io_exc_cause_wb; + _T_2336 <= io_exc_cause_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2338 <= 1'h0; + _T_2337 <= 1'h0; end else begin - _T_2338 <= io_interrupt_valid_r_d1; + _T_2337 <= io_interrupt_valid_r_d1; end end endmodule @@ -53868,371 +53869,371 @@ module dec_decode_csr_read( output io_csr_pkt_postsync, output io_csr_pkt_legal ); - wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2568:198] - wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:165] - wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2568:198] - wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2568:129] - wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2636:81] - wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2636:121] - wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2636:155] - wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2637:97] - wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2638:81] - wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2638:121] - wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2638:162] - wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2568:198] - wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2639:105] - wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2639:145] - wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2568:198] - wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2568:198] - wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2641:81] - wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2641:129] - wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2642:105] - wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2642:153] - wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2643:105] - wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2643:153] - wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2644:105] - wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2644:161] - wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2645:105] - wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2645:161] - wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2646:97] - wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2646:153] - wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2647:105] - wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2647:161] - wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2648:105] - wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2648:161] - wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2649:105] - wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2649:161] - wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2650:105] - wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2650:161] - wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2651:105] - wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2651:153] - wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2652:113] - wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2652:161] - wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2653:97] - wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2653:153] - wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2654:113] - wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2568:198] - assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:57] - assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2571:57] - assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2572:57] - assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2573:57] - assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:57] - assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2575:57] - assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2576:57] - assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2577:65] - assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2578:65] - assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2579:57] - assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2580:57] - assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2581:57] - assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2582:57] - assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2583:57] - assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2584:57] - assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2585:57] - assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2586:57] - assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2587:57] - assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2588:57] - assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2589:57] - assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2590:57] - assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2591:57] - assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2592:57] - assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2593:57] - assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2594:57] - assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2595:57] - assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2596:57] - assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2597:57] - assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2598:57] - assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2599:65] - assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2600:57] - assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2601:57] - assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2602:57] - assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2603:57] - assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2604:57] - assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2605:57] - assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2606:57] - assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2607:57] - assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2608:57] - assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2609:57] - assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2610:57] - assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2611:57] - assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2612:57] - assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2613:57] - assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2614:57] - assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2615:49] - assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2616:57] - assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2617:57] - assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2618:57] - assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2619:57] - assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2620:57] - assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2621:57] - assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2622:57] - assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2624:57] - assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2626:57] - assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2627:57] - assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2628:57] - assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2629:57] - assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2630:57] - assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2631:57] - assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2632:57] - assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2633:57] - assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2634:57] - assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2635:57] - assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2636:34] - assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2638:30] - assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2641:26] + wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2569:198] + wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:165] + wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2569:198] + wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2569:129] + wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2637:81] + wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2637:121] + wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2637:155] + wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2638:97] + wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2639:81] + wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2639:121] + wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2639:162] + wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2569:198] + wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2640:105] + wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2640:145] + wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2569:198] + wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2569:198] + wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2642:81] + wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2642:129] + wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2643:105] + wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2643:153] + wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2644:105] + wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2644:153] + wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2645:105] + wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2645:161] + wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2646:105] + wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2646:161] + wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2647:97] + wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2647:153] + wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2648:105] + wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2648:161] + wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2649:105] + wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2649:161] + wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2650:105] + wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2650:161] + wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2651:105] + wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2651:161] + wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2652:105] + wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2652:153] + wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2653:113] + wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2653:161] + wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2654:97] + wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2654:153] + wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2655:113] + wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2569:198] + assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2571:57] + assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2572:57] + assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2573:57] + assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2574:57] + assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2575:57] + assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2576:57] + assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2577:57] + assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2578:65] + assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2579:65] + assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2580:57] + assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2581:57] + assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2582:57] + assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2583:57] + assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2584:57] + assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2585:57] + assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2586:57] + assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2587:57] + assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2588:57] + assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2589:57] + assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2590:57] + assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2591:57] + assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2592:57] + assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2593:57] + assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2594:57] + assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2595:57] + assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2596:57] + assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2597:57] + assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2598:57] + assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2599:57] + assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2600:65] + assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2601:57] + assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2602:57] + assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2603:57] + assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2604:57] + assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2605:57] + assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2606:57] + assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2607:57] + assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2608:57] + assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2609:57] + assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2610:57] + assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2611:57] + assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2612:57] + assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2613:57] + assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2614:57] + assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2615:57] + assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2616:49] + assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2617:57] + assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2618:57] + assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2619:57] + assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2620:57] + assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2621:57] + assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2622:57] + assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2623:57] + assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2625:57] + assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2627:57] + assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2628:57] + assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2629:57] + assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2630:57] + assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2631:57] + assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2632:57] + assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2633:57] + assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2634:57] + assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2635:57] + assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2636:57] + assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2637:34] + assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2639:30] + assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2642:26] endmodule module dec_tlu_ctl( input clock, @@ -61898,7 +61899,6 @@ module exu( input io_dec_exu_ib_exu_dec_debug_wdata_rs1_d, input [31:0] io_dec_exu_gpr_exu_gpr_i0_rs1_d, input [31:0] io_dec_exu_gpr_exu_gpr_i0_rs2_d, - output [7:0] io_exu_bp_exu_i0_br_index_r, output [7:0] io_exu_bp_exu_i0_br_fghr_r, output io_exu_bp_exu_i0_br_way_r, output io_exu_bp_exu_mp_pkt_bits_misp, @@ -62440,7 +62440,6 @@ module exu( assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 183:47] assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 184:47] assign io_dec_exu_tlu_exu_exu_npc_r = _T_188[30:0]; // @[exu.scala 233:66] - assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 211:31] assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 209:58] assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 204:43] assign io_exu_bp_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[exu.scala 219:48] @@ -81259,7 +81258,6 @@ module quasar( wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 77:19] wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 77:19] wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 77:19] - wire [7:0] exu_io_exu_bp_exu_i0_br_index_r; // @[quasar.scala 77:19] wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 77:19] wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 77:19] wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 77:19] @@ -82066,7 +82064,6 @@ module quasar( .io_dec_exu_ib_exu_dec_debug_wdata_rs1_d(exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d), .io_dec_exu_gpr_exu_gpr_i0_rs1_d(exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d), .io_dec_exu_gpr_exu_gpr_i0_rs2_d(exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d), - .io_exu_bp_exu_i0_br_index_r(exu_io_exu_bp_exu_i0_br_index_r), .io_exu_bp_exu_i0_br_fghr_r(exu_io_exu_bp_exu_i0_br_fghr_r), .io_exu_bp_exu_i0_br_way_r(exu_io_exu_bp_exu_i0_br_way_r), .io_exu_bp_exu_mp_pkt_bits_misp(exu_io_exu_bp_exu_mp_pkt_bits_misp), @@ -82339,76 +82336,76 @@ module quasar( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 285:27] - assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 285:27] - assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 285:27] - assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 285:27] - assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 285:27] - assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 285:27] - assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 285:27] - assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 285:27] - assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 285:27] - assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 285:27] - assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 285:27] - assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 285:27] - assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 285:27] - assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 285:27] - assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 285:27] - assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 284:27] - assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 284:27] - assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 284:27] - assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 284:27] - assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 283:27] - assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 283:27] - assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 283:27] - assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 283:27] - assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 283:27] - assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 283:27] - assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 283:27] - assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 283:27] - assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 283:27] - assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 283:27] - assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 283:27] - assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 282:27] - assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 282:27] - assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 282:27] - assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 282:27] - assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 282:27] - assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 282:27] - assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 282:27] - assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 282:27] - assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 282:27] - assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 282:27] + assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 284:27] + assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 284:27] + assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 284:27] + assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 284:27] + assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 284:27] + assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 284:27] + assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 283:27] + assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 283:27] + assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 282:27] + assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 282:27] + assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 282:27] + assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 282:27] + assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 282:27] + assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 282:27] + assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 282:27] + assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 281:27] + assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 281:27] + assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 281:27] + assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 281:27] + assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 281:27] + assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 281:27] + assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 281:27] + assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 281:27] + assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 281:27] + assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 281:27] assign io_core_rst_l = reset & _T_2; // @[quasar.scala 82:17] - assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 219:19] - assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 219:19] - assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 219:19] - assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 219:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 219:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 219:19] - assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 219:19] - assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 222:24] - assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 223:23] - assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 224:31] - assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 225:21] - assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 226:24] - assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 227:20] - assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 228:26] - assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 229:25] - assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 230:24] - assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 231:25] - assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 232:23] - assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 233:23] - assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 234:23] - assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 235:23] - assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 239:11] - assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 239:11] - assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 239:11] - assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 239:11] - assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 239:11] - assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 239:11] - assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 239:11] - assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 239:11] + assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 218:19] + assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 218:19] + assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 218:19] + assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 218:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 218:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 218:19] + assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 218:19] + assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 221:24] + assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 222:23] + assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 223:31] + assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 224:21] + assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 225:24] + assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 226:20] + assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 227:26] + assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 228:25] + assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 229:24] + assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 230:25] + assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 231:23] + assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 232:23] + assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 233:23] + assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 234:23] + assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 238:11] + assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 238:11] + assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 238:11] + assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 238:11] + assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 238:11] + assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 238:11] + assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 238:11] + assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 238:11] assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 100:13] assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 100:13] assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 100:13] @@ -82430,7 +82427,7 @@ module quasar( assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 101:15] assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 101:15] assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 101:15] - assign io_dmi_reg_rdata = dbg_io_dmi_reg_rdata; // @[quasar.scala 236:20] + assign io_dmi_reg_rdata = dbg_io_dmi_reg_rdata; // @[quasar.scala 235:20] assign ifu_clock = clock; assign ifu_reset = io_core_rst_l; // @[quasar.scala 90:13] assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 95:26] @@ -82457,8 +82454,8 @@ module quasar( assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 88:18] assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 88:18] assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 88:18] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_exu_bp_exu_i0_br_index_r; // @[quasar.scala 102:25] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 102:25] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 102:25 quasar.scala 104:43] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 102:25 quasar.scala 103:42] assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 102:25] assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 102:25] assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 102:25] @@ -82481,11 +82478,11 @@ module quasar( assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 100:13] assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 100:13] assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 100:13] - assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 284:27] - assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 284:27] - assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 284:27] - assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 284:27] - assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 284:27] + assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 283:27] + assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 283:27] assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 98:25] assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 99:18] assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 99:18] @@ -82610,36 +82607,36 @@ module quasar( assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 125:18] assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 125:18] assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 125:18] - assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 217:28] - assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 217:28] - assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 217:28] - assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 217:28] + assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 216:28] + assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 216:28] + assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 216:28] + assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 216:28] assign dbg_clock = clock; - assign dbg_reset = io_core_rst_l; // @[quasar.scala 176:13] - assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 177:26] - assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 178:28] - assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 179:28] - assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 180:29] - assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 181:29] - assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 182:34] - assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 183:29] - assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 184:21] - assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 185:23] - assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 186:24] - assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 187:24] - assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 283:27] - assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 283:27] - assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 283:27] - assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 283:27] - assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 283:27] - assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 283:27] - assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 283:27] - assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 283:27] - assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 201:26] - assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 188:25] - assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 189:20] - assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 190:23] - assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 191:20] + assign dbg_reset = reset; + assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 176:26] + assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 177:28] + assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 178:28] + assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 179:29] + assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 180:29] + assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 181:34] + assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 182:29] + assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 183:21] + assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 184:23] + assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 185:24] + assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 186:24] + assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 282:27] + assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 282:27] + assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 200:26] + assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 187:25] + assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 188:20] + assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 189:23] + assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 190:20] assign exu_clock = clock; assign exu_reset = io_core_rst_l; // @[quasar.scala 152:13] assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 153:20] @@ -82718,24 +82715,24 @@ module quasar( assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 171:18] assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 171:18] assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 171:18] - assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 216:28] + assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 215:28] assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 163:18] assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 163:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 122:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 122:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 122:18] - assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 239:11] - assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 239:11] - assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 285:27] - assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 285:27] - assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 285:27] - assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 285:27] - assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 285:27] - assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 285:27] - assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 285:27] - assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 285:27] - assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 285:27] - assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 285:27] + assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 238:11] + assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 238:11] + assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 284:27] + assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 284:27] + assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 284:27] + assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 284:27] + assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 284:27] + assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 284:27] + assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 284:27] + assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 284:27] + assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 284:27] + assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 284:27] assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 159:32] assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 160:35] assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 161:29] @@ -82777,52 +82774,52 @@ module quasar( assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 172:20] assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 173:19] assign pic_ctrl_inst_clock = clock; - assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 211:23] - assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 210:30] - assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 212:29] - assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 213:31] - assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 214:33] - assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 215:34] - assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 216:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 216:28] - assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 216:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 216:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 216:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 216:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 217:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 217:28] + assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 210:23] + assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 209:30] + assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 211:29] + assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 212:31] + assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 213:33] + assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 214:34] + assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 215:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 215:28] + assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 215:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 215:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 215:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 215:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 216:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 216:28] assign dma_ctrl_clock = clock; - assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 195:18] - assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 196:24] - assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 197:30] - assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 198:28] - assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 199:25] - assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 202:28] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 200:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 200:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 200:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 200:23] - assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 200:23] - assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 201:26] + assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 194:18] + assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 195:24] + assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 196:30] + assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 197:28] + assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 198:25] + assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 201:28] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 199:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 199:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 199:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 199:23] + assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 199:23] + assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 200:26] assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 125:18] - assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 203:31] - assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 207:34] - assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 204:29] - assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 205:30] - assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 206:26] - assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 282:27] - assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 282:27] + assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 202:31] + assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 206:34] + assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 203:29] + assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 204:30] + assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 205:26] + assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 281:27] + assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 281:27] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 171:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 171:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 171:18] diff --git a/src/main/scala/dec/dec_tlu_ctl.scala b/src/main/scala/dec/dec_tlu_ctl.scala index 030d289e..fb626d31 100644 --- a/src/main/scala/dec/dec_tlu_ctl.scala +++ b/src/main/scala/dec/dec_tlu_ctl.scala @@ -2125,7 +2125,8 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm val dicad1_raw = WireInit(UInt(7.W),0.U) val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) - val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r(6,0), io.ifu_ic_debug_rd_data(70,64)) + val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(70,64)) + dontTouch(dicad1_ns) dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} dicad1 := Cat(0.U(25.W), dicad1_raw) @@ -2497,7 +2498,7 @@ for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)} io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W), io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W), io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W), - io.csr_pkt.csr_mimpid.asBool -> 0x1.U(32.W), + io.csr_pkt.csr_mimpid.asBool -> 0x2.U(32.W), io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)), io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)), io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)), diff --git a/src/main/scala/quasar.scala b/src/main/scala/quasar.scala index a50b1524..0d59507e 100644 --- a/src/main/scala/quasar.scala +++ b/src/main/scala/quasar.scala @@ -100,8 +100,8 @@ class quasar extends Module with RequireAsyncReset with lib { ifu.io.ic <> io.ic ifu.io.iccm <> io.iccm ifu.io.exu_ifu.exu_bp <> exu.io.exu_bp - //ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r - //ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt <> dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt diff --git a/target/scala-2.12/classes/dec/csr_tlu.class b/target/scala-2.12/classes/dec/csr_tlu.class index 3e7a3ca3..ddf5a8d6 100644 Binary files a/target/scala-2.12/classes/dec/csr_tlu.class and b/target/scala-2.12/classes/dec/csr_tlu.class differ diff --git a/target/scala-2.12/classes/dec/dec_decode_csr_read.class b/target/scala-2.12/classes/dec/dec_decode_csr_read.class index 33499649..2e3650dd 100644 Binary files a/target/scala-2.12/classes/dec/dec_decode_csr_read.class and b/target/scala-2.12/classes/dec/dec_decode_csr_read.class differ diff --git a/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class b/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class index 204148ea..d09675f7 100644 Binary files a/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class and b/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class differ diff --git a/target/scala-2.12/classes/dec/dec_timer_ctl.class b/target/scala-2.12/classes/dec/dec_timer_ctl.class index d02dd6e8..ecdd9b45 100644 Binary files a/target/scala-2.12/classes/dec/dec_timer_ctl.class and b/target/scala-2.12/classes/dec/dec_timer_ctl.class differ diff --git a/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class b/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class index 92834fc0..813911d5 100644 Binary files a/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class and b/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class differ diff --git a/target/scala-2.12/classes/quasar.class b/target/scala-2.12/classes/quasar.class index b34b78aa..2867c5df 100644 Binary files a/target/scala-2.12/classes/quasar.class and b/target/scala-2.12/classes/quasar.class differ