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Clk enable removed from predictor

This commit is contained in:
waleed-lm 2020-10-07 09:52:47 +05:00
parent 90b3fa7b27
commit 15ad557ece
4 changed files with 6759 additions and 3608 deletions
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3072
el2_ifu_bp_ctl.fir
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7293
el2_ifu_bp_ctl.v
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2
src/main/scala/ifu/el2_ifu_bp_ctl.scala
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@ -393,7 +393,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W)))) val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W))))
for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){ for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
bht_bank_rd_data_out(i)((16*k)+j) := RegNext(bht_bank_wr_data(i)(k)(j), 0.U)//, bht_bank_sel(i)(k)(j)) bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j))
} }
bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i))) bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i)))

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target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
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